COMPUTER TECHNOLOGY

BACHELOR IN COMPUTER SCIENCE

Second PARTIAL EXAM TYPE A
May, 2021

SURNAME, NAME: GROUP:

Question 1 (2.5 points; 20 minutes)

Given the following circuit, complete the chronogram for the signals Q0, Q1 and D1, being M2_1 a 2
to 1 multiplexer and with CLR signal active with a one. (2.2 points)

Is it a Mealy or a Moore Machine? Explain Why (0.3 points)

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Computer Technology. Second Partial exam 1

 COMPUTER TECHNOLOGY
BACHELOR IN COMPUTER SCIENCE
Second PARTIAL EXAM TYPE A
May, 2021

SURNAME, NAME: GROUP:

Question 2 (2.5 points; 20 minutes)

Given the following state diagram:

a) implement an architecture of the system in VHDL. For the combinational part of the FSM,
implement only S1 and S2 states. (1.9 points)
b) How many Flip-flops are needed? (0.3 points)
c) What type of FSM is it? (0.3 points)

ARCHITECTURE problem2 OF exam2 IS

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Computer Technology. Second Partial exam 2

 COMPUTER TECHNOLOGY
BACHELOR IN COMPUTER SCIENCE
Second PARTIAL EXAM TYPE A
May, 2021

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Computer Technology. Second Partial exam 3

 COMPUTER TECHNOLOGY
BACHELOR IN COMPUTER SCIENCE
Second PARTIAL EXAM TYPE A
May, 2021

Question 3 (2.5 points; 20 minutes)

A well-known manufacturer assigns us the task of the design of the memory of a new microprocessor.
The requirements are the following:

- Word length: 32 bits

- Max capacity 64 K
- 32K of SRAM at the bottom of the memory (low positions).
- 16 K of EEPROM at the top of the memory (high positions).
- 8K of FLASH.
- The free space must be place between the SRAM and the FLASH memory

We have available the following memory chips:

- SRAM: 8Kx32 bits.

- EEPROM: 16Kx16 bits
- FLASH: 4Kx32 bits.
a) Determine the number of address lines and data lines of the system

b) Draw the memory map of the system

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Computer Technology. Second Partial exam 4

 COMPUTER TECHNOLOGY
BACHELOR IN COMPUTER SCIENCE
Second PARTIAL EXAM TYPE A
May, 2021

c) Indicate the initial and final address (in hexadecimal) of each module and the number of
address lines necessary for each module

d) Draw the schematic of the Chip Select (CS) control circuit for the system. Don’t forget to
indicate the modules of each CS line.

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Computer Technology. Second Partial exam 5

 COMPUTER TECHNOLOGY
BACHELOR IN COMPUTER SCIENCE
Second PARTIAL EXAM TYPE A
May, 2021

SURNAME, NAME: GROUP:

Question 4 (2.5 points; 40 minutes)

A consumer appliance company wants to implement an automatic popcorn cook function for its last
microwave oven model. The microwave oven has a start (I) and stop (P) buttons, a door sensor (D), a
humidity sensor (H) and a general purpose input (EoC). The system controls a signal that activates the
current through the magnetron (M) of the microwave oven and a signal that activates a beeper (B) to
indicate that the popcorn bag is totally cooked. In addition, the FSM needs to control a Timer
generating the enable signal (En). The required system functionality is the following:

1.- Initially the microwave oven is in standby mode, where the magnetron is disable (M = 0). If no
buttons are pressed it remains in this state.

2. The cook procedure starts from the standby when only the start button is pressed (I = 1) and the
door is closed (D = 0), the Magnetron signal is activated (M = 1) and the popcorn start to be cooked.

3. The popcorn bag starts to inflate and at some time the built pressure inside the bag will break the
seal releasing steam into the microwave chamber. In that moment, the humidity sensor is activated
(H=1) by the steam indicating that the popcorn is cooked and disabling the Magnetron (M = 0).

4. When the popcorn is cooked the beep signal is activated (B = 1) for 3 seconds. The company wants
you to reuse one of the timers that is implemented in the microwave oven control logic board which
VHDL code is given in figure 1. After the beep period the system returns to the initial state. The user
can cancel the beeps, returning to the standby mode, either by pressing the stop button (P = 1) or by
opening the door (D = 1).

5. If the stop button is pressed (P = 1) once or the user opens the door (D = 1) when the magnetron is
active the cooking is paused. During the pause the magnetron is disable. In this state, if the stop button
is pressed again the procedure will be cancel returning the microwave oven to the standby mode. If
the microwave oven is paused, the cook procedure can be resumed pressing the start button when
the door is closed (D = 0).

6. The activation of the start or stop buttons in any other situation not considered in the previous
statements is ignored.

7. If start and stop buttons are pressed at the same time, the stop button has priority when is
applicable.

a) Draw the state transition graph of the finite state machine (FSM) that implements this functionality.
The designed FSM must use the timer given in figure 1. Indicate clearly in the state transition graph
key which inputs and outputs are used from the VHDL code in the FSM.

HINT1: The beeper and the timer are active at the same time.

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Computer Technology. Second Partial exam 6

 COMPUTER TECHNOLOGY
BACHELOR IN COMPUTER SCIENCE
Second PARTIAL EXAM TYPE A
May, 2021

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;

ENTITY timer IS
PORT( clk, reset, en: IN std_logic;
eoc: OUT std_logic);
END timer;

ARCHITECTURE behavioral OF timer IS

SIGNAL k: INTEGER RANGE 0 TO 3;
BEGIN
eoc <= '1' WHEN k = 3 and en = '1' ELSE '0';
PROCESS(clk, reset)
BEGIN
IF reset = '0' then
k <= 0;
ELSIF clk'EVENT and clk = '1' THEN
IF en = '0' THEN
k <= 0;
ELSE
k <= k + 1;
END IF;
END IF;
END PROCESS;
END behavioral;

Figure 1. Timer VHDL code.

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Computer Technology. Second Partial exam 7

 COMPUTER TECHNOLOGY
BACHELOR IN COMPUTER SCIENCE
Second PARTIAL EXAM TYPE A
May, 2021

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Computer Technology. Second Partial exam 8