Ee ee Cia 2 DATA REPRESENTATIO ion/ Data Types 22 ation 2.2 Integer’ 2.3 Floa ng Pi VIE 24 Character Rep Standard for Floating Point Numbers on (Alphanumeric Code/ Ch 2. Computer Arithmetic 2.5.1 Binary Addition Binary Subtraction Binary Multiplication 4 Binary Division 2's Complement Arithmetic 2.6 Ad ers 6.1 Serial Adder 2 Parallel Adder 2. 2.1 Ripple C y Adder 2 Cascading Ripple Carry Adders 2.3 Carry Look Ahead Adder 2.6.2.4 4-Bit Carry Look 2 ad Adder 2.5 Cascading of Carry Look Ahead Adders 2,7 Binary Multiplication 2.7.1 Shift & Add Multiplication 2.7.2 Booth’s Algorithm 2.7.3Ca 2.8 Binary Division 'y Save Multiplication 281 Restoring Division Algorithm, 2.8.2 Non Restorin, 8 Division Algorithm 2.9 Floating Point Arithmetic 56JR DATA REPRESENTATION/ DATA TYPES om puter uses a fixed number of bits to represent a piece of data, which could be a number. 3 , or others. Integers, for example, can be represented in 8-bit, 16-bit, 32-bit or 64-bit the programmer, choose an appropriate bit-length for your integers. Your choice will constraint on the Fane of integers that can be represented. Besides the bit-length. an vacge 30 represented in various representation schemes, e.g., unsigned ys. signed integers. san it unsigned integer has a range of 0 to 255, while an 8-bit signed integer has a range of -128 Mn7-both representing 256 distinct numbers. you It is important to note that a computer memory location merely stores a binary pattern. It ssensrely up 19 YOU 88 the programmer, to decide on how these patterns are to be interpreted. For ple, the B-bit inary patter “0100 0001” can be interpreted as an unsigned integer 65. ot an ‘ascil character's, or some secret information known only to you. In other words, you have to fs deeide how 10 represent a piece of data in a binary pattem before the binary patterns make rene. The interpretation of binary pattem is called data representation or encoding. Furthermore. ‘a is important that the data representation schemes are agreed-upon by all the parties, ie. esosial standards need t0 be formulated and straight away followed ‘once you decided on the data representation scheme, certain constraints, in particular, the ‘sion and range will be imposed. Hence, it is important to understand dara representation to write correct and high-performance programs. + Allie operations ae divided into two categories: Arithmetic operations & logical operations Basic Arithmetic operations are * Addition © Subtraction Multiplication + Division + Basic logical operations are e AND ¢ OR * NOT Jo Perform arithmetic operation; It is important to know data types and their representation. ‘There are two basic data types |, Fixed point number system 2.Floating point number system The comparison between fixed point and floating-point number system is presented in Table 2.1.and Hlonting pant Number Syetem Table 2.1, Comparison between Fixed point WLOATING POINT NUMBEICNYV ET iy annem FIXED POINT NUMBEI SYSTEM 7 aC Tiere numbers are representod with only. | fry numbers fe Bad eh bony Integer part: Positive integer Negative Intoyer part ‘and fraetional pt Integer . Here radix point is fixed and assumed to | Flere rll va jo not Oy on $0ld ta be cor viel ‘be right of right most digit. joule uo cava poi umber Fram og ran pont mur sr ae) a i considered flouting point NTATION the radix point fixed after the tan integer, The commonl iden bit-lengths, there ar 2.2 INTEGER/ FIXED POINT NUMBER REPRESE smote numbers or fired? a pived number of DHS 42-bit or 64-bit, Hes pol numbers with Integers are w 1. Computers use d to represen! significant bit s are B-bil, 16-bit, bit-lengths for integer representation schemes for integers: 1. Unsigned Integers 2. Signed Integers 1. Unsigned Integers: The unsigned i 2 Signed Integers: The signed integers ean represent 76r point representation is shown in Fig. 2.1 ry can represent zero and positive integers 0, positive and negative integers, Fin ]‘phe fixed point number representation is broadly classified into two categories and discussed pelow: J) Representation of Unsigned Numbers 9) Representation of Signed Numbers JpRepresentation of Unsigned Number {Unsigned numbers contain only magnitude of the number. They don’t have any sign. That means al] unsigned binary numbers are positive. As in decimal number system, the placing of positive in front of the number is optional for representing positive numbers. Therefore, all positive qumbers including zero can be treated as unsigned numbers if positive sign is not assigned in front of the number. Range of number represented by unsigned number: An n-bit pattern can represent 2" distinct {ntegers. For 8 bit unsigned decimal number; range is specified as 0-255. Example 2.1. How many values of unsigned integers can be represented with 4 bits? solution : Range : O to 2**" 7 for m=4, Range : 2*4_1 j.e with 4 bits , values 0 to 15 can be represented as shown below: i Decimal Hex || Binary Decimal Hex 1111 4s io PROTPOMYAHEYNK Oo BERE Boe NaMeennosigned binary number imber 108 in unsigned binary jumbe ta a[ number is 1101100. This is the represen, lent of 108 decim Kanmple 2.2. Represent Solution: The binary equival yumber unsigned binary nun nee Rie tude of the number 108. esent the maga Inis having 7 bits, These 7 bits represent the mag is Example 2.3 fhe value signed jor: corres| ing to 8 bit binary py f integer correspond ‘Ke Fi e value of ple 2.3. Fin 01000001. 26 = 6510. Solution; The value of unsigned integer is 1*240 + 1% Example 2.4. Find the value of unsigned integer corresponding to 16 bit binary patter, ‘0000 0000 1000 B00). Solution: The value of this unsigned integer is Bx2*3 + 1%2°7 = 21610, 2) Representation of Signed Number The Most Significant Bit MSb of signed binary numbers is u ummbers, Hence, iti also called as signed bit, The positive sign is represented by placing *0* in the sign bit. Similarly, the negative sign is repre If the signed binary number contains ‘N’ bits, then NI bits represent the magnitude of the Sumber and leftmost one biti. MSb is reserved for representing sign of the number. There ar three types of representations for signed b id to indicate the sign of the ented by placing *1” in the sign bit. A. Signed-Magnitude Representation 4. 1's complement Representation ©. 2's complement Representation Alll three representations rema) femain same for a positive : e negative number differs in each form Positive number, But, the representation of negative AL Signed-Magnitude Representation In signed magnitude representation; Called as signed bit, Usually signed shows the Fepresentation of 8 bit sig the first bit js dedicated to represent the sign and hence it is ns ion i: ae ° + ined me Presentation is done in form of 8 bits. Fig. 22Ja signed magnitude representation of an & bit number, the leftmost bit (D7) will represent sign as ghown in Fig, 2.3 and rest (D6-D0) bits represent magnitude of number D7 (Sign bit) > ‘1° represents negative sign, 2 D7 (Sign bit) 0" represents positive sign, « DO-D6 (Magnitude bits) > Represents magnitude of number Left most bit D7 If D7=1 ----> Indicates number is _ If D7=1----> Indicates number _ist+ve Figure 2.3. Indication of D7 Bit in ; Signed Magnitude Representation The Range of number represented by signed magnitude representation method for n bit amber is-(2°'-1) to+ 10 +127 '-1), For example: For 8 bit Decimal numbers: specified range is -127 © Limitation: There is one problem in signed magnitude representation as we have two representations of 0 as shown in Fig, 2.4 % For example 0 can be +0 and -0. The +0 is represented as 00000000 as D7 bit is 0 to indicate +ve sign and D6-D0 bits are 0000000 to represent magnitude. Whereas -0 is represented as 10000000 85 D7 bitis | to indicate -ve sign and D6-D0 bits are 0000000 to represent magnitude SZzeUGEE DS (oa... ps 02 51. pe, sign k=—————_ magnitude —————_ >] be bz ae a “ eters cial ae Figure 2.4, Representation of Zero aombeana es ie tion: signed magnitude representation method is good bu ‘oF -ve integer representation: Sig 3 2 ‘computation / arithmetic can’t be performed as it may lead to wrong results: i $s 10011000. The arithme z and -24 is represented asl Metie FOR EXAMPLE: +16 is represented 2s 00010000 pute; it comes out 40 aS per signey operation (+16-24) should provide result -8 but when we com| magnitude representation:- +16 300010000 -24 310011000 10101000 > WRONG RESULT Therefore we use I’s complement and 2’s complement representation. The biggest advantage 2's complement is same representation of +0 and -0 as shown in Fig. 2.5 1's complement method +0 > 0000 0000 > ee 8 2's Complement method wD 0000 0000 -0 aa 0000 0000's complement of 0 is 0) Discard carry Figure 2.5. Representation of +0 and -0 by 1's and 2"s complement method ‘The Table 2.2 shows signed magnitude representation of numbers 0 to Ze7 Table 2.2. si ble 2.2. Signed Magnitude Representation pe _[wonoo aS i 10000001 2 0000010, LE EIR. | 4128 oniior =| as | srittiiot +126 _ onto ae Hi11110 Har oui “a7 niin Example 2.5. Represent 425 and -25 using signed magnitude representation method Solution: 011001 Where 11001 = 25 And MSb is 0 to represent it “+ve 111001 Where 11001 = 25 And MSb is 1 to represent it *-ve" Example 2.6. Represent +8, +27, +64 using signed magnitude representation method. Solution: +8 = 00001000 +27 = 00011011 -64 = 11000000 ed magnitude representation method. Example 2.7. Represent -108 using The magnitude of this number is 108. Solution: Consider the negative decimal number -108 having 7 bits. All these bits We know the unsigned binary representation of 108 is 1101100. It is represent the magnitude. laced on left most side Since the given number is negative, consider the sign bit as one, which is pl of magnitude. Hence ~10810 = 111011002 ‘Therefore, the sign-magnitude representation of -108 is 11101100. of 8 bits as Example 2.8. The signed number representation is given in the form (01000001). Find the integer value. = It indicates number is positive Solution: As Signed bit D7 is ‘The 7 bit magnitude value is (100 0001)2 = (65)10 Hence, the integer is +65BW Os and all 0's to 1's. Fis: 26 ement of Mable 2.3 represents 1°s comp 1’s complement of 108 or represent -108 in 1's complement form. Solution: Consider the negative decimal number -108, The magnitude of th We know the signed binary representation of 108 is 01 101100. It is having 8 bits. ‘The MS this number is zero, which indicates positive number. The I's complement of a numbers ® by changing all 1's to 0's and all O's to I's in order to get the negative number. In this 4 obtain ~108;9 = 1001001 12 Example 2.9. Find jis number is \\plement of (108) 15 i, (1001091 Vp Beet O27 i 1s complemen form 1000 27= 00011914 = 1110111 (1's complement) -27=11100100(1's complement) “Complement each bit in representation of +1=11110 Hence -1= 11110, 2.12. Find out the decimal value of g: Complement each bit in given binary inary sequence 11109 Sequence 00011 indie, in one’s complement form. ates it +3, ment representation can be find out by adding 1 to 1's complement of number, Therefore 2's Vs complement + 1. Fig. 2.7 shows the way of finding 2°s complement. Table 2.4 's complement of numbers in the range 0 to 1274.2°s Complement Rel Ott 10 ont Example 21 Solution: Representation of +5 = 00101 1°s complement of 15 11010 | 2's complement of +S oll Je 25 wang 278 0o™ jement 5, Find 2's comple tof (8)100F represent 8 usit e Example 2 representation. Solution : Represe! 1°s complement of 2's complement oF ( 6, What decimal must be a negative num and then add 1 t0 2 (00001000)2 (ui1101 ie qa 1000)2 e two the most sig nal number sntation of (8) (8)10 8)10 J value does tht nber, sim et OFF ment 110011 represent? 1. We can find the 1 Example 2.1 Solution: It complement of 110011 01100 (The 1's complement of given number) Ewa) vn number representing +13) oor 104 (The 2's complement of give! therefore, (110011) must be -13- 17, Represent the negative decimal number -108 using 2” complement ion of (108)10 = (01101 100)2 108),0 = (10010011) = 1’s complement of (108)10 + 1 Example 2. Solution: Representati 1's complement of ( 2° complement of (108)i 10010011 (The 1’s complement of 108) +1 10010100 Th werefore, the 2’s complement of (108)i0 is 100101002. 66very large integers & ve adjusted as computation proceeds ‘Therein Rie led floating point numbers, iene jint representation has three fields: «Sign bit Significant digit/ mantissa Exponent A computer must be able to of binary point is variable and IY point is said to be float and 2.18. Consider the number fi tolttol-[1 O/0\0 number in floating point format 1{o] it is shifted to right of first bit and number is multiplied by correct sealing factor to get . After the step 1; the number is said to be in normalized form, E it Jee String of Significant digits (Mantissa) Scaling Factor (Base in scaling factor is 2) 1 ‘ANDARD FOR FLOATING POINT NUMBERS ‘epresenting floating point number is 32 bits and 64 bits developed by IEEE nd Electronics Engineers) called as IEEE 754 standards as shown in Fig.Double Precision entation EEE 754 Standards Figure 2.8. 1 stem) on representation because it Joating Point S led a single precis ion representation '5 ° a. Single Precision Representation (32 Bit F y The 32 bit standard representation is ca eccuries a single 32 bit word. 32 bit single precis 32 bit word is divided into three fields:- i ) is the si i. The most significant bit Gt numbers. 5 is one pit representing the sign hown in Fig. 2.9. Th an bit (5), with 0 for positive numbers and 1 for negative of the number is an 8-bit biased present exponent (E') Ti cess 127 exponent. Size of exponent fei m that can be represented. E’ = E (Scalin presentation of exponent is al ii, The next 8 bits (30-23) r integer representing the determines the range of valu Factor) +Bias. As Bias = 127. S0 this re} called as Excess 127 format. a (M). M is an unsigne nificand bit 2-0) represents Mant ficand, Size of Ma ¢ representation. iii, The remaining 23 bits (2 integer’ Mantissa/ Signi determines the precision of th — Bits —$—$—$—$—$$—$—$>| Sd e130: aanee, 0 Sign 8 Bits Excess 127 23 Bits Mantissa Exponent Figure 2.9, 32 bit Single Precision Representationd into three fields: presentation is shown in Fig. 2.10. The 64 j, The most significant bit (63) isthe sig n bit (S i fumbers and 1 for negative number (S), with 0 for positive 8. ii, The pet eonsecatiye 11 bits (62-52) represent excess 1023 exponent (G). E’ = E (Scaling Factor) +Bias. As Bias = 1023, $o this representation of exponent is also called as Excess 1023 format, The remaining 52 bits (51-0) represent Mantissa (M), 11 Bits Excess 1023 52 Bits Mantissa Exponent Figure 2.10. 64 bit Double Precision Representationjsio™ jer (1259.125)i0 into the IEEE single pre“ decimal numb: Humber in Binary format. [tc ‘and fractional decimal va Bametinds The decimal to binary conversion ented to bind J to binary 1 decimal er decimal value is ¢ after decimal is converte for the give {o.225):0- (0-002) (2259-125) 1011-001)2 (20011129 1 to Binary Conversion for decimal number (1259.125)10 g the radix point 10 Po ‘after the most significa sitions ahead from the nt bit as shown in F Figure 2.11. Decimal ber by floatin .d now it is just ize the binary num — Normali ying ani where itis currently I step 2: Normal! zation of Binary Number 1011.001 of Binary Number 10011101need to be done er ase done fr representation, Sis representing iv gn bit will be zero, Exponent is identified as 10; as } ined 10 postion ahead wherefrom it was currently lying. Mantissa is representing | eaats after radix point. So Mantisa identified i 0011101011001. Excess 127 ane ind Out by adding 127 to identified exponent. In this way excess 127 exponent is ipary sare of 197 15 ae lated by repeated division by 2 method. Identification step of min Fig. 2.13. Step 3 : Identifying S, E, M and E" s=0 —=10 M = 0011101011001 E' =E +127 = 10 + 127 = (137)10 (137)10 = (10001001), E' = 10001001 Figure 2.13. Identification of S, E, Mand E?is shown in Fig. 2.14 Step 4 ~ Single Precision Format Representation is shown in Fig Step 4 : Single Precision Format Representation 00111010110010000000000 Ss E' Mantissa Figure 2.14, Single Precision Format Representation Example 2.20, Represent the decimal number (1259.125)iainto the IEEE Double precision format, Step 1 = Convert given decimal number in binary format as shown in Fig, 2.15 Step 1: Decimal to Binary Conversion (0.125):0-(0.001)2 (1259.125):0 (210011101011.001).> a lize the binary number as shown in Fig, 2.16 Normal et? step 2 : Normalization of Binary Number 0 1.0011101011001 x 210 Figure 2.16. Normalization of Binary Number 10011101011,001 ation of S, E, M and E" is shown in Fig, 2.17, Step 3 : Identifying S, E, Mand E' s=0 M = 0011101011001 E' = E + 1023 = 10 + 1023 = (1033):10 jentifict op} Went Figure 2.17. Identification of S, E, Mand E” BStep 4 Double precision format representation is shown in Fig. 2.18 Step 4 ; Double Pracision Format Representation 63 6 5251 0 011101011001000000000 0 S E Mantissa Figure 2.18. Double Precision Format Representation Example 2.21. Represent the decimal number (-307.1875)10 into the IEEE single precision format. Step 1 - Convert given decimal number (-307.1875)i0 in binary format as shown in Fig. 2.19. Step 1: Decimal to Binary Conversion 0.1875 x2 0).3750 (0.1875)10 = (0.0011). (307.1875):0 (307)10 = (100110011), (100110011.0011), Figure 2.19. Decimal to Binary Conversion for decimal number (307. 1875)i0 1%|= Normalize the binary number as shown in Fig. 220, Step 2 : Normalization of Binary Number 1,0110011,0011 v 1.0011001100 x 28 Figure 2.20. Normalization of Binary Number 100110011,0011 3 — Identification of S. E, M and E” is shown in Fig. 2.21, j Step 3 : Identifying S, E, M and E’ S=1 E=8 M = 0011001100 E'=E+127 = 8+127 =(135):0 (135)10 = (10000111)2 £' = 10000111 Figure 2,21, Identification of S, E, Mand EStep 4 - Sit Example 2.22. Represent the decimal number (-307.1875, format. Figure 2.22. Single Precision Format Representation igure 2.22 Step 1 Conver given decimal number (307.1875) in binary format as shown in Fig, 2.2, Step 1: Decimal to Binary Conversion 0.1875 x2 | 0).3750 x2 0).7500 x2 1).5000 x2 | | | 1). _ (0.1875):0 = (0.0011) (307.1875):0 3 (307)10 = (100110011), {100110011.0011). )w into the IEEE Double precision2- Normalize the binary number as shown in Fig 2.24 Step 2: Normalization of Binary Number 1,.Q0110011,0011 v 1.0011001100 x 2® Figure 2.24. Normalization of Binary Number 100110011.0011 ‘Step 3 Identification of S, B, M and E? is shown in Fig, 2.25 Step 3 : Identifying s, E, M and E S=aq,b=3 M = 0011001100 E+ 1023 = 8+1023 = (1031)10 Figure 2.25. Identification of S, E, Mand E”sation i Step 4 ~ Double precision format repr Step 4 : Double Precision Format Representation 32 51 62 001100110000 0000000000 - - Figure 2.26, Double Precision Format Representation Example 2.23, Represent the decimal number (-0.7: Step | ~Convert given decimal number (0.75) i into the IELE. Sin Step 1: Decimal to Binary Conversion i Figure 2.27. Decimal to Binary Conversion for decimal number (0.75), Step 2— Normalize the binary number as shown in F Step2:. ' sop 3 Hentitication of S,E, M and Fis shown in Fig, 2.29 Step 3 : Identifying S, E, M and E" E= M=1 E'=E+127 = -1 +127 =(126)10 (126)10 = (1111110) E'= 1111110 Figure 2.29. Identification of S, E, M and B* Step 4 — Single precision format representation is shown in Fig. 2.30. Step 4 : Single Precision Format Representation 10000000000000000000000 5 [= Mantissa Figure 2.30. Single Precision Format Representationini ial se ch oi he, they Were arlior ¢ pullers Were used only for purpose of en iad Dine By How a day's computers are not just me for a . oy ma (re also used to tepresent Information such ag names, ea e ol or. ms ‘formation is represented Using letters and symbols, Computer is : ihe an deal with Py and O's, So to deal with letters and symbols, they use alpha erie g i 0 Processable by a Codes Write alphanumeric data in a form that is understandable and Processable by a including: Used * Letters of alphabet * Numbers . Mathematical symbols * Ponetuation marks Punctuation Marks are symbols that are used to aid the clarity and comprehension of language, Some Sommon punctuation marks are; ~ Period, Comma, 2, | Apostrophes, q mark, hyphen, Using alphanumeric codes, we can interface input Output devices Keyboards, Monitors, printers ele, with computer, Several coding techni hepresent Alphanumeric Information as a Series of O's and I's, . first alphanumeric code | telecommunication Wis Morse code invented in 1837, Due to variable length of Mors characters, Morse Code could not Adapt (0 automated circuits, T) Codey are). NAscn Code iques were invei he two most Popular ch; 20 HODIC Code ') American Standard ¢ ‘ode for Information Interchange (ASCID), It is Pronounced ay ASKER, Wis 07 bit code Used to rey Computer input Output, The 7 bit code represents 128 (27) charact obsolete characters and 96 printable characters, The 32 non Printable characters are use indicate certain formatting Actions such as white space, Carriage Return, Tabs, Line break, F break and Line feed, The ASCy| Table with 7 bit code (XOXSX4x3x2x10), Containing Printable Characters Is shown in Table 2.5. Present alphanumeric da ers. including 32 non prinAble ANCHE Hable a LL TT TT TTT ON | 00 10 40 MtExample 2.24, Represent ASCH ¢ Solution: ey 7] oOfo;ofo/oj1] 1 by Represent “A' in AS Examples Solution: 100 0001 is 41 (he) or 65 (decimal). It represents °A\ Examples Represent “B' in ASCII code, ents °B' Solution: 100 0010 is 42 (hex) or 66 (decimal). It repr 2) Extended Binary Coded Decimal Interchanging Code (EBCDIQ) It is designed by IBM CORPORATION specifically for mainframe computers. It is frequently used code by computer for transferring alphanumeric data, : So it can represent 256 (2°) different characters. ily grouped in to group of 4 bits so as to represent > Itisan 8 bit cod > Since it is an 8 bit code, so it can be in terms of hexadecimal digits. By using hexadecimal number system notation; amount of and special characters using EBCDIC Code is digits used to represent various characte! reduced in volume of one is to four. In this way 8 bit binary code could be reduced to 2 hexadecimal digits which are easier to decode if we want to view internal representation in memory. The differences between ASCII and EBCDIC are shown in Table 2.6.‘Table 2.6. Differences between ASCH & EBCDIC | pool EBCDIC | [ ; [ 7 Bit Code ‘BBCode Represent 128 characters Represents 256 characters ‘Used on Microcomputers Used on IBM’s Mainframe Computers ‘One zero need to be inserted to ‘ Easily grouped into hexadecimal form for E represent it in compact hexadecimal : compact representation form j . 25 COMPUTER ARITHMETIC ‘Arithmetic means operations like addition, subtraction, multiplication and division. Arithmetic | applied on decimal numbers is called as decimal arithmetic. If such operations are performed on binary numbers, then arithmetic is called binary arithmetic. The binary Arithmetic can be further divided into four subcategories as shown in F 31 Figure 2.31. Binary Arithmeticwe need to consider the two binary numbers A ang mber which is to be ; ~ While doing the binary addition, is i JEND & nut i /-d number is added is called as AUG! Number in which 2™ num! n of these two numbers, y AUGEND is called as Addend. We can perform the addition similar to the addition of two unsigned binary numbers. : . In binary, Augend & Addend can have 4 combinations. The rules of binary addition are in Table 2.7. Table 2.7. Rules of binary addition ) of 1°s in a column produces Summation = 0 ) of 1°s ina column produces Summation = 1ee gxample 2.27. Perform the binary addition of numbers 1011 and 1100. solution: gxample 2.28. Perform the binary addition of numbers 0101 and 1111 Solution: Example 2.29. Perform the binary addition of numbers 01101010, 0001000, 10000001 and qiti111. Solution: 1 1111111 01101010 00001000 + 10000001 11111111 1111100102A, 2 WINAKY SUBTRACTION nsider the two binary num| * White 4 ction, we need 10 60 ny the binary subtrn s ' is called as Minuend & numbc ‘ 1, The number from whieh subtraction lake place be subtracted is cal yinrahend mbinations, The rules of b > In Winary, Minwend & Subsrahend can have 4 ¢ b hown in Table 2.8 Fable 2.8, Rules of Binary Subtraction | Bubirahend | Difference | Borrow 4 ee [_—t — | o 1 0 bees? | {—_—_ Fxample 2.30, Subtract 0110 from 1011 using binary subtraction method numbers fa fof1}1ju | Number 2 Bei) 2] 0 | 6 Solution Borrow ied | Difference} While doing the binary multiplication, we need to consider the two binary numbers A and B. ‘The number in which 2" number is multiptied is called ax multiplicand & number which is to bbe multiplied is called multiplier. Binary Multiplication is similar to decimal multiplication. p Inbinary, Multiplicand & Mukiplier can have 4 combinations. The rules of binary multiplication are shown in Table 2.9. Table 2.9. Rules for Binary Multiplication1011 partial Product 1 0000x partial Product 2 1011XX —— 55 110111 —= sample 28, Perfrm binary maipction of mambers 104101 and L111 Sotuton 45 = 101101 63 = 111111 101101 101101X 101101XX 101101XXX 101101XXXX 101101XXXXX oduct 3 Number 1 Partial Product 1 Partial Product 2 Partial Product 3 Partial Product 4 Partial Product 5 Partial Product 6 Partial ample 234. Divide 10101 by 1001 wingerenenonion wwitie at the Heiaey Hiv inti, ve anuider the nwo binwry ouenbers A ane Ay The yh whet Ia dn Jidond and number by whieh dividend} rei ened lan 292 sow Bivvy ier Remnlaan i Quan ivinary Division 3 O0001101 4 Quotiont pivior ——w 1011] 1001001 1 to Dividend 1011 001110 Partial =» ” remainders 1011 * oottt 1011 1004 Remainder Viguve 2,42, Binary Division Yonnple 2.34 Divide 1110101 by 1001 using Minnry ivision polution Dividend 1110101 (1101 Sa Quotient 1004 01014 1004 01001 1001 Remainder 0000 Divisor@>1 004Rules for Subtraction by 2 below: 2s COMPLEMENT ARITHMETIC erformed by digital circuit (ha > Binary Arithmetic is basically Ps i ss well bi ition as we cuit for binary ad utilize same digital circuit for binary °° : ; enient and cheaper ; more conv e & circuit des ~ mor n wil ithmetic. P' additional hardwar 2's Complement Ar method used for this purpose #6 called as simply represented as simple Pinay repr . : ine binary numbers A & B. represented using 2° complement. Conside subtracted, We know that number 4 whenever we have to subtract @ number B fro A. then tak i iit to A. So, mathematically we ean WTS ss q A-BeA So, the subtraction of two signed binary en | binary numbers, But, we have to take 2's comps b subtracted. This is the adva same rules of addition of two binary numbers & cs *s Complement Method: The algorithm to subtract two binary number usi ¢ Take 2’s complement of the subtrahend, «Add 2's complement of the subtrahend with minuend. Ifthe result of above addition has carry bit 1, then it is dropped and this result will be positive number. tive. The ‘© If there is no carry, then take 2s complement of the result which will be ne tales fe ion by 2° for subtraction by 2"s complement method are divided into four cases as shown in Fig, 2.i Zs Complement Method lf Minuend & Subtrahend are of Same Sig Minuend & Subtrahend Then answers treated as Negative and Hence 2's Complement of Answer is taken to get Correct Result Resultis Correct andisin 'sComplement Form, Carryislgored Figure 2.33. Rules for Subtraction by 2’s Complement Method Example 2.35. Perform subtraction on the following numbers using 2’s complement method. a) (+48) — (+23) | __b) (+23) - (+48) ©) (-23) + (-48) d) (-48) + (-23) onSS 10110000 a] 48 > 00110000 ' 2 10001 Z| 23 p> ovotott oo = 1) 00011001 25 Ignore J vest is Correct carry &wve 2] 23 > 00010111 = 00010111 4a a =] 48 > 00110000 == 11010000 EE No Carry indicates Result is-ve Correct Result 100111 SS 00121001 (-25) 23 > coon 48 > 001100003, When both the numbers are negative numbers/ when both the operands are cas ame : ; $ ent method, Then the Sign bit of result (MSB) is compared with sign bits of both (Minuend & Subtrahend), If S sign, Perform the Addition of two decimal numbers (23) + (48) using eae ands gn bit are same for Result, Minuend & Subtrahend. It op gpcans cult is correct and is in 2°s complement form as shown below 23 > 00010111 I [ih101001 + 48 => 00110000 === [010000 Result Ignore yy 1) @o111001 ee Carry 01000111 Result (-71) CASE 4.When both the numbers are negative numbers, Perform the Addition of two decimal n bit of result is not own below, If numbers (-112) + (-80) using 2°s complement method as s s. It means there is a problem of overflow ie result same with the sign bit of both the operand: sult is to be interpreted suitably, The result in this case can’t be accommodated using 8 bits and r of 9 bits, Instead of MSB giving sign, CY is indicating sign and rest 8 bits indicate cons magnitude, It is because if we add two ve numbers then how can the result be ve.Sign Bit =1 Result is -ve 11000000 Result (-192) 2.6 ADDERS In computer arithmetic hardware, adders play an important role because all arithmetic operations can be performed with the help of addition. For example: Subtraction can be performed usin, complement method based on addition; multiplication can be performed by repeated addition method; division can be performed by repeated subtraction method and subtraction can ultimately be performed using addition. Adders are of two types: 1) Serial Adder 2) Parallel Adder 2.6.1 SERIAL ADDER Serial adder is based on principle of two n bit numbers by serial bit by bit addition, Let Ai and Bi, are two n bit numbers which need to be added. For the addition of these two n bit numbers, only one full adder is employed in the system along with one D flip-flop as shown in Fig.2.34. Here the operands, Ai and Bi, they are supplied sequentially bit by bit, starting with the least significant bit ‘The Full adder generates sum and carry as output. So sum for i'® stage is denoted as Si and the carry from same stage that is provided as input to the D flip-flop. So carry produced by 94Figure 2.4. Serial Adder bit position through the full adder is remembered by this D flip-flop because D flip idered as one bit memory. Then D flip-flop passes that particular carry as input during a particular flop is consi tne next clock cycle forthe addition of next bits; those are present atthe next consecutive position. qin this way: addition of one bit position takes place with one clock cycle and total w clock cycles are required to complete the addition process of n bits. This is the basic working principle ‘of Serial adder. To understand how serial adder works: we take one example. Let's say, Ai and Bi both are containing total four bits each, Let's say Ai is 1000 and Bi is TILT. So first of all, we are putting east significant bits of Ai and Bi i.e O and I respectively to the fll adder. Them full adder adds the wo bits present at the least significant bit position and generates sum as 1 and carry as 0; then ‘ary is passed to D flip-flop. The D flip-flop is the transparent flip-flop and also called as the Delay Mip-flop. D flip-flop passes the 0 input at its output terminal after one clock pulse, In this yay total delay produced here is the one elock pulse. So after one clock pulse; the 0 carry bit is jssed to the full adder when the next consecutive bits 0 and | are supplied. This process keeps on repeating till the most significant bits are supplied to full adder for addition. After addition of the ‘most significant bits with the carry from the previous stage: the final sum and carry are obtained. MERITS: > The circuit for serial adder is small & hence it is very cheap imespective of number of bits to be added. As only one full adder and one D flip-flop is required. So obviously, if cireuit is very %al because e8PECIVE OF Mu ait ix elven eS J one D Hiptlop Is required, full wader and : tv eral der LIKE Fs 90y UF wg jg 6 en al sip call vr, ington hut rw eh ats me he w Taretoarre fe rit dependent Se? atx A and fhe unter of Wits fn the members A onl (114, then also we 1 we! 1 employ Only one fy andl ane 2 Mipstap. DEMERETS for completing mldon of bi may © ‘The sorial adkdar is slo ooy since tt takes 1 lock cycle The parallel adder performs the ad bit positions simultaneously. In th i null bit j fi difition is dene bit by bi e witions, as only a single full adder is emp} bit posith aby tn the parallel adder multiple full adders are employed in parallel depending up, 4 system. In the paraltel add numer of bite that we need to add, In this way the simuitwnoously. Therefore addition of two n bit numbers is performed by employing n sepa, akan fo addition of multi bits positions take py. auidorn Parallel adders differ in the way the carry bits are generated and based on the intern ‘addition mechanism; we can have two types of parallel adder: 1. Ripple cary adder 2. Carry look ~ abend adder 2.62.1 RIPPLE CARRY ADDER (0-bit) The block diagram of n-bit Ripple Carry Adder is shown in F In the n-bit Ripple Ca ‘Adder. total n full adders are employed in the system and they are connected in cascaded mode, 4 nd B are the two n-bit numbers, The number A is containing n bits from AO, Al to Ant ‘Similarly, the number B is also containing n bits from BO to Bn-1, An-I and the Bn-1 are the most Significant bits of number A and B respectively and the AO and BO are the least significant bits of number A and 1) respectively. The n full adders are shown with stage 0 to stage n-1. The initial carry Cin to the stage 0 is provided with the value zero because initially there is no carry and this full adder is generating the sum S0 and the Carry CO, So carry out from stage 0 is acting as the amy input of the next consecutive stage 1, Then the carry output of stage 1 is acting as the camry ‘Input of next consecutive stage 2 and so on. So in this way, cach stage performs the addition on the two bits by taking into account the carry from the previous bits position and %6 each stage addersoe a EE CS RE CY 5 als tae re cemesere singe aal sa ck ssc fe aes Oe ae Se Tl ly sls i cs cig cme ae ape sc my A gl i tra ci Sag tame: fever. fe carp alti © wimtivete ete tr wenIrS > Taenpeie care adifer is fewer then he sexe aie opie care adiier is comsaderet Se sow femme each hil aitier than mest wort Ge he ox ww Se colonia Some fe peevious Gil adhe So that's whe & S cemime the dees oe he This deta is called as the coms propaumiom dee. I af is the time dees fhe omit aii ant wed hese we he 2 fil adifes copieved @ he swsem Gr he wider of 2 es mecmum propuasion debs the the o bit Ripple Cary Adder & 2 Ges we A my 2 (Si tee we ompaese derouet al de suse aes. Ete mst of mem = then time miter Som cary we propeeme thom LSb a MSb sue is moe This s ken 2s ar ombiem. The didiereness Senveet seal adiier amé Sppie Ge aie re rene 2een Serial Adder and Ripple Carry Adder Differences betw Table 2.10. RIPPLE CARRY ADDER ue to a single S148° adder Delay di No Flip-flop means no Propagation delay | ta ps ce Minimum time needed by ripple | stages of carry adder = 21d addition | | | It proves that ripple carry js faster than serial adder. RIPPLE CARRY ADDERS an construct adder of any speci 2.62.2 CASCADING fic length. For example: Ty adder as shown in Fig. 236 dder is 2n. In the cascaded ripple carry adder ith n bit each. In this way t By cascading ripple carry adders, we ¢ mbit adders of ripple carry adder can be case ‘Therefore Word length of cascaded ripple camy both the modules simultaneously perform addition on two numbers Wi allows the carry propagation from one module to the next module so that the final carry C mis generated and final sum (S 20-1---.S0) is generated here. S 2»-1 is considered as most significant bit of sum and So is considered as least significant bit of sum. aded to construct 2n-bitSind sn Figure 2.36, Cascading Ripple Carry Adders By cascading WYO modules of 4 —bit ripple carry adders, we can construct adder of 8+ bit length as show? | proagati ; ‘Gn is the initial input carry provided to the ripple carry adder. The 4-bit ripple camry adkler is gading the four I sam andthe intermediate carry C3, The earry C3 is forwarded in Fig. 2.37. Both the modules simultaneously perform addition and then allow the carry n from one module to next module, In the cascading of two four bit ripple carry adders; least significant bits of A and B and generating the four least significant bits of nput to next 4-bit ripple carry aader and this is further adding the most significant four bits of A and B. The 4-bit ripple carry ‘adder generates the four most significant bits for the summation and the one bit as final carry. In tisway we ean easily increase the word length of ripple carry adder by the cascading, AGASAGA7 4.85.86 B7 AO ALAZAS. 081.82 83, 4-Blts Ripple Carry Adder ca 48h Ripple Carry Addor 3 eed 36 7 Ss st se 33 Figure 2.37. 8- bit Parallel Adder using 4 bit Ripple Carry Adder 992.6.2.3 CARRY LOOK AHEAD ADDER rey. propegaifon Proplers: 1 HT speed. AS and carry until fo it ean no Ripple carry adder suffers with the ¢ 1 yenerate 4 module waits for carry to arrive from previous module: S sel 1 feads to the delay in srry propagation problem 1s moxtule, Therefore & : rere may be the different type it obtain carry from previ jon delay, Th the performance. That delay is called as carry propa m and one of of logic approaches that can be emplayed to overcome the ead Adder (CLA). The ook Ah ploying the Carry L0 follows gy for the quick carry of the prev and that is saving the time in the carry propagation probler Carry Look Ahead at is by em such solution 1 ‘a special strate} fous stage. In this ease, carry Adder is considered as high speed adder, whlch for the carrie’ input signal The cell repres 8, at cach stage without waiting ice based on the giver generation sentation or the block signal is calculated in adv addition. This is the biggest advantage oF this method. ad adder is shown in Fig: 2-3) diagram of n-bit carry look 3 Carry Look Ahead adder Cn Sn ry Look Ahead Adder Figure 2.38, Block Diagram of C ‘The nebit carry look ahead adder is based on the (wo inputs A and B. A and B are two nit umbers. The third input to cary Jook ahead adder is the carry from the previous positon. Hen if we add the nth bits of A and B, then the carry is taken from nel stage. Henceforth carry look ahead adder works on three inputs An, Bn and Cn-l, The carry look ahead adder generates the two 100 inthe t The cat inputs input © previo propag whethi noth. : . Sgomponentss Gn and Pr. Gn and Pa are called as cany Benerate component and the carry P propasete Component respectively, The final sum is denoted as Sn : and the final carry is denoted as (m The truth table of carry Took ahead adder is shown in Table 2.1 1 Table 2.11. Truth Table of Carry Look Ahead Adder In the truth table of full adder, An. Bn and Cn-1 are three inputs and Sn and Cn are two outputs. The carry is produced corresponding to four input combinations. In the last two combinations of Jnput; the carry is produced when both An and the Bn are one. So we can take one condition for uhe generation of carry as “If both An and Bn are one, then the Carry is one.” In the rest of the two inpat combinations if either of the two An or Bn is one, then we need to check the carry from the ion. So if either of two An or Bn is one, then the previous carry Cn-1 gets opagated to the next stage as carry. There! fore total two factors are responsible for deciding ther there should be a carry bit or not. One is called as the Carry generation component and nother is called as the carry propagation component. carry is generated under the condition if both An and Bn are one. The condition of carry eration is defined as An* Bn. If An and Bn are one; then AnBn becomes one and in this way En becomes one. So this is one of the condition under which we can say Cn is one if both An and Bn are one, So Gn is one. This condition is called us Carry generation component Gn and Gn is ifboth An and Bn are one. In the second condition: if either of the two inputs An or Bn is one 101one, Se wn te Cn I shen Y pmo joua Mays Cred, i alee ane we, Hen Pn le ane. The ee " an on Hi ly rine, Hien PA Mition ore word Hn. F0 185 WD PO IS on yng wid Vie earTy (OR fit the eonlition tat WE either An OW Hin I alea Pn ie ane, Pa Romper PRM pOHIEHt h ariy prepagetion be detined n pent V6 walled Ws the warty py, came avd he Wn ie gern, then Pheretiove Cn is one if cy i Wf eomnpunent and HFA ie ane, sen tne Cine l be preypayaled 1 EP vor nt An or Bn should be one, BO ¥e Cun say 5, Avr wt the goin Have, anvanier condition Vo it hk ion if both An and Bn uenoriie a carry lprespaetive af earry Une! trom previews position IF hoth An and Fin ae 1) lake care about Enel; Cn wi jot thve wanidien AF ay An and Hin arene’ shen ne need fo take ear be pr fin 1 one, 80 these are sid the vevond condition tei aye n propayates Enel JEAN or Hin he Iyg i called ne the eMPFY Benerate COmPORer wonlivione that tend (a the erry weneration, One I saunter tn called aa carry propagate eompenent ion of carry input LO A staLe, Withow The eary lovk nhiead udder invalven enrly determinat atye, by direetly determining earry like signals duoliy enery wutjnal fram previews vot that.» eanry signal Will be generated in two eases © Wie bwwed on the fi 1) When bath bite Anand Hn are 1, AF +) When one of the two bite (either An or Bn is 1) and the Cnet (earry of the previous Aaya) ie 1 Here ave to taetures wdieh decide whether here should bed earey bitor not, 1, CAHHY GENERATION COMPONENT (Gn); Stage 1 generates a carry irrespective of the earty COA AE AR AND Hn lit h The Hint faetor depends on the data bits of the current stage ie. Cnn tin 2, CATHY FHOPAGATION COMPONENT (Fn): Stage 0 propagates Crt, if An or Bn is | Fhe seeond tetar depends on both! (he datw bit pullerns OF current stage & Carry from previous ie Pie An MOU Mn Henee entry exprewnion ean he rewritten in terns of discunied factors / component as Cre did Manela EL j4 &BIT CARRY LOOK AHEAD ADDER jy abit carry ' 49, The four stages of addition are st fig? ors wor lel; $0 « ju 00ers WO lel; $0 carry look ahead adder is considered as parallel rhe four bit earry look ahead adder is jook ahead adder; total fo loo ‘otal four full adders are employed in the syst hown in 1 system as show age 7er0; stage or ; Slage one; stage two and stage three. As four simultaneously in . adding the four bits of number A and number B number A are considered as AO, Al, A2 and A3. The bits A3 are considered as the most signif four bits in the ancously. The int and the least significant bits of A. Similarly number pis also containing four bits as BO, B1, B2 and B3. The bits B3 and BO are considered as the gost SB past pipnitica f st significant bits of B. Cin is the initial carry and by default this is seasitered a5 7270. In the circuit of carry look ahead adder; as cary look ahead generator is erating al the carries in advance to save the time of addition, In this way the earry propagation lem that was the limitation of the Ripple carry adder is avoided here with the help of carry ook ahead generator. Carry Look Ahead Generator Figure 2.39. 4-bit carry Look Ahead Adder ‘he bits AO and BO are passed to stage 0 Full adder and sum term SO is generated and the two other components generated are GO (Carry Generate Component) and PO (Carry Propagate 103i ba eaAS A2 ALA 83 820180 4-BIt Carry Look Ahead Adder os cin S3 S2 s1 so Figure 2.40. 4- Bit Carry Look Adder {diagram of 4 bit carry look ahead adder is shown in Fig.2.41 jgouit diag! see? Figure 2.41. 4-Bit Carry Look Ahead Adder: Circuit Diagram 105serate Component is An*Bn. In 1 adder, the earry Generate Compe th my or the stage cary look hem sigrolsC ee in the equtions as se cits. TY Se emer cay represented our carry generate components are ePr= Go A0B0 cence rom Gi=A1Bl cet PECO= 1+ PLEO PL Og G2=A2B2 ca-62 PECL GY PGI PDPL GOS 4 P3C2= G34 PIG2+ PD pa, 7 G=A3B3 rot Re 1 Para pa erate components are derived withthe help of four AND gates The four AND gates are represented as Go, Gl, G2 and G3. The cary the relation An XOR Ba. In this way the four earry propagate e = ery 0 8 goer Py wo gu AND eel ty one two input AND ate, one the weal wei generate By one pa Opn oer on fe Oe The es ve cay Cam be Fema yon pa AND ug vet AND geo ve apt AND ae ad a eg A eration of C3 COMONEN Bach bit of multipli pple of successive shift arting from least S12! ier is checked st a. [fMultiplier bit is 0: Then partial pro‘ is mu Lf Multiplier bit is 1: Then partial product i : computer, It is co’ biinad jon is implemented in @ i jiding n registers for storing ? partial products and then a viding : : process) There i provision of an adder for summation op ocess). The : 2 partial product in a register, accumulating to add all 0°s to partial pr . d 10 Product sing duct is 0. |tiplicand, nvenient to chan, BE Prog When multip slightly because instead of Pro" them simultaneously (cumbersome cessively numbers and suet 9, then there is no nee two binary corresponding bit of multiplier is 0 will not alter its value. Flowchart for multiplication process: The flow chart for Shift-and-Add Multiplication process 1S shown in Fig. 2.47 fer med as register C, A, B, Q and eouy, d, we need various registers nan this register holds the end around carry of adder and initgy ly 1 the register A depends upon number of bits in the implementation of this metho« The register C is one bit register and it is taken as zero. The number of bits in mmultiplicand and the multiplier. We assume the number of bits in the multiplicand and multiply as n. Therefore register A is n bit register. The register A holds the partial product. The initia + is assumed to be zero. Hence all the bits present in the register A are initially Zerg, partial produc The register B holds multiplicand and it contains n bits. The register Q holds multiplier and it aly 0 contains n bits. The Count register is loaded with integer n. ance this process, each bit of multiplier is checked starting from the least significant bit, irst of all, the least significant bit of multiplier i,¢ QO is checked; whether it is 1 or 0. If QO iS prin i 4 one; then multiplicand is added to the initial partial product and the result is stored i combinati gister C Else if all 2 ination of register C and A. Else if QO is zero; then no addition is required, Thereafte oth es gi ift rij i ; a the cases logical shift right operation is performed on the bits of thr i a After shifting all the bits present in the CAQ, the i Mei , the count value is decremented by one, Now count value need to be ch lecked whether it is zero or non zero. If count value is ual IS not equal to zero, thenpiNARY MULTIPLICATION conventional multiplication process ¢ th partial products are generated; one for each digit in multiplier and finally these partial products summed (o produce the final product wes ve partial product is shifted one position to left relative to preceding partial product as shown in Fig.2.46 1011 Multiplicand (11) 1101 Multiplier (13) Lora 0000 1011 Partial products 1011 10001111 Product (143) Figure 2.46. Binary Multiplication prove doing summing operation, each suec ‘The computer arithmetic hardware for multiplication can be implemented based on three methods: i) Shift and Add Multiplication 2) Booth’s Algorithm {Carry Save Multiplication j.1 SHIFT-AND-ADD MULTIPLICATION ifi-and-add multiplication is similar to the multiplication performed by paper and pencil. This ethiod adds the multiplicand M to itself Q times, where Q denotes the multiplier. To multiply two imbers by paper and pencil, the algorithm is to take the digits of the multiplier one at a time from ight (0 left, multiplying the multiplicand by a single digit of the multiplier and placing the ietmediate product in the appropriate positions to the left of the earlier results. 41Figure 2.47. Flow Cis out of the loop. eontrol Thetea 4 and 60" : aller the final product is stored in the register AQ tion oti Shift Right CAQ Count= Count SHIFT Figure 2.47. Flow Chart for Shift-and-Add Multiplicat 13i -and-Add Multipticar Example 2.36. Multiply 1101 by 1011 (11413) using Shift-an plication tori,1, mattiply 1001 by 5100 (9°12) esta Shih wnd-Add Mattptication Algorith=:ajalisation Jai jutiplier i loaded into register Q, ” jutiplicand is loaded into register B, pegister A is initially set to 0. ‘ gesister is initially set to ‘0° é 7 count register is set ton. Where n are een. ik: check the status of Ov Q. i 1fQ> Q1-10. then perform AC A-B % 1fQ> Q1= 01s then perform AC A+ ? 3, After addition or subtraction peor arithmetic shift right on AQ, 4, After arithmetic shift right, the count register is decrem byt sot , sfcount register isnot equal fo 0, then computational loop is repeated FROM step ? to step 4. =0, then final is recei tee pei gp 5: feount ©, then final product is received in register pair AQ and further computation will estopped Ww_ 334. Maltiply and (-3) by using Booth’s Multiplication. ye on? “ mu ve ya EN \ ‘aca s =e = =zaeastil 427 get | a1 | a Sin com: so, Multiply (15) and (12) by sing Booth cate 2.0. MERE E ro" Wt OL re ma TO“ meer T\)o\a camila | ret thle 1 Ba ais [oer | coos Hees es ea a ry moi A A Somme Ne PORE ROY ae caMed Oped cote epee yeye el ele eee | Re ou mV — a seh ao PiNe lenored : ‘ON 7) eye e(e(e lee 7 m Walaualateleenl tal mestet240. . Multi ply ly (15) 5) an id (al 2) by u: sins 1g Be oot] hi’ 'sM ultiy iplica tion mn. waiN L78 CARRY SAVE MULEIPLICATION anc sie 1000 te eon et mica 111, The Sande so et ith deca vale 63 sig ieee ,C. DE and ¥ 98 shown in ig 999 ‘et and six partial products are y ete 1 of all partial prntucts H06 angry tial pd wee Pe ; =) mae if ? iats of #9, 24 and PS, C100 its OF PO, Pong 45 = 101101 % ee ae: wry 90 and suecensive { 4 63=11lilly "” ranged in a toe Wh v t Pan 101101 A Jer with eurry look wend festure to aveimilae the carry yeneruied at th 101101x 8 101101KX ¢ 101101XXX D ie 101101KXXX E 101LOLKKKKK F ————__. ¢ Partial Products : A,B,C,D,e.F ——_—_ Figure 2.50. Carry Save Addition Based Multiplication Tn group of paral products are made in such a way tht ech group comin mines, The group | consists of paral products A, Band C. The group 2 co Fut D. E and F. The groupl partial produets are passed 19 carry save ables sav generated are St and C1. The group 2 partial prods are passed o cat Py| one example 10 understand ant? one ue ae CATTY Save addition based mul ei geimal value 45 cd inary Value 101101, Let muttipti mee Ee 8 value 111111. The X and Y ate passed to plier is Y with decimal value 63 = multi i i i ee plicr and six partial products are nat a. Bs sD; Band Pas shown in F 45 = 101101 X 63 = 111111 y 101101 A 101101X B 101101XX C 101101XXX D 4101101XXXX E 101101 XXXXX F gpartial Products : A,B,C,D,E,F ——— Final Product Figure 2.50. Carry Save Addition Based Multiplication thn goup of partial products are made in such a way that each group contai i satus, The group 1 consists of partial products A, B and C. The group 2 c eee jndu’sD, E and F, The group! partial produets are passed to carry aoe os oe cay generated are SI and Cl. The group 2 partial products are passed to ee 2an 123$1. CY and $2 are pasieadt 410 cay $3, C3 and C2 are ~~, : ne adder 4 and sum and carry generated are S4 und C4 respectively. Tinally Sang 6g ig sum and carry generated are $2 and C2 respective! 3 and sum and carry generated are $3 and C3 respec fi ger ] complete i carry ook ahead ae and inal product em is generate: Ts complete imple of carry save addition based multiplication is shown in F Me Figure 251, tmples Advantages of Carry Save Maltipiy DIVISION BN orth provides a quotient and a rem 5 no inder when we divide two numbers. Binary ise ms are generally Of YO {¥Pes: slow algorith \ vn i 7, noire ae m and fast algorithm. Slow division i je restoring ne Performing restoring, SRT algorithm and under fast ol na mid. 1 enor -Raphso! The detailed discussion about restoring and non ot? om algorithms is given below: oe RING DIVISION ALGORITHM J # : is called so bec: i postoring Bil ‘ause here partial remainder is restored by adding divisor negative difference. oT 104 ee. y spe estore, SHVISION algorithm needs restoring register A after each unsuccessfl y sini The Subtraction is set to unsuccessful if the result is —ve. Therefore this noth 10d is referred to as restoring division algorithm. The flow chart for Restoring Division algorithm 15 shown in Fig. 2.52. _gpivision Algorithm steps: orité itatisation) sep i sor is loaded in register B pjvided is Toaded in register Q pesister A is initially set to zero. ze count register is loaded with number of bits (n) in dividend and divisor. sep? spit A and Q left one binary position sp « subract divisor (B) from A an 4 dplace answer back in A. ACAB Bsjgaes ett of dh of divisi ve vision proc i reiste si ister A stores re oe emain ms TF air At Qk holds result. The e regist er Q st (ores ‘ quoteRestoring Division Now son ALGORITHM of ” 5 DIVISION I it 2:2 NON RESTORING seston) ene boas Simpler tO sori loaded in ester pis va sbaation, 0 09 reser : sve ig adion a js loaded in repister Q pivided ger Ai intially 510 20, vision us dow chart of Non Restoring ® Re ues led wih uso + pect et tis 0nd and ds ge? > catents of TRIIETS A and Q Tet by one Kinry ou qin coments OFT ‘QTefby one binary poston, et? unbitof Ais 1 (means <0) je sian ‘Then add divisor to A(AC Avg) wd) vd yact divisor ffom A (AG A sen subir (ACAD) sen Hed wie sign bitofA is (means AO) ‘Then QE 0 pe (AO) en QE 1 sen ; ‘ecrement count register by 1. Coumt€Count «check count epster, if eount isnot equal 0 then repeat stp {After neyeles, count becomes 0, me ep «hie sign bit of As 1 (means A0) ‘Then It indicates end of division process and register ‘ares quotient and register A stores remainder.ee ee Non-Restoring Division Joaded in register B jsor is + OT jedi toaded in register Q piv" piv _qior A i initially Set to zero, ist! count register is loaded with number of bits (n) in dividend and divisor. he © 197 mnents of registers A and Q left by one binary position, shift ger ee Then add divisor to A (A€ A+B) pit of A is 1 (means A<0) (0) ‘4 sen subtract divisor from A (A€ A-B) 4 ¥ ihe sign bit of A is 1 (means A<0) nite si Then QO€ 0 pie (470) Then Q0€ I sip : foo count register by 1. Count©Count-1 Check count register, if count is not equal to 0, then repeat steps 2-4; (n-1) times more. ‘Aftern cycles, count becomes 0, sip «Ifthe sign bit of A is 1 (means A<0) ‘Then add divisor back to A (A€© A+B). Then there will be end of division process and yistet pair AQ holds result. The register Q stores quotient and register A stores remainder. Hse (A>0) ‘Then It indicates end of division Process and register pair AQ holds result. The register Q res quotient and register A stores remainder. 129py 5 using non restoring division algorithm. Example 2.42. Divide 11 bqNGPOINT ARITHMETIC 2 fl erations witht floating point number are more complicated than with fixed point an tic ° execution of floating-point number takes longer time and requires more complex N ne or rrosting point addition & subtraction of two numbers requires first an alignment of yo since the exponent parts must be made equal before adding or subtracting the e : A Haene by: iS F oe poi te alignment is done by shift one mantissa while its exponent is adjusted until it is i nent. erm of following floati wr me consi the sum. 8 ing point numbers: aie? ot Mh g5372400X 107 per sl per? 0.158000 X a va t; The two exponents must be equal before the mantissa can be added, There are essary thal to! ant Shifting to right causes a loss of least significant fete gone # method is preferable because it only reduces the accuracy while the first method may 1. The usual alignment procedure is: To shift the mantissa that has the smallest case an e170 ato the right by a number of places equal to difference between exponents, After ew pment: Mantssa can be added, The floating point addition implementation by second method soon in Fig. 254. 0.5372400 X 10? + 0.0001580 X 10? 0.5373980 X 107 Figure 2.54. Floating Point Addition 131qxo floating point numbe SX consider ny exponent of the both aumbers same spe number with a smaller exponeny P a in exponents. 8. ~ If ty and equal to the larger exponent. x ire shifting its mantissa TB ee is vince od corre coun, aa ae 68X10 1 | 0,0175X10" torcemine the sign of result mantissa and det Step 3: Perform addition Subtraction om the Step 4: Normalize the result, if neCesSAY bers. Example 243. Find the sum of following floating point Number 1:- X = 0.9504 x 10" Number 2: ¥ = 0.8200 x 10° Solution: XS Aw 10" = 0.9504x 10" ¥ = B x 10>= 0.8200 20° 2) Compare exponents + 3-2=2 2) Align mantissas X= o.ss0ex 1c = 0.08200 x 10° 3) Add mantissas 2= 21.0324 x20 4) Normatze a Spice coyleeX=Ax10-=0.950ax = B x 10°= 0.8200x: 22 {assume e122) 1) Compa exponen 2) Align mantissas X= 0.9504x 3 3) Subtract mantiss 2 =0.8068a0 4) Normalized resul Pr sanye 24 Fstpve sairstion rina Hine ptt member, K =A x10 = 0.9504x 10° Y= Bx 10°= 0.8200x 10 1) Compare exponents : 3-221 2) Align mantissas X = 0.9504 x 10° Y= 0.08200 x 10° 3) Subtract mantissas Z = 0.806840 x 10° 4) Normalized result 2 =0.806840x 10°