IEEE Sponsored 2nd International Conference on Innovations in Information Embedded and Communication Systems
ICIIECS'15
A New Multi Level DC Link Inverter Topology with
Variable Frequency Inverted Sine Carrier PWM
under Equal Switching Transition
M. Keerthana
Department of EEE
M.I.E.T Engineering College
Tiruchirappalli, India
keerthymathi@gmail.com
Abstract-This paper presents with a novel course group of
multilevel topology to trim down the number of switches,
clamping diodes and dearth of capacitors based on DC link. A
new variable inverted sine carrier PWM is used as a switching
technique with equal switching transition. A multilevel voltage
source inverter can be shaped by connecting a Multi Level DC
Link (MLDCL) with a single-phase bridge inverter. The MLDCL
provides a dc voltage with the shape of staircase reminiscent of
the rectified form of a commanded sinusoidal wave, with or
without pulse width modulation to the bridge inverter, which in
turn alternates the polarity to generate an ac voltage. Compared
with the cascaded H-bridge, diode-clamped, flying-capacitor
multilevel inverters, the MLDCL inverters can appreciably trim
down the switch count as well as the number of gate drivers as
the number of voltage levels increases. A new variable frequency
inverted sine carrier pulse width modulation (VFISCPWM) with
equal switching transition is used to control this proposed
topology. Simulation results are obtained and compare with
multi carrier phase disposition pulse width modulation
(MCPDPWM) to validate the proposed inverter.
Index Terms-Multi Level Inverter, PWM, THD, Equal
Switching Transition, Voltage Level
I. INTRODUCTION
Multilevel inverter is an effective and practical solution for
increasing power demand and reducing harmonics of AC
waveforms. Function of a multilevel inverter is to synthesize a
desired voltage wave shape from several levels of DC voltages.
The principal function of multilevel inverters is to synthesize a
desired ac voltage from several separate dc sources, which may
be obtained from batteries, fuel cells, or solar cells. The desired
output voltage waveform can be synthesized from the multiple
voltage levels with less distortion, less switching frequency,
higher efficiency, and lower voltage devices [1]-[5]. Multilevel
voltage-source inverters based on the diode-clamped phase
legs, flying-capacitor phase legs, or cascaded H-bridges were
proposed for replacing the two-level inverters with series
connection of switches or transformer-coupled multiple two­
level inverters in medium and high-voltage level applications
such as motor drives and static var compensators [6]-[7]. The
978-1-4799-6818-3/15/$31.00 © 2015
L. Jebaraj
Department of EEE
M.I.E.T. Engineering College
Tiruchirappalli, India
jebarajjebin@gmail.com
multilevel structures can ensure even voltage sharing, both
statically and dynamically, among the active switches while it
is difficult for a two-level inverter with a series connection of
switches to do so. Substantial reduction in size and volume is
possible due to the elimination of the bulky coupling
transformers or inductors. Multilevel inverters can offer better
voltage waveforms with less harmonic content and, thus, can
significantly reduce the size and weight of passive filter
components.
The last feature was further explored in multilevel inverters
using insulated gate bipolar transistors (IGBTs) for replacing
gate-turn-off-thyristor (GTO)-based two-level inverters
because IGBTs can switch faster and have less demanding gate
drive requirements than GTOs. On the other end of the power
spectrum, because of their low cost resulting from widespread
use in the automotive and power supply industries, low on­
resistance, and fast switching capability, low-voltage
MOSFETs are utilized in multilevel inverters to reduce the
inverter cost or to provide a high bandwidth sinusoidal output
voltage at high efficiency that it is unable to achieve with linear
amplifiers [8]-[10]. Despite the superior voltage waveform
quality provided by higher level inverters, the neutral point­
clamped inverter in [11] perhaps the most widely used
multilevel structure because of its relatively small number of
switches. The high switch count and the difficulty in balancing
the voltage of the capacitors in the diode-clamped
configuration have prevented the wide acceptance of the higher
level inverters in practical applications. As the number of
voltage levels m grows, the number of active switches
increases according to 2 x (m-I) for the cascaded H-bridge,
diode-clamped, and flying-capacitor multilevel inverters. In
addition, for each phase, the diode-clamped inverter requires at
least 2 x (m-2) clamping diodes and (m-l) capacitors for
dividing the dc voltage, and the flying-capacitor inverter needs
(m-2) clamping capacitors.
This paper presents a new class of multilevel inverters
based on an MLDCL and a bridge inverter with a new variable
frequency inverted sine carrier PWM implementation [12]
under equal switching transition. Compared with the
IEEE
 IEEE Sponsored 2nd International Conference on Innovations in Information Embedded and Communication Systems
ICIIECS'15
conventional multi carrier PWM multilevel inverters, the new
MLDCL inverters can significantly reduce the switch count as
well as the number of gate drivers as the number of voltage
levels increases. For a given number of voltage levels , the new
inverter requires active switches, roughly half the number of
switches, clamping diodes, and absence of voltage-splitting
capacitors in the diode-clamped configuration, or clamping
capacitors in the flying-capacitor configuration. Simulation
results are carried out and compare with the same topology
through MCPDPWM method to verity the validity of the
proposed MLDCL inverter.
II. C ARRIER B ASED SH-PWM METHOD
The author [13] developed multilevel sub harmonic PWM
(SHPWM) as follows. For an m level inverter, m-lcarriers with
the same frequency fc and same peak-to-peak amplitude Ac are
disposed such that the bands they occupy are contiguous. The
reference, or modulation, waveform has peak-to-peak
amplitude Am and frequency fm, and it is centered in the
middle of the carrier set. The reference is continuously
compared with each of the carrier signals. If the reference is
greater than a carrier signal, then the active device
corresponding to that carrier is switched on, and if the
reference is less than a carrier signal, then the active device
corresponding to that carrier is switched off. In multilevel
inverters, the amplitude modulation index rna and the
frequency ratio m fare defmed as
Am
m a=--'-'-'----
(m-l).Ac
(1)
fc
m f =­ (2)
fm
The author also considered different methods of disposing
the many carrier bands required in multilevel PWM. In carrier­
based multilevel PWM, the number of carrier bands is one less
than the number of voltage levels for an inverter with an odd
and even number of bands(even and odd number of levels). For
a sine-wave modulation (reference) waveform centered in the
carrier bands (SH-PWM), the duration of time that the
waveform exists during each of the bands occupied can be
computed as follows. Using the amplitude symmetry of the
sine wave about the time axis, the band crossing times, where
[
the reference waveform crosses from one band to an adjacent
band, for bands above (or containing the zero axis in the case
( )
that is even) can be computed from
J
m-I
1 . .[--1]
2.n-mod --
2 m
t n= ( _) ; n= 0, , 2, (3)
m a-m I. 2 D
where mod(x/y) is the modulus operator. Also noting that
the sine wave has a maximum amplitude at 7r 12, this is set
equal to t [mI2] . From (3), the band dwell times in radians
(starting at the band adjacent to the zero axis in the case that m
is odd or the band occupying the zero axis in the case that is
even) are then calculated
tband n= 2.(t n+l- t n );n= 0,1,2, . .[� -1] (4)
Because of the symmetry of the sine wave about the zero
axis, the bands below the zero axis are simply
tband-n= tband n (5)
The number of switching per modulation cycle at each level
of the inverter is dependent on the carrier frequency for that
level and the duration of time that the reference waveform
dwells within the level's corresponding time band. If the carrier
frequency for all of the levels is identical, the top and bottom
levels will have many more switching than the intermediate
levels.
III. PROPOSED INVERTER TOPOLOGY
The power circuit of new proposed simple basic umt IS
shown in figurel. It consists of two dc voltage sources, one
diode and five unidirectional switches (S, Sb Sz, S3 and S4)
from voltage point of view. The unidirectional switches
conduct current in two directions and block voltage in one
direction. In addition, each unidirectional switch consists of an
IGBT with an anti-parallel power diode and a driver circuit.
The number of switches available in this circuit is five.
Therefore, the number of driver circuits in the proposed system
is also only five and thereby with less switch count compared
to existing topologies, gives low switching losses and thereby
increase in efficiency. So size and cost of the inverter is
reduced. One diode is connected across the series combination
of voltage source Ez and switch S. The operation of proposed
1:
inverter is classified in to four modes.
Mode The switches Sl and S4 are in ON state. The other
switches (S, Sz and S3) are in OFF state. The current flow path
under this made is EI-SI-L-S4-D-EJ and the output voltage
across the load is +Vdc.
Mode 2: The switches S, SJ and S4 are in ON state. The
other switches (Sz and S3) are in OFF state. The current flow
path under this made is EJ-SJ-L-S4-EJ-S-Ez and the output
voltage across the load is +2Vdc•
1
I( I(
E, •
Sl S3
_
�
1
S2
S.
Ez
Fig.l: Proposed MLDCL inverter topology
Mode 3: The switches Sz and S3 are in ON state. The other
switches (S, SJ and S4) are in OFF state. The current flow path
 IEEE Sponsored 2nd International Conference on Innovations in Information Embedded and Communication Systems
ICIIECS'15
under this made is EJ-SrL-SrD-EJ and the output voltage path under this made is EJ-SrL-SrErS-EJ and the output
across the load is -Vde' voltage across the load is -2Vdc. The output voltage Vde has
been taken as 100V. All the operating modes are also given in
- figure 2.
Table I shows the output voltage levels of the proposed unit
s, 1 -
s,
based on different switching patterns. In this Table, 1 and 0
indicate the on and off states of the switches, respectively. As
1
shown in Table , the proposed basic unit is able to generate five

1
Load
voltage levels (two positive levels, two negative levels and one
S2 s. zero level) at the output. It is also obvious that this basic unit is
E2 D
1 able to generate all of the positive and negative voltage levels
at the output.
-
-
TABLE I: THE OUTPUT VOLTAGE OF THE PROPOSED BASIC UNIT BASED ON
(a) Mode 1 DIFFERENT SWITCHING PATTERNS

-
Mode S S, Sz S3 S4 Vdc
-
E,

1
1 0 1 0 0 1 +Vdc
s, s,
- 2 1 1 0 0 1 +2Vdc
s

1
Load
3 0 0 1 1 0 -Vdc
S,
+

E, D 4 1 0 1 1 0 -2Vdc

-
- The proposed control strategy replaces the conventional
fixed frequency carrier waveform by variable frequency
(b) Mode 2 inverted sine carrier PWM under equal transition. The inverted
sine carrier PWM has a better spectral quality and helps to the
- output voltage for a given modulation index compared to the
1 conventional carrier based PWM. In order to balance the
number of active switching among the levels is to vary the
- carrier frequency based on the slope of the modulating wave in
each band. The frequency ratio for each band should be set
1
Load
properly for balancing the switching action for all levels.
S2 The VFISPWM provides an enhanced spectral quality and
D helps to the output voltage for a given modulation index, lower
total harmonic distortion (THD) and minimizes the switch
-
utilization among the various levels in inverters. In this method
the control signals have been generated by comparing
(c) Mode 3
sinusoidal reference signal with a high frequency inverted sine
-
carrier. The carrier frequencies are so selected that the number
- of switching in each band are equal. A comparative evaluation

1
E, between the VFISPWM and the conventional modulation is
s, S, also presented in terms of output voltage quality, power
- circuitry complexity, and total harmonic distortion (THD),
s
weighted total harmonic distortion (WTHD) and
1
Load
implementation cost.
1
S, s.
+
For the ISCPWM pulse pattern, the switching angles may
E2 D be computed as the same way as SPWM scheme. The
- equations of inverted sine wave is given by (7) and (8) for its
- odd and even cycles respectively. The intersections (qJ, qz, q3
(d) Mode 4
... qi) between the inverted sine voltage waveform of amplitude
1 p.u and frequency fc and the sinusoidal reference waveform
Fig. 2: Operation under different modes of amplitude Ma p.u and frequency fo can be obtained by
Mode 4: The switches S, Sz and S3 are in ON state. The substituting(6) in both (7) and (8). The switching angles for
other switches (Sl and S4) are in OFF state. The current flow ISCPWM scheme can be obtained from (9) and (10).
 IEEE Sponsored 2nd International Conference on Innovations in Information Embedded and Communication Systems
ICIIECS'15
y = m asinx (6) amplitude levels. The output voltage comparison at different

( ; (i -1)J
amplitude levels are also shown in figures 3 to 7.
y =1-sin m f x - (7)

y= 1-sin ( mf x - ; (i- 2)J (8)

(
m aSinqi + sin m fqi- ; (i-l)} i=1,3,5... (9)
(a)

(
m aSinqi +sin m fqi- ; (i-2)} i=2,4,6... (10)

where
Ma - modulation index
Mf - frequency ratio
(b)
IV. RESULTS AND DISCUSSION
Fig.4: Output voltage waveform comparison under the sine amplitude of 0.7.
In this work the simulation results were obtained from the (a) MCPDPWM method (b) Proposed VFISCPWM method
proposed 5 level topology through Variable Frequency
Inverted Sine Carrier Pulse Width Modulation technique
(VFISCPWM) under equal switching transition and compare
the validity of results with Multi Carrier Phase Disposition
PWM (MCPDPWM) method under the same topology. The
simulation results were taken through MATLAB 7.6
SIMULINK platform using 2.8 GHz Intel Core 2 Duo
processor based PC. The proposed 5 level inverter topology is (a)
run with two types of modulation techniques named as
MCPDPWM and VFISCPWM with the following parameters.

(b)
Fig.5: Output voltage waveform comparison under the sine amplitude ofO.8.
(a) MCPDPWM method (b) Proposed VFISCPWM method
(a)

(a)
(b)
Fig.3: Output voltage waveform comparison under the sine amplitude of 0.6.
(a) MCPDPWM method (b) Proposed VFISCPWM method

The two DC power sources are 100 V each. The load

resistance value is set to be 100 ohms. The output voltage of
the proposed inverter is 200 V and the output current is 2 A.
The validity of results is verified with five different sine
amplitude conditions are 0.6, 0.7, 0.8, 0.9 and 1.0 respectively. (b)
The percentage THD values are also obtained under the same Fig.6: Output voltage waveform comparison under the sine amplitude of 0.9.
(a) MCPDPWM method (b) Proposed VFISCPWM method
 IEEE Sponsored 2nd International Conference on Innovations in Information Embedded and Communication Systems
ICIIECS'15
f3 11E======""""""""'"""'''
''''
''' ''"''======
'' ��
is equal will results the quality and quantity of the output
voltage increased in proposed method as compare with the
MCPDPWM method. The output voltage wave forms are taken
in five different amplitude levels. In MCPDPWM method the
number of pulses at every stage is not same under all different
amplitude levels. In similar way the current wave forms are
also give the reflection of voltage wave form in feasible
(a) manner. The output current comparison at different amplitude
levels are also depicted in figures 8 to 12.

(b)
Fig.7: Output voltage waveform comparison under the sine amplitude of l.0. (a)
(a) MCPDPWM method (b) Proposed VFISCPWM method

(b)
(a)
Fig.IO: Output current waveform comparison under the sine amplitude ofO.8.
(a) MCPDPWM method (b) Proposed VFISCPWM method

(b)
Fig.8: Output current waveform comparison under the sine amplitude of 0.6. (a)
(a) MCPDPWM method (b) Proposed VFISCPWM method

(b)
(a)
Fig.ll: Output current waveform comparison under the sine amplitude of 0.9.
(a) MCPDPWM method (b) Proposed VFISCPWM method

The RMS voltage levels at different amplitudes are given in

(b)
Fig.9: Output current waveform comparison under the sine amplitude of 0.7.
(a) MCPDPWM method (b) Proposed VFISCPWM method
From the output voltage point of view by implementing the
equal switching transition, the number of pulses at every stage
Table 2. From these results the RMS voltage is increases in
proposed method by 14.32 V against MCPDPWM method
under the amplitude level of 0.6 will makes to increase 17.05%
of voltage rise in proposed method. Similarly the increasing
voltages are 14.14V, 14.8 V, 10.9 V and 8.4 V against
MCPDPWM method under the amplitude level of 0.7, 0.8, 0.9
and 1.0 respectively will also makes to increase 14.26%,
13.17%, 8.62% and 5.94% of voltage rise in proposed method
respectively. From these analyses it is proved that the validity
of proposed method is quite suitable.
 IEEE Sponsored 2nd International Conference on Innovations in Information Embedded and Communication Systems
ICIIECS'15
The peak voltage levels at different amplitudes are given in Fundllmental (50Hz) '" 139 ..
nm ", 4523%

Table 3. From these results the peak voltage is increases in

proposed method by 20.20 V against MCPOPWM method
under the amplitude level of 0.6 will makes to increase 17.00%
of voltage rise in proposed method. Similarly the increasing
voltages are 20.0 V, 20.9 V, 15.5 V and 15.8 V against
MCPOPWM method under the amplitude level of 0.7, 0.8, 0.9
and 1.0 respectively will also makes to increase 14.26%, Fig.13: Harmonic spectrum for Output current of proposed VFISCPWM
13.15%, 8.67% and 5.89% of voltage rise in proposed method under the sine amplitude of 0.6.
respectively. From these analyses it is proved that the validity Fundamental (50Hz) '" 1602 .. THD", 40 .. 17%

of proposed method is quite suitable. � 20

25

�
] 15
."
;£ 10

:!1 5

Fig.14: Harmonic spectrum for Output current of proposed VFISCPWM

under the sine amplitude of 0.7.
Fundamental (50Hz)" 179 8 .. .. THO= 35J7%

(a)
20

� 15
J
'E'O
'£

Fig.IS: Harmonic spectrum for Output current of proposed VFISCPWM

under the sine amplitude of 0.8.
(b) Fundamental (50Hz) '" 194.2 .. THD= 30.60%

16
Fig.12: Output current waveform comparison under the sine amplitude of l.0. � 14
(a) MCPDPWM method (b) Proposed VFISCPWM method � 12
�
§ 10
TABLE II: RMS VOLTAGE AT DIFFERENT AMPLITUDE LEVEL � 8
� 6
:!1
RMS Voltage 4

RMS Voltage 2

Amplitude (Proposed
(MCPDPWM)
VFISCPWM)
Fig.16: Harmonic spectrum for Output current of proposed VFISCPWM
0.6 83.98 98.3
under the sine amplitude of 0.9.
0.7 99. 1 6 1 1 3 .3
Fundamental (50Hz) = 211.9 .. THO= 28.01%

0.8 1 1 2.4 127.2

0.9 126.4 1 37.3

1 .0 1 4 1 .5 1 49.9

The harmonic spectrum of output current for the proposed

inverter under different amplitude level is depicted in figures
13 to 17. The percentage THO comparison is also depicted in Fig.17: Harmonic spectrum for Output current of proposed VFISCPWM
figure 18. From these figures the reduction in total harmonic under the sine amplitude of 1.0.
distortion is exposed in majority of amplitude cases such as .VFISCP\VM aMCPDP\VM
0.6, 0.7, 0.8, 0.9 and 1.0. 60
45.23
50
TABLE II: RMS VOLTAGE AT DIFFERENT AMPLITUDE LEVEL 40
a
E: 30
Peak Voltage >'
20
Peak Voltage
Amplitude (Proposed 10
(MCPDPWM)
VFISCPWM)
0.6 1 1 8.8 1 39.0

0.7 1 40.2 1 60.2

Fig.18: % THO level comparison at different amplitude

0.8 1 58.9 179.8 From figure 18, the percentage total harmonic distortion
0.9 178.7 1 94.2
reduction occurred in the amplitude levels 0.6, 0.7 and 0.8 are
1 .0 200. 1 2 1 1 .9
4.47%, 2.36% and 3.94% respectively. Similarly in the
amplitude levels 0.9 and 1.0 are 2.54% and 6.57% respectively.
 IEEE Sponsored 2nd International Conference on Innovations in Information Embedded and Communication Systems
ICIIECS'15
It is proved that the proposed topology with VFISCPWM
method is having superior advantages than the proposed
topology with MCPDPWM method. Voltage levels under
equal switching transition can also give the validated results
against the switching techniques by MCPDPWM method.
V. CONCLUSION
In this study a novel course group of multilevel topology
was constructed to trim down the number of switches,
clamping diodes and dearth of capacitors based on DC link. A
new variable inverted sine carrier PWM is used as a switching
technique with equal switching transition. is used to control
this proposed topology. Simulation results are obtained and
compare with multi carrier phase disposition pulse width
modulation (MCPDPWM) to validate the proposed inverter.
From the simulated results VFISCPWM with equal switching
transition is proved to be superior as compare with
MCPDPWM technique without equal switching transition.
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