B.

Tech 1st Semester

Basic Electronics (ECCI-101)

Field Effect Transistors

Faculty
Dr. Partha Pratim Shome
Department of Electronics and Communication Engineering
Dr B R Ambedkar National Institute of Technology Jalandhar,
India
parthaps.ec@nitj.ac.in
 Field Effect Transistors (FETs)

⮚FET is a three terminal semiconductor device. It is unipolar transistor i.e.

depends only on one type of charge carrier, either electron or hole.

⮚The current is controlled by the applied electric field hence, it is a voltage

controlled device.

⮚FET is simple to fabricate and occupies less space on a chip than a BJT.
About 100000 FETs can be fabricated in a single chip. This makes them
useful in VLSI (very large scale integrate) system.

⮚It have high input Impedances and Low output Impedance so they are
used as buffers at the front end of voltage and other measuring devices.

⮚There are two types of FET – the JFET (Junction Field Effect Transistor)
and MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
Field Effect Transistors (FETs)- Types
 Junction FETs (JFETs)

There are two types of JFETs There are three terminals:

• n-channel • Drain (D) and Source (S) are connected to the n-
• p-channel channel
The n-channel is more widely • Gate (G) is connected to the p-type material
used.
The basic construction of the n -channel JFET is shown in
the Figure. The major part of the structure is the n -type
material, which forms the channel between the embedded
layers of p -type material. The top of the n -type channel is
connected through an ohmic contact to a terminal referred
to as the drain (D), whereas the lower end of the same
material is connected through an ohmic contact to a
terminal referred to as the source (S). The two p -type
materials are connected together and to the gate (G)
terminal. In essence, therefore, the drain and the source are
connected to the ends of the n -type channel and the gate to
the two layers of p -type material. In the absence of any
applied potentials the JFET has two p – n junctions under
no-bias conditions. The result is a depletion region at each
junction.
 MOSFETs

⮚The name MOSFET stands for metal-oxide-semiconductor-field-

effect- transistor.

⮚MOSFETs can be further divided into depletion type and

enhancement type.

⮚The MOSFETs became a practical reality in the 1970s.

⮚In the MOSFET, the current is controlled by an electric field

applied to the semiconductor surface.

⮚This phenomenon used to modulate the conductance of a

semiconductor, or control the current in a semiconductor, by
applying an electric field perpendicular to the surface is called the
field effect.
 Depletion Type MOSFETs

n-Channel depletion-type MOSFET p-Channel depletion-type MOSFET

Graphic Symbols for depletion-type MOSFET

Depletion Type MOSFETs: Basic Construction

The basic construction of the n-channel depletion-type

MOSFET is provided in the adjacent figure. A slab of p
-type material is formed from a silicon base and is
referred to as the substrate. It is the foundation on
which the device is constructed. In some cases the
substrate is internally connected to the source terminal.
However, many discrete devices provide an additional
terminal labeled SS, resulting in a four-terminal device.
The source and drain terminals are connected through
metallic contacts to n-doped regions linked by an n-
channel as shown in the figure. The gate is also
connected to a metal contact surface but remains
insulated from the n-channel by a very thin silicon
dioxide (SiO2) layer. SiO2 is a type of insulator referred
to as a dielectric, which sets up opposing (as indicated
by the prefix di-) electric fields within the dielectric
when exposed to an externally applied field. The fact
that the SiO2 layer is an insulating layer means that:
There is no direct electrical connection between the
gate terminal and the channel of a MOSFET.
Depletion Type MOSFETs: Basic Construction

In addition:
It is the insulating layer of SiO2 in the MOSFET
construction that accounts for the very desirable high
input impedance of the device.
Because of the very high input impedance, the gate
current IG is essentially 0 A for dc biased
configurations. The reason for the label metal–oxide–
semiconductor FET is now fairly obvious: metal for
the drain, source, and gate connections; oxide for
the silicon dioxide insulating layer; and
semiconductor for the basic structure on which the
n- and p-type regions are diffused.

The construction of a p-channel depletion-type

MOSFET is exactly the reverse of p-channel MOSFET.
That is, there is now an n-type substrate and a p-type
channel, as shown in the adjacent figure. The terminals
remain as identified, but all the voltage polarities and
the current directions are reversed.
Depletion Type MOSFETs: Basic Operation

In the Figure, the gate-to-source voltage VGS is set to 0

V by the direct connection from one terminal to the
other, and a voltage VDD is applied across the drain-to-
source terminals. The result is an attraction of the free
electrons of the n-channel for the positive voltage at the
drain. The result is a current similar to that flowing in
the channel of the JFET. In fact, the resulting current
with VGS=0 V continues to be labeled IDSS, as shown in
the Figure.
In the bottom Figure, VGS is set at a negative voltage
such as -1 V. The negative potential at the gate will
tend to pressure electrons toward the p-type substrate
(like charges repel) and attract holes from the p-type
substrate (opposite charges attract) as shown in the Fig.
Depending on the magnitude of the negative bias
established by VGS, a level of recombination between
electrons and holes will occur that will reduce the
number of free electrons in the n -channel available for
conduction. The more negative the bias, the higher is
the rate of recombination.
Depletion Type MOSFETs: Basic Operation

The more negative the bias, the higher is the rate of

recombination. The resulting level of drain current is
therefore reduced with increasing negative bias for VGS.
For positive values of VGS, the positive gate will draw
additional electrons (free carriers) from the p-type
substrate due to the reverse leakage current and
establish new carriers through the collisions resulting
between accelerating particles. As the gate-to-source
voltage continues to increase in the positive direction,
the drain current will increase at a rapid rate for the
reasons listed above. As revealed above, the application
of a positive gate-to-source voltage has “enhanced” the
level of free carriers in the channel compared to that
encountered with VGS= 0 V. For this reason the region
of positive gate voltages on the drain or transfer
characteristics is often referred to as the enhancement
region, with the region between cutoff and the
saturation level of IDSS referred to as the depletion
region.
Depletion Type MOSFETs: Drain and Transfer Characteristics

n-Channel

p-Channel

Transfer Characteristics Drain Characteristics

 Enhancement Type MOSFETs: Construction
D
Metal
G
Oxide
S • The Drain (D) and Source (S) connect
(SiO2)
to the to n-doped regions.
• The Gate (G) connects to the p-doped
W
substrate via a thin insulating layer of
Drain
region
SiO2
n+ n+
L
Source
region Drain (D) Gate (G) Source (S)
p-type
substrate Metal Oxide
(Body) Channel (SiO2)
region

Channel
n+ n+
B region

p-type L
• The primary difference between the substrate
construction of depletion-type and (Body)

enhancement-type MOSFETs is the Body (B)

absence of a channel
• The n-doped material lies on a p-doped
substrate that may have an additional
terminal connection called the Substrate
(SS)

Circuit Symbols for enhancement-type MOSFET

 Enhancement Type MOSFETs: Operation

G VDS
D VGS If, both VDS and VGS have been set at
iD iG S
iS =iD some positive voltage greater than 0 V,
u +
=0
+u
establishing the drain and the gate at a
positive potential with respect to the
+u +u
iD

e-
e-
p-type substrate e- e-
If VGS = 0 V and a voltage applied between
the drain and the source of the device of,
the absence of an n-channel will result in a
current of effectively 0 A. With VDS some
positive voltage, VGS at 0 V, and terminal
SS directly connected to the source, there
are in fact two reverse-biased p–n junctions
between the n-doped regions and the p-
substrate to oppose any significant flow
between drain and source.
source. The positive potential at the gate
B
will pressure the holes (since like charges
GND repel) in the p-substrate along the edge of
the SiO2 layer to leave the area and enter
deeper regions of the p-substrate. The
result is a depletion region near the SiO2
insulating layer void of holes. However,
the electrons in the p-substrate will be
attracted to the positive gate and
accumulate in the region near the surface
of the SiO2 layer. The SiO2 layer and its
insulating qualities will prevent the
negative carriers from being absorbed at
the gate terminal.
Enhancement Type MOSFETs: Construction
 Enhancement Type MOSFETs: Triode Region

G
As VGS increases in magnitude, the
VGS VDS
D iD S
concentration of electrons near the SiO2
iG iS =iD
surface increases until eventually the
=0
u +
+u +u
+u induced n-type region can support a
iD
measurable flow between drain and
e- e- source. This region in the transfer
B
p-type substrate e- e- characteristic curve is also known as
GND Triode region. The level of VGS that
results in the significant increase in drain
iD (mA) vGS = Vt+2 V current is called the threshold voltage and
0,4 is given the symbol VT. Since the channel
vGS = Vt+1,5 V
is nonexistent with VGS = 0 V and
0,3
“enhanced” by the application of a
vGS = Vt+1 V
positive gate-to-source voltage, this type
0,2
of MOSFET is called an enhancement-
0,1
vGS = Vt+0,5 V
type MOSFET.
vGS ≤ Vt

0 50 100 150 200 vDS (mV)

Enhancement Type MOSFETs: Triode Region
 n-MOS Transistor Operation: Saturation Region

If we hold VGS constant and increase the level of VDS, the drain current will eventually reach
a saturation level. The leveling off of ID is due to a pinching-off process depicted by the
narrower channel at the drain end of the induced channel .

G
DS
D VGS
iD S
iG V
iS =iD
=0
+u +u

iD
n-channel
B
p-type substrate
GND

If VGS is held fixed at some value such as 8 V and VDS is increased from 2 V to 5 V, the voltage VDG will
increase from -6 V to -3 V and the gate will become less and less positive with respect to the drain. This
reduction in gate-to-drain voltage will in turn reduce the attractive forces for free carriers (electrons) in
this region of the induced channel, causing a reduction in the effective channel width. Eventually, the
channel will be reduced to the point of pinch-off and a saturation condition will be established as
described
Channel Length Modulation
 p-Channel Enhancement MOSFET

The p-channel enhancement-type MOSFET is similar to the n-

channel, except that the voltage polarities and current directions
are reversed.