HD68000/HD68HCO000 MPU (Micro Processing Unit) — HD¢8000 — "The HD68000 is the first in a family of advanced micropro: cessor from Hitachi, Utilizing VLSI technology, the HD68000 fs a. fullydmplemented l6-bit microprocessor with 32-bit fester, 2 rich basi instruction set, and versatile addressing modes. "The HD68000 potseses an atynchronous bus structure with 24-bit address bus and a 16-bit data bus. FEATURES ‘© 32-Bit Data and Address Registers © 16 Megebyee Direct Addressing Range (© 56 Powerful Instruction Types Operations of Five Main Data Types Memory Mapped, / (© 14 Addressing Modes — HDeBHCO00 — “The HD68HC000is a 16-bit microprocessor of HD68000 family, which is exactly compatible with the conventional HD88000. “The HDSSHCOOO is « complete CMOS device and the power dissipation is extremely low. FEATURES ‘© Instruction Compatible with NMOS HD68000 in Compatible with NMOS HD68000 ‘SAC Timing Compatible with NMOS HOG8000 Low Power Disipation log t¥p = 20 mA, Ice mex =35 mA at f= 125 MH} 11D68000-8, HD68000-10, HD68000-12 HDB8HC000-8, HDEBHCO00-10, HOD6BHC000-12 HD68000¥-8, HD68000 MbeonGD0oY 8 HOSSNCOODY. 10, HDBEMCODDY-12 wr (cas) "H088000P-3 HD6SHC000P.8, HDSSHCODOP.10, HDSBHCOQOP-12 S (oP.64) ‘HD88000PS-8 HO6BHCOOOPS-8, HOSBHCOOOPS-10, HOE8HCOOOPS-12 & (0P.645) HDsB0000P-8 HD6BHCOOOCP-6, HOB8HC000CP-10, HD6SHCOOOCP.12 @& (cP-68) @ HITACHI Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 * (415) 589-8300 907HD68000/HD68HCO00 = TYPE OF PRODUCTS TwoeNo. | Procan | SPATS rosage Teams a0 Te HO68000-10 10.0 ae ‘HOG8000-12 125 oaEDDO¥E 3 HO68000¥10, NMOS 100 a oe 13 OBeoOORS 30 OeanoOP So 70 osencocre 30 Hoeercooo 3 20 FossH000.70 168 HD68HCO00-12 125 Cen! Hoss = Hossvtooo0 30 Too] Pcacs Hosswcoooes2 138 HossHooooRe to HoseHcooarso—] cmos [—7os—] ores Hosercoooat2 135 Hosarcoo0reo to FOSBHCOOOPSIo Too —} vss HOGBHCOOOPHZ_| 125 Hoesrenooces to Hear cno0CR Too] crs HOBBFCOONCRTT 135 (Note) 1068000 eters to the NMOS varion 68000, and HOBSHCDOD ‘ltr othe CU reson 800” 6800 ees for NMOS @HITACHI 908 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300© PIN ARRANGEMENT © Panes. HD62000/HD68HC000 (Top View) arte ate aw ze ae Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 + (415) 589-8300 @HITACHI Boeggerezezee (Top View! 909HD68000/HD68HC000 |= ABSOLUTE MAXIMUM RATINGS Hem Symbol HDeB00. HDSBHCO00 Unit Valve Value ‘Supply Volts Vec™ O3~ +70 3~ 85 v Input Voltoge Vin" ~035 97.0 a= 85 v ‘Operating Temperature Ronge Toor O= 970 O= #70 e Storage Temperature Too 55 F160 = = F160 c ‘with respect to Vgg (SYSTEM GNOI (NOTE) Permanent LSI damage may ecu Hf maximum rings ae exceeded. Normal operation shouldbe under recommanded operating cantons. ont ar excused, eould aot rly oF USL = RECOMMENDED OPERATING CONDITIONS Since sh HOBBHCDOO is» -MOS device, usr are expected tobe cautout on “een proba emia by voltage frecturtont. em Symbol HoB#o08 osenicoeo Unit min | wo [max | min | wo | max Supply Voriage Veo" | 475 | 60 | 525 | 475 | 60 | 626 v LK 7 26 [= Wer Inoue Voltage [Omarion | "| 2 | | Mee [20 fT Vee ul ‘All inputs Var | -03 | - | 08 [-03 [~- [os v Operating Temperature Tews (ss as aes] ean One| ea | 7 *e = wie epee to Vg (SYSTEM GND) @HITACHI 910 Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300© ELECTRICAL CHARACTERISTICS OC CHARACTERISTICS (Voc = SV # BX, Vag = OV, HD68000/HD68HC000 Ta= 0~+70°C, Fig. 1, unless otherwie noted.) Hem, |Symbol | Test Condition cS. — Unit, min | me min | max] CLK T 28 | \% ; ec input “High” Vol ee alee ‘Other Inputs mal 20 | Vel 20 Veo uM Tapa “Low” Votige Vi Ver-03] 08 [ves-03] 08 | Vv TPL, ~ IPLy, VPA, CLK - | 25] - | 28 Ings Lesage Crane Lanta a tn hte TE, A,~ An. Dp ~ 0; ‘Three-State (Off State} po) r O08. eee Fog For tO8.RM- OE, | mr | @zavioav| - | | - | 70 | HA BS, A, ~ Ary, BG, Dp ~ Dy, Output “High” Voltage] FCo~ FCs, EDS, AAW, ODS, | Von | lon=-40Qu 24 | - | Vec-075] - | Vv VA E = Nee-a76) —— FACT Trtéma] - [ost - | 08 A= Bin, BG, Fos ~ FC ta s32ma] - [os] — | 0s Output “Low” Vol ou ee eo" RES Vo. Fig=60ma] - | 05{ - | 05 | v BS,0,~ D5, WOE RATE, | ors ak lo53ma | - | os| - | os Mi femme] - | 15 Power Dissipation a a Pr 4°10 Mi — ‘pa > #2125MHz | — 1.75 - - Ww PLASTIC PACKAGE weetey | - | os e226 teamaz_ | - || — | 2 Curent Disiption tos [texomnr | - | — | - | 0 | ma tesma{ - | — | — | 35 Vn =0V. Capacitance (Package Type Dependent) on | ee | - deoo| - [200 | oF iar ih exe pll uprurior of 1.1K wih oud ov oy sao Se 0” ron yen - on oo 182074) t Eaunatent Ri leoti for Abra, a, BOO, ~O,.€ ere” tbe miwiDe a” sme tBu ter AA BOF, PC, Figue 1 Test Loods @ HITACHI bitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Pint Pky. «Brisbane, CA 94005-1619 « (415) 589-6300 911HD68000/HD68HC000 (© AC CHARACTERISTICS (Voc = BV + 8%, Vos = OV, Ta = 0~ +70°C, unk cLock TIMING otherwise noted.) OMe | 10MM: | 125MHe Item Symbol Test Condition | — = = Unit Frequency of Operation | f 40| 80] 40| 100] 40] 125 mae Gycle Time tee 125 | 260 | 100 a0 | 250 | ne teu 55 [125 [ 45| 125] 35 [ 125] ne Clock Pulse Width Fig.2 tH 85 | 125[ 95] 125] 35] 125 rf. ter =| wf = [wl =] Rise and Fall Times te 0b el at et wore) Te meanurements are raference to and trom alow voltage of 0.8 vot and high voltage of 2.0 vols, unless otherwie note “The voltage wing through this ange should star utuide and ate through the range such tha the eo all wil be near betwten 8 velt ond Bove, Figure 2 Clock input Timing @HITACHI 912 Hitachi America, Ltd. » Hitachi Plaza ¢ 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300HD68000/HD68HC000 READ AND WRITE CYCLES “TTet [8 MHz | 10MM: | 126MHz bn ua) Symbol condition | rin] mex min] max} min] mex] Ut [eer ee] [a8] 280 00] 80] 00 [280 | Giock Width Low et 66 | 126] 46 | 126) 36 | 126) ne 3__| Glock Width High ton 86 | 126| 45 | 126) 36 | 125] ns 4 _| Glock Fall Time ter = [sof -[ of =] sf B_| Crock Rise Time % = [of = [tof = [6 | Glock Low to Address Vall touay =| 70] — | eo] — [66*[ mw @A_| Clock High to FC Valid tenrev =| 70; -| 0] —| 85] = 7 | Glock High to Adaros, Data Bos High Impedance (Maximum) tenaoz =| a) -| 7) -| 0) T_| Chock High to Address, FC Invalid Minima | tena ot-[el-[e[-[w [9*_| chock High to AS, BS Low ‘ons | o| «| o| s6) 0 [ss | 112 | Adare Valid to AS, 58 Low (Rexd/ BS Low (Write) tava aol - | 20] - | o| -| os THAT | FC Vala to AS, DS Low (Reed? TS Low (write) trove eo| - | s0| - | 40] - | m 121_| Clock Low to AS, DS High teusn | Fig. 3, || 70] -| 86] - | 50] me 197_[ AS, DS High to Address/FC Invalid tearr| Fie. [30 — | 2of - [vol — | ne 14 | AS, BS width Low (Read)/AS Low (Write) feu 240} ~ | 195) — | 160| - | ns T4A? | OS wiath Low (Write) %pa._| 115] — | 95] - | 0] — | rs 16? | AS, DS width High te 160] — | 105] — | @5| -| ns T6_| Goock High to Control Bus High Impedance | toncz = [20] - [70] — | 60] ms | 172_| AS, D8 High to R/W High (Read) tenn | ao] - | 20] -[ 10] - | os 184 | Clock High to R/W High ‘oun ‘0 | 70] 0 | ool 0 | ol ns 20° | Glock High to RW Low (Write) ‘oun, = |-70| - [oo] — | oof vs 20a | AS Low to R/W Valid (Write) ‘asav = [20 = [20] — [20] ne 212 | Address Valid to R/W Low (Write) tavat | zo| -[o| -|o[-] ws 210? | FC Vali to RAW Low (Write) ‘eevm eo} - | so[ — | 30] — | 222 | R/W Low to DS Low (Write), StALSL go; - | 50] - | 30) -]| ns 23_| Clock Low to Data Out Vaid (ite tex00 | = | 70] — [a5 — | s5| ns 25? | AS, DS High to Data Out Invalid (Write) | tgupou | 0] — | -20o[ - [15] — | ns 26% | Data Out Valid to DS Low (write 00s | [a0] = |20] — [15] — [os 275 | Data in to Clock Low (Setup Time on Read) | toca | 15] — | 1o| — | to] — | ns 287 | AS, DS High to DTAGK High TsHoAK 0 [245] 0 [100] 0 | 160] ne 29 | AS. DS High to Data In Invalid (Hold Time on Read) ‘SHON o}-| 0} -] 0} -| 30 _| BS, BE Wigh to BERR High Tsuen o{-[ol=|e}t-| = 3125 | BTACK Low to Data In (Setup Time toaLor = | so] - | 0s] - | sol ns 3E_| HAUT and RESET Input Transition Time | trae © [200] “0 | 200] “0 [200] "ns 33_[ Clock High to BG Low ToHGL - | 70! -| ©) 50] ns "34 | Clock High to BG High YoHGH - | 70) - | oo} - | 50) ms w]e] |% 35 | BR Lowto ‘BRLGL 15 +38] 18 +331 1s 43a oy er or bse @HITACHI Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94006-1819 + (415) 589-8300 913HD68000/HD68HC000 READ AND WRITE CYCLES (CONTINUED) Tet [8M] 10Wi: | 125MHe Num ren Symbo!| Condition | in| max | min] mex | min]_max| U* 367 | BR High 10386 High toRHGH 15] SO) 15] Sel 1s] Me loneer 37_| BEAGK Low 10 BG High toaucH 15] Bet 15] 26] 15] MPS ox pee 378° | BGACK Low to BF Hish | toncony 20 | cll 20 | cle! 2° |outel 38 | BG Low to Control, Address, Data Bur a High Impedance (S High) touz =| | -| | -| 0] os 39_| BO wish High on 15] — [48] — [78] — |oxrr 40_| Glock Low to VR Low | avn ed 41_| Clock Low to E Transition tcLeT = [90 |= 55 |= a5 | oe 42_| © Output Ris feet =|, -| 25] - | 25] om 43_| VA Low to E High Wyner 200[ = [iso[ = | 90[ = | ns 44__| AS, DS High to VPA High ‘sven Fia.3, [0 | 120[ 0 | oo| 0] 70] ns 45 | E Low to Control, Address Bur Invalid Fig (Address Hold Time) teLcat go| - | to] - | 1) - | ns “46 _| BGACK Width Low tGAL, 6] = [1s] = [a8] = loner. 17°_| Asynehvonous Input Setup tas 20] = | 20] — [20] — [os 489 | BERR Low to DTACK Low ‘evo 20] = | 20| — | 20] — [ws 49 _| 8, BS High to Low ‘6H6L =70| 70 [-55) 65 [45] 45 | ne 50__| € Width High ten 450] = | 380] — | 200) = [ns 51_| EWisth Low ‘ee yoo] = [ss0[ = | 440] — [ns 53_| Cock High to Data Out Invalid M00! of -le[-|ol-|m™ B4_| E Low to Data Out Invali ‘e101 so] |) 20) — | 6) — | mw '55_| RIW to Data Bur Driven Taupe | = | 10f = 56+ | HALT/AESET Put wih tyre wo] — = [of - 57_| BGACK High to Conwol Bus Driven | taaso. 1] = sl = 887 | BG High to Control Bus Driven ‘oH 15} — T= [os] — ores 1 Fa caectnce of tan or wu t0 50 picture, iba Snanotond rm the alu nin th maximum column 2. Atul ve dipend on clock period 3.1487 wwii for bom OTACK and BERR, #48 maybe 0 nanomcon 914 Bg paar wp, MPU must ba eid a RES wat for 100 mat low saizton of anh creviny. Alter the siti i powered op, arto ihe minanum plee width equles vo rent ove tye It the mynchronous setup tie (#47) requirements ae ating te OTACK low-rate wtp ti (#31) ragularant canbe nore ta mut oni tat the date loc low vetup tine 127) forthe flloning ye ‘Winen Sand FW ara equally loaded (420%), ubtract 10 nanowecond fom the values ven inthe column. ‘The processor wit negate and bapn crivng tha but auin if external ebization loge nogatn BR before ering BGACK. ‘The minimum value must be met to guarantee proper operation, Ifthe maximum value it exceeded, BG may be reared. The aling ede of 8 wage both the negation ofthe svobes (AS and xB) and th ting ep FE, yt evens can occu {in depercing upon the outing 0 tech tana Sone! ‘cur betwen the ‘sin ge ot the svabes and the flop eae ee & lace @ HITACHI Hitachi America, Lig. « Hitachi Plaza « 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (416) 589-8300HD68000/HD68HC000 ‘These waveforms should only be referenced in regard to the output signals. Refer to other functional descriptions and edge-toedge measurement of the timing specifications. They thelr related diagrams for device operation. fare not intended as a functional description of the input and ACT/RESET notes: 1 Satu time forthe wynehonous inputs BGATK, 1FLa3 and VFR autantes thir recognition at he next fling ade of the cock 2. Reed al at thi tne ony in order 0 insre bang recognized wth and ofthis bs evel 3. Timing meesurements ee referenced to and from alow voltage of 0.8 vit ands high voltage 2.0 vol, uniew otharwte note. ‘The vakge rng tough tvs range theuld rt out med bs rough she range auc a he lan fl wil bien Daten Osvoiena Zora. Figure 3. Read Cycle Timing @HITACHI tachi America, Lid,» Hitachi Plaza © 2000 Sierra Point Pray. « Brisbane, CA 94005-1819 « (415) 589-8300 915HD68000/HD68HC000 ‘These waveforms should only be referenced in regard to the signals. Refer to other functional descriptions and their related edge-toredge measurement ofthe timing specifications. They are diagrams for device operation. ‘ol intended asa functional description of the input and output BERR (ote 2) “FAUT IRERET ‘Asynchronous Inout t (ote) NOTES: 1. Timing memurarents ar retecnce to and trom slow voltage of 08 volt and high voltage of 20 volt, unas otherita note. ‘Tha valine ing troup ti range Pou wart cutidewnd pas through the ange sch tet te a fl wi be nea Deen Oe vaitanc ZO volt, ecaue of loingvratons, FUR ey be vali afar B evan though both are initited by the ring eget $2 (Sscietion 204), 2 Figure 4. Write Cycle Timing @uHrmacni 916 Hitachi America, Ltd. « Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300_ HD68000/HD68HC000 © HMCS6800 TIMING Ter [Shiite [Own | TOWNE | 6 MRE ‘em oo SrmbetIconditon| in| max] min] max] min] max] min max] 12_| cock Low wo AS, DS High ‘eu sol - | 70] -| 55) - | so] m 18_| Goek High to RAT High ‘on eof o| 700 | co] 0 | co, nw 20__| Clock High 10 R/W Low (Write vena wo - | 70 -| oo - | eo] me 23] Clock Low to Data Ot Vaid (Wiel ‘e100 wl | ot — | es = | 88] me 27[ Dotan to lock Low (Setup Time on Read) | toe zt [5 - Lot = 0] = po 39] BE. DS High to Daten Inve iota Time on Read) wwon | Fins, | o|-|o]-| 0] -| 0] -| m Wo | Gk Low 0 VW Low exw) Fie [=P RPS] l= | WO = | TO oe 7 Glock Low 0 Transition ust es ee 42 | Output fie and Fall Tne vt = [asl = [as] = [a5] — [26] ne 43_| VUR Low io High een a0] — [200] — | 160] - | 90) - | ne ‘44_| BS. BS High to VPA High ‘eavin 0 |reo| 0 [120] 0 | 6] 0 | 70] ww 45 | E Low to Convel, deren Burinvald | tetas 3] =| 3] -| 1 - | vol - | me (acre old Tal “F_| Rayrehronou Input Sep Te ua zt pol | lf oo 491 _| BS, BS High 1 € Low es [eo] —|-70| 70] ~58] 65) 45] 45] ne 50 | € wieth High 1 eo] — [480] - | 350] - [700] — | mw 51_[ Ewath Low ‘et 300] = [700] — [S80] — [00] — [re 54 [ Ew to Data Out invalid Tip8 ot -1 = -1 =~] sf) nore. 1, The fling ade of 88 igen both he ragation eoending woo gon ech he aing wage ofthe E cock strobe (AS and xD8) and "Speclcation #49 incicney Ue atacute maxima sce that wil eur bean the ring ede Sf ling eof. Either of has event canoocur ft, 80 S182 594 ww Wow ww ww ww ww SE SE ST SD NOTE: Thi timing degra is netded for shoe who wit 10 ton thei own cout to gnarate VHA t show the bast cave pouibly atanaia Figure 5. HDS800 Timing—Best Case @HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300 917HD68000/HD68HC000 OSIM WW i SO8E STO = = NOTE: Thi timing ira tinea for sha who wih to dain thei own iret to ganacate VK, It show the worst cae pomibiyatsnae Figure 6. HOS800 Timing—Weorst Case BUS ARBITRATION Tet | Omir | Own | ZB WHe Jum he rm = it o ‘Symbol | condition [in| max {min | max| min] max. ue 7 | Ghock High to Addr, Data Bur 1 High Impedance ounce =| | - | 70| -| 0] 78 | Giock High 10 Coniral Bus igh Tmpedance | once =e = [70] = eo 33_| Clock High to 8G Low tonce = [70 |= [eo] — [soos] 34_| Clock High to BG High enon | =| v|- | sol | sof ns = Bons yg | Ore «| 7 35 | BR Low to BG Low TRLGL 18] 436/15 [43.5] 15] 43.5 [0 Pee 361 | BR High 10 5G High tenvan 1.5] S08 15 | 800 1.5] 7 tton Pee —— Fin. 7~ [py] 90n4| 5 | Bom 9 g| 70m 37 | BORCK Low 19 BG High voncon| Fit 2~ [15 | Poet] | fe) 1s | hou 7a? | BGACK Low to BF Han ‘oacenn 20 jel} 20 foesey 20 fated G8 | BE Low to Conirol, Adare, Di " _| “Bus High impedance (AS High) tar = 1% {= |] - |e) s | BE wie Hi ‘on 48] — [v5] - [78] — Joo 48_| BGACK Wish Low oat 15] - [15] - [15] — fewer 47 Asynchronour Input Stop Time ‘asi 20[-- [20 [=] 20[— | mw 87_| BGACK High to Control Bus tcaso | vs] — [rs [— [15] = lox rer 58’ | BG High to Contro! Bus Driven tGHBD. ws] = [rs] - [15 = few Pe NOTES: 1. The processor wil noate BG and bein driving the bu atin textrnlabitation logic neptes BA bate anetng BGRER. 2. The minimum value ust be met to gutrante Broper operation. the maximum values excnded, BE may be reauerted, @HITACHI 918 Hitachi America, Lt. © Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 » (45) 589-8300HD68000/HD68HC000 Figures 7, 8, and9 depict the thre bus arbitration cases th ‘ean ae. Figue 7 show the ting where AS is negated when the procesor asserts BG (ldle Bus Case). Figure 8 shows the timing where AS i aserted when the procesor aserts BC (ete Bus Cas). Figure 9 shows the ting where more than fone bus master are requesting the bus. Refer to Bus Arbitration fors complete dscuson of bus ux ‘The waveforms shown in Figures 7, 8, and 9 should only be referenced in regard to the edge-toedge measurement of the ‘ming specifications. They are not intended as a functional ‘description of the input and output signals. Refer to other func- tional desceiptions and their related diagrams for device opera- Won, m a0 = roava68 “ om 1 — am 4, Aika o-Ps Figure 7, Bus Arbiteation Timing Diagram ~ Idle Bus Case @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 (415) 589-8300 919HD68000/HD68HC000 AYN nae an Ey Figure 9. Bus Arbitration Timing Diagram — Multiple Bus Requests @ HITACHI 920 Hitachi America, Ltd, « Hitachi Plaza + 2000 Sera Point Phwy. «Brisbane, CA 94006-1819» (415) 589-8300= INTRODUCTION AAs shown inthe programming model, the 68000 offers seven teen 32-bit registers in addition to the’32-bit program counter ‘and a 16-bit status register. Th first eight registers (DO ~ D7) are used as data registers for byte (B-it), word (16-it), and long word (32-bit) data operations. The second set of seven regaters (AO ~ A6) and the system stack pointer may be used ar toftware stack pointers and base address registers. In addi- ton, these registers may be used for word and long word ‘address operations. All 17 registers may be used as index regs- te. “The status register contains the interrupt mask (eight levels, avaiable) as well as the condition codes; extend (X), negative (S), zero (2), overflow (V), and cary (C). Additional status bits indicate that the processor is in a trace (T) mode andjor Ina supervisor (S) sate Status Register User Byte System Byte IConaition Gade Register) ERS 38 aya ULEESSP PERT aS Extend Trace Mode cary Unused, read as 200 ‘© DATA TYPES AND ADDRESSING MODES Five basic data types are supported, These data types ae: Q) Bits (2) BCD Digits (4 bits) G) Bytes (bits) (4) Word (16 bits) (3) Long Words (32 bits) In addition, operations on other data types such as memory address, status word data, etc, are provided for in the instruc tion set ‘The 14 addressing modes, shown in Table I basic types: (0) Register Direct (2) Register Indirect Q) Absolute Immediate (S) Program Counter Relative (6) Implied Inclided in the register indiect addressing modes is the capar billty to do postincrementing, predecrementing, offsetting and indexing, Program counter telative mode can also be modified indexing and offsetting includes six HD68000/HD68HC000 Programming Model a 1618 ar 9 oo Sack Powe Coonte a same sritem Sve? Uwe ove Loe eset Direct Adéreming Ont Repiter Direct ‘Asians Regier Direct ‘Abwolute Orta Addresing AAbrlute Short ‘Absolute Long 2 rogram Countar Relative Addroming Retative with Oe Imlied Raiser Wworesr EA = Effective Address ‘An = Adve Ragiater (On = Dae Register Xn = Addree oF Date Raper used fs Index Ropister SSR = Stat Regier PC = Program Counter 1 }= Contents of = Eight bit Offer [asplacement @HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300 921 1 Addressing Modes Generation EA= (Next Word) EA= (Next Two Words) _ EAS IAN) EA IAN An An +N Anon = N EAs Ian} EAT (and + EAT (An) + (ka) +e DATA = Next Wordls) dis Sixtanit Otte (aiptacement) N= Hor Byte. 2 for Words and & for Long Sze iryte, Ne? to heeHD68000/HD68HC000 # instruction ser ovERviEw ‘The 68000 inaction set is shown in Table 2. Some ad sonal mtn evr, o mr of than a topeat in Table 3. Spec emphasis been giren tothe n- Stott sts support of strvetued hgh evel languages ofc tate ease of propamming, Each lstucion, wth few excep. tions, operates on byes, wordt, and loeg words and mox instructions can use any of the 14 addressing modes. Combining {instruction types, data types, and addressing modes, over 1000 ‘useful instructions are provided. These instructions include signed and unsigned multiply and divide, “quick” arithmetic ‘operations, BCD arithmetic and expanded operations (through traps). Table 2 Instruction Set Tran Dacian Tireran Darton "A065 | Aad Oacne wih Exand “COR Excamnn Or Sr oo Exo | Excnenge Regt a RESET | Reet Exar Devine ano Ext_| Syn eums ROL | Rome Lernout Eon ee Ron | Rosnte Reh without Exon ash ‘Aorta BR ‘sump to Subroutine ince all [nae Cote eee Bee] tare Coniinaly tex | Cont tects Aras Roxr | Rove Rant Exon Bec et a Caner tink | tnt sce re | Rasa rom Cncepuon peur Tat nd Cn ue Lees Sit Lat fre | Ruwrnand rece saa | ranch Anas tsa pit Sie at frs___| Rawin rom Suan hie ‘MOVE ‘Move ‘s8cD ‘Subtract Decimal with Extend Ld een MOVEM ‘Move Multiole Registers: Sec ‘Set Conditional r__| over | Nowereconara Oxte Soe | Ste eax MULs | Sons tutty sue | Suteact cur mut swar | Snap Dae Rag — | compere _____ “waco TAS ‘Test and Set Operand D8ce | To Condon, Sasaman'and” NEG tase To rach Nor | trary | Yowon Onion cows | staned Oviae nor 337 tm Dive | Unoores Ome ne ae Table 3 Variations of Insrvetion Typet Deseinton tempvevon | Veraion Desertion 75 700 aaa wove [wove Tow Boon | Add rae MOVER | ove Adc tooo | Aatowee movea | Mow Owck oor | ne MOVE trom SR | Move tom Stats Rainer foox __| Aaa win Een MOVE tosh | Move to Sena Repatr aa ano gies MOVE to CCA_| Move to Condon Coes ae pez iomoaie MOVE Us| More Ur Sch ome ‘AND! 0.CoR | And immer 0 me NEG Neate Gonditon Cade NEGx __| Nap with Extn ANDIo sR on on oma! Or on Ortaca | compare Adorn Canaan Son caer oniiesn | Srimmets ea setae we a Seva fontrecen | Exstuie or iimasate suet Sect nga Sun Sutwect ook cont ose suex Scaoct on ton i @HITACHI 922 Hitachi America, Ltd. « Hitachi Piaza # 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 + (415) 589-8300HD68000/HD68HC000 = REGISTER DESCRIPTION ANO DATA ORGANIZATION ‘The following paragraphs describe the registers and data organization of the 68000. © OPERAND SIZE Operand sizes are defined 25 follows: a byte equals & bits, ‘a word equals 16 bits, and a long word equals 32 bits. The ‘operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction ‘operation, Impliet instructions support some subset of all three ‘¢ DATA ORGANIZATION IN REGISTERS ‘The eight data registers support data operands of 1,8, 16, cor 32 bits. The seven uddress registers together with the active sack pointer support address operands of 32 bits DATA REGISTERS Each data register i¢ 32 bits wide. Byte operands occupy the low order & bits, word operands the low order 16 bits. and long word operands the entte 32 bits. The least significant bit, is addressed as Bit zero; the most significant bit is addressed asbit 31 ‘When a data register is used as cither a source or destination ‘operand, only the appropriate low-order portion is changed: the remaining high-order portion is neither used nor changed. byw FFEFEE ADDRESS REGISTERS teach address repster and the stack pointer is 32 bits wide and holds a full 32 bit address. Address registers do not support byte sized operands. Therefore, when an address register is used a8 4 source operand, either the low order word or the entire long word operand is used depending upon the operation size. When an addres register is used asthe destination operand, the entire register is affected regardless of the operation siz. If the ‘operation size is word, any other operands are sign extended 10.32 bits before the operation is performed. ‘© DATA ORGANIZATION IN MEMORY Bytes are individually addressable with the high order byte having. an even address the same as the word. as shown in Figure 10. The low order byte has an odd address that is one ‘count higher than the word address. Instructions and multibyte data are accessed only on word (even byte) boundaries. If a long word datum is located at address n(n even), then the second word of that datum is located at address n + 2, ‘The data types supported by the 68000 are: bit data, integer data of 8, 16, or 32 bits, 32-bit addresses and binary coded ecimal data. Each of these data types is put in memory, as shown in Figure 11. The numbers indicate the order in which the dita would be accessed from the processor. Ward FFFFFE yt FEFEEE, Figure 10 Word Organization in Memory @HITACHI Hitachi America, Ltd. © Hitachi Plaza # 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 * (415) 589-8300 923HD68000/HD68HC000 2 Bre? 08 1 Word = 168 9 2 oe 8 7 6 6 4 3 2 * Woda an Wort oa Wo? os 1 Lone Word 32 Bie is 3 2 wo 9 67 eee gees geet eel noe igh Order mt nent nt nea ‘Low Order a so] a “ 2 Binary Coded Decimal Dit = 1 By ip yp fo 8b ee 10 n {MSO aco scot mt so] 802 2 od ac08 acoe [econ ws NSD> Hon Sonia USO: Cea Samtieane Ose Figure 11 Data Organization in Memory @HITACHI 924 Hitachi America, Ltd, « Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 + (415) 589-8900ee © ADDRESSING Instructions forthe 68000 contain two kinds of information: the type of function to be performed, and the location of the ‘operand(s) on which to perform that function. The methods ted to locate (address) the operand(s) are explained in the following paragraphs. Instructions specify an operand location in one of three ways: Register Specification — the number of the register is given in the register field of the instruction. Effective Address — use of the different effective address modes. Implicit Reference — the definition of certain instructions Implies the use of specifi registers. © INSTRUCTION FORMAT Instructions are from one to five words in length, a8 shown in Figure 12. The length of the instruction and the operation to be performed is specified by the first word ofthe instruction ‘which is called the operation word. The remaining words further specify the operands. These words are either immediate ‘operands or extensions to the effective address mode specified in the operation word. © PROGRAM/DATA REFERENCES ‘The 68000 separates memory references into two classes: rogram references, and data references. Program references, as ‘the name implies, are references to that section of memory HD68000/HD68HC000 ‘contains the program being executed. Data references refer to that section of memory that contains data. Operand reads are from the data space except in the ease of the program counter telative addressing mode. All operand writes are to the data space. ‘© REGISTER SPECIFICATION ‘The register field within an instruction specifies the register to be used, Other fields within the instruction specify whether the register selected is an address or data register and how the register is to be used. © EFFECTIVE ADDRESS Most instructions specify the location of an operand by using the effective address field in the operation word. For example, Figure 13 shows the general format ofthe single effective address instruction ‘operation word. The effective address is composed of two 3.bit fields: the mode field, and the cegister field. The value in the mode field selects the different address modes. The register field contains the number ofa register. "The effective address field may require additional informa tion to fully specify the operand. This additional information, called the effective address extension, is contained in the following word or words and is considered part of the instruc: tion, as shown in Figure 12. The effective address modes are grouped into three categories: register direct, memory address: ing, and special “ ) 0 9 26 Ect Aaron Mode Rosier persion Word {en Word Specifies Operation and Modes) Trane Oprend {11 Amp, Ora or Two Word) ouroeettectve Adc Extension [W Any, One or Two Wore ree Figure 12_tnstruetion Form fauet jeter Figure 13. Single-Etfective-Address Instruction Operation Word General Format @ HITACHI Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-8300 925HD68000/HD68HC000 REGISTER DIRECT MODES ‘These effective addressing modes specify that the operand {sin one ofthe 16 multifunction registers. Date Repister Direct ‘The operand is in the data register specified by the effective ‘address register field. exaneus comments MPU MEMORY eee — Move a4, 8201000 311 901114001100 oto tee aes Fara ———— Word Absohare maare com{ see regi oo ‘ome +2[ 00201 a rove aa sz0r000 ON? 2} 0020 ——~_ @HITACHI 926 Hitachi America, Ltd. « Hitechi Plaza # 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300HD68000/HD68HC000 exaune comments we wewony 2 Seacat nai sgn exanses shee ect =] MOVE $201000, A4 szoro00| a0 ou on pos ——_~_— - 4 Wort rod ad Long E—~ 3 Aeoater — ote om [378 wove s2otcea,aa owt +3[ 9020 om +4[ 1000 ——_- MEMORY ADDRESS MODES ‘Adres Raga indict Thee effective addreming modes specify that the operand The adress ofthe operand isin the adres citer speciied isin memory and provide the specific addres ofthe operand. by the repster (eld, The reference is clasified a8 a data refer tence with the exception of the jump and jump to subroutine instructions. exuanwur comments meu mewonY eae 4 co + Machin Lat Cding ce =—— MOVE (401, 90 2211 9900 coor como Toe rs — Med | Bae |” eae ores om [3510 we ove 101,00 tech —_- @HITACHI Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 927HD68000/HD68HC000 ‘Address Register Indirect With Postinerement The address of the operand i in the addres register specified by the repister field. After the operand address is used, it is incremented by one, two, or four depending upon whether address register is the stack pointer and the operand size is the size of the operand is byte, word, or long word. If the (oop) a MovE 164) +.$2000 ‘Address Register Indirect With Predecrement The address of the operand is in the addres register specified by the register field. Before the operand address is used, itis decremented by one, two, ot four depending upon whether byte, the address is incremented by two rather than one to keep the stack pointer on a word boundary. The reference is iid shee sesny ea ae Gotan —~— ‘Sect mene a bates peers Ee ) “Neves ane cots ene ee ae awn p= St a om [ae oes ——~__ ceteris pine and te operand ie byt te the operand size is byte, word, or long word. If the address Move ~ (421,$4000 928 exams address is decremented by two rather than one to keep the sack pointer on a word boundary. The reference is classified asa data reference CcommeNTS An Mme Ans €A = (Aol eMony Vat An Ad ptr —~— ere soore| 1334 Long Word a ‘+ Macine vt Song FT ) wove — 031, 24000 oT 11 20011110 eof a Nod asi om [are ra com. +2[ ate cea @HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94008-1819 « (415) 589-8300HD68000/HD68HC000 ‘Addrass Regleter Indirect With Displacement register and the sign-extended 16-bit displacement integer in "This sduress mode requires one word of extension. The ad- the extension word. The reference is classified at a data refet~ dress of the operand is the sum of the address in the address ence with the exception ofthe jump to subroutine instructions xan COMMENTS meu mewory Where An t=-Pointer Raper EZ 18BW Dimtocemant #5 Onpincement Sin Extended sisi area 1100] Ae ove 109140), 9000 EF) ne yop ae oT wae | es — Re s2000[ A865 ey er awe move £10080, $9999 yy | ace Aooness rslaton BROEEaion, Ome +2[ ore SBGUEATON ow, val 3000 2: Seanovo9 b—~_J ‘Address Rage Indret With Index ight bits of the extension word, and the contents ofthe index ‘This eddress mode requites one word of extension. The register. The reference isclasified as a data reference with the ‘address of the operand is the sum of the address in the address exception of the jump and jump to subroutine instructions. register, the aignextended displacement integer in the low order pawns comments Sencar Rt wu memory te Rr —> Donates Indes Register, Cc oa4 (Either Address Register or 10005 ——_~-_— = |# Machine Level Codi ‘s4BE0) TS "a Move 804140, 00), $1000 —_ ~~ Rey #0 MOVE S041A0,001, ys ae ow om. ‘000 te 00000100 “ADDRESS: sal 7 EREEGE on wea} obs ‘ho = cocoa Cana Fak 50 2 Seonzsec 2 eobon a coaDH8O @ HITACHI Hitachi America, Ltd. Hitachi Plaza © 2000 Sierra Point Pkwy. + Brisbane, CA 94005-1819 » (415) 589-8300 929HD68000/HD68HC000 ‘SPECIAL ADDRESS MODE ‘Absolute Short Addren ‘The special address modes use the effective address register This address mode requires one word of extension, The ad: fleld to specify the special addressing mode instead ofa register dress of the operand is the extension word. The 16dit address ‘number. is sign extended before it i used. The reference is classified as a data reference with the exception of the jump and jump to subroutine instructions. ‘COMMENTS EA Next Mord) neu Memory 6s Warde Sion Extended 1+ Macon Level Coding NOT. $2000 1000110 10111000 rE Nariaracon| Wor $2000 comments wey mewony Besar Sgn Exantes ~~ eae a |# Machine Level Coing, yO. ees fecaeria gout ooo) 11111000 fm Rosohate ——~-_ Abril a ou Es MOVE $1000, $2000 owe aire om. +2[ 1000 ‘om. +4[ 2000 a @HITACHI 930 Hitachi America, Ltd, » Hitachi Plaza © 2000 Sierra Point Pkwy. Brisbane, CA 94006-1819 » (415) 589-8300HD68000/HD68HC000 ‘Absolute Long Address first extension word; the low-order part of the address is the "This address mode requires two words of extension, The second extension word. The reference is classified as a data ‘address of the operand is developed by the concatenation of reference with the exception of the jump and jump to sub- the extension words. The highorder part of the address is the routine instructions. ‘coMMENTS (EA Next Two Worst! eu Memory —~_, asst teem eee 1 Machine Level Coding ee NEG $014000 aree_gjon gag neg Roiotae -—~_J Tiatuction Lona om [a8 NEG so14000 oms2 [ot com +4 [4000 -—~_J Progeam Counter With Displacement the extension word. The value in the program counter is the ad “Thus address. mode requires one word of extension. The dress of the extension word. The reference is clasified as a pro: address of the operand isthe sum ofthe address inthe program gram reference counter and the tignextended 16-bit displacement integer in exam comments Seas el td www memory Bat San Extees Shia Code Cc ‘MOVE (LABEL). 00 ERRKASCD) 00 ——a) 11 909099111010 ao TL ‘$8000 2034 ey ee Coca soe | ae SS ——~— Move \LABELI.00 oonese enteuearion rena A= 20001000. Ape > Psa] 000002 9002 | asco — @HITACHI Hitachi America, Ltd. © Hitachi Plaza» 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (418) 569-6300 931HD68000/HD68HC000 Program Counter With Index ‘This address mode requires one word of extension. Thit ‘address is the sum of the address in the program counter, the signextended displacement integer in the lower eight bits of the extension word, and the contents of the index restr. ‘The value in the program counter is the address ofthe extension word. Ths reference is classified asa program reference A= PC) + IR + ce (ore) Pc Value | —Tonraeton Extension Word msg wee ro sine [wie] o To To] Oipicamant cep A&irarat | pe +a. — D/A Date Regier = 0, Acres Raper’ Sate abe Regitr Index Derwe Oat dec +a: + Ax —ef seat in able long Word nde Ragnar = 1 ors noon —~__ examne comments Seas cl +(e) 6s wou memory te = care regram Counter _ -—~_, Fix Banged nes Rep (Ein Rae ee) EEEEo0 | ——se000 [338 a nxtna gene bon ended s2002| e010 IR ye Wer bony Wana BaaaTETG]AD (ong Word Berge wa a eae (# Machine Level Coding ———, MOVE (LABEL) (A), 00, | ‘Sseora qo11 coop cors_1011 Perea > — rear ora MOVE (LABEL) (A000 4090 9000 001 seontes onpsme—| gal [P linen BREE rons Roce | b= Bogota Ames | Comer zee ~9.= 00000010 index Tanah ‘000022 ~~ @HITACHI 932 Hitachi America, Ltd, « Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-6300HD68000/HD68HC000 Imeediate Date Extension Word ‘This address mode requires either one or two words of ex: ‘tension depending on the size of the operation. A Byte sprain — operand i Tow order yt of extention ooo o0000; aye ‘Word operation ~ operand is extension word is o___) [tong word operation — operand is in the two extension c= ‘words, high-order 16 bits are in the first extension word, low-order 16 bits are inthe second extension word. XAMPLE ‘commens fSOate = Hose Words) eu memory oon or at er + Mate Lal Coins oan ee Nove #81000, 40 ——_—— + ep 00 ane om aor MOVE #81000, AO oon 1000 ———— ames conments wu menor 0 Long Word Machine Level Cosine (20000054) 03 MOVEG #$54, 03 a. ayn 931g o10r_s010 Cc fag 3 Fixed immediate aie tee Gn ore om [788 ovEa HSSA, 00 -~ @HITACHI Hitachi America, Ltd. « Hitachi Paza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 889-600 933HD68000/HD68HC000 Condition Codes or Status Register A selected set of instructions may reference the status regi ter by means ofthe effective address Feld. These are aiorceR ANDI eSk fonrioccR tonto sk eae counanrs ORCER apy wenony TES a ORI to SR Anatruction oe Move cc San MOvE roe morta MOVE fk cen wove si se i c= “ie be eee om[ “ae MOVE $1020, sR Ome? 1029. + errecrive ADORE ENCODING suMMaRy sack pin (SP) th esac pier (USP) othe sat Tale ir sary ofthe elective addesng odes di tepiter (R). costed inthe previous areaph svsrew stack The system sack is ssed imply by many isustios user acs and quate maybe cated and manned trou’ the addreang modes, Address eter even (AT) the system [ —Reoiner stack pointe (SP. The system snk porter weiter te sper Register Direct | 000 _[ register number ___visor stack pointer (SSP) or the user stack pointer (USP), de- Address Register Direct 001 | register number pending on the state of the S-bit in the status register. If the ie ae venster omper~ Sto ndcate supervisor state, SSP isthe ache ter sack Aeteres Register ingest __7_010 eae meet pointer, and the USP cannot be referenced as an address re- Adds Rages incest wth 9x5 | caine umber per if the Stitindats wer sat, the USP the ste Table 4 Effective Address Encoding Summary ‘Aairessing Mode Mode _|__ Register + a system stack pointer, and the SSP cannot be referenced. Each 100. | vegister number _8¥8tem stack fils from high memory to low memory. 101 | register number SYSTEM STACK POINTERS : : Ue Stack Supervisor Stack 110 | register number a” ar Abolute Long Program Counter with Diplacement Program Counter with usp See. . Tromeate af 100 1 Acenad wren 5-0 * Acoma an 51 ‘ren sucaed on stew sucied on © INPLICIT REFERENCE eee Sateen oto Some instructions make implicit reference to the program use neees counter (PC), the system stack pointer (SP), the supervisor * Ineraosing Addresses Procesing @uHiTacu 934 Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300HD68000/HD68HC000 “The address mode SP@- creates a new item on the active system stack, and the address mode SP @+ deletes an item from the active system stack. “The program counter is saved on the active system stack on subroutine calls, and restored from the active system stack on returns. On the other hand, both the program counter and the status register are saved on the supervisor stack during the processing of traps and interrupts. Thus, the correct execution ‘Of the supervisor state code is not dependent on the behavior ‘of user code and user programs may use the user stack pointer arbitrarily. In order to keep data on the system stack aligned properly, data entry on the stack is restricted so that data is always put in the stack on a word boundary. Thus byte data is pushed on ft piled from the system stack in the high order half of the ‘word; the lower haf is unchanged. USER STACKS ‘User stacks can be implemented and manipulated by employ- ing. the address register indirect with postincrement and pre Gecrement addressing modes. Using an address register (on of ‘AO through A6), the user may implement stacks which are filled cither from high memory t0 low memory, or vice verse. The important things to remember are: Povsing predecrement, the register is decremented before its contents are used asthe pointer into the stack, = using postincrement, the register is incremented after its ‘contents are used as the pointer into the stack, ~ byte data must be put on the stack in pairs when mixed with word or long data so that the stack will not get Imisaligned when the data is retrieved, Word and long. accesses must be on word boundary (even) addresses. Stack growth from high to low memory is implemented with ‘An 2- to push data on the stack, ‘An@+ to pull data from the stack ‘After eigher 2 push or a pull oper ‘the last (Kop) item onthe stack. This is ilustrated as: re) Stack growth from low to high memory is implemented with ‘An to push data on the stack, ‘An@- to pull data from the stack [After either push or a pull operation, register An points to the next available space on the stack, This slustrated as: Z B Zz ‘queues ‘User queves can be implemented and manipulated with the address register indirect with postincrement or predecrement addressing, modes. Using a pait of address registers (two of AO through A6), the user may implement queves which are filled tither from high memory to low memory, or vie versa. Because {queues are pushed from one end and pulled from the other. two Tepsters ae used: the put and get pointes. ‘Queve growth from low to high memory is implemented with ‘Apute to put data into the queue ‘Aget@' to get data from the queue After a put operation, the put address register points to the next avilable space in the queve and the unchanged get address fegister points to the next item to remove from the queue ‘After a get operation, the get addres register points 0 the next ‘tem to remove from the queue and the unchanged put uddress register points to the next available space in the queue, This illusteated as ete cent ou ree) ih memory If the queve is to be implemented as a citcular buffer the address repiser should be checked and, if necessary, adjusted before the put or get operation is performed, The address regis- ter is adjusted by subtracting the buffer length (in bytes). Queve growth from high to low memory is implemented with ‘Apul@- to put data into the queue. ‘ApetG ~to get data from the queve. After a put operation, the put address register points to the last item put in the queve, and the unchanged get address register points to the last item removed from the queue. After a jet operation, the get address register points to the last item emoved from the queue and the unchanged put addres register points tothe last tem put in the queue. This is illustrated as: @HITACHI Hitachi America, Ltd, © Hitachi Plaza © 2000 Sierra Point Pray. * Brisbane, CA 94005-1819 + (415) 589-8300 935HD68000/HD68HC000 link stack (LINK), unlink stack (UNLK), and move quick few marwory (MOVEQ). Table 5 is a summary of the data movement a operations poe tate Table 5 Date Movernent Operations 5 Thsvroction | Operand Sie ‘Operation Z : exc 32 Fx Ry venige LEA 2 EA>An An >) Age se ee unk S (Bran fe Seep wn memory Move | 816,32 | (EAn=>EAd wove ea IF the queue isto be implemented 484 ciculr buffer, the mover (EA) Dr et or put operation should be performed fis, and then the dress register should be checked and. if nccesiry. adjusted MOVEO ex Da The addves register is adjusted by adding the buller length PEA EA =—ISP) lin bytes) ‘SWAP (n{31:16) = Dnl16:0] ‘SINSTRUCTION SET SUMMARY UNLK f= (ea The following paregraphs contain an overview of the fom = ——————L | and structure of the 68000 mstuction set The insrctions —(woTES) form a set of fools that include all the machine functions to toute 1 ingame perform the following operations: Data Movernent Integer Arithmetic Logical Shift and Rotate Bit Manipulation Binary Coded Decimal Program Control ‘System Control ‘The complete range of instruction capabilities combined with the flexible addressing modes described previously pro vide a very flexible base for program development. (© DATA MOVEMENT OPERATIONS ‘The basic method of data acquisition (transfer and storage) 's provided by the move (MOVE) instruction. The move instruc: tion and the effective addressing modes allow both address ‘and data_manipulation. Data move instructions allow byte ‘word, and long word operands to be transfered from memory to memory, memory to register, register to memory, and regis: ter to memory, and register to register, Address move instruc tions allow word and long word operand transfers and ensure ‘that only legal address manipulations are executed. In addition to the general move instruction there are several special data movement instructions: move multiple registers (MOVEM), move peripheral data (MOVEP), exchange registers (EXG), oad effective addres (LEA), push effective address (PEA), ‘of add (ADD), subtract (SUB), multiply (MUL), and divide (DIV) as well as arithmetic compare (CMP), clear (CLR), and negate (NEG). The add and subtract instructions are available wats See So ea See ee Serra are tens oe eerie Seta abe nn a ats a Tecate wm add extended (ADDX), subtract extended (SUBX), sign extend @HITACHI 936 Hitachi America, Ltd. « Hitachi Plaza + 2000 Sierra Point wy.» Brisbane, CA 94005-1819 « (415) 589-8900Table 6 Integer Arithmetic Operations HD68000/HD68HC000 shift and rotate operations can be performed in either resisters ‘ot memory. Register shifts and rotates support all operand ‘Seeaton Siees and allow shift count specified in the instruction of Baia or One to eight bits or O 1063 specified in a data register avon en Cee Sifts tnd rotates are for word operands only and Sn ieas An allow only singe-bit shifts or rotates, Table 8 is a summary Dx+ yo X= Ox Of the shift and rotate operations. Sinaloa eK AS) Table 8 Shift and Rotate Operations inncton bowed See Oonaion inviea! a ast sr62 | oc}e{=——o OnieAl=On * 7 =o om Pa A Cr ee] 7 =1¢ | (Drie Dns ust ee — ex Yer'32 | tOnlw Do» pe — ais —| Torts = 2 | orx(€al = On (sR uty [163639 | OnslEA= Dn — 4 NEG O-(EAI>EA, Rot NEGK 0-A)-X-fA mon or EA~D: (ex) sn 2a sue | TEA ian ea Oxt Arvin) an ae 7 ROXR suex = ant Ta a 1st 316.32 ‘© GIT MANIPULATION OPERATIONS (WOTEY 1 1=bitnamber Bit manipulation operations. ate accomplished using the =) ie ith predecerant FZ earet with postnrement (+L imedinte dete © LOGICAL OPERATIONS Logical operation instructions AND, OR. EOR. and NOT ate available for all sizes of integer data operands, A similar Sct of immediate instructions (ANDI, ORI, and EORD) provide following instructions: bit test (BTST). bit test and set (BSET), bit test and cleat (BCLR). and bit test and change (BCHG). Table 9 is a summary of the bit manipulation operations (Bit 2 of the status register isZ_) Table 9 Bit Manipulation Operations these logical operations with all sizes of immediate data, Table a Seacend Sie ee Tis.a summary of the logical operations. — ee — er eecreae Table 7 Losical Onerations aan - ~ bit ot EAI= c : (rbreren Tranige | Soom oe von Sore aE DraleAl— Om 7 a bit of (EA) ~ bit of EA ano erst | teanonen noe el Se) «BINARY CODED DECIMAL OPERATIONS ae Multiprecision arithmetic operations on binary coded deci- imal numbers are accomplished using the fllowing instructions add decimal with extend (ABCD), subtract decimal with extend {SBCD), and negate decimal with extend (NBCD). Table 10 is ' summary of the binary coded decimal operation. NOTE => oe 5 Table 10 Binty Coded Dect Operation AD iogesta 1 ekenw OR Trovcion | Oprang Sa ‘pean eco ® ‘SHIFT AND ROTATE OPERATIONS : Shit operations in both ditections are provided by the ~sgep : Or. arithmeuie istractions ASR and ASL and logical shift instr: Piha ane UM Tons ESR and CSL. The rotate inseucions (wath and without “WHO z O-ltalg-X > A extend) avaiable are ROXR, ROXL, ROR. and ROL. All a @HITACHI Hitachi America, Ltd. « Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 937HD68000/HD68HC000 ‘© PROGRAM CONTROL OPERATIONS. Program control operations are accomplished using a series of conditional and unconditional branch instructions and return instructions, These instructions are summarized in Table 11 ‘The conditional instructions provide setting and branching forthe following conditions: CC — carry lear LS — low or same CS — carry set LT — less than EQ — equal MI — minus F— never true NE — not equal GE ~ greater or equal PL — plus GT ~ greater than T. — always true HI — high VC — no overflow LE — tess or equal VS ~ overflow ‘Table 11. Program Control Operations Tevucton Opener Condition Bee Branch condtionaly (14 con snd 160i olsen D8ce Test condition, decrement nd branch ait dnlacoment Sec Setbyte cancion (16 contions ‘Uneondivonsl Ra Branch aways sn ‘Band 16 daolacement rd ame m4 ump 10 suoroutin Rewrna — ars Return trom mbrouting ‘© SYSTEM CONTROL OPERATIONS System control operations are accomplished by using priv leged instructions, trap generating instructions, and instructions that use or modify the status register. These instructions are summarized in Table 12 Table 12 System Control Operations Teatucton Dewston Prope Reser eae exter devices stor MOVE USP | Move uae sack points ANDI 0 SR Logit AND totus rgater ORI to SR Logie! EOR to statu eter MOVE EAtOSR | Lewd new satu ‘Trap Geneeting TRAP Ta TRAP ‘rap on overtow __cnx Check rape apne bounds ‘Sans ene ANDItO CCR — | Lopicl AND to condition coat ORI to COR opie! EOR to conation codes MOVE EA10.CCR | Lond new condition cde onto cor © BRANCH INSTRUCTION ADDRESSING BRANCH INSTRUCTION FORMAT Operation Word Extention Word RELATIVE, FORWARD REFERENCE, B8IT OFFSET examen comments 1 Stet Contained in 8 L588 ot Op Word neu memory 2 Site ee omotamene hance, SM Ota «Osman word Ofer Ud Machine Cover Coane 9E0. NeXT = 2110 0111 oo01 1110 sie ——_ ss000| erie a) oe aoe 8020 [wen OP Code Pc+2~ S002 Eercitd 020 r—~_ J @HITACHI 938 Hitachi America, Ltd, « Hitachi Plaza © 2000 Sierra Point Phy, « Brisbane, CA 94005-1819 « (415) 589.8300HD68000/HD68HC000 RELATIVE, BACKWARD REFERENCE 8.8IT OFFSET AML comMENTS = Otten Containes in 8 L505 neu Memory ot Sp Wore 1 Stee 74 Comptmant Number Te Stet iene Others Une (¢ Machine Level Coding ONE NeXT a) ope aye oe ‘4000 | “ext OF Code Samar Nor Eaue! Fay | NE NEXT i c+ 2 = 402 FOE ‘000 -—~_J RELATIVE, FORWARD REFERENCE, 16-817 OFFSET examine comments tte en Word eu mewony en ofa Fo Someta Ott techn Cv Coin ‘oc NeXT | je Spe ame —— wasn | we = Branch ‘ooo [6200 Gary ewe ‘0a | van ce next 8002 “Rent OF ose c+2 = 4002 3278008 on? -—™_ @HITACHI Hitachi America, Ltd, « Hitachi Plaza » 2000 Sierra Point Pkwy, « Brisbane, CA 94006-1819 « (415) 889-8300 939HD68000/HD68HC000 = SIGNAL AND BUS OPERATION DESCRIPTION ‘The following paragraphs contain a brief description of the input and output signals. A discussion of bus operation during ‘the various machine cycles and operations is alo given, (NOTH The teams amartion and oaprtion wil be used extent This is done Tp avo confston when desling with 4 mintare of "acinedow” and "acive nigh” signals The term ser oF Sssertion Ws used fo indiate that a sma ative Or te Aependent of whether that voltage felow or high. The tem ‘eget or nepavon is sed to inieate tats iat iat a ‘he ¢ SIGNAL DESCRIPTION The input and output signals can be functionally organized into the groups shown in Figure 14. The following paragraphs provide a brief description of the signals and also a reference (GF applicable) to other paragraphs that contain more detail about the function being performed, Vasco Ahn ate EB 0,0, 7 fe FRE) ssycrronous woesco (=e FEES vincton Soon aq ES Cone SB) RS xr Figure 14 Input and Output Signals ADDRESS BUS (A: through Ars) This 23-bit, unidirectional, thteestate bus is capable of addressing 8 megawords of data, It provides the address for bus operation during all cycles except interrupt cycles. During imterrupt cycles, addeess lines Ax, Az, and As. Provide infor ‘mation about what level interrupt i being serviced while addvess lines Ae through Aaa are all set toa logic high DATA BUS (De through Dis} This. 16: threestate bus is the general purpose data path. It can transfer and accept data in either word or byte length, During an interrupt acknowledge cycle. an external device supplies the vector number on data lines De through D> ASYNCHRONOUS BUS CONTROL ‘Asynchrofious data transfer are handled using the following control signals: address strobe, read/write, upper and lower ata strobes, and data transfer acknowledge. These signals explained inthe following paragraphs, ‘Address Strobe (A8) ‘This signal indicates that there is a valid address on the address bus. Rend Mite (8/0) This signal defines the data bus transfer as a read or weite cycle. The RY/W signal also works in conjunction withthe upper and lower data strobes as explained inthe following paragtaph, Upper and Lower Data Strobes (UDS, LOS) ‘These signals control the data on the data bus, as shown, in Table 13. When the R/W line is high, the processor will read from the data bus as indicated. When the R/W line is low, the processor will write tothe data bus as shown, ‘Table 13 Data Strobe Control of Data Bus oo wos | ts Hi High, Valid data bits 7 Vaid di ie “tom ton on | ei oH Hin | Low | High | Movad data | Vaid data its | Valid date bits Low | High — ign | Vale dee No valid data Valid data bits | Valid data bite Low Low Low Vali data oH Low | Valid data bits | Vatid data bits o~7" 0 TValia Valid data, Low | High | Low | Valid data on Data Transfer Acknowledge (OTACK) his input indicates that the data transfer is completed When the provessor recognizes DTACK during 9 read ¢ uta is latched and the bus eycle terminated. When DTA 's recognized during a write cycle, the bus ycle is terminated. (Refer to ASYNCHRONOUS VERSUS SYNCHRONOUS Of ERATION) BUS ARBITRATION CONTROL ‘These three signals form a bus arbitration circuit to dete ‘mine which device wil be the bus master device, Bus Request (BR) This input is wite ORed with all other devices that could bbe bus masters. This input indicates to the processor that some other device desires to become the bus master. Bus Grént (86) ‘This output indicates 10 all other potential bus master devices that the processor will release bus control at the end of the current bus oycle, Bus Grand Acknowledge (BGACK) This input indicates that some other device has become the bus master. This signal cannot be asserted until the following four conditions are met (1) A Bus Grant has been received (2) Address Strobe is inactive which indicates that the microprocessor is not using the bus (3) Datu Transfer Acknowledge is inactive which indicates @HITACHI 940 Hitachi America, Ltd « Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94006-1819 « (415) 589-8900that nether memory nor peripherals are using the bus (4) Bus Grant Acknowledge is inactive which indicates that no other device is stil claiming bus mastership INTERRUPT CONTROL (TFL, IP, PC;) "These input pins indicate the encoded. print lvl ofthe device requesting an interupt Level even the highest prion i oo desert erp ened seven can no be masked. Te eat signican bis gen in TPE and the most spnifcant bit is eontaned in fPLE Thos lines mast romain sable unt the rover sgl inte tupt acknowledge (FC» ~ FC ave all ih) to iste that the interap vecoguised SYSTEM CONTROL ‘The system control inputs are used (o either reset or halt the processor and to indicate to the processor that bus errs hhave occurred. The three system control inputs are explained in the following paragraphs Bus Error (BERR) "This input informs the processor that there is a problem with the eycle currently being execvied, Problems may be 2 tesult of: (1), Nontesponding devices {Q) Interrupt vector number acquisition fature 3) legal access request a5 determined by 2 memory man- agement unit (4) Other application dependent errors ‘The bus error signal interacts with the halt signal to detet- imine if exception processing should be performed or if the ‘current bus c¥ele should be retried Refer to BUS ERROR AND HALT OPERATION paragraph for additional information about the interaction of the bus error and halt signals eset (HEB) "This bidirectional signal line acts to rset (initiate a system initialization sequence) the processor in response to an external reset signal, An internally generated reset (result of a RESET instruction) causes all external devices to be reset and the internal state of the processor is not affected. A total system reset (processor and external devices) is the result of external HALT and RESET signals applied at the same time. Refer 10 RESET OPERATION paragraph for additional information about reset operation Hatt ATT ‘When this bidirectional line is driven by an external device, it will cause the processor to stop at the completion of the current but cycle. When the processor has been halted using this input, all control signals are inactive and all three-state lines fare. put in their high-impedance state. Refer to BUS ERROR ‘AND HALT OPERATION paragraph for additional information ‘about the interaction between the halt and bus error signals. "When the processor has stopped executing instructions, such in ¢ double bus fault condition, the halt line i driven by the processor to indicate to external devices that the processor has stopped. WMics8900 PERIPHERAL CONTROL “These control signals are used to allow the interfacing of syn cchronous HD6800 peripheral devices_with the asynchronous {68000. These signals are explained in the following paragraphs. HD68000/HD68HC000 Enable (€) "This signal is the standard enable signal common to all |11D6800 type peripheral devices. The period for this output is ten 68000 clock periods (six elocks low: four clocks high). En- lable is generated by an internal ring counter which may come tip in any state (.e., at power on, it is impossible to guarantee phase relationship of Eto CLK), is free-running clock and runs regardless of the state ofthe bus on the MPU. ‘Valid Petipherat Adress (VFA) ‘This input indicates that the device or region addressed i a 1106800 family device and that data transfer should be syn- chronized with the enable (E) signal. This iput also indicates that the processor should use automatic vectoring for an inter: rupt. Refer to INTERFACE WITH HD6800 PERIPHERALS. ALS. Valid Memory Address (VMIAY ‘This output i used to indicate to HD6800 peripheral devices that there isa valid address on the address bus and the processor is synchronized to enable. This signal only responds toa valid peripheral addres: (VPA) input which indicates thatthe periph: tral is a HID6800 Family device PROCESSOR STATUS (FCs, FC, FC:) These function code outputs indicate the state (user or supervisor) and the cycle type currently being executed, 35 Shown in Table 4. The information indicated by the function ‘code outputs i valid whenever address strobe (AS) i active Table 14 Function Code Outputs Fer Fe] oe Crete Toe Tow [Low Stow | tow | Hi “us High [Low | User Progra ow | High | High | (Undetie, Rerved Low | Low | (Undefined, Reserved tow [High | Supervier Bata High [Low | Superior Progam Hist [Hah | aterupt Acknowidge etock (Lx) ‘The clock input is TTL-compatible signal tha is internally buffered for development of the internal clocks needed by the processor. The clock input should not be gated off at any time, End the clock signal must conform to minimum and maximum pulse width time, SIGNAL SUMMARY Table 15 is 2 summary of a previous paragraphs. the signals discussed in the ‘© BUS OPERATION ‘The following paragraphs explain control signal and bus ‘operation during data transfer operations, bus arbitration, bus terror and halt conditions, and reset operation @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy.» Brisbane, CA 94005-1619 + (415) 589-8300 941HD68000/HD68HCO000 Table 15 Signal Summary Trees i Signal Name Mnemonic IrowvOutowt | Active Stute freee aaron Bat er output na ves | ves Da Bus De= Dis inpwvoutput igh yes | yes ‘Adare Sob s outout ‘ow ves | ne. oad Write Re ‘outout se ve v° Upper and Lower Data Sivober WOE TOE a wm | = Data Transl Acknowledge input iow ro | ne Bun Request input tow ro | re ‘But Grant = “ovtout iow ro | re ‘Bus Grant Aknowiedoe input iow mo | ne Trearupt Priority Lave nou tow | ne | But Eroe input | tow ae Reset inpuvoutput ro | no" Hale inputloutout net |e Enable e ‘output hie rene Vali Womory Ades aK eutout tow | we | ro Vali Peripheral Adress WR input |W ro | no Function Code Output Fos, FC., FC, output high vr | ee Clos eux input om 0 | ne Power input Vee. input =e 5 S Ground Ves input = = FOmmanin DATA TRANSFER OPERATIONS Transfer of data between devices involve the following leads (1) Address Bus Ay through Ary (2) Data Bus Dp through Djs G) Control Signals The address and data buses are separate parallel buses used. to transfer data using an asynchronous bus structure, In all cycles, the bus master assumes responsibility for deskewing all signals it issues at both the start and end of 2 cycle. In addition, the bus master is responsible for deskewing the ac knowledge and data signals from the slave device The following paragraphs explain the read, waite, and read rmodify-write cycles. ‘The indivisible tead-modify-write cycle js the method used by the 68000 for interlocked multiprocessor communications Read Cycle During a read cycle, the processor receives data from memo: 1y OF a peripheral device. The processor reads bytes of data in all cases. Ifthe instruction specifies a word (or double word) ‘operation, the processor reads both upper and lower bytes simultaneously by asserting both upper and lower data strobes ‘When the instruction specifies byte operation, the processor uses an internal Ao bit to determine which byte to read and then issues the data strobe required for that byte. For bytes ‘operations, when the Ao bit equals zero, the upper data strobe is issued. When the Ao bit equals one, the lower data strobe is issued. When the data is received, the processor correctly post tions i internally ‘A word read eycle flow chart is given in Figure 15, A byte read cycle flow chart is given in Figure 16, Read cycle timing is siven in Figure 17. Figure 18 details word and byte read cycle ‘operations. Refer to these illustrations during the following detailed. [At state zero (SO) in the read eycle, the address bus (Ay through Ars) is in the high impedance state. A function code is asserted on the function code output line (FC through FC). ‘The read/write (R/W) signal is switched high to indicate a read cycle. One half clock cycle later, at state I, the address bus is released from the high impedance state. The function code ‘outputs indicate which address space that this cycle will operate In state 2, the address strobe (AS) is asserted to indicate that there is valid address on the address bus and the upper and lower data strobe (ODS, LDS) is asserted as required. The mem. ‘ory or peripheral device uses the address bus and the address strobe to determine if it has been selected. The selected device uses the read/write signal and the data strobe to place its infor- ‘mation on the data bus. Concurrent with placing data on the data bus, the selected device aserts data transfer acknowledge (TACK Data transfer acknowledge must be present at the processor at the start of state S or the processor will substitute wait states for states S and 6. State 5 starts the synchronization of the feturning data transfer acknowledge. At the end of state 6 (beginning of state 7) incoming data is latehed into an internal data bus holding register. During state 7, address strobe and the upper and/or lowe data strobes are negated. The address bus is held valid through State 7 to allow for static memory operation and signal skew. @HITACHI 942 Hitachi America, Ltd. « Hitachi Plaza ¢ 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300HD68000/HD68HC000 Bus MASTER suave pusmasten suave Addrou Device 2 Seen fans 1) Set RA to Rees Pace Function Code on FCs ~FCs 2) Pine Function Code on FC4 ~FCS 3) Pica Addrem on As ~ Aan 2) Amor Ader Strobe (8) 18) Amat Adres Strobe (AB) 51 Anert Upper Osta Srabe (JOB) 0° Low: 8) Auer Upper Dats Stabe (UO? and Lower {Data Stabe (LOB) foe on AL) Deve Suabe (COS) tL 3) Place Adare on Ar An tpt Oats sous Date 2 Pica Oas on Ge ~Dy oF, ~ Du (ome 1) Oxcode Address ay : 2) Pace Dats on Ov ~O, 2) Aisrt Data Teanster Acenowsase 5 ert Data Tear eae Acquis O38 sie Dae 17 Laten Daa 1) Len Dae 2) Nagate ODS or [OS 2) eget ODS ana TOE 3) Negute AS 23) Noma XS se Oye ormnata Cycle comin 1) Remove ats om Dy ~Dy of Ds~ Ors 1) Remove Duta rom Ox =D oe 2) Neget| eae Star Next ye ‘Sut Nat cyte Figure 18 Word Read Cycle Flow Chart Figure 16 Byte Read Cycle Flow Chart 50 51 82 52 54 55 56 57 50 S1 S253 54 55 50 57 5051 5253 M wow mw 95.56 57 tg) YC fen = rand = = ape = = te = = ef — = = Semmens = = =f Figure 17. Read and Write Cycle Timing Diagram @HITACHI Hitachi America, Ltd.» Hitachi Plaza # 2000 Sierra Pont Pkwy. « Brisbane, CA 94006-1819 « (415) 5898300 943.HD68000/HD68HC000 0 51 52 53 54 55 56 57 50 SI 57 53 54 55 56 57 SO SI S251 S495 $6 57 ae TUL AAA Fe -- == Wora esd — ~ —ofe- (04a Byte Rese Even byte Rea — af Figure 18 Word and Byte Read Cycle Timing Diagram ‘The read/write signal and the function code outputs aso remain vali through state 7 to ensure a correct transfer operation. The slave device Keeps its data asserted until it detects the negation of either the address strobe or the upper and/or lower data, strobe. The slave device must remove its data and data transfer acknowledge within one clock period of recognizing the nega tion of the addess or data strobes, Note thatthe dats bus might ‘not become free and data transfer acknowledge might not be femoved until state 0 or 1 ‘When address strobe is negated. the slave device is released, Note that a slave device must remain selected as long as address strobe is aserted to ensure the correct functioning of the read modify-write cycle Write Cycle uring write eye. the processor sends data to menor ox a peripheral device. The processor writes bytes of data in SI cles If the instruction species 3 word operation the pro essor wits both bytes. When the instruction specifies a byte Speration, the processor uses at internal Ap bit to determine which byte to write and then isues the data strobe requiced Tor that byte. For byte operations, when the Ap bit equals 220, {he upper dats stobe issued When the Ay Bit eq the lower data strobe is sued. word wite cycle low charts gyven in Figure 19. A byte wsite cycle flow chart is gven in Figure 20, Write cycle timing is given in Figure 17. Figure 21 details word and byte write cycle operation. Refer to these Ilusteaions during the following detailed discussion. ‘ML state zero (SO) in the wate cycle, the address bus (Ay ‘through Ars) i inthe high impedance stat. A function code is suserted on the function code output line (FC through FC). (NOTE The read/write (R/) signal remains high until state 210 pre ents conflicts with procedingfead jes. The data bus tot aren ant state 3, One half clock late, at state 1, the address bus is released from the high impedance state. The function code outputs indicate which addres space that this cycle wll operate on, In state 2, the address strobe (AS) is asserted to indicate ‘that there isa valid address on the address bus. The memory. or peripheral device uses the address bus and the addres strobe to determine if it has been selected. During state 2, the read/ write signal is switched low to indicate a write cycle. When ‘external processor data bus buffers are required, the read/write line provides sufficient directional control. Data is not aserted during this state to allow sufficient turn around time for ex- ternal data buffers (if used). Data is asserted onto the data bus ring state 3 in state 4, the data strobes are aserted as required to ind cate that the data bus is stable. The selected device uses the read/wnte signal and the data strobes to take its information from the data bus. The selected device asserts data transfer acknowledge (DTACK) when it has successfully stored the data Data transfer acknowledge must be present at the processor tthe start of state S or the processor will substtste wait states for states $ and 6. State 5 start the synchronization of the returning data transfer acknowledge During state 7, address strobe and the upper and/or lower data strobes are negated. The address and data buses are held valid through state 7 to allow for static memory operation and signal skew. The read/write signal and the Function code output also remain valid through state 7 to ensure a correct transf ‘operation. The save device keeps its data transfer acknowledge asserted unlit detects the negation of ether the address strobe for the upper and/or lower data strobe. The slave device must acknowledge within one clock period after recognizing the negation of the address or data strobes. Note that the processor releases the data bus atthe end of state 7 bout that data transfer acknowledge might not be removed ‘until state O or I, When address strobe is negated, the slave Aevice is released. @HITACHI 944 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1619 » (415) 589-8300HD68000/HD68HC000 aus masTER stave Sars Device, 1 race Function Code on FCx ~ FC: 2) Place Aaronson Ay ~ Arp 3 Anwce asores Seems ro we 5) Pace Dats on 8) aunt Upoer Data Srcbe (TBE) and omer Bate Sbe (CDS) Inout Oata 2) Store Bata on Dy ~ Ove ora — 1) Neqote WOE ara COS 21 Neqote 35 2) Serniico erminae Cyete_ 1) Negate DTC Stan Next Cycle Figure 19 Word Write Cycle Flow Chart BUSMASTER SLAVE 1) ace Function Case an FCy ~ FC, 2) Pace Asaress on A, Aag 5) ere siren Strobe 8) 4) Sermo mee 5) ace Ona on Ds ~ 0: oF By wom) [Nutt Unser Oata Stabe (UDB! or Lower (na Stove (COS! (based on Aa) - | snout Baa 11 Decoge Aare 21 Stor Oats. on De ~Ds st DB. aseted Dye if ODS i anertes Terminate Outpt 1 Negate UBS ane COS 21 Negate BS 31 femove Ont from De ~ Ds oF. ~ Diy | Negate OTACR ent Cvele Figure 20. Byte Write Cycle Flow Chart 50 51 52 53 $4 $6 S6 S7 50 SI S2 S? S455 56 57 50 SI 52 53.94 55 56 57 Figure 21, Word and Byte Write Cycle Timing Diagram @ HITACHI Hitachi America, Ld.» Hitachi Plaza © 2000 Sierra Point Phy. « Brisbane, CA 94005-1819 » (415) 589-8300 945HD68000/HD68HC000 Reed Modify Write Cycle The read-modily-write cycle performs 2 read, modifies the data in the arthmeticlogic unit, and writes the data back to the same address. In the 68000 "this cycle is indivisible in that, the address strobe is aserted throughout the entre cycle. The test and set (TAS) instruction uses this eycle to provide mean ingful communication between processors in a multiple pro- #8Sor environment. This instruction is the ony instruction that uses the read-modify-write cycle and since the test and set in- struction only operates on bytes, all read-modify-write cycles are byte operations. A tead-modify-write cycle flow chart is sven in Figure 22 and a timing diagram is given in Figure 23 Refer to these illustrations during the following detailed discus ‘At state zero (SO) in the read-modify-wrte cycle, the address bbus (Ay through Ass) is inthe high impedance state. A function code is asserted on the function code output line (FCe through FC,). The read/write (R/W) signal is switched high to indicate a read cycle. One half clock cycle later at state 1, the address bus is released from the high impedance state. The function code outputs indicate which address space that this cycle will operate on, In state 2, the address strobe (AS) is asserted to indicate that there is a valid address on the address bus and the upper oF ower data strobe (UDS, LDS) i asserted as required. The mem- ‘ory or peripheral device uses the address bus and the address strobe to determine if it has been selected. The selected device ‘uses the read/write signal and the data strobe to place its infor- ration on the data bus, Concurrent with placing data on the data bus, the selected device asserts data transfer acknowledge atthe start of state $ or the processor will substitute wait states for states $ and 6. State 5 starts the synchronization of the returning data transfer acknowledge. At the end of state 6 (beginning of state 7) incoming data is latched into an internal data bus holding register. During state 7, the upper or lower data strobe is negated. ‘The address bus, addres strobe, read/write signal, and function code outputs remain as they were in preparation for the write portion of the cycle. The slave device keeps its data asserted Unt it detects the negation of the upper ot lower data strobe ‘The slave device must remove its data and data transfer ac- knowledge within one clock period of recognizing the negation of the data strobes. Internal modification of data may occur from state 8 to state 11- (NOTE) The rad/vrite gna remains high unt sate 14 to prevent bus Conflicts withthe preceding Yea portion ofthe cycle and the fate but no ried bythe proceuor un Sate 18 In state 14, the read/write signal i switched low to indi 4 write cycle. When extemal processor data bus buffers required, the read/write line provides sufficient directional ‘control. Data is not asserted during ths state to allow sufficient tum around time for external data buffers (if used). Data is amserted onto the data bus during state 15. In state 16, the data strobe is asserted as required to indicate that the data bus is stable. The selected device uses the read/ write signal and the data strobe to take its information from the ‘bus, The selected device asserts data transfer acknowledge (DTACK) when it has succesfully stored its data Data transfer acknowiedge must be present at the processor at the start of state 17 of the processor will substitute wait states for states 17 and 18, State 17 starts the synchronization of the returning data transfer acknowledge forthe waite portion of the cycle. The bus interface circuitry issues requests for subsequent internal cycles during state 18, During state 19, address strobe and the upper or lower d strobe is negated, ‘The address and data buses are held valid through state 19'to allow for static memory operation and signal skew. The read/write signal andthe function code outputs also remain valid through state 19 to ensure a correct transfer ‘operation. The slave device keeps its data transfer acknowledge asserted until it detects the negation of either the address strobe ‘or the upper or lower data strobe. The slave device must remove its data transfer acknowledge within once clock period after Fecognizing the negation of the address or data strobes, Note that the processor releases the data bus at the end of state 19, ‘but that data transfer acknowledge might not be removed until sate Or L When adress robes negated the slave devices BUS ARBITRATION Bus arbitration is a technique used by musterype devices to request, be granted, and acknowledge bus mastership, In ts simplest form, it consists of: (1) Asserting a bus mastership request. (2) Receiving 2 grant that the bus is available at the end of the current cycle (3) Acknowledging that mastership has been assumed Figure 24 is a flow chart showing the detall involved in a request from a single device. Figure 25 is a timing diagram for the same operations. This technique allows processing of bus requests during data transfer cycles. “The timing diagram shows thal the bus request 38 negated at the time that an acknowledge i aserted. This type of oper: ation would be true for a system consisting of the processor and one device capable of bus mustersip. In systems having ‘number of devices capable of bus mastership, the bus request Tine from each device is wite ORed to the processor. In this, system, itis easy to see that there could be more than one bus request being made. The timing diagram shows that the bus grant signal is negated a few clock cycles after the transition of the acknowledge (BGACK) signal However, if the bus requests are still pending, the processor will assert another bus grant within a few clock cycles after it was negated. This additional assertion of bus grant allows ‘external arbitration circuitry 10 select the next bus master before the current bus master has completed its requirements. ‘The following paragraphs provide additional information about the three steps in the arbitration process. @ HITACHI 946 Hitachi America, Ltd. © Hitachi Plaza « 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 » (415) 589-6300HD68000/HD68HC000 aus Masten Acaren Device 1) See AA Reva 2} Piece Function Code on Fy ~FC> 3) Pisce Aaareson Ay Ase 4) Ame Agar robe (3) 13) Amer Opps Osts Stabe (UDB! or (oer Bate Stabe ICDS) 1) Latch Dae 2) Nagate UDS 0” COS 3) Stor Bae Modiesion Terminate Cele Ds =Dy oF D, - Dis output Trnster 1 sae Ra vo wre | 2 Placa Daa on Dy ~O» or Ds Dis | 8} Aner Upper Date Sobe (OTS) or Lover 1) Stabe Osta on Ds =D» of Ds Die Date Svabe (COS) 2) Auer Oats Teasie Acknowledge Brace Terminate Output Tansee 1 Negute DOS or TOS 2) Neate 3} Remove Dats trom “Ds ot 4) Serr to Rene L_____—_ 1s BRE —__——__ Figure 22 ReadModity Write Cycle Flow Chi $0 $1 2.59 $4 $5 $6.57 50 so siosiisizsiastesissi6st7siBsi9 ere —\_ fT sooo Figure 23. Read Modify. Write Gye Timing Diagram kK @HITACHI Hitachi America, Ltd. « Hitachi Plaza # 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 947HD68000/HD68HC000 PROCESSOR REQUESTING DEVICE (ae Grant us Avie 1 Assert Gus Grant (6S) ‘Acknoadge Bus Matertnig 3) Ne bu maser auere Bus Grant Ackoowiedge BGACK) to become naw 4) Bos master oapaes Requesting the Bus External devices capable of becoming bus masters request ‘the bus by asserting the bus request (BR) signal. This iss wire (ORed signal (although it need not be constructed from open collector devices) -that indicates to the processor that some extemal device requires control of the external bus. The pro- cessor is effectively at a lower bus priority level that the ex- ternal device and will relingush the bus after it has completed the last bus cycle it has started ‘When no acknowledge is received before the bus request signal goes inactive, the processor will continue processing when it detects that the bus request is inactive. This allows ‘ordinary processing 10 continue if the arbitration circuitry responded to noise inadvertently Feceiving the Bur Grant _ The procestor asserts bus grant (BG) as soon as possible. Normally this is immediately after internal synchronization The only exception to this occurs when the processor has made an internal decision to execute the next bus cycle But has not progressed far enough into the cycle to have asserted the address strobe (AS) signal. In ths case, bus grant will not be asserted until one clock after address strobe is asserted to indicate to extemal devices that 2 bus cycle is being executed The bus grant signal may be routed through 2 daisy chained network or through a specific priority-eneoded network. The processor is not affected by the external method of arbitration aslong asthe protocol is obeyed. Acknowledgement of Masterhip Upon receiving & bus grant, the requesting device waits until address strobe, data transfer acknowledge, and bus grant acknowledge are negated before issuing its own BGACK. The negation of the address strobe indicates that the previous ‘master has completed its cycle, the negation of bus grant acknowledge indicates that the previous master has releated the bus. (While address strobe is aserted no device is allowed a cycle.) The negation of data transfer acknow - licates the previous slave has terminated its connection {0 the previous master. Note that in some applications data @HITACHI 948 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 » (415) 589-8300HD68000/HD68HC000 transfer acknowledge might not enter into this function, Gen- eral purpose devices would then be connected such that they were’ only dependent on address strobe. When bus grant ac- knowledge is issued the device is bus master until it negates ‘bus grant acknowledge. Bus grant acknowledge should not be negated until after the bus cycl(s) is (are) completed. Bus rmastership is terminated at the negation of bus grant acknow- edge. “The bus request from the granted device should be drop- ped after bus grant acknowledge is asserted. If a bus request 1s stll pending, another bus grant will be aserted within a few clocks of the negation of bus grant. Refer to Bus Arbitration Control section, Note that the processor does not perform any external bus eycles before it re-asserts bus grant BUS ARBITRATION CONTROL ‘The bus arbitration control unit in the 68000 i implemented with a finite state machine. A state diagram of this machine is thown in Figure 26. All sxyachronous signals to the 68000 are synchronized before being used internally. This synchronization is accomplished in & maximum of one cycle ofthe system clock, ‘assuming that the asynchronous input setup time (#47) has RK Grant Acknowledge Internal G= Bus Grant ‘T= Three State Contd te Bus Conta! Lovie** X= Dont Core + State machine wil oot change state if bus it in $0. Rater to BUS SRBrTRATION CONTROL for sonal stormaton, ‘+ The addron but wil ba placed ia the high impedence sate if To Mitted tna RE le ogee Figure 26 State Diagram of 68000 Bus ‘Arbitration Unit ‘been met (see Figure 27). The input signal is sampled on the falling edge of the clock and is valid internally after the next falling edge. ‘As shown in Figute 26, input signals labeled Rand A are ternally synchronized on the bus request and bus grant acknowledge pins respectively. The bus grant output is lebeled Gand the internal three-state control signal T. If Tis true, the address, data, function code line, and control buses are placed in a high-impedance state when AS is negated. All signals are shown in positive logic (active high) regardless of their true active voltage level State changes (valid outputs) occur on the next rising edge ter the internal signals valid. ‘A timing diagram of the bus arbitration sequence during 2 processor bus cycle is shown in Figure 28. The bus arbitration Sequence while the bus i inactive (ie., executing internal ‘operations such as a multiply instruction) is shown in Figure 29. Tf a bus request is made ata time when the MPU has already begun 2 bus cycle but AS has not been asserted (bus state $0), BBG will not be asserted on the next rising edge. Instead, BG wil be delayed until the second rising edge following it's internal assertion, This sequence is shown in Figure 30. er eux: { [BR (exter of he me Figure 27. Timing Relationship of External Asynchronous Input to Internal Signals @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy, « Brisbane, CA 94005-1819 » (415) 589-8300 949HD68000/HD68HC000 us rlenad trom tee ate anc BGAGK negated intra BGACK meget 50 ST 5253 S455 56 57 50ST Proceso Ateena Figure 28 Bus Arbitration During Processor Bus Cycle Th vata mena ona oT or aS Ur —— BP fe ee ae aU eee ate rete SEER SEsE TEE =TONOL EEE SESE DIES ESEUSESTET SSI ESEUIESIESELSESESIIBIEE=TETEESEECE=TETTEIEE Bene Nf 2D Procenor To Birt ‘Alternate Bur Marte eer Figure 29 Bus Arbitration with Bus Inactive @HITACHI 950 Hitachi America, Ltd. « Hitachi Piza + 2000 Sierra Point Pkwy. + Brisbane, CA 94006-1819 + (418) 589-8300HD68000/HD68HC000 SGACK sate BGACK nega Proceuor starts next bu evel 'BGACK negated intern | TULL LS LS 50 5ST 82 53 S45 8657 80 S182 5 54 55 56 57 50 St Figure 30. Bus Arbitration During Processor Bus Cycle Special Case ‘BUS ERROR AND HALT OPERATION In a bus architecture that requires a handshake trom an ex: ternal device, the posibihty exists thatthe handshake might sot foccur. Since different systems will equite a different maximum Tesponse time, a bus er70r input is provided. External circuitry must be used to determine the duration between address strobe land data transfer acknowledge before issuing a bus error signal When a bus error signal i received, the processor has two options. initiate a bus error exception sequence or try running the bus cycle again. Exception Sequence ‘When the bus error signal is asserted, the current bus cycle fs terminated, If BERR is asserted before the falling edge of 2, AS will be negated in S7 in either a read or write cycle ‘As long as BERR remains asserted, the data and address buses ‘willbe in the high-impedance staie. When BERR is negated, the processor will bepin stacking for exception processing Figure 31 is a timing diagram for the exception sequence. ‘The sequence is composed of the following elements (1) Stacking the program counter and status register (2) Stacking the error information (G) Reading the bus ertor vector table entry (8) Executing the bus error handler routine “The stacking of the program counter and the status register is the same as if an interrupt had occurred, Several additional items are stacked when a bus error occurs. These items are used to determine the nature of the error and correct it, if possible. The bus error vector is vector number two located at address '$000008. The processor loads the new program counter from this location, A software bus error handler routine is then executed by the processor. Refer to EXCEPTION PROCESS- ING for additional information tunning the Bus Cycle When. during 4 bus cycle, the processor receives a bus error signal and the halt pin is being driven by an external device, the processor enters the re-run sequence. Figure 32 isa timing 100 miiseconds ef twores 21 SP aa eer fxn sate Union: XXXKKK 3) S8P Lomrascinnare 61 Fratimucion etch hare, AILContt Signa nate, ‘Dea But Rend Moe Figure 35 Reset Operation Timing Diagram ‘THE RELATIONSHIP OF DTACK, BERR, ANO HALT In order to propel contol termination oft bs eye for & retun or a bus error condition, DTACK. BERR, sod HALT Should ‘be auered.and- negated on the ring edge of the 68000 clock. Tis wil aur that when two signs aneted ‘simultaneously, the required setup time (947) for both of them wl be met ding he same bus ste This or some equalent precation, should be dagned extemal tothe 68000, Prametere48 i intenged 10 ensue is ‘peation in totaly asynchronous system, end may begnred Afthe above condone met. The ptefened bus eyle terminations, may be summarized 5 follow (case number fe to Table 15 Normal Termination: DTACK overs fin (cs 1) i Trmintion is aered athe sae time or before DTACK and. BERR remains negated (cues Sand 3). is ered in iu of at he same time, or before DTACK (case 4); BERR. Isinegted at the siete or afer brat AALT and BERR are asserted in liew ofa the same timer before DING ‘Bus Error Termination: Re-Run Terminetion: (cates 6 and 7); HALT must be held at least one cycle after BERR. Case § in- icates BERR. may precede HALT which allows fully asynchronous asser. thon, Table 16 details the resulting bus cycle termination under various combinations of control signal sequences. The nega- tion of thete same control signals under several conditions is shown in Table 17 (DTACK is assumed to be negated normal- ly in all cases; for best results, both DTACR and BERR should be negated when address strobe is negated.) Example A: A system uses a watchdog timer to terminate Accesses to un-populated address space, The timer asserts TACK and BERR simultaneously after time-out. (cae 4) Example B: A system uses error detection on RAM con- tents, Designer may (a) delay DTACK until data verified, and return simultaneously to re-run error cycle nd (ase 6), or if valid, return DTACK:; (b) delay DTACK until data verified. and setun BERR at same time as DTACK if data in error (case 4); (c) retum DTACK prior to data verifica- ton, as described in previous section. If data invalid, BERR is asserted (case 1) in next cycle, Error-handling software must know how to recover error eyele. @ HITACHI 954 Hitachi America, Ltd, « Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1619» (415) 569-8300