vfBGA Assembly

(Very Fine-pitched Ball Grid Array)

Process Flow
Lesson 12
Facilitator: Engr. Ireene P. Valencia, Ph.D

K402933L
M C ‘99

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Assembly Process Flow
•Front of Line (FOL)
* Die Preparation
* Die Attach
* Wire bond

• End of Line (EOL)

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 Assembly Process Flow

FOL EOL

Front of Line Assembly End of Line Assembly

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are stations from Die-prep, are stations from encapsulation or
up to Internal Visual Inspection. Mold down to Packaging.
 Die-prep
1

IVI
4
FOL

3 Die attach

Wire bond

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 Die-Prep

Wafer Incoming Monitor Wafer Thickness Monitor

Wafer Wash
Mount Before Detape
Wafer Tape Wafer Saw
Backgrind Die Visual Inspection

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 Wafer Incoming Monitor
➢Inspects the wafer to ensure that the wafer has not been
damaged during transit.
➢To establish an inspection procedure for separation of defect-
clustered wafers
note : rejected dice are marked with inked dots.

Wafer -
A thin slice of single crystal silicon . . DIE
w/c is used as the basic substrate for .
the fabrication of Ics.
Wafer Flat
Die -
The individual semiconductor element of
integrated
circuit. (also known as chip) or a piece of silicon
containing integrated circuit.

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Wafer Wash
Cleans the wafers thoroughly from any
foreign materials before covering with tape.

Dry Temp DI Temp

Emergency Stop

UC-2400

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Wafer Tape
Provides tape onto the wafer top surface to prevent
any debris or particles from getting in contact with
the front side of the wafer during the backgrind
process.

Top

Takatori ATM 1000 C Taper

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Backgrind
Reduces the thickness of the wafer (die backside).
Then WASH to ensure no residues of silicon debris is
clinging at the back surface of the wafer before detape
process.

Wafer

Chuck table / Grinder

Shibayama VG-502 MK II-8

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Wafer De-tape

The process of removing or peeling off the

tape after the backgrind process.

Wafer Mount
NEL
Takatori ATRM-2100 Wafer de-tape

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 Wafer Thickness Monitor
Measures the thickness of the wafer. Ensures
required thickness is achieved. Then WASH to
ensure no foreign materials are left on the surfaces
of the wafer before wafer mount.

MTI Proforma

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Mount Before Detape (MBD)
The process of mounting the wafer onto the
Nitto tape to hold the wafer in place before
cutting or before the wafer is sawn.

Wafer Mount
LTD2500F
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Wafer Saw
To cut the wafer into individual die or
the process of separating the dice
from the wafer.

Disco Saw Model DFD-2D/8

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Die Visual Inspection (DVI)
To screen assembly lots for Fab and Assembly
related defects. DVI is the final step in Die Prep
process where the wafers are inspected to
determine if they meet spec.

High Power Microscope

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FOL
Die Attach Substrate Prep

Die Attach Cure Substrate Bake

Prewirebond Plasma Clean Substrate Mark

Wirebond

IVI

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Substrate Bake

To remove moisture from the substrate surface.

Blu-M Oven

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 Substrate Mark
To mark product traceability information on
substrate. The mark consists of an assembly process
order number (lot number) and a substrate serial
number.

HTA AP2000

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Die attach

To attach or mount a die into a definite

substrate location.

ESEC DA
Model 2008

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 adhesive

Fiducial cross
leadfingers

substrate mark die

Oval hole

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 Die attach Cure
To cure adhesive to complete adhesion
property of material.

XXX - XX

Despatch Oven or Blu-M Oven

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Wire bond XQ

K&S 1488 & 8028 Automatic

Wire Bonder MODEL

XQ

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 Prewirebond Plasma Clean
To remove contaminants from the surface of the
substrate leads and die bondpads to ensure good
bonding quality at wirebond operation.

8888 8888

MARCH PX-1000

March PX-1000

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 Wire bond
Provides electrical interconnection from device bond pads to
package leads. Gold wire is the media used for connection
of bond pads to corresponding leads as per the bonding diagram.

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Internal Visual Inspection (IVI)
To screen assembly lots for Die Prep escapees, Die
Attach and Wirebond defects. IVI is the final step in
FOL process where the units are inspected to
determine if they meet spec. If they pass inspection,
they move on to EOL operations.

IC OPT-652
Auto Handling Inspection
Low Power Scope

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 EOL

Premold Plasma Clean

Mold
Flux Clean
Post Mold Cure
Saw Singulation
Lasermark

Ball Attach Package Visual Inspection

Reflow Pack

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Premold Plasma Clean
To clean the solder masked surface of the
substrate for good adhesion of mold epoxy
compound to the core substrate.

8888 8888

MARCH PX-1000

March PX-1000

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 Mold
To encapsulate device circuitry to serve as protection
against damaging external force/energy. It also
strengthens the physical condition of the device during
handling and field application.

Microfits ASA Model 808S

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 Post Mold Cure
To further cure the mold compound of the molded
substrate.

Despatch Oven
Model PBC2-32

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Laser Mark
To mark the package for assembly
traceability to prevent from mixing.

GSI Lumonics Lasermark

Model PML2000

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Ball Attach
To place solder balls onto the substrate lands prior to
the reflow process and check for missing balls, extra
balls, and gross placement errors.
Soder ball

Land pad

BP20 Ball Placer

VC15 Vision Checker
LD40 Loader/Unloader

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Solder Ball Reflow
To bond the solder ball to package lands.

Electrovert Omniflo 7 Model Oven

FL200U Loader/Unloader

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 Flux Clean
To remove flux residue from ball mount and reflow
operations

AATC Mega II Cleaner

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Saw Singulation
➢To take solid BGA leadframes from
cassettes
➢To saw the leadframes
➢To wash the diced units
➢To dry the units
➢To inspect the units
➢To bin the rejects by dropping them in
either of the two reject cups
➢To put the parts into a shipping tray

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Saw Singulation

finished product

Intercon SBS8800 Matirx Array Singulation

DAD681

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(PVI) Package Visual Inspection
To screen assembly lots for package mechanical and
visual defects. PVI is the final step in assembly process
where the units are inspected to determine if they meet
spec. If they pass inspection, they move on to the next
operation.

3 diopter K402933L
M C ‘99

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Pack Process
The units are packed and are transported to test area.

Intermec Bar Code Printer

Tape Dispense Machine

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 IC PACKAGING
TECHNIQUES

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 PACKAGING TECHNIQUES

TRANSISTOR-OUTLINE (TO) PACKAGE

FLAT PACK
DUAL INLINE PACKAGE (DIP).

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 Transistor-Outline Package.

TO was a reliable package that only required

increasing the number of leads to make it
useful for ICs. Leads normally number
between 2 and 12, with 10 being the most
common for IC applications.
Once the IC has been attached to the header,
bonding wires are used to attach the IC to the
leads. The cover provides the necessary
protection for the device.

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 Exploded TO-5.

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 TO-5 package.

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 TO-5 mounting PLUG-IN
MOUNTING

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 TO-5 mounting EMBEDDED CAN(LEADS PLUGGED IN)

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 Flat Pack

Many types of IC flat packs are being produced

in various sizes and materials. These packages
are available in square, rectangular, oval, and
circular configurations with 10 to 60 external
leads.
They may be made of metal, ceramic, epoxy,
glass, or combinations of those materials.

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 Enlarged flat pack exploded view

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 Typical flat pack.

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 Dual Inline Package
DIP was designed primarily to overcome the difficulties
associated with handling and inserting packages into
mounting boards.
DIPs are easily inserted by hand or machine and require
no spreaders, spacers, insulators, or lead-forming tools.
Standard hand tools and soldering irons can be used to
field-service the devices.
Plastic DIPs are finding wide use in commercial
applications, and a number of military systems are
incorporating ceramic DIPS

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 DIP packaging steps.

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 DIP packaging steps.
(A). The integrated-circuit die is sandwiched between the two
ceramic elements. The element on the left of view (A) is the
bottom half of the sandwich and will hold the integrated-
circuit die. The ceramic section on the right is the top of the
sandwich.
(B) The large well in protects the IC die from mechanical
stress during sealing operations. Each of the ceramic
elements is coated with glass which has a low melting
temperature for subsequent joining and sealing. View (B)
shows the Kovar lead frame stamped and bent into its final
shape. The excess material is intended to preserve pin
alignment. The holes at each end are for the keying jig used in
the final sealing operation.

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 DIP packaging steps.
(C). The lower half of the ceramic package is
inserted into the lead frame. The die is
mounted in the well and leads are attached.
(D) The top ceramic elements are bonded to
the bottom element and the excess material is
removed from the package.
(E) is the final product.

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 Dual inline package (DIP).

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 Flip Chip Package
Flip chip assembly is the direct electrical connection of
face-down (hence, “flipped”) electronic components onto
substrates, circuit boards, or other components, by means
of conductive bumps on the chip bond pads.
Flip chip is also called Direct Chip Attach (DCA), since the
chip is directly attached to the substrate, board, or carrier
by the conductive bumps.
In contrast, wire bonding, the older technology that flip
chip replaces, uses face-up chips with an individual wire
connected to each bond pad.

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 Flip Chip and a substrate

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Face-down (FLIP-CHIP) mounting
method
Conductive patterns are evaporated inside the package
before the die is attached.
These patterns connect the external leads to bonding
pads on the inside surface of the die.
The pads are then bonded to appropriate pedestals on
the package that correspond to those of the bonding
pads on the die

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 Flip-chip package.

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Advantages over other microelectronic
assembly methods:
Smallest Size – Eliminating bond wires and cumbersome individual packages. Flip
chip is the simplest minimal package, smallest because it is very close to chip size.
Highest Performance – Because of its small size, flip chip offers the highest speed
electrical performance of any assembly method. Eliminating bond wires reduces
the delaying inductance and capacitance of the connection by a factor of 10.
Greatest Connection Flexibility – Flip chip gives the greatest input/output
connection flexibility. Flip chip connections can use the whole area of the die,
accommodating many more connections on a smaller die, and placing them most
efficiently.
Most Rugged – Flip chip is mechanically the most rugged interconnection method.
Lowest Cost – Flip chip can be the lowest cost interconnection for high volume
automated production, with costs of a fraction of a cent per connection. This
explains flip chip’s longevity in the cost-conscious automotive world, and growing
popularity in smart cards, RFID cards, cellular telephones, and other cost-
dominated applications.

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THE END

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