u RS) Data Library Issued March 1988 8509 Bucket brigade delay lines ‘The RS bucket brigade delay line system comprises ‘wo delay lines and a matching clock driver. Introduction to the bucket-brigade delay line ‘To characterise an anelogue signal of f hertz complete- 1y, at least 2f samples per second are needed. If these are stored in the stages of a kind of shift register then the attractive features of the shift register — especially as a delay line - can be used for analogue signal handling, Sampled values of the analogue signal are stored in the form of charges on a series of capacitors. Between successive capacitors is a switch that transfers the charge from one capacitor to the next on command of a clock pulse, By analogy with the old fire-fighting method, in which buckets of water were passed along the line from man to man, a delay line of this sort is known asa bucket-brigade Since each capacitor cannot take up a new charge until it has passed on its previous one, only half the capaci- tors camry information and the ones in between are empty, Starting from the condition shown in Figure 1(2), the transfer proceeds in two stages: in the first, bucket 1 empties into bucket 2, and bucket 3 into bucket 4 and in the second, bucket 2 empties into bucket 3, and bucket 4 into bucket 8. ‘Two antiphase clock signals are required; one to ‘govern the emptying of even-numbered, and the other of odd-numbered buckets, ‘There is a practical drawback to the scheme illustrated in Figure 1. The buckets in which the samples are stored must empty completely during each transfer. In practice, the buckels are capacitors and the samples are charges on them. Owing to leakage current, com plete discharge is difficult to ensure. So instead, the scheme illustrated in Figure 2 is adopted, Figure 2(a) represents the initial condition; buckets 2 and 4 are fl, and samples are stored in buckets | and 3. During the first transfer, bucket 2 fils bucket 1, and bucket 4 fills bucket 3. What remains in bucket 2s then equal to the original contents of bucket 1, and what retmains in bucket 4 is equal to the original contents of bucket 3. During the next transfer, bucket 3 fils bucket 2, and bucket § fills bucket 4. Thus, as the buckets empty from night to lef, the sampled quantities move, as before, from left to right, that is from input to output. ‘This is the scheme used in a practical bucket brigade delay line. ‘Stock numbers 631-288 to 301 guguU 89 Sg UeUs Figure 1 Sample transfer in a bucket-brigade, sim- plified scheme. Samplos in buckets I and 3 (a) are ‘poured into empty buckets 2 and 4 (b); thus, the samples move step by step from leftto right (c) euTe ge we" Figure 2 Sample transfer in a bucket-brigade, practical scheme. Buckets 1 and 3 contain samples (@); when full buckets 2 and 4 are poured into them. (b), the sample quantities move, as before, from left to right (c)8509 M3004 (631-288) "The MN3O04 is a 612 stage, low noise, bucket brigade delay line providing a signal to noise ratio of 854B. The device features low insertion loss and no gate back bias isrequired, ‘Analogue signals, in the aucio band, can be delayed by 2.86ms to 25.6ms by adjusting the clock frequency. The device is ideally suited for processing audio signals to generate an artificial delay in public address systems. May also be used to obiain musical effects such as reverberation, vibrato and chorus effects. Absolute maximum ratings Supply voltage -18V 10 +030 Output voltage -18V 10 +030 Operating temperature 20°C to +60°C Storage temperature __-88°C to + 125°C ATTENTION (OBSERVE PRECAUTIONS FORHANDUNG. eugoTRosranc ‘SENSITIVE DEVICES. Aish Features @ Variable delay of audio signal: 2.56ms~ 28 6ms @ Clock component cancellation capability @ Low insertion loss: L, = 1/SdB typ. ‘Wide dynamic range: SIN = 854B typ. © Wide frequency response: f< 03x cy @ Clock frequency range: 10~ 100kHz @ Low noise: V,. = 0.21mVrms max, @ Low distortion; THD = 0.4% typ. Applications ‘A. Reverberation and echo effects of audio equipments such as stereo, ‘Tremolo, vibrato and chorus effects in electronic musical instruments Variable or fixed delay of analogue signals. Telephone time compression and delay line for voice communications systems. > >> Pin conections eno’ jg ourz cpt fz [aj ours IN [3 2] CP2 Veo [+] M3004 [1:] Voo NC [5 10] NC NCE z] NC Nc [| z] NC TOP VIEW Figwe § Block diagram ee at poe 280 TOperating conditions Parameter Condon min | tye | max | une Dezinsupply volage =f -is | ie |v Gate supply voltage Vo, v Clock volage W level a |v Clock volage U eve Vos v Cloccnput capaciance wo_| oF Greek requancy 0 100 |e Glock pulse wid core Clock ise tine 00 | as Choc alltime 00s Clock crss point a = [4 Tp debi = = Electrical characteristics (Ta = 25°C, Vpp = Vcrx = -SV. Vers = OV, Ve Parameter Simbel Condon win | typ. [max | unn Signal delay time 5 266 mae | oe Tapa gal requency fk @ ra Tnpalsignal sing ac ie THD 76dB typ. @ No insertion loss: L; @ Low distortion: THI © P channel silicon gate process, Applications ‘A. Reverberation elect in audio equipment ‘A. Chorus effect in electronic musical instruments. Pin connections ow]? ham cre [3] [BD Moo Vo fa cor MN3011 ours [oun ‘ours [2] [a] oure ours [4] 5 ours TOP VIEW8509 Figure 20 Block diagram Figure 21 Timing diagram Maximum delay time by tap output Tomminalofihetapouput] ouri | our | ours | oura | ours | oure | Remark ‘Sages of BED Sage) Ea ee ) ‘Maimam delay time Ga) we | w1_| 7 | 3 | 19s | Wea] Cock lon Operating conditions (1a = 25°C) Parameter Symbol Condition mn | typ | max] une Drain supply voltage 4 [is |e [_v Gate supply volage Totl V Gok vliage W level a 3 ¥ Crock votiage TTevel Yoo v ‘Coekinpat capacitance 0] aF ‘Clock frequency ~ 10 100 KH Gioek pulse wiet® osr Crock rise time” =| Crock allie” | Crock ess point 7 3 py Input de Bias = =0_[¥ *seaFiguea! ate Electrical characteristics (Ta = 25°C, Voo = Vor. = -I8V, Vex Parameter Symbol Condition min | typ | max | unit Signal delay time ‘OUT I terminal oe 1.98 198 ms ‘OUT enminal toe 331 [me ‘OUT Sernnal toa | for = lee ~ look ao7 eT [as ‘OUT erminal toe 385 [me GUTS terminal oe BS 1398 ms OUTS ermina Toe 86 1684 ms Inpat signal frequency i - 0 KHz Tnpat signal velage ¥. io Vis insertion ows i me af Te Tora farmonie distortion | THD ei = OTS uw [es | Noize votege Our i ourz oure fey = 100K, 04 | mvems Ourd OUTS UTE | _Vno_| Weighted by curve Signal o noise rao QUT 1, OUT2 OUT3 Fop = 100kHz, weighted by ‘A’ curve n ta ourdours ours | _sw_| Viovs max output eign8509 ‘Terminal description TerminalNo. | Symbol Description. 1 GND 2 Gee _| Glock pulse? 3 Veo _ | Supply voltage 4 OUTS | Ourputof stage 2328 3 OUTS | Outputofstage 2700 6 Our | Output otstage 1728 7 ours | Output ofsiage 1194 é Cura | Cuiputofstage 662 9 UTI | Cutputofstese 396 10 €PI_ | Glock pulse | 0 Vos __| Bias terminal 1 IN _| Signal input terminal ‘Note, Each delayed output produced by combining signals rom the relevant sage withthe soccessve stage and canceling out the cloek components Figure 22 Internal schematic Toa! Vom! wi : rH beg eh _ ie oe Pops pve Epa elk reota tl = red toaa eo i rire Pioqd no LH re re t Veo Lyoka bu = PLLTypical application Figure 23 Reverberation effect generation circuit * Adjust to minimise datotion (VR 100k0 typ) Yee should not excoed +16. Application circuit electrical characteristics (Vec = +18V, Ta tem Symbol Condition Min | typ. | Max | Unit Supply current ec ne [isa [ma Power dissipation Per 185070) mW ‘Signal delay time to | OUT for 83 @ m_|_as Catoff frequency ‘co 3 iz Input signal swing Vi_| THD = 25% 110.5) _[Vims Insertion oss b | OUTS = Ik Vi= c00mv_ 0 al 4 eB ‘Total harmonic distortion THD | t= Weic Vi= Viiman) -6aB Om08) * Noise voltage Veo _[ OUTS Vi= OV oo.) mvs Signal to noise ratio SN [Vex Viiman) 70460) eB ‘Conterisof( represent the value at Voc = +808509 MN 3101 (631-301) ‘The MNBIO1 is a two phase clock generator that is ideally suited for driving the MNaO04 or MN3011 bucket brigade delay lines. Oscillation frequency is adjusted by the addition ofan external RC circuit Features @ Suitable for driving MNS0O4 and MN3OLI directly @ internal or external frequency adjustment @ Two phase clock output (Duty: 1/2) © Voc voltage generator is builtin for MN3004 and Absolute maximum ratings pou Supply voltage —__-18vto 40a § Stale poner supply: “6016 pany Voowosvio rosy © 83oad Dualin-ine plastic package Output voltage Vop-03V io +03 Power dissipation 2007 : Operating temperature —_—_—— -10°C +70°C a Storage temperature 30°C to +125" = ono (Te Vecour cpt 7] ox1 ATTENTION oe [3] MNTON I] on cnseavePaecauTions ca [=] oxs rOMANOUNG ~ tuecrostane TOP VIEW his Sevome overs Figure 24 Block diagram Operating condition (Ta = 25°C) item Symbol Condon ma | ty. | wax | ont | Drain supply valoge Voo_ [OND =0V 2 f-« |e |v Clock oscillator frequency adjustment Figure 28 Oscillation generation circuit 10oO Electrical characteristics (Ta = 25°C, Vpn = -18V, GND = 0V) Item Symbol Condition Min | tye | Max | Unit Input drain current Top _| Notoad 3 mA ‘Total power dissipation Pax | Clock output 40kHz S mW ‘OX! Input terminal Voltage H level Vine 0 Vv Voltage level Vu Woot! Voo_|_¥ Input leakage current hx | aa (OX2 Output terminal ‘Ouiput current H level Tom mA ‘Output current level Tous mA (utput leakage current Thou ao | aa (Cuiput leakage current Thom ao | mak ‘OX Output terminal ‘Output current F level Tena 18 mA (Cutpat current 1 level lous 2 mA (Output leakage current Tow | na ‘Output leakage current howe ao [aA (CPI, GP2 Output terminal (utpat current H level Tox 10 mA (Output current level Tua 10 mA (Output leakage current Thos _| Vo= Von 30 [aa ‘Cuiput leakage current eos ‘GND [oA Vos our Output terminal * (Output voltage Vooour a4 Vv ‘This terminal generates Voc vollage for the MINSOO# ane NOL devices nly. ‘Terminal description Terminal No. | Symbol v0 Description 1 Gnp_| Power supply [Ground 2 en 0 [Gockoupat 3 Von _ | Power supply | Supply voltage 4 cP2 0 _ | Clockoutput 2 antiphase to CPI) 3 Ox 0 | Forinternal timing see | For external timing apply a square wave ofthe required a ona [fable below frequency to pin 7 and leave pins Sand 6 open circuit 1 ox ! eee wer | Vassupnly for MINS004 and MNGOM (Woo = Voox "¥5) Clock oscillator frequency range Constant Example Rm Rm oF fooct* (eta) | foo" _cetts) Example © ° Skt IM % 1810 1800, 7810780 Bamie @ 2k 101M 100 8210440 2610220 Bamle @ Bae Bkto IM 200 140 280 07% 140 ‘Ghockoutput eequency of CP] or CPaterminal + Opeiiation requoncy ofX), OX2and OX u8509 RS Data Library Figure 26 Clock oscillator frequency characteristics ‘The maximum clock frequency ‘The upper limit of the value of clock frequency is determined depending on the load capacitance and ‘power consumption. ‘The permissible dissipation for this LSTis Pp If the clock frequency on the load capacitance is increased, the power consumption will be increased. (Refer to Figure 27) Accordingly, in order to utilize the MN3101 with dissipa- tion less than the permissible value, it is necessary to select adequate values for the clock frequency and load capacitance. Figure 28 shows an example of the dependence of the ‘maximum clock frequency on the load capacitance is Pp = 160mW, By connecting a resistance to the clock output terminal, it ismade possible to increase the value of the maximum clock frequency without increasing dissipation. (Refer to Figures27/and 28.) Itis because the dissipation on the LSI side is lessened, ‘a8 a part of the power consumption required for driving the load capacitance is consuined by the series resis Figure27 Example of the dependence of power ‘consumption onthe clock frequency Ponte es 8 ‘despation 200m beceanienn Figure28 Example ofload capacitance ‘characteristic ofthe maximum clock frequency inthe power consumption cof 160m feptmax)—C, a= 150m RS Components Ltd. PO Box 99, Corby, Northants, N17 9RS Q Be Fletrocomponents Company ‘Telephone: 0836 201234 ©RS Components Ltd, 1985, V