Testing of Other Faults

(i) Transistor Fault

(ii) IDDQ Test

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 IDDQ Current Testing
! Definition
! Faults detected by IDDQ tests
! Vector generation for IDDQ tests
§ Full-scan
§ Quietest
! Instrumentation difficulties
! Sematech study
! Limitations of IDDQ testing
! Summary

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Motivation
• Early 1990’s – Fabrication Line had 50 to 1000 defects
per million (dpm) chips
§ IBM wants to get 3.4 defects per million (dpm) chips (0
defects, 6 s)
• Conventional way to reduce defects:
§ Increasing test fault coverage
§ Increasing burn-in coverage
§ Increase Electro-Static Damage awareness
• New way to reduce defects:
§ IDDQ Testing – also useful for Failure Effect Analysis

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 What is Current Testing?
• Also called IDDQ Testing
• Measurement of the supply, VDD,
• quiescent current
• the sum of all off-state transistors
• Useful only for CMOS circuits
• Limitation due to shrinking technology

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 What is Current Testing?
continued..
• Current-based (IDDQ /IDDT)* test methods, collectively known as IDDX
tests
• Also called parametric tests since they measure chip parameter i.e.
current.
• Leakage current (IDDQ) test is a defect-based test that measures device
supply current under steady state conditions
*
Qàstands for ‘quiescent’
T à stand for ‘transients’

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 What is Current Testing?
continued..

• Fully static CMOS circuits consume little power when their inputs are
stable. This is because there is no direct path from the VDD supply rail
to ground.

• Hence if an IC draws a large amount of current when its inputs are

stable, it is likely to be defective. This is the basic philosophy behind
IDDQ testing

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 Basic Principle of IDDQ Testing
The Figure shows the input and
output voltages, and the drain
current that flows through the
transistors.

After switching completes, this

current is referred to as the quiescent
current and called IDDQ.

In the good circuit IDDQ falls to a

negligible value, whereas in the
defective circuit, IDDQ remains
elevated long after switching is over.

We detect such faults by measuring

at the time instant shown by the • Measure IDDQ current through Vss bus
arrow.
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 About IDDQ (Current)Test
• An IDDQ test is capable of detecting shorts (bridges) between two switching nodes or
a signal and power supply line (both categories referred to as an active or pattern-
dependent defect) or between VDD and ground (called a passive or pattern-
independent defect).

• An active defect increases leakage for some (but not all) input patterns while a
passive defect increases leakage for all input patterns.

• An active defect degrades functionality of a chip (due to reduced noise margin, etc.).

• For this reason, several IDDQ test methods are targeted towards discarding chips with
active defects. A passive defect may not affect the functionality, but increases the
power consumption of a chip. It also reduces the reliability of a chip and can result
in a customer return
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 Current Testing Basics

Ø CMOS circuits operate with normally negligible static current

(power)
Ø But, a defect that causes an appreciable static current can
be detected by measuring the supply current, IDDQ
Ø Technique used since inception of CMOS technology

Ø Limitation due to shrinking technology

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 IDDQ Testing
IDD --- Current flow through VDD
Q --- Quiescent state
IDDQ Testing --- Detecting faults by monitoring IDDQ
VDD

IDD

Inputs Outputs
CMOS
circuit

Normal IDDQ: ~10-9Amp.

Abnormal IDDQ: >10-5Amp.
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 Advantages of IDDQ Testing
• Fault effect is easy to detect- Large difference between faulty and fault free
circuit.

• Many realistic faults are detectable- Faults detectable include bridging,

break, transistor stuck-on, gate-oxide short, latch-up , etc..

• ATPG is relatively simple- No fault propagation is needed.

• Test length is shorter

• Built-in current sensing is possible-Many built-in current sensors have been
developed.

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IDDQ Distribution

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 How Does it Work?
• Apply a test pattern
• Wait for the transient to settle down
• Measure the current
• Needed:
• How to generate the patterns
• How to measure the current
• But, first current characteristics

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Dynamic Current

Vout

VOH

Vin Vout
VOL
t

I
CL

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Inverter: Good and Faulty IDDQ

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 IDDQ Measurement
• Measurement may interfere with the measured
current
• A successful measurement should be:
• easily placed between the CUT and the bypass Capacitor of the
power pin
• Capable of measuring small currents
• Non intrusive, no drop of VDD
• Fast measurement few ns per pattern
• Two types: on- and off-chip

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 External Measurement

Vdd
Power
CUT R Supply
Dt

t
(a) (b)

Problem: CUT sensitive to power supply drop on R

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 Current Sensing Structures
R
Power Sense amplifiers
CUT Supply
designed
to minimize the VDD
voltage drop
(a)

Shunting by diode
limits
the voltage drop to
R R
0.7V

(b) Another option is to

use pass transistor
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 Internal Measurement
When large IDDQ exists, V>VR I
and Fail flag is set.
VDD-GND Shorts

Vdd

IC Bridging Faults

Gate oxide
DUT pinholes
Vref
VGND
Floating gates &
V.drop junction leakages
Comparator
VGND
No defect
GND No
(a) (b) defect Defect

Vref 22
 BICS Based on Bipolar
Transistor
VDD
VDD
f2

CMOS f1 CMOS
Pass/Fail
Flag f1 Module
Module V
Virtual
Ground
VR
V VR Switchin
+ - g
circuit

I
GND

Fault
The switching circuit may switch off a
categories faulty module to prevent large power
consumption
V

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Faults Detected by IDDQ
Tests

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Stuck-at Faults Detected by IDDQ Tests

• Bridging faults with stuck-at fault behavior

§ Levi – Bridging of a logic node to VDD or VSS – few of
these
§ Transistor gate oxide short of 1 KW to 5 KW
• Floating MOSFET gate defects – do not fully turn
off transistor

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 NAND Open Circuit Defect – Floating gate
CMOS transistors stuck-open cause high
impedance states at a logic gate output, and
under certain situations,IDDQ is elevated and
the fault can be detected.
IDDQ testing does not guarantee detection, but
works in practice because the floating output
node is capacitively coupled into the substrate,
as well.
The coupling often results in an intermediate
voltage on the node

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Floating Gate Defects
• Small break in logic gate inputs (100 – 200
Angstroms) lets wires couple by electron tunneling
§ Delay fault and IDDQ fault
• Large open results in stuck-at fault – not
detectable by IDDQ test
§ If Vtn < Vfn < VDD - | Vtp | then detectable by IDDQ test

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Multiple IDDQ Fault Example

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Capacitive Coupling of Floating
Gates
• Cpb – capacitance from poly to
bulk
• Cmp – overlapped metal wire
to poly
• Floating gate voltage depends
on capacitances and node
voltages
• If nFET and pFET get enough
gate voltage to turn them on,
then IDDQ test detects this
defect
• K is the transistor gain
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 Bridging Faults S1 – S5
• Caused by absolute short (< 50 W) or
higher R short between logic gates
• Segura et al. evaluated testing of
bridges with 3 CMOS inverter chain
• IDDQRb tests fault when Rb > 50 KW
• For 0 £ Rb £ 100 KW, current further
increases to high value and provide
good testability.
• Largest deviation when Vin = 5 V
bridged nodes at opposite logic values
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CMOS Transistor Stuck-Open Faults

• IDDQ test can sometimes detect fault

§ Works in practice due to body effect

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Delay Faults

• Most random CMOS defects cause a timing delay

fault, not catastrophic failure
• Many delay faults detected by IDDQ test – late
switching of logic gates keeps IDDQ elevated
• Delay faults not detected by IDDQ test
§ Resistive via fault in interconnect
§ Increased transistor threshold voltage fault

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Leakage Faults

• Gate oxide shorts cause leaks between gate & source or

gate & drain
• Mao and Gulati leakage fault model:
§ Leakage path flags: fGS, fGD, fSD, fBS, fBD, fBG
G = gate, S = source, D = drain, B = bulk

• Assume that short does not change logic values

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Weak Faults
• nFET passes logic 1 as 5 V – Vtn
• pFET passes logic 0 as 0 V + |Vtp|
• Weak fault – one device in C-switch does not turn on
§ Causes logic value degradation in C-switch

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Paths in Circuit

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 Transistor Stuck-Closed Faults
• Due to gate oxide short
(GOS)
• k = distance of short from
drain
• Rs = short resistance
• IDDQ2 current results show
3 or 4 orders of magnitude
elevation

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Gate Oxide Short

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Quietest Leakage Fault Detection – Mao
and Gulati

• Sensitize leakage fault

• Detection – 2 transistor terminals with leakage must
have opposite logic values, & be at driving strengths
• Non-driving, high-impedance states won’t work –
current cannot go through them

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Weak Fault Detection – P1 (N1) Open
• Elevates IDDQ from 0 µA to 56 µA

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Second Weak Fault Detection Example
• Not detected unless I3 = 1

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Limitations of IDDQ Testing
• Sub-micron technologies have increased leakage
currents
§ Transistor sub-threshold conduction
§ Harder to find IDDQ threshold separating good & bad
chips
• IDDQ tests work:
§ When average defect-induced current greater than
average good IC current
§ Small variation in IDDQ over test sequence & between
chips
• Now less likely to obtain two conditions
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Delta IDDQ testing (D IDDQ)

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Delta IDDQ Testing -- Thibeault
• Use derivative of IDDQ at test vector i as current
signature
D IDDQ (i) = IDDQ (i) – IDDQ (i – 1)
• Leads to a narrower histogram
• Eliminates variation between chips and
between wafers
• P – probability of false test decisions
Ø For a fault-free chip, only intrinsic variation in IDDQ causes the mean delta IDDQ to be
close to or equal to zero and the variation in deltas to be small.
Ø The screening can be performed if any absolute ΔIDDQ surpasses the maximum
permissible threshold or if the variance in the ΔIDDQ values is too large (consecutive
vector method).
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 IDDQ Versus DIDDQ
Ø Figure shows why DIDDQ testing is better than
IDDQ testing, and why it may significantly extend
the usefulness of current testing.

Ø The DIDDQ histogram is narrower than IDDQ the

histogram data using threshold current.
Ø The IDDQ histogram is affected by chip-to-chip
and wafer-to-wafer variations in current
measurements, which may be larger than
variations in vector-to-vector measurements.
Ø DIDDQ testing eliminates this confusing variation
between chips.
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 Difference in Histograms
• A – test escapes, B – yield loss
Declaring a good IC to be bad results in a yield loss and
declaring a bad IC to be good results in a test escape.

Thibeault compared the probability of false test decisions

P for IDDQ and DIDDQ Testing.

The solid line is the current distribution of good ICs, and

the dashed one is for bad ICs.

Area A represents the test escapes and area B represents

the yield loss.

The vertical line separating A and B is the decision

threshold (x).

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 Example Differential IDDQ Histogram
• Better peak Resolution with
| D IDDQ (i) |, doubles point
Count

This method reduces the effective variance caused by vector-

to-vector
variation during IDDQ tests. The abscissa location of a peak is
usually very close or equal to the average current value caused
by a given defect mechanism.

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IDDQ Built-in Current Testing

• Build current sensor into ground bus of device-

under-test
• Voltage drop device & comparator
§ Compares virtual ground VGND with Vref at end of each
clock – VGND > Vref only in bad circuits
§ Activates circuit breaker when bad device found

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Conceptual BIC Sensor

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CMOS BIC Sensor
The unit has a sense amplifier and a circuit
breaker, and disconnects the defective
functional unit from power when abnormal
currents occur due to VDD-GND shorts or
radiation generated latch-up.

The circuit breaker activates when the virtual

ground voltage becomes sufficiently high to
turn on the inverter in the circuit breaker. This
turns on M9 and turns off M10, which shorts
the base of Q1 to ground to turn it off. A
MOSFET could also be the voltage drop
device.

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Setting Optimal # Transistors in Block
• Must partition chip into functional units, each with its
own BIC
§ Too large a unit – combined leakage currents erroneously
trigger BIC sensor
• Idefmin – smallest defect current
• Inoisemax – maximum noise-related peak supply current
• Minimum area sensor design at Idefmin and IDDQ
intersection
• Nmax – maximum # transistors in 1 BIC unit
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Graph for Choosing Nmax

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Summary
• IDDQ tests improve reliability, find defects causing:
§ Delay, bridging, weak faults
§ Chips damaged by electro-static discharge
• No natural breakpoint for current threshold
§ Get continuous distribution – bimodal would be better
• Conclusion: now need stuck-fault, IDDQ, and delay
fault testing combined
• Still uncertain whether IDDQ tests will remain useful
as chip feature sizes shrink further

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Summary
• IDDQ current limit setting to differentiate between
good and bad circuits is difficult
• IDDQ testing is becoming more problematic
§ Greater leakage currents in MOSFETs in deep sub-
micron technologies
§ Harder to discriminate elevated IDDQ from 100,000
transistor leakage currents
• DIDDQ holds promise to alleviate problems
• Built-in current testing holds promise

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