Digital Clock Design Using Verilog Dhl

2
Table of Contents
1.0 INTRODUCTION ........................................................................................................................... 4
1.1 OBJECTIVES .............................................................................................................................. 4
1.1.1 General Objective: ............................................................................................................ 4
1.1.2 Specific Objectives ............................................................................................................ 4
1.2 OVERVIEW ............................................................................................................................... 4
1.3 Verilog HDL .............................................................................................................................. 4
1.4 Counter .................................................................................................................................... 5
1.5 LED .......................................................................................................................................... 5
1.6 KEY /PUSH BUTTONS ................................................................................................................ 5
2.0 METHODOLOGY ........................................................................................................................... 6
2.1 Compilation ............................................................................................................................. 7
2.2 Pins assignment ....................................................................................................................... 8
2.3 Block diagram .......................................................................................................................... 9
3.0 IMPLEMENTATION ..................................................................................................................... 10
3.1 Verilog HDL codes .................................................................................................................. 11
3.2 Loading verilog HDL codes into Cyclone II FPGA Experiment board. ................... ..................... 14
4.0 RESULTS ..................................................................................................................................... 15
5.0 CONCLUSION ............................................................................................................................. 16
6.0 References ................................................................................................................................. 17

3Table of figures
Figure 1: Full compilation........................................................................................................................
compilation........................................................................................................................ 7
Figure 2: Pins assignment.
ass ignment. .......................................................................................................................
....................................................................................................................... 8
Figure 3: Schematic diagram for digital clock. ..............................................................................
.............................................................................. ............ 9
Figure 4 : Cyclone II FPGA Experiment Board ......................................................................................... 10
Figure 5 : USB-Blaster
..........................................................................................................................
.......................................................................................................................... 14
Figure 6 : Cyclone II FPGA board display the results.
............................................................................ 15

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1.0 INTRODUCTION
Digital clock means clock is using ciphers to display time digitally which is completely differentfrom Analog
Clock, where the time is displayed by mechanical hands. Digital clocks are oftenmade up by electronic drives;
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1.1 OBJECTIVES1.1.1

General Objective:
The main objective of this project was to design and implementation of digital clock usingVerilog HDL.

1.1.2 Specific Objectives

The following were specific objectives1. The designed program must count hours from 00:00 :00 to 23:59:59
using eight sevensegment displays.2.

The digital clock design using Magic SOPC experiment box. That means the pins assignmentmust
assi gnmentmust be finished.

1.2 OVERVIEW
A digital clock has been designed and implemented as presented in this report. It displays thetime
t hetime on seven
segment led displays and time from 00:00:00 to 23:59:59 .Which means it displayhours,
displa yhours, minutes, and seconds
.It made up by 7 segment LED patterns with
wit h two bits key enablesignal, 25 bits Counters, Registers.
 

1.3 Verilog HDL

To make this digital clock to work properly we used Verilog language to program each andevery device. All
enable signal are active low (enabled when a signal is 0) and if enable signal isfast enough the human eyes
cannot distinguish the between ON/OFF interval of the LEDs andperceives that all displays are lit
simultaneously. To supply a 1Hz signal to the concurrentalways blocks, one can make use of a counter that
receives a 50MHz clock from the onboardclock source.

1.4 Counter

Apart from the clock there is counter which plays a major role in this project. It was used tocount and increment
the output before next state to occur during display of seven segmentdisplay and normally works on positive
edge clock. Counters in the tens place resent onachieving a value of 5, 5 and 2 (with the units counter on 3) for seconds, minutes
and hoursrespectively. This is because the LED accepts only one character at a time, and converting abinary
number into a two decimal digit number. The three counters are updated using the samemethod of concurrent
always blocks and a counter generating a 1Hz signal.

1.5 LED
To display data on the LED, one needs to first initialize the LED on power-on. The LED connectsto the FPGA
through a 4-bit data bus and three control bits. Since the data bus is also sharedwith the onboard Magic SOPC, it
is necessary to write a logical high bit at all times while usingthe LED. A schematic diagram is given in the
th e user
manual, which has been reproduced here forconvenience.

The three most significant bits are decoded to generate the enable signal and areused as the selection signal for
multiplexing .As it shown on program codes in section 2.0 weuse timing of 0.5second
0 .5second for 50Hz to count up by
increment of 1 bit and when it reachesmaximum bit value {25 bits} it clear the counter to zero and start again to
count. The threemost significant bits are decoded to generate the enable signal and are used as the
selectionsignal for multiplexing.

1.6 KEY /PUSH BUTTONS

Using the push button switches SET or KEY, we set the desired time and the set time could beseen on the
seven-segment LED displays. Every time a push button is pressed,
pr essed, thecorresponding display advances by one.
By pressing the button continuously for more than 2 s,the displays
dis plays advance fast. The figure 1 below show the
six seven segment display and threepush button named SET. In this system, hours, minutes, and seconds can be
set by pushbuttons. We need three independent push button switches to set them.

Six seven segment display and three push button (SET)

2.0 METHODOLOGY
 

This section presents the methods used to implement the design of a digital clock. HardwareDescriptive
Language used in the design of digital clock and implemented using the Magic SOPCexperiment box. Typical
digital clocks applied were of the 50 or 60 hertzo
6 0 hertzoscillation of  AC
AC  power 
 power or a 32,768 hert
hertzzcrystal oscillator as in
aquartz clock to keep time, a frequency of 1 Hertz was used in this particular experiment. MostMos t digital
digitalcclocks
display the hour of the dayin
dayin24 hour format.A
format. A more commonly used hour sequence option is is12 hour format(
format(with
some indication of AM or PM). Emulations of analog-style faces often use an LCDsscreen, and theseare also
a nLCD
sometimes described as digital.

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2.1 Compilation
Here is where .v file named as clock (clock.v) is simulated
si mulated to see whether the written Verilogcodes had some
errors or not. The figure below presents the full compilation of the Verilogcodes for the digital clock which was
successful compiled as it shown below.

Figure 1: Fullcompilation.

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2.2 Pins assignment
The diagram below shows how pins where assigned ready for download into SOPC board forimplementation.