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Compal La-9531p r0.2 Schematics
Compal La-9531p r0.2 Schematics
Compal Confidential
Model Name : V5WE2/T2/C2 (EA/EG/BA50_HW)
File Name : LA-9531P
1 1
Compal Confidential
2 2
3 2012-12-03 3
REV:0.2
4 4
ZZZ
Part Number Description
CRT Conn.
Fan Control
page 27 page 36
port 4 port 5
Lynx Point - LP USB port 0 USB/B (port 1,2) USB port 5
2
Flexible IO
page 32 page 32 page 24
PCH
PCIe 2.0 48MHz
5GT/s USBx8
SATA3.0 SATA3.0
port 3 6.0 Gb/s 6.0 Gb/s
port 0 port 2 HD Audio 3.3V 24MHz
3
Card Reader LPC BUS 3
2 in 1 SPI ROM x2
(SD/MMC) CLK=24MHz Int. Speaker Int. MIC Combo Jack
page 29 page 7
ENE page 35 page 35 page 35
KB9012/KB932
page 33
LS-9532P EC ROM x1
4
DC/DC Interface CKT. USB/B (port 1,2) (KB932)
4
page 33
page 37 page 32
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
+0.675VS +0.675VSP to +0.675VS switched power rail for DDR terminator ON OFF OFF Board ID / SKU ID Table for AD channel
+1.05VSDGPU +1.0VSDGPU switched power rail for GPU ON OFF OFF Vcc 3.3V +/- 5%
+0.95VSDGPU +0.95VSDGPUP to +0.95VSDGPU switched power rail for CPU ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.35V +1.35VP to +1.35V power rail for DDRIIIL ON ON OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+1.5VSDGPU +1.5VSDGPUP to +1.5VSDGPU switched power rail for GPU ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+1.8VS +3VS to 1.8V switched power rail to CPU ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+1.8VSDGPU +1.8VS to +1.8VSDGPU switched power rail for GPU ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VALW +3VALW always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VLP B+ to +3VLP power rail for suspend power ON ON ON 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+3VS +3VALW to +3VS power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+3VSDGPU +3VS to +3VSDGPU switched power rail for GPU ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V
+5VALW +5VALWP to +5VALW power rail ON ON ON*
+5VS +5VALW to +5VS switched power rail ON OFF OFF
BOARD ID Table BTO Option Table
2 2
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* BTO Item BOM Structure
+RTCVCC RTC power ON ON ON Board ID PCB Revision Unpop @
0 0.1 Connector CONN@
1 0.2 EC 940 940@
2 0.3 EC 9012 9012@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. 3 1.0
4 AMD GPU VGA@
EC SM Bus1 address EC SM Bus2 address 5 Mars component MARS@
6 SUN component SUN@
Device Address Device Address
Smart Battery 0001 011X On Board Thermal Senser 0100 110x
7 VRAM Selection X76@
VGA Internal Thermal Senser 0100 000x
VRAM x 8pcs 128@
USB Port Table
G Senser 0011 000x
3 External
PCH SM Bus address USB 2.0 Port
USB Port
0 USB Port(Left 3.0)
Device Address
ChannelA DIMM0 1001 000x JDIMM1
1 USB Port(Right 2.0) TPM Module TPM@
3 3
ChannelB DIMM1 1001 010x JDIMM2
2 USB Port(Right 2.0) G-Sensor GSEN@
3 KB Backlight BL@
EHCI1
4 Mini Card (WLAN+BT)
5
6
7 Camera Debug Only DEG@
HASWELL_MCP_E
U1A
C54 C45
27 CPU_DP1_N0 DDI1_TXN0 EDP_TXN0 EDP_TXN0 25
C55 B46
27 CPU_DP1_P0 DDI1_TXP0 EDP_TXP0 EDP_TXP0 25
B58 A47
27 CPU_DP1_N1 DDI1_TXN1 EDP_TXN1 EDP_TXN1 25
C58 B47
DP to CRT 27 CPU_DP1_P1
B55 DDI1_TXP1
DDI1_TXN2
EDP_TXP1 EDP_TXP1 25
A55 C47
A57 DDI1_TXP2 EDP_TXN2 C46
B57 DDI1_TXN3 EDP_TXP2 A49
DDI1_TXP3 DDI EDP EDP_TXN3 B49
D D
C51 EDP_TXP3
26 CPU_DP2_N0 DDI2_TXN0
C50 A45 EDP_AUXN 25
26 CPU_DP2_P0 DDI2_TXP0 EDP_AUXN
C53 B45 EDP_AUXP 25
26 CPU_DP2_N1 DDI2_TXN1 EDP_AUXP
B54
HDMI 26
26
CPU_DP2_P1
CPU_DP2_N2
C49 DDI2_TXP1
DDI2_TXN2 EDP_RCOMP
D20 EDP_COMP R1 1 2 24.9_0402_1% +VCCIOA_OUT
B50 A43 Trace width=20 mils,Spacing=25mil,Max length=100mils
26 CPU_DP2_P2 DDI2_TXP2 EDP_DISP_UTIL
A53
26 CPU_DP2_N3 DDI2_TXN3
B53
26 CPU_DP2_P3 DDI2_TXP3 EDP_DISP_UTIL 25
1 OF 19 Rev1p2
HASW ELL-MCP-E-ULT_BGA1168
@
C94 1 2 6.8P_0402_50V8C
XEMC@ T20 @ D61
T2 @ K61 PROC_DETECT MISC
N62 CATERR J62 XDP_PRDY#_R @ T157
+1.35V 34 H_PECI PECI PRDY K62 XDP_PREQ#_R @ T158
2 1 R68 R8 JTAG
PREQ E60 XDP_TCK_R @ T159
+1.05VS_VTT PROC_TCK
62_0402_5% 56_0402_5% E61 XDP_TMS_R @ T160
1 2 H_PROCHOT#_R K63 PROC_TMS E59 XDP_TRST#_R @ T161
34,39,40 H_PROCHOT# PROCHOT PROC_TRST
THERMAL F63 XDP_TDI_R @ T162
PROC_TDI
1
B B
A A
U1 U1 U1 U1 U1
HASWELL_MCP_E
U1C
HASWELL_MCP_E
U1D
16 DDR_B_DQS[0..7]
3 OF 19 Rev1p2
HASW ELL-MCP-E-ULT_BGA1168 4 OF 19 Rev1p2
@ HASW ELL-MCP-E-ULT_BGA1168
@
A A
PCH_RTCX1
1 2 HASWELL_MCP_E
PCH_RTCX2 U1E
R101 10M_0402_5% +RTCVCC
1
C149
Y1 +RTCVCC 1U_0402_10V6K ME CMOS PCH_RTCX1 AW5
32.768KHZ_12.5PF_FC-135 PCH_RTCX2 AY5 RTCX1
2 1 R69 2 R72 1 2 1M_0402_5% SM_INTRUDER# AU6 RTCX2 J5
INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0 32
20K_0402_1% PCH_INTVRMEN AV7 RTC H5 SATA_PRX_DTX_P0 32
1 2 AV6 INTVRMEN SATA_RP0/PERP6_L3 B15
PCH_SRTCRST#
SRTCRST SATA_TN0/PETN6_L3 SATA_PTX_DRX_N0 32 HDD
1 2 PCH_RTCRST# AU7 A15
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 32
1 1 R70
1
D C153 C154 20K_0402_1% 1 J8 SATA_PRX_DTX_N1 32 D
18P_0402_50V8J 18P_0402_50V8J C150 R71 SATA_RN1/PERN6_L2 H8
SATA_RP1/PERP6_L2 SATA_PRX_DTX_P1 32 ODD
1U_0402_10V6K @ 0_0603_5% A17
2 2 SATA_TN1/PETN6_L2 SATA_PTX_DRX_N1 32
B17
2 CMOS SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 32
2
HDA_BIT_CLK AW8 J6
HDA_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
HDA_RST# AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14
HDA_SDIN0 AY10 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15
36 HDA_SDIN0 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
T6 @ AU12 AUDIO SATA
HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
+RTCVCC RTCRST close RAM door T7 @ AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5
T8 @ AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17 R937
T9 @ AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 0_0402_5%
PCH_INTVRMEN R73 1 2 330K_0402_5% I2S1_SCLK SATA_TP3/PETP6_L0 1 2 EC_SCI# 34,9
R74 1 @ 2 330K_0402_5%
V1 PCH_GPIO34
:
SATA0GP/GPIO34 PCH_GPIO34 9
INTVRMEN U1 PCH_GPIO35
:
SATA1GP/GPIO35 PCH_GPIO35 9
* H Integrated VRM enable
L Integrated VRM disable SATA2GP/GPIO36
V6
AC1
PCH_GPIO36
PCH_GPIO37
PCH_GPIO36 9
+1.05VS_ASATA3PLL
SATA3GP/GPIO37 PCH_GPIO37 9
T95 @
PCH_JTAG_RST# AU62
51_0402_5% 1 @ 2 R97 PCH_JTAG_TCK AE62 PCH_TRST A12 SATA_IREF R75 1 2 0_0603_5%
T21 @ PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11 @ T13
T19 @ PCH_JTAG_TDO AE61 PCH_TDI RSVD K10 @ T14
PCH_TDO RSVD within 500 mils
T15 @ PCH_JTAG_TMS AD62 JTAG C12 SATA_RCOMP R2 1 2 3.01K_0402_1%
T10 @ AL11 PCH_TMS SATA_RCOMP U3 PCH_SATALED#
RSVD SATALED PCH_SATALED# 35
T11 @ AC4
T22 @ PCH_TCK_JTAGX AE63 RSVD R10 1 2
HDA for AUDIO T12 @ AV2 JTAGX 10K_0402_5%
+3VS
C RP14 EMC@ RSVD C
36 HDA_BITCLK_AUDIO 1 8 HDA_BIT_CLK
36 HDA_SYNC_AUDIO 2 7 HDA_SYNC
36 HDA_RST_AUDIO# 3 6 HDA_RST#
36 HDA_SDOUT_AUDIO 4 5 HDA_SDOUT 5 OF 19 Rev1p2
HASW ELL-MCP-E-ULT_BGA1168
33_0804_8P4R_5% @
ME Debug
B B
+RTCBATT
+RTCBATT
2
+CHGRTC
R446
+
1K_0402_5%
3 1
+RTCBATT_R
2
20mil
20mil
+RTCVCC
D32
1
CHN202UPT_SC70-3 JBATT1
-
1 LOTES_AAA-BAT-054-K01
2
C168 CONN@
0.1U_0402_16V4Z SP07000H700
A 2 A
HASWELL_MCP_E
U1F
PCH_GPIO23 T2
9 PCH_GPIO23 PCIECLKRQ5/GPIO23
R216
10K_0402_5%
@ 6 OF 19 Rev1p2
HASW ELL-MCP-E-ULT_BGA1168
2
VGA_CLKREQ# @
1
HASWELL_MCP_E
U1G
R221
10K_0402_5% LPC_AD0 AU14 AN2 SMB_ALERT#
34,35 LPC_AD0 LAD0 SMBALERT/GPIO11 SMB_ALERT# 34,9
LPC_AD1 AW12 AP2 PCH_SMBCLK
34,35 LPC_AD1 LAD1 SMBCLK PCH_SMBCLK 31
LPC_AD2 AY12 LPC AH1 PCH_SMBDATA
34,35 LPC_AD2 PCH_SMBDATA 31
2
2
R305 1 9012@ 2 0_0402_5%
R116 R119
2
B DMN66D0LDW -7_SOT363-6 B
C66 1 2 0.1U_0402_16V7K
1
U6 PCH_SMBDATA 6 1 D_CK_SDATA D_CK_SDATA 15,16,35
PCH_SPI_CS0# 1 8 RP19
CS# VCC
5
PCH_SPI_MISO_1 2 7 PCH_SPI_IO3_1 PCH_SPI_MOSI_1 1 8 PCH_SPI_MOSI
PCH_SPI_W P1# 33_0402_5% 2 1 R108 PCH_SPI_IO2_1 3 DO(IO1) HOLD#(IO3) 6 PCH_SPI_CLK_1 PCH_SPI_CLK_1 2 7 PCH_SPI_CLK
4 WP#(IO2) CLK 5 PCH_SPI_MOSI_1 PCH_SPI_IO3_1 3 6 PCH_SPI_HOLD1# PCH_SMBCLK 3 4 D_CK_SCLK
GND DI(IO0) D_CK_SCLK 15,16,35
PCH_SPI_MISO_1 4 5 PCH_SPI_MISO
EN25QH16-104HIP_SO8 EMC@ Q7B
9012@ 33_0804_8P4R_5% DMN66D0LDW -7_SOT363-6
+BIOS_SPI C152
Reserve for EMI(Near SPI ROM)
10P_0402_50V8J
R103 1 2 1K_0402_5% PCH_SPI_HOLD1# 1 2 2 1 PCH_SPI_CLK_1 +3VS
R102 1 9012@ 2 1K_0402_5% PCH_SPI_W P1# R104 XEMC@ 33_0402_5%
32,34,6 SPI_W P1#_R R564 1 940@ 2 1K_0402_5% XEMC@
Q8A
2
+3VS DMN66D0LDW -7_SOT363-6
PU 2.2K at EC side (+3VS)
C67 1 2 0.1U_0402_16V7K SML1CLK 6 1 EC_SMB_CK2 18,24,34,37
U7
5
PCH_SPI_CS1# 1 8 RP20
PCH_SPI_MISO_2 2 CS# VCC 7 PCH_SPI_IO3_2 PCH_SPI_MOSI_2 1 8 PCH_SPI_MOSI
PCH_SPI_W P1# 33_0402_5% 2 9012@ 1 R109 PCH_SPI_IO2_2 3 DO HOLD# 6 PCH_SPI_CLK_2 PCH_SPI_CLK_2 2 7 PCH_SPI_CLK SML1DATA 3 4
WP# CLK EC_SMB_DA2 18,24,34,37
4 5 PCH_SPI_MOSI_2 PCH_SPI_IO3_2 3 6 PCH_SPI_HOLD1#
GND DI PCH_SPI_MISO_2 4 5 PCH_SPI_MISO Q8B
EN25QH32-104HIP_SO8 DMN66D0LDW -7_SOT363-6
9012@ 33_0804_8P4R_5%
C453
Reserve for EMI(Near SPI ROM)
U6 10P_0402_50V8J
1 2 2 1 PCH_SPI_CLK_2
R402 XEMC@ 33_0402_5%
XEMC@
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/07/10 2013/07/10 Title
MX25L6406EM2I-12G_SO8
Issued Date Deciphered Date HSW MCP(4/11) CLK,SPI,SMBUS
940@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SA00004G600 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 7 of 51
5 4 3 2 1
5 4 3 2 1
+3VS
1
R227
* HL:
DSWODVREN - On Die DSW VR Enable
:Enable(DEFAULT)
10K_0402_5%
Disable
2
R59 1 DEG@ 2 0_0402_5% SYS_RESET# +RTCVCC
32 XDP_DBRESET#
PU at Page 4 (double PU)
HASWELL_MCP_E
U1H
D R124 1 2 330K_0402_5% D
R125 1 @ 2 330K_0402_5%
R206 SYSTEM POWER MANAGEMENT
PM_APW ROK R64 1 2 0_0402_5% PCH_PW ROK_R SUSW ARN# 1 @ 2 0_0402_5% SUSACK# AK2 AW7 DSW ODVREN
SYS_RESET# AC3 SUSACK DSWVRMEN AV5 PCH_RSMRST#_R
SYS_PW ROK R61 1 @ 2 0_0402_5% SYS_PW ROK_R AG2 SYS_RESET DPWROK AJ5 PCH_PCIE_W AKE#
SYS_PWROK WAKE PCH_PCIE_W AKE# 29
34 PCH_PW ROK R62 1 2 0_0402_5% PCH_PW ROK_R AY7 1K_0402_5% 1 2 R120 +3VALW _PCH
R63 1 @ 2 0_0402_5% PM_APW ROK AB5 PCH_PWROK 8.2K_0402_5% 1 2 R157
11,34 VCCST_PG_EC APWROK +3VS
34 PBTN_OUT# R110 1 @ 2 PBTN_OUT#_R PLT_RST# AG7 V5 CLKRUN# CLKRUN# 35
34,35 PLT_RST# PLTRST CLKRUN/GPIO32
0_0402_5% AG4 LPCPD#
SUS_STAT/GPIO61 LPCPD# 35
AE6 SUSCLK
SUSCLK/GPIO62 SUSCLK 34
AP5 PM_SLP_S5#
SLP_S5/GPIO63 PM_SLP_S5# 34
34 PCH_RSMRST# R79 1 @ 2 0_0402_5% PCH_RSMRST#_R AW6 @ T27
PCH_RSMRST# R117 1 2 10K_0402_5% SUSW ARN# AV4 RSMRST @ T28 @ T29
9 SUSW ARN# SUSWARN/SUSPWRDNACK/GPIO30
PBTN_OUT#_R AL7 AJ6 PM_SLP_S4#
PWRBTN SLP_S4 PM_SLP_S4# 34
Note: EC is +3VL change to @ PCH_ACIN AJ8 AT4 PM_SLP_S3#
ACPRESENT/GPIO31 SLP_S3 PM_SLP_S3# 34
+3VALW _PCH R156 1 2 8.2K_0402_5% PCH_BATLOW # AN4 AL5 @ T30
T31 @ AF3 BATLOW/GPIO72 SLP_A AP4 @ T96
AM5 SLP_S0 SLP_SUS AJ7 PM_SLP_LAN# R118 1 @ 2
SLP_WLAN/GPIO29 SLP_LAN +3VALW _PCH
10K_0402_5%
+3VALW_PCH
8 OF 19 Rev1p2
R245 Note: Deep Sx need use EC GPIO for HASW ELL-MCP-E-ULT_BGA1168
100K_0402_5% ACPRESENT function @
@ DDPB_CTRLDATA: Port B Detected
@ D21
2
R65
2 HASWELL_MCP_E
PCH_PW ROK 0_0402_5% U1I
P
U43
3
DDPC_CTRLDATA
EC_SMI# U6
34 EC_SMI# PIRQA/GPIO77
VGA_ON P4 C5 DDI1_AUX_DN
+3VS 38,9 VGA_ON PIRQB/GPIO78 DDPB_AUXN DDI1_AUX_DN 27
DGPU_HOLD_RST# N4 DISPLAY B6
9 DGPU_HOLD_RST# PIRQC/GPIO79 DDPC_AUXN
35 TP_INT# TP_INT# N2 B5 DDI1_AUX_DP
PIRQD/GPIO80 DDPB_AUXP DDI1_AUX_DP 27
+1.05VS_VTT T26 @ AD4 A6
PME DDPC_AUXP
1
GPIO
U17 R310 PCH_GPIO55 U7
9 PCH_GPIO55 GPIO55
1 5 10K_0402_5% PCH_GPIO52 L1
NC VCC @ Project_ID1 L3 GPIO52 C8
GPIO54 DDPB_HPD CPU_DP_HPD 27
11,46 VGATE 2 PCH_GPIO51 R5 A8 CPU_HDMI_HPD 26
9 PCH_GPIO51
2
5
VCC
PLT_RST# 1
VCC
IN1 4 PLT_RST# 1
OUT PLTRST_VGA# 17 IN1
DGPU_HOLD_RST# 2 4
GND
GND
IN2
1
1
R391 R416
3
3
+3VS +3VS MC74VHC1G08DFT2G_SC70-5 VGA@ U30
VGA@ MC74VHC1G08DFT2G_SC70-5
2
2
1
A A
R205 R204
10K_0402_5% 10K_0402_5% Project_ID1 Project_ID0
@ @ Project ID
GPIO54 GPIO53
2
Project_ID1 Project_ID0
V5WE2/T2 UMA 0 0
Security Classification Compal Secret Data Compal Electronics, Inc.
2
R214 R215
*V5WE2/T2 DIS 0 1 2012/07/10 2013/07/10 Title
10K_0402_5% 10K_0402_5%
V5WV2 1 0
Issued Date Deciphered Date HSW MCP(5/11) PM,GPIO,DDI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
x 1 1
1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 8 of 51
5 4 3 2 1
5 4 3 2 1
+3VS
+3VS
RP23 1 8 PCH_GPIO51 PCH_GPIO51 8
2 7 PCH_GPIO83
3 6 PCH_GPIO55 PCH_GPIO55 8 RP36 1 8 PCH_GPIO88
4 5 SERIRQ 2 7 PCH_GPIO92 +1.05VS_VTT
10K_0804_8P4R_5% 3 6 PCH_GPIO85
RP24 1 8 EC_IN_RW 4 5 PCH_GPIO39
1
2 7 HASWELL_MCP_E
PCH_GPIO69 10K_0804_8P4R_5% U1J
3 6 PCH_GPIO4 R144
4 5 PCH_GPIO7 1K_0402_5%
D 10K_0804_8P4R_5% D
RP25 1 8 PCH_GPIO5
2
2 7 PCH_GPIO1 PCH_GPIO76 P1 D60 H_THERMTRIP#
3 6 PCH_GPIO94 PCH_GPIO8 AU2 BMBUSY/GPIO76 THERMTRIP V4
GPIO8 RCIN/GPIO82 EC_KBRST# 34
4 5 PCH_GPIO93 AM7 T4 SERIRQ SERIRQ 34,35
10K_0804_8P4R_5% EC_LID_OUT# AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 PCH_OPIRCOMP 1 2 R145
34 EC_LID_OUT# GPIO15 PCH_OPI_RCOMP
RP26 1 8 PCH_GPIO2 PCH_GPIO16 Y1 MISC AF20 @ T106 49.9_0402_1%
2 7 PCH_GPIO91 PCH_GPIO17 T3 GPIO16 RSVD AB21 @ T32
3 6 PCH_GPIO90 PCH_GPIO24 AD5 GPIO17 RSVD
4 5 PCH_GPIO38 PCH_GPIO27 AN5 GPIO24
10K_0804_8P4R_5% PCH_GPIO28 AD7 GPIO27
RP16 1 8 PCH_GPIO19 PCH_GPIO26 AN3 GPIO28
PCH_GPIO19 7 GPIO26
2 7 PCH_GPIO36 PCH_GPIO36 6 R6 PCH_GPIO83
3 6 VGA_ON PCH_GPIO56 AG6 GSPI0_CS/GPIO83 L6 PCH_GPIO84
VGA_ON 38,8 GPIO56 GSPI0_CLK/GPIO84
4 5 EC_KBRST# PCH_GPIO57 AP1 N6 PCH_GPIO85
10K_0804_8P4R_5% PCH_GPIO58 AL4 GPIO57 GSPI0_MISO/GPIO85 L8 PCH_GPIO86
RP28 1 8 PCH_GPIO18 PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 DGPU_PRSNT#
PCH_GPIO18 7 GPIO59 GSPI1_CS/GPIO87
2 7 PCH_GPIO35 PCH_GPIO35 6 PCH_GPIO44 AK4 L5 PCH_GPIO88
3 6 PCH_GPIO48 PCH_GPIO47 AB6 GPIO44 GPIO GSPI1_CLK/GPIO88 N7 PCH_GPIO89
4 5 PCH_GPIO34 PCH_GPIO48 U4 GPIO47 GSPI1_MISO/GPIO89 K2 PCH_GPIO90
PCH_GPIO34 6 GPIO48 GSPI_MOSI/GPIO90
10K_0804_8P4R_5% PCH_GPIO49 Y3 J1 PCH_GPIO91
RP29 1 8 PCH_GPIO71 PCH_GPIO50 P3 GPIO49 UART0_RXD/GPIO91 K3 PCH_GPIO92
2 7 PCH_GPIO49 PCH_GPIO71 Y2 GPIO50 UART0_TXD/GPIO92 J2 PCH_GPIO93
3 6 PCH_GPIO16 PCH_GPIO13 AT3 HSIOPC/GPIO71 LPIO UART0_RTS/GPIO93 G1 PCH_GPIO94
4 5 PCH_GPIO37 PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 PCH_GPIO0
PCH_GPIO37 6 GPIO14 UART1_RXD/GPIO0
10K_0804_8P4R_5% PCH_GPIO25 AM4 G2 PCH_GPIO1
PCH_GPIO45 AG5 GPIO25 UART1_TXD/GPIO1 J3 PCH_GPIO2
RP30 8 1 PCH_GPIO67 PCH_GPIO46 AG3 GPIO45 UART1_RST/GPIO2 J4 PCH_GPIO3
7 2 PCH_GPIO65 R66 GPIO46 UART1_CTS/GPIO3 F2 PCH_GPIO4
C 6 3 PCH_GPIO6 0_0402_5% PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 PCH_GPIO5 C
5 4 PCH_GPIO64 EC_SCI# 1 @ 2 PCH_GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 G4 PCH_GPIO6
34,6 EC_SCI# GPIO10 I2C1_SDA/GPIO6
10K_0804_8P4R_5% DEVSLP0 P2 F1 PCH_GPIO7
32,8 DEVSLP0 DEVSLP0/GPIO33 I2C1_SCL/GPIO7
RP31 8 1 PCH_GPIO84 PCH_GPIO70 C4 E3 PCH_GPIO64
7 2 PCH_GPIO0 PCH_GPIO38 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 PCH_GPIO65
6 3 PCH_GPIO3 PCH_GPIO39 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66
5 4 PCH_GPIO89 PCH_SPKR V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 PCH_GPIO67
36 PCH_SPKR SPKR/GPIO81 SDIO_D1/GPIO67
10K_0804_8P4R_5% C3 EC_IN_RW EC_IN_RW 35
RP32 8 1 PCH_GPIO17 SDIO_D2/GPIO68 E2 PCH_GPIO69
7 2 PCH_GPIO23 SDIO_D3/GPIO69
PCH_GPIO23 7
6 3 PCH_GPIO76 10 OF 19 Rev1p2
5 4 PCH_GPIO50 HASW ELL-MCP-E-ULT_BGA1168
10K_0804_8P4R_5% @
R311 1 2 PCH_GPIO70
10K_0402_5%
+3VALW _PCH
RP34 1 8 PCH_GPIO10
2 7 SMB_ALERT#
SMB_ALERT# 34,7
3 6 SUSW ARN#
SUSW ARN# 8
4 5 TP_W AKE#
TP_W AKE# 10,35 +3VALW _PCH
10K_0804_8P4R_5%
RP35 8 1 PCH_GPIO8 +3VALW _PCH
7 2 USB_OC1#
USB_OC1# 10
6 3 PCH_GPIO13 +3VS
1
5 4 PCH_GPIO26
10K_0804_8P4R_5% R301 R303 R269 1 @ 2 1K_0402_1% PCH_SPKR
B RP37 1 8 PCH_GPIO45 10K_0402_5% 10K_0402_5% B
+3VS 2 7 PCH_GPIO14
3 6 PCH_GPIO44
2
4 5 PCH_GPIO46 PCH_GPIO56 PCH_GPIO57
10K_0804_8P4R_5% SPKR / GPIO81 : NO REBOOT
RP38 1 8 DGPU_HOLD_RST# DGPU_HOLD_RST# 8
2 7 PCH_GPIO47
3 6 PCH_GPIO24 1: ENABLED
4 5 PCH_GPIO28
10K_0804_8P4R_5% 0: DISABLED (Have internal PD)
RP39 1
2
8
7
PCH_GPIO58
PCH_GPIO59 *
3 6 PCH_GPIO27
4 5 PCH_GPIO25
10K_0804_8P4R_5%
RP40 1 8 USB_OC2# USB_OC2# 10
2 7 PCH_GPIO60 PCH_GPIO60 7
3 6 USB_OC0# +3VALW _PCH +3VS
USB_OC0# 10,33
4 5 PCH_GPIO9 PCH_GPIO66 R270 1 @ 2 1K_0402_1%
10K_0804_8P4R_5% PCH_GPIO86 R272 1 @ 2 1K_0402_1%
R248 1 2 PCH_GPIO73 R247 1 @ 2 10K_0402_5% EC_LID_OUT# R273 1 2 1K_0402_5%
PCH_GPIO73 7
10K_0402_5%
GPIO15 : TLS Confidentiality GSPI0_MOSI / GPIO86 : Boot BIOS Strap SDIO_D0 / GPIO66 : Top-Block Swap Override
+3VS
1: Intel ME TLS with confidentiality 1: ENABLED 1: ENABLED
1
R306 0: Intel ME TLS with no confidentiality 0: SPI ROM (Have internal PD) 0: DISABLED (Have internal PD)
A
10K_0402_5%
@ * (Have internal PD)
* * A
2
DGPU_PRSNT#
GPIO87
DGPU_PRSNT# Security Classification Compal Secret Data Compal Electronics, Inc.
2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 9 of 51
5 4 3 2 1
5 4 3 2 1
HASWELL_MCP_E
U1K
B B
A A
4
VDDQ VCC E39
1 @ 2 F59 VCC E41
38 3VS_GATE VCC VCC
T39 @ N58 E43
R182 +VCCIO_OUT T40 @ AC58 RSVD VCC E45
1 RSVD VCC
0_0402_5% C5 +1.05VS_VTT E47
0.1U_0603_25V7K VCC_SENSE_R E63 VCC E49
@ R164 T41 @ AB23 VCC_SENSE VCC E51
2 2 @ 1 0_1206_5% A59 RSVD VCC E53
E20 VCCIO_OUT VCC E55
+VCCIOA_OUT VCCIOA_OUT VCC
T42 @ AD23 E57
T43 @ AA23 RSVD VCC F24
T44 @ AE59 RSVD VCC F28
RSVD VCC F32
H_CPU_SVIDALRT# L62 VCC F36
0_0402_5% 1 @ 2 R165 H_CPU_SVIDCLK N63 VIDALERT VCC F40
46 VR_SVID_CLK VIDSCLK VCC
VIDSOUT L63 F44
+3VS VCCST_PG_EC_R B59 VIDSOUT HSW ULT POWER VCC F48
+1.05VS_VTT 0_0402_5% 1 2 R167 PCH_VR_EN F60 VCCST_PWRGD VCC F52
46 VR_ON VR_EN VCC
46,8 VGATE 0_0402_5% 1 2 R168 VR_READY C59 F56
VR_READY VCC
1
1
R422 1 2 0.1U_0402_16V7K D63 G25
100K_0402_5% U16 R309 CPU_PW R_DEBUG H59 VSS VCC G27
@ 1 5 10K_0402_5% Reserved Only P62 PWR_DEBUG VCC G29
NC VCC R166 T45 @ P60 VSS VCC G31
2
2
+1.05VS_VTT T145 @ U59 G53
R169 T146 @ V59 RSVD VCC G55
SVID ALERT 150_0402_1% RSVD VCC
VCC
G57
@ AC22 H23
1 +CPU_CORE AE22 VCCST VCC J23
+1.05VS_VTT AE23 VCCST VCC K23
VCCST VCC K57
Place the PU CPU_PW R_DEBUG
VCC
AB57 L22
resistors close to CPU VCC VCC
1
AD57 M23
VCC VCC
2
2 1 H_CPU_SVIDALRT# 12 OF 19 Rev1p2
46 VR_ALERT#
HASW ELL-MCP-E-ULT_BGA1168
@
+1.35V_CPU
B B
SVID DATA VDDQ DECOUPLING
+1.05VS_VTT
Place the PU
resistors close to CPU
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1
C8
C9
C10
C11
R173 @ @ @ + C18
C12
C13
C14
C15
C16
C17
130_0402_1% 330U_2.5V_M
R174 2 2 2 2 2 2 2 2 2 2 2
2
0_0402_5%
2 @ 1 VIDSOUT +1.05VS_VTT
46 VR_SVID_DATA
+CPU_CORE
1U_0402_6.3V6K
@
22U_0805_6.3V6M
1 1
1
C7
C6
R177
100_0402_1% Note: 0 ohm PLACED CLOSE TO CPU @
2 2
+1.35V : 470UF/2V/7343 *2
10UF/6.3V/0603 * 6
2
VCC_SENSE_R 2 @ 1 R178
VCC_SENSE 46
0_0402_5% 2.2UF/6.3V/0402 * 4
A A
13 VSS_SENSE_R 2 @ 1 R235
VSS_SENSE 46
0_0402_5%
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 11 of 51
5 4 3 2 1
5 4 3 2 1
+1.05VS_VTT HASWELL_MCP_E
U1M
1U_0402_6.3V6K
M9 VCCHSIO C30 1 2 1U_0402_6.3V6K
1U_0402_6.3V6K
N8 VCCHSIO mPHY AH11
P9 VCC1_05 RTC VCCSUS3_3 AG10
1 1 1
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
VCC1_05 VCCRTC +RTCVCC
+1.05VS_AUSB3PLL B18 AE7 +VCCRTCEXT 1 2 1 1 1
VCCUSB3PLL DCPRTC
C21
C20
C31 +1.05VS_ASATA3PLL B11 C54 0.1U_0402_16V7K @ @
VCCSATA3PLL +3VS
C52
C51
C50
1U_0402_6.3V6K
2 2 2
@ 2 2 2
T99 @ Y20 SPI Y8 C58 2 1 0.1U_0402_16V7K
AA21 RSVD OPI VCCSPI @
D +1.05VS_APLLOPI D
W21 VCCAPLL
Near K9 Near L10 Near M9
VCCAPLL AG14
VCCASW +1.05VS_VTT
AG13
+3VALW _PCH VCCASW
+1.05VS_VTT
HDA --> 3.3V or 1.5V T105 @ J13 USB3
+1.05VS_VTT +1.05VS_AUSB3PLL I2C --> 1.8V DCPSUS3 J11 C27 1 2 10U_0603_6.3V6M
Near B18 VCC1_05 H11 C33 1 2 1U_0402_6.3V6K
C42 1 2 1U_0402_6.3V6K 2 1 C38 AH14 AXALIA/HDA VCC1_05 H15 C40 1 2 1U_0402_6.3V6K
L1 1 2 C32 1 2 100U_1206_6.3V6M 1U_0402_6.3V6K VCCHDA VCC1_05 AE8 C41
2.2UH_LQM2MPN2R2NG0L_30% VCC1_05 AF22 1U_0402_6.3V6K
Idc 1.2A Rdc 0.11ohm +/-30% T116 @ AH13 VRM/USB2/AZALIA VCC1_05 AG19 +PCH_VCCDSW 1 @ 2+PCH_VCCDSW _R 1 2
DCPSUS2 CORE DCPSUSBYP AG20 R209 0_0402_5%
+1.05VS_ASATA3PLL +3VALW _PCH DCPSUSBYP AE9
VCCASW +1.05VS_VTT
C28 AF9 C36 1 2 22U_0805_6.3V6M
Near B11 Near AC9 2 1 22U_0805_6.3V6M AC9 VCCASW AG8 C37 1 2 1U_0402_6.3V6K
C46 1 2 1U_0402_6.3V6K C59 @ AA9 VCCSUS3_3 VCCASW AD10 C43 @1 2 1U_0402_6.3V6K
L2 1 2 C61 1 2 100U_1206_6.3V6M Near AH10 2 1 0.1U_0402_16V7K AH10 VCCSUS3_3 DCPSUS1 AD8
2.2UH_LQM2MPN2R2NG0L_30% C29 V8 VCCDSW3_3 GPIO/LCC DCPSUS1
Idc 1.2A Rdc 0.11ohm +/-30% Near V8 2 1 22U_0805_6.3V6M W9 VCC3_3
VCC3_3 J15
+1.05VS_APLLOPI VCCTS1_5 +1.5VS
R210 +3VS
THERMAL SENSOR K14 +3VS
0_0805_5% VCC3_3 K16 C55 1 2 0.1U_0402_16V7K
1 @ 2 Near AA21 VCC3_3
C47 1 2 1U_0402_6.3V6K
L3 1 2 C22 1 2 100U_1206_6.3V6M +1.05VS_AXCK_DCB J18
2.2UH_LQM2MPN2R2NG0L_30% K19 VCCCLK SDIO/PLSS U8
VCCCLK VCCSDIO +3VS
Idc 1.2A Rdc 0.11ohm +/-30% A20 T9 C44 1 2 1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL VCCACLKPLL VCCSDIO
+1.05VS_VTT J17
C C57 R21 VCCCLK C
Near J17 2 1 1U_0402_6.3V6K T21 VCCCLK LPT LP POWER C53 @1 2 1U_0402_6.3V6K
+1.05VS_VTT +1.05VS_AXCK_DCB C56 T100 @ K18 VCCCLK SUS OSCILLATOR AB8 C25 @1 2 100U_1206_6.3V6M
Near R21 2 1 1U_0402_6.3V6K T101 @ M20 RSVD DCPSUS4
Near J18 T102 @ V21 RSVD
C48 1 2 1U_0402_6.3V6K AE20 RSVD AC20 @ T103
+3VALW _PCH VCCSUS3_3 RSVD
L4 1 2 C23 1 2 100U_1206_6.3V6M AE21 AG16 +1.05VS_VTT
2.2UH_LQM2MPN2R2NG0L_30% VCCSUS3_3 USB2 VCC1_05 AG17
Idc 1.2A Rdc 0.11ohm +/-30% VCC1_05 C45 1 2 1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL
Near A20 13 OF 19 Rev1p2
C49 1 2 1U_0402_6.3V6K HASW ELL-MCP-E-ULT_BGA1168
L5 1 2 C24 1 2 100U_1206_6.3V6M @
2.2UH_LQM2MPN2R2NG0L_30%
Idc 1.2A Rdc 0.11ohm +/-30%
+3VALW J5 @ +3VALW_PCH
B JUMP_43X39 B
1 2
1 2
A A
HASWELL_MCP_E HASWELL_MCP_E
U1N U1O U1P HASWELL_MCP_E
D H17 D
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J59
A28 VSS VSS AJ45 AP3 VSS VSS AW33 D38 VSS VSS J63
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L15
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L17
A52 VSS VSS AJ58 AP54 VSS VSS AW44 D46 VSS VSS L18
A56 VSS VSS AJ60 AP57 VSS VSS AW47 D47 VSS VSS L20
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
AF12 VSS VSS AL36 AT40 VSS VSS AY53 F26 VSS VSS U22
AF14 VSS VSS AL39 AT42 VSS VSS AY57 F30 VSS VSS U61
C AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U9 C
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62
VSS VSS VSS VSS VSS VSS_SENSE VSS_SENSE_R 11
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 Rev1p2 VSS
AH30 VSS VSS AN32 AU53 VSS VSS C18 HASW ELL-MCP-E-ULT_BGA1168
AH32 VSS VSS AN35 AU55 VSS VSS C20
VSS VSS VSS VSS @
AH34 AN36 AU57 C25
AH36 VSS VSS AN39 AU59 VSS VSS C27
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH40 VSS VSS AN42 AV16 VSS VSS C39
AH42 VSS VSS AN43 AV20 VSS VSS C57
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
AH51 VSS VSS AN48 AV33 VSS VSS D18
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
B AH57 VSS VSS AN52 AV39 VSS VSS D23 B
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31
VSS VSS VSS 15 OF 19 Rev1p2 VSS
HASW ELL-MCP-E-ULT_BGA1168
@
14 OF 19 Rev1p2
HASW ELL-MCP-E-ULT_BGA1168
@
A A
HASWELL_MCP_E HASWELL_MCP_E
U1Q U1R
U1S HASWELL_MCP_E
1
T172 @ CFG9 V61 B51 @ T81
T182 @ CFG10 V60 CFG9 RSVD_TP R224
T181 @ CFG11 U60 CFG10 L60 @ T82 1K_0402_1%
T180 @ CFG12 T63 CFG11 RESERVED RSVD_TP @
T179 @ CFG13 T62 CFG12 N60 @ T83
2
T178 @ CFG14 T61 CFG13 RSVD
T177 @ CFG15 T60 CFG14 W23 @ T84
CFG15 RSVD Y22 @ T85
T176 @ CFG16 AA62 RSVD AY15 OPI_COMP
T175 @ CFG18 U63 CFG16 PROC_OPI_RCOMP
T174 @ CFG17 AA61 CFG18 AV62 @ T86
U62 CFG17 RSVD D58
T173 @ CFG19
CFG19 RSVD
@ T87 Physical Debug Enable (DFX Privacy)
CFG_RCOMP V63 P22
CFG_RCOMP VSS N21
VSS 1: DISABLED
T90 @ A5 CFG3
RSVD P20 @ T88
RSVD 0: ENABLED; SET DFX ENABLED BIT
T91 @ E1 R20 @ T89
T92 @ D1 RSVD RSVD IN DEBUG INTERFACE MSR
T93 @ J20 RSVD
T94 @ H18 RSVD
TD_IREF B12 RSVD CFG4
TD_IREF
1
19 OF 19 Rev1p2
HASW ELL-MCP-E-ULT_BGA1168 R225
@ 1K_0402_5%
B B
2
2 1 CFG_RCOMP
R222 49.9_0402_1%
2 1 OPI_COMP
R223 49.9_0402_1%
2 1 TD_IREF Display Port Presence Strap
R226 8.2K_0402_5%
A A
+1.35V
+1.35V +1.35V +1.35V
JDIMM1
1
+V_DDR_REFA 1 2
VREF_DQ VSS1 +5VALW +5VS
0.1U_0402_16V7K
3 4 DDR_A_D9
VSS2 DQ4
C34
R54 DDR_A_D13 5 6 DDR_A_D12 1
R293 1.8K_0402_1% DDR_A_D8 7 DQ0 DQ5 8 @
2_0402_1% 9 DQ1 VSS3 10 DDR_A_DQS#1 R187 1 2 SA_ODT0
2
1 2 11 VSS4 DQS#0 12 DDR_A_DQS1 66.5_0402_1%
5 SA_DIMM_VREFDQ DM0 DQS0 2
2.2U_0402_6.3V6M
1 13 14
2
@ DDR_A_D14 15 VSS5 VSS6 16 DDR_A_D15
1 1 DQ2 DQ6 +1.35V
C105
0.1U_0402_16V7K
C106
C158 @ DDR_A_D10 17 18 DDR_A_D11 R186 R191 R188 1 2 SA_ODT1
0.022U_0402_25V7K R185 19 DQ3 DQ7 20 U45 66.5_0402_1%
100K_0402_5% 100K_0402_5%
2 1.8K_0402_1% DDR_A_D29 21 VSS7 VSS8 22 DDR_A_D25 1 5 Q18
DQ8 DQ12 NC VCC @
1
2 2 DDR_A_D28 23 24 DDR_A_D24 LBSS138LT1G_SOT-23-3
1
25 DQ9 DQ13 26 2 D R189 1 2 SB_ODT0
1 VSS9 VSS10 4 DDR_PG_CTRL A SB_ODT0 16 1
R176 DDR_A_DQS#3 27 28 4 2 66.5_0402_1%
24.9_0402_1% DDR_A_DQS3 29 DQS#1 DM1 30 DIMM_DRAMRST# 3 Y G
DQS1 RESET# DIMM_DRAMRST# 16,4 GND
@ 31 32 S
2
3
DDR_A_D30 33 VSS11 VSS12 34 DDR_A_D27 74AUP1G07GW_TSSOP5 M_A_B_DIMM_ODT R190 1 2 SB_ODT1
DQ10 DQ14 SB_ODT1 16
DDR_A_D31 35 36 DDR_A_D26 66.5_0402_1%
37 DQ11 DQ15 38
DDR_A_D44 39 VSS13 VSS14 40 DDR_A_D45
DQ16 DQ20 DDR_VTT_PG_CTRL 43
DDR_A_D41 41 42 DDR_A_D40
43 DQ17 DQ21 44
VSS15 VSS16 DDR_A_DQS#[0..7] 5
DDR_A_DQS#5 45 46
DDR_A_DQS5 47 DQS#2 DM2 48
DQS2 VSS17 DDR_A_DQS[0..7] 5
49 50 DDR_A_D42
DDR_A_D43 51 VSS18 DQ22 52 DDR_A_D46
DQ18 DQ23 DDR_A_D[0..63] 5
DDR_A_D47 53 54
55 DQ19 VSS19 56 DDR_A_D52
All VREF traces should DDR_A_D51 57 VSS20 DQ28 58 DDR_A_D53
DDR_A_MA[0..15] 5
Layout Note: have 10 mil trace width DDR_A_D50 59 DQ24 DQ29 60
Place near JDIMM1 61 DQ25 VSS21 62 DDR_A_DQS#6
+1.35V 63 VSS22 DQS#3 64 DDR_A_DQS6
65 DM3 DQS3 66
DDR_A_D49 67 VSS23 VSS24 68 DDR_A_D54
DDR_A_D48 69 DQ26 DQ30 70 DDR_A_D55
DQ27 DQ31
1U_0402_6.3V6K
C107
1U_0402_6.3V6K
C108
1U_0402_6.3V6K
C109
1U_0402_6.3V6K
C110
71 72
VSS25 VSS26
1 1 1 1
@ @
10U_0603_6.3V6M
C112
10U_0603_6.3V6M
C113
10U_0603_6.3V6M
C114
DDR_A_MA1 97 98 DDR_A_MA0
99 A1 A0 100
1 1 1 1 VDD9 VDD10
5 SA_CLK_DDR0 SA_CLK_DDR0 101 102 SA_CLK_DDR1 SA_CLK_DDR1 5
SA_CLK_DDR#0 103 CK0 CK1 104 SA_CLK_DDR#1
5 SA_CLK_DDR#0 CK0# CK1# SA_CLK_DDR#1 5
105 106
2 2 2 2 DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 5 +1.35V
5 DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# DDR_A_RAS# 5
111 BA0 RAS# 112
DDR_A_WE# 113 VDD13 VDD14 114 DDRA_CS0_DIMMA#
5 DDR_A_WE# WE# S0# DDRA_CS0_DIMMA# 5
1
5 DDR_A_CAS# DDR_A_CAS# 115 116 SA_ODT0
117 CAS# ODT0 118 R56
DDR_A_MA13 119 VDD15 VDD16 120 SA_ODT1 1.8K_0402_1%
DDRA_CS1_DIMMA# 121 A13 ODT1 122
+1.35V 5 DDRA_CS1_DIMMA# S1# NC2
123 124 R296
2
125 VDD17 VDD18 126 +VREF_CA 1 2
NCTEST VREF_CA SM_DIMM_VREFCA 5
127 128 2_0402_1% 1
1
DDR_A_D0 129 VSS27 VSS28 130 DDR_A_D5 @
DQ32 DQ36
10U_0603_6.3V6M
C115
10U_0603_6.3V6M
C116
10U_0603_6.3V6M
C117
2.2U_0402_6.3V6M
0.1U_0402_16V7K
1 DDR_A_D1 131 132 DDR_A_D4 C162
@ 133 DQ33 DQ37 134 R295 0.022U_0402_25V7K
1 1 1 VSS29 VSS30 1 1
2
C119
C120
+ C118 DDR_A_DQS#0 135 136 @ 1.8K_0402_1%
DQS#4 DM4
1
330U_2.5V_M DDR_A_DQS0 137 138
2
@ 139 DQS4 VSS31 140 DDR_A_D3
2 2 2 2 DDR_A_D2 141 VSS32 DQ38 142 DDR_A_D7 2 2 @ R294
SF000002Z00 DDR_A_D6 143 DQ34 DQ39 144 24.9_0402_1%
330U 2.5V H4.2 145 DQ35 VSS33 146 DDR_A_D18
2
DDR_A_D21 147 VSS34 DQ44 148 DDR_A_D19
17mohm OSCON DDR_A_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#2
3 153 VSS36 DQS#5 154 DDR_A_DQS2 3
155 DM5 DQS5 156
DDR_A_D17 157 VSS37 VSS38 158 DDR_A_D22
DDR_A_D16 159 DQ42 DQ46 160 DDR_A_D23
+0.675VS DQ43 DQ47 +VREF_CA 16
161 162
DDR_A_D36 163 VSS39 VSS40 164 DDR_A_D37
DDR_A_D33 165 DQ48 DQ52 166 DDR_A_D32
167 DQ49 DQ53 168
VSS41 VSS42
1U_0402_6.3V6K
C121
1U_0402_6.3V6K
C122
1U_0402_6.3V6K
C123
1U_0402_6.3V6K
C124
205 206
2
G1 G2
1 1
Channel A
0.1U_0402_16V7K
C125
C126
0_0402_5%
R211
0_0402_5%
R212
@
@ @ TYCO_2-2013022-1
CONN@
2 2
SP07000JN10
1
4 4
<Address: SA1:SA0=00>
+1.35V
+1.35V +1.35V
JDIMM2
DDR_B_DQS#[0..7] 5
1
+V_DDR_REFB 1 2
3 VREF_DQ VSS1 4 DDR_B_D12
VSS2 DQ4 DDR_B_DQS[0..7] 5
R57 DDR_B_D8 5 6 DDR_B_D9
R297 1.8K_0402_1% DDR_B_D14 7 DQ0 DQ5 8
DQ1 VSS3 DDR_B_D[0..63] 5
2_0402_1% 9 10 DDR_B_DQS#1
2
1 2 11 VSS4 DQS#0 12 DDR_B_DQS1
5 SB_DIMM_VREFDQ DM0 DQS0 DDR_B_MA[0..15] 5
2.2U_0402_6.3V6M
1 13 14
1
@ DDR_B_D10 15 VSS5 VSS6 16 DDR_B_D13
1 1 DQ2 DQ6
C127
0.1U_0402_16V7K
C128
C159 @ DDR_B_D11 17 18 DDR_B_D15
0.022U_0402_25V7K R213 19 DQ3 DQ7 20
2 1.8K_0402_1% DDR_B_D28 21 VSS7 VSS8 22 DDR_B_D25
DQ8 DQ12
1
2 2 DDR_B_D29 23 24 DDR_B_D24
2
25 DQ9 DQ13 26
1 VSS9 VSS10 1
R179 DDR_B_DQS#3 27 28
24.9_0402_1% DDR_B_DQS3 29 DQS#1 DM1 30 DIMM_DRAMRST#
DQS1 RESET# DIMM_DRAMRST# 15,4
@ 31 32
2
1U_0402_6.3V6K
C130
1U_0402_6.3V6K
C131
1U_0402_6.3V6K
C132
71 72
VSS25 VSS26
1 1 1 1
@ @
10U_0603_6.3V6M
C134
10U_0603_6.3V6M
C135
10U_0603_6.3V6M
C136
DDR_B_MA1 97 98 DDR_B_MA0
99 A1 A0 100
1 1 1 1 VDD9 VDD10
5 SB_CLK_DDR0 SB_CLK_DDR0 101 102 SB_CLK_DDR1 SB_CLK_DDR1 5
SB_CLK_DDR#0 103 CK0 CK1 104 SB_CLK_DDR#1
5 SB_CLK_DDR#0 CK0# CK1# SB_CLK_DDR#1 5
105 106
2 2 2 2 DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 5
5 DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS# DDR_B_RAS# 5
111 BA0 RAS# 112
DDR_B_WE# 113 VDD13 VDD14 114 DDRB_CS0_DIMMB#
5 DDR_B_WE# WE# S0# DDRB_CS0_DIMMB# 5
5 DDR_B_CAS# DDR_B_CAS# 115 116 SB_ODT0 SB_ODT0 15
117 CAS# ODT0 118
DDR_B_MA13 119 VDD15 VDD16 120 SB_ODT1
A13 ODT1 SB_ODT1 15
5 DDRB_CS1_DIMMB# DDRB_CS1_DIMMB# 121 122
+1.35V 123 S1# NC2 124
125 VDD17 VDD18 126 +VREF_CA
NCTEST VREF_CA +VREF_CA 15
127 128
DDR_B_D4 129 VSS27 VSS28 130 DDR_B_D5
DQ32 DQ36
10U_0603_6.3V6M
C137
10U_0603_6.3V6M
C138
10U_0603_6.3V6M
C139
2.2U_0402_6.3V6M
DDR_B_D1 131 132 DDR_B_D0
133 DQ33 DQ37 134
1 1 1 VSS29 VSS30 1 1
C141
0.1U_0402_16V7K
C142
DDR_B_DQS#0 135 136 @
DDR_B_DQS0 137 DQS#4 DM4 138
@ 139 DQS4 VSS31 140 DDR_B_D2
2 2 2 DDR_B_D3 141 VSS32 DQ38 142 DDR_B_D6 2 2
DDR_B_D7 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D16
DDR_B_D21 147 VSS34 DQ44 148 DDR_B_D17
DDR_B_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#2
3 153 VSS36 DQS#5 154 DDR_B_DQS2 3
155 DM5 DQS5 156
DDR_B_D22 157 VSS37 VSS38 158 DDR_B_D19
DDR_B_D23 159 DQ42 DQ46 160 DDR_B_D18
+0.675VS 161 DQ43 DQ47 162
DDR_B_D36 163 VSS39 VSS40 164 DDR_B_D37
DDR_B_D33 165 DQ48 DQ52 166 DDR_B_D32
167 DQ49 DQ53 168
VSS41 VSS42
1U_0402_6.3V6K
C143
1U_0402_6.3V6K
C144
1U_0402_6.3V6K
C145
1U_0402_6.3V6K
C146
205 206
2
G1 G2
1 1
Channel B
0.1U_0402_16V7K
C147
C148
0_0402_5%
R231
@
@ TYCO_2-2013022-1
CONN@
2 2
SP07000JN10
1
4 4
<Address: SA1:SA0=10>
LVTMDP
PCIE_RX5N PCIE_TX5N NC#AF35 AG36
NC#AG36
R38 P33
P37 PCIE_RX6P PCIE_TX6P P32
PCIE_RX6N PCIE_TX6N
AP34
P35 P30 TXCAP_DPA3P AR34
N36 PCIE_RX7P PCIE_TX7P P29 TXCAM_DPA3N
2 PCIE_RX7N PCIE_TX7N AW37 2
TX0P_DPA2P AU35
N38 N33 TX0M_DPA2N
M37 NC#N38 NC#N33 N32 AR37
NC#M37 NC#N32 TX1P_DPA1P AU39
TX1M_DPA1N
PCI EXPRESS INTERFACE
K35 L30
J36 NC#K35 NC#L30 L29 2160842006A0MARSXT_FCBGA962
NC#J36 NC#L29 @
J38 K33
H37 NC#J38 NC#K33 K32
NC#H37 NC#K32
H35 J33
G36 NC#H35 NC#J33 J32
NC#G36 NC#J32
G38 K30
F37 NC#G38 NC#K30 K29
NC#F37 NC#K29
3 3
F35 H33
E37 NC#F35 NC#H33 H32
NC#E37 NC#H32
CLOCK
AB35
7 CLK_PEG_VGA PCIE_REFCLKP
AA36
7 CLK_PEG_VGA# PCIE_REFCLKN
CALIBRATION
Y30 VGA_PCIE_CALRP R794 1 VGA@ 2 1.69K_0402_1% +0.95VSDGPU
PCIE_CALR_TX
2 VGA@ 1 AH16 Y29 VGA_PCIE_CALRN R796 1 VGA@ 2 1K_0402_1% +0.95VSDGPU
R795 1K_0402_5% TEST_PG PCIE_CALR_RX
3.3-V tolerant
PLTRST_VGA# AA30
8 PLTRST_VGA# PERSTB
2160842006A0MARSXT_FCBGA962
@
4 4
U51 U51
PART 9 0F 9
+MPLL_PVDD 2 1
+1.8VSDGPU
U52 VGA@ MUTI GFX VGA@
1 8 VGA_SMB_CK2 AD29 AU24
VDD SCLK T109 GENLK_CLK NC#AU24
1 VGA@ AC29 AV23 VGA@ 1 VGA@ 1 SM010030010 200ma
T110 GENLK_VSYNC NC#AV23
0.1U_0402_16V4Z
C823
1U_0402_6.3V6K
C825
10U_0603_6.3V6M
C826
GPU_THERM_D+ 2 7 VGA_SMB_DA2
2200P_0402_50V7K D+ SDATA AT25 120ohm@100mhz DCR 0.2
C827 1 2 VGA@ 3 6 THM_ALERT# AJ21 NC#AT25 AR24 AV33 XTALIN
2 D- ALERT# AK21 SWAPLOCKA DPA NC#AR24 XTALIN 2 2
GPU_THERM_D- 4 5 1 VGA@2 SWAPLOCKB AU26
THERM# GND +3VSDGPU NC#AU26
R798 4.7K_0402_5% AV25
NC#AV25 L65
ADM1032ARMZ-2REEL_MSOP8 AR8 AT27
75mA BLM18AG121SN1D_2P
AU8 NC#AR8 NC#AT27 AR26 +SPLL_PVDD 2 1
NC#AU8 NC#AR26 +1.8VSDGPU
T111
AP8 AU34 XTALOUT VGA@
+3VSDGPU AW8 DBG_CNTL0 AR30 XTALOUT
R03 modify BOM NC#AW8 NC#AR30
1 AR3 AT29 VGA@ 1 VGA@ 1 1
+3VSDGPU NC#AR3 NC#AT29
1U_0402_6.3V6K
C829
10U_0603_6.3V6M
C830
AR1
AU1 NC#AR1 AV31 +MPLL_PVDD H7
T112 DBG_DATA0 NC#AV31 MPLL_PVDD
2
AU3 AU30 H8
T113 DBG_DATA1 DPB NC#AU30 MPLL_PVDD 2 2
R800 R801 T114
AW3
4.7K_0402_5% 4.7K_0402_5% Q54B VGA@ AP6 DBG_DATA2 AR32 AW34 XO_IN 1 @ 2
T115 DBG_DATA3 NC#AR32 XO_IN
5
VGA@ VGA@ DMN66D0LDW-7_SOT363-6 T118
AW5 AT31 0_0402_5% R799
AU5 DBG_DATA4 NC#AT31 +SPLL_PVDD AM10
PLLS/XTAL
T117
1
1
VGA_SMB_CK2 4 3 EC_SMB_CK2 AR6 DBG_DATA5 AT33 SPLL_PVDD L66
EC_SMB_CK2 24,34,37,7 T119
AW6 DBG_DATA6 NC#AT33 AU32
100mA
T121 BLM18AG121SN1D_2P
AU6 DBG_DATA7 NC#AU32 +SPLL_VDDC 2 1
T120 DBG_DATA8 +0.95VSDGPU
2
Q54A VGA@ T122
AT7 AU14 +SPLL_VDDC AN9 AW35 XO_IN2 2 @ 1 VGA@
DMN66D0LDW-7_SOT363-6 AV7 DBG_DATA9 NC#AU14 AV13 SPLL_VDDC XO_IN2 0_0402_5% R802
T124 DBG_DATA10 NC#AV13
VGA_SMB_DA2 1 6 EC_SMB_DA2 AN7 VGA@ 1 VGA@ 1
EC_SMB_DA2 24,34,37,7 T123 DBG_DATA11
1U_0402_6.3V6K
C832
10U_0603_6.3V6M
C833
T125
AV9 AT15
AT9 DBG_DATA12 NC#AT15 AR14 SPLL_PVSS AN10
T127 DBG_DATA13 NC#AR14 SPLL_PVSS
AR10
T126 DBG_DATA14 DPC 2 2
AW10 AU16 SPLL_PVSS
T128 DBG_DATA15 NC#AU16
AU10 AV15
T130 DBG_DATA16 NC#AV15
T129
AP10 AK10 T137
AV11 DBG_DATA17 AT17 AF30 CLKTESTA AL10
T131 DBG_DATA18 NC#AT17 NC_XTAL_PVDD CLKTESTB T138
T133
AT11 AR16 AF31
DBG_DATA19 NC#AR16 NC_XTAL_PVSS
0.1U_0402_16V4Z 51.1_0402_1%
0.1U_0402_16V4Z 51.1_0402_1%
T132
AR12 1 1
DBG_DATA20
C892
C891
T134
AW12 AU20 @ @ Mars MLPS configuration
AU12 DBG_DATA21 NC#AU20 AT19
T136 DBG_DATA22 NC#AT19
AP12
T135 DBG_DATA23 AT21 2 2 Bits[5:1] PU(1%) PD(1%) Cap
NC#AT21 AR20
R898 0_0402_5% NC#AR20 2160842006A0MARSXT_FCBGA962
xx000 NC 4.75k
1
VGA_SMB_CK2 1 VGA@ 2VGA_SMB_CK2_R AJ23 DPD AU22 @
SMBCLK SMBus NC#AU22 xx001 8.45k 2.00k
R904
R841
VGA_SMB_DA2 1 VGA@ 2VGA_SMB_DA2_R AH23 AV21 @ @
R899 0_0402_5% SMBDATA NC#AV21
AT23
xx010 4.53k 2.00k
+3VSDGPU NC#AT23 AR22
Slave ID: 0x41 xx011 6.98k 4.99k
2
AK26 NC#AR22
AJ26 SCL I2C
2 SDA xx100 4.53k 4.99k 2
2
R409 AD39
100K_0402_5% R AD37
T154 xx101 3.24k 5.62k
GENERAL PURPOSE I/O
D22 VGA@ GPU_DPRSLPVR AH20 AVSSN
RB751V40_SC76-2
47 GPU_DPRSLPVR AH18 GPIO_0 AE36
xx110 3.40k 10.0k
GPIO_1 G T156
VGA@ AN16 AD35
xx111 4.75k NC
1
1U_0402_6.3V6K
C834
0.1U_0402_16V4Z
C835
GPU_VID_1 AM13 1 1 0_0603_5%
47 GPU_VID_1 AK14 GPIO_15_PWRCNTL_0 AC33
GPU_VID_3 +VDD1DI PS0_[1]=1 : same as GPIO_11 Since the frame buffer size is 512 MB
47 GPU_VID_3 AG30 GPIO_16 VDD1DI AC34
THM_ALERT# PS0_[2]=0 : same as GPIO_12 the aperture size is set to 256 MB.
AN14 GPIO_17_THERMAL_INT VSS1DI @ @
R806 10K_0402_5% 1 @ 2 GPIO_19_CTF AM17 GPIO_18_HPD3 (SUN NC) 2 2 PS0_[3]=0 : same as GPIO_13
GPU_VID_2 AL13 GPIO_19_CTF V13 PS0_[4]=1 : Reserved for internal use only. Must be 1
47 GPU_VID_2 AJ14 GPIO_20_PWRCNTL_1 NC#V13 U13 PS0_[5]=1 : AUD_PORT_CONN_PINSTRAP[0]
AK13 GPIO_21 NC#U13 AF33
AN13 GPIO_22_ROMCSB NC#AF33 AF32
10mil
CLKREQB NC#AF32
L68 100 - 512Kbit M25P05A (ST)
(GPIO1, 2, 7, 11, 12, 13, 18, 21 is NC at SUN) AA29 117mA 0_0603_5% 101 - 1Mbit M25P10A (ST)
NC#AA29 AG21 2 1
NC#AG21 +1.8VSDGPU 101 - 2Mbit M25P20 (ST)
AG32 AC32 MARS@
AG33 GPIO_29 NC#AC32 101 - 4Mbit M25P40 (ST)
GPIO_30 1 1@
0.1U_0402_16V4Z
C837
1U_0402_6.3V6K
C838
AC31 @ 101 - 8Mbit M25P80 (ST)
AJ19 NC_SVI2#AC31 AD30
GENERICA NC_SVI2#AD30 100 - 512Kbit Pm25LV512 (Chingis)
AK19 AD32
AJ20 GENERICB NC_SVI2#AD32 2 2 101 - 1Mbit Pm25LV010 (Chingis)
AK20 GENERICC
3 3
AJ24 GENERICD
AH26 GENERICE_HPD4
GENERICF_HPD5
PS_1[1] = 0 : PCIeR GEN3 is not supported.
VREFG:Use a voltage divider to set AH24 PS_1[2] = 0 : Reserved for internal use only
GENERICG_HPD6
VREFG = 1.80 V / 3 (or 0.60-V nominal). PS_1[3] = 0 : Reserved for internal use only
AM34 PS_0
PS_0 PS_1[4] = 1 : TX_PWRS_ENB: Full Tx output swing.
AC30 PS_1[5] = 1 : TX_DEEMPH_EN: Tx deemphasis enabled.
CEC_1
+1.8VSDGPU R810 1 MARS@ 2 499_0402_1% AK24 AD31 PS_1
HPD1 MLPS PS_1
20mil PS_2[1] = 0 : Reserved.
R811 1 MARS@ 2 249_0402_1% PS_2[2] = 0 : Reserved.
C841 1 2 0.1U_0402_16V4Z +VGA_VREF AH13 AG31 PS_2 PS_2[3] = 0 : BIOS_ROM_EN :Disable the external BIOS ROM device.
MARS@ (SUN NC) DBG_VREFG PS_2 PS_2[4] = 0 : VGA_DIS : 0=VGA controller capacity enabled.
PS_2[5] = 1 : Reserved.
Place VREFG divider and cap close to ASIC BACO
AL21 AD33 PS_3
PX_EN PS_3
2
DDC1CLK
1
AN26
2 VGA@ 1 TESTEN AD28 DDC1DATA X76@ @ @ VGA@ PS_3[4] = 1 : AUD_PORT_CONN_PINSTRAP[1]
VGA@ +3VSDGPU R817 1K_0402_5% TESTEN AM27 R812 R821 R816 R808 PS_3[5] = 1 : AUD_PORT_CONN_PINSTRAP[2]
R822 AUX1P AL27 10K_0402_5% 10K_0402_5% 10K_0402_5% 8.45K_0402_1%
1M_0402_5% RP21 AUX1N
2
XTALOUT 2 1 XTALIN 1 8 JTAG_TRSTB AM23 AM19 PS_0 ======= VRAM ID for Mars =======
2 7 JTAG_TDI AN23 JTAG_TRSTB DDC2CLK AL19 PS_1
X2 3 6 JTAG_TCK AK23 JTAG_TDI DDC2DATA PS_2
VGA@ 4 5 JTAG_TMS AL24 JTAG_TCK AN20 PS_3 001 Micron MT41K256M16HA-107G:E
Crystal AM24 JTAG_TMS AUX2P AM20
3 4 10K_0804_8P4R_5%
T18 @ JTAG_TDO AUX2N @ VGA@ @ @
OUT GND
1
@ AL30 1 1 1 1
NC#AL30
0.1U_0402_16V7K
C842
0.01U_0402_16V7K
C847
0.1U_0402_16V7K
C843
0.1U_0402_16V7K
C840
2 1 AM30 X76@
4 GND IN NC#AM30 R815 R823 R818 R809 4
VGA@ VGA@ THERMAL AL29 10K_0402_5% 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1%
C848 27MHZ_10PF_X3G027000BA1H-U C849 +3VSDGPU GPU_THERM_D+ AF29 NC#AL29 AM29 2 2 2 2 VGA@ VGA@ VGA@
2
10P_0402_50V8J 10P_0402_50V8J GPU_THERM_D- AG29 DPLUS NC#AM29
1 @ 2 DMINUS AN21
R819 10K_0402_5% NC#AN21 AM21
1 VGA@ 2 MLPS_EN# AK32 NC#AM21
R820 10K_0402_5% GPIO_28_FDO AK30
AL31 NC#AK30 AK29
+1.8VSDGPU TS_A NC#AK29
Crystals must have a max ESR of 80 ohm
L69 @ 13mA 10mil AJ30 Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 0_0603_5% +TSVDD AJ32 DDCVGACLK AJ31 2012/07/10 2013/07/10 Title
AJ33 TSVDD
TSVSS
DDCVGADATA Issued Date Deciphered Date MARS-Pro_STRAP
10U_0603_6.3V6M 2 1 @ C844
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1U_0402_6.3V6K 2 1 @ C845 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1U_0402_16V4Z 2 1 VGA@ C846 2160842006A0MARSXT_FCBGA962 Custom 0.2
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 18 of 51
A B C D E
A B C D E
U51D MAA[0..15]
MAA[0..15] 22
U51C
PART 4 0F 9 DQMA#[0..7]
PART 3 0F 9 MDB[0..63] DQMA#[0..7] 22
MDA[0..63] 23 MDB[0..63] GDDR5/DDR3 QSA[0..7]
GDDR5/DDR3 MDB0 C5 P8 MAB0
22 MDA[0..63] DQB0_0 MAB0_0/MAB_0 QSA[0..7] 22
MDA0 C37 G24 MAA0 MDB1 C3 T9 MAB1
MDA1 C35 DQA0_0 MAA0_0/MAA_0 J23 MAA1 MDB2 E3 DQB0_1 MAB0_1/MAB_1 P9 MAB2 QSA#[0..7]
DQA0_1 MAA0_1/MAA_1 DQB0_2 MAB0_2/MAB_2 QSA#[0..7] 22
(SUN 64 bin on at Channel B) MDA2 A35 H24 MAA2 MDB3 E1 N7 MAB3
MDA3 E34 DQA0_2 MAA0_2/MAA_2 J24 MAA3 MDB4 F1 DQB0_3 MAB0_3/MAB_3 N8 MAB4
MDA4 G32 DQA0_3 MAA0_3/MAA_3 H26 MAA4 MDB5 F3 DQB0_4 MAB0_4/MAB_4 N9 MAB5
DQA0_4 MAA0_4/MAA_4 DQB0_5 MAB0_5/MAB_5
MEMORY INTERFACE A
MDA5 D33 J26 MAA5 MDB6 F5 U9 MAB6
MDA6 F32 DQA0_5 MAA0_5/MAA_5 H21 MAA6 MDB7 G4 DQB0_6 MAB0_6/MAB_6 U8 MAB7 MAB[0..15]
DQA0_6 MAA0_6/MAA_6 DQB0_7 MAB0_7/MAB_7 MAB[0..15] 23
MDA7 E32 G21 MAA7 MDB8 H5 Y9 MAB8
1
MDA8 D31 DQA0_7 MAA0_7/MAA_7 H19 MAA8 MDB9 H6 DQB0_8 MAB1_0/MAB_8 W9 MAB9 DQMB#[0..7] 1
DQA0_8 MAA1_0/MAA_8 DQB0_9 MAB1_1/MAB_9 DQMB#[0..7] 23
MDA9 F30 H20 MAA9 MDB10 J4 AC8 MAB10
MDA10 C30 DQA0_9 MAA1_1/MAA_9 L13 MAA10 MDB11 K6 DQB0_10 MAB1_2/MAB_10 AC9 MAB11 QSB[0..7]
DQA0_10 MAA1_2/MAA_10 DQB0_11 MAB1_3/MAB_11 QSB[0..7] 23
MDA11 A30 G16 MAA11 MDB12 K5 AA7 MAB12
MDA12 F28 DQA0_11 MAA1_3/MAA_11 J16 MAA12 MDB13 L4 DQB0_12 MAB1_4/MAB_12 AA8 B_BA2 QSB#[0..7]
MEMORY INTERFACE B
DQA0_12 MAA1_4/MAA_12 DQB0_13 MAB1_5/BA2 B_BA2 23 QSB#[0..7] 23
MDA13 C28 H16 A_BA2 MDB14 M6 Y8 B_BA0
+1.5VSDGPU DQA0_13 MAA1_5/MAA_BA2 A_BA2 22 DQB0_14 MAB1_6/BA0 B_BA0 23
MDA14 A28 J17 A_BA0 MDB15 M1 AA9 B_BA1
DQA0_14 MAA1_6/MAA_BA0 A_BA0 22 DQB0_15 MAB1_7/BA1 B_BA1 23
MDA15 E28 H17 A_BA1 MDB16 M3
DQA0_15 MAA1_7/MAA_BA1 A_BA1 22 DQB0_16
MDA16 D27 MDB17 M5 H3 DQMB#0
MDA17 F26 DQA0_16 A32 DQMA#0 MDB18 N4 DQB0_17 W CKB0_0/DQMB_0 H1 DQMB#1
DQA0_17 W CKA0_0/DQMA_0 DQB0_18 W CKB0B_0/DQMB_1
1
MVREFDA MDA23 E24 DQA0_22 W CKA1B_0/DQMA_5 E10 DQMA#6 MDB24 U4 DQB0_23 W CKB1_1/DQMB_6 AK5 DQMB#7
MDA24 C22 DQA0_23 W CKA1_1/DQMA_6 D9 DQMA#7 MDB25 V6 DQB0_24 W CKB1B_1/DQMB_7
DQA0_24 W CKA1B_1/DQMA_7 DQB0_25
1
1
1U_0402_6.3V6K
C850
MDA30 D19 DQA0_29 EDCA0_3/QSA_3 E16 QSA4 MDB31 Y5 DQB0_30 EDCB1_0/QSB_4 AH1 QSB5
2
MDA31 E18 DQA0_30 EDCA1_0/QSA_4 E12 QSA5 MDB32 AA4 DQB0_31 EDCB1_1/QSB_5 AJ9 QSB6 MVREFDB
MDA32 C18 DQA0_31 EDCA1_1/QSA_5 J10 QSA6 MDB33 AB6 DQB1_0 EDCB1_2/QSB_6 AM5 QSB7
DQA1_0 EDCA1_2/QSA_6 DQB1_1 EDCB1_3/QSB_7
1
MDA33 A18 D7 QSA7 MDB34 AB1
DQA1_1 EDCA1_3/QSA_7 DQB1_2
1
1U_0402_6.3V6K
C851
R900 MDA35 D17 A34 QSA#0 MDB36 AD6 K1 QSB#1 R827 VGA@
0_0402_5% MDA36 A16 DQA1_3 DDBIA0_0/QSA_0B E30 QSA#1 MDB37 AD1 DQB1_4 DDBIB0_1/QSB_1B P1 QSB#2 100_0402_1%
@ MDA37 F16 DQA1_4 DDBIA0_1/QSA_1B E26 QSA#2 MDB38 AD3 DQB1_5 DDBIB0_2/QSB_2B W4 QSB#3
2 2
2
MDA38 D15 DQA1_5 DDBIA0_2/QSA_2B C20 QSA#3 MDB39 AD5 DQB1_6 DDBIB0_3/QSB_3B AC4 QSB#4 2
2
1
40.2_0402_1% 15mil MDA42 F12 F8 QSA#7 MDB43 AG4
MARS@ MDA43 A12 DQA1_10 DDBIA1_3/QSA_7B MDB44 AH5 DQB1_11 T7 ODTB0 R901
ODTB0 23
2
MVREFSA MDA44 D11 DQA1_11 J21 ODTA0 MDB45 AH6 DQB1_12 ADBIB0/ODTB0 W7 ODTB1 0_0402_5%
DQA1_12 ADBIA0/ODTA0 ODTA0 22 DQB1_13 ADBIB1/ODTB1 ODTB1 23 +1.5VSDGPU
MDA45 F10 G19 ODTA1 MDB46 AJ4 @
DQA1_13 ADBIA1/ODTA1 ODTA1 22 DQB1_14
1
2
DQA1_14 DQB1_15 CLKB0
1U_0402_6.3V6K
C852
1
100_0402_1% MDA49 H13 MDB50 AG8 AD8 CLKB1
2 DQA1_17 DQB1_18 CLKB1 CLKB1 23
MARS@ MDA50 J13 J14 CLKA1 MDB51 AG7 AD7 CLKB1# R829
CLKA1 22 CLKB1# 23
2
MDA51 H11 DQA1_18 CLKA1 H14 CLKA1# MDB52 AK9 DQB1_19 CLKB1B VGA@
DQA1_19 CLKA1B CLKA1# 22 DQB1_20
MDA52 G10 MDB53 AL7 T10 RASB0# 40.2_0402_1% 15mil
DQA1_20 DQB1_21 RASB0B RASB0# 23
MDA53 G8 K23 RASA0# MDB54 AM8 Y10 RASB1#
RASA0# 22 RASB1# 23
2
MDA54 K9 DQA1_21 RASA0B K19 RASA1# MDB55 AM7 DQB1_22 RASB1B MVREFSB
DQA1_22 RASA1B RASA1# 22 DQB1_23
MDA55 K10 MDB56 AK1 W 10 CASB0#
DQA1_23 DQB1_24 CASB0B CASB0# 23
1
MDA56 G9 K20 CASA0# MDB57 AL4 AA10 CASB1# 1 VGA@
DQA1_24 CASA0B CASA0# 22 DQB1_25 CASB1B CASB1# 23
1U_0402_6.3V6K
C853
MDA57 A8 K17 CASA1# MDB58 AM6 R831
DQA1_25 CASA1B CASA1# 22 DQB1_26
MDA58 C8 MDB59 AM1 P10 CSB0# VGA@
DQA1_26 DQB1_27 CSB0B_0 CSB0# 23
MDA59 E8 K24 CSA0# MDB60 AN4 L10 100_0402_1%
DQA1_27 CSA0B_0 CSA0# 22 DQB1_28 CSB0B_1 2
MDA60 A6 K27 MDB61 AP3
2
MDA61 C6 DQA1_28 CSA0B_1 MDB62 AP1 DQB1_29 AD10 CSB1#
DQA1_29 DQB1_30 CSB1B_0 CSB1# 23
MDA62 E6 M13 CSA1# MDB63 AP5 AC10
DQA1_30 CSA1B_0 CSA1# 22 DQB1_31 CSB1B_1
MDA63 A5 K16
DQA1_31 CSA1B_1 U10 CKEB0
CKEB0 CKEB0 23
MVREFDA L18 K21 CKEA0 MVREFDB Y12 AA11 CKEB1
MVREFDA CKEA0 CKEA0 22 MVREFDB CKEB1 CKEB1 23
MVREFSA L20 J20 CKEA1 MVREFSB AA12
3 MVREFSA CKEA1 CKEA1 22 MVREFSB 3
N10 WEB0#
W EB0B WEB0# 23
L27 K26 WEA0# AB11 WEB1#
NC#L27 W EA0B WEA0# 22 W EB1B WEB1# 23
N12 L15 WEA1#
NC#N12 W EA1B WEA1# 22
AG12
NC#AG12 T8 MAB13
H23 MAA13 MAB0_8/MAB_13 W8 MAB14
R835 1 VGA@ 2 MEM_CALRP0 M27 MAA0_8/MAA_13 J19 MAA14 MAB1_8/MAB_14 U12 MAB15
120_0402_1% MEM_CALRP0 MAA1_8/MAA_14 M21 MAA15 MAB0_9/MAB_15 V12
M12 MAA0_9/MAA_15 M20 MAB1_9/RSVD
AH12 NC#M12 MAA1_9/RSVD AH11 1 2 1 2
NC#AH12 DRAM_RST VRAM_RST# 22,23
VGA@ VGA@
R838 R839
2
10_0402_5% 1 VGA@ 51.1_0402_1%
2160842006A0MARSXT_FCBGA962 VGA@ C854
@ R840 120P_0402_50V8
2160842006A0MARSXT_FCBGA962 4.99K_0402_1%
@ 2
1
Place all these components very close
to GPU (Within 25mm) and
keep all component close to
each Other (within5mm) except Rser2
U51E
PART 5 0F 9
1.5A AC7
MEM I/O
AA31
+1.5VSDGPU
VGA@ @ VGA@ @ VGA@ AD11 VDDR1 NC#AA31 AA32
20mil
VDDR1 NC#AA32 +1.8VSDGPU
0.01U_0402_16V7K
C856
0.01U_0402_16V7K
C857
0.01U_0402_16V7K
C858
0.01U_0402_16V7K
C859
0.01U_0402_16V7K
C860
1 1 1 1 1 AF7 AA33 VGA@ @ @
AG10 VDDR1 NC#AA33 AA34
VDDR1 NC#AA34 1 1 1
1U_0402_6.3V6K
C861
1U_0402_6.3V6K
C862
10U_0603_6.3V6M
C863
AJ7 W30 NC For Mars
AK8 VDDR1 NC#W30 Y31
2 2 2 2 2 AL9 VDDR1 NC#Y31 V28
G11 VDDR1 NC_BIF_VDDC W29 2 2 2
G14 VDDR1 NC_BIF_VDDC AB37
100mA
PCIE
G17 VDDR1 PCIE_PVDD
G20 VDDR1 G30
1 1
VGA@ @ VGA@ @ VGA@ G23 VDDR1 PCIE_VDDC G31
VDDR1 PCIE_VDDC +0.95VSDGPU
0.1U_0402_16V4Z
C864
0.1U_0402_16V4Z
C865
0.1U_0402_16V4Z
C866
0.1U_0402_16V4Z
C867
0.1U_0402_16V4Z
C868
1 1 1 1 1 G26 H29 VGA@ @ @ @ VGA@ VGA@
G29 VDDR1 PCIE_VDDC H30
VDDR1 PCIE_VDDC 2.5A 100mil 1 1 1 1 1 1
1U_0402_6.3V6K
C869
1U_0402_6.3V6K
C872
1U_0402_6.3V6K
C873
1U_0402_6.3V6K
C874
1U_0402_6.3V6K
C875
10U_0603_6.3V6M
C876
H10 J29
J7 VDDR1 PCIE_VDDC J30
2 2 2 2 2 J9 VDDR1 PCIE_VDDC L28
K11 VDDR1 PCIE_VDDC M28 2 2 2 2 2 2
K13 VDDR1 PCIE_VDDC N28
K8 VDDR1 PCIE_VDDC R28
L12 VDDR1 PCIE_VDDC T28
VGA@ VGA@ VGA@ @ @ VGA@ VGA@ VGA@ L16 VDDR1 PCIE_VDDC U28
VDDR1 PCIE_VDDC
2.2U_0402_6.3V6M
C880
2.2U_0402_6.3V6M
C881
2.2U_0402_6.3V6M
C882
2.2U_0402_6.3V6M
C883
2.2U_0402_6.3V6M
C884
1 1 1 1 1 1 1 1 L21
VDDR1
10U_0603_6.3V6M
C877
10U_0603_6.3V6M
C878
10U_0603_6.3V6M
C879
L23
L26 VDDR1 N27
L7 VDDR1 BACO BIF_VDDC T27
1.4A 60mil
2 2 2 2 2 2 2 2 VDDR1 BIF_VDDC +0.95VSDGPU
M11 VGA@ @ VGA@
N11 VDDR1
VDDR1 1 1 1
1U_0402_6.3V6K
C890
1U_0402_6.3V6K
C889
10U_0603_6.3V6M
C888
P7 AA15 +VGA_CORE
R11 VDDR1 CORE VDDC AA17
U11 VDDR1 VDDC AA20
U7 VDDR1 VDDC AA22
30A (TBD) 2 2 2
Y11 VDDR1 VDDC AA24
Y7 VDDR1 VDDC AA27
VDDR1 VDDC AB16
VDDC AB18
VDDC AB21
VDDC AB23
+VDDC_CT VDDC AB26
20mil 13mA LEVEL VDDC
Must always be connected to PCIE_VDDC.
TRANSLATION AB28 0.95 V for "Mars" and
1 2 +VDDC_CT AF26 VDDC AC17
+1.8VSDGPU VDD_CT VDDC "Heathrow"/"Chelsea" on both BACO and
L70 VGA@ VGA@ AF27 AC20
VDD_CT VDDC non-BACO designs.
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V4Z
BLM18AG121SN1D_2P 1 1 1 AG26 AC22
@ AG27 VDD_CT VDDC AC24
VGA@ VDD_CT VDDC
C885
C886
C887
AC27
2 VDDC AD18 2
2 2 2 10mil 25mA VDDC AD21
I/O
+VDDR3 AF23 VDDC AD23
AF24 VDDR3 VDDC AD26
AG23 VDDR3 VDDC AF17
2 1 AG24 VDDR3 VDDC AF20
+3VSDGPU VDDR3 VDDC
L71 @ VGA@ VGA@ AF22
VDDC
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
BLM18AG121SN1D_2P 1 1 1 300mA DVP AG16
VDDC
C896
C897
C898
VGA@ AD12 AG18
AF11 VDDR4 VDDC
AF12 VDDR4 AH22
2 2 2 AF13 VDDR4 VDDC AH27
VDDR4 VDDC AH28
VDDC M26
AF15 VDDC N24
AG11 VDDR4 VDDC R18
20mil AG13 VDDR4 VDDC R21
2 1 +VDDR4 AG15 VDDR4 VDDC R23
+1.8VSDGPU VDDR4 VDDC
L72 MARS@ MARS@ R26
VDDC
0.1U_0402_16V4Z
1U_0402_6.3V6K
C908
C899
@ T20
MARS@ VDDC T22
VDDC T24
2 2 2 VDDC U16
VDDC U18
VDDC U21
VDDC U23
VDDC U26
VDDC V17
VDDC V20
VDDC V22
VDDC V24
VDDC V27
VDDC Y16
VDDC Y18
3 3
VDDC Y21
VDDC Y23
VDDC Y26
VDDC Y28
VDDC
AA13
VDDCI AB13
360mil
VDDCI +VGA_CORE
AC12
VDDCI AC15
VDDCI AD13
3.5A (DDR3)
VDDCI
0.1U_0402_16V4Z
C917
0.1U_0402_16V4Z
C918
0.1U_0402_16V4Z
C919
AD16 1 1 1
VDDCI M15 @ @ @
VDDCI M16
VDDCI M18
VOLTAGE VDDCI M23 2 2 2
ISOLATED
N13
VCC_GPU_SENSE AF28 VDDCI N15
47 VCC_GPU_SENSE FB_VDDC VDDCI N17
VDDCI N20
AG28 VDDCI N22
T139 FB_VDDCI VDDCI R12
VDDCI R13
VSS_GPU_SENSE AH29 VDDCI R16
47 VSS_GPU_SENSE FB_GND VDDCI T12
VDDCI T15
VDDCI V15
VDDCI
1
Y13
@ VDDCI
R842
0_0402_5% 2160842006A0MARSXT_FCBGA962
@
2
4 4
U51F
PART 6 0F 9
AB39 A3
E39 PCIE_VSS GND A37
F34 PCIE_VSS GND AA16
F39 PCIE_VSS GND AA18
G33 PCIE_VSS GND AA2
G34 PCIE_VSS GND AA21
H31 PCIE_VSS GND AA23
H34 PCIE_VSS GND AA26
H39 PCIE_VSS GND AA28
J31 PCIE_VSS GND AA6
1 J34 PCIE_VSS GND AB12 1
K31 PCIE_VSS GND AB15
K34 PCIE_VSS GND AB17
K39 PCIE_VSS GND AB20
L31 PCIE_VSS GND AB22
L34 PCIE_VSS GND AB24
M34 PCIE_VSS GND AB27
M39 PCIE_VSS GND AC11
N31 PCIE_VSS GND AC13
N34 PCIE_VSS GND AC16
P31 PCIE_VSS GND AC18
P34 PCIE_VSS GND AC2
P39 PCIE_VSS GND AC21
R34 PCIE_VSS GND AC23
T31 PCIE_VSS GND AC26
T34 PCIE_VSS GND AC28
T39 PCIE_VSS GND AC6 U51H
U31 PCIE_VSS GND AD15
U34 PCIE_VSS GND AD17 PART 8 0F 9
V34 PCIE_VSS GND AD20
V39 PCIE_VSS GND AD22 DP_VDDR DP_VDDC
W31 PCIE_VSS GND AD24 AP31
20mil
W34 PCIE_VSS GND AD27 DP_VDDC AP32
PCIE_VSS GND DP_VDDC +0.95VSDGPU
Y34 AD9 AN33
Y39 PCIE_VSS GND AE2 DP_VDDC AP33
PCIE_VSS GND AE6 AN24 DP_VDDC AL33
280mA
GND NC#AN24 DP_VDDC 1 VGA@ 1 VGA@ 1 VGA@
0.1U_0402_16V4Z
C927
1U_0402_6.3V6K
C928
10U_0603_6.3V6M
C929
AF10 AP24 AM33
GND AF16 AP25 NC#AP24 DP_VDDC AK33
GND AF18 AP26 NC#AP25 DP_VDDC AK34
GND AF21 AU28 NC#AP26 DP_VDDC AN31 2 2 2
GND GND NC#AU28 DP_VDDC
AG17 AV29
F15 GND AG2 NC#AV29
2 F17 GND GND AG20 2
F19 GND GND AP20 AP13
F21 GND AG6 AP21 NC#AP20 NC#AP13 AT13
F23 GND GND AG9 AP22 NC#AP21 NC#AT13 AP14
F25 GND GND AH21 AP23 NC#AP22 NC#AP14 AP15
F27 GND GND AJ10 AU18 NC#AP23 NC#AP15
F29 GND GND AJ11 AV19 NC#AU18
F31 GND GND AJ2 NC#AV19 DP GND
F33 GND GND AJ28 AN27
F7 GND GND AJ6 AH34 DP_VSSR AP27
F9 GND GND AK11 AJ34 DP_VDDR DP_VSSR AP28
G2 GND GND AK31 AF34 DP_VDDR DP_VSSR AW24
G6 GND GND AK7 AG34 DP_VDDR DP_VSSR AW26
H9 GND GND AL11 AM37 DP_VDDR DP_VSSR AN29
J2 GND GND AL14
237mA AL38 DP_VDDR DP_VSSR AP29
J27 GND GND AL17 AM32 DP_VDDR DP_VSSR AP30
GND GND +1.8VSDGPU DP_VDDR DP_VSSR
J6 AL2 @ VGA@ VGA@ AW30
GND GND DP_VSSR
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V4Z
J8 AL20 1 1 1 AW32
GND GND DP_VSSR
C936
C937
C938
K14 AN17
K7 GND AL23 DP_VSSR AP16
L11 GND GND AL26 DP_VSSR AP17
L17 GND GND AL32 2 2 2 DP_VSSR AW14
L2 GND GND AL6 DP_VSSR AW16
L22 GND GND AL8 DP_VSSR AN19
L24 GND GND AM11 DP_VSSR AP18
L6 GND GND AM31 DP_VSSR AP19
M17 GND GND AM9 DP_VSSR AW20
M22 GND GND AN11 CALIBRATION DP_VSSR AW22
M24 GND GND AN2 DP_VSSR AN34
N16 GND GND AN30 DP_VSSR AP39
N18 GND GND AN6 AW28 DP_VSSR AR39
N2 GND GND AN8 NC#AW28 DP_VSSR AU37
3 N21 GND GND AP11 DP_VSSR AF39 3
N23 GND GND AP7 DP_VSSR AH39
N26 GND GND AP9 AW18 DP_VSSR AK39
N6 GND GND AR5 NC#AW18 DP_VSSR AL34
R15 GND GND B11 R845 DP_VSSR AV27
R17 GND GND B13 150_0402_1% DP_VSSR AR28
R2 GND GND B15 2 MARS@ 1 AM39 DP_VSSR AV17
R20 GND GND B17 DP_CALR DP_VSSR AR18
R22 GND GND B19 DP_VSSR AN38
R24 GND GND B21 DP_VSSR AM35
R27 GND GND B23 DP_VSSR AN32
R6 GND GND B25 DP_VSSR
T11 GND GND B27
T13 GND GND B29
T16 GND GND B31
T18 GND GND B33
T21 GND GND B7
T23 GND GND B9 2160842006A0MARSXT_FCBGA962
T26 GND GND C1 @
U15 GND GND C39
U17 GND GND E35
U2 GND GND E5
U20 GND GND F11
U22 GND GND F13
U24 GND GND
U27 GND
U6 GND
V11 GND AG22
V16 GND NC#AG22
V18 GND
V21 GND
V23 GND
4 V26 GND 4
W2 GND
W6 GND
Y15 GND
Y17 GND
Y20 GND
Y22 GND A39
Y24 GND VSS_MECH AW1
Y27 GND VSS_MECH AW39 Security Classification Compal Secret Data Compal Electronics, Inc.
GND VSS_MECH
2012/07/10 2013/07/10 Title
Issued Date Deciphered Date MARS-Pro_PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2160842006A0MARSXT_FCBGA962 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
@ Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 21 of 51
A B C D E
A B C D E
1
J1 B1 J1 B1 J1 B1 J1 B1
R846 L1 NC/ODT1 VSSQ B9 R847 L1 NC/ODT1 VSSQ B9 R848 L1 NC/ODT1 VSSQ B9 R849 L1 NC/ODT1 VSSQ B9
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
128@ L9 NC/CE1 VSSQ D8 128@ L9 NC/CE1 VSSQ D8 128@ L9 NC/CE1 VSSQ D8 128@ L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96
X76@ X76@ X76@ X76@
+1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU
1
1
R850 R851 R854 R855
4.99K_0402_1% 128@ 4.99K_0402_1% 128@ 4.99K_0402_1% 128@ 4.99K_0402_1%
128@
3 3
2
VREFCA_A1 VREFDA_Q1 VREFCA_A3 VREFDA_Q3
1
1
1 1 1 1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R858 C939 R859 R862 C943 R863 C944
4.99K_0402_1% 4.99K_0402_1% C940 4.99K_0402_1% 4.99K_0402_1% 128@
128@ 128@ 128@ 128@ 128@ 128@ 128@
2 2 2 2
2
2
+1.5VSDGPU +1.5VSDGPU +1.5VSDGPU
+1.5VSDGPU
128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 128@ 128@ 128@ 128@ 128@
1U_0402_6.3V6K
C947
1U_0402_6.3V6K
C948
1U_0402_6.3V6K
C949
1U_0402_6.3V6K
C950
1U_0402_6.3V6K
C951
1U_0402_6.3V6K
C952
1U_0402_6.3V6K
C953
1U_0402_6.3V6K
C954
1U_0402_6.3V6K
C955
1U_0402_6.3V6K
C956
1U_0402_6.3V6K
C957
1U_0402_6.3V6K
C958
1U_0402_6.3V6K
C959
1U_0402_6.3V6K
C960
1U_0402_6.3V6K
C961
128@ 1 1 1 1 1
1U_0402_6.3V6K
C962
1U_0402_6.3V6K
C963
1U_0402_6.3V6K
C964
1U_0402_6.3V6K
C965
1U_0402_6.3V6K
C966
1 2
19 CLKA0
R866 40.2_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
128@ 2 2 2 2 2
1 2
19 CLKA0#
R867 40.2_0402_1%
+1.5VSDGPU
1
+1.5VSDGPU
C395
0.01U_0402_16V7K 128@ 128@ 128@ 128@
2 128@ 128@ 128@ 128@
128@ 1 10U_0603_6.3V6M 1 1 1
C972
10U_0603_6.3V6M
C973
10U_0603_6.3V6M
C974
10U_0603_6.3V6M
C975
4
1 1 1 1 4
128@
10U_0603_6.3V6M
C968
10U_0603_6.3V6M
C969
10U_0603_6.3V6M
C970
10U_0603_6.3V6M
C971
1 2
19 CLKA1 2 2 2 2
R868 40.2_0402_1%
2 2 2 2
128@
1 2
19 CLKA1#
R869 40.2_0402_1%
1 Security Classification Compal Secret Data Compal Electronics, Inc.
C406 Issued Date 2012/07/10 2013/07/10 Title
Deciphered Date
2
0.01U_0402_16V7K
128@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3 / Channel A
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 22 of 51
A B C D E
A B C D E
1
J1 B1 J1 B1 J1 B1 J1 B1
R870 L1 NC/ODT1 VSSQ B9 R871 L1 NC/ODT1 VSSQ B9 R872 L1 NC/ODT1 VSSQ B9 R873 L1 NC/ODT1 VSSQ B9
VGA@ J9 NC/CS1 VSSQ D1 VGA@ J9 NC/CS1 VSSQ D1 VGA@ J9 NC/CS1 VSSQ D1 VGA@ J9 NC/CS1 VSSQ D1
243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96
X76@ X76@ X76@ X76@
+1.5VSDGPU +1.5VSDGPU
+1.5VSDGPU +1.5VSDGPU
1
1
R874 R875
4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ R878 R879
3 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ 3
2
2
VREFCB_A1 VREFDB_Q1
VREFCB_A3 VREFDB_Q3
1
1 1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@ R886 C981 R887 C982
VGA@ VGA@ 4.99K_0402_1% VGA@ 4.99K_0402_1% VGA@
2 2 VGA@ VGA@
2
2 2
2
R890 40.2_0402_1%
1 2 +1.5VSDGPU +1.5VSDGPU
19 CLKB0
VGA@ +1.5VSDGPU +1.5VSDGPU
R891 40.2_0402_1% VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
1 2 1 1 1 1 1 1 1 1 1 1 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
19 CLKB0#
1U_0402_6.3V6K
C987
1U_0402_6.3V6K
C988
1U_0402_6.3V6K
C989
1U_0402_6.3V6K
C990
1U_0402_6.3V6K
C985
1U_0402_6.3V6K
C991
1U_0402_6.3V6K
C992
1U_0402_6.3V6K
C993
1U_0402_6.3V6K
C994
1U_0402_6.3V6K
C995
VGA@ 1 1 1 1 1 1 1 1 1 1
1U_0402_6.3V6K
C996
1U_0402_6.3V6K
C997
1U_0402_6.3V6K
C998
1U_0402_6.3V6K
C999
1U_0402_6.3V6K
C1000
1U_0402_6.3V6K
C1001
1U_0402_6.3V6K
C1002
1U_0402_6.3V6K
C1003
1U_0402_6.3V6K
C1004
1U_0402_6.3V6K
C1005
1
C409 2 2 2 2 2 2 2 2 2 2
+1.5VSDGPU 2 2 2 2 2 2 2 2 2 2
0.01U_0402_16V7K
2 +1.5VSDGPU
VGA@
R892
40.2_0402_1%
1 2 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
19 CLKB1
10U_0603_6.3V6M
C1009
10U_0603_6.3V6M
C1006
10U_0603_6.3V6M
C1007
10U_0603_6.3V6M
C1008
VGA@ 1 1 1 1
R893 VGA@ VGA@ VGA@ VGA@
10U_0603_6.3V6M
C1010
10U_0603_6.3V6M
C1011
10U_0603_6.3V6M
C1012
10U_0603_6.3V6M
C1013
40.2_0402_1%
1 2 2 2 2 2
4 19 CLKB1# 2 2 2 2 4
VGA@
1
C410
0.01U_0402_16V7K
2
VGA@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3 / Channel B
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 23 of 51
A B C D E
5 4 3 2 1
+3VS_TL
+3VS +3VS_TL U50 TL@
TL@ 19 TXOUT_CLK+ TXOUT_CLK+ 25
L63 2 1 DP_V33 TXEC+
30mil 30mil 40mil 3 DP_V33 TXEC-
20 TXOUT_CLK- TXOUT_CLK- 25
2 1 FBMA-L11-201209-221LMA30T_0805
R928 TL@ 0_0603_5% 60mil TL@ 60mil13 SWR_VDD TXE2+
21 TXOUT2+ TXOUT2+ 25
+1.2V_TL
Power
L73 2 1 SWR_VDD 18 22 TXOUT2-
LVDS
D PVCC TXE2- TXOUT2- 25 D
FBMA-L11-201209-221LMA30T_0805
L6 1
TL@L6
TL@ 2 +1.2V_TL_OUT 60mil12 23 TXOUT1+ TXOUT1+ 25
4.7UH_PG031B-4R7MS_1.1A_20% 11 SWR_LX TXE1+ 24 TXOUT1-
SWR_VCCK TXE1- TXOUT1- 25
+1.2V_TL 27
7 VCCK 25 TXOUT0+
DP_V12 TXE0+ TXOUT0+ 25
60mil 26 TXOUT0- TXOUT0- 25
TXE0-
Close to Pin3
DP_V33
2
RTD2132S
25 EDP_AUXP_C AUX_P
10U_0603_6.3V6M
C1016 TL@
0.1U_0402_16V4Z
C1015 TL@
0.1U_0402_16V4Z
C983
DP-IN
1 14 R932 1 TL@ 2 0_0402_5%
GPIO
25 EDP_AUXN_C AUX_N GPIO(PWM OUT) TL_INVT_PWM 25
1 1 1 15 R948 1 TL@ 2 0_0402_5%
GPIO(Panel_VCC) TL_ENVDD 25
5 16 R934 1 TL@ 2 0_0402_5%
25 EDP_TXP0_C 6 LANE0P GPIO(PWM IN) 17 PCH_INV_PWM 25,8
25 EDP_TXN0_C LANE0N GPIO(BL_EN) TL_BKOFF# 25
TL@
2 2 2
CSCL 9 LVDS 29 I2CC_SCL
CIICSCL1 MIICSCL1 I2CC_SCL 25
CSDA 10 28 I2CC_SDA
CIICSDA1 EDID MIICDA1 I2CC_SDA 25
Other
1 2 TL_HPD 32 ROM 31 MODE_CFG1
25 EDP_HPD HPD MIICSCL0 30 MODE_CFG0
R936 8 MIICSDA0
C DP_REXT C
1K_0402_5% 4 33
DP_GND GND
2
Close to L64 Close to Pin13 Close to P18 TL@
TL@
SWR_VDD R938 RTD2132R-CG_QFN32_5X5
12K_0402_1% Part Number = SA000069200 TL@ +3VS_TL
10U_0603_6.3V6M
C984
0.1U_0402_16V4Z
C1020 TL@
22U_0805_6.3V6M
C986
0.1U_0402_16V4Z
C1019 TL@
0.1U_0402_16V4Z
C1018 TL@
RP41
1
I2CC_SCL 1 8
1 1 1 1 1 use 2132S symbol I2CC_SDA 2 7
CSCL 3 6
TL@
TL@
CSDA 4 5
2 2 2 2 2
4.7K_8P4R_5%
2
0.1U_0402_16V4Z
C1022 TL@
0.1U_0402_16V4Z
C1017 TL@
0.1U_0402_16V4Z
C1021 TL@
1 @
R943 R944
B 1 1 1 B
4.7K_0402_5% 4.7K_0402_5%
TL@
TL@
2
1
1
2 2 2 TL@
2
MODE_CFG0 Q53A
MODE_CFG1
CSDA 1 6
EC_SMB_DA2 18,34,37,7
2
@
R945 R946 DMN66D0LDW-7_SOT363-6 TL@
5
4.7K_0402_5% 4.7K_0402_5% Q53B
TL@
CSCL 4 3
EC_SMB_CK2 18,34,37,7
1
DMN66D0LDW-7_SOT363-6
MODE_CFG0(PIN30)
0 1
0 X EP MODE
MODE_CFG1(PIN31)
A 1 ROM ONLY MODE* EEPROM MODE A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Translator - RTD2132R
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9532P Schematic
Date: Monday, December 03, 2012 Sheet 24 of 51
5 4 3 2 1
A B C D E
1000P_0402_50V7K
C364
1 @ 1 1 XEMC@
3 C367 2 2 C365 SM010014520 3000ma
EN 4.7U_0603_6.3V6K 68P_0402_50V8J
G5243T11U_SOT23-5
220ohm@100mhz
2 2 2 DCR 0.04
1 2
8 PCH_ENVDD
R947 0_0402_5%
24 TL_ENVDD
+3VS
XEMC@
5
INVTPWM C549 1 2 220P_0402_50V7K
BKOFF# 2 XEMC@
P
+3VS +3VS 34 BKOFF# B
U20 @ 4 DISPOFF# C528 1 2 220P_0402_50V7K
M74VHC1GT125DF2G_SC70-5
24 TL_BKOFF#
TL_BKOFF# 1
A
Y
LCD/ LED PANEL Conn.
G
1 @ 2 1 5 U22 TL@
100K_0402_5% OE Vcc
1
2 2
R362 NC7SZ08P5X_NL_SC70-5
3
R401
2 1K_0402_5%
IN A @
@
1 EDP@ 2 1 R959 2
2
DISPOFF# 9 8
I2CC_SCL 10 9
24 I2CC_SCL 11 10
I2CC_SDA
24 I2CC_SDA 12 11
TXOUT0- 13 12
eDP 24
24
TXOUT0-
TXOUT0+
TXOUT0+ 14
15
13
14
TXOUT1- 16 15
24 TXOUT1- 16
C372 1 2 0.1U_0402_16V7K EDP_TXN0_C
EDP_TXN0_C 24 TXOUT1+ 17
4 EDP_TXN0 24 TXOUT1+ 17
C371 1 2 0.1U_0402_16V7K EDP_TXP0_C EDP_TXP0_C 24 18
4 EDP_TXP0 19 18
3 TXOUT2- 3
24 TXOUT2- 19
C374 1 2 0.1U_0402_16V7K EDP_TXN1_C TXOUT2+ 20
4 EDP_TXN1 24 TXOUT2+ 20
C373 1 2 0.1U_0402_16V7K EDP_TXP1_C 21
4 EDP_TXP1 22 21
TXOUT_CLK-
24 TXOUT_CLK- 22
TXOUT_CLK+ 23
24 TXOUT_CLK+ 24 23
EDP_TXN0_C 25 24
EDP_TXP0_C 26 25
+3VS 27 26
EDP_TXN1_C 28 27
C369 1 2 0.1U_0402_16V7K EDP_AUXN_C R613 2 @ 1 100K_0402_1% EDP_TXP1_C 29 28
4 EDP_AUXN 29
4 EDP_AUXP C370 1 2 0.1U_0402_16V7K EDP_AUXP_C R614 2 @ 1 100K_0402_1% 30
EDP_AUXN_C 31 30
EDP_AUXP_C 32 31
33 32
EDP_HPD 34 33
EDP_AUXN_C 24 34
EDP_AUXP_C 24 35
+3VSFor Camera 36 35
+3VS 37 36
USB20_P7 38 37
+5VS 10 USB20_P7 39 38
USB20_N7
10 USB20_N7 39
1
40
R383 40
10K_0402_5% Q13 ACES_50203-04001-001
2
G
@ L2N7002LT1G_SOT23-3 SP010014B00
@ CONN@
2
1 @ 2
R406
0_0402_5% R364 Security Classification Compal Secret Data Compal Electronics, Inc.
100K_0402_5% 2012/07/10 2013/07/10 Title
Issued Date Deciphered Date
eDP Connector
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 25 of 51
A B C D E
A B C D E
HDMI_GND
W=40mils 4 CPU_DP2_N2 C383 2 1 0.1U_0402_16V7K HDMI_TX0- 4 5 XEMC@ 4 3
3 C384 2 1 0.1U_0402_16V7K HDMI_TX0+ 3 6 4 3
OUT 4 CPU_DP2_P2
1 4 CPU_DP2_N3 C385 2 1 0.1U_0402_16V7K HDMI_CLK- 2 7 HDMI_CLK+ R369 1 2 0_0402_5%
XEMC@ HDMI_R_CK+
1 4 CPU_DP2_P3 C386 2 1 0.1U_0402_16V7K HDMI_CLK+ 1 8
IN C378
1 1
2 0.1U_0402_16V4Z RP18 HDMI_TX0- R370 1 2 0_0402_5%
XEMC@ HDMI_R_D0-
GND 2 EMC@ 680_8P4R_5%
3
1 2
AP2330W-7_SC59-3 L14 1 2
WCM-2012-900T_0805
+3VS 5 XEMC@ 4 3
Q14B 4 3
DMN66D0LDW-7_SOT363-6 HDMI_TX0+ R371 1 2 0_0402_5%
XEMC@ HDMI_R_D0+
4
HDMI_TX1- R372 1 2 0_0402_5%
XEMC@ HDMI_R_D1-
+3VS
1 2
+3VS L15 1 2
1
WCM-2012-900T_0805
R376 XEMC@ 4 3
1M_0402_5% Q14A 4 3
2
<BOM Structure> DMN66D0LDW-7_SOT363-6 HDMI_TX1+ R373 1 2 0_0402_5%
XEMC@ HDMI_R_D1+
2
8 CPU_HDMI_HPD 1 6 HDMI_HPD
HDMI_TX2- R374 1 2 0_0402_5%
XEMC@ HDMI_R_D2-
1
1
1 2
R121 C387 L16 1 2
2 100K_0402_5% 220P_0402_50V7K WCM-2012-900T_0805 2
2 EMC@ XEMC@ 4 3
2
4 3
HDMI_TX2+ R375 1 2 0_0402_5%
XEMC@ HDMI_R_D2+
RP15
2.2K_0804_8P4R_5%
1 8 HDMI_SCLK
3
+HDMI_5V_OUT 2 7 HDMI_SDATA HDMI connector 3
3 6 DDI2_CTRL_CK JHDMI1
+3VS 4 5 DDI2_CTRL_DATA 32 HDMI_HPD HDMI_HPD 19
18 HP_DET
+HDMI_5V_OUT +5V
17
HDMI_SDATA 16 DDC/CEC_GND
HDMI_SCLK 15 SDA
+3VS 14 SCL
13 Reserved
CEC
2
HDMI_R_CK- 12
Q15A 11 CK-
CK_shield
2
DMN66D0LDW-7_SOT363-6 HDMI_R_CK+ 10
HDMI_R_D0- 9 CK+
1 6 HDMI_SCLK 8 D0-
8 DDI2_CTRL_CK D0_shield
HDMI_R_D0+ 7
4 3 HDMI_SDATA D2 HDMI_R_D1- 6 D0+
8 DDI2_CTRL_DATA D1-
Q15B XEMC@ 5
DMN66D0LDW-7_SOT363-6 HDMI_R_D1+ 4 D1_shield 20
YSLC05CH_SOT23-3
1
HDMI_R_D2- 3 D1+ GND 21
5
2 D2- GND 22
+3VS D2_shield GND
Place closed to JHDMI1 HDMI_R_D2+ 1 23
D2+ GND
Reserved for ESD
ACON_HMR2U-AK120C
ZZZ CONN@
4 DC232002700 4
L30 1 @ 2 0_0603_5% 1 2
+3VS_6511 L48 BLM18AG121SN1D_2P
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
SM010030010 200ma 120ohm@100mhz DCR 0.2
1U_0402_6.3V6K
1 1 1 1 1
C473 @
@
C476
C472
C579
10U_0603_6.3V6M
0.1U_0402_16V4Z
C75
2 2 2 2 2
1 1
@
C455
C457
2 2
D D
+1.8VS_6511 +1.8VS_RXVCC
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
ISPSDA_R
+5VS
1 1
1
1
+3VS +HDMI_5V_OUT
@
22_0402_5%
C519
C498
R407 @ @
2
R408
22_0402_5%
2.2K_0402_5%
1
1
R240
2
2
8 CPU_DP_HPD 3 1 DP_HPD 4.7K_0402_5% R234 R230 R123
1 @ 2 4.7K_0402_5%
S
R127
1 @ 2
Q24 R418 R241
2
2
L2N7002LT1G_SOT23-3 100K_0402_5% 4.7K_0402_5%
@ +3VS
55
56
16
46
54
17
15
49
52
U42 CRT_DATA_1 1 6
CRT_DATA 28
2
1.52mA C477
DDCSCL
DDCSDA
OVDD
OVDD
OVDD
IVDD
IVDD
IVDD
IVDD
DP_HPD 44 51 1 2 0.1U_0402_16V4Z
Q27A
5
HPD MCUVDDH
4.2mA 100.5mA C496 1 2 0.1U_0402_16V4Z DMN66D0LDW-7_SOT363-6
C68 2 1 0.1U_0402_16V7K CPU_DP1_C_P0 30 50 1 2 1 2 CRT_CLK_1 4 3 CRT_CLK 28
4 CPU_DP1_P0 RX0P MCUVDD
C69 2 1 0.1U_0402_16V7K CPU_DP1_C_N0 31 R133
4 CPU_DP1_N0 RX0N 4.7K_0402_5% C614
C70 2 1 0.1U_0402_16V7K CPU_DP1_C_P1 33 53 MCURSTN 0.1U_0402_16V4Z Q27B
4 CPU_DP1_P1 RX1P MCURSTN DMN66D0LDW-7_SOT363-6
C71 2 1 0.1U_0402_16V7K CPU_DP1_C_N1 34
4 CPU_DP1_N1 RX1N
32 @ T97 1 2 R413 22_0402_5% R80
URDBG ISPSCL 28 +3VS
+3VS R50 2 @ 1 1M_0402_5% 1 2 R412 22_0402_5% 0_0603_5%
ISPSDA 28 +3VS_6511
R421 2 @ 1 100K_0402_5% C72 19 ISPSCL_R 1 @ 2 R411 22_0402_5% 1 2
0.1U_0402_16V7K ISPSCL 20 ISPSDA_R 1 @ 2 R410 22_0402_5%
C R400 1 @ 2 0_0402_5% 2 1 DDI1_AUX_C_DP 24 ISPSDA C
8 DDI1_AUX_DP RXAUXP
D
R415 1 @ 2 0_0402_5% 2 1 DDI1_AUX_C_DN 23 27 R397 2 1 22_0402_5% CRT_CLK_1 3 1
8 DDI1_AUX_DN RXAUXN VGADDCCLK CRT_CLK_1 28
C73 25 R398 2 1 22_0402_5% CRT_DATA_1 CRT_DATA_1 28
0.1U_0402_16V7K VGADDCSDA Q25
R420 2 @ 1 100K_0402_5% DDI1_AUX_DP_R 22 1 DMG2301U-7_SOT23-3
G
+3VS VSYNC 28
2
R51 2 @ 1 1M_0402_5% DDI1_AUX_DN_R 21 DCAUXP VSYNC 2 R396
DCAUXN HSYNC HSYNC 28 @
1K_0402_5%
6511_PWR_EN# 2@ 1
45 1
OSCOUT
+1.8VS_RXVCC 35 56.95mA 65.5mA 8 +1.8VS_DAC C411
29 AVCC VDDC 11 0.1U_0402_16V7K
AVCC VDDC 14 2
IT6511FN VDDC @
1
18
VGADETECT VGADETECT 28
3 R196 1 2 100_0402_1%
39 6.158mA RSET
+1.8VS_RXVCC ASPVCC
2
0.293mA 5 +1.8VS_DAC
VDDA
75_0402_1%
75_0402_1%
75_0402_1%
+3VS R134 1 @ 2 10K_0402_5% 42
B INT# 4 1 2 C500 B
COMP
R197
R199
R201
R193 1 2 10K_0402_5% 48 0.1U_0402_16V4Z
R194 1 2 10K_0402_5% 47 PCSDA
Note: need external PU to 2K ~ 10K PCSCL 41 XTALIN_6511
XTALIN 40 XTALOUT_6511 +3VS
6511_PWR_EN 43 XTALOUT
SYSRSTN
GND
2
@
R584
IT6511FN_QFN56_7X7 R419 100K_0402_5%
57
1M_0402_5%
XTALOUT_6511 XTALIN_6511
1
6511_PWR_EN#
38 6511_PWR_EN#
X4
27MHZ_10PF_X3G027000BA1H-U
Crystal
1
3 4 D
OUT GND 6511_PWR_EN 2
45 6511_PWR_EN
2 1 G
GND IN Q52
18P_0402_50V8J
1 S
3
L2N7002LT1G_SOT23-3
18P_0402_50V8J
1
@
C65
2 C74
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ITE IT6511FN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 27 of 51
5 4 3 2 1
A B C D E
W=40mils
1 1
+HDMI_5V_OUT
CRB1.0 use 47ohm@100Mhz Bead
L42 EMC@
27
27
ISPSDA
ISPSCL CRT Connector
BLM18BA470SN1D_2P
1 2 CRT_R_2 JCRT1
27 CRT_R
L45 EMC@ 6
BLM18BA470SN1D_2P 11
1 2 CRT_G_2 1
27 CRT_G
L46 EMC@ 7
BLM18BA470SN1D_2P 12
1 2 CRT_B_2 2
27 CRT_B
8
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
13
1 1 1 1 1 1 3
9
C648
C615
C611
C647
C618
C616
14
4
2 2 2 2 2 2 10 16
G
15 G 17
5
C-H_13-12201560CP
CONN@
DC060006E00
2 R175 2
+HDMI_5V_OUT 1 XEMC@ 2 0_0603_5% CRT_HSYNC_2
VGADETECT 27
U24 @
CRT_DATA 27
1 5 0.1U_0402_16V4Z 2 1 C447 R180
R439 OE Vcc 1 XEMC@ 2 0_0603_5% CRT_VSYNC_2
0_0402_5% 1 1
2 @ 1 CRT_HSYNC 2 @ @
27 HSYNC IN A C448 C449 CRT_CLK 27
10P_0402_50V8J 10P_0402_50V8J
3 4 CRT_HSYNC_1 2 2
GND OUT Y
M74VHC1GT125DF2G_SC70-5
R239 +HDMI_5V_OUT
0_0402_5% U23
2 @ 1 1 5
OE Vcc
2 @ 1 CRT_VSYNC 2
27 VSYNC IN A
R441
0_0402_5%
3 4 CRT_VSYNC_1
GND OUT Y
M74VHC1GT125DF2G_SC70-5
3 3
+HDMI_5V_OUT
@ C451 +3VS
1 2 0.1U_0402_16V4Z
1 2 C452
@ 0.1U_0402_16V4Z
1
2
7
U10
VCC_VIDEO
VCC_SYNC
VCC_DDC
3 CRT_R_2
HSYNC 13 VIDEO_1 4 CRT_G_2
VSYNC 15 SYNC_IN1 VIDEO_2 5 CRT_B_2
SYNC_IN2 VIDEO_3
CRT_CLK_1 10 14 CRT_HSYNC_1
27 CRT_CLK_1 DDC_IN1 SYNC_OUT1
27 CRT_DATA_1 CRT_DATA_1 11 16 CRT_VSYNC_1
DDC_IN2 SYNC_OUT2
9 CRT_CLK
1 2 8 DDC_OUT1 12 CRT_DATA
4 BYP DDC_OUT2 4
C454
0.1U_0402_16V4Z DDC_CLK/DAT reserved PU Resistor
GND
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 28 of 51
A B C D E
5 4 3 2 1
+1.2V_LAN
+VDDO_CR
U48 R759
37 +3VALW +3V_LAN
4.7U_0603_6.3V6K
+LAN_BIASVDDH 0_0805_5%
20 BIASVDDH +3V_LAN
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 L74
VDDO_CR
1U_0402_6.3V6K
C820
C771
C772
C773
C774
@ @ 1 @ 2 1 2
+1.2V_LAN 35 17
60mil
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+LAN_XTALVDDH
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 VDDC XTALVDDH 1 1 1
C777
C803
C779
C780
61 BLM31PG601SN1_2P @
2 2 2 2 VDDC
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
48 3 1
D
+LAN_AVDDH 1 1
2 2 AVDDH 2 2 2
C784
42 @
+3V_LAN AVDDH
C783
7 Q6
G
2
56 VDDO DMG2301U-7_SOT23-3 2 2
D 62 VDDO D
VDDO 49 LAN_MIDI3-
TRD3_N 50 LAN_MIDI3+ LAN_MIDI3- 30
TRD3_P LAN_MIDI3+ 30 LAN_PWR_EN# 34
47 LAN_MIDI2-
TRD2_N 46 LAN_MIDI2- 30
LAN_MIDI2+
TRD2_P LAN_MIDI2+ 30
+LAN_AVDDL 39 43 LAN_MIDI1- 20mil
45 AVDDL TRD1_N 44 LAN_MIDI1+ LAN_MIDI1- 30
L56
51 AVDDL TRD1_P LAN_MIDI1+ 30 1 2
+LAN_XTALVDDH 1 +3V_LAN
AVDDL 41 LAN_MIDI0- C785 BLM18AG601SN1D_2P
+LAN_GPHYPLLVDDL 36 TRD0_N 40 LAN_MIDI0+ LAN_MIDI0- 30
0.1U_0402_16V4Z
GPHY_PLLVDDL TRD0_P LAN_MIDI0+ 30
R02 modify for ESD +LAN_PCIEPLLVDD 32
20mil 2 L57
PCIE_PLLVDDL +LAN_BIASVDDH 1 2
1
29 C787 BLM18AG601SN1D_2P
C786 1 2 0.1U_0402_16V4Z PLT_RST_BUF# PCIE_PLLVDDL 65 0.1U_0402_16V4Z
EMC@ SO_LINKLED# LAN_LINK# 30
66 2
SCLK_SPD1000LED# 20mil
L58
2 +LAN_AVDDH 1 2
SPD100LED#_SERIALDO BLM18AG601SN1D_2P
1 1
C789 C790
0.1U_0402_16V7K 1 2 C788 PCIE_PRX_C_DTX_P3 28 67 R760 2 @ 1 0_0402_5% @
10 PCIE_PRX_DTX_P3 PCIE_TXD_P TRAFFICLED#_SERIALDI LAN_ACTIVITY# 30
0.1U_0402_16V7K 1 2 C791 PCIE_PRX_C_DTX_N3 27 0.1U_0402_16V4Z 0.1U_0402_16V4Z
10 PCIE_PRX_DTX_N3 PCIE_TXD_N 2 2
33
10 PCIE_PTX_C_DRX_P3 34 PCIE_RXD_P 8 +VDDO_CR_R R761 1 @ 2 0_0603_5% +VDDO_CR
+VDDO_CR
10 PCIE_PTX_C_DRX_N3 PCIE_RXD_N GPIO1_LR_OUT
5 5IN1_LED_R# R762 2 @ 1 0_0402_5%
R763 1 @ 2 0_0402_5% GPIO_0 5IN1_LED# 35
34 EC_PME#
0_0402_5%
PLACE NEXT P14
20mil
L61
+LAN_GPHYPLLVDDL 1 2
+3V_LAN +1.2V_LAN
BLM18AG601SN1D_2P
1 1
C801 C802
2
1K_0402_5%
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2
R783
LAN_XTALI
LAN_XTALO_R
1
20mil
1
1K_0402_5%
1 1
2
R784
C804 C805
1 3 LAN_XTALO SPROM_CLK SPROM_DOUT
1 3 (EECLK) (EEDATA) 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
A GND GND 2 2 A
1 1
1
On chip 1 0
C799 2 4 C800
15P_0402_50V8J 15P_0402_50V8J
2 2 AT24C02 1 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Broadcom BCM57786X
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 29 of 51
5 4 3 2 1
5 4 3 2 1
+3V_LAN
T1
1
1 24 R786 R787
D
29
29
LAN_MIDI3+
LAN_MIDI3-
LAN_MIDI3+
LAN_MIDI3-
2
3
TCT1
TD1+
MCT1
MX1+
23
22
RJ45_MIDI3+
RJ45_MIDI3-
LAN Connector 1K_0402_5% 1K_0402_5%
D
TD1- MX1-
2
4 21
LAN_MIDI2- 5 TCT2 MCT2 20 RJ45_MIDI2- C806 1 2 220P_0402_50V7K
29 LAN_MIDI2- TD2+ MX2+
29 LAN_MIDI2+ LAN_MIDI2+ 6 19 RJ45_MIDI2+ XEMC@
TD2- MX2- C807 1 2 220P_0402_50V7K
7 18 JRJ45 XEMC@
LAN_MIDI1+ 8 TCT3 MCT3 17 RJ45_MIDI1+ RJ45_MIDI0+ 1
29 LAN_MIDI1+ TD3+ MX3+ PR1+
29 LAN_MIDI1- LAN_MIDI1- 9 16 RJ45_MIDI1- 9 LAN_ACTIVITY#
TD3- MX3- RJ45_MIDI0- 2 LED_YELLOW_A1 LAN_ACTIVITY# 29
10 15 PR1- 10 C808 1 2 68P_0402_50V8J
LAN_MIDI0- 11 TCT4 MCT4 14 RJ45_MIDI0- RJ45_MIDI1+ 3 LED_YELLOW_A2 XEMC@
29 LAN_MIDI0- TD4+ MX4+ PR2+
29 LAN_MIDI0+ LAN_MIDI0+ 12 13 RJ45_MIDI0+
TD4- MX4- RJ45_MIDI2+ 4
PR3+ 11 LAN_LINK#
RJ45_MIDI2- 5 LED_GREEN_B1 LAN_LINK# 29
75_0402_1%
75_0402_1%
PR3-
1
GST5009-E 12 C809 1 2 68P_0402_50V8J
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SP050006B10 RJ45_MIDI1- 6 LED_GREEN_B2 XEMC@
PR2-
R788
R789
1 1 1 1
7 13
C810
C811
C812
C813
RJ45_MIDI3+
PR4+ GND 14
75_0402_1%
75_0402_1%
2
2
GND
1
RJ45_MIDI3- 8 40mil
2 2 2 2 PR4-
R790
R791
SANTA_130451-F
CARD READER_2in1 SP07000TF00 CONN@
DC234005300
2
RJ45_GND
C
Place close to TCT pin C
B88069X9231T203_4P5X3P2-2
1
XEMC@
J15
1
40mil JUMP_43X118
D39 EMC@
L30ESDL5V0C3-2
@
2
Card Reader Connector
JP2
2
+XDPW R_SDPW R_MSPW R
1
JREAD1
CR_CMD_XD_CLE 3
B 29 CR_CMD_XD_CLE CMD B
4
5 VSS
R897 2 EMC@ 1 CR_CLK 6 VDD
29 CR_CLK_XD_RY_BY# CLK +XDPW R_SDPW R_MSPW R
0_0402_5% 7
VSS
CR_DATA0 8 +3VALW
29 CR_DATA0
CR_DATA1 9 DAT0 L75
40mil
29 CR_DATA1 DAT1
D
CR_DATA2 1 3 1 1 2
29 CR_DATA2 DAT2
1U_0402_6.3V6K
C821
CR_DATA3 2 BLM31PG601SN1_2P
29 CR_DATA3 CD/DAT3
1
1 1 1 1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
C817
C818
C819
R793 Q9 @ @
G
2
CR_W P#_XD_W P# 10 10K_0402_5% DMG2301U-7_SOT23-3
29 CR_W P#_XD_W P# WP SW
CR_XD_W E#_SD_DETECT 11
29,32 CR_XD_W E#_SD_DETECT CD SW 2 2 2 2
12
2
13 GND SW
GND SW Q23
L2N7002LT1G_SOT23-3 D
1
1
T-SOL_156-1000302601_NR 2 @
29 CR_PW R_EN
C822
CONN@ G
0.1U_0402_16V4Z
SP07000TF00 S
3
2
C26
R26
CR_CLK 1 XEMC@ 2 1 2
XEMC@
22_0402_5%
6.8P_0402_50V8C
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 30 of 51
5 4 3 2 1
A B C D E
4 21 22 PLT_RST_BUF#
IN 21 22 PLT_RST_BUF# 29,8
1 10 PCIE_PRX_DTX_N4 23 24
@ 3 25 23 24 26
EN 10 PCIE_PRX_DTX_P4 25 26
27 28
G5243T11U_SOT23-5 29 27 28 30 MINI1_SMBCLK R432 1 @ 2 0_0402_5%
2 29 30 PCH_SMBCLK 7
@ 31 32 MINI1_SMBDATA R434 1 @ 2 0_0402_5% PCH_SMBDATA 7
10 PCIE_PTX_C_DRX_N4 31 32
33 34
10 PCIE_PTX_C_DRX_P4 33 34
35 36
34 W LAN_ON 35 36 USB20_N4 10
37 38
37 38 USB20_P4 10
39 40
41 39 40 42 R443 1 2 100K_0402_5%
+3VS_W LAN 41 42 +3VS_W LAN
43 44 MINI1_LED# 34
2 R435 45 43 44 46 2
0_0402_5% 47 45 46 48
1 @ 2 E51TXD_P80DATA_R 49 47 48 50
34 E51TXD_P80DATA 49 50
1 @ 2 E51RXD_P80CLK_R 51 52
34 E51RXD_P80CLK 51 52
1
R436 53 54
0_0402_5% GNDGND
R437 R438 BELLW _80053-1021
100K_0402_5% 1K_0402_5% CONN@
@ DC040009P00
2
D
1
2 Q20
34 BT_ON#
G L2N7002LT1G_SOT23-3
S @
3
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI CARD (WLAN)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 31 of 51
A B C D E
A B C D E
1
SATA ODD Conn.
C392 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2 GND JODD1
6 SATA_PTX_DRX_P0 A+
6 SATA_PTX_DRX_N0 C393 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3
4 A- 1
C391 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5 GND C401 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 2 GND
6 SATA_PRX_DTX_N0 B- 6 SATA_PTX_DRX_P1 A+
1 C394 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 6 6 SATA_PTX_DRX_N1 C402 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 3 1
6 SATA_PRX_DTX_P0 7 B+ 4 A-
GND C403 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N1 5 GND
6 SATA_PRX_DTX_N1 B-
C405 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 6
6 SATA_PRX_DTX_P1 B+
R308 8 7
+3VS V33 GND
0_0402_5% 9
1 @ 2 +3VS_HDD 10 V33 +5VS R593
11 V33 0_0805_5% 8
R307 1 @ 2 0_0402_5% 12 GND 1 2
80mils +5VS_ODD 9 DP
8,9 DEVSLP0 GND +5V
10U_0603_6.3V6M
C404
0.1U_0402_16V4Z
C407
13 1 10
GND +5V
1
+5VS R49 1 2 0_0805_5% +5VS_HDD 14 ODD_MD 11
15 V5 12 MD 14
16 V5 T185 @ 13 GND GND 15
2
17 V5 2 GND GND
18 GND
19 Reserved 23 SANTA_201902-1_13P-T
+3VS +5VS 20 GND GND 24 CONN@
21 V12 GND 25
100mils 22 V12 GND 26 LTCX004HZ00
V12 GND
10U_0603_6.3V6M
C420
0.1U_0402_16V4Z
C397
1 1 CCM_C127043HR022M27FZR_22P-T
1
0.1U_0402_16V4Z
C390
@
CONN@
DC231211190
2
2 2
2 2
Debug Board
JDB1
1 2
1 2 PCH_SPI_CLK_1_R 7
3 4
7 PCH_SPI_CS0#_1_R 3 4 PCH_SPI_MOSI_1_R 7
7 PCH_SPI_MISO_1_R 5 6 +BIOS_SPI
7 5 6 8
7 SPI_HOLD1#_R
34 EC_SPICLK
9
11
7
9
8
10
10
12
EC_SPICS#/FSEL#_R 34
Kill SW
3 34 EC_SO_SPI_SI_R1 11 12 EC_SI_SPI_SO_R1 34 3
+EC_SPI 13 14
13 14 EC_RST# 34,35
15 16
17 15 16 18
19 17 18 20 SPI_W P1#_R 34,6,7
29,30 CR_XD_W E#_SD_DETECT 19 20
21 22
21 22 ON/OFFBTN# 33,35
23 24 R569
25 23 24 26 1K_0402_1% JP5
27 25 26 28 1 940@ 2 1 3
29 27 28 30 2 1 G1 4
29 30 REC_MODE_L 34 +3VALW 2 G2
31 32 EC UART_RXD 34
33 31 32 34 ACES_87212-02G0
34 EC UART_TXD 33 34 +3VALW _EC
35 36 CONN@
37 35 36 38
39 37 38 40
26 HDMI_HPD 39 40 SPI_W P1#_R 34,6,7
41 42
43 41 42 44
43 44 LID_SW # 33,34
45 46
8 XDP_DBRESET# 45 46 KSI2 34,35
47 48
34,35 KSI0 47 48 KSO3 34,35
49 50
34,35 KSO2 49 50 KSO4 34,35
51 52
G1 G2
E&T_1001K-F50C-05R
CONN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD/Debug Board
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 32 of 51
A B C D E
A B C D E
D15 U25
L24 XEMC@ C483 W=60mils
10 PCH_USB3_TX0_P 2 1 PCH_USB3_TX0_P_C 2 1 U3TXDP0 U3RXDN0 1 1 10 9 U3RXDN0 0.01U_0402_16V7K 1 8
C484 0.1U_0402_16V7K 1 2 2 GND OUT 7 R454
2 2 IN OUT
U3RXDP0 9 8 U3RXDP0 @ 3 6 0_0402_5%
2 1 PCH_USB3_TX0_N_C 3 4 U3TXDN0 4 IN OUT 5 1 @ 2
10 PCH_USB3_TX0_N 34 USB_CHARGE_2A# EN/ENB OCB USB_OC0# 10,9
C482 0.1U_0402_16V7K U3TXDN0 4 4 7 7 U3TXDN0
OCE2012120YZF_4P SY6288D10CAC_MSOP8
EMC@ U3TXDP0 5 5 6 6 U3TXDP0
3 3
L25
1 PCH_USB3_RX0_P 2 1 U3RXDP0 8 1
10 PCH_USB3_RX0_P
L05ESDL5V0NA-4 SLP2510P8
PCH_USB3_RX0_N 3 4 U3RXDN0
10 PCH_USB3_RX0_N +USB3_VCCA
OCE2012120YZF_4P
EMC@ W=100mils SF000002Y00
R458 1 EMC@ 2 0_0402_5% EMC@
R461 1 EMC@ 2 0_0402_5% 1 1 220U 6.3V OSCON
L26 C487
ESR 17mohm@100Khz
0.1U_0402_16V4Z
USB20_P0 3 4 U2DP0_L C486 +
10 USB20_P0 3 4
220U_6.3V_M 2
10 USB20_N0
USB20_N0 2
2 1
1 U2DN0_L 2
USB3.0 Conn.
W CM2012F2SF-670T04_0805
XEMC@ JUSB1
1
U2DN0_L 2 VBUS
U2DP0_L 3 D-
4 D+
U3RXDN0 5 GND
U3RXDP0 6 StdA-SSRX- 10
7 StdA-SSRX+ GND 11
U3TXDN0 8 GND-DRAIN GND 12
U3TXDP0 9 StdA-SSTX- GND 13
StdA-SSTX+ GND
OCTEK_USB-09EAAB
CONN@
2 2
DC233008O20
3 3
USB/B
(USB Port 1, Port2)
+5VALW
PWR/B 1
JUSB2
JPW R1 2 1
1 3 2
1 +3VALW 3
2 +3VLP 4
2 3 LID_SW# USB_EN# 5 4
3 LID_SW# 32,34 34 USB_EN# 5
4 PWR_LED# PWR_LED# 35 6
4 5 ON/OFFBTN# USB20_N1 7 6
5 ON/OFFBTN# 32,35 10 USB20_N1 7
6 USB20_P1 8
6 10 USB20_P1 8
9
7 USB20_N2 10 9
GND 10 USB20_N2 10
8 USB20_P2 11
GND 10 USB20_P2 11
12
ACES_88514-00601-071 13 12
CONN@ 14 13
14
SP010014M00
ACES_88514-01201-071
CONN@
SP01001BF00
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 Conn/USB_B/PWR_B
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 33 of 51
A B C D E
A B C D E
C501 +3VALW R24 +3VALW_EC L31 SM010030010 200ma 120ohm@100mhz DCR 0.2 +3VALW_EC
22P_0402_50V8J 0_0805_5% BLM18AG121SN1D_2P
2 1 2 XEMC@ 1 CLK_PCI_LPC 1 @ 2 1 2 +EC_VCCA +3VS LID_SW# R476 1 2 100K_0402_5%
+EC_VCCA
XEMC@ R477 33_0402_5% XEMC@ XEMC@ 1
+3VLP
1 1 1 1 2 2
2
0.1U_0402_16V4Z
C502
0.1U_0402_16V4Z
C503
0.1U_0402_16V4Z
C504
0.1U_0402_16V4Z
C505
1000P_0402_50V7K
C506
1000P_0402_50V7K
C507
@ @ +EC_VCC C508
1 2 0.1U_0402_16V4Z
2
ECAGND
6 1 R485 1 9012@ 2 4.7K_0402_5%
+3VALW_EC 2 2 2 2 1 1 7,9 SMB_ALERT# SMB_ALERT#_R 35 +5VS
R480 2 1 47K_0402_5% EC_RST#_R R236 R483 1 9012@ 2 4.7K_0402_5%
0_0805_5% Q50A
C509 2 1 0.1U_0402_16V4Z DMN66D0LDW-7_SOT363-6
ECAGND 40
111
125
TP_CLK R478 1 940@ 2 4.7K_0402_5%
22
33
96
67
U28 +3VS
9
TP_DATA R479 1 940@ 2 4.7K_0402_5%
1 2
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
32,35 EC_RST# EC_MUTE# 1 2 10K_0402_5%
R591 DEG@ 0_0402_5% R481 @
1 1
3
LPC_AD0 10 LPC & MISC 64
35,7 LPC_AD0 LPC_AD0 GPIO39 65 ADP_I
+3VALW_EC CLK_PCI_LPC 12 ADP_I/GPIO3A 66 AD_BID0 ADP_I 40,41
RP12 AD Input
7 CLK_PCI_LPC 13 CLK_PCI_EC GPIO3B 75 DMN66D0LDW-7_SOT363-6
PLT_RST# H_PROCHOT#_EC 5
1 8 35,8 PLT_RST# 37 PCIRST#/GPIO05 GPIO42 76 Q50B
EC_SMB_DA1 EC_RST#_R EC_PME#
2 7 EC_SMB_CK1 EC_SCI# 20 EC_RST# IMON/GPIO43 EC_PME# 29
6,9 EC_SCI#
4
3 6 EC_SMB_CK2 WLAN_ON 38 EC_SCII#/GPIO0E
4 5 EC_SMB_DA2 31 WLAN_ON GPIO1D 68
Latest design guide suggest change to
+3VS DAC_BRIG/GPIO3C 70 EN_DFAN1 74LVC1G06.
EN_DFAN1/GPIO3D 71 EN_DFAN1 37
2.2K_0804_8P4R_5% DA Output
KSI0 55 IREF/GPIO3E 72
+3VS KSI1 56 KSI0/GPIO30 CHGVADJ/GPIO3F
KSI2 57 KSI1/GPIO31
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
R488 1 @ 2 10K_0402_5% EC_SMI# KSI4 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 LAN_PWR_EN# EC_MUTE# 36
1 2 10K_0402_5% 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 LAN_PWR_EN# 29
R492 @ EC_SCI# KSI5 WLAN_PME#
61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 WLAN_PME# 31
KSI6 PS2 Interface EC_ENTERING_RW
1 2 0.01U_0402_16V7K PLT_RST# KSI7 62 KSI6/GPIO36 EAPD/GPIO4D 87 TP_CLK EC_ENTERING_RW 35
C511
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK 35
XEMC@ KSO0 39 88 TP_DATA
40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA 35
KSO1
KSO2 41 KSO1/GPIO21 1 2 0_0402_5%
ESD request KSO2/GPIO22
R509 @ ACIN 39,41,8
KSI[0..7] KSO3 42 97 VGATE_3V
32,35 KSI[0..7] KSO4 43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 USB_CHARGE_2A# VGATE_3V 8
2 2
KSO[0..17] KSO4/GPIO24 W OL_EN/GPXIOA01 USB_CHARGE_2A# 33
KSO5 44 99 HDA_SDO EC_ACIN C512 2 1 100P_0402_50V8J
X1 @
32,35 KSO[0..17]
KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109 VCIN0_PH_R
HDA_SDO 6
32.768KHZ_12.5PF_FC-135 KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00
KSO7/GPIO27 SPI Device Interface
EC_XCLK1 2 1 EC_XCLK0 KSO8 47
KSO9 48 KSO8/GPIO28 119 EC_SI_SPI_SO 1 R158 2 940@ 49.9_0402_1% EC_SI_SPI_SO_R
KSO10 49 KSO9/GPIO29 SPIDI/GPIO5B 120 EC_SO_SPI_SI 1 R159 2 940@ 49.9_0402_1% EC_SO_SPI_SI_R
1 1
KSO11 50 KSO10/GPIO2A SPIDO/GPIO5C 126 EC_SPICLK_R 1 R160 2 940@ 49.9_0402_1% EC_SPICLK
KB930&9012 Co-Layout Item
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 EC_SPICLK 32
C513 C514 KSO12 51 128 EC_SPICS#/FSEL# 1 R146 2 49.9_0402_1% EC_SPICS#/FSEL#_R
@ 15P_0402_50V8J 15P_0402_50V8J @ KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A 940@ +EC_VCC 1 @ 2
2 2 KSO13/GPIO2D +3VALW
KSO14 53 R691 2 1 100K_0402_5% R494 0_0402_5%
KSO15 54 KSO14/GPIO2E 73 ENBKL R495 1 @ 2 0_0402_5%
KSO15/GPIO2F ENBKL/GPIO40 ENBKL 8 +3VLP
KSO16 81 74 930_PECI
KSO17 82 KSO16/GPIO48 PECI_KB930/GPIO41 89 FSTCHG
KSO17/GPIO49 FSTCHG/GPIO50 FSTCHG 41 Pin 111 is a power source for HW operation of KB9012.
90 BATT_BLUE_LED#
BATT_CHG_LED#/GPIO52 91 EC_WLAN_LED# BATT_BLUE_LED# 35 So, power plan will be different between KB930 and KB9012.
CAPS_LED#/GPIO53 EC_WLAN_LED# 35
EC_SMB_CK1 77 GPIO 92 PWR_LED 930_PECI R496 1 940@ 2 43_0402_1%
40,41 EC_SMB_CK1 EC_SMB_CK1/GPIO44 PW R_LED#/GPIO54 PWR_LED 35 H_PECI 4
EC_SMB_DA1 78 93 BATT_AMB_LED#
40,41 EC_SMB_DA1 79 EC_SMB_DA1/GPIO45 BATT_LOW _LED#/GPIO55 95 BATT_AMB_LED# 35
EC_SMB_CK2 SM Bus SYSON 9012_PECI R497 1 9012@ 2 43_0402_1%
18,24,37,7 EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON 38,43
EC_SMB_DA2 80 121
18,24,37,7 EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 PM_SLP_S4#
PM_SLP_S4#/GPIO59 PM_SLP_S4# 8
Pin74(KB930),Pin118(KB9012) are with different PECI pin location,
PM_SLP_S3# 6 100 PCH_RSMRST#
8 PM_SLP_S3#
PM_SLP_S5# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_LID_OUT#
PCH_RSMRST# 8 so HW must co-layout for it.
8 PM_SLP_S5# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 EC_LID_OUT# 9 Please make sure which EC pin will be connected to PECI circuit.
EC_SMI# VCIN1_PROCHOT_R
8 EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05
R605 1 DEG@ 2 E51TXD_P80DATA 16 103 H_PROCHOT#_EC
32 EC UART_TXD 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104
0_0402_5% GPXIOA07 9012_PCH_PWROK 2 9012@ 1
R606 1 DEG@ 2 E51RXD_P80CLK VCCST_PG_EC 18 GPIO0B VCOUT0_PH/GPXIOA07 105 BKOFF# R498 0_0402_5%
32 EC UART_RXD 11,8 VCCST_PG_EC GPIO0C GPO BKOFF#/GPXIOA08 BKOFF# 25
0_0402_5% WL_OFF# 19 GPIO 106 PBTN_OUT# GPXIOA07 2 940@ 1
31 WL_OFF# 25 GPIO0D PBTN_OUT#/GPXIOA09 107 PBTN_OUT# 8 PCH_PWROK 8
EC_SPOK GPU_ACIN R499 0_0402_5%
40 EC_SPOK EC_INVT_PW M/GPIO11 PCH_APW ROK/GPXIOA10 GPU_ACIN 18 +3VALW_EC
R565 FAN_SPEED1 28 108 MINI1_LED# 2 9012@ 1
3 37 FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 MINI1_LED# 31 MAINPWON 40,42 3
0_0402_5% 2 @ 1 REC_MODE_L_R 29 R500 0_0402_5%
32 REC_MODE_L EC_PME#/GPIO15
E51TXD_P80DATA 30
31 E51TXD_P80DATA EC_TX/GPIO16
E51RXD_P80CLK 31 110 EC_ACIN Pin104 This co-layouted circuit is for power fail function of
31 E51RXD_P80CLK 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112
9012_PCH_PWROK EC_ON
PCH_PW ROK/GPIO18 EC_ON/GPXIOD02 EC_ON 35,42 KB930 and KB9012.At KB930, PCH_PWROK will be connected to pin 104.
2
PWR_SUSP_LED# 34 114 ON/OFF
35 PWR_SUSP_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFF 35 At KB9012,PCH_PWROK will be connected to pin 32,
G_SEN_INT 36 GPI 115 LID_SW#
37 G_SEN_INT NUM_LED#/GPIO1A LID_SW #/GPXIOD04 LID_SW# 32,33
116 SUSP# @ @ and VCOUT0_PH will be connected to pin 104.
SUSP#/GPXIOD05 117 SUSP# 38,41,43,44,45
VCCST_PWRGD R696
GPXIOD06 118 9012_PECI VCCST_PWRGD 11,45
R697 10K_0402_5%
1
122 PECI_KB9012/GPXIOD07 R501 1 2 0_0402_5%
AGND/AGND
69
KSI[0..7]
KB Conn.
JKB1 KSO[0..17]
KSI[0..7] 32,34
TP_CLK
+3VS_TP
KSO0 1
KSO[0..17] 32,34
TP_DATA +3VS R609 1
R610 1
@ 2 0_0402_5%
940@ 2 0_0402_5%
TP Conn.
100P_0402_50V8J
1 +3VALW _PCH
2 1 9012@ 2
C553
XEMC@ C551
KSO1 KSI0_SW R577 0_0402_5% KSI0
100P_0402_50V8J
2 1 1
KSO2 3 KSO5_SW R585 1 9012@ 2 0_0402_5% KSO5 0.1U_0402_16V4Z 2 1 C552 JTP1
KSO3 4 3 940@ 1
KSO4 5 4 TP_CLK 2 1
5 +3VALW _EC 2 2 2
XEMC@
KSO5_SW 6 TP_DATA 3
KSO6 7 6 C522 940@ 4 3
KSO7 8 7 0.1U_0603_25V7K U41 D_CK_SDATA 5 4
8 15,16,7 D_CK_SDATA 5
1 KSO8 9 2 1 1 2 KSO5 D_CK_SCLK 6 9 1
9 VCC 1Y1 15,16,7 D_CK_SCLK 6 G1
KSO9 10 5 7 10
KSO10 11 10 KSO5_SW 3 1Y0 4 ON/OFF R608 1 @ 2 0_0402_5% 8 7 G2
11 1Z 1S 34 SMB_ALERT#_R 8
KSO11 12 KSI0_SW 9 R607 1 940@ 2 0_0402_5%
12 2Z 10,9 TP_WAKE#
KSO12 13 10 KSI0 ACES_51524-0080N-001
KSO13 14 13 6 2Y1 7 F3_BTN 2 D36 1 CONN@
14 GND 2Y0 8 TP_INT#
KSO14 15 11 8 ON/OFF 940@ SP01001A900
KSO15 16 15 PAD 2S (For Wake Up and Interrupt) RB751V40_SC76-2
KSO16 17 16 NX3L4684TK_MO-229-10_3X3
KSO17 18 17 940@ R693 2 940@ 1 10K_0402_5%
KSI0_SW
KSI1
19
20
18
19 To TP/B Conn. +3VS_TP
KSI2 21 20
KSI3 22 21 +5VS
KSI4 23 22 +3VALW _EC C663 9012@
23 JTP2
KSI5 24 C523 940@ 0.1U_0402_16V4Z
KSI6 25 24 27 0.1U_0603_25V7K U44 940@ 1 1 2
KSI7 26 25 G1 28 2 1 1 5 1 2 SW4 9012@ SW5 9012@
26 G2 VDD GND 2 TP_DATA 34
3 TJE-532QR5_4P TJE-532QR5_4P
3 TP_CLK 34
ON/OFF 2 6 4 LEFT_BTN# 3 1 RIGHT_BTN# 3 1
PWR_BTN# EC_ENT_RW EC_ENTERING_RW 34 4
E-T_6905-E26N-01R 5 RIGHT_BTN#
CONN@ F3_BTN 3 7 R586 1 940@ 2 5 6 LEFT_BTN# 4 2 4 2
BTN_A EC_IN_RW EC_IN_RW 9 6
SP01000IJ00 0_0402_5%
4 8 R589 1 940@ 2 7
EC_RST# 32,34
5
6
5
6
BTN_B EC_RST# 0_0402_5% GND 8
9 F3 + Power BTN --> Reset EC GND
KB Conn.
JKB2 SLG4N059VTR_TDFN8_2X2
PAD
ACES_88514-00601-071
CONN@ 100g for Press 100g for Press
2 KSO0 1 SP010014M00 2
KSO1 2 1
KSO2 3 2
KSO3 4 3
KSO4
KSO5_SW
5
6
4
5
KB BackLight Conn.
KSO6 7 6 +5VS
KSO7 8 7 JBL1
8
S
KSO8 9 3 1 +5VS_BL 4 6
KSO9 10 9 +5VALW 3 4 G2 5
KSO10
KSO11
11
12
10
11 R451
BL@
Q44
2
1
3
2
G1
PW R_LED#
LED LED6 +3VALW
G
PW R_LED# 33
2
1
KSO13 14 1 BL@ 2 KBL_EN_R ACES_50504-0040N-001 Q17 R699 51_0402_5%
KSO14 15 14 CONN@ 2 L2N7002LT1G_SOT23-3
15 34 PWR_LED
KSO15 16 1 @ 2 SP01000Z300 G 34 BATT_AMB_LED# BATT_AMB_LED# 3 4 1 2
16 A
1
KSO16 17 R592 S R698 390_0402_5%
3
17 D
1
2
KSI3 22 21 L2N7002LT1G_SOT23-3 2 abnormall shutdown PW R_LED# 1 2 1 2
22 @ B
KSI4 23 @ R700 51_0402_5%
KSI5 24 23
KSI6 25 24 27 PWR_SUSP_LED# 3 4 1 2
25 G1 34 PWR_SUSP_LED# A
KSI7 26 28 R701 390_0402_5%
26 G2 +3VS
LTST-C295TBKF-CA_AMBER-BLUE
E-T_6905-E26N-01R HDD LED For BCM57786X
2
3 CONN@ +3VS 3
5
R740 LED4 U39
1
51_0402_5% 2 EC_W LAN_LED# 1 2 1 2
P
B 5IN1_LED# 29 34 EC_WLAN_LED#
1 2 2 1 MEDIA_LED# 4
Y
A R702 680_0402_5%
A A
1
PCH_SATALED# 6
G
LTST-C191KFKT-2CA_ORANGE
LTST-C191TBKT-CA_BLUE MC74VHC1G08DFT2G_SC70-5
3
ON/OFF BTN +3VALW _EC +3VLP
2
R522 R534
100K_0402_5% 100K_0402_5%
D24
940@ 9012@ TPM Board JTPM1
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB & TP & TPM Connector & LED
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
32,33 ON/OFFBTN# DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 35 of 51
A B C D E
A B C D E
3
@ 2 CONN@ GND
+VDDA
SP02000K200
D27 D37
AZ5125-02S.R7G_SOT23-3 AZ5125-02S.R7G_SOT23-3
XEMC@ XEMC@
(output = 300 mA)
1
1 GND 1
R523
HP_PLUG#_1 100K_0402_5%
1
SM010014520 3000ma 220ohm@100mhz DCR 0.04
2
+PVDD_HDA
40mil
1
D
L33 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z Q31 2 HP_PLUG# GND GND
+VDDA
FBMA-L11-201209-221LMA30T_0805 1 1 L2N7002LT1G_SOT23-3 G
1
10U_0603_6.3V6M
C608
C558 C559 S
Headphone Out
3
2 2 GNDA
@ C444 C445
2 2 2 XEMC@ XEMC@ JHP1
GNDA 330P_0402_50V7K 330P_0402_50V7K COM_MIC 4
1 1
GND GND
Place near Pin41 Place near Pin46 3
L36
HP_LEFT R238 1 2 60.4_0603_1% HPOUT_L_1 1 2 0_0603_5%
XEMC@ HPOUT_L_2 1
L55 1 @ 2 0.1U_0402_16V4Z +3VS_VDDA
+3VS
HP_RIGHT R237 1 2 60.4_0603_1% HPOUT_R_1 1 XEMC@ 20_0603_5% HPOUT_R_2 2
1
HD Audio Codec
1
10U_0603_6.3V6M
C605
GNDA
2
2 HP_PLUG# 6 7
GNDA SINGA_2SJ3053-100111F
Place near Pin40 SM010030010 200ma 120ohm@100mhz DCR 0.2 CONN@
20mil +MIC2_VREFO COM_MIC DC230009K00
SM010030010 200ma 120ohm@100mhz DCR 0.2
+3VS_DVDD 0.1U_0402_16V4Z L52 1 @ 2 +3VS HP_PLUG# GNDA
1
+AVDD1_HDA
2
0_0603_5% R539
L54 1 @ 2 0.1U_0402_16V4Z
20mil 1
@ C582
1
C636
1
C564 MIC2JD_1 2.2K_0402_5% D1
+VDDA
10U_0603_6.3V6M
C567
1
2 0_0603_5% 10U_0603_6.3V6M D LBSS138LT1G_SOT-23-3 22K_0402_5% EMC@ 2
2
C561 C562 2 2 2 2 MIC2JD 1 2 COM_MIC
@ 0.1U_0402_16V4Z G
2
2 2 S 1
2
0.1U_0402_16V4Z GND Place near Pin1, 9 C571
GNDA R543
26
40
41
46
36
1
1
9
Place near Pin25, 38 U34 10U_0603_6.3V6M 22K_0402_5%
2
DVDD_IO
AVDD1
AVDD2
PVDD1
PVDD2
CPVDD
DVDD
Internal MIC INT_MIC_R 2 1 INT_MIC C770 1 2 LINE2_C_L 24 GNDA
1
R726 1K_0402_5% 4.7U_0603_6.3V6K LINE2_L
C62 1 2 C769 1 2 LINE2_C_R 23
EMC@ 1000P_0402_50V7K 4.7U_0603_6.3V6K LINE2_R 35mA 42 SPKL+
GNDA C568 1 2 MIC2_C_L 17 68mA 600mA SPK_OUT_L+
GNDA GNDA GND
COM_MIC 2 1 COM_MIC_R 4.7U_0603_6.3V6K MIC2_L
Combo MIC
R540 1K_0402_5% C569 1 2 MIC2_C_R 18 43 SPKL-
4.7U_0603_6.3V6K MIC2_R SPK_OUT_L-
22 45 SPKR+
LINE1_L SPK_OUT_R+
21
LINE1_R 44 SPKR-
19 SPK_OUT_R-
MIC1_L 32 HP_LEFT
20 HPOUT_L
MIC1_R 33 HP_RIGHT
35 HPOUT_R
1 CBN 8 HDA_SDIN0_AUDIO 1 R547 2 HDA_SDIN0 6
C570 SDATA_IN 33_0402_5%
2.2U_0402_6.3V6M 37 5
2 CBP SDATA_OUT HDA_SDOUT_AUDIO 6
29 10 HDA_SYNC_AUDIO 6
+MIC2_VREFO MIC2_VREFO SYNC
10mil 11 HDA_RST_AUDIO#
RESETB HDA_RST_AUDIO# 6
30
3 MIC1_VREFO_R 6 3
+INTMIC_VREFO 10mil31 BCLK HDA_BITCLK_AUDIO 6
MIC1_VREFO_L XEMC@ +INTMIC_VREFO
C584 1 2
10mil27 1 XEMC@ 2 1 2 C573
GNDA LDO1_CAP
10U_0603_6.3V6M R548 0_0402_5% 22P_0402_50V8J
Int. MIC
1
GNDA C574 1 2 39 GND R417
10U_0603_6.3V6M LDO2_CAP 2
C583 1 2 7 GPIO0/DMIC_DATA 10K_0402_5%
GND LDO3_CAP
10U_0603_6.3V6M 3 15mil L51 15mil
R546 2 1 20K_0402_1% 15 GPIO1/DMIC_CLK 0_0603_5% JMIC1
GNDA
2
JDREF 47 INT_MIC_R 1 XEMC@ 2 INT_MIC_R_1 1
PD# EC_MUTE# 34 2 1
R529 2
Place near 1
GND 47K_0402_5% C550
codec C575 1 2 2.2U_0402_6.3V6M CPVEE 34 12 MONO_IN 2 1 BEEP#_R 1 @ 2 XEMC@ 3
CPVEE PCBEEP BEEP# 34 G1
10mil13 220P_0402_50V7K 4
HP_PLUG#_1 R545 2 1 39.2K_0402_1% SENSE_A 16 C555 2 G2
MIC2JD_1 R549 2 @ 1 20K_0402_1% 14 SENSE A MONO_OUT 38 1U_0402_6.3V6K R530 ACES_88266-02001
SENSE B AVSS2 47K_0402_5% CONN@
2
R531
4.7K_0402_5%
C556
@ 100P_0402_50V8J
0.1U_0402_16V4Z
C576
10U_0603_6.3V6M
C578
4 25 GNDA
DVSS AVSS1 2
1
49 2 2 2
GND
ALC3225-CG_MQFN48_6X6
GND
GNDA Place next pin27 GNDA
J7 J14
JUMP_43X39 JUMP_43X39
4 1 2 1 2 4
@ 1 2 @ 1 2
GNDA
J11 J12
JUMP_43X39 JUMP_43X39
1 2 1 2
@ 1 2 @ 1 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC3225
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 36 of 51
A B C D E
FAN1 Conn
+5VS C632
4.7U_0603_10V6K H3 H4 H5 H6 H9 H10 H11 H12 H17 FD1 FD2
1 2 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
@ @
1
U31
1
1 8 FIDUCIAL_C40M80 FIDUCIAL_C40M80
2 EN GND 7
+VCC_FAN1 3 VIN GND 6 FD3 FD4
2 @ 1 4 VOUT GND 5 @ @ @ @ @ @ @ @ @
34 EN_DFAN1 VSET GND
R515 1 AP2113AMTR-G1_SO8 H13 H14 H15 H16 H20 H24 @ @
1
0_0402_5% H_4P0 H_4P0 H_4P0 H_4P0 H_4P0 H_4P0
C626 FIDUCIAL_C40M80 FIDUCIAL_C40M80
0.1U_0402_16V4Z
2 @
1
C627 @ @ @ @ @ @
4.7U_0603_10V6K
+3VS 1 2 H21 H27
H_3P0 H_3P7
@ C631
1
1000P_0402_50V7K
R516 1 2
1
10K_0402_5%
40mil JFAN1
2
+VCC_FAN1 1 @ @
2 1 4
34 FAN_SPEED1 2 GND
3 5
3 GND
1
C630 H22 H23
1000P_0402_50V7K ACES_88231-03041 H_2P5N H_2P5X3P5N
XEMC@ CONN@
2
SP020020710
@ @
1
+3VS
1
R518 +3VS
10K_0402_5%
GSEN@ U2 GSEN@
1 C633 1 2 10U_0603_6.3V6M
2
8 Vdd_IO GSEN@
4 CS 14 C628 1 2 0.1U_0402_16V4Z
18,24,34,7 EC_SMB_CK2 SCLSPC Vdd
18,24,34,7 EC_SMB_DA2 6
7 SDA/SDI/SDO
R519 1 @ 2 10K_0402_5% SDO/SA0 11 G_SEN_INT
+3VS INT1 G_SEN_INT 34
R520 1 GSEN@ 2 10K_0402_5% 16 9
15 ADC1 INT2
13 ADC2 10
ADC3 RES
2
3 NC 5
NC GND 12
GND
LIS3DHTR_LGA16_3X3
GSEN@
LIS3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole & G-Sensor
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 37 of 51
A B C D E
+5VALW +5VS
2
U33
DMN3030LSS-13_SOP8L-8 R552
8 1 U11 @ J36 100K_0402_5%
7 2 +3VALW 1 14 1 2 +3VS @
VIN1 VOUT1 1 2
2
4.7U_0603_10V6K
C587
1U_0402_10V6K
C588
6 3 1 1 2 13
1
VIN1 VOUT1
4.7U_0603_10V6K
C585
4.7U_0603_10V6K
C586
1 1 5 35V@ R551 47K_0402_5% C976 JUMP_43X118 SUSP
43 SUSP
35V@ 470_0603_5% SUSP# 2 R927 1 3VS_ON 3 12 2 1 330P_0402_50V7K
35V@ 35V@ C980 ON1 CT1
1 1
4
2 2 1 2 4 11 Q29
+5VALW
1
2 2 +5VS_R 0.1U_0402_16V4Z VBIAS GND L2N7002LT1G_SOT23-3
D
1
2 R926 1 5VS_ON 5 10 2 1 @
ON2 CT2
3
0_0402_5% 330P_0402_50V7K 2
34,41,43,44,45 SUSP#
C979 +5VALW 6 9 C967 @ J37 G
VIN2 VOUT2
1
20mil 10mil 1@ 2 7 8 1 2 +5VS S
3
R553 1 35V@ 2 5VS_GATE 5 SUSP 0.1U_0402_16V4Z VIN2 VOUT2 1 2 R555
+VSB
100K_0402_5% 15 JUMP_43X118 10K_0402_5%
Q30B GPAD @
1
4
6
C592 DMN66D0LDW -7_SOT363-6 TPS22966DPUR_SON14_2X3
Reserved
2
0.1U_0603_25V7K 35V@
35V@
SUSP 2 2
Q30A
1
DMN66D0LDW -7_SOT363-6
35V@
+3VALW TO +3VS
2
R566 R567 R568
+3VALW +3VS 470_0603_5% 470_0603_5% 470_0603_5%
U35 @ @ @
DMN3030LSS-13_SOP8L-8
1
8 1
7 2 +0.675VS_R +1.05VS_VTT_R +1.8VS_6511_R
2
4.7U_0603_6.3V6K
C594
4.7U_0603_6.3V6K
C595
4.7U_0603_6.3V6K
C596
2 2 2 6 3 2 1 2
D D D
1
1U_0402_6.3V6K
C597
35V@ 5 35V@ R558
470_0603_5% 2 SUSP 2 SUSP 2
6511_PW R_EN# 27
35V@ 35V@ G G G
4
6 1
3
+3VS_R L2N7002LT1G_SOT23-3 L2N7002LT1G_SOT23-3 L2N7002LT1G_SOT23-3
@ @ @
10mil
20mil 2 35V@ 1 3VS_GATE 2 SUSP
+VSB +1.35V +5VALW
R559 1 Q32A
1
3
2
0.1U_0603_25V7K 35V@
35V@ R573 R554
SUSP 5 2 470_0603_5% 100K_0402_5%
@ @
Q32B
4
1
DMN66D0LDW -7_SOT363-6 SYSON#
35V@ +1.35V_R
3
3VS_GATE 11
6
5 SYSON
SYSON 34,43
2 SYSON# Q40B
Q40A DMN66D0LDW -7_SOT363-6
4
DMN66D0LDW -7_SOT363-6 @
1
@
3 3
2
R570 R571
470_0603_5% 470_0603_5%
+3VS +3VSDGPU @ @
U12 VGA@ 100mil(1.5A)
1
1
5 OUT +1.5VSDGPU_R +1.8VSDGPU_R
IN
2
3
2
4 GND C621
IN VGA@
2 1 4.7U_0603_6.3V6K
C620 3 VGA_ON# 2 5 VGA_ON#
4.7U_0603_6.3V6K EN Q45A Q45B
VGA@ G5243T11U_SOT23-5 DMN66D0LDW -7_SOT363-6 DMN66D0LDW -7_SOT363-6
4
1 @ @
8,9 VGA_ON
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 38 of 51
A B C D E
A B C D
+5VS
1 VIN 1
1
GND EMI@ PC102 EMI@ PC104 @PR102
@ PR102
100P_0603_50V8 1000P_0603_50V7K 34,4,40 H_PROCHOT# 47K_0402_1% @ PR103
@PR103
2
10K_0402_1%
2
8
@ PC105
6
D 0.022U_0402_16V7K 3
P
2 2 1 1 + BATT_TEMP 34,40
@ PQ101A G O 2
-
G
DMN66D0LDW-7_SOT363-6 @ PU102A
@PU102A
1
S LM393DR_SO8
4
@PD102
@ PD102
1
LL4148_LL34-2 @ PR104
@PR104
1
1.5M_0402_5%
@ PC106 @ PR101
@PR101
2
100P_0402_50V8J 100K_0402_1%
2
1
2
@ PR106 2
H_PROCHOT# 47K_0402_1%
VIN @ PU102B
@PU102B
8
@PC107
@ PC107 LM393DR_SO8
3
D 0.022U_0402_16V7K 5
P
5 2 1 7 +
O
2
@ PQ101B G 6
- ACIN 34,41,8
G
@ PD101 DMN66D0LDW-7_SOT363-6
1
LL4148_LL34-2 S
4
@ PD103
@PD103
930@ PD104 LL4148_LL34-2 @ PR107
@PR107
1
LL4148_LL34-2 @PJ101
@ PJ101 1.5M_0402_5%
2 1 1 2
2
1 2 1
1
BATT+ JUMP_43X39 @ PR108
@PR108 @ PR109
@PR109
68_1206_5% 68_1206_5%
930@ PQ102
TP0610K-T1-E3_SOT23-3
2
2
N1 3 1
VS
1
930@ PR111
2
22K_0402_1%
1 2
3
35 51ON# 3
@PR105
@ PR105
0_0402_5%
1 2
+3VLP +CHGRTC
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom V5WE2 M/B LA-9531P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, December 03, 2012 Sheet 39 of 51
A B C D
A B C D
+3VLP
CONN@ PJP201
SUYIN_200275GR008G13GZR
10 EMI@ PL201
GND 9 HCB2012KF-121T50_0805
GND 8
8 7
BATT_S1 1 2 BATT+ <45,47>
1
7 6 BI @ PC209
6 5
1
TH 2 1 0.1U_0603_25V7K
+3VLP
2
5 4
1
EC_SMCK PR206
1
4 3 EC_SMDA 6.49K_0402_1% EMI@ PC202 @ PR229 @ PR230
1
3 2
1
PR203 1000P_0402_50V7K 10K_0402_1% 10K_0402_1%
2
2 1 PR202 PR208 1K_0402_1%
2
1
1
100_0402_1% 1K_0402_1%
1
1 2 @ PU204
BATT_TEMP 34,39 1 8
PR201 @ PR231
2
100_0402_1% 100K_0402_1% VCC TMSNS1
EC_SMB_CK1 34,41
2 7 2 1
2
GND RHYST1
EC_SMB_DA1 34,41
1
MAINPWON 3 6 @ PR232
OT1 TMSNS2 47K_0402_1%
4 5 @ PH202
OT2 RHYST2 100K_0402_1%_TSM0B104F4251RZ
G718TM1U_SOT23-8
2
2 2
3 1
PH201 under CPU botten side : 120W
B+ +VSBP
0.22U_0603_25V7K
Recovery at 56 degree C
1
+3VLP +EC_VCCA
PC205
PC206
@ PR211
34 EC_SPOK
100K_0402_1%
2
3 3
@ PR212 @ @
2
1
4.87K_0402_1%
1
1
@ PR213 0.1U_0603_25V7K 21K_0402_1% 12.4K_0402_1% 90W@ PR218
2
1
100K_0402_1% 10.5K_0402_1%
@ PR217 @ PU201
2
@ PR219 @ PR216 100K_0402_1% 1 8
2
VCC TMSNS1
1
1K_0402_1% D 100K_0402_1%
2
1 2 2 34,39,4 H_PROCHOT# 2 7 2 1 VCIN0_PH 34
2
42 SPOK G @ PQ203 GND RHYST1 @ PR220
2N7002KW_SOT323-3 34,42 MAINPWON MAINPWON 3
~OT1 TMSNS2
6 9.53K_0402_1%
1
D
S
3
@ PC208 2 1 2 4
~OT2 RHYST2
5 1 2 VCIN1_PROCHOT 34
1U_0402_6.3V6K G
2
1
PH201
1
100K_0402_1%_TSM0B104F4251RZ @ PR222
@ PJ201 B value:4250K±1% 10.5K_0402_1%
1 2 PR225
+VSBP +VSB
2
1 2 10K_0402_1%
JUMP_43X39
2
1
1_0402_1%
PR227
0_0402_5%
PR226
4 4
2
2
34 ECAGND
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 40 of 51
A B C D
A B C D
1
D
2 PQ301
G 2N7002KW_SOT323-3
S
3
PQ304
SIS412DN-T1-GE3_POWERPAK8-5
1 2 1 2 1
2
1
PR302 PR301 5 3 1
1M_0402_5% 3M_0402_5%
100ppm
0.01U_0402_50V7K
VIN PQ302 P1 PQ303 P2 B+ CHG_B+
4
AON6414AL_DFN8-5 SIS412DN-T1-GE3_POWERPAK8-5 PR303
1_0402_1%
1 1 0.02_1206_1% EMI@ PL301
PC308
PR305
1
2 2 1.2UH_PNS40201R2YAF_3A_30%
5 3 3 5 1 4 1 2
2200P_0402_50V7K
4x4x2
2
0.1U_0402_25V6
2 3 @
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
2
0.1U_0402_25V6
4
4
1
1
1_0402_1%
PC303
PC304
@EMI@ PC305
EMI@ PC307
PR304 BQ24735_BATDRV 1 2
1
1
VIN
PC301
PC302
PC306 PR306
2
0.1U_0402_25V6 4.12K_0603_1%
2
2
@ 1 2
2
2
0.1U_0603_25V7K
0.1U_0402_25V6
PD302
BAS40CW_SOT323-3
1
PC311
PC309
2
1
4.12K_0603_1%
4.12K_0603_1%
PC310
0.047U_0402_25V7K
1
1 2
PR307
PR308
5
10_1206_1%
0_0603_5%
1
PR310
PR309
2
PR311 PQ305
0_0603_5% SIS412DN-T1-GE3_POWERPAK8-5
BQ24735_ACN
2 2
BQ24735_BST 2
BQ24735_ACP
1
DH_CHG 1 2 DH_CHG-1 4
BQ24735_LX
1 2 PD303
DH_CHG
RB751V-40_SOD323-2
PC312 PL302 PR312
3
2
1
1U_0603_25V6K 1 2 10UH_FDSD0630-H-100M-P3_3.8A_20% 0.01_1206_1%
BQ24735_LX 1 2 CHG 1 4 BATT+
PC313
5
1U_0603_25V6K 2 3
680P_0402_50V7K 4.7_1206_5%
20
19
18
17
16
SIS412DN-T1-GE3_POWERPAK8-5
1 CSOP1
1 CSON1
VCC
PHASE
HIDRV
BTST
REGN
10U_0805_25V6K
10U_0805_25V6K
21
0.1U_0402_25V6
0.1U_0402_25V6
PAD
PC314
PC317
PC315
PC318
1
1
PQ306
1 15 DL_CHG 4
2
ACN LODRV
2
1
2 14
ACP GND PR314
3
2
1
BQ24735RGRR_QFN20_3P5X3P5 10_0603_5%
0.1U_0603_25V7K
2
BQ24735_CMSRC 3 13 SRP 1 2 CSOP1
CMSRC SRP
PC321
BQ24735_ACDRV 4 12 SRN 1 2 CSON1
2
ACDRV SRN PR315
6.8_0603_5%
+3VLP 1 2 ACOK 5 11 BQ24735_BATDRV
PR316 ACOK ACDET BATDRV
100K_0402_1%
IOUT
SDA
SCL
ILIM
3 34,39,8 ACIN 3
6
10
ACDET PR317
316K_0402_1%
2 1 +3VALW
1
100K_0402_1%
1
@ PR318
@PR318 VIN
0.01U_0402_25V7K
PC322
PR320
1
2M_0402_1%
Vin Detector
2
2
2
1
1
PR322
@PR321
@ PR321 422K_0402_1% Min. Typ Max.
2M_0402_1% L-->H 17.520V 18.006V 18.504V
2
ACDET
2200P_0402_50V7K
@ PQ307
ILIM and external DPM
1
100K_0402_1% PR324
1 2 2 64.9K_0402_1%
34 FSTCHG EC_SMB_DA1 34,40 Min. Typ Max.
2
@ PQ308 0_0402_5%
1
2N7002KW_SOT323-3 D 2 1 1 2
ADP_I 34,40
3
2
34,38,43,44,45 SUSP#
1
G PC324 @ PC325
4
100P_0402_50V8J 0.1U_0402_16V7K 4
S
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 41 of 51
A B C D
5 4 3 2 1
D D
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
4.7U_0402_6.3V6M
IN EN2 PR404 PC401 B+
4.7U_0402_6.3V6M
1
1
6 1 2 1 2
@ PC426
BST_3V
150K_0402_1%
BS
1
1
@EMI@ PC403
EMI@ PC410
PC408
PC405
@ PC425
PR405
0_0603_5%
0.1U_0603_25V7K
2
PL402
2
2
@ 10 LX_3V 1 2
+3VALWP
2
LX
9 4
@EMI@ PR409
1UH_PCMB053T-1R0MS_7A_20%
GND OUT
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
2 5
680P_0603_50V7K 4.7_1206_5%
40 SPOK PG LDO +3VLP
PC411
PC416
PC414
PC413
1
SY8208BQNC_QFN10_3X3
2
PC422
13V_SN
4.7U_0603_6.3V6M
2
Check pull up resistor of SPOK at HW side
C C
@EMI@ PC423
3.3V LDO 150mA~300mA
2
Vout is 3.234V~3.366V
TDC=8A
@ PJ401
+3VALWP 1 2 +3VALW
1 2
JUMP_43X118
B+ EMI@ PL404
HCB2012KF-121T50_0805 PU402
1 2 5V_VIN 8 1 3V5V_EN
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
IN EN1
3 ENLDO_3V5V PR403 PC404
EN2
1
1
PC406
PC407
EMI@ PC409
@EMI@ PC402
0_0603_5% 0.1U_0603_25V7K
B 6 BST_5V 1 2 1 2 B
BS
2
@
PL403
9 10 LX_5V 1 2 +5VALWP
GND LX
VCC_3.3V 5 4 1UH_PCMB053T-1R0MS_7A_20%
VCC OUT
1
680P_0603_50V7K 4.7_1206_5%
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
2 7
@EMI@ PC424 @EMI@ PR408
PG LDO VL
1
PC420
PC417
PC418
PC415
PC412
4.7U_0603_6.3V6M
SY8208CQNC_QFN10_3X3
2
15V_SN
2
2
1
PC421
4.7U_0603_6.3V6M
2
@ PJ402
+5VALWP 1 2 +5VALW
2
1 2
JUMP_43X118
Vout is 4.998V~5.202V
5V LDO 150mA~300mA TDC=8A
PR407
2.2K_0402_5%
1 2
34,35 EC_ON
@ PR402
1 2
34,40 MAINPWON 0_0402_5%
A A
3V5V_EN
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR406
PC419
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALW/5VALW
EN1 and EN2 dont't floating AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9532P Schematic
Date: Monday, December 03, 2012 Sheet 42 of 51
5 4 3 2 1
A
2200P_0402_50V7K
10U_0805_25V6K
Ipeak=12.34A ; 1.2Ipeak=14.808A ;Imax=8.638A
0.1U_0402_25V6
1/2Delta I=0.7353A (F=300K Hz)
1
PC502
EMI@ PC503
@EMI@ PC521
PR504=(1.2Ipeak-1/2Delta I) *Rds(on)(max)*1.2/9uA=8.45Kohm
choose PR504=8.45Kohm (for safety >1.2Ipeak)
MDV1525URH_PDFN33-8-5
2
Rds(on)=5.0m ohm(max) ; Rds(on)=4.2m ohm(typical) +1.35VP
Ilimit_min=(8.366K*9uA)/(5.0m*1.2)=15.058A
PQ502
Ilimit_max=(8.535K*11uA)/(4.2m*1.2)=22.352A
UG_1.35V 4
Iocp=Ilimit+1/2Delta I=15.79A~23.09A
JUMP_43X39
Iocp(min)>1.2Ipeak
PJ503
1
2012/9/6
3
2
1
2
@
2
PR502 PC504 PL501
OVP=110% 115% 120% 2.2_0603_5% 0.1U_0603_25V7K S COIL 1.5UH 20% TMPB0604M-1R5MN-Z01 11A
BST_1.35V 2 1 BST_1.35V-1 2 1 1 2
+0.675VSP
靠靠Output Cap PAD 6.6x7.3x3.8 TAI-TECH +1.35VP
S TR MDU1512RH 1N POWERDFN56-8
10U_0805_25V6K
10U_0805_25V6K
LX_1.35V
1
DCR:8.5mΩ
5
20
19
18
17
16
1
1
PC501
PC505
PU501 @EMI@ PR503
4.7_1206_5% 1
VTT
BOOT
UGATE
PHASE
VLDOIN
21
2
2
PAD
PQ503
+ PC506
1 15 LG_1.35V 4 330U_2.5V_M
VTTGND LGATE
1
@EMI@ PC507
680P_0402_50V7K 2
2 14
2
VTTSNS PGND PR504
3
2
1
8.45K_0402_1%
3 13 2 1
GND RT8207MZQW_WQFN20_3X3 CS
4 12 Rds=4.2mΩ(Typ)
+VTT_REFP VTTREF VDDP
5.0mΩ(Max)
5 11 2 1
+1.35VP VDDQ VDD PR505 +5VALW
PGOOD
+3VALW
1
1U_0603_10V6K
5.1_0603_5% @ PJ504
TON
PR513 PC508 +1.35VP 1 2 +1.35V
FB
S3
S5
1 2
10K_0402_1%
1_0402_1% 0.033U_0402_16V7K
2
1
PC509
1 2
15 DDR_VTT_PG_CTRL JUMP_43X118
S3_1.35V 7
S5_1.35V 8
10
PR506
PC510
1U_0603_10V6K @ PJ505
2
@ PR501 1 2
680K_0402_1% @ 1 2
2
1 2
34,38,41,44,45 SUSP# PGOOD_1.35V JUMP_43X118
PR507 PR508
1_0402_1% 887K_0402_1%
1 2 2 1 1.35V_B+
1 34,38 SYSON 1
@ PJ506
2
1
@ PC512 2 1
@ PQ501 0.1U_0402_16V7K
2N7002KW_SOT323-3 FB=0.75V @ PJ511
1
D
2
1
+0.95VSDGPUP 1 2
2 To GND = 1.5V 1 2
38 SUSP SUSP
G
@ PC511
0.1U_0402_16V7K PR510 To VDD = 1.8V JUMP_43X118 +0.95VSDGPU
2
10K_0402_1%
S
3
22U_0805_6.3V6M
22U_0805_6.3V6M
16
15
14
13
1
1
PC533
VGA@ PC534
VGA@ PL506
BOOT
VIN
EN
PWRGD
1UH_PCMB063T-1R0MS_12A_20%
2
2
@ 1 12 LX_0.95V 1 2
VIN PH
+0.95VSDGPUP
1
@EMI@ PR533
2 11
4.7_0402_1%
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
VIN PH
1
VGA@ PC535
VGA@ PC536
VGA@ PC537
VGA@ PC538
VGA@ PU504
TPS54618
3 10
2
GND PH
2 SNUB_0.95V
4 9
GND SS/TR
VSENSE
RT/CLK
2200P_0402_50V7K
COMP
AGND
680P_0402_50V7K
17
PW RPD
VGA@ PC542
@EMI@ PC539
1
VGA@ PC540
22P_0402_50V8J
19.1K_0402_1%
5
1
VGA@ PR535
1
3300P_0402_50V7K 18K_0402_1%
169K_0402_1%
VGA@ PR537
VGA@ PR534
2
1
2
2
STATE S3 S5 1.35VP VTT_REFP 0.675VSP
1 2
2
S0 Hi Hi On On On VGA@ PC541
FB=0.799V
1
Off 2 +0.95VSDGPUP
VGA@ PR536
S3 Lo Hi On On (Hi-Z) 100K_0402_1% Ipeak=4.28A ; 1.2Ipeak=5.136A ;Imax=2.996A
F=131904/(PR534^0.9492)=1000KHz, PR534=169KΩ
2
S4/S5 Lo Lo Off Off Off
(Discharge) (Discharge) (Discharge) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/07/10 Deciphered Date 2013/07/10 Title
Note: S3 - sleep ; S5 - power off THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.35VP/0.675VSP/0.95VSDGPUP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 43 of 51
A
5 4 3 2 1
VFB= 0.704V
Vo=VFB*(1+11.5K/10K)= 1.5V VGA@EMI@ PL504
Freq=290KHz(typ) HCB2012KF-121T50_0805
1.5VSG_B+ 2 1
D B+ D
Cesr= 15m ohm
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
SIS412DN-T1-GE3_POWERPAK8-5
Ipeak= 4.7A Imax= 3.29A Iocp=5.64A
VGA@EMI@ PC516
VGA@ PC517
@ PC518
@EMI@ PC519
Iocp= 5.72A~6.43A
1
VGA@ PQ504
2
4
3
2
1
VGA@ PU502 2.2_0603_1% 0.1U_0603_25V7K
VGA@ PR512 1 10 BST_1.5VSG 1 2 1 2
56.2K_0402_1% PGOOD VBST
2 1 TRIP_1.5VSG 2 9 DH_1.5VSG VGA@ PL502
TRIP DRVH 4.7UH_PCMB063T-4R7MS_5.5A_20% +1.5VSDGPUP
3 8 SW _1.5VSG 1 2
43,45,47 VGA_PG EN SW
5
FB_1.5VSG 4 7 +5VALW
VFB V5IN
SI7716ADN-T1-GE3_POWERPAK8-5
1
RF_1.5VSG 5 6 DL_1.5VSG 1
TST DRVL
VGA@ PQ505
1
1
11 VGA@EMI@ PR518 + VGA@ PC523
TP VGA@ PC515 4 4.7_1206_5% 330U_2.5V_M
Resistance(KΩ) Frequency(KHz) VGA@ PR514 TPS51212DSCR_SON10_3X3 1U_0603_10V6K
2
470K_0402_1% 2
470 290
2
1
C Rds=13.5mΩ(Typ) VGA@EMI@ PC522 C
3
2
1
680P_0402_50V7K
200 340 16.5mΩ(Max)
2
100 380
39 430 VGA@ PR515
FB=0.704V 11.5K_0402_1%
2 1
1
1
@ PC526
1U_0402_6.3V6K
2
Note:Iload(max)=3A
PU503
APL5930KAI-TRG_SO8
6
B 5 VCNTL 3 B
0.022U_0402_16V7K
9 VIN VOUT 4 +1.5VSP
VIN VOUT
1
1
PC528 8
EN
1
4.7U_0603_6.3V6K 7 2 PR519
PC529
22U_0805_6.3V6M
22U_0805_6.3V6M
GND
POK FB 20K_0402_1%
2
1
PC525
PC524
FB=0.8V
1
PR523 FB_1.5VSP
1_0402_1%
2
1 2 +1.5VSP_ON @
34,38,41,43,45 SUSP#
1
1
PR521
1
@ PR522 22.6K_0402_1%
@ PJ509 PC527 22K_0402_5%
2
+1.5VSDGPUP 1 2 +1.5VSDGPU 0.1U_0402_16V7K
2
1 2
2
JUMP_43X118
@ PJ510
1 2
1 2
JUMP_43X118
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VSP/+1.5VSDGPUP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 44 of 51
5 4 3 2 1
5 4 3 2 1
PR603
D 1K_0402_1% D
2 1 SUSP# 34,38,41,43,44
@ PR607
1M_0402_1%
1 2
B+ PC606
PU601 0.1U_0402_16V7K
2200P_0402_50V7K
8 1 EN_+1.05VSP PR602 PC605 1 2
IN EN
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0_0603_5% 0.1U_0603_25V7K
6 BST_+1.05VSP 1 2 1 2 PL601
BS
1
@EMI@ PC602
EMI@ PC603
PC604
PC623
0.68UH_PCMC063T-R68MN_15.5A_20%
9
GND LX
10 SW_+1.05VSP 1 2 +1.05VSP
2
4
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
FB_+1.05VSP
FB
1
1
PC624
PC625
PC626
PC627
PC628
PC629
1 2 3 7
+3VS
@ PR613 ILMT BYP +3VALW
2
1
10K_0402_1% 2 5 @EMI@ PR604
PG LDO
1
PR619 4.7_0805_5% @
@ PC614 1M_0402_1% SY8208DQNC_QFN10_3X3
1 2
0.1U_0402_16V7K
2 @EMI@ PC607
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
680P_0402_50V7K
2
1
1
PC601
PC608
C PR618 C
10K_0402_1% PR605
2
2 1 100K_0402_1%
+3VS
2 1 @ PJ602
1 2
+1.05VSP 1 2 +1.05VS_VTT
VFB=0.6V
11,34 VCCST_PWRGD JUMP_43X118
@ PJ603
1 2
1 2
1
JUMP_43X118
PR608
133K_0402_1%
+3VS
2
1
@ PC615
1U_0402_6.3V6K
2
+3VS
Note:Iload(max)=3A
PU602
1
APL5930KAI-TRG_SO8
6 @ PC617
5 VCNTL 3 0.022U_0402_16V7K 1U_0402_6.3V6K
+1.8VS_6511
2
9 VIN VOUT 4
VIN VOUT
1
1
B PC610 8 B
EN
1
PC611
7 2 Note:Iload(max)=3A
22U_0805_6.3V6M
22U_0805_6.3V6M
4.7U_0603_6.3V6K PR609
GND
POK FB 20K_0402_1%
2
1
PC613
PC612
APL5930KAI-TRG_SO8
1
@ PR610 FB_1.8VS_6511 6
0_0402_5% 5 VCNTL 3
0.022U_0402_16V7K
+1.8VSDGPU
2
2
1 2 9 VIN VOUT 4
27 6511_PWR_EN +1.8VS_6511_ON @
VIN VOUT
1
1
1
VGA@ PC620
VGA@ PC618 8
EN
1
1
7 2
22U_0805_6.3V6M
22U_0805_6.3V6M
PR611 4.7U_0603_6.3V6K VGA@ PR614
GND
POK FB
1
VGA@ PC621
PC616 22K_0402_5% FB=0.8V
2
PC622
0.1U_0402_16V7K
2
1
FB_1.8VSDGPU
2
2
43,44,47 VGA_PG @
1
1
VGA@ PR616
@ PR617 15.8K_0402_1%
22K_0402_5%
2
Ien=10uA, Vth=0.3V, notice
2
the res. and pull high
voltage from HW
A A
Ien=10uA, Vth=0.3V, notice
the res. and pull high
voltage from HW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VSP/+1.8VSDGPU/+1.8VS_6511
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 45 of 51
5 4 3 2 1
5 4 3 2 1
51622_VREF
1
150K_0402_1% 100K_0402_1%
39K_0402_1% 274K_0402_1%
150K_0402_1% 8.87K_0402_1%
1
1
PH705
PR702
PR703
PR704
100K_0402_1%_TSM0B104F4251RZ
B value:4250K Close MOS. CPU_B+
EMI@ PL701
2
PC748 @ HCB2012KF-121T50_0805
2
PR708 4700P_0402_25V7K 2 1
B+
2200P_0402_50V7K
10K_0402_1% 1 2
1
2 1 THERM
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
68U_25V_M_R0.36
1
PR705
PR706
PR707
1
PC747 +
PC702
PC703
PC709
EMI@ PC704
@EMI@ PC705
PC706
0.1U_0402_25V6 PR709 PR710
D 2 1 392K_0402_1% 56K_0402_1% D
2
1 2 1 2 2
@ PR711 @
10K_0402_1%
1 2 SLEWA OCP-I
1
PR712 B-RAMP
39K_0402_1% EMI@ PC749
2 1 F-IMAX 1000P_0402_50V7K
2
O-USR PU702
PR713 CSD97374CQ4M_SON8_3P5X4P5 +CPU_CORE
10K_0402_1% PR701 2.2_0603_5% 5 1 SKIP#
1 2 VBAT 2 1CPU_BOOT1 6 VIN SKIP# 2 PL702
CPU_B+ BOOT_R VDD 3 +5VS
PC701 0.1U_0603_25V7K 0.22UH_PCMB104T-R22MS_35A_20%
1 2CPU_BOOT1-1 7 PGND1 4 CPU_PHASE1 1 4
PWM1 8 BOOT VSW
9 PWM
1
CSP1-1 2 3
680P_0402_50V7K 4.7_1206_5%
PGND2
EMI@ PR714
PC740
1
1U_0603_10V6K DCR:0.82mΩ±5%
2.21K_0402_1%
2
PR715
PR716
1 2
24.9K_0402_1%
2
1 2
16
15
14
13
12
11
10
EMI@ PC714
PH702 PR717
10K_0402_1%_TSM0A103F34D1RZ
IMON
OCP-I
O-USR
VBAT
SLEWA
B-RAMP
F-IMAX
THERM
2
3.01K_0402_1%
1 2 1 2
CSP1 17 8 Close choke.
CSP1 VR_ON VR_ON 11 PC711 B value:3435K
CSN1 18 7 SKIP# 0.082U_0402_16V7K
CSN1 SKIP#
1
@ PR718 0_0402_5% 1 2
2 1 19 6 PWM1 PR734
@ PR719 0_0402_5% CSN2 PWM1 10K_0402_1% PC712
1 2 20 PU701 5 0.082U_0402_16V7K
C CSP2 PWM2 C
1 2 CSN1
2
+3VS 21 TPS51622RSM_QFN32_4X4~D 4
PU3 N/C CSP1
22 3
N/C PGOOD VGATE 11,8
@ PR721 0_0402_5%
11 VSS_SENSE 1 2 GFB 23 2 VDD 2 1 Use X7R is better or far away inductor.
GFB VDD +3VS
2
@ PR722 0_0402_5%
Maximum current: 32A
VR_HOT#
1 2 VFB 24 1
ALERT#
@ PR724 @ PR725
DROOP
1
COMP
VREF
0_0402_5%
VCLK
2K_0402_1%
GND
PAD
V5A
PC746
1U_0402_6.3V6K
1
25
26
27
28
29
30
31
32
33
+1.05VS_VTT
75_0402_1%
130_0402_1%
54.9_0402_1%
0.1U_0402_16V7K
1
1
PR729
PR730
PR731
PC741
DROOP
Close to PWR IC
2
COMP
PC742 @
51622_VREF
2
100P_0402_50V8J
2 1
VR_SVID_CLK 11
1
V5A 2 1
+5VS
PR732
10_0603_5%
1
B PC745 B
1U_0402_6.3V6K Consider use 0603 for inrush power.
2
VIN 12V-20V
MAX current 32A
Thermal current 10A
Dynamic current 27A
Over current level 45A
Switching frequency 600KHz
Boot voltage 1.7V
DC Load- line 2m Ohm
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 46 of 51
5 4 3 2 1
5 4 3 2 1
0.1U_0603_25V7K
2200P_0402_50V7K
MARS XT HCB2012KF-121T50_0805
10U_0805_25V6K
10U_0805_25V6K
2 1
@EMI@ PC801
VGA@EMI@ PC802
VGA@ PC803
VGA@ PC804
1
1
18
18
18
18
18
GPU_VID_5
GPU_VID_4
GPU_VID_3
GPU_VID_2
GPU_VID_1
2
MDU1516URH_POWERDFN56-8-5
5
VGA@ PR801
20K_0402_1% +3VSDGPU
D D
1 2
VGA@ PQ803
+3VSDGPU
1
VGA@ PC805 4
0.1U_0402_16V7K
2
VGA@ PR802 VGA@ PC806
@ PR803 2.2_0603_5% 0.22U_0603_10V7K
3
2
1
1
1
1_0402_1% BOOT2_VGA 2 1 BOOT2_2_VGA 1 2 VGA@ PR848
VGA@ PR845
@ PR843
@ PR841
@ PR839
@ PR837
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
1 2 0_0603_5%
18 GPU_DPRSLPVR UGATE2_VGA 1 2 UGATE2-1_VGA VGA@ PL804
1
S COIL 0.22UH 20% FDUE0640-H-R22M=P3 25A
@ PR804 PHASE2_VGA 1 2
+VGA_CORE
2
0_0402_5%
V2N_VGA
VGA@ PR806
VGA@ PR807
MDU1511RH_POWERDFN56-8-5
10K_0402_1%
3.65K_0402_1%
2
1
DCR: 0.97mΩ±5%
VGA@ PR808
7x7x4
1_0402_1%
VGA@ PQ804
VGA@ PR809
LGATE2_VGA 4 VGA@EMI@ PR805 10K_0402_1%
2
1
1
4.7_1206_5% 1 2V1N_VGA
@ PR846
VGA@ PR844
VGA@ PR842
VGA@ PR840
VGA@ PR838
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
VSUM+_VGA VSUM-_VGA
3
2
1
1
2
2
VGA@EMI@ PC807 ISEN2_VGA
680P_0402_50V7K
GPU_VID_5
GPU_VID_4
GPU_VID_3
GPU_VID_2
GPU_VID_1
2
+3VSDGPU
1
VGA@ PC808
VGA@ PR814
10K_0402_1%
1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31
C C
1 2
CLK_EN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
2
VGA@ PR810 30
100K_0402_5% BOOT2 29
VGA@ PR811 1 UGATE2 28
43,44,45 VGA_PG PGOOD PHASE2
47K_0402_1% +3VS 1 2 2 27 @ PR812
2 1 3 PSI# VSSP2 26 @ PR813 0_0402_5%
4 RBIAS LGATE2 25 0_0402_5% 2 1
VR_TT# VCCP +5VS
5 24 2 1
6 NTC PWM3 23
7 VW LGATE1 22
COMP VSSP1 VGA_CORE
8 21
5.9K_0402_1%
1 2 9 FB PHASE1 Freq.=400KHz
VGA@ PR815
1000P_0402_50V7K
ISEN3
1
UGATE1
10 Imax=27.00A
VGA@ PC811
BOOT1
ISUM+
ISEN2
1
1
ISEN1
ISUM-
VSEN
IMON
VIN
33P_0402_50V8J 41 1U_0603_10V6K
AGND Iocp=49.00A
2
11
12
13
14
15
16
17
18
19
20
0.22U_0402_10V4Z
1
1
VGA@ PC815
VGA@ PC816
VGA@ PC817
VGA@ PC818
1U_0603_10V6K
0.22U_0603_25V7K
2
B B
BOOT1_VGA
MDU1516URH_POWERDFN56-8-5
10U_0805_25V6K
10U_0805_25V6K
5
VGA@ PC819
VGA@ PC820
1
1
VGA@ PR847
VGA@ PQ801
VSUM-_VGA
0_0603_5%
2
VGA@ PR823 UGATE1_VGA 1 2 UGATE1-1_VGA 4
10_0402_5%
1 2
+VGA_CORE VSUM+_VGA
VGA@ PR824 VGA@ PC821
2.2_0603_5% 0.22U_0603_10V7K
3
2
1
2 1 BOOT1_1_VGA 1 2
1
VGA@ PL802
82.5_0402_5%
2.61K_0402_1%
20 VCC_GPU_SENSE
1
PHASE1_VGA 1 2
@ PR827
+VGA_CORE
0.1U_0603_25V7K
0.22U_0603_16V7K
1
V1N_VGA
VGA@ PC823
@ PC824
2
1
5
VGA@ PC822
VGA@ PR828
MDU1511RH_POWERDFN56-8-5
VGA@ PR831
11K_0402_1%
10K_0402_1%
1
1
330P_0402_50V7K DCR: 0.97mΩ±5%
2
1
VGA@ PR830
VGA@ PR832
7x7x4
3.65K_0402_1%
330P_0402_50V7K
VGA@ PQ802
@ PC825
1_0402_1%
0.01U_0402_25V7K
2
1
VGA@ PR833
2
2
1
4.7_1206_5% 1 2V2N_VGA
2
2
2
3
2
1
20 VSS_GPU_SENSE VSUM-_VGA
2
1
VSUM+_VGA
Layout Note:
VGA@EMI@ PC828
VGA@ PR835 VGA@ PR836 Place near Phase1 Choke 680P_0402_50V7K
2
10_0402_5% 953_0402_1% ISEN1_VGA
1 2 1 2
VSUM-_VGA
A A
1
VGA@ PC829
0.1U_0402_16V7K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+GPU_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 47 of 51
5 4 3 2 1
5 4 3 2 1
PWR Rule
CPU DCLL=1.5m ohm dedign 330uF/9m *0, 22uF *30 +CPU_CORE
1
22U_0805_6.3V6M
PC902
22U_0805_6.3V6M
PC903
22U_0805_6.3V6M
PC904
22U_0805_6.3V6M
PC905
22U_0805_6.3V6M
PC906
22U_0805_6.3V6M
PC907
22U_0805_6.3V6M
PC908
22U_0805_6.3V6M
PC909
2
2
D D
1
22U_0805_6.3V6M
PC920
22U_0805_6.3V6M
PC921
22U_0805_6.3V6M
PC922
22U_0805_6.3V6M
PC923
22U_0805_6.3V6M
PC924
22U_0805_6.3V6M
PC925
22U_0805_6.3V6M
PC926
22U_0805_6.3V6M
PC927
2
2
+CPU_CORE
1 1 1 1 1 1 1 1
22U_0805_6.3V6M
PC934
22U_0805_6.3V6M
PC935
22U_0805_6.3V6M
PC936
22U_0805_6.3V6M
PC937
22U_0805_6.3V6M
PC938
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
@
PC939
PC940
PC941
2 2 2 2 2 2 2 2
22U_0805_6.3V6M
PC949
22U_0805_6.3V6M
PC950
22U_0805_6.3V6M
PC951
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
@ @ @
PC952
PC953
PC954
PC955
PC956
2 2 2 2 2 2 2 2
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE_CAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
5 4 3 2 Date: Monday, December 03, 2012 1 Sheet 48 of 51
5 4 3 2 1
VGA@ PC1001
VGA@ PC1002
VGA@ PC1003
VGA@ PC1004
VGA@ PC1005
VGA@ PC1006
VGA@ PC1007
VGA@ PC1008
560uF*2+330uF*2
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
D D
1
2 10uF*8+2.2uF*16
2
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
VGA@ PC1009
VGA@ PC1010
VGA@ PC1011
VGA@ PC1012
VGA@ PC1013
VGA@ PC1014
VGA@ PC1015
VGA@ PC1016
VGA@ PC1017
VGA@ PC1018
1
1
2
2
560U_2.5V_M
560U_2.5V_M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1 1 1
330U_D2_2.5VY_R9M
VGA@ PC1019
VGA@ PC1020
VGA@ PC1021
VGA@ PC1022
VGA@ PC1023
VGA@ PC1024
VGA@ PC1025
VGA@ PC1026
PC1027
1
1
+ + +
2
2
C 2 2 2@ C
AMD MARS
VDDCI
330uF*1+2.2uF*1
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE CAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 49 of 51
5 4 3 2 1
A B C D E
1107A-------------------
1122A-------------------
A --> B Change List 1. Page22, Add X7603@ for VRAM 2Gb*4 HYN 128M16
1. Page04, Move R25 to JXDP1.60
Update U1 option component for CPU
Add X7604@ for VRAM 2Gb*8 HYN 128M16 2. Page6,8, Change EC_SMI from GPIO77 to GPIO34
1203A------------------- 1121A-------------------
1.Page11, R169 change to @ Delete R445
1. Page06, Add R937 for EC_SCI# Path to GPIO34 3. Page07, Change Y2 to X3G024000DC1H(SJ10000CS00)
2.Page36, Mound R417 (Cancel AMIC@) 2. Page09, RP28.5 connect to GPIO34
3.Page18, R898, R899, R409, D22 change BOM Structure to VGA@ 4. Page08, U17, U43, R310 change to @
1120A------------------- Mount R65
4.Page34, R485, R483 change to 9012@ 1. Page06, Delete chargeable RTC circuit
R479, R478 change to 940@ R310.1 change to +3VS
Change ODD to SATA port1 5. Change all 932@ to 940@
5.Page35, C663, SW4, SW5 change to 9012@ Page32, Modify ODD SATA netname to SATA port 1 .
1129A------------------- R161, D29, R564, U6, R569, C522, C523, C552, D36, Q39, R522,R586, R589, R607,
1.Page32, JODD1.11 Reserve a TestPoint for DFT R610, R624, R693, U41, U44, C516, C518, D28, R146, R158, R159, R160, R496, R499,
2. Page29, +1.2V_LAN_OUT add 680P for EMI R504, R507, R508, R511, R601, U28, U29
1 2.Page29, Pop C779, C783 3. Page37, Modify H21 from 2P5 to 3P0 1
3.Page17, Update U51 BOM Structure for BOM Select 6. Page11, R169 change to XDP@
4. Page38, Add 2 jump for power cousumption measure 7. Page12, add C414 and change PCH_PWR_EN to PCH_PWR_EN#
4.Page04, Add QDJC@ BOM Structure for U1 J36(+3VS),J37(+5VS)
1128A------------------- delete Q33, R561, R563
5. Delete XDP port and related circuit 8. Page16, delete R58, R298, R300, C163, R299, R302
1.Page18, Add D22 to prevent GPU_ACIN leakage Page04, Delete C63,C64,C96,C97,C98,R20,R21,R22,R23,R27~R31
2.Broadcom recommend modify(Add componment Function Field is 9. Page17, Add option component (U51) for SUN_XT
Delete R3,R86,R87,R88,R89,R90,R91,R4,C92,C93 10. Page19, Add R900, R901 with BOM structure @
45.1) Delete R5,R14,R15,R16,R7,R19,R25,C35,JXDP1
Page29, Add C803 0.1uF to U48.20(VDDO_CR), 11. Page24, delete R405, U20, R362, R401, C164
Page07, Delete R66,R67 Change U8 to G5243AT11U(SA000028Y10)
Page29, Add L74(BLM31PG601SN1) between Q6.1 and +3V_LAN 6. ESD DVT Modify:
Add C820 (1uF) to Q6.1 12. Page25, delete R367, D7, F1, D8, D19
Page08, Delete C39 13. Page26, change L47, L48 to BLM18AG121SN1D(SM010030010)
Page30, Add L75(BLM31PG601SN1) between Q9.1 and Page24, Delete D6
+XDPWR_SDPWR_MSPWR 14. Page27, Delete D31, F2, C450
Page28, Delete D7,D18 15. Page28, Delete R781, D23, R782, R785, U49, C803
Add C820 (1uF) to Q9.1 Page30, Delete D38
3.Page18, Change L69 to R_Short 16. Page29, Delete R792
Page33, Delete D16 change T1 to GST5009-E (SP050006B10)
4.Page20, Change L72 to BLM18AG121SN1D (the same to L71) Page35, Delete D25,D30,D34
5.SW confirmed function 17. Page30, delete R414, C166
Page36, Delete D26,R544,C572 R438, Q20 change to @
Page08, unpop R245,d21 (ACPRESENT tp PCH no need) Page37, Delete ESD TP JUMPs:
Page36, unpop R529 (EC_BEEP no need) Change U9 to G5243AT11U(SA000028Y10) with BOM@
J10,J20,J17,J21,J16,J19,J18 18. Page31, delete R595, R587, Q34, R597, R596, R562
6.Default EC_SCI# to GPIO34 J22,J24,J28,J25,J29,J23,J27
Page06, Pop R937 19. Page32, Change U25 to SY6288D10CAC_MSOP8(SA00004KB10)
J26,J30,J31,J33,J32,J34,J35 Change JUSB1 to OCTEK_USB-09EAAB(DC233008O20)
Page09, Unpop R66 Page29, C786 change to EMC@
7.Reserve DGPU_HOLD_RST# direct to PLTRST_VGA# path Delete R472, R469, R460, R462, C635, U46, R459, R463, R464
Page04, Add C96 to DIMM_DRAMRST# 20. Page33, Mount R503
Page08, Add R405 0ohm connect DGPU_HOLD_RST# and PLTRST_VGA# Page33, C487 change to EMC@ and 0.1uf
8.Page35, Chagne R702 to 680ohm (ME confirm) Change R506 to 8.2K
Delete D4 Change R509 to R_Short with BOM @
9.Page35, Delete SW1 (debug) for Layout convenience Page26, C378 change to EMC@
10.Page24,Change L6 to (4.7uH_SH00000GS00) same as Q5WV8 Delete R491, R493, D20
C387 change to EMC@ 21. Page34, add R535 (100K_0402)
2 11.Page29,Change RP22 to R768,R769,R770.R771 for SD 3.0 EMI 1119A-------------------
2
1127A------------------- Mount R632
1. Page06, Add a nochargeable RTC battery. 21. Page35, L51 change to BLM18AG121SN1D(SM010030010)
1.Page24, Change U50.11 connect from L6.2 to L6.1 2. Page15, Add R191 for DDR_VTT_PG_CTRL pull high +5VS option.
2.Page34, Change R502 from R_short to 940@ 0ohm Change JMIC1 to ACES_88266-02001(SP020008Y00)
3. Add page24, Reserve eDP to LVDS translator (RTD2132R) Delete R143, R668, R162, R181, C719, R671
3.Page36, Change R237,R238 to 60 Ohm(Codec vendor recommend) Add bom structure TL@(translate) and EDP@(eDP mode)
4.Page09, Add R67 for EC_SCI# -> GPIO 10 option 23. Page37, delete R424, C169
4. Page25, Add R947 for ENVDD option. Change U12 to G5243AT11U(SA000028Y10)
1126A------------------- Add connect TL_INVT_PW to INVTPWM
1.Page36, Delete D26 (ESD Confirm) 24. Page43, SW1 change BOM Structure to @
Add connect RTD2132R TL_HPD to EDP_HPD 1015A-------------------
2.EMI part Schematics modify(EMI confirm1123) Modify JLVDS1 pin net name fo Co-Lay eDP & LVDS
Page26, Change R368,R369,R370,R371,R372,R373,R374,R375 to 0403 1. Modify BOM Structure/Function Field for EMC@(45.1)
R_short Page06, RP14
Page28, Change R175,R180 to 0603 R_short Page07, RP19, R390
Page36, Change L36,L38,L51,R527,R528,R532,R533 to 0603 R_short Page24, L11
Page32, Delete C408,C398 Page25, R368, R369, R370, R371, R372, R373, R374, R375
Page33, Delete R453,R455,R456,R457 Page27, L42, L45, L46,R175, R180
3.Page38, Change 3/5 VS circut BOM Structer to 35V@ Page28, R774
4.Page32, Modfiy JHDD1 to LTCX004LGA0 (S H-CONN CCM Page29, R897, C814, D39
C127043HR022M27FZR 22P H3.05 HDD) Page32, L24, L25, R458, R461
Modfiy JODD1 to LTCX004HZ00 (S H-CONN SANTA 20190X-X Page35, R527, R528, R532, R533, L36, L38, D1, C62
13P H3.6 ODD ) 2. Modify BOM Structure/Function Field for XEMC@(45.1)
1123A------------------- Page04, C63, C64, C96, C97, C98, C94, C95, C60, C92, C93, C35
1.Delete +3VALW to +3VALW_PCH MOS Circuit: Page07, R104, C152, R402, C453
Page12, Delete C589,C414,R77,Q10,C590,C591 Page08, C39
Page34, Delete U28.16 PCH_PWR_EN# off page Page24, C528, C549, C364, C365, D6
2.Page12, Unpop R210 ,Pop L3 and C22 for +1.05VS_VTT high ripple Page25, D2, L13, L14, L15, L16
3.Unpop and Componment reduce----------------------------- Page28, C792, C786
3
Page16, Delete C824,C828,C831,C836,C839 for unpop reduce. Page29, R26, C26, C806, C807, C808, C809, JP1, JP2, D38 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR-HW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 50 of 51
A B C D E
5 4 3 2 1
2 Module Design Module Design change 3/5V solution 3/5V 11/13 DVT
4 Check no need keep with HW 39 Delete PR112, PR113, PBJ101 11/20 DVT
Add PR518, PC522, PR714, PC714, PR829, PC828,
5 EMI request EMI PR806, PC807, PC749 11/20 DVT
Change PR701 to 2.2
EMI Delete PL102, PC103, PC101, PL202, PC201 and PL703 11/26 DVT
6 EMI request EMI confirm remove
7
C C
10
11
B B
12
13
14
15
16
A 17 A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Monday, December 03, 2012 Sheet 51 of 51
5 4 3 2 1
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