Optimization of Test Wrapper Length for TSV

Based 3D SOCs Using a Heuristic Approach

Tanusree Kaibartta1(&) and Debesh Kumar Das2

1
Department of Computer Science and Engineering,
IIT (ISM) Dhanbad, Jharkhand, India
kaibartta.tanusree@gmail.com
2
Department of Computer Science and Engineering,
Jadavpur University, Kolkata, India

Abstract. Core of an integrated circuit is supplied test stimulus generated by an

external test source and then responses of the core are compared with expected
responses. Test access mechanism (TAM) is a mechanism responsible for
transporting test data to the cores. Core of a three-dimensional System on Chip
(SOC) has various elements related to testing of the core, known as wrapper
input cells, wrapper output cells and set of scan chains. These elements are to be
interconnected to form wrapper chains. To perform this, the elements are con-
nected in an order such that the wrapper chain begins with the wrapper input
cells and then internal scan chains followed by the wrapper output cells. This
paper aims to determine the placement of core elements in several layers of 3D
SOC for a number of wrapper chains and interconnect the core elements using
available number of TSV such that the length of the longest wrapper chain is
minimized.

Keywords: Wrapper
TSV
TAM

1 Introduction

Generation to generation, there are high demands for electronic products to provide
more functionalities and higher performance with less power consumption. SOC design
consisting of a number of embedded cores is the solution to satisfy this market demand.
Since embedded cores in a core-based SOC are not easily accessible via chip input and
output pins, a special test infrastructure must be included in the chip to test them.
According to IEEE 1500 in [1], the basic SOC test infrastructure of an embedded core
is composed of - (1) test access mechanism (TAM) and (2) wrapper. Testing of a core
can be described as follows-first, the test stimuli are sent to the particular core, and the
test response is sent out. Then the test response is compared with the predefined correct
response. Hence, TAM provides the way to transport test stimuli from the test pattern
source to the core and core to the test response sink. Wrappers are also important
components of the test access infrastructure in a core-based SOC. Detail of the wrapper
design is discussed in Sect. 2.

© Springer Nature Singapore Pte Ltd. 2019

S. Rajaram et al. (Eds.): VDAT 2018, CCIS 892, pp. 310–321, 2019.
https://doi.org/10.1007/978-981-13-5950-7_27
 Optimization of Test Wrapper Length for TSV Based 3D SOCs 311

SOC design consisting of a number of embedded cores has become increasingly

complex and interconnects has become the performance and power limiter for inte-
grated circuits (ICs). Due to this, electronic system design technology has shifted from
two dimensional integrated circuit (2D IC) to three dimensional integrated circuit (3D
IC). Technological shift from 2D IC to 3D IC helps to resolve the interconnect related
problem. Among various 3D integration technologies such as wire bonded, microbump
based, contactless and through-silicon-via (TSV) interconnects, TSV based 3D inte-
gration method has the capability to provide the shorter interconnect length compared
to 2D IC. Reduction in interconnect length reduces the interconnect energy and latency
and thus increases the performance. According to report in [2], design transition of 2D
to 3D architecture of arithmetic logic of barrel shifter helps to achieve 9% reduction in
latency and 8% reduction in energy consumption. In spite of the above benefits, 3D
SOC provides additional challenges on how to distribute the wrapper elements of a
core in multi-layers such that wrapper length can be reduced. Number of works in
wrapper optimization and test infrastructure design of 2D IC have been proposed in
literatures [3–5]. Limited works exists in the domain of 3D SOC. Optimization of test
infrastructure design under given number of TSV of 3D SOC has been proposed in [6,
7]. ILP and Genetic algorithm based approaches are used in [6] and [7] respectively.
Wrapper optimization of 3D SOC is presented in [8] and [9]. In [8], a heuristic
method is used to reduce the wrapper chain length under the constrain of TSV. Same
problem is resolved using genetic algorithm based approach in [9]. In this research
work, we are dealing with 3D SOC, so wrapper elements i.e. input, output and scan
chains has to be distributed in several layers. Main focus of our work is to create
balanced wrapper chain to minimize the scan test time by distributing wrapper elements
i.e. input, output and scan chains of the cores in different layers of 3D SOC under the
constraint of given number of TSVs. The paper is organized as follows. Section 2 gives
insight into wrapper architecture. Motivational example is discussed in Sect. 3. The
wrapper optimization problem is formulated in Sect. 4. Proposed algorithm is dis-
cussed in Sect. 5. Experimental results on different benchmark SOC is discussed in
Sect. 6. Finally, the paper concludes with observations in Sect. 7.

2 Wrapper Architecture

The striking feature of the 1500 standard is the provision of a wrapper on each core.
A test wrapper is basically a layer of design-for-test (DFT) logic that connects a TAM
to a core for the purpose of testing. According IEEE 1500 standard each wrapper
consists of input, output and scan chain. Further, scan chain itself is the combination of
scan-in and scan-out. In a wrapper chain at first, all the inputs are present either in one
layer or in multiple layers. After input, scan-out follows scan-in. Scan chain is also
distributed either in one layer or multiple layers depending upon the architecture. Same
arrangement is followed in case of output. The element wise processing sequence of
wrapper chain is first inputs then scan-in, which is followed by scan-out and finally
output is achieved. The number of clock cycles depends on the length of the wrapper
chain. Therefore to minimize the time, we must optimize the length of the longest
wrapper chain.
312 T. Kaibartta and D. K. Das

The number of wrapper chain depends on the TAM width. The values of each cell
indicate the layer number.

Table 1. Initial stage of wrapper design of the given example as mentioned in [9]
W1 W2 W3 W4
I Sc O I Sc O I Sc O I Sc O
2 2 3 2

Table 2. Final wrapper design of the given example as mentioned in [9]

W1 W2 W3 W4
I Sc O I Sc O I Sc O I Sc O
1 2 3 2 3 2 2 3 2 2 2 1
3 3 1 3 3 1 3 2
1 1 1 1

3 Motivational Example

Consider, a core with 10 functional inputs, 10 functional outputs and 5 internal scan
chains each of length 8, number of maximum available TSVmax 14, TAM width 4 and
total number of layers 3. Objective is to distribute the wrapper elements over three
layers of 3D SOC for a number of wrapper chains and interconnect the core elements
using TSVmax such that the length of the longest wrapper chain is minimized. As the
number of wrapper chains is equal to TAM width, 25 wrapper elements (i.e.
10 + 10 + 5) are to be distributed among 4 wrapper chains. A motivational example
depicting solution for wrapper optimization problem is presented in Table 1 which is
taken from [9]. W1, W2, W3 and W4 indicate four wrapper chains. For each wrapper
chain I, SC and O indicate input, output and scan chain respectively. The value of each
cell in Table 1 indicates the layer number.
According to [9], initially the wrapper elements are chosen randomly. That means
chosen element can be of any type i.e. input, output or scan type. If the element type is
scan type, no requirement check is needed and it can be placed at any wrapper,
otherwise requirement check has to be performed because input and output affects the
number of TSVs. According to [9], the input and output requirement over 4 wrapper
chains W1, W2, W3 and W4 for the given problem is 3, 3, 2 and 2 and 2, 2, 3 and 3
respectively.
Based on this approach, suppose an element chosen randomly is of scan chain type
and is placed randomly at layer 2 of wrapper chain W1 as shown in Table 1. TSV
requirement in this case is 2. Suppose, the next element is of input type, so it will be
placed in the next wrapper i.e. W2 and in the same way, the wrapper elements are
assigned to the other two wrapper chains W3 and W4. At this point, each wrapper chain
contains exactly one wrapper element as shown in Table 1, and the total number of
 Optimization of Test Wrapper Length for TSV Based 3D SOCs 313

TSVs required up to this stage is 10 (i.e. 2 + 2 + 4 + 2). This is the completion of first
cycle of assigning wrapper elements to every wrapper chains and in the next clock
cycle, the next element will be assigned to the wrapper chain W1. In this way, we obtain
the final stage as shown in Table 2 in [9].

4 Problem to be Solved

Wrapper length optimization problem for TSV based 3D SOC core can be stated as
follows - Given a 3D SOC core consisting of varying functional parameters such as
number of functional inputs, number of functional outputs, set of scan chains, the length
of each scan chains, TAM width and maximum number of available TSVs (TSVmax), we
have to distribute the core elements over several layers of 3D SOC and interconnect the
core elements using TSVmax such that length of the longest wrapper chain is minimized.
This approach can be termed as wrapper design with available number of TSVs.
From the above discussion, it is clear that for a given TSVs (i.e. TSVmax) and given
TAM width T, the goal of the proposed heuristic algorithm is to create some balanced
wrapper chains whose maximum length is minimum. As the chip pins are at the lowest
layer, so we assume the wrapper chain begins and ends at lowest layer and layer
number starts from bottom to top and top to bottom (i.e. bottom layer number is 1, next
layer number is 2 and so on). We also assume that TSVs internal to the scan chains are
not considered for TSV calculation.

5 Our Algorithm
5.1 Data Structure
For a given core, wrapper elements are described as E = E1, E2, …, En, TAM width T
and maximum number of available TSVs (TSVmax). The proposed algorithm uses
element and wrapper data structures.
The data structure of element is presented in Table 1. It contains the information
about each core wrapper element Ei of the list E. The information includes the type of
element (i.e. Input wrapper (I/P), Output wrapper (O/P) and Scan chain), layer number
indicates in which it is placed and the length of the wrapper element. The wrapper data
structure maintains three different lists using five variables corresponding to each type
of wrapper element Ei. Information about the number of TSVs required at any instant
of time, specifically before insertion of a wrapper element into the wrapper chain, is
stored in the no_of_tsv.
The variables, length and no_of_elements are used to hold the length of the wrapper
chain and the number of different types of wrapper elements contained by the wrapper
chain respectively. Before starting of the algorithm, the length of wrapper chains are
initialized with 0. The variable no_of_input and no_of_output indicate the total number
of input and total number of output of the wrapper chain, respectively (Tables 3 and 4).
314 T. Kaibartta and D. K. Das

Table 3. Data structure of element

Type Type of the element (I/P, Scan chain, O/P)
Layer Layer no of the element
Length Length of the element

Table 4. Wrapper data structure

no_of_tsv Total no of TSVs required to connect all the elements for a particular
wrapper chain
no_of_elemens Total no of elements (input + scan chain + output) for a particular wrapper
chain
no_of_input Total no of input for a particular wrapper chain
no_of_output Total no of output for a particular wrapper chain
Length Length of a wrapper chain

If I/Ps are connected with scan-in in the same layer then the TSV requirement is 0.
Hence the value of no_of_tsv is zero but if they are in different layers, the no-of-tsv
holds a non-zero value. If scan-in is connected with scan-out either in same layer or
different layers then the value of no_of_tsv is 0 as the internal TSVs are not counted. If
scan-out is connected with other scan-in or with O/P in the same layer then the value of
no_of_tsv is zero but if they are in different layers then no_of_tsv is considered. Hence,
the no_of_tsv is some non-zero value. If O/P is connected with different O/P in the
same layer, then TSV requirement is zero (i.e. no_of_tsv is 0) but if they are in different
layers then TSV is considered (i.e. the value of tsv is some non-zero value).

5.2 Exact Algorithm

The proposed algorithm tries to create a set of balanced wrapper chain W = W1, W2,
W3, W4 ……. WT where T equals to maximum available TAM width and Wi is the i th
wrapper chain. In wrapper length optimization problem, scan chain is the major con-
tributor of increasing wrapper length. Therefore to reduce the wrapper length, the scan
chain has to be placed properly such that the wrapper length gets minimized and TSV
constraint (TSVmax) is satisfied.
Our algorithm is explained using the same problem discussed in Sect. 3, i.e. a core
with 10 functional inputs, 10 functional outputs and 5 internal scan chains each of
length 8, number of maximum available TSVmax 14, TAM width 4 and total number of
layers 3. Objective is to distribute the wrapper elements over three layers of 3D SOC
for a number of wrapper chains and interconnect the core elements using TSVmax such
that the length of the longest wrapper chain is minimized.
Based on this, we implemented our algorithm and obtained the initial stage shown
in Table 5. To get balanced wrapper chains, our first target is to place the scan chains
among four wrapper chains. Hence, the scan chain requirements for four wrappers W1,
W2, W3 and W4 are 2, 2, 3 and 2 respectively. These scan chains has to be placed in
three layers in a way such that it satisfies TSV requirement (TSVmax). At first iteration,
 Optimization of Test Wrapper Length for TSV Based 3D SOCs 315

four scan chains are placed in four wrapper as shown in Table 5. According to Table 6
and Fig. 1, W1 which spans across two layers, contains one input element, two scan
chain elements and one output element and they are placed in layers 1, 2 and 1
respectively. Hence, the TSV requirement for W1 is 2 and wrapper chain length is 18.
Similarly, W2 which spans across three layers, contains three input element, two scan
chain elements and three output elements. Two input elements are placed at layer 1 and
one input element is placed at layer 2, scan chain is placed at layer 2, two output
elements are placed at layer 1 and one output element is placed at layer 2. Hence, the
wrapper length is 14 and TSV requirement is 2.
Similarly W3 which spans across three layers, contains three input elements, one
scan chain element and three output elements. Two input elements are placed at layer 2
and one input element is placed at layer 3, scan chain element is placed at layer 3, three
output elements are placed at layer 1. Hence, wrapper length is 14 and TSV require-
ment is 4.
Finally, W4 which spans across three layers contains three input elements, one scan
chain element and three output elements. Two input elements are placed at layer 2, one
input element is placed at layer 1, one scan chain element is placed at layer 2, two
output elements are placed at layer 2 and one output element is placed at layer 1.
Hence, the wrapper length is 14 and TSV requirement is 2. Hence, the maximum
wrapper length is 18 and TSV requirement is 10 (i.e. 2 + 2 + 4 + 2).
Figure 1 shows the conceptual design of the given problem where 25 core elements
are distributed on wrapper chains W1, W2, W3 and W4 over three layers. I, O written
square boxes indicate input and output respectively and filled square box indicates scan
chain.

Table 5. Initial stage of our solution for the problem

W1 W2 W3 W4
I Sc O I Sc O I Sc O I Sc O
2 2 3 2

6 Experimental Result

The proposed heuristics based algorithm is coded in C++ language and executed on a
Intel Core 2 Duo processor having 1 GB RAM. Cores from ITC02 SOC test bench-
marks are used for experiment. For experimental results, we have used cores 7, 5 and 4

Table 6. Final stage of our solution for the problem

W1 W2 W3 W4
I Sc O I Sc O I Sc O I Sc O
1 2 1 2 2 2 3 3 1 1 2 1
2 1 1 2 1 2 2
1 1 2 1 2 2
316 T. Kaibartta and D. K. Das

Fig. 1. Conceptual design of wrapper chain for the given example

of SOCs d281, h953 and p93791 respectively. We have restricted the number of layers
to 3 for each simulation. The experimental result is presented in Tables 7, 8, and 9.
Columns 1, 2, 3, 4, 5 and 6 indicate TAM width, maximum TSV, longest wrapper
length obtained in [9], CPU time mentioned in [9], longest wrapper length in proposed
method and CPU time in proposed method respectively. In these tables TAM width,
maximum TSV, longest wrapper length and CPU time are abbreviated as TAM,
TSVmax, LWL and Time respectively.
According to Table 7, we have achieved good results in 4 instances among 23
instances in all respect that is longest wrapper length wise and CPU time wise, though in
remaining 19 instances our wrapper length is same as the wrapper length mentioned in [9].
Experimental result of core 5 of SOC Benchmark h953 is shown in Table 8.
Compared to [9], our algorithm shows better result in 18 instances among 28 instances
in all respect that is longest wrapper length wise and CPU time wise.
According Table 9, for core 4 of SOC Benchmark p93791, our algorithm performs
better in 27 cases.
Optimization of Test Wrapper Length for TSV Based 3D SOCs 317
318 T. Kaibartta and D. K. Das

Table 7. Result of problem I for benchmark d281 of core 7

TAM TSVmax LWL [9] Time [9] LWL Time
2 10 1129 0.13 1064 0.002
11 1223 0.08 1064 0.004
10 1223 0.11 1064 0.002
11 1095 0.1 1064 0.004
12 710 0.1 710 0.001
3 14 710 0.1 710 0.001
16 710 0.1 710 0.002
15 784 0.13 710 0.002
12 532 0.08 532 0.003
14 532 0.06 532 0.015
4 16 532 0.1 532 0.003
18 532 0.1 532 0.003
22 532 0.11 532 0.015
12 426 0.08 426 0.003
14 426 0.08 426 0.003
(continued)
 Optimization of Test Wrapper Length for TSV Based 3D SOCs 319

Table 7. (continued)
TAM TSVmax LWL [9] Time [9] LWL Time
5 16 426 0.1 426 0.001
18 426 0.11 426 0.003
22 426 0.11 426 0.003
12 355 0.11 355 0.002
14 355 0.1 355 0.015
6 16 355 0.1 355 0.003
18 355 0.08 355 0.002
22 355 0.11 355 0.003

Table 8. Result of problem I for benchmark h953 of core 5

TAM TSVmax LWL [9] Time [9] LWL Time
2 8 367 0.12 258 0.007
10 375 0.1 258 0.003
11 377 0.12 258 0.015
11 377 0.1 258 0.015
8 244 0.1 243 0.015
3 10 245 0.1 243 0.013
12 252 0.12 245 0.013
14 251 0.12 246 0.005
8 129 0.08 129 0.015
4 10 246 0.1 129 0.015
12 368 0.1 129 0.007
16 250 0.133 129 0.008
8 124 0.15 123 0.008
5 10 123 0.08 127 0.009
12 246 0.1 123 0.009
16 248 0.1 124 0.009
8 123 0.1 123 0.027
6 10 126 0.1 126 0.013
12 123 0.1 123 0.011
16 243 0.06 126 0.011
8 124 0.13 123 0.013
7 10 123 0.1 125 0.013
12 124 0.08 123 0.013
16 244 0.08 125 0.024
8 123 0.15 123 0.015
8 10 123 0.1 124 0.036
12 123 0.08 123 0.012
16 123 0.1 124 0.016
320 T. Kaibartta and D. K. Das

Table 9. Result of problem I for benchmark p93791 core 4

TAM TSVmax LWL [9] Time [9] LWL Time
2 11 85 0.1 77 0.01
8 88 0.11 77 0.01
12 91 0.13 77 0.01
11 80 0.13 77 0.01
11 96 0.11 77 0.01
12 53 0.11 51 0.015
13 53 0.1 51 0.015
3 14 52 0.08 51 0.013
15 73 0.15 51 0.015
13 64 0.08 51 0.015
12 40 0.1 39 0.016
13 39 0.1 39 0.014
4 14 40 0.08 39 0.015
18 46 0.1 39 0.016
20 54 0.11 39 0.014
12 32 0.08 31 0.016
13 31 0.08 37 0.015
5 14 32 0.1 31 0.015
18 36 0.11 31 0.015
20 31 0.08 31 0.015
12 27 0.08 26 0.016
13 27 0.13 32 0.015
6 14 28 0.15 26 0.015
18 27 0.11 26 0.015
20 31 0.11 26 0.015
12 24 0.08 22 0.016
13 24 0.1 25 0.015
7 14 24 0.08 22 0.015
18 23 0.1 22 0.015
20 24 0.13 22 0.015
12 21 0.06 20 0.016
13 21 0.11 25 0.015
8 14 21 0.1 20 0.015
18 23 0.08 20 0.015
20 21 0.06 20 0.015
 Optimization of Test Wrapper Length for TSV Based 3D SOCs 321

7 Conclusion

We have presented an optimization technique for minimizing the wrapper length for 3D
core-based SOCs under constraints on the number of TSVs and the TAM width. We
have carried out a series of simulations for three ITC02 SOC test benchmarks by
considering three layer in 3D IC. Simulation results show that the proposed method
leads to lower wrapper length compared to the earlier work in [9]. We have also
demonstrated a conceptual design to show the distribution of wrapper elements i.e.
input, output and scan chain. This work is expected to pave the way for core-based
testing of emerging 3D SOCs.

References
1. IEEE Std.1500: IEEE Standard Testability Method for Embedded Core based Integrated
Circuits. IEEE, New York (2005)
2. Puttuswamy, K., Loh, G.H.: The impact of 3-dimensional integration on the design of
arithmetic units. In: IEEE International Symposium on Circuits and Systems, pp. 4951–4954.
IEEE, Greece (2006)
3. Iyengar, V., Chakrabarty, K., Marinissen, E.J.: Test wrapper and test access mechanism co-
optimization for system-on-chip. J. Electron. Test. Theory Appl. 18, 213–230 (2002)
4. Goel, S.K., Marinissen, E.J.: SOC test architecture design for efficient utilization of test
bandwidth. ACM Trans. Des. Autom. Electron. Syst. 8(4), 399–429 (2003)
5. Giri, C., Sarkar, S., Chattopadhyaya, S.: A genetic algorithm based heuristic technique for
power constrained test scheduling in core-based SOCs. In: IEEE Proceedings of IFIP
International Conference on Very Large Scale Integration, USA, pp. 320–323 (2007)
6. Wu, X., Chen, Y., Chakrabarty, K., Xie, Y.: Test-access mechanism optimization for core-
based three-dimensional SOCs. Microelectron. J. 41, 601–615 (2010)
7. Kaibartta, T., Das, D.K.: Testing of 3D IC with minimum power using genetic algorithm. In:
10th International Design and Test Symposium (IDT), pp. 112–117. IEEE, Jordon (2015)
8. Noia, B., Chakrabarty, K., Xie, Y.: Test-wrapper optimization for embedded cores in TSV-
based three-dimensional SOCs. In: IEEE International Conference on Computer Design,
pp. 70–77 (2009)
9. Roy, S.K., Giri, C., Rahaman, H.: Optimization of test wrapper for TSV based 3D SOCs.
J. Elctron. Test. 32, 511–529 (2016)