Scanned with CamScanner2.3. DATA BUS The data ee roup of eight lines used for data flow. These fi ie, data can £10 bath the directions, between the CPU « ‘The microprocessor uses the data bus to perform the data. Microprocessor 8085 has $data lines AD “AD, As address at different time, hence same 8 pins AD,-ADg are used for transferrin address as well as 8 bit data, bi i time multiplexed or time shared address data bus. As Pins, so it can transfer maximum 8 bit of data in parallel. On thest transferred frost OO H to FELH. The largest number that can a 1111 1111. The data bus influenc i efermines the word length and register size of a micropro lines so 8085 is a 8 bit microproc 4. INTERNAL DATA BUS The 8 bits data bus i i registers. General purpose Scanned with CamScannerScanned with CamScanner8 LSB's of result in ALU are al operation in ALU ani back into accumulator 2.5.3. Temporary Registers. There are three 8 bit registers register can store maximum S.bit of data. These registers cana the programmer. These registers can be used only. by, the sig essor will use these re For storing are called. temporary. register 25.4. Scanned with CamScanner= ae — 10 Instruction decoder (ID). The 8 bit number of instruction register (IR) is applied 1 ‘As ID has 8 inputs, so number of ID outputs are 2° = 256 (Y, 10 Y>4.). Each ID output is connected to one controlling circuit. Hence, there are 256 controlling circuits. Each circuit ill generate control signal required for performing the particular operation. So Microprocessor 8085 can perform 256 different oper ions, which are controlled by these 256 controlling circuits. When 8 bit number of Instruction Register (IR) is given as i to ID thus only one ID output becomes active (logic 1) and rest of the 255 ID inactive (logic 0). So the controlling circuits connected to the active ID outgs control signal and a particular operation is executed. 2.5.7. 16 Bit Registers : «Fut Program counter (PC). The program counter instruction to be executed and always contains the 16 bitad PC is updated by thelgl after the processor has fetched the comp depends on the n Scanned with CamScannerScanned with CamScannerSOD (Serial data out) (Pin 4). This is output pin of microprocessor which is used for sefial output. The data can be sent out serially by using SIM* instruction. SID (Serial data in) (Pin §). This is Input pin of microprocessor. This is used for input data serially. By using RIM** instruction se al data in is possible TRAP (Pin 6). This is a non-maskable interrupt having highest priority. TRAP is also known as RST 4.5. The vector location of TRAP is 0024 H. RST 5.5 (Pin 7). RST 6.5 (Pin 8) RST 7.5 (Pin 9), 5.5, RS RST 7.5 are input pins of microprocessor and known as restart s recognised all next instructions will be is executed from a given below RST 5 8 x 5.5 = 002C H . 8x65 RST. 75 Loc 003C H 8x75 ENTR (Interrupt-request) (Pin 10). It is an interrupt reques interrupt. Among interrupt it has the lowest priority, Des not increment its content, It suspends the rocessor executes Interrupt service routings TNPA (Interrupt acknowledge bar) (Pin 11). It is Outp respofise e interrupt st an active low signal is sent AD,-AD, (Pin 12-19). Time multiplexed addr address as well as dats bus. These are used for the address or VO address during the first clock cyg used for daia Airing second and third clock cych significant & bits of the address bus must be VSS (Pin 20). Ground reference. AAs Pin 21-28). Address pin Scanned with CamScannerScanned with CamScanner_— icroprocessor. Wh RESETIN (Pin 36). It is input pin of mi he contents of program counter becomes or is reset. T applied to this pin the microprocess« 0000 H. It also disable Interrupts. nicroprocessor. This signal en active low signal is CLK (Clock output) (Pin 47). This is Output pin of 1 be used as the system clock for other d HOLD (Pin 39). A high on this pin suspends normal CP ‘a DMA (Direct memory access) con After receiving the HOLD request the microprocessor — puses as soon as the current machine cycle is completed. The as soon as the HOLD signal is removed. levices. >U operations. It indicates troller is requesting the can that another device such as use of address and data bus. felinguishes the use of the processor requires the buses HLDA (Hold acknowledge) (Pin 38). It is @ output signal acknowledgement. It indicates that HOLD request has been received. for Hi VCC (Pin 40). It is +5 V power supply. 27. DEMULTIPLEXING THE BUS AD,-AD, As we know that microprocessor 8085 is having ADg-ADj | dress as well as data. These are used for the lower 8 the first clock cycle address is transferred on) rin ALE ignal is conneet In the first clock cycle output ch A During the s is disabled. It meang D,-D, Scanned with CamScannerScanned with CamScanner-10. When both Generate MEMRD _MEMRD (Memory Read) and MEMWR (Memory Write) control signals. When the TO/M signal goes hi of IORD (VO Read) input signals go low, the outputs of the gates go low and igh, it indicates the peripheral /O. Fig. 2.10 shows the generation and IOWR (VO Write) control sginals. Fig. 2.10. 2.10. CLOCK GENERATION METHODS IN 8085 The 8085 clock frequency can be generated by a external clock circuit. The frequency at X,X, is divi in order to obtain 3.03 MHz, a clock source of 64 For crystals with less than 4 MHz, a capacitor of ure the starting up of the Scanned with CamScannerScanned with CamScanner(id) For complex mathematic (@) Applications where high and software supports al computation cost is justified. The high cost is involved in peripherals LANGUAGES OF INSTRUCTIONS OF MICROPROCESSOR Microprocessor 8085 can perform 256 different operations. In order to execute any operation, we have to give the corresponding instruction to Microprocessor, The Instructions of microprocessor can be written in languages as given below (2) Machine language instruction, When cight bit number is applied tor Instruction Gecoder input, then only one circuit generates controlling signals, by which microprocessor Performs a particular operation, The 8 bit binary number applied to the input of Instruction decoder is called as Instruction of microprocessor in machine language or machine language instruction 3.1, (©) Hexcode language Keyboard is used struct n. For feeding the instruction, Hexadecimal number So programmer has to feed the instructions in the form of 2-digit Hexadecimal number operating code (opcode). The instruction of microprocessor in the form of two-digit Hexcode is called as Hexcode language instruction. The pie. digit Hexcode is translated in to 8 binary bits (machine language), (©) Assembly language or mnemonics. The above two languages are diffiealt for the programmer. Hi ce for programmer, the instructions of microprocessor are made im the form of English abbreviations (short form) and the instruction is called Assembly: language instruction or mnemonics. Machine language, Mnemonics and Hexcode of some instructions are shown ig = Table 3.1 Table 3.1. Mnemonics Hexcode (Assembly Language) | Language (opcode) _ MVIA 3EH WH 21H STA 32H ADDRESSING MODES OF 8085 To perform any operation using microprocessor, we have t0 gi instruction to microprocessor. For executing any instruction, ETistruction, we have to give address of of source of data is given in a instructi ply addressing mode. result, For storing these instruction we have Scanned with CamScannerIf source or destinations is fixed. There are five typ ~ * of addressing modes of A Immediate Addressing Mode (IAM). If 8/16 bit In these instruction: MVIA. 35 H, (if) L) ne mnemonic which rep Scanned with CamScannerUse| In the a . © above tw —— directly, two instructions the 8 bit data is transferred from one register to other ieee ter Indirect Addressing Mode. If 8/16 bit data required for executing the 'S present in memory location, the 16 bit address of this memory location is 1 Present in register pair and the name of register pair is given alongwith the instruction, then it is Called as “Register indirect addressing mode’ instruction e.g., LDAX B, STAX B. In LDAX B accumulator is loaded with 8 bit data from the memory location whose address is stored in BC pair, so it has indirect addressing mode 5. Implicit Addressing Mode. If the address of source of data as well as address of ation of result is fixed, then there is no need to give any operand alongwith the struction. such instructions are called as ‘Implicit addressing mode’ instructions, eg, yi) CMA (Compliment accumulator) A | 11000101 —-| 00111010 | A ii) STC (Set carry flag) T . TYPES OF 8085 INSTRUCTIONS The programmers has to remember the instructions of microproces nemonics. To execute any instruction, the programmer has to transl into equivalent two digit Hexcode (8 bit code). Depending upon required to express each mnemonic completely in the form of of microprocessor are divided into three types. Each instructio perform a specified task on the given data. Each instru code (opcode) and operand. The first part of the i ned by the computer and is called the opera the instruction is the data to be operated on a called the operand given in the instruction a, internal registers of micropro cation. When the operand is a register, A register to the C register. MOV, and which means that the 0} 1, One/Single Byte Inst number is not given as opt Scanned with CamScannerwhose binary equivalent is (01111000), First two bits 01 represents the Move operatio Tegisters ‘A’ and last three bits are the code of @ ADDC (ii) LDAX B 2. Two/Double Byte Instruction (DBD. If 8 bit instruction then to express such instruction completel such instructions are called double byte instr (a) The first b 1 (©) The: Scanned CamScannerTable 3,2 poed the Wau as vino -2 shows the symbols and abbreviations used = to Table 3.2, “plain the instruction, Register Register with Data X_ Memory 4 | Memory with Address 2000 H 4 Register Pair 1 pashan X showing contents of Memory CF | Location 2000 H Tes 33 = Ee r | Register Pair giving the Address | R | 8 Bit Register | of Memory having Data X | | Exchange | Higher 8 Bit Register, —_ Register Pair —~— | 16 Bit Bus | Lower 8 bit Regsister Pair g 8 Bit Bus 3.4.0. Data Transfer Instructions : data data Source Destination The instructions which are used to transfer 8/16 bit are called as data transfer instructions. The previous previous data of destination will be lost. Ai) MOV Rad, Rs (Move data of Source register Rs into (Register direct addressing (Single byte instruction) Different combinatiot Scanned with CamScannerScanned with CamScanner(Immediate addre (Triple byte instr Example 3.8. Fransfer 125 H ino register palr HL Solutio, LXIH, 1D25 ip | ee The same ¢ ration can be performed by using the set of two instructions MVIH, 1D H MVIL, 25 H But it is better to use single instruction LXI, because in first case the f LXIH, 1D25 H is Triple byte instruction, so three memory locations are case MVI is double byte instruction so total four bytes of memory are used same operation Example 3.6. Transfer FFOO H in register pair DE. Solution, LXID, FFOO H FFOO (Register indirect addressing mode) (Sing Note, In any instruction if ‘M’ is pres will be always given by HL pair Example 3.7, Store 8 bit data of Solution. As we have to trans We can use instruction MOV M, Step ‘1' Scanned with CamScannerStep Move contents of Reg ‘C" MOV M, C So the program becomes Ux, 008 MOV M. C: eee Scanned with CamScannerOT CTT TEI addressing mode) struction) (Register indi (Single byte In this instruction, address of memory location is given by HL pair and data of memory is transferred to the destination register Rd Example 3.10. Transfer 8 bit number of memory location 2500 H into register B Solution, ‘ LXIH, 2500 H. MOV B, M (vi) MVI M, data (8 bit) (Move immediate data into memory) Address HL data ———+ Immediate addressing mode) Oo Example 3.11. Transfer 45 H into memory location 6583 H. le byte instruction) Solution. LXIH, 6 MVIM. i6 emer 8 Example 3.12. Transfer FF H into memory location 4500 H. Solution. LXIH, 4500 H: MVIM, FF H FFH Scanned with CamScannerLXIH, 21004 MOV A.M Scanned with CamScannermory location ABCD H. 16. Store 8 bit data of register ‘D’ into me Solution. ABCD Ist method ; LXI H, ABCD H MoV M,D Hind method : MOVA,D LXIB, ABCD H STAXB ix) LDA address (16 bit) (Lo: mulator from Address data) D ode) (Triple byte instruction) Data Data Memory e Example 3.17. Transfer 8 bit data of memory location C000 H. Solution. LDAC000H (2) STA Address (16-bit) (Store accumulator at given address) (Direct addressing mode) (Triple byte A 3.18, Store 8 b Scanned with CamScannerIrarmirmen SAT OF Micsomenr veer RORS 2nd method : LXTH, C000 0 MOV M.A W GI ‘ Example 319, Store & bit of Register Scanned with CamScannerHLD address (16 bit) ore HL pair direct at given memory address) oS ee A h————+|_MSB | Address+1 Memory rect addressing je byte instruction) Example 3.21. Store 16 bit number of Register pair H L in the memory location Solution. (Implicit addressing mode) (Single byte instructions) Example 3.22. Store 16 bit Scanned with CamScannerOM eee aii Scanned with CamScannerGas) @ 8 bit addition without carry (iH) 16 bit addition without carry (ii) 8 bit BCD addition (i) 8 bit subtraction with/without borrow (v) Increment of 8/16 bit data (vi) Decrement of 8/16 bit data (vii) Comparison of two 8 bit nun Microprocessor will execute arithmetic instructions 1" ALU and copied into status flags (CF, AC, Z, P, S) s Remember. tn all arithmetic instructions the first data is taken from accumulator and result is ck to accumulator ADD R (ADD register R Data) nh _sbits bit —————> +¥ 4J-oG I CF A A R First data) (Name of Register R) ddressing mode) tions) affected after the execution of ADD R For examp! Suppose the contents of register C before giving the instr contents of register A = 75 H, then after execution of instruction 01110101 10010011 ar 00001 Example 3.23. Write a prog Register H and B, store 8 bit rest Scanned with CamScannerSev OF Micxoreocesson 8085 MOV AH ADD B MOV L.A Scanned with CamScannerSolution. We have to perform be Weasels A Program : MVIA. 55H ADI 7 (su) apts C+ oh MOV C.A Comments (iv) ADC R (Add with carry register R data) (Register direct addressing mode) (Si le byte instructions) (All flags are affected) [oantt Example 3.27. Write a program to add two 16 bit numbers present in register ind DE. Store 16 bit result in register pair HL Solution. We have to add data X1 and XO in register pair BC with ur DE and store result Z1, ZO in HL pair as shown below : Program : MOV A, C h ADD E MOV L, A MOV A,B Scanned with CamScannerM THE (Register indirect addressing mode) (Single byte instruction) (All flags are affected) Example 3.28, Two 16 bit numbers ai from 7000 H onwards, add. shesas vo} location after Scanned with CamScannerExample Store the result in registers B, ¢ Solution, (AB © DD) A Tet t6 bie mamber c 5 3 t Program Comments And 16 bit muniber : sult MVIA.CDH ; con ——a[t ADI 43H CD ]+437 —f MOVD, A MVIA, ABH ACI 65 H MOVC,A MVIA, 00H ADCA MOV B, A (vii) DAD Rp (Double a (Register direct addres (Single byte inst (Only carry flag i Scanned with CamScannerSolution. RESULT [| Scanned with CamScanner= r instruction (2) To convert this binary result in accumulator into BCD result, nee rae DAA. Logic used by microprocessor for DAA is given in steps 3 B's of accumulator. (3) If 4 LSB’s are greater than 9, then 6 is added to 4 LSB’s of accumulator. 1, then 6 is added to 4 MSB‘s of accumulator, (4) If 4 MSB’s are greater than 9 or CF Write a program to perform addition of two decimal numbers using Example 3 BCD numbers. Solution, Let us suppose two decimal numbers are (38), and (56)19 mvta.3eH ; [oon 7000—] A BCD of (38), ADI 36! ‘voit 1000] or 0110 000 1110_] Binary A 000 1110 | 110 1 00] (BCD) = [9 A () SUB R (Subtract Register ‘R’ Data) (Register direct addressing mode) (Single byte instruction) (All flags are affected) x Y —e A B When microprocessor perform the subtraction X = (@® X>Y, then result Z will be either positive or binary number and CF = 0 (@) X 00 H, then CF = 0, Z = 0. (xviii) INR R (Increment Register R Data) (Register direct addressing mode) (Single byte instruction) (Except CF, All other flags are affected [x] Example 3.37. What will be INR B? (i) If Register B contai - (0) Mf Register B ca Scanned with CamScannerIn (ii) case carry flag is not aff (xix) INR M (Increment Memory Data) Hi (Register indirect addressing mode) (Single byte instru (Except carry flag Scanned CamScanner(330) For example @DeRE (Register indirect addressing mode) (Single byte instruction) (Except carry flag, all flags are affected). Example 3.40. Decrement memory location Solution. (xxiii) DCX mg ( (Register direct Scanned with CamScannerScanned with CamScanner| {@ ANA R (AND Accumulator with Register R Data) (Register direct addressing mode) } (Single byte instruction) ays, 1 always and Z, S, P will indicate status of result) AND = _ (a i A R A Example 3.41. What will be the contents of accumulator after execution of instruction ANA A ? Solution. The contents of accumulator will remain same since as per Boolean theorem. AA=A (i) ANA M (AND Accumulator with Memory Data) , M address I loeb }— i "ae 1 indirect addressing mode) instruction) ), AC = 1 and Z, S, P indicate status of result), ii) ANI Data 8 bit (AND Accumulator with Immediate d f AND | « &a—— mmediate addressing mode) D instruction) CF = 0, AC = | and Z, S, P indicate status of Example 3.42. Re 14 LSB’s of accumulate Solution. As we know 1.A = Ag OA = Now we have to mal LSB’s o 1 Ap A, bits with ‘0’ and restig Scanned with CamScannerPerform ANDing of the bit whose status other bits with “0 Scanned CamScanner=z, = ENEESSSSSRSN For example (1) XRAB : x) XRI data (8 bit CF status of resul Example 3.44 Using the above theorems, Inver We have to invert A., A, Scanned with CamScannerINsrtocHION ‘SET OF Mickomeocesson 8085 Gh OMA (Complement Accumulator) (Implicit addressing mode) (Single byte instruction) (No flags are affe For example Scanned with CamScannereet db DD DD, Dy D, Dy : ‘Accumulator ‘Rotate Right Accumulator through addressing mode) oe byte instruction) ‘ (Only CF is affected) DD DD Dy Dy Dy Dy Accumulator Scanned with CamScanner4. Stack Related Instructions. Stack me (RAM) which is used to save useful data of register p upward direction. As the data is arranged in the form of ‘out (LIFO) or First in last out (FILO), When the data is transferred between microprd selecting one memory location, microprocessor will pointer to address pins. Stack pointer is a stack, this is also, Scanned with CamScannerSev of Mireornocrsion 8085, +38 | reerme non ~ | FFFF DAD SP (Double Addition of Stack Pointer Data) SPHL (Transfer HL pair data into Stack Pointer) 34.4.1. Initialization of Stack Memory. Bef: 10 define the si of Stack memory. As ata is save ‘k memory is started/initialigy If IFFF H is ¢ t memory location address, then = 0000 H. To start the S| ie address into SP usj LXI SP. Fy Scanned with CamScannersing mode) (Single byte: (No fl Scanned with CamScanner} | Step 4 X-1 +) ——"] SP SP (RIAM) (Register Indirect Addressing Mode) jingle byte instruction) flags are affected) step 1, the contents of stack pointer is loaded into lower register 7 step 2, the contents of stack pointer is incremented by 1. step 3, the contents of stack pointer is loaded into higher In step 4, stack pointer is incremented by 1. When microprocessor executes POP Rp instruction, then memory location is transferred into register pair Rp and th y two. The memory location where 16 bit address is (viii) XTHL (Exchange Stack Top with Hl SP (Implicit addressing mode (Single byte instruction) (No flags are affected Scanned with CamScannerAs XTHL is Scanned with CamScanner(i) IMP aaa 88 (16 bit) (Wnconditional Jump) address ——e [dar Fo : | T OX: ample, SMP 5000, 5000 1 —C_] * \ Pe With IMP 5000 H, PC is loaded with 5000 H Suppose the instructi struction IMP 5000 H is store e micro (ohio achat is stored in the microp' rocessor from address 4200 H JMP 4201 H 00 4202 H 50 I av freee air ies i P MICROPROGE J a IMP 5000 H is executed, Microprocessor 5000 H Z Fig. 3.2 (2). ‘When instruction ‘Z’ in place of “Y’. iii) Conditional Jump f the condition given in the instru ansferred into program count If the condition given in not transferred into PCy (a) JC address, With Scanned with CamScanner(d) JNZ address (16 bit) uM if no Zer With this instruction if (Z = 0),' then mig (e) JPE address (16 bit) (JUMP if parity With this instruction if (P = 1), then mié () JPO address (16 bit) (JUMP. With. fe1 9875 H 9876 H 9877 H 9878 H 9899 H y Fig.33 3.4.6. Subroutine/Subprogram/Service-Routine. If any operation im is required to be performed more than once, then it is called repetitive such operation, programmer can prepare the program only once and stored in separate memory location. As this program is a part of is called Subprogram/Subroutine/Service Routine. This sul for number of times and when required to execute the sul to give CALL instruction in the main program. (@ CALL address (16 bit) (Unconditional Call) MAIN PROGRAM CALL SUBPROGRAM subprogram. Microp} by decrementing Scanned with CamScanner(1) The address 5000 H given alongwith (Temporary register pair). PC will contai Ww (2) The address 2167 H of next instruction (PUSH PC). Scanned with CamScannerTarehcnow Set or MicROrNOCRON BOBS j Toprocessor transfers control back from subprogram to main ansfers the contents of stack top to program counter. With this incremented by 2 Sequence of Operation : (Refer Fig. 3.4) By RET instruction, mic Program. Microprocessor tr instruction, stack pointer is (8) After op-code fetch of RET instruction, PC will contain address 5164 Has shown in Fig. 3.4 above [ster] Pc (ii) When microprocessor executes RET instruction, then the address 2167 H is ferred back from stack top to PC oud nasn|_ 7146 | 91464 7? So control is transferred back from subprogram to main program and fi from where microprocessor has left carlies If CALL instruction is given in main program, then RET instruction In subprogram. (#i) Conditional CALL Instructions Sequence of Operation 1. If condition given in the instruction is satisfied t “CALL! instruction ie. microprocessor execu address, 2. If condition given in the instruction is not CALL subprogram, instead micropro sequence. The different Conditional 88 (16 bit) (CALL if If (CF = 1), then microproce (b) CNC address (16 bit) (C, if CF = 0, then mictopr (c) CZ address (16 bit) if Z = 1, then micr (d) CNZ address (11 Scanned with CamScanner(g) CM address (16 bit) (CALL if if S = 1, then microprocessor = (h) CP address (16 bit) (CALL if if S = 0, then microprocessor (iv) Conditional Return Instructio 1. If condition given in the instruction i RET instruction, ie. microprocessor 2. If condition given in the instruction i Scanned CamScannera 3. eo 48. Other Instructions of Microprocessor : | 1. NOP (No Operation), This instruction does not perform any operation, but for FT an’ the opcode from memory location to instruction (opcode fetch), microprocessor | Will requite 4 clock cycles so four clock cycles time of microprocessor is wasted. If a time lay or time gap of four clock cycles is required between the execution of two instructions | Xand Y, then for producing this time delay, programmer can give NOP instruction between the instruction X and Y 2. HLT (HALT). This instruction should be the last instruction of all main programs. After Opcode fetch of HALT" instruction, the address of PC is auto incremented by one. When microprocessor executes HALT instruction, then it performs the following operations: (® The address in PC is decremented by one. (@) Microprocessor stops opcode fetch operation and execution of any other instruction. This is called HALT state of microprocessor can be made to exit from HALT state by the following methods (a) When microprocessor is reset (©) When microprocessor is (©) When interrupted ogic ‘1’ is applied on HOLD pin of microprocessor. he above methods, opcode fetch circuit is enabled, hence micrt opcode fetch and execution of instruction. 3.IN and OUT IN : Input Data to Accumulator from a port with 8 bit Addn Opcode Operand Bytes M-Cycles IN 8 bit port 3 address The contents of the input port whose address is g accumulator. Flags. No flags are affected OUT : Output Data from Accumulator Opeode Operand Bytes M. OUT 8 bit port 2 address The contents of the accumulato operand. Flags. No flags are aff Scanned with CamScannerScanned with CamScanner_____ 5.1. INTRODUCTION When microprocessor executes any prog etween the execution of main program, if mig ch from main prog) tine (ISR) as shown in ion comes in the ISR, then microprocessor from where it has left. by Row instruct instruction “Y Scanned with CamScanner5.2.1. Sequen 16 H as shown in Fig, fe the contents of sta: top. - Let the main program is stored fj ‘3 and RST 2 instruction is given at location 3517 H. kitty, ck pointer is 8153. Stack p INTERRUPT SERVICE ROUTINE 010 ont MAIN PROGRAM SS os 2 2 sP Fig. 5.3. Execution of RST 2. After Opcode fetch of ‘RST 2’ instruction, the addres shown below : IR RST2 The address 3518 H of next instruction Y shown in Fig. 5.4. The contents of SP is decrer Scanned with CamScannerwe address (8 X n) His transferred - 0H Her «mis coul ll the ace, microprocessor Will execute if also be done by CALL 0010 IC, so we cannot store TSR at these se locations, so microprocessor f RAM memory locations. H R address of ‘RSTn’ instruction Calf Scanned with CamScanneros Let mae Biv Main ms en at Memon stam a i PY locatign tO" from mo re ey Step |, von 2158, “MONY location 2187 Hf and RST 6 imams Pc + Let ini : | Contaj, MMitially s; a | Sms 215914 which in FC24. After RST 6, 1R : | re 6, IR. contains opcode of - pulttess of next instruction 10 be exccuad’ oT © md SP | FC24 | a IR | RST6 ; 2159 i Step 2. Stack pointe & aa ‘CK Pointer is decremented by two and contents of PC is Stored into stag Sheep: (Fey22] rcx 59 Fc23 [21 -+— FC 24 21 [59 Pig Step 3. Address of RST 6 is calculated as given below : 8xn= 8x 6=(48)) =30H So 0030 H is loaded into PC 0030 H 00 | 30 PamagG Step 4. So microprocessor executes ISR from location 0030 H. Step 5. When RET instruction comes in the ISR, then micropro from ISR to main program instruction ‘Y’. 5.2.3. Difference between CALL, JMP and RSTn jaress | CALL Aron TBI (Triple Byte Instruction) 2. The address of next 2. The 16 bit address of ” instruction is not saved instructon is saved. from PC to Stack memory to stock | The 16 bit branching address is given alongwith JMP/CALL instruction ond is address can be anything Scanned with CamScannerIn all the jssled by an instruction that iss ¢ r The block diagram which controls the diferent ig shown in Fig. 5.6. The description of different 1. TRAP (RST 4.5). 11 is the positive ed joterrupt. This means that, ifthe signal on the TRAP high level, the microprocessor completes the cu Counter in the stack, and branches to location 0024 veitive edge and level) on the TRAP ine, the p eevne falling edge. This avoids multiple inte used for such critical events as po generally It has first priority. TRAP interrupt (NMI). Scanned with CamScannerWhen positive edge is applied at RST 7.5 pin, the 8085 microprocessor completes execution of the current instruction, push the current program counter ee in the stack and branches to 003C H. This positive edge also sets an internal D - ra that it remembers the RST 7.5 interrupt. The recognition of RST 7.5 automatically @sables the 8085 system interrupt. 3 i 3. RST 65. It is level triggered (5°) hardware interrupt having third priority. Ir can be disabled so it is maskable interrupt. It is enabled if (@ Q=1 (b) M.65=0. When a high level signal is applied at RST 6.5, it causes the 8085 to complete xecution of the current instruction, push the current program counter contents im the tack and branches to 0034 H. The recognition of RST 6.5 automatically disables the 085 system interrupt. 4, RST 5.5. It is level triggered (7) hardware interrupt having 4th priority. It can be disabled, so it is maskable interrupt. RST 5.5 interrupt is enable if @)Q=1 (6) M55 =0. When a high level signal is applied at RST 5.5, it causes the 8085 to c execution of the current instruction, push the current program counter cont stack and branches to 002C H. The recognition of RST 5.5 automatically i 8085 system interrupt. RST 5.5, RST 6.5, RST 7.5 can be enabled or SIM instruction. 5. INTR. It is level triggered (7) hardware interrupt havi be disabled, so it is maskable interrupt. ‘INTR’ is enable if (a) Q=1. ; A high level on this pin causes the 8085 to cot instruction, push the program counter contents in acknowledge (INTA ) low pulse on the control bi either a one byte RSTn (RST 0 - RST 7) or a provided by an external hardware. i The hardware interrupt of Scanned with CamScanner2, RST7.5 Se 8 x 6.5 = 00344 me 8x 5.5=002CH | Itdepends on opcode i | by on external hardware 5.4. MACHINE CONTROL INSTI CONTROLLING HARDW. For explanation of Machine Co Interrupt. (Fig. 5. : Scanned with CamScanner. ‘Reset’ input = 1, (OR Gate - 5). So, R= 1, Q, are disabled, i es hardware ji hen, “Any Interry ecognised’ = es hardware interrupt signal, # ra hanhend = 1s R= 1, O; = 0, hence, when microprocessor executes ISR of any th Ware interrupt, then, Q; = 0.'To make Q; = 1, we have to give instruction “BI” jn | © ISR normally before ‘RET instruction 3. SIM Instruction (Set Interrupt Mask) | (Implicit Addressing Mode) (Single Byte Instruction) This instruction is used for three different functions : (a) To set masking bits for RST 7.5, RST 6.5 and RST 5.5 interrupts. (b) The second function is to reset RST 7.5 flip-flop. (©) The third function is to implement serial Input Output. Format for SIM instruction : Ay Sara. Me 43 fa 5 ARSE Ao. soo | soe | x | rvs [use [urs | Mes | M55 See nae i RST7SMASK Co RST 6.5 MASK bares ST 5.5 MASK 1—> MASKED [eee te { 1F 0. BITS 0-2 IGNORED. mococreune { pessoa ———» RESETRST75 IF 1, RST 7.5 FLIP FLOP IS RESET OFF peg doa IF 1, BIT Ay 1S OUTPUT TO SERIAL OUTPUT SERIAL OUTPUT DATA IGNORE, IF BIT. When microprocessor executes SIM instruction, then & transferred to different flip-flops as given in the format Explanation. If A, = MSE (Masking Set Fi ible) and Ay flip-flops are transferred to masking flip, respectively. For example : 1. (a)lf A, = MSE 1, Ay = 0/1, th Scanned with CamScanner(b)If A, = SOB = 0, then Ay Hence the data transfer is. possi Example $.1. Write instruction t ena ‘gn SOD pin Solution. To enable RST 5.5, 0, To enable RST 6.5, Q, 8 bit data of a 1 and M Scanned CamScannerScanned with CamScannerScanned with CamScannerScanned with CamScanner“reps OF Execution ; a It address in “PC” is 4125 H and Microproce: Q) : R ) Microprocessor will Stee tnstruction Y from PC to Stack as shown in ig sa an eras contains 8174 H crag oe oe aa ove ae GRR Fay ph oe ER rc Fig. 5.8 (b). (3) For RST 7.5, n = 7.5, So ISR addr ess will be 8 x 7.5 = 003C H, this address ig i Ssor execute ISR from location 0003C H. (4) When mic 'y hardware interrupt ISR, then any interrupt = » instruction ‘EI’ is given in the ISR before ‘RET’ instruction. recognised = 1, so R 7.5 = 1, so Q To make Q, = 1 - SEQUENCE OF EXECUTION OF HARDWARE INTERRUPT (INTR) INTERRUPTING DEVICE Scanned with CamScanner(d) VO Read machine cycle. The time required by microprocessor to read one pp from V/O device is called 1/O read machine cycle, It requires 3T-states. (e) /O Write machine cycle. Time required by microprocessor to write one g data into I/O device is called /O Write machine cycle, It requires 3T-states, 8.3. INSTRUCTION CYCLE Time required by the microprocessor to execute one instruction is called Insp cycle. One instruction cycle con: of either one or more than one machine cycles, total number of clock cycles required for executing the different instructions varies frg 4 clock cycles to 18 clock cycles. 8.4. HOW A STORED PROGRAM IS EXECUTED ? The first operation in any instruction is op-code fetch. During opcode fetch the CPU transfer contents of program counter (PC) on address bus and performs read operation to read opcode of the particular instruction. Then microprocessot memory read /write operation depending upon the instruction. 8.5. TIMING DIAGRAM OF OPCODE FETCH MACHINE CYCLE Ty T —) - _— crock ‘\ JaeeN |e [onan / Scanned with CamScannerAs 10/M =0, RD =0, WR <: Hence 8 bit opcode The address ae Drpan eal i ii) Ts Clock Cycle. In this elo on ADy~ AD, pins. Then signal. The fetch cycle is (iv) T, Clock Cycle instruction is executed, Af and the data bus Scanned with CamScanneri tai, Se a 8 MSB's OF ADDRESS rm y LSBs OF Ne y ADDRESS y ADy i ALE 108 IO/M = 1/0 RESPECTIVELY Fig. 8.3. To latch 8 LSB’s of address on AD, ~ ADy pins, ALE pin. Microprocessor also gives IO/M = 1 respectively. So 8 bit data of ins AD, - ADy. (3) T, Clock G Scanned with CamScannerScanned with CamScannerinstruction decoder is called machine language instruction. 3. Mnemonics. Instruction of microprocessor, made in the for abbrevations. 4. Addressing Mode. The method by which the address of source is given. 5. Types of Instructions : 1. Single byte instruction 2. Double byte instruction 3. Triple byte instruction. 6. STACK memory. Part of RAM which is used to save useful di FILO fashion. 7. STACK pointer. 16 bit register which hold the address of stack t 8. Sub program. Part of main program which can be called again 9, Summary of Instruction Set : ACI : Add Immediate data to Accumulator with Carry Opcode Operand Bytes M-Cycles T-States ACI 8-bit data az Zz 7 Flags. All flags are affected. ADC : Add Register to Accumulator with Carry Opcode Operand Bytes M-Cycles T-States ADC Reg. (R) 1 4 Mem. (M) 1 2 ao Scanned with CamScannerFlags. S, Z, P are modified to efl Scanned with CamScannerCMA : Compliment Accumulator Opeode Operand Bytes M-Cycles CMA None 1 1 Flags. No flags are affected. CMC : Compliment Carry Flag Opcode Operand Bytes M-Cycles T-States_ Hexcode CMC None 1 1 4 3F Flags. 8 bit data of Register/Memory are affected, no other flags are affected. T-States Hexcode 4 2F CMP : Compare with Accumulator Opcode Operand CMP Reg. (R) 1 i Mem. (M) 1 Hexcode . Hex B8 B9 BA BB BC BD BE BF Bytes | M-Cycles _T-States 4 2 - w & we ted ddsrh ine) Lefer. tes) Description. The contents of the oj i perand regist contents of the accumulator. eee oe If (A) < (Reg/Mem) : Carry flag is set If (A) = (Reg/Mem) : Zero flag is set f(A) > (Reg/Mem) : Carry Flags. S, P, AC a Operation, be CPI : Compare Opcode. Scanned with CamScannerScanned with CamScannerSE ene Bytes M-Cycles ‘T-States Hexcode : ee nd 7 the ae except ota are Porgy ee ee ‘he instruction is given in Chapter 6. Flags. No flags are affected. 1: Bnable Interrupts Opcode Operand Bytes M-Cycles T-States Hexcode Bl None 1 1 a FB The Interrupt Enable flip- -flop is set and all interrupts are enabled. The di explanation of the oe No flags are affected. 7 ; Halt and Enter Wait State Opcode Operand Bytes. M-Cycles HLT None 1 2 or more 5 or more 76 T-States Hexcode Flags. No flags are affected. DN - Input Data to Accumulator from a Port with 8 bit Address Opeode Operand Bytes M-Cycles T-States Hexcode IN 8 bit port 2 a address io DB { the input port whose address is gi ss is given are read and loaded int Flags. erie ENR : Increment contents of Register/Mi Opeede Operand Bytes, Ink Reg Mem, flags are affected. Scanned with CamScannerScanned with CamScannerFlags. No flags are affected. LDAX : Load Accumulator Indirect Opcode Operand Bytes | M-Cycles T-States He LDAX B/D Reg. 1 2 7 Rey pair B DI The contents of memory location is copied into the accumulator the memory location is given by register pair. Flags. No flags are affected. LHLD : Load H and L Registers Directly from Memory Opcode Operand Bytes M-Cycles T-States LHLD 16 bit 3 5) 16 address Flags. No flags are affected. LXI : Load Register Pair Immediate Opcode Operand Bytes M-Cycles _T--States LxXI Reg. pair 3 3 10 16 bit data + Move-copy from Opcode Moy Scanned with CamScannerDestination Location B Cc dD BE iH L M A MVI : Move Iminediate 8-bit Opcode Operand INR __Reg., Data Mem., Data Scanned with CamScannerFlags. ZS, P are modified to reflect the results of the operation, AC and as. ZS ; reset ORI ; Logically or Immediate Opcode Operand —_ Bytes. M-Cyeles ort 8 bit 2 2 7 ¥6 data States Hexcode The contents of the accumulator are logically ORed with the 8-bit data and 3 back to accumulator Flags. S, Z, P are modified to reflect the results of the operation. CY and OUT : Output data from Accumulator to a Port with 8-bit Address Opcode Operand Bytes M-Cycles tates Hexes OUT 8 bit port 2 3 10 D3. data The contents of the accumulator are copied into the output port specified operand. Flags. No flags are affected. PCHL : Load Program Counter with HL Contents Opcode Operand Bytes. M-Cycles__T-States PCHL None 1 1 Hexcode 6 E9 : The contents of registers H and L are copied into the program counter, The f H are placed as a high-order byte and of L as a low-order byte, 4 Flags. No flags are affected, POP : POP the contents of Opeode Operand POP Reg Scanned with CamScannerPUSH : Push Register Pair into Stack Peode = Operand = Bytes. M-Cycies. T-S PUSH Reg. pait 1 7 Flags. No flags are modified. RAL : Rotate Accumulator Left through Carry, Opcode Operand Bytes M-Cycles RAL None 1 1 ‘With this instruction each binary bit of the ag through the Carry fla in the b placed in the least significant position Dy. Scanned with CamScannerRLC : Rotate Accumulator Left Opcode Operand Bytes M-Cycles T-States Hi RLC None 1 1 4 With this instruction each binary bit of the accumulator is rotated | Bit D, is placed im the position of Dy as well as in the Carry flag. Flags. CF is modified according to bit D,. S, Z, P, AC are not affe RRC : Rotate Accumulator Right Opcode Operand Bytes M-Cycles T-States Hi RLC None 1 1 4 With this instruction each binary bit of the accumulator is rotated right Bit D, is placed in the position of D, as well as in the Carry flag. Flags. CF is modified according to bit Dy. S, Z, P, AC are not RET : Return from Subroutine Unconditionally Opcode Operand Bytes M-Cycles__T-States RET None 1 3 10 Flags. No flags are affected. Return conditionally Op Description Flag Hex main program on Carry CY= D, ogram withNoCary CY=0 D, Program on positive S=0 Ff, main program on minus main program on Parity Even ° main program on Parity Odd on Zero © main program on No J Mote, If condition is £ not ion is true it No flags are af Scanned with CamScannerBytes 1 Opcode/Operand RSTO RST 1 1 1 RST2 1 RST3 1 RST 4 1 RSTS 1 RST 6 1 RST7 1 Scanned with CamScanner—————————— Flags. No flags are affected. : Set Interrupt Mask te ess Operand —_ Bytes M-Cycles T-States Hex SIM None 1 1 4 3 : Copy H and L Registers to the Stack Pointer Opcode Operand Bytes M-Cycles T-States Hex 1 1 6 (8085) 5 (8080) SPHL SPHL None Flags. No flags are affected. STA : Store Accumulator Directly into Memory Location Opcode Operand Bytes M-Cycles T-States Hi STA 16-bit a 4 13 Flags. No flags are affected. STAX ; Store Accumulator Indirectly from Memory Location Opcode Operand Bytes. M-Cycles _T-States SSB B/D reg it 2 a pair B Flags. No flags are affected, SUC : Set Carry Flag 0 peode Operand Bytes M-Cycles _ T-States Scanned with CamScannerFlags. All flags are affected. ’ SUI : Subtract Immediate 8 bit data from Accumulator Opcode Operand Bytes. M-Cycles_ > SUI 8-bit 2 ai data Flags. All flags are affected. XCHG : Exchange HL pair with DE pair data Opcode Operand Bytes. M-Cyeles XCHG None 1 ‘ Flags. No flags are affected. XRA : Exclusive OR with Accumulat Opcode Operand —_Byt XRA Reg. Mem. Scanned with CamScanner