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A Single and Adjacent Error Correction Code

for Fast Decoding of Critical Bits
Kazuteru Namba, Member and Fabrizio Lombardi, Fellow
two parts: the critical bits and the other (remaining) bits;
Abstract— Many systems have critical bits which must be critical bits must be decoded faster than the other bits as well
decoded at high speeds; for example, flags to mark the start and end of a as for the bits in traditional (minimum-weighted) Hamming
packet (SOP and EOP) determine subsequent actions, thus they must be SEC codewords. In this SEC code, a syndrome is divided into
decoded first and fast. This paper presents a new single and adjacent
error correction (SAEC) code; as the codewords have critical bits, the
two parts; only one part is examined for decoding the critical
proposed code accomplishes a fast decoding for them. The proposed code bits. This scheme reduces the decoding time by not
is a systematic code and permits shortening. This is accomplished by considering the other part; in this decoding scheme, the SEC
reducing the information bits, so that columns in the H matrix can be code of [9] does not use some column vectors in the H matrix,
eliminated, while still keeping both the SAEC capability and the
systematic feature, but for an odd number of information bits, an
so it is different from a traditional Hamming code.
adjustment step in critical bits is required. It is shown that the check bit The adjacent error is a specific type of multiple error; in
length of the proposed code is nearly the same as that of the traditional such error, two adjacent bits are flipped, i.e. a burst error with
(optimal) Hamming SAEC code. The decoder of the proposed SAEC code a length of two bits. Adjacent errors occur frequently in
is compared with the traditional Hamming SAEC code; this comparison
shows that on average, the delay time for the critical bits is reduced by 6 %
memory systems [11,12,13]; they can also occur in
compared with the traditional Hamming SAEC code (so at the same communication systems due to several physical phenomena,
reduction level as a previous SEC scheme for fast decoding of critical bits such as in the presence of crosstalk [14,15]. Therefore,
over a traditional SEC code). Also, the area and power consumption of adjacent ECCs have also been proposed in the technical
the proposed decoder show average reductions of 12% and 10%
compared with the decoder of a traditional SAEC code.
literature for communication systems. An optimal single and
Index Terms— error correction code (ECC), adjacent error adjacent error correcting code based on Hamming codes has
correction, parallel decoding, critical bits. been presented in [1]. The scheme of [9] supports only single
errors for correction. To the best knowledge of the authors,
I. INTRODUCTION there are no existing ECCs with stronger functions for fast
decoding of critical bits.
Error control codes (also referred to as error correcting
This paper presents a single and adjacent error correction
codes, ECCs) are widely used to improve system
(SAEC) code. In the proposed code, critical bits are decoded
dependability, in particular for communication and storage
fast; the proposed SAEC code is a systematic code. A detailed
systems [1]. Based on application and requirements, high
analysis of the features of the proposed code is pursued; for
speed ECC decoding is often required and usually
example, it is shown that the proposed code permits
implemented using a parallel decoding scheme. Parallel
shortening; the information bits can be reduced, such that
decoding does not use feedback shift registers because it must
some columns in the H matrix can be eliminated, while still
execute in only few clock cycles. Several parallel decoding
keeping both the SAEC capability and the systematic feature.
schemes have been proposed [1,2]; some of these schemes
However, for an odd number of information bits, an
target burst ECCs [1,3,4]. The scheme of [5] considers long
adjustment step in critical bits is required. It is also shown that
codewords; some codes suitable for parallel decoding, e.g.
the check bit length of the proposed code is nearly the same as
orthogonal Latin square codes, have been studied [6] and few
the traditional (optimal) Hamming SAEC code. Comparison in
schemes have been analyzed to reduce the delay of a parallel
terms of different figures of merits (such as delay time for the
decoder [7,8].
critical bits, decoder area and power dissipation) is presented.
Systems with so-called critical bits require decoding for
These results confirm that the proposed SAEC code improves
these bits to be performed at high speed; for example, in some
over the traditional Hamming SAEC code; moreover
circuits that are part of a packet-based communication system
simulation results show that for decoding of critical bits,
(such as a router or a switch), every packet is first saved into
SAEC is provided at nearly the same figures of merit as SEC
storage, and then decoded in parallel [9]. In such system, the
in [9]
flags marking the start and end of a packet (SOP and EOP)
This paper is organized as follows. Section 2 presents a
determine the subsequent actions [10]; thus, the flags (so
brief review of relevant works in the technical literature; it
critical bits) must be decoded fast. To decode such critical bits
also discusses that the scheme of [9] cannot be extended to an
fast, Reviriego et. al. have presented a single error correction
adjacent error correcting code. Section 3 proposes the new
(SEC) code [9]. In this SEC code, codewords are divided into
SAEC code. A detailed evaluation and comparison of the
proposed code is pursued in Section 4. Section 5 concludes
K. Namba is with the Graduate School of Advanced Integration Science,
Chiba University, Chiba, JAPAN, email: namba@ieee.org; F. Lombardi is this manuscript.
with the Department of Electrical and Computer Engineering, Northeastern
University, Boston, MA 02115, USA; email: lombardi@ece.neu.edu
0018-9340 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TC.2018.2821688, IEEE
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Figure 1. Example H matrix of [9].
pattern by applying the original syndrome s to the error pattern

II. REVIEW calculation for the original code.
This row operation reduces the non-zero elements in the
A. Single and adjacent error correcting code (SAEC)
lowermost row, so bringing in a faster decoding. For example,
The construction of a traditional SAEC code [1] is the following matrix H is an H matrix of an SAEC code; P is a
presented next. This code is optimal; furthermore the check bit regular matrix:
length of the code is only one bit more than the Hamming 1 0 0 1 0 1 1
SEC code. 0 1 0 1 1 1 0
| 𝐻𝐻 = � �
0 0 1 0 1 1 1
Let α be a root of a generation polynomial; 𝑥𝑥 denote a 1 1 1 1 1 1 1
| 1 0 0 0
coefficient vector (column vector) of x. For example, consider 0 1 0 0
a generation polynomial g(x)=x3+x+1. It is true that 𝑃𝑃 = � �
0 0 1 0
| | | | | | | 1 1 1 1
0 1 2 3 4 5
�𝛼𝛼 𝛼𝛼 𝛼𝛼 𝛼𝛼 𝛼𝛼 𝛼𝛼 𝛼𝛼 6 � The following matrix PH also works as an H matrix of an
| | | | | | | SAEC code:
1 0 0 1 0 1 1 1 0 0 1 0 1 1
= �0 1 0 1 1 1 0� 0 1 0 1 1 1 0
𝑃𝑃𝑃𝑃 = � �
0 0 1 0 1 1 1 0 0 1 0 1 1 1
The following H matrix is capable of correcting single 0 0 0 1 1 0 1
and adjacent errors. The number of non-zero elements in the lowermost row of PH
| | | is significantly less than for H.
0 1 𝑖𝑖
𝐻𝐻 = � 𝛼𝛼 𝛼𝛼 ⋯ 𝛼𝛼 ⋯� B. SEC code for fast decoding of critical bits
| | | Figure 1 shows an example of an H matrix of the SEC
1 1 ⋯ 1 ⋯ code of [9]. In this scheme, every codeword consists of critical
In this paper, O denotes a zero matrix or a zero vector, or
bits, the other information bits (simply referred hereafter to as
O means that the value of all elements (except those whose
“information bits”) and check bits. This matrix consists of two
values are specified) are zero. For example, the following
sets of column vectors C 1 and C 2 ; C 1 corresponds to the
matrix represents an identity matrix:
critical bits and C 2 corresponds to the information and check
1 𝑂𝑂
bits. This matrix also consists of two sets of rows R 1 and R 2 .
� ⋱ �
All column vectors are non-zero and differ from each other;
𝑂𝑂 1
moreover, for columns in C 1 , the bits corresponding to R 1
The H matrix capable of correcting single and adjacent
errors has a row in which all elements are non-zero; such row
incurs in slow decoding even when parallel decoding is
employed. So, the H matrix is usually transformed by the row
operation (i.e. left-multiplication by a regular matrix) using
the following regular matrix [1]:
1 𝑂𝑂 0
𝑃𝑃 = � ⋱ ⋮�
𝑂𝑂 1 0
1 ⋯ 1 1
In this row operation, all rows (but the lowermost row) are
added to the lowermost row.
It is well known that row operations do not change the
code function, because the error pattern can be calculated
using the same process as for the original code. This is given
as follows. A syndrome s is given by sT=HeT where xT is the
transpose of x; the syndrome s' for the row-operated code is Figure 2. Outline of parallel decoder with fast decoding for critical
given by s'T=PHeT=PsT. So we can obtain the original bits.
syndrome s by sT=P−1s'T. Finally we can calculate the error
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considered in the modified code; this XOR is not considered

in the original code. The XOR is equal to the XOR of other
adjacent (fourth and fifth) column vectors; thus it is not
possible to distinguish adjacent errors on the bits
corresponding to these pairs of column vectors. Finally it is
concluded that this simple extension of [9] is not applicable to
adjacent error correction codes.
III. PROPOSED SAEC CODE SCHEME

A. H matrix of the proposed SAEC code
Figure 3. Example H matrix of SAEC codes and syndromes for This section presents the proposed SAEC code for fast
adjacent errors.
decoding of critical bits. Like the SEC code of [9], every
differ from those for any other columns in C 1 and C 2 . codeword of the proposed SAEC code consists of critical bits,
In the H matrix of the Hamming SEC code, all non-zero other information bits and check bits. The other information
vectors appear as column vectors. For a check bit length of 5, bits are simply referred hereafter to as “information bits.”
the H matrix of the Hamming code has 25−1=31 column The following matrix H is the H matrix of the proposed
vectors; however, the H matrix of the SEC code of [9] (shown SAEC code for fast decoding of critical bits:
in Figure 1) has only 22 (out of the 31 column vectors), i.e.
nine vectors are not used. The bits corresponding to R 1 (i.e.
the uppermost three bits) of the nine vectors are equal to those
of a column vector in C 1 .
Figure 2 illustrates the diagram of the parallel decoder; it
consists of a syndrome generator, an error pattern calculator
and XOR gates. The syndrome generator consists of XOR where flipud(H) is the matrix which is generated by flipping
trees and generates the syndrome from a received word. The the rows of H in the up-down direction; it is defined as
error pattern calculator determines the error pattern from the follows:
syndrome. Finally, the corrected word is given as the XOR of 𝑂𝑂 1
the received word and the error pattern. The error pattern flipud(𝐻𝐻) = � ⋰ � 𝐻𝐻
calculator is divided into two parts, one for the critical bits and 1 𝑂𝑂
one for the information bits; the part for the critical bits The critical bits correspond to the column vectors C 1 .
operates at higher speed. The information bits correspond to C 2 or C 3 . The check bits
Next, the parallel decoding scheme of the code of [9] is correspond to C 4 , C 5 or C 6 . Let k 1 and k 2 be the lengths of the
explained. Let s i be a part of a syndrome corresponding to critical and information bits. Let r 1 and r 2 be the numbers of
rows R i . Initially, s 1 and s 2 are generated in the syndrome rows R 1 and R 2 ; the check bit length r of the proposed code is
generator. In the error pattern calculator for critical bits, s 1 is given by r= r 1 + r 2 +1.
compared with the part corresponding of R 1 of the column Let g α (x) be a primitive polynomial whose degree is
vectors in C 1 . If it is equal to that of the i-th column vector, a equal to r 1 ; let g β (x) be a primitive polynomial whose degree
single error has occurred on the i-th bit in the critical bits and is r 2 , such that r 2 ≥3 and g β (x)≠xr2+xr2−1+1. Let α and β be the
detected. At the same time, in the calculator for the roots of g α (x) and g β (x).
information bits the entire syndrome is compared with the The matrix H 11 is defined as follows:
column vectors in C 2 . If it is equal to the i-th column vector, a | | |
single error on the i-th bit of the received word is then 𝐻𝐻11 = �𝛼𝛼 −𝑘𝑘1 ⋯ 𝛼𝛼 −2 𝛼𝛼 −1 �
detected. The error pattern calculation for critical bits executes | | |
faster for critical bits than information bits, because it where α−1 is an element such that α1α−1 = α0.
examines only s 1 . The matrices H 12 and H 22 are defined as follows:
C. Simple extension of fast decoding for critical bits
Next, we consider a simple extension of the scheme of
[9] for an adjacent error correcting code; however as shown
too, such scheme cannot be extended in a simple way.
Figure 3 shows the H matrix of an SAEC code. All
column vectors and XOR of adjacent column vectors are
distinguishable from each other; so this feature characterizes where m is an integer such that k 2 =m(2r2−1)−r 1 −2 and
the capability of SAEC. Then, the second column vector is m+k 1 <2r1−2.
eliminated; the scheme of [9] requires this elimination, The matrix H 22,i is given as follows:
because it needs some column vectors not to be used. | | |
𝑟𝑟
However, this modified H matrix is not capable of SAEC, 𝐻𝐻22,𝑖𝑖 = �𝛽𝛽 0 𝛽𝛽1 ⋯ 𝛽𝛽 2 2 −2 �
because the XOR of the first and third column vectors must be | | |
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| Table 1. Types of errors.

The j-th column of H 12,i (0≤j≤2 −2) is �𝛼𝛼 𝑖𝑖 � when j is
r2 s3=1 s3=0
| s1≠0 s1=αi s1=(α+1)αi adj. on X1
single on X1
(i<0) (i<0) adj. on X1-X2
| single on X1
s1=αi s1=(α+1)αi adj. on X2
even and �𝛼𝛼 𝑖𝑖+1 � when j is odd; the matrix H 12,i is given as (i≥0)
single on (X3, X4)
(i≥0) adj. on (X3, X4)
adj. on X4-X5
|
s1=0 single on X5 /
follows: single on X6 /
adj. on X2-X3
adj. on X5-X6
| | | | | | adj. on X5
𝐻𝐻12,𝑖𝑖 = �𝛼𝛼 𝑖𝑖 𝛼𝛼 𝑖𝑖+1 𝛼𝛼 𝑖𝑖 ⋯ 𝛼𝛼 𝑖𝑖 𝛼𝛼 𝑖𝑖+1 𝛼𝛼 𝑖𝑖 � single on Xi : single error on Xi
adj. on Xi : adjacent error on Xi
| | | | | | adj. on Xi-Xi+1 : adjacent error between Xi and Xi+1
H' 12,0 and H' 22,0 are obtained by eliminating the two leftmost
columns from H 12,0 and H 22,0 .
s 1 =flipud((α+1)αj), s 2 =(β+1)β2^r2−2 and s 3 =0.
The matrix H 13 is defined as follows:
 If an adjacent error occurs between X 2 and X 3 , s 1 =O,
| | | | s 2 =β2^r2−2 and s 3 =0.
𝐻𝐻13 = �𝛼𝛼 𝑚𝑚−1 𝛼𝛼 𝑚𝑚−2 ⋯ 𝛼𝛼 𝑟𝑟1−1 𝛼𝛼 𝑟𝑟1 �  If an adjacent error occurs on the i-th and (i+1)-th bits of
| | | | (X 3 , X 4 ), s 1 =flipud((α+1)αm−i−2), s 2 =O and s 3 =0.
The following is an example of an H matrix of the  If an adjacent error occurs between X 4 and X 5 ,
proposed code for k 1 =2, k 2 =27, g α (x)=g β (x)=x3+x+1: s 1 =flipud(α0), s 2 =(10⋯0)=β0 and s 3 =1.
 If an adjacent error occurs on the i-th and (i+1)-th bits of
X 5 , s 1 =O, s 3 =0, and the i-th and (i+1)-th bits of s 2 are 1’s and
the other bits of s 2 are 0’s.
(1)
 If an adjacent error occurs between X 5 and X 6 , s 1 =O,
s 2 =(0⋯01) and s 3 =1.
Table 1 summarizes the relations between the syndrome
Next, it is shown that the proposed H matrix is capable of and the types of errors. We can identify the location of errors
correcting single and adjacent errors, i.e. any syndromes of as follows:
single and adjacent errors are non-zero and differ from each  If s 3 =1 and s 1 is non-zero, find i such that s 1 =αi and
other. −k 1 ≤i≤m. As m+k 1 <2r1−2 and g α (x) is a primitive polynomial,
Let X i be a part of a codeword or a received word then a unique i can be found. If i<0, the syndrome is for a
corresponding to columns C i ; let s i be a part of a syndrome single error on the (i+k 1 )-th bit of X 1 . If i≥0, consider s 2 . If
corresponding to rows R i . s 2 =O, it is for a single error on the (m−i−1)-th bit of (X 3 ,X 4 ).
| | | If s 2 ≠O, find j such that s 2 =βj and 0≤j≤2r2−2. If j is even, it is
As flipud �𝛼𝛼 𝑟𝑟1−1 ⋯ 𝛼𝛼 1 𝛼𝛼 0� is an identity matrix, for a single error on the j-th bit of X 2,i ; if j is odd, it is for a
| | | single error on the j-th bit of X 2,i−1 . However if it is established
that an error occurs on the j-th bit of X 2,0 , then this is wrong;
it is true that
the correct fault location is as follows: if j=0, it is for an
| | | | adjacent error between X 4 and X 5 . If j≥2, it is for a single error
(𝐻𝐻13 𝐼𝐼) = �𝛼𝛼 𝑚𝑚−1 𝛼𝛼 𝑚𝑚−2 ⋯ 𝛼𝛼 1 𝛼𝛼 0� on the (j−2)-th bit of X 2,0 .
| | | |  If s 3 =0 and s 1 is non-zero, find i such that s 1 =(α+1)αi and
Hence, consider X 3 and X 4 by regarding the i-th bit of X 4 as −k 1 ≤i≤m. If i<0, it is for an adjacent error on the (i+k 1 )-th bit
the (m−r 1 +i)-th bit of X 3 . We represented the combined part as of X 1 and the next bit (if i=−1, the next bit is on X 2 ; otherwise
| on X 1 ). If i≥0, examine s 2 . If s 2 =O, it is for an adjacent error
(X 3 , X 4 ). Hereafter a column vector �𝑥𝑥 � is denoted simply on the (m−i−1)-th and the next bit of (X 3 , X 4 ). If s 2 ≠O, find j
| such that s 2 =(β+1)βj and it is for an adjacent error on the j-th
by x thus avoiding possible confusion. bit of X 2,i and the next bit. However if it is established that an
The syndromes for single and adjacent errors are as error occurs on the j-th bit of X 2,0 , then it is required to
follows: establish the adjacent error on the (j−2)-th bit of X 2,0 and the
 If a single error occurs on the i-th bit of a received word; next bit.
the syndrome is equal to the i-th column of the H matrix.  If s 1 =O, then either an error on X 5 and X 6 or an adjacent
 If an adjacent error occurs on the i-th and (i+1)-th bit of error between X 2 and X 3 has occurred. If s 2 =β2^r2−2 and s 3 =0,
X 1 (0≤i<k 1 −1), then s 1 =flipud((α+1)αi−k1), s 2 =O and s 3 =0. it is for an adjacent error between X 2 and X 3 . Otherwise, it is
 If an adjacent error occurs between X 1 and X 2 (i.e. the for an error on X 5 and X 6 , the syndrome (s 2 , s 3 ) is equal to the
last bit of X 1 and the first bit of X 2 ), s 1 =flipud((α+1)α−1), error pattern. As g β (x)≠xr2+xr2−1+1, the syndrome for the
s 2 =β2 and s 3 =0. adjacent error between X 2 and X 3 differs from any single or
 If an adjacent error occurs on the i-th and (i+1)-th bits of adjacent error pattern, i.e. it can be distinguished from the
X 2,j , s 1 =flipud((α+1)αj), s 2 =(β+1)βi (for j≠0), s 2 =(β+1)βi+2 (for syndrome for any errors on X 5 and X 6 .
j=0) and s 3 =0. Parallel decoding is accomplished by comparing a
 If an adjacent error occurs between X 2,j and X 2,j+1 ,
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syndrome with the column vectors and the XOR of the

adjacent column vectors (note that this error location
identification process is only used for the proof of the SAEC
capability of the proposed code; it will not be considered for
its implementation). As errors on X 1 can be identified without
examining s 2 , then the decoding time is further reduced by not
using s 2 . The detailed construction of the decoder is discussed
in III.D
B. Row-operated code
Similar to the traditional SAEC code (shown in II.A), the
number of 1’s in the lowermost row can be reduced with a row
operation using the following regular matrix P:
Figure 4. Error pattern calculator for the i-th bit in the proposed
SAEC code.
In the proposed code construction (shown in III.A), the

critical bit length k 1 can be set to an arbitrary value; thus
In this row operation, the rows in R 2 are not added to the shortening of critical bits is not needed. However, the
lowermost row R 3 . information bit length k 2 is limited to m(2r2−1)−r 1 −2 where m,
This row operation does not change the code function (so, r 1 and r 2 must be integer values; thus shortening of the
the SAEC capability); furthermore it does not change the information bit length could be needed.
important feature of the proposed code (namely, the fast As already mentioned previously, an improper shortening
decoding of the critical bits) as explained next. The syndrome can harm the adjacent error correcting capability. We can
s'=(s 1 ' s 2 ' s 3 ') for the row-operated code is given by s'T=PsT shorten the information bit length by eliminating the rightmost
from the syndrome s for the original code. So the parts of the columns without harming the correcting capability. However,
original syndrome s 1 and s 2 are identical to those for the this elimination leads to another problem; this elimination
row-operated code s 1 ' and s 2 '. However, the last bit of the harms the systematic feature of the proposed code (shown in
syndrome for the original code s 3 is given by the sum (XOR) III.B), because it destroys the identity matrix in the rightmost
of all bits in s 1 ' and the last bit s 3 '. Overall, the original columns.
syndrome s 1 and s 3 is found from s 1 ' and s 3 '; therefore, it is To reduce the information bits and still keeping both the
possible to decode the critical bits by not examining s 2 '. SAEC capability and the systematic feature, the leftmost
This row operation makes the rightmost (r 1 +r 2 +1) columns in C 2,0 can be eliminated (where the number of
columns as an identity matrix; thus, the proposed eliminated columns must be even). For example, if we want to
row-operated code is a systematic code, because information reduce two information bits from the codeword of the example
words are embedded in the codewords with no change. H matrix in Eq. (1), the following two columns (i.e. the
The example H matrix in Eq. (1) can be transformed as leftmost two columns in C 2,0 ) can be eliminated:
follows:
This elimination does not harm the adjacent error correcting

The row operation reduces the number of 1’s in the capability as explained below. This changes the syndrome of
lowermost row; it does not change the rows except the the adjacent errors between X 1 and X 2 ; however it changes
lowermost one. Furthermore, a 7×7 identity matrix appears at only s 2 , which is not examined for the decoding of the critical
the rightmost seven columns. bits. Furthermore, this elimination does not change the
C. Code shortening syndromes for any other errors.
The proposed code does not allow shortening odd
In general, a shortened error correcting code can be used;
information bits. If an odd number of information bits must be
however, it is not easy to shorten an adjacent error correcting
reduced, an adjustment step is required. The leftmost
code, i.e. it is not easy to delete column vectors for adjacent
information bit can be regarded as critical. So effectively
error correction. Moreover, an arbitrarily shortening can harm
making even the number of information bits required. It is not
the adjacent error correcting capability as mentioned
possible to eliminate columns corresponding to the
previously in II.C.
information bits, except those in C 2,0 . If it is needed to reduce
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Figure 7. Power consumption of parallel decoder for proposed

code (normalized by the traditional code at 100%).
Figure 5. Delay time of parallel decoder for proposed code

Table 2. Check bit length of proposed code and difference from
(normalized by the traditional code at 100%).
traditional SAEC code
k1 k2=64 128 256 512 1,024
4 8 (+0) 9 (+0) 10 (+0) 11 (+0) 12 (+0)
8 9 (+1) 9 (+0) 10 (+0) 11 (+0) 12 (+0)
16 9 (+1) 10 (+1) 10 (+0) 11 (+0) 12 (+0)
error detector detects a single error on the i-th bit by

comparing the syndrome with the i-th column vector of the H
matrix. The adjacent error detector compares the syndrome
with the XOR of the two corresponding column vectors. The
calculator shares the adjacent error detectors with the adjacent
calculators (for the (i−1)-th and (i+1)-th bits). For critical bits,
only s 1 and s 3 as parts of the syndrome are used; s 2 is not
examined (however for the information bits, all parts s 1 , s 2
and s 3 are examined). The error pattern calculator for critical
bits is smaller and faster than for the information bits; this
feature accounts for the faster decoding of the critical bits.
IV. EVALUATION
In this section, the decoder of the proposed code is
Figure 6. Area of parallel decoder for proposed code (normalized compared with the traditional optimal SAEC code (shown in
by the traditional code at 100%). II.A). These decoders are designed by Verilog and then
synthesized by the Synopsys Design Compiler with an
more information bits, the parameter m should be set to a industrial 180nm technology.
smaller value in the code construction. Figure 5 shows the delay times for the proposed code
D. Hardware normalized by the traditional SAEC code (i.e. at 100%). The
delay time for the critical bits is reduced on average to 94%
Next, the parallel encoder and decoder for the proposed
(this average is shown in the figure with a dotted line), i.e. a
code are presented. A parallel encoder for the proposed code is
6 % reduction. 94% is also the same average delay as the SEC
constructed by a conventional scheme i.e. using XOR trees.
of [9] compared with the traditional Hamming SEC code.
The proposed code can be decoded in a manner similar to [13];
The result for k 1 =8 and k 2 =1024 is due to the large fan-out in
hence, the outline of the parallel decoder for the proposed
the error pattern calculator; a large number of inverters and
code is the same as in [13] (shown in Figure 2). The difference
buffers were inserted by the synthesis tool.
from [13] is in the error pattern calculator.
Figures 6 and 7 show the area and the power
Figure 4 shows the error pattern calculator for the i-th bit
consumption normalized by those for the traditional SAEC
on the proposed code. The calculator for every information bit
code (again at 100% and averages shown by dotted lines in
is placed in parallel; the calculator consists of a single error
these figures). The results for the proposed code are better
detector, adjacent error detectors and an OR gate. The single
EDIT) <
than the traditional code; the average area and power hardware implementation have many positive features. The
consumption are at 88 % and 90 % levels of those for the check bit length of the proposed code has been shown to be
decoder of the traditional code. The result for k 1 =8 and nearly the same as the traditional (optimal) Hamming SAEC
k 2 =1,024 is caused by the large number of inverters and code. The design of the decoder for the proposed SAEC code
buffers. These additional inverters and buffers increase the has been compared with the traditional Hamming SAEC code;
power consumption of the circuit. this comparison has shown that on average, the delay time for
Next we consider the reasons for the reductions in area the critical bits has been reduced by 6 % compared with the
and power consumption. These reduction occur for the error traditional Hamming SAEC code (so at the same reduction
pattern calculator, so not for the syndrome generator and the level as the SEC scheme of [9] for fast decoding of critical bits
XORs in Figure 2. These reductions are possible due to two over a traditional SEC code). Also, the area and power
reasons. As first reason, the proposed code does not examine consumption of the proposed decoder have shown average
s 2 for the critical bits; as second reason, many but same reductions of 12% and 10% compared with the decoder of a
calculations are performed in the error pattern calculator traditional SAEC code.
hardware. Therefore, the synthesis tool targets these Lastly it should be noted that while it has been shown
calculations for improvement. Consider the error on the i-th that a simple extension of SEC [9] to SAEC requires an
bit of X 2,j (0<i<2r2−2); this error can be detected by comparing innovative code construction, the provision of SAEC to SEC
the syndrome with the following three vectors: the column [9] for critical bits using the proposed scheme is rather
vector of the H matrix corresponding to the i-th bit, the XOR efficient as evidenced by the evaluation of the figures of merit
of the column vectors corresponding to the i-th and (i−1)-th (except as expected, for the error pattern calculator) presented
bits, and the XOR of those in the i-th and (i+1)-th bits. So, the in this paper.
error can be detected by the following calculations (for the
case with no row operation): REFERENCES
((s 1 =flipud(α j+(i mod 2) ))∧(s 2 =βi)∧(s 3 =1)) [1] E. Fujiwara, Code design for dependable systems: theory and practical
∨(P j ∧(s 2 =(β+1) β i−1 )) ∨(P j ∧(s 2 =(β+1) β i )) applications.Wiley-Interscience, 2006.
where P j =(s 1 =flipud((α+1)α j )∧(s 3 =0). The calculation of P j [2] K. Namba and F. Lombardi, “High-speed parallel decodable non-binary
single-error correcting (SEC) codes,” IEEE Trans. Device Mater.
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reduction does not occur for the traditional SAEC code. [3] E. Fujiwara, K. Namba, and M. Kitakami, “Parallel decoding for burst
The average area and power consumption for the error control codes,” Proc. 2002 IEEE Int. Symp. Information Theory, p.
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decoder of the traditional code. The proposed code can be also [4] G. Umanesan and E. Fujiwara, “Parallel decoding cyclic burst error
correcting codes,” IEEE Trans. Comput., vol. 54, no. 1, pp. 87–92, Jan.
compared to the SEC code of [9]; in this case, the averages are 2005.
at the 97 % and 104% levels. The reduction in averages occurs [5] P.-Y. Chen, C.-L. Su, C.-H. Chen, and C.-W. Wu, “Generalization of an
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larger than for SEC codes. Furthermore the reduction of the [6] M. Demirci, P. Reviriego, and J. A. Maestro, “Unequal error protection
codes derived from double error correction orthogonal Latin square
calculation for P i does not occur for the SEC code. codes,” IEEE Trans. Comput., vol. 65, no. 9, pp. 2932–2938, Sep. 2016.
Table 2 shows the check bit length of the proposed code. [7] P. Reviriego, S. Pontarelli, J. A. Maestro, and M. Ottavi, “A method to
The value in the parenthesis indicates the difference between construct low delay single error correction codes for protecting data bits
the proposed and the traditional SAEC codes. For example, for only,” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 32,
no. 3, pp. 479–483, Mar. 2013.
k 1 =16 and k 2 =16, the check bit length of the proposed code is
[8] V. Gherman, S. Evain, N. Seymour, and Y. Bonhomme, “Generalized
9, while for the traditional code it is 8; hence, the difference is parity-check matrices for SEC-DED codes with fixed parity,” Proc.
9−8=+1. The check bit length of the proposed code is nearly IEEE Int’l On-Line Testing Symp., 2011.
the same as the traditional (optimal) SAEC code; this feature [9] P. Reviriego, M. Demirci, A. Evans, and J. A. Maestro, “A method to
is also applicable to the scheme of [9], but for SEC. design single error correction codes with fast decoding for a subset of
critical bits,” IEEE Trans. Circuits Syst. II, vol. 63, no. 2, pp. 171–175,
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V. CONCLUSION [10] Ten Gigabit Ethernet Medium Access Controller, OpenCores. [Online].
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multiple-bit soft errors induced by cosmic ray neutrons on DRAM’s,”
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must accomplish fast decoding for the critical bits. The [12] A. Dutta, “Low cost adjacent double error correcting code with complete
proposed code is a systematic code, because information elimination of miscorrection within a dispersion window for multiple bit
words are embedded in the codewords with no change. The upset tolerant memory,” Proc. IEEE/IFIP Int’l Conf. VLSI-SoC, pp.
287–290, 2012.
proposed code is amenable to shortening. To reduce the
[13] D. Radaelli, H. Puchner, S. Wong, and S. Daniel, “Investigation of
information bits, the columns in the H matrix can be multi-bit upsets in a 150 nm technology SRAM device,” IEEE Trans.
eliminated, such that both the SAEC capability and the Nucl. Sci., vol. 52, no. 6, pp. 2433–2437, Dec. 2005.
systematic feature are retained; however, an adjustment step in [14] B. Victor and K. Keutzer, “Bus encoding to prevent crosstalk delay,”
critical bits is required for an odd number of information bits. IEEE/ACM Int. Conf. Comput. Aided Des., 2001.
In terms of figures of merit, the proposed code and its
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no.10, pp.1076–1080., Oct. 2004.

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This article has been accepted for publication in a future issue of this journal, but has not been

A Single and Adjacent Error Correction Code

Figure 1. Example H matrix of [9].

pattern by applying the original syndrome s to the error pattern

considered in the modified code; this XOR is not considered

III. PROPOSED SAEC CODE SCHEME

| Table 1. Types of errors.

syndrome with the column vectors and the XOR of the

In the proposed code construction (shown in III.A), the

This elimination does not harm the adjacent error correcting

Figure 7. Power consumption of parallel decoder for proposed

Figure 5. Delay time of parallel decoder for proposed code

error detector detects a single error on the i-th bit by

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