30B2 US00657773 2) United States Patent (10) Patent No: US 6,677,730 B2 Bedini (45) Date of Patent: Jan. 13, 2004 (S#)_ DEVICE AND METHOD FoR PULSE: So1ssid A 91099 Chi CHARGING ATATTERY AND FOR DRIVING S908008 A 121099 Plan cut OTHER DEVICES WITH A PULSE Sow.6a1 A 2000 Themes Gina A210) Gen — cur Ales SIUU&D A 9 adn a (5) ete to Raia CoA Suu A 30 Ta ; lstait A113 Lam ta : : Stotsso m "Zara, Staion (73) Assignee: Enongems, Ine, Coeur d'Alene, ID cate wit aaa ras (Us) 6.229.285 BL 5/2001 Ding Con BL SA Pony oa (*) Notice: Sabjectto any disclaims, the term ofthis, a tM ose teat extended or add ude 35 US. 1540) by 46 dys OTHER PUBLICATIONS US 6.75216, 12001, Andersen tata) (21) App Nos 10032,28 Pte s Primary Examiner—Eatward H. Tso (22) Filed: Dec. 21, 2001 (74) Attorney, Agent, or Firm—Thomas G, Walsh; (5) Prior Publication Data Ce {i 0801711 At an 25, 28 6 ABSTRACT 6 HUIM 1044; HOLME 1046 A twophase sldtae batley changer can weve igat By Soayiss cosy from 4 vnkty of sours including AC cen 2 brit, DC enero a DCo-DC iver, solr ells or (8) 320/103, 124 ny other compatible source of input energy. Phase I is the 3207125, 125, 130, 159, 16020 olbes compa paresis ‘ charge phase and pine Il the charge pase whocin 4 references Sigal o ewe pase trough dual ining switch hat 6H hed controls independently two channels dividing. the two US. PSTENT DOCUMENTS pate, Te dal ining vic is cote toe chip . br puke with modulo Apel earsillwed 0 Sana A 41904 Potanaty ea Samo A 494 Polity buil op in a capacier bank, the cpactr banks ten Hes aes ee disconnected fom fe enerayinpt soc sd hen pe SS A oo thm aa charger high vlage inte rex to ecuve the cage {oo Brown J tal ‘The mometay dsinnéton of he caper from fhe Sisor Tse lap eoiy sous allows fora fe-foang pote Lier Ok chang inthe capaci. One the cpacior has completed 11007 Repu et a 121997 Podrchasky et 4/1998 Daigle 51999 Tsewer SOLZ347 A 6/109 Gabon SASSI A 81999) Hasepa el discharging the potential charge ito the battery, thee tor disconnects fom the battery and re-connects 10 the energy source thus completing the two-phase eye 25 Claims, 6 Drawing SheetsUS 6,677,730 B2 Sheet 1 of 6 Jan. 13, 2004 US. PatentUS. Patent Jan. 13, 2004 Sheet 2 of 6 US 6,677,730 B2 Ele. 2US. Patent Jan. 13,2004 Sheet 3 of 6 US 6,677,730 B2 GO 42 FIG.US. Patent Jan. 13,2004 Sheet 4 of 6 US 6,677,730 B2 FiG. 4A-PUS. Patent Jan. 13,2004 Sheet 5 of 6 US 6,677,730 B2 Lu! Lp < ry Y A hey Lo Sn) VU UJ ed €iG. 5US. Patent Jan. 13,2004 Sheet 6 of 6 US 6,677,730 B2 9 \ VY Fre. 7US 6,677,730 B2 1 DEVICE AND METHOD FOR PULSE (CHARGING A BATTERY AND FOR DRIVING. ‘OTHER DEVICES WITH A PULSE. ‘TECHNICAL FIELD ‘The invention relates generally to a hater pulse charger using soldsate device and method Wherein the current joing othe battery is pt constant. Te signal or curent is ‘momentarily swittinterupted a it lows through either the first channel, the charge phase, o¢ the seenné channel, the dischage phase. Tis two-phase eye allermates the signa ‘nthe to channels therehy allowing a potential charge in a ‘apactor to disconnect from is power soutee an instant before the capacitor discharges is stored portal energy into a battery for eceving the capacitor sstored energy. The capacitor then dscomects frm the battery ad recoanects (othe power source upon competion of the discharge phase, thereby competing charge-scharge cycle. The battery pulse charger can also drive devices, such as a motor sed beating clement, with pulses BACKGROUND AND PRIOR ART Preset day buttery chargers us a constant charge creat {in their eperation with oo momeatay disconnection of the signal or cutent ast flows either: 1) rom a primary eneray ~ source 1o the charger or 2) ftom the charger itself into batery foe receiving the charge, Some chargers ae eegulted {o aconstnt curentby any of several methods, while others ae constant and are not regulate. There are no batlery chargers cucently inthe art or available wherein there is 8 ‘momentary signal or curtent disconnection between the primary energy source and the ergs capacitors an iatant fore the capacitors dischinge the sored potential energy into a battery receiving the pulse charge. Noe are there any chargers in the ar that disconnect the chsrper from the battery reeviving the ebarge when the charger capacitors receive enety Lum the primary source. The momentary ‘current interuption allows the baltery a short rest period” and requires less enemy fom the primary energy sousce ‘while putting more energy into the battery ressiving the charge while requiring a shorter peri of time. SUMMARY OF THE INVENTION ‘One aspect ofthe invention cates toa solid-state device snl method for creating » pulse cumeat to pulse charge a butery or a bans of batteries in which a new and unigue method is wsed to increase and preserve for a longer perio of time the energy stored in the battery as compared to ‘coustan-cucent battery chargers. The device uses a timed pulse 1 create a waveform ia a DC pulse to be discharged {nto the battery teoviving the charge, ‘One embodiment ofthe Invention uses & mest foe dus stehing sch as a pulse width: modulator (PWM), for cumple, a Ingic chip SG3S21N BWM, and a means for ‘optical coupling toa bank of high-energy eapaciios wo tore timed intial pulse ebarge. This is the charge phase, or phase 1. The charged capacitor bank thea discharges the Stored high energy into the battery rcsiving the charge in time pulse, Just prior odiscarging the sored energy into the battery the capacitor bank is momentarily disconnected from the power source, thus completing the charge phase, ani thereby leaving the capacitor bank ss free-floating poletial charge disonanicted trom the primary enceey Source to then be discharged into the batery. The tansfe of energy from the capacitor bank wo the batery competes the Alischage phase, or phase TL The tworphise c¥ele now repeats sel. 2 ‘This embodinet ofthe batty pulse larger works by ‘eansferrng energy fom a soure, sich as an, AC source, an unfiltered DC source of high voltage tbe stored in ‘apacitoe or captetor bank, A switching regulator is se 2 timed pulse, for example, & one second pulse that i 180 degrees out of phase foreach set of switching functions. The firs function istobuild the charge inthe capacitor bank rom the primary energy source; he second function isto dson- eet the power source from the capacitor bak; the thin Tunetion ist dschange the red high voltage tothe batery ‘witha high voltage spike in timed pulse for example, a one second pulse; and the fourth function is to reconnect the apacine bank to the primary energy soure. The device ‘operates through & two-channel onoll Switching mechanism fof a gauging ro-gauging function wherein tho charger is Alisconnecied from sls primary energy source an slant before the pulse charger distrges the high-energy pulse fo ths hatery to be charged. AS the primary charging switch closes, the secondary discharging Switch opens, and vives in timed pulses to compete the two pase eyele. “The means for a power supply is varied with several ‘option avaiable asthe primary eneegy soure, For exumple, primary input energy may come from an AC source con: nected int the proper vollage (transformer; from an AC generator, from a primary input battery, trom solar cells, fiom a DC40-DC inverter, or ftom any other adaptable source of enerpy. fa transformer means the source of primary input energy, it ean be 4 Standard rectifying trans- Tormer used in power supply applications or any other teansformer meaas applicable to the desired function. For example, it can be # 120-volt to 45-volt AC step-down temsformer, and the reciier cam be # fllavave bridge of 200 vols at 20 amps, which is unftered when eonneced ‘he outpa ofthe transformer. The postive output terminal of the bridge recite is connected! 10 the drains of the parallel Jield-effet transistor, and the negative terminal iy con- ‘nected tothe capacitor bank negative ‘The Fle Feet Transistor (FET) switches can be IRF260 FERS or any other FET means to accomplish this Function, Alar in parallel to achieve the proper cren ofthe pases Ench FET may be connected through a Twat, (.5-hm ‘esistor wil a comme bus conaocton atthe souece. Al he FET gates may be connected through & 240-ohm resistor to 4 common bus. These also may be a2 Keohm resistor betwee the goes aid the devin bus ‘Ararsistor means, for example an MJEIS02$ trasisior, as driver forthe gates, drives the bus nd in tur, an optical ‘oupler drives te driver ustsistor though the fst channel ‘ist chagiag Switch is used to chage the capacitor bank, which acts as 2 DC poteatal source to the batery. The capacitor bank shen disconnected Irom the power retiet eiteuit, The pulse batery charger is then tansferred to second fel eile swith through the second channel forthe discharge phase. The discharge phase is driven by a ‘easistor, the transistor diven by an optical coupler. With 2 second or discharge switch on, the capacitor bank potential charge is discharged ito the battery to receive the charge. The battery receiving the charge is then disconnected from the pulse charger espscior bank wo repeat the eee. The pulse charger may have any suitable source of input power ‘inching 1) solar pares to ase the voltage tote capacitor bank; 2) wine generator; 3) a DC-to-DC inverter 4) an allerater, 5) an AC moor generator 6)a atc ure sucht 4384 igh voltage spark; and 7) othe devices that can raise ‘he potential ofthe eapaitor bank. In another embodiment ofthe invention, one can use the pulse charger ta drive a device such asa motor nr heating clement with pulses of energyUS 6,677,730 B2 3 [BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is « schematic drawing of » solidstate pulse charger according to an embodiment ofthe invention FIG. 2 isa schematic drawing of a conventional DC-0- DC converter hat canbe used to provide power to the pulse charger of FIG. 1 according an embodiment of the invention, FIG. 3 is a schematic drawing of 1 conventional AC power siply that canbe used to provide power tothe pulse sharger of FIG. Taeeording #0 an embodiment of the inversion, TIGS. 44-D are schematic drawings of other conven- tional power supplies that can he wsed to prove power to the pulse charger of FIG, 1 according to an embodiment of the invention FIG, $i block disgram of the solid-state pul charger of FIG. | acconing to an embodiment ofthe inversion. FIG, 68 diagram of a DC motor thatthe pulse charger of FIG. 1 can drive according to an embodiment of the FIG. 7 is diagram of « heating clemcat that the pulse charger of FIG. Lean dive scoring to an embodiment of the inverion DETAILED DESCRIPTION OF THE INVENTION, Aa embodiment ofthe present invention is a device and method for a solidstate puke charger that uses a stored potetil charge in capacitor bank. The solid-state pulse ‘hargcr comprises 2 combination of elements and circuitry to caplue and store available energy into a expacitor hank, ‘The stoned energy inthe capacitors thea pulse charge into the battery te charged. Tn one version af this embodiment, ‘ete ia ist momentary disconnection between te ebarget an theater receiving te charge during the charge phase Df the cycle, and a second momentary disconnection between the charger and the input eerpy souree during the discharge phase of the eye. ‘Asa surtng point and an arbitrary method in describing this device and method, the How of an loerca signal or ‘current wil be tracked fem the primary opt energy to final ‘Sorage im the battery receiving the pulse charge. FIG. 1 is schematic drawing of the solid-state pulse charger according to an embodiment of the invention. AS ‘thou in FIG, I, the primary input energy source ta the pulse charger is a power supply II, examples of which ae Shown in FIGS. 2, 3, 4A-4D. A 12-volthatery, asa low voltage energy source 12, drives a cual switching means of = ‘ontral such a 8 loge chip or « pulse width modulator (PWM) 13. Alternatively, the voltage from the power supply may bo converted oa vollage suitable power the PWM IB. Ihe PWM 13 may be an SG3S24N logic chip, and functions asan oseilatror mer to dive ‘with “onof” ste that are connected whet on either a first optical isolator 14, or ia the alternative, to a sesond ‘optical lator 15. The frst and second optical isolators 14 and 18 may be HDS optical isolators. When te loge chip 13 is connected to «fst channel, its disconnected from a second channel, this restiting in two phases of signal Aireetion; phase Ia charge phase, and phase I, a dischnge pase. When the lopie chip 13 i switched (6 the charge pase, the signal flows othe frst optical isolator 14 From te optical isolator 14, te signal continue its low through {first NPN por transior 16 that activates an Nechsavel MOSFET 18a and an N-channel MOSFET 185, Current channel output 5 4 lowing dough the MOSFETS 181 and 186 builds up a vollage aeross a cxpacitor bank 20, thereby complating the charge phase ofthe switching activity. The discharge pase begins when the logic ehip 13 is switched to the second chanel, with current flowing to the second aptca isolator 15 and thea through a second NPN power iarsistor 17, which setivates an Necheanel MOSFET 190 and an Nechanael MOSFET 19h, Ate the logic chip 18 clases the first channel and opens the second chante, the potential charge inthe capacitor bank 20 fee Hosting betwee the power supply IL, from which the capacitor bank 20 is now Aiseonnected, and then connected toa attery 2310 recive ‘ho charge. Iisa tis point in ime thatthe potential charge in the capacitor bank 20s discharged through high-energy pulse into the battery 22 or, a bank (ao shown) of baller, ‘The discharge phase is completed ouce the battery 22 receives the charge. The logic chip 13 then switches the second channel closed and opens the fist channel thus completing the ebarge-discharge eyce. The eye is epti= tive with the lagi chip 13 controling the signal diection io either channel one tothe capacitor bank, orto channel ‘vo oth battery 22 from the eapactor bank. The batery 22 |g given # momeatary rest period without 4 coatinious current during the charge phase. ‘The component values forthe described embodiment are as follows, Te reso 24,26, 4 have the following respective values: 4.7KD, 4.7KQ, 47KQ, 3300, 3300, 2K, 470, 470, 005047 W), 0050TW), 2KO, 479, 879, 0050(7 W), and O.OSQC7W). Tae potentiometer 46 is 10KQ, tb capacitor 48 is 2, andthe total capacitance of the eapacitor bank 20 is 0.132. The voltage of the batery 22 isberween 12-24 V, and the wotage ofthe power supply 11 24-50 V suc tha the supply vollge is approximately 12-15 V higher than the battery voltage Other embodiments of the puke charger aro comtem- plated. For example, the bipolar transistors 16 and 17 may be replaced with field-effect transistors, andthe teansistors 1&2, 18%, 19, anc) 196 may be replced wih bipolar ot insulated: gute bipolar (IGBT) trnsisiors. Furtemore, one can change the component values to change the eye time, the peak pulse voltoge, the amount of charge that the eapacitoe bank 20 delivers tothe battery 22, ee. In ation, the pals charger can have one or more than Wo transistors 1 and 18, and one or more than two tracsistrs 19a and 19, Sill referring. to FIG. 1, the operation of the above= discussed embodimert ofthe pulse charger is discussed, ‘To begin the fist pase of the eycle during which the apavitor bank 20s charged the logic etcit 13 deactivates the isolator 18 and activates the isolator 14. Typically, the circuit 13 is configured to deactivate the isolator 15 before frat the sometime that it activates the isolator 4 alough the cuit 13 may be configured to deactivate the isolator 1S ale it stivates the isolator 1, Next, the activated isolator 14 gonerates a base curent ‘hat activates the tansisior 16, which in tun generstes current tha activates the (anistrs 184 and 185. “The activated transistors Ik and 8b charge the capaci= tors in the bank 20 10a charge voltage equal o appeoxi= mately equal othe voltage ofthe power supply IL les the lowest threshold voltage ofthe transistors 180 an 188. To begin the second phase of the eycle during Which the capacitoe bank 20 pulse charges the batery 22, the logic circuit 13 deactivates the isolstor 14 and activates the {solsioe 18, Typically the circit 13 is eonigured to deac= tite the isolaler 14 belore of atthe seme time that itUS 6,677,730 B2 5 activates the isolator 18, although the cceut 13 may be ‘configured to deactivate the isolator 14 afer it atvates the ‘olatoe 1S Next, the activated isolator 1S generates a base cutent tat stivates the vansistor 17, which in tun generates a current that aetvates the teasisors 192 and 195, “Tho activated tanssiors 19s and 195 discharge the apacitors in the bank 20 at the hatery 22 unt the voltage css the bank 2081 is approximately equal tothe voltage cro the hatery 22 ps the lowest threshold wollage of the tearsisions 194 and 195, Allematively, the czcuit 13 can deactivate the isolaog 18 at a time hefove the bank 20 reaches this level of cischage. Because the resistances of the transistors 194 and 196, the ests and 40, and the battery 22 are relatively lo, the eapacitors inthe bank 20 discharge ater rapidly, thus delivering pub of current to charge the battery 22. For example, where the pulse charger includes components having the values listed above, th bunk 20 delivers a pulse of current bing a duration of ‘oc approximately of 100 ms and peak of or approximately of 250.4 FIG. 2 isa schematic drawing of a conventional DC- DC converter 30 that ean be used as the power supply HT of FIG. 1 accosding to aa embodiment of the invention. A DC“o-DC converter conversa ow DC voltage 10a higher DC voltage or vice-versa. Therefore, such a converter can convert Hw voltage into a higher Vollage thatthe pulse charger of FIG, [ean use to ebarge the expaciter bank 20 (FIG. 1). More specially, the converter 30 receives energy from a source BT such as a I2-volk bang. An optical ‘Solaoe seasor 33 contrls an NPN power trsasisior 31 which provides a cutent fo a primary col 36 af « power teansformer 32. A logic chip or pulse width, modblator (PWM) 34 alternately switches on an off an IRF260 sist Nechanel MOSFET A8< and an TRF260 sooond Nechsavel [MOFSET 35) such thit wher the MOSFET 380 is om the MOSFET 38) is off and vice-versa, Consequently, the switching MOSHETS 38< and 38b dive respective sections ofthe primary col 36 to generate an output volage across secondary coll 38, fullavave bridge eetiie 39 rectiies the voltage across the secondary oil 38, and tis wetted voltage is provided to the pulse charger of FIG, 1 Furthermore, the secondary coil 38 can be tapped o provide a lower voltage forthe PWM 13 of FIG. T such tbat the DC-o-DC converter 30 ean be wsed as both the power supply 11 and the low-voltage supply 12 of FIG. 1 FIG. 3 isa schematic drawing of an AC power supply 40 that can e used as bth the power supply HL and the power supply 12 of FIG. 1 acconling to au embodiment of te fnvention, The power input 2 to the supply 40s 120 VAC. ‘fis tansfomer 44 and fll-wavereclfer 46 compose the supply LL anda second transformer 48, fulwave rectifier 50, and voltage regulator 82 compese the supply 12, FIGS. 4A-D are schematie drawings of varios conven: tions primary energy input sources that can he used 8 the supply HL andor the supply 12 of FIG, 1 asvoeding © a0 embealiment of the vention. FIG. 4A is a schematic drawing of serially coupled bateies FIG, 4B is reberatic drawing of serially coupled solar cells, FIG. 4C isa sehe- matic draving of aa AC generator and FIG. 4D is a schematic drawing of a DC generator FIG. $2 lock diagram of the solid-state pulse charger of FIG, 1 according to an embodiment of the invention, Block A is the power supply 11, which can be suy suitable ower supply suchas these shown in FIGS. 2,3, AAD. Black B is the power supply 12, which can be say suitable 6 power supply such asa 12 VDC supply othe supply town in FIG, 3. Block C is the PWM 13 and its porpheral components. Block D isthe charge switch that includes the First apical isolator chip 14, the fst NPN’ power transistor 16 the frst set of two Nchangel MOSFETS 18 and 185, and their peripheral resistors. Block I isthe capacitor bank 20, Block Fis the discharge switch that includes te second ‘optical isolator ei 1, the seooud NPN power easisor 17, w the second set of two Nechannel MOSFETS 194 and 196, and their peripheral resisors. Block G is the battery 22 that is being pulse chargod ‘Aunique feature that distinguishes one embodiment the shove-deserbed pulse charger from conventional chargers is the method chasing the batery with pulses of cureat instead of wil 4 continuous evirent. Consequently, the battery is given a rest period betwoen pulses FIG. 6 iss dixgram of « DC motor 60 that the pulse chargee of FIG, I can drive acoording to an embodiment of the invention. Speifcally, one ean conneet the moto 60 in place ofthe batery 22 (FIG. 1) such thatthe pulse changer {aves the motor with pulses of erent. Allhough one need ‘ot modify the pub charger to crive the motor 60, ce can ‘modify the pulse charger to make it more efficient for Arving the motor. For example, one can modify the valies ofthe resistors peripheral to the PWM 13 (FIG. 1) to vary the width and peak of the drive pulses fom the capacitor ink 20 (FIG. 1). FIG. 7is a diageam ofa beating element 70, such as & Ayer of waterbeating clement, tha the pulse ebarger of FIG. Lan drive acooding to an embodiment of the iaven- ‘ion. Specifically, one can connect the beating element 70 in place ofthe batery 22 (FIG. 1) sue that te pulse charset ‘rivesthe elemeat with pulses of cute. Although ove need not modify the pulse chagerto drive the clement 70, one can ‘modify tho pulso charger to make it more efficent for Arving the elect. Far example, one can modily the vakics ofthe resistors peripheral tothe PWM 13 (HG. 1) to vary ‘he wiih and peak of ihe drive pulses feom the capacitor bank 20 (FIG. 1). In the embodiments discussed above, specifi electronic clements and components ace used. However, itis known that a varity of avilable trsasisios, resistors, capacitors, teansformers, timing, components, optical isoltors, pulse ‘wid modulators, MOSFET, and other electronic compo eats may be used in varcty of combinations to achieve an equivalent result Finally lliough the invention has been described with reference of particular means, materials and ‘embodiments, itis tobe understood thatthe invention is not limited othe particulars disclosed and extends toll equva- Jents within the scope of the claims, ‘What is claimed is 1. Asoldstate pulse battery charger where input power from a primary source is stored asa potential charge in & capacitor bank, said capacitor bank then disconnected from Si input power source through a dua ming means sid ‘apacioe tem connected oa battery to ceive the potential charge, the charge then discharged into sid batery from sid capacitor, said batery then disconnected fom said capacitor though said dual timing mans, said capacitor ‘ha re-eoaneced to sa input power source completing & to phase switching eyele comprising:US 6,677,730 B2 1 42 cans for providivg input powers a means for timing a signal and a curet flow in wo phases, «charge phase and a discharge phase, through tithe ist chanel output for charging sad capacitor hank, ora second channel output for discharging stored nergy from said capacitor into sai ater, the current flowing from sid first channel oxipat theough a Sst ‘optical isolator and through a first NPN power ttanssior, sai fs tansisoraetivating a fist pic of [N-channel MOSPE'S with voltage store asthe poten ial charge in so capacitor bank, sad capacitor dis- ‘connecting fom said input power means by said timing Sail means for ising cient Dow conaceting wo sid second channel output, eurent flowing fom Said sec ‘ond channel through second optical isolator and through a second NPN power transistor, said second teansistor setivating a second pair cf Nechanoel MOSFET, said eapucitor connecting to said battery, te potemial change discharging into said battery, said timing means disconnecting said expactor trom said hater, and connecting sail capacitor to said power 2. The pulse charger of claim 1 wherein the means for ™ providing input power is an AC volage current, 13. The pulse charger of claim 1 wherein the means for providing input power is atin: 4 The pulse charger of claim I wherein the means for providing input power is a DC generator ‘5. The pulse charger of clin wherein the means for providing input poser is an AC generator, 6. The pulse charger of claim 1 wherein the means for providing input power isa sola cll "7. The pulse charger of claim 1 wherein the means for providing input power is a DC-Ae-DC inverter 8. Ameo of making a solid-state pulse hatery ebayer ‘wherein input poser from a primary soute is stored a5 potential charge in &expactor bank, seit eapscitor discon Foctd from sad input power scarce through a dal timing means, sad capacitor connected to a batery to receive the potemial change, said charge discharged ino ssid baery from said capacitor, seid battery disconnected from sid capacitor through said dual timing means, said capacitor feconnected to sid input power source completing 4 Wo phase cycle comprising the steps of 2. providing a source of input power; ', connecting 4 means for dual-timing ssid charger to control a signal or cutent flo through first channel output comprising a fist optical isolator, a frst NPN § power transistor and a first psi of N-channel MOS FERS «capturing energy from said curent and storing said eoergy in said capacitor bank thereby ching said ceupacitor, 4. switching the fow of said curent using said timing device to second channel comprising a second optical ‘solar, 2 Seanad NPN power Iransisior and x seoond pair of N-channel MOSFET, thus disconnecting said. °° eapacitor from said power souree and connecting sid capacitor to sad batery; «©. dschorging the potential charge im said battery ‘switching the flow of the current using si’ timing device to sid power source and sid fst chanael to complete sid eye 8 9. The pulse charger of claim 8 whereia the means for providing input power is an AC voltage ou 10, The pulse charger of claim 8 wherein the means for providing input power isa battery. 11, The puke charger of clsim 8 where the means for providing input power is a DC generator 12, Ibe pulse charger of elaim 8 wherein the means for providing inp paver is an AC general. 13. The pulse charger of claim 8 wherein the means for providing input power isa solar ell 14. The pulse charger of claim 8 wherein the means for providing input power is a DCo-DC inverter. 18. Abaltery changer, comprising: a supply node; 8 charge node; s cbarge-storage devioe; and A switch circuit coupled tothe supply and the charge toces an he charge-storage device, the swith circuit operable to, charge te charge storage device and prohibits batery- ‘barge current fem Mowing into the charge node ring «batery-rest period and allow the buttery-charge curent to flow fom the charge-sorage device into the charge node during a batery-charge period, and prohibit the battery-charg current from flowing into the charge node during a batery-et peri, 16. The battery charger of claim 15, further comprising: capacitor coupled to the swite circus and ‘whereia the witch cireuit s operable to, alow the batiery-charge eucent to from the eapaitor ito the charge node dusing the batery-charge peti, and charge the capacitor during the batery-est perio 17. Aamethod, comprising: charging a hatiery during a frst period of «charge eye; snd scumulating charge in «charestrage device snd p= Iubiting the charging of the batery during a second peti ofthe charge eye 18. The method of eis 17 wherein targing the hater compris charging the batery with 4 charg eureat dug te ist period of the cbarge yet; and prohibiting te chasing of te battery comprises prhid- iting the charge current fom owing into the hatery during the second perio ofthe charge eye 19. The method of esis 17, wherein caging the battery comprises discharging the chang ‘oraye deve he baer during the is peril of the charge eye, and _ohibiting the charging of the battery comprises waco pling the chargesorae device eam the ater ding the second prod ofthe charge eye 20, The mettod of claim 17 wherein the eharge-storage device compres capacitor. 21. The methed of claim 1? wherein the length of the second pri teat to evel of charge accumlited in the charge storage device.US 6,677,730 B2 9 22, A avo, compeising dlischaging a ehurge-storage deve iato a battery daving 4 fst pool of batlry-charg evel; and ‘uncoupling the charge-storage device rom the hatlery and charging the chargestorage device during a sesond petiodl ofthe batery-charge eye 23, The method of claim 22 wherein uncoupling the charge-storage device comprises uncoupling te bare onage deve from the batery before commencing charg ing of the charge-storage device 10 24, The metod of claim 22 wherein uncoupling the charge-storage uncoupling the chargestrage device from the battery ater commencing charging of the charg-storage device, 25. The method of elim 22 wherein uncoupling the charge-storage devi comprises simultaneously uncoupling te charge-storage device fom te battery and commencing charging of the charge-siorage device