Ali Suleman

22K-4060
BS AI (2A)
Digital Logic Design (LAB#3)

Task 1: OR, AND, NOT Gate using NOR gate.

i. OR GATE

Truth Table (OR GATE)

A B A+B (A+B)’ ((A+B)’+ ((A+B)’+(A+B)’)’
(A+B)’)
0 0 0 1 1 0
0 1 1 0 0 1
1 0 1 0 0 1
1 1 1 0 0 1

ii. AND GATE

Truth Table (AND GATE)

A B (A+A)’ (B+B)’ ((A+A)’+ ((A+A)’+(B+B)’)’
(B+B)’)
0 0 1 1 1 0
0 1 1 0 1 0
1 0 0 1 1 0
1 1 0 0 0 1

iii. NOT GATE

Truth Table (AND GATE)

A (A+A) (A+A)’
0 0 1
 1 1 0

Task 2: OR, AND, NOT Gate using NAND gate.

i. OR GATE

Truth Table (OR GATE) AND GATE

A B (A.A)’ (B.B)’ ((A.A)’.(B.B)’) ((A.A)’.(B.B)’)’
0 0 1 1 1 0
0 1 1 0 0 1
1 0 0 1 0 1
1 1 0 0 0 1

ii. AND GATE

Truth Table (AND GATE)

A B A.B (A.B)’ ((A.B)’.(A.B)’) ((A.B)’.(A.B)’)’
0 0 0 1 1 0
0 1 0 1 1 0
1 0 0 1 1 0
1 1 1 0 0 1

iii. NOT GATE

Truth Table (NOT GATE)

A (A.A) (A.A)’
0 0 1
1 1 0
 Lab Assignment Tasks
QUESTION 1
Logic Expression:
[((AB+CD)’+B’).C’]
Circuit Diagram

Truth Table
(AB+CD)
A B C D AB CD AB+CD B’ (AB+CD)’+B’ C’ ((AB+CD)’+B’).C’
’
0 0 0 0 0 0 0 1 1 1 1 1
0 0 0 1 0 0 0 1 1 1 1 1
0 0 1 0 0 0 0 1 1 1 0 0
0 0 1 1 0 1 1 0 1 1 0 0
0 1 0 0 0 0 0 1 0 1 1 1
0 1 0 1 0 0 0 1 0 1 1 1
0 1 1 0 0 0 0 1 0 1 0 0
0 1 1 1 0 1 1 0 0 0 0 0
1 0 0 0 0 0 0 1 1 1 1 1
1 0 0 1 0 0 0 1 1 1 1 1
1 0 1 0 0 0 0 1 1 1 0 0
1 0 1 1 0 1 1 0 1 1 0 0
1 1 0 0 1 0 1 0 0 0 1 0
1 1 0 1 1 0 1 0 0 0 1 0
1 1 1 0 1 0 1 0 0 0 0 0
1 1 1 1 1 1 1 0 0 0 0 0
 QUESTION 1
Logic Expression:
[((AB+CD)’+B’).C’]
Circuit Diagram

Truth Table
(AB+CD)
A B C D AB CD AB+CD B’ (AB+CD)’+B’ C’ ((AB+CD)’+B’).C’
’
0 0 0 0 0 0 0 1 1 1 1 1
0 0 0 1 0 0 0 1 1 1 1 1
0 0 1 0 0 0 0 1 1 1 0 0
0 0 1 1 0 1 1 0 1 1 0 0
0 1 0 0 0 0 0 1 0 1 1 1
0 1 0 1 0 0 0 1 0 1 1 1
0 1 1 0 0 0 0 1 0 1 0 0
0 1 1 1 0 1 1 0 0 0 0 0
1 0 0 0 0 0 0 1 1 1 1 1
1 0 0 1 0 0 0 1 1 1 1 1
1 0 1 0 0 0 0 1 1 1 0 0
1 0 1 1 0 1 1 0 1 1 0 0
1 1 0 0 1 0 1 0 0 0 1 0
1 1 0 1 1 0 1 0 0 0 1 0
1 1 1 0 1 0 1 0 0 0 0 0
1 1 1 1 1 1 1 0 0 0 0 0
 QUESTION 2
Logic Expression:
((A’B)’+C)’
Circuit Diagram

Truth Table

A B C A' A'B (A'B)' (A'B)'+C  F

0 0 0 1 0 1 1 0
0 0 1 1 0 1 1 0
0 1 0 1 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 0 1 1 0
1 0 1 0 0 1 1 0
1 1 0 0 0 1 1 0
1 1 1 0 0 1 1 0
 QUESTION 3
(a) Logic Expression: (A + B)(B + C)
Circuit Diagram

Truth Table
A B C A+B B+C (A+B)(B+C)
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 1 1
0 1 1 1 1 1
1 0 0 1 0 0
1 0 1 1 1 1
1 1 0 1 1 1
1 1 1 1 1 1
(b) Logic Expression: (AB + C)D
Circuit Diagram

Truth Table
A B C D A.B A.B+C (AB+C).D
0 0 0 0 0 0 0
0 0 0 1 0 0 0
0 0 1 0 0 1 1
0 0 1 1 0 1 1
0 1 0 0 0 0 0
0 1 0 1 0 0 0
0 1 1 0 0 1 1
0 1 1 1 0 1 1
1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 1 1
1 0 1 1 0 1 1
1 1 0 0 1 1 0
1 1 0 1 1 1 0
1 1 1 0 1 1 1
1 1 1 1 1 1 1

(C) Logic Expression: ((A + B’C)(A + BC))’

 Circuit Diagram

Truth Table
((A + B’C)(A +
A B C B' B'C BC A+B'C A+BC F
BC))
0 0 0 1 0 0 0 0 0 1
0 0 1 1 1 0 1 0 0 1
0 1 0 0 0 0 0 0 0 1
0 1 1 0 0 1 0 1 0 1
1 0 0 1 0 0 1 1 1 0
1 0 1 1 1 0 1 1 1 0
1 1 0 0 0 0 1 1 1 0
1 1 1 0 0 1 1 1 1 0
(D) Logic Expression: A’BC + AB’C + ABC’ + (ABC)’

Circuit Diagram

A B C A' B' C' A'BC AB'C ABC' ABC (ABC)' F

0 0 0 1 1 1 0 0 0 0 1 1
0 0 1 1 1 0 0 0 0 0 1 1
0 1 0 1 0 1 0 0 0 0 1 1
0 1 1 1 0 0 1 0 0 0 1 1
1 0 0 0 1 1 0 0 0 0 1 1
1 0 1 0 1 0 0 1 0 0 1 1
1 1 0 0 0 1 0 0 1 0 1 1
1 1 1 0 0 0 0 0 0 1 0 0
(d) Logic Expression: (A’ + BC)’
Circuit Diagram

Truth Table
A B C A' B.C A'+BC (A'+BC)'

0 0 0 1 0 1 0

0 0 1 1 0 1 0

0 1 0 1 0 1 0

0 1 1 1 1 1 0

1 0 0 0 0 0 1

1 0 1 0 0 0 1

1 1 0 0 0 0 1

1 1 1 0 1 1 0
 QUESTION 4
(a) Logic Circuit

Output:
(AB+CD)
A B C D AB CD AB+CD B’ (AB+CD)’+B’ C’ ((AB+CD)’+B’).C’
’
0 0 0 0 0 0 0 1 1 1 1 1
0 0 0 1 0 0 0 1 1 1 1 1
0 0 1 0 0 0 0 1 1 1 0 0
0 0 1 1 0 1 1 0 1 1 0 0
0 1 0 0 0 0 0 1 0 1 1 1
0 1 0 1 0 0 0 1 0 1 1 1
0 1 1 0 0 0 0 1 0 1 0 0
0 1 1 1 0 1 1 0 0 0 0 0
1 0 0 0 0 0 0 1 1 1 1 1
1 0 0 1 0 0 0 1 1 1 1 1
1 0 1 0 0 0 0 1 1 1 0 0
1 0 1 1 0 1 1 0 1 1 0 0
1 1 0 0 1 0 1 0 0 0 1 0
1 1 0 1 1 0 1 0 0 0 1 0
1 1 1 0 1 0 1 0 0 0 0 0
1 1 1 1 1 1 1 0 0 0 0 0