Juned Altaf Mulani Education

Mtech/VLSI & Embedded System,

Physical Design Engineer
junaidmulani11@gmail.com 7972184485
https://www.linkedin.com/in/juned-mulani-
b73821169
Profile
"As a current intern at Intel in the Physical Design domain,
I am passionate about the VLSI industry and eager to
secure a full-time opportunity to further my professional
development and contribute to the advancement of
technology. With a strong background in relevant skills. I
am confident in my ability to bring value to any team and
drive success in a fast-paced and dynamic environment."
Professional Experience
Graduate technical Intern, INTEL INDIA
08/2022 – present | Bangalore, India
Did partition convergence from RTL to GDS, Logic
•
Delhi Technological University
06/2021 – present | Delhi, India
CGPA: 8.20 (Upto 3rd semester) Aug 2021 -
Present
Bachelors in Engineering/Electronics &
Telecommunication., DY Patil Institute of
Engineering Management & Research / Pune
University
06/2015 – 06/2019 | Pune, India
CGPA: 8.0 June 2015 - June 2019
Skills
C , Verilog HDL, TCL ,PYTHON languages,
Tools ((Xilinx) Vivado, LT SPICE, Synopsys
Fusion compiler ,Primetime),
Software (Keil (MDK), Proteus, MPLAB)
Projects
Cache controller using Verilog,
Implementation of 2 level cache controller

synthesis. Place and route, CTS, Static timing analysis,

using verilog hdl on Xilinx Vivado tool and
ASIC flow.
verifying caching via simulation.
Performed experiments on block which aimed for
•

power, area and timing optimization. Power and Design Analysis of 6T SRAM, 9T
Developed TCL scripts for efficient implementation of
•

SRAM and Power Efficient Binary Content

design modifications and implemented automation in Addressable Memory Core Cam Cells.,
the flow process. Implemented and designed 6T SRAM ,9T SRAM
Performed and understanding of Unified power format -
•

& PEBCAM Cells using Lt spice tools and

VCLP, RC Extraction, Formal equivalence, Caliber and LV different design of PEBCAM cell for low power
for block. applications using adiabatic logic.
Exposure to power analysis EDA tools such as PTPX.
•

Implementation of DFF using various

Languages techniques for low power application., The
project consist of simulation of SETFF, DETFF
English,Hindi,Marathi and TSPC-FF on LTSPICE and their power has
been compared.
Courses
PWM of Particular Duty Cycle using
DIGITAL IC DESIGN Verilog., This project is implemented on
Vivado tool. In this PWM signal of different
DIGITAL ELECTRONICS duty cycle has been generated.
COMPUTER ORGANIZATION AND ARCHITECTURE Seed Sowing Apparatus., This project aims
at bringing automation in the field of sowing
STATIC TIMING ANALYSIS
process in agriculture and also improving
ASIC DESIGN FLOW efficiency.

RTL DESIGN
Awards
Applied for patent for project of “Seed
Sowing Apparatus”. Patent Application No-
201821038225 A

Won project competition at my college

Gate2021 qualified with 97.67 percentile.