Introduction to AMD Vivado™
AMD Tools and Frameworks
AMD Vitis™ AI
Enables the implementations of
machine learning inference, using
Tensor Flow, Caffe and PyTorch
*Requires a SoC/RFSoC/AMD Alveo™
PYNQ
Python framework for rapid
prototyping on SoC/RFSoC/Alveo
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AMD Vitis™ Petalinux
Embedded and accelerated SW Embedded Linux solutions
development. Used to develop
software solutions for
MicroBlaze™, Arm® R5, A9, A53
and A72.
AMD Vitis™ / Vivado HLS AMD Vivado™
High-Level Synthesis (HLS) tool Design capture and
supporting C/C++/OpenCL implementation for the base
platform
2
AMD Vivado™ Overview
• Vivado is the foundation of all design
and higher level tools
• Vivado enables us to capture ✓ Simulate designs using
designs using VHDL or Verilog Vivado Simulator
✓ Synthesize, place and
• Large IP library to accelerate our route the design
designs ✓ Generate power
estimations
• Integrates Vivado / Vitis HLS IP
✓ Create AMD support
cores architecture

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 AMD Vivado™ Overview
FPGA Implementation Flow

Synthesis – Translates the HDL design into a series of logic equations

which are then mapped onto the resources available in the target FPGA.

Place – The logic resources determined by the synthesis tool are placed at We can control the flow
available locations within the target device.
implementation settings
by using constraints (XDC
file) and implementation
Routing – The placed logic resources in the design are interconnected strategies.
using routing and switch matrixes to implement the final application.

Bit File – The generation of the final programming file for the target FPGA.

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AMD Vivado™ IP Integrator
AMD Vivado™ IP Integrator (IPI)
Create system-level designs
• Instantiate and interconnect IP cores

• IP-centric design flow

• Plug-and-play IP
• Vast IP catalog

• Accelerates
• Integration
• Productivity

• Example applications
• Embedded
• DSP
• Video
• Analog
• Networking

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AMD Vivado™ IP Integrator:
Intelligent IP Integration
• Automated IP subsystems

• Block automation for rapid design creation Hierarchy

Support

• One click IP customization System Hierarchy

View
Interface Connections with
• Board aware Live DRCs

• Support all 7 Series FPGAs and AMD Tcl Console

Zynq™ SoCs
Extensible IP Catalog
• Built-in presets, accelerating design
creation

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AMD Vivado™ IP Integrator:
Intelligent IP Integration
Correct-by-construction
• Interface level connections

• Extensible IP repository

• Real-time DRCs and parameter

propagation / resolution

• Designer assistance

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Demonstration
AMD Vivado™
Clock Domain Crossing
Clock Domain Crossing
Ideal solution uses one clock and the entire design is synchronous.
BUT!

Modern devices have multiple clocks to address different clock domains e.g.
ADC / DAC clocks, source synchronous interfaces.
Brings with it the need to transfer data, and signals safely and reliability
between the clock domains.

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Metastability
One issue which can arise with incorrect domain crossing is metastability.

This can lead to corruption of data or incorrect behaviour.

Occurs when a flip flops set up or hold time is violated.

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Metastability

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Clock Domain Crossing
Several techniques can be used depending upon what needs to be transferred:

• Two stage synchroniser – Ideal for single bit data

• Grey code synchroniser – Encodes data bus in grey code and transfer between domains
– Ideal for counters as input to be converted to grey code can only decrement /
increment by one from previous value

• Hand shake synchroniser – Transfers data bus between two clock domains using
handshake signals

• Pulse synchroniser – transfer pulse from one clock domain to another

• Asynchronous FIFO – transfers data from one domain to another, useful for high
throughput / burst transfers

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Clock Domain Crossing
To support reset functionality across clock domains we may need the
following synchronisers structures.

» Asynchronous Reset Synchroniser – enables asynchronous assertion and

synchronous de-assertion.

» Synchronous Reset Synchroniser – synchronises a synchronous reset to another

clock domain.

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CDC in AMD
AMD Parameterised Macros (XPM) – provide CDC structures
Use registers optimised for CDC in the fabric
» Registers located close together and have small set up and hold windows
Described within UG953 Libraries Guide
Described within UG 974 UltraScale™ Architecture Libraries

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 AMD Vivado™ CDC Report
Following Synthesis – in TCL window run the command report_cdc

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 AMD Vivado™ Timing Analysis – Clock Interaction

Generated from Flow Navigator when implementation is

open.

Yellow show unrelated clock – Indicates CDC issues as well.

(Means we need to define constraints.)

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 AMD Vivado™ Timing Analysis – Inter clock Issues

Detailed path report – Source and Destination Clocks different

If you forget to report_cdc

following synthesis. CDC issues
will be apparent in the timing
report if we have not correctly
addressed the constraints.

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 AMD Vivado™ Flow - Schematic
Engineers can use
information
provided in the text
report to navigate
to the schematic to
understand where
CDC might be.

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Strategies and Reports
AMD Vivado™ – Strategies
• Strategies are a defined set of Vivado implementation feature options that control the implementation
results.

• These strategies can be used to explore:

• Timing Performance (e.g., Performance_Explore)
• Congestion - Strategies to reduce routing congestion in areas of the design
• Area - Optimize for area
• Power – Optimize for power
• Quick Flow – Reduced implementation time

We should always try to achieve timing closure.

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AMD Vivado™ – Reports

• Vivado provides several reports which can be used to help focus in on performance
issues in the design:

• Design Analysis Report – Provides information on design timing, congestion, and

complexity of design.

• Quality of Result Report – Provides overall design assessment and methodology

check – QOR can also make suggestions to fix issues in the design.

• Both are very useful to achieve timing closure of the design.

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AMD Vivado™ – Design Analysis Report
Design Analysis Report provides information on:
• Timing – Provides information on the timing and
physical characteristics of timing paths.
• Complexity – Provides information on routing
complexity and LUT distribution.
• Congestion – Provides information on routing
congestion.

No need to run full implementation.

Generate report after running opt_design
command in TCL.

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AMD Vivado™ – Design Analysis Report
• Along with timing information, DAR can provide information on design complexity
including indicating design risk for implementation.

• Low Risk Rent Analysis <0.65 and Fan Out <4.

• High Risk Rent Analysis >0.65 <0.85 and Fan Out >4 % <5 – May be difficult to place
without congestion.

• Very High Risk, Rent Analysis >0.85 and Fan Out >5 – May not implement

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AMD Vivado™ – Quality of Result

• Quality of Result Assessment (QoRA) and Quality of Result Suggestions

(QoRS) since both provide information that can be used to achieve timing
closure.

• Like Design Analysis Report – Run initially after doing the Opt.

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AMD Vivado™ – Quality of Results

SCORE MEANING CORRECTIVE ACTION

1 Design will not implement Redesign RTL / HLS modules
2 Design will implement timing Review constraints & RTL HLS
problems
3 Design Runs have a small Use QoR suggestions, review
chance of success clocking, ML strategies
4 Design should meet timing if Use QoR suggestions, ML
directives used strategies
5 Design will implement without Run Implementation
timing issues

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AMD Vivado™ – Quality of Results

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Reducing Run Time
Design Check Points

• AMD Vivado™ uses a physical design

database to store placement and routing
information.

• Design checkpoint files (.dcp) allow you to

save and restore this physical database at key
points in the design flow.

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AMD Vivado™ – Reducing Compile Time
• Implementing a FPGA design can take a considerable time > 1 Hour.

• Iterating the design can therefore be an issue, there are several options which can
reduce the implementation time both in synthesis and place and route.
Synthesis

Global Performs a traditional top-down synthesis of the entire design. Selecting this
option takes the longest time because you need to re-run the entire synthesis
every time you make a change.
Out of Context Per IP Runs synthesis and creates a Design Check Point (DCP) for every individual
IP block within your design. These check points are then collected into a
black-box at the top-level implementation. Using this option means that only
the blocks you change need to be re-synthesized, which saves time. OOC-IP
also creates an IP customization file (XCI) for each IP block, allowing for
customization and OOC XDC files. OOC-IP is the default setting for synthesis
within Vivado. This option applies to all IP within the block diagram.
Out of Context Per Block Diagram Like the OOC-IP option however this option allows you to define the entire
block diagram as OOC.

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AMD Vivado™ – Reducing Compile Time
• Incremental synthesis can also be used when
the changes are small.

• Write out incremental synthesis to the post

synthesis design check point.

• Selecting incremental synthesis then provides

two options:
• Automatically use previous DCP
• Use a defined DCP

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AMD Vivado™ – Reducing Compile Time
• Incremental implementation allows use of
Design Check Point as the starting point.

• Preserves QoR predictability by reusing

prior placement and routing from a
reference design.

• Speeds up place and route run time or

attempts last mile timing closure.

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