1 2 3 4 5 6 7 8

00
PCI-EXPRESS EDGE CONNECTOR

0 M
A +3.3V_BUS
A

RD 17 SI 17 16 15 14 10 8 7 1 +3.3V_BUS
+3.3V_BUS

+3.3V_BUS +12V_BUS +12V_BUS

+0.95V

2
+3.3V_BUS +3.3V_BUS 16 15 14 13 R1022
14 10 8 7 1 +3.3V_BUS 1 +12V_BUS 16 15 14 13 11 8 1 +12V_BUS +0.95V_PG

(C 96 C
+3.3V_BUS
17 16 15 14 10 8 7 1 1+3.3V_BUS
17
16
15
14
10
7
8 +3.3V_BUS 17 16 15 11 8
+3.3V_BUS 17

3
10K 10 8 7 1 +3.3V_BUS
+3.3V_BUS

1
1
16 15 14
17 16 15 14 10 8 7 1 +3.3V_BUS
R1021 1 Q1004 17 16

1
1K UNNAMED_1_NPN_I129_C MMBT3904 8 7 1 +3.3V_BUS

3
MPCIE1 15 14 10
R1002 2 3
Q1002

1 2

5
45.3K BSH111 B1 A1 PRESENCE 1
R1001 1% +12V PRSNT1_A1 1 Q1003
45.3K B2 A2 UNNAMED_1_CAP_I127_A MMBT3904
+12V +12V

2
1%

1
)2 7 ON
DNI B3 +12V +12V A3 C1021

2
B4 A4 0.1uF
GND GND 6.3V C1011

2
SMBCLK 1 2 SMCLK B5 A5 0.1uF
5,17 IN R1004 SMCLK JTAG2 U4B

2
6.3V
SMBDATA 0R 1 2 SMDAT B6 A6 JTDIO_LOOP NC7SZ08P5X_NL
5,17 BI R1003 SMDAT JTAG3 C1012 R1005

3
0R B7 A7 0.1uF 10K
GND JTAG4 6.3V
DNI
B8 +3.3V JTAG5 A8 U4A

1
+3.3V_BUS B9 JTAG1 +3.3V A9 1
2 3
Q1001 B10 3.3Vaux +3.3V A10 4 PERST#_BUF
2,16
BSH111
OUT
17 16 15 14 10 8 7 1 +3.3V_BUS B11 A11 2

F
WAKE_ PERST_

0
Mechanical Key
B12 RSVD_B12 GND A12 NC7SZ08P5X_NL

1
B13 GND REFCLK+ A13 PCIE_REFCLKP
2 PERST#
OUT
PETP0_GFXRP0 B14 A14 PCIE_REFCLKN

吳 13 jo ID
2 OUT PETp0 REFCLK- OUT 2
2
PETN0_GFXRN0 B15 PETn0 GND A15
OUT DNI
B16 GND PERp0 A16 PERP0
2
IN 0R
B17 PRSNT2_B17 PERn0 A17 PERN0
2 1
R1007 2
IN
B18 GND GND A18
2
PETP1_GFXRP1 B19 PETp1 RSVD_A19 A19 Place R61 in U100
OUT
2
PETN1_GFXRN1 B20 PETn1 GND A20
OUT
B21 GND PERp1 A21 PERP1
2
IN
B B22 GND PERn1 A22 PERN1
2 B

積 09 ne EN
IN
2
PETP2_GFXRP2 B23 PETp2 GND A23
OUT
2
PETN2_GFXRN2 B24 PETn2 GND A24
OUT
B25 GND PERp2 A25 PERP2
2
IN
Place these caps as close to the PCIE B26 GND PERn2 A26 PERN2
2
IN
CAP CER 10UF 20% 16V X5R
2
PETP3_GFXRP3 B27 PETp3 GND A27
OUT
connector as possible
2
PETN3_GFXRN3 B28 PETn3 GND A28
OUT
(1206)1.8MM H MAX B29 GND PERp3 A29 PERP3
2
IN
B30 RSVD_B30 PERn3 A30 PERN3
2
IN

源 05 pe TI
B31 PRSNT2_B31 GND A31
B32 GND RSVD_A32 A32
16 PETP4_GFXRP4 B33 A33
+12V_BUS 2 OUT PETp4 RSVD_A33
14
11 2
PETN4_GFXRN4 B34 PETn4 GND A34
OUT
1 +12V_BUS B35 GND PERp4 A35 PERP4
2
IN
C1001

8
B36 GND PERn4 A36 PERN4
2
13 IN
15 2
PETP5_GFXRP5 B37 PETp5 GND A37
OUT
2
PETN5_GFXRN5 B38 PETn5 GND A38
OUT

01 i( AL
change to 0805 B39 GND PERp5 A39 PERP5
2
IN
10uF_16V

B40 GND PERn5 A40 PERN5

2
IN
2
PETP6_GFXRP6 B41 PETp6 GND A41
OUT
2
PETN6_GFXRN6 B42 PETn6 GND A42
OUT
+12V_BUS B43 GND PERp6 A43 PERP6
2
IN
C0805_67 B44 GND PERn6 A44 PERN6
2
IN
16 15 14 13 11 8 1 +12V_BUS
2
PETP7_GFXRP7 B45 PETp7 GND A45
OUT
2
PETN7_GFXRN7 B46 PETn7 GND A46
OUT
1

B47 GND PERp7 A47 PERP7

2
IN
B48 A48

(0
PRESENCE PERN7
C1002 C1003 1 PRSNT2_B48 PERn7
IN 2
0.15uF 0.15uF B49 A49
GND GND

裴
16V 16V
VVVV302-01S B50 PETp8 RSVD_A50 A50
2

B51 PETn8 GND A51

B52 GND PERp8 A52
+3.3V_BUS B53 GND PERn8 A53
B54 PETp9 GND A54
17 16 15 14 10 8 7 1 +3.3V_BUS CAP CER 10UF 10% 6.3V X5R B55 PETn9 GND A55

00 RM 亮
(0805)1.4MM MAX THICK B56 GND PERp9 A56
1

B57 GND PERn9 A57

C1004 B58 PETp10 GND A58
10uF B59 A59
C 6.3V PETn10 GND C
B60 GND PERp10 A60 SYMBOL LEGEND
2

B61 GND PERn10 A61

B62 PETp11 GND A62
+3.3V_BUS B63 PETn11 GND A63 DNI DO NOT
B64 A64

11 A工 樂
GND PERp11 INSTALL
17 16 15 14 10 8 7 1 +3.3V_BUS B65 GND PERn11 A65
B66 PETp12 GND A66 # ACTIVE
1

B67 PETn12 GND A67 LOW

C1005 C1006 C1007 B68 GND PERp12 A68

0.1uF 1uF 0.01uF B69 A69
GND PERn12 DIGITAL
6.3V 6.3V 10V
B70 PETp13 GND A70 GROUND
2

B71 PETn13 GND A71

B72 GND PERp13 A72 ANALOG

60
B73 GND PERn13 A73 GROUND
B74 A74

)
PETp14 GND
B75 PETn14 GND A75 BUO BRING UP

+12V_BUS B76 GND PERp14 A76 ONLY

程
B77 GND PERn14 A77
16 15 14 13 11 8 1 +12V_BUS B78 PETp15 GND A78
B79 PETn15 GND A79
B80 GND PERp15 A80
1

1)
B81 PRSNT2_B81 PERn15 A81
C1008 C1009 C1010 B82 RSVD_B82 GND A82
0.1uF 0.1uF 0.1uF
16V 16V 16V
x16 PCIe
2

課
x16 PCIe

D D

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Thursday, July 04, 2013 Sheet 1 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

Oland PCIe Interface

00 M
NOTE: Some of the PCIE testpoints will

0
be available through vias on traces.
A A

RD 17 SI
U1A
220nF for GEN3

TP109

1
PETP0_GFXRP0 AA38 PCIE_RX0P PCIE_TX0P Y33 PCIE_TX0P
C1101 2 10.22uF PERP0
1
IN OUT
1
PETN0_GFXRN0 Y37 PCIE_RX0N PCIE_TX0N Y32 PCIE_TX0N C1102 2 1
0.22uF PERN0
1
IN 6.3V OUT
TP110

1
PETP1_GFXRP1 Y35 PCIE_RX1P PCIE_TX1P W33 PCIE_TX1P C1103 2 6.3V 1
0.22uF PERP1
1
IN OUT
PETN1_GFXRN1 W36 W32 PCIE_TX1N 2 10.22uF PERN1

(C 96 C
1 PCIE_RX1N PCIE_TX1N C1104 1
IN 6.3V OUT

1
PETP2_GFXRP2 W38 PCIE_RX2P PCIE_TX2P U33 PCIE_TX2P C1105 2 6.3V 1
0.22uF PERP2
1
IN OUT
1
PETN2_GFXRN2 V37 PCIE_RX2N PCIE_TX2N U32 PCIE_TX2N C1106 2 10.22uF PERN2
1
IN 6.3V OUT

1
PETP3_GFXRP3 V35 PCIE_RX3P PCIE_TX3P U30 PCIE_TX3P C1107 2 6.3V 1
0.22uF PERP3
1
IN OUT
1
PETN3_GFXRN3 U36 PCIE_RX3N PCIE_TX3N U29 PCIE_TX3N C1108 2 1
0.22uF PERN3
1
IN 6.3V OUT
2 6.3V

)2 7 ON
1
PETP4_GFXRP4 U38 PCIE_RX4P PCIE_TX4P T33 PCIE_TX4P C1109 10.22uF PERP4
1
IN OUT
1
PETN4_GFXRN4 T37 PCIE_RX4N PCIE_TX4N T32 PCIE_TX4N C1110 2 1
0.22uF PERN4
1
IN 6.3V OUT
PETP5_GFXRP5 T35 PCIE_RX5P PCIE_TX5P T30 PCIE_TX5P C1111 1 6.3V 20.22uF PERP5
1 IN 0.22uF OUT 1
1
PETN5_GFXRN5 R36 PCIE_RX5N PCIE_TX5N T29 PCIE_TX5N
C11122 1 PERN5
1
IN 6.3V OUT
6.3V 0.22uF
1
PETP6_GFXRP6 R38 PCIE_RX6P PCIE_TX6P P33 PCIE_TX6P
C11132 1 PERP6
1
IN 0.22uF OUT
1
PETN6_GFXRN6 P37 PCIE_RX6N PCIE_TX6N P32 PCIE_TX6N
C11142 1 PERN6
1
IN 6.3V OUT

F
TP120

0
6.3V 0.22uF
1
PETP7_GFXRP7 P35 PCIE_RX7P PCIE_TX7P P30 PCIE_TX7P
C11152 1 PERP7
1
IN 0.22uF OUT
1
PETN7_GFXRN7 N36 PCIE_RX7N PCIE_TX7N P29 PCIE_TX7N
C11162 1 PERN7
1
IN 6.3V OUT
TP121
6.3V
N38 N33

吳 13 jo ID
NC#N38 NC#N33
M37 NC#M37 NC#N32 N32

M35 NC#M35 NC#N30 N30

L36 NC#L36 NC#N29 N29

L38 NC#L38 NC#L33 L33

K37 NC#K37 NC#L32 L32
B B

積 09 ne EN
K35 NC#K35 NC#L30 L30
J36 NC#J36 NC#L29 L29

J38 NC#J38 NC#K33 K33

H37 NC#H37 NC#K32 K32

H35 NC#H35 NC#J33 J33

G36 NC#G36 NC#J32 J32

源 05 pe TI
G38 NC#G38 NC#K30 K30
F37 NC#F37 NC#K29 K29

F35 NC#F35 NC#H33 H33 +0.95V

E37 NC#E37 NC#H32 H32 10 8 +0.95V

01 i( AL
PCIE_REFCLKP AB35 PCIE_REFCLKP PCIE_CALR_TX Y30 PCIE_CALRP R1013
1 21.69K PCIE_CALR_TX 1.69k pull up for Oland
1 IN R1014
1
PCIE_REFCLKN AA36 PCIE_REFCLKN PCIE_CALR_RX Y29 PCIE_CALRN 1 2 2K
IN PCIE_CALR_RX 1k pull up for Oland
PX_EN
OUT 15,16,17
1 2 1K AL21 AB39
R1015 PX_EN VSS
DNI VSS E39
+1.8V VSS F34
AA30 F39

(0
PERST#_BUF
1,16 PERSTB VSS
IN
VSS G33

裴
VSS G34
16 14 9 8 +1.8V
VSS H31
B11
+PCIE_PVDD 1.8V 200mA VSS H34
1 2 AB37 PCIE_PVDD VSS H39
1

1
120R J31
VSS
C1143 C1189 C1173 C1175 VSS J34

00 RM 亮
10uF 1uF 1uF 0.1uF K31
6.3V 6.3V 6.3V 6.3V VSS
AA31 NC#33 VSS K34
2

AA32 NC#34 VSS K39

C AA33 NC#35 VSS L31 C
AA34 NC#36 VSS L34
W30 NC#37 VSS M34
Y31 NC#38 VSS M39
VSS N31
V28 N34

11 A工 樂
NC_BIF_VDDC VSS
W29 NC_BIF_VDDC VSS P31
VSS P34
VSS P39
G30 PCIE_VDDC VSS R34
G31 PCIE_VDDC VSS T31
+0.95V H29 PCIE_VDDC VSS T34
H30 PCIE_VDDC VSS T39
J29 PCIE_VDDC VSS U31

60
J30 PCIE_VDDC VSS U34
L28 V34

)
PCIE_VDDC VSS
1

1
M28 PCIE_VDDC VSS Y39
C1161 C1160 C1159 C1158 C1150 C1151 C1152 C1153 C1154 C1155 N28 PCIE_VDDC VSS V39

程
1uF 10uF 10uF 10uF 1uF 1uF 1uF 1uF 1uF 1uF R28 W31
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V PCIE_VDDC VSS
T28 PCIE_VDDC VSS W34
2

U28 PCIE_VDDC VSS Y34

1)
OLAND M2 GDDR5

D
課 D

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Thursday, July 04, 2013 Sheet 2 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

(3) Oland MEM Interface Ch A&B

00 M
U1B U1C

0
4
DQA0_<0> C37 DQA0_0 4 3C18
DQA1_0
DQA1_<0> 0
4 4
DQB0_<0> C5 DQB0_0 4 3AA4
DQB1_0
DQB1_<0>
4
A DQA0_<0> DQA1_<0> DQB0_<0> DQB1_<0> A
4
DQA0_<1> C35 DQA0_1 4 3A18
DQA1_1
DQA1_<1> 1
4 4
DQB0_<1> C3 DQB0_1 4 3AB6
DQB1_1
DQB1_<1>
4
DQA0_<1> DQA1_<1> DQB0_<1> DQB1_<1>

RD 17 SI
4
DQA0_<2> A35 DQA0_2 4 3F18
DQA1_2
DQA1_<2> 2
4 4
DQB0_<2> E3 DQB0_2 4 3AB1
DQB1_2
DQB1_<2>
4
DQA0_<2> DQA1_<2> DQB0_<2> DQB1_<2>
4
DQA0_<3> E34 DQA0_3 4 3D17
DQA1_3
DQA1_<3> 3
4 4
DQB0_<3> E1 DQB0_3 4 3AB3
DQB1_3
DQB1_<3>
4
DQA0_<3> DQA1_<3> DQB0_<3> DQB1_<3>
4
DQA0_<4> G32 DQA0_4 4 3A16
DQA1_4
DQA1_<4> 4
4 4
DQB0_<4> F1 DQB0_4 4 3AD6
DQB1_4
DQB1_<4>
4
DQA0_<4> DQA1_<4> DQB0_<4> DQB1_<4>
4
DQA0_<5> D33 DQA0_5 4 3F16
DQA1_5
DQA1_<5> 5
4 4
DQB0_<5> F3 DQB0_5 4 3AD1
DQB1_5
DQB1_<5>
4
DQA0_<5> DQA1_<5> DQB0_<5> DQB1_<5>
4
DQA0_<6> F32 DQA0_6 4 3D15
DQA1_6
DQA1_<6> 6
4 4
DQB0_<6> F5 DQB0_6 4 3AD3
DQB1_6
DQB1_<6>
4
DQA0_<6> DQA1_<6> DQB0_<6> DQB1_<6>
4
DQA0_<7> E32 DQA0_7 4 3E14
DQA1_7
DQA1_<7> 7
4 4
DQB0_<7> G4 DQB0_7 4 3AD5
DQB1_7
DQB1_<7>
4
DQA0_<7> DQA1_<7> DQB0_<7> DQB1_<7>
4
DQA0_<8> D31 DQA0_8 4 3F14
DQA1_8
DQA1_<8> 8
4 4
DQB0_<8> H5 DQB0_8 4 3AF1
DQB1_8
DQB1_<8>
4
DQA0_<8> DQA1_<8> DQB0_<8> DQB1_<8>
4
DQA0_<9> F30 DQA0_9 4 3D13
DQA1_9
DQA1_<9> 9
4 4
DQB0_<9> H6 DQB0_9 4 3AF3
DQB1_9
DQB1_<9>
4
DQA0_<9> DQA1_<9> DQB0_<9> DQB1_<9>
DQA0_<10> C30 4 3F12 DQA1_<10> 10 DQB0_<10> J4 4 3AF6 DQB1_<10>

(C 96 C
4 DQA0_10 DQA1_10 4 4 DQB0_10 DQB1_10 4
DQA0_<10> DQA1_<10> DQB0_<10> DQB1_<10>
4
DQA0_<11> A30 DQA0_11 4 3A12
DQA1_11
DQA1_<11> 11
4 4
DQB0_<11> K6 DQB0_11 4 3AG4
DQB1_11
DQB1_<11>
4
DQA0_<11> DQA1_<11> DQB0_<11> DQB1_<11>
4
DQA0_<12> F28 DQA0_12 4 3D11
DQA1_12
DQA1_<12> 12
4 4
DQB0_<12> K5 DQB0_12 4 3AH5
DQB1_12
DQB1_<12>
4
DQA0_<12> DQA1_<12> DQB0_<12> DQB1_<12>
4
DQA0_<13> C28 DQA0_13 4 3F10
DQA1_13
DQA1_<13> 13
4 4
DQB0_<13> L4 DQB0_13 4 3AH6
DQB1_13
DQB1_<13>
4
DQA0_<13> DQA1_<13> DQB0_<13> DQB1_<13>
4
DQA0_<14> A28 DQA0_14 4 3A10
DQA1_14
DQA1_<14> 14
4 4
DQB0_<14> M6 DQB0_14 4 3AJ4
DQB1_14
DQB1_<14>
4
DQA0_<14> DQA1_<14> DQB0_<14> DQB1_<14>
4
DQA0_<15> E28 DQA0_15 4 3C10
DQA1_15
DQA1_<15> 15
4 4
DQB0_<15> M1 DQB0_15 4 3AK3
DQB1_15
DQB1_<15>
4
DQA0_<15> DQA1_<15> DQB0_<15> DQB1_<15>
4
DQA0_<16> D27 DQA0_16 4 3G13
DQA1_16
DQA1_<16> 16
4 4
DQB0_<16> M3 DQB0_16 4 3AF8
DQB1_16
DQB1_<16>
4
DQA0_<16> DQA1_<16> DQB0_<16> DQB1_<16>
4
DQA0_<17> F26 DQA0_17 4 3H13
DQA1_17
DQA1_<17> 17
4 4
DQB0_<17> M5 DQB0_17 4 3AF9
DQB1_17
DQB1_<17>
4
DQA0_<17> DQA1_<17> DQB0_<17> DQB1_<17>

)2 7 ON
4
DQA0_<18> C26 DQA0_18 4 3J13
DQA1_18
DQA1_<18> 18
4 4
DQB0_<18> N4 DQB0_18 4 3AG8
DQB1_18
DQB1_<18>
4
DQA0_<18> DQA1_<18> DQB0_<18> DQB1_<18>
4
DQA0_<19> A26 DQA0_19 4 3H11
DQA1_19
DQA1_<19> 19
4 4
DQB0_<19> P6 DQB0_19 4 3AG7
DQB1_19
DQB1_<19>
4
DQA0_<19> DQA1_<19> DQB0_<19> DQB1_<19>
4
DQA0_<20> F24 DQA0_20 4 3G10
DQA1_20
DQA1_<20> 20
4 4
DQB0_<20> P5 DQB0_20 4 3AK9
DQB1_20
DQB1_<20>
4
DQA0_<20> DQA1_<20> DQB0_<20> DQB1_<20>
4
DQA0_<21> C24 DQA0_21 4 3G8
DQA1_21
DQA1_<21> 21
4 4
DQB0_<21> R4 DQB0_21 4 3AL7
DQB1_21
DQB1_<21>
4
DQA0_<21> DQA1_<21> DQB0_<21> DQB1_<21>
4
DQA0_<22> A24 DQA0_22 4 3K9
DQA1_22
DQA1_<22> 22
4 4
DQB0_<22> T6 DQB0_22 4 3AM8
DQB1_22
DQB1_<22>
4
DQA0_<22> DQA1_<22> DQB0_<22> DQB1_<22>
4
DQA0_<23> E24 DQA0_23 4 3K10
DQA1_23
DQA1_<23> 23
4 4
DQB0_<23> T1 DQB0_23 4 3AM7
DQB1_23
DQB1_<23>
4
DQA0_<23> DQA1_<23> DQB0_<23> DQB1_<23>
4
DQA0_<24> C22 DQA0_24 4 3G9
DQA1_24
DQA1_<24> 24
4 4
DQB0_<24> U4 DQB0_24 4 3AK1
DQB1_24
DQB1_<24>
4
DQA0_<24> DQA1_<24> DQB0_<24> DQB1_<24>
4
DQA0_<25> A22 DQA0_25 4 3A8
DQA1_25
DQA1_<25> 25
4 4
DQB0_<25> V6 DQB0_25 4 3AL4
DQB1_25
DQB1_<25>
4
DQA0_<25> DQA1_<25> DQB0_<25> DQB1_<25>
DQA0_<26> F22 4 3C8 DQA1_<26> DQB0_<26> V1 4 3AM6 DQB1_<26>

F
DQA0_26 DQA1_26 26 DQB0_26 DQB1_26
4 DQA0_<26> DQA1_<26> 4 4 DQB0_<26> DQB1_<26> 4

0
4
DQA0_<27> D21 DQA0_27 4 3E8
DQA1_27
DQA1_<27> 27
4 4
DQB0_<27> V3 DQB0_27 4 3AM1
DQB1_27
DQB1_<27>
4
DQA0_<27> DQA1_<27> DQB0_<27> DQB1_<27>
4
DQA0_<28> A20 DQA0_28 4 3A6
DQA1_28
DQA1_<28> 28
4 4
DQB0_<28> Y6 DQB0_28 4 3AN4
DQB1_28
DQB1_<28>
4
DQA0_<28> DQA1_<28> DQB0_<28> DQB1_<28>
4
DQA0_<29> F20 DQA0_29 4 3C6
DQA1_29
DQA1_<29> 29
4 4
DQB0_<29> Y1 DQB0_29 4 3AP3
DQB1_29
DQB1_<29>
4
DQA0_<29> DQA1_<29> DQB0_<29> DQB1_<29>
DQA0_<30> D19 4 3E6 DQA1_<30> 30 DQB0_<30> Y3 4 3AP1 DQB1_<30>

吳 13 jo ID
4 DQA0_30 DQA1_30 4 4 DQB0_30 DQB1_30 4
DQA0_<30> DQA1_<30> DQB0_<30> DQB1_<30>
4
DQA0_<31> E18 DQA0_31 4 3A5
DQA1_31
DQA1_<31> 31
4 4
DQB0_<31> Y5 DQB0_31 4 3AP5
DQB1_31
DQB1_<31>
4
DQA0_<31> DQA1_<31> DQB0_<31> DQB1_<31>

4
MAA0_<0> G24 MAA0_0 4 3H19
MAA1_0
MAA1_<0> 0
4 4
MAB0_<0> P8 MAB0_0 4 3Y9
MAB1_0
MAB1_<0>
4
MAA0_<0> MAA1_<0> MAB0_<0> MAB1_<0>
4
MAA0_<1> J23 MAA0_1 4 3H20
MAA1_1
MAA1_<1> 1
4 4
MAB0_<1> T9 MAB0_1 4 3W9
MAB1_1
MAB1_<1>
4
MAA0_<1> MAA1_<1> MAB0_<1> MAB1_<1>
4
MAA0_<2> H24 MAA0_2 4 3L13
MAA1_2
MAA1_<2> 2
4 4
MAB0_<2> P9 MAB0_2 4 3AC8
MAB1_2
MAB1_<2>
4
MAA0_<2> MAA1_<2> MAB0_<2> MAB1_<2>
4
MAA0_<3> J24 MAA0_3 4 3G16
MAA1_3
MAA1_<3> 3
4 4
MAB0_<3> N7 MAB0_3 4 3AC9
MAB1_3
MAB1_<3>
4
MAA0_<3> MAA1_<3> MAB0_<3> MAB1_<3>
B 4
MAA0_<4> H26 MAA0_4 4 3J16
MAA1_4
MAA1_<4> 4
4 4
MAB0_<4> N8 MAB0_4 4 3AA7
MAB1_4
MAB1_<4>
4 B

積 09 ne EN
MAA0_<4> MAA1_<4> MAB0_<4> MAB1_<4>
4
MAA0_<5> J26 MAA0_5 4 3H16
MAA1_5
MAA1_<5> 5
4 4
MAB0_<5> N9 MAB0_5 4 3AA8
MAB1_5
MAB1_<5>
4
MAA0_<5> MAA1_<5> MAB0_<5> MAB1_<5>
4
MAA0_<6> H21 MAA0_6 4 3J17
MAA1_6
MAA1_<6> 6
4 4
MAB0_<6> U9 MAB0_6 4 3Y8
MAB1_6
MAB1_<6>
4
MAA0_<6> MAA1_<6> MAB0_<6> MAB1_<6>
4
MAA0_<7> G21 MAA0_7 4 3H17
MAA1_7
MAA1_<7> 7
4 4
MAB0_<7> U8 MAB0_7 4 3AA9
MAB1_7
MAB1_<7>
4
MAA0_<7> MAA1_<7> MAB0_<7> MAB1_<7>
4
MAA0_<8> H23 MAA0_8 4 3J19
MAA1_8
MAA1_<8> 8
4 4
MAB0_<8> T8 MAB0_8 4 3W8
MAB1_8
MAB1_<8>
4
MAA0_<8> MAA1_<8> MAB0_<8> MAB1_<8>
M21 MAA0_9 MAA1_9 M20 U12 MAB0_9 MAB1_9 V12

4
WCKA0_0 A32 WCKA0_0 WCKA1_0 C14 WCKA1_0
4 4
WCKB0_0 H3 WCKB0_0 WCKB1_0 AE4 WCKB1_0
4
BI BI BI BI
4
WCKA0B_0 C32 WCKA0B_0 WCKA1B_0 A14 WCKA1B_0
4 4
WCKB0B_0 H1 WCKB0B_0 WCKB1B_0 AF5 WCKB1B_0
4
BI BI BI BI

源 05 pe TI
4
WCKA0_1 D23 WCKA0_1 WCKA1_1 E10 WCKA1_1
4 4
WCKB0_1 T3 WCKB0_1 WCKB1_1 AK6 WCKB1_1
4
BI BI BI BI
4
WCKA0B_1 E22 WCKA0B_1 WCKA1B_1 D9 WCKA1B_1
4 4
WCKB0B_1 T5 WCKB0B_1 WCKB1B_1 AK5 WCKB1B_1
4
BI BI BI BI

4
EDCA0_0 C34 EDCA0_0 EDCA1_0 E16 EDCA1_0
4 4
EDCB0_0 F6 EDCB0_0 EDCB1_0 AB5 EDCB1_0
4
BI BI BI BI
4
EDCA0_1 D29 EDCA0_1 EDCA1_1 E12 EDCA1_1
4 4
EDCB0_1 K3 EDCB0_1 EDCB1_1 AH1 EDCB1_1
4
BI BI BI BI
4
EDCA0_2 D25 EDCA0_2 EDCA1_2 J10 EDCA1_2
4 4
EDCB0_2 P3 EDCB0_2 EDCB1_2 AJ9 EDCB1_2
4
BI BI BI BI

01 i( AL
4
EDCA0_3 E20 EDCA0_3 EDCA1_3 D7 EDCA1_3
4 4
EDCB0_3 V5 EDCB0_3 EDCB1_3 AM5 EDCB1_3
4
BI BI BI BI

4
DDBIA0_0 A34 DDBIA0_0 DDBIA1_0 C16 DDBIA1_0
4 4
DDBIB0_0 G7 DDBIB0_0 DDBIB1_0 AC4 DDBIB1_0
4
BI BI BI BI
4
DDBIA0_1 E30 DDBIA0_1 DDBIA1_1 C12 DDBIA1_1
4 4
DDBIB0_1 K1 DDBIB0_1 DDBIB1_1 AH3 DDBIB1_1
4
BI BI BI BI
4
DDBIA0_2 E26 DDBIA0_2 DDBIA1_2 J11 DDBIA1_2
4 4
DDBIB0_2 P1 DDBIB0_2 DDBIB1_2 AJ8 DDBIB1_2
4
BI BI BI BI
4
DDBIA0_3 C20 DDBIA0_3 DDBIA1_3 F8 DDBIA1_3
4 4
DDBIB0_3 W4 DDBIB0_3 DDBIB1_3 AM3 DDBIB1_3
4
BI BI BI BI

4
ADBIA0 J21 ADBIA0 ADBIA1 G19 ADBIA1
4 4
ADBIB0 T7 ADBIB0 ADBIB1 W7 ADBIB1
4
BI BI BI BI

(0
4
CSA0B_0 K24 CSA0B_0 CSA1B_0 M13 CSA1B_0
4 4
CSB0B_0 P10 CSB0B_0 CSB1B_0 AD10 CSB1B_0
4

裴
OUT OUT OUT OUT
K27 CSA0B_1 CSA1B_1 K16 L10 CSB0B_1 CSB1B_1 AC10

4
CASA0B K20 CASA0B CASA1B K17 CASA1B
4 4
CASB0B W10 CASB0B CASB1B AA10 CASB1B
4
OUT OUT OUT OUT
4
RASA0B K23 RASA0B RASA1B K19 RASA1B
4 4
RASB0B T10 RASB0B RASB1B Y10 RASB1B
4
OUT OUT OUT OUT
4
WEA0B K26 WEA0B WEA1B L15 WEA1B
4 4
WEB0B N10 WEB0B WEB1B AB11 WEB1B
4
OUT OUT OUT OUT

00 RM 亮
4
CKEA0 K21 CKEA0 CKEA1 J20 CKEA1
4 4
CKEB0 U10 CKEB0 CKEB1 AA11 CKEB1
4
OUT OUT OUT OUT

4
CLKA0 H27 CLKA0 CLKA1 J14 CLKA1
4 4
CLKB0 L9 CLKB0 CLKB1 AD8 CLKB1
4
OUT OUT OUT OUT
C 4
CLKA0B G27 CLKA0B CLKA1B H14 CLKA1B
4 4
CLKB0B L8 CLKB0B CLKB1B AD7 CLKB1B
4 C
OUT OUT OUT OUT

+MVDD +MVDD

11 A工 樂 1

1
R3602 R3603
40.2R 40.2R
1%
MVREFDA L18 MVREFD_A 1% MVREFDB Y12 MVREFD_B

1 2

1 2
1

1
C3602 C3603
1uF 1uF
6.3V R3606 6.3V R3607
MVREFD/S =0.7* 100R 243R 100R
1
R3601 2 MEM_CALRP0 M27 MEM_CALRP0
2

2
60
1% MVREFD/S =0.7* 1%
VDDR1
2

2
)
VDDR1
(GDDR3/4/5)
(GDDR3/4/5)

1 2 1 2

程
AH11 L20 AA12
DRAM_RST DRAM_RST_RR DRAM_RST_R
R3630 R3615 DRAM_RST MVREFSA MVREFSB
OUT
1

1)
49.9R 10R
2

C3607
120pF OLAND M2 GDDR5 OLAND M2 GDDR5
50V R3612
5.1K
2

課
1

D D

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector
Connectorci20313 1.0

Date: Thursday, July 04, 2013 Sheet 3 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

+MVDD

11 9 4 +MVDD

(4) GDDR5 Memory Channel A&B

GDDR5

23CNOPN001 +MVDD

C2305

C2311

C2312

C2313

C2317

C2318

C2319

C2320

C2321

C2322
1

1
U2700
GDDR5

1uF
DQB1_<0> DQB1_<22> M2 B1

00
GDDR5
3 DQ31__DQ7 VDDQ_B1
DQB1_<0>
23CNOPN001 +MVDD 23CNOPN001 +MVDD 23CNOPN001 +MVDD DQB1_<1> DQB1_<23> M4 DQ30__DQ6 VDDQ_B3 B3
U2000 U2300 U2400
3 DQB1_<1> 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
DQB1_<2> DQB1_<21> N2 DQ29__DQ5 VDDQ_B12 B12
3 DQB1_<2>

2
3
0 DQA0_<0> DQA0_<30> M2 DQ31__DQ7 VDDQ_B1 B1 3 DQA1_<0> DQA1_<21> M2 DQ31__DQ7 VDDQ_B1 B1 3 DQB0_<0> DQB0_<30> M2 DQ31__DQ7 VDDQ_B1 B1 3 DQB1_<3> DQB1_<20> N4 DQ28__DQ4 VDDQ_B14 B14

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF
DQA0_<0> DQA1_<0> DQB0_<0> DQB1_<3>
3
1 DQA0_<1> DQA0_<31> M4 DQ30__DQ6 VDDQ_B3 B3 3 DQA1_<1> DQA1_<22> M4
DQ30__DQ6 VDDQ_B3 B3 3 DQB0_<1> DQB0_<31> M4 DQ30__DQ6 VDDQ_B3 B3 3 DQB1_<4> DQB1_<19> T2 DQ27__DQ3 VDDQ_D1 D1
DQA0_<1> DQA1_<1> DQB0_<1> DQB1_<4>
3
2 DQA0_<2> DQA0_<29> N2 DQ29__DQ5 VDDQ_B12 B12 3 DQA1_<2> DQA1_<23> N2
DQ29__DQ5 VDDQ_B12 B12 3 DQB0_<2> DQB0_<29> N2 DQ29__DQ5 VDDQ_B12 B12 3 DQB1_<5> DQB1_<16> T4 DQ26__DQ2 VDDQ_D3 D3
DQA0_<2> DQA1_<2> DQB0_<2> DQB1_<5>
3 DQA0_<3> DQA0_<28> N4 DQ28__DQ4 VDDQ_B14 B14 DQA1_<3> DQA1_<20> N4
DQ28__DQ4 VDDQ_B14 B14 DQB0_<3> DQB0_<28> N4 DQ28__DQ4 VDDQ_B14 B14 DQB1_<6> DQB1_<18> V2 DQ25__DQ1 VDDQ_D12 D12
3 DQA0_<3> 3 DQA1_<3> 3 DQB0_<3> 3 DQB1_<6>

M
4 DQA0_<4> DQA0_<26> T2 DQ27__DQ3 VDDQ_D1 D1 DQA1_<4> DQA1_<17> T2
DQ27__DQ3 VDDQ_D1 D1 DQB0_<4> DQB0_<26> T2 DQ27__DQ3 VDDQ_D1 D1 DQB1_<7> DQB1_<17> V4 DQ24__DQ0 VDDQ_D14 D14
3 DQA0_<4> 3 DQA1_<4> 3 DQB0_<4> 3 DQB1_<7>
3
5 DQA0_<5> DQA0_<25> T4 DQ26__DQ2 VDDQ_D3 D3 3 DQA1_<5> DQA1_<16> T4
DQ26__DQ2 VDDQ_D3 D3 3 DQB0_<5> DQB0_<25> T4 DQ26__DQ2 VDDQ_D3 D3 3 DQB1_<8> DQB1_<24> M13 DQ23__DQ15 VDDQ_E5 E5 +MVDD
GND
DQA0_<5> DQA1_<5> DQB0_<5> DQB1_<8>
3
6 DQA0_<6> DQA0_<27> V2 DQ25__DQ1 VDDQ_D12 D12 3 DQA1_<6> DQA1_<18> V2
DQ25__DQ1 VDDQ_D12 D12 3 DQB0_<6> DQB0_<27> V2 DQ25__DQ1 VDDQ_D12 D12 3 DQB1_<9> DQB1_<25> M11 DQ22__DQ14 VDDQ_E10 E10

0
DQA0_<6> DQA1_<6> DQB0_<6> DQB1_<9>
3
7 DQA0_<7> DQA0_<24> V4 DQ24__DQ0 VDDQ_D14 D14 3 DQA1_<7> DQA1_<19> V4
DQ24__DQ0 VDDQ_D14 D14 3 DQB0_<7> DQB0_<24> V4 DQ24__DQ0 VDDQ_D14 D14 3 DQB1_<10> DQB1_<26> N13 DQ21__DQ13 VDDQ_F1 F1
DQA0_<7> DQA1_<7> DQB0_<7> DQB1_<10>
A 8 DQA0_<8> DQA0_<16> M13 DQ23__DQ15 VDDQ_E5 E5 DQA1_<8> DQA1_<24> M13
DQ23__DQ15 VDDQ_E5 E5 DQB0_<8> DQB0_<16> M13 DQ23__DQ15 VDDQ_E5 E5 DQB1_<11> DQB1_<27> N11 DQ20__DQ12 VDDQ_F3 F3 A
3 3 3 3

RD 17 SI
DQA0_<8> DQA1_<8> DQB0_<8> DQB1_<11>
9 DQA0_<9> DQA0_<17> M11 DQ22__DQ14 VDDQ_E10 E10 DQA1_<9> DQA1_<25> M11
DQ22__DQ14 VDDQ_E10 E10 DQB0_<9> DQB0_<17> M11 DQ22__DQ14 VDDQ_E10 E10 DQB1_<12> DQB1_<30> T13 DQ19__DQ11 VDDQ_F12 F12
3 DQA0_<9> 3 DQA1_<9> 3 DQB0_<9> 3 DQB1_<12>
3
10 DQA0_<10> DQA0_<18> N13 DQ21__DQ13 VDDQ_F1 F1 3 DQA1_<10> DQA1_<26> N13
DQ21__DQ13 VDDQ_F1 F1 3 DQB0_<10> DQB0_<18> N13 DQ21__DQ13 VDDQ_F1 F1 3 DQB1_<13> DQB1_<29> T11 DQ18__DQ10 VDDQ_F14 F14 C2340 C2325 C2327 C2332 C2328
DQA0_<10> DQA1_<10> DQB0_<10> DQB1_<13>
3
11 DQA0_<11> DQA0_<19> N11 DQ20__DQ12 VDDQ_F3 F3 3 DQA1_<11> DQA1_<27> N11
DQ20__DQ12 VDDQ_F3 F3 3 DQB0_<11> DQB0_<19> N11 DQ20__DQ12 VDDQ_F3 F3 3 DQB1_<14> DQB1_<28> V13 DQ17__DQ9 VDDQ_G2 G2 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF
DQA0_<11> DQA1_<11> DQB0_<11> DQB1_<14>
3
12 DQA0_<12> DQA0_<20> T13 DQ19__DQ11 VDDQ_F12 F12 3 DQA1_<12> DQA1_<29> T13
DQ19__DQ11 VDDQ_F12 F12 3 DQB0_<12> DQB0_<20> T13 DQ19__DQ11 VDDQ_F12 F12 3 DQB1_<15> DQB1_<31> V11 DQ16__DQ8 VDDQ_G13 G13 4V 4V 4V 4V 4V
DQA0_<12> DQA1_<12> DQB0_<12> DQB1_<15>
13 DQA0_<13> DQA0_<22> T11 DQ18__DQ10 VDDQ_F14 F14 DQA1_<13> DQA1_<30> T11
DQ18__DQ10 VDDQ_F14 F14 DQB0_<13> DQB0_<22> T11 DQ18__DQ10 VDDQ_F14 F14 DQB1_<16> DQB1_<14> F13 DQ15__DQ23 VDDQ_H3 H3
3 DQA0_<13> 3 DQA1_<13> 3 DQB0_<13> 3 DQB1_<16>
14 DQA0_<14> DQA0_<21> V13 DQ17__DQ9 VDDQ_G2 G2 DQA1_<14> DQA1_<28> V13
DQ17__DQ9 VDDQ_G2 G2 DQB0_<14> DQB0_<21> V13 DQ17__DQ9 VDDQ_G2 G2 DQB1_<17> DQB1_<15> F11 DQ14__DQ22 VDDQ_H12 H12
3 DQA0_<14> 3 DQA1_<14> 3 DQB0_<14> 3 DQB1_<17>
3
15 DQA0_<15> DQA0_<23> V11 DQ16__DQ8 VDDQ_G13 G13 3 DQA1_<15> DQA1_<31> V11
DQ16__DQ8 VDDQ_G13 G13 3 DQB0_<15> DQB0_<23> V11 DQ16__DQ8 VDDQ_G13 G13 3 DQB1_<18> DQB1_<13> E13 DQ13__DQ21 VDDQ_K3 K3 +MVDD
DQA0_<15> DQA1_<15> DQB0_<15> DQB1_<18>
3
16 DQA0_<16> DQA0_<13> F13 DQ15__DQ23 VDDQ_H3 H3 3 DQA1_<16> DQA1_<14> F13
DQ15__DQ23 VDDQ_H3 H3 3 DQB0_<16> DQB0_<13> F13 DQ15__DQ23 VDDQ_H3 H3 3 DQB1_<19> DQB1_<12> E11 DQ12__DQ20 VDDQ_K12 K12 GND
+MVDD
DQA0_<16> DQA1_<16> DQB0_<16> DQB1_<19>
3
17 DQA0_<17> DQA0_<12> F11 DQ14__DQ22 VDDQ_H12 H12 3 DQA1_<17> DQA1_<15> F11
DQ14__DQ22 VDDQ_H12 H12 3 DQB0_<17> DQB0_<11> F11 DQ14__DQ22 VDDQ_H12 H12 3 DQB1_<20> DQB1_<11> B13 DQ11__DQ19 VDDQ_L2 L2
DQA0_<17> DQA1_<17> DQB0_<17> DQB1_<20>
18 DQA0_<18> DQA0_<14> E13 DQ13__DQ21 VDDQ_K3 K3 DQA1_<18> DQA1_<13> E13
DQ13__DQ21 VDDQ_K3 K3 DQB0_<18> DQB0_<14> E13 DQ13__DQ21 VDDQ_K3 K3 DQB1_<21> DQB1_<9> B11 DQ10__DQ18 VDDQ_L13 L13
3 3 3 3

(C 96 C
DQA0_<18> DQA1_<18> DQB0_<18> DQB1_<21>
19 DQA0_<19> DQA0_<15> E11 DQ12__DQ20 VDDQ_K12 K12 DQA1_<19> DQA1_<12> E11
DQ12__DQ20 VDDQ_K12 K12 DQB0_<19> DQB0_<15> E11 DQ12__DQ20 VDDQ_K12 K12 DQB1_<22> DQB1_<10> A13 DQ9__DQ17 VDDQ_M1 M1
3 DQA0_<19> 3 DQA1_<19> 3 DQB0_<19> 3 DQB1_<22>
3
20 DQA0_<20> DQA0_<11> B13 DQ11__DQ19 VDDQ_L2 L2 3 DQA1_<20> DQA1_<11> B13
DQ11__DQ19 VDDQ_L2 L2 3 DQB0_<20> DQB0_<12> B13 DQ11__DQ19 VDDQ_L2 L2 3 DQB1_<23> DQB1_<8> A11 DQ8__DQ16 VDDQ_M3 M3 C2041 C2033 C2039 C2035 C2036
DQA0_<20> DQA1_<20> DQB0_<20> DQB1_<23>
3
21 DQA0_<21> DQA0_<9> B11 DQ10__DQ18 VDDQ_L13 L13 3 DQA1_<21> DQA1_<9> B11
DQ10__DQ18 VDDQ_L13 L13 3 DQB0_<21> DQB0_<9> B11 DQ10__DQ18 VDDQ_L13 L13 3 DQB1_<24> DQB1_<0> F2 DQ7__DQ31 VDDQ_M12 M12 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF C2444 C2435 C2434 C2430 C2405 C2431
DQA0_<21> DQA1_<21> DQB0_<21> DQB1_<24>
3
22 DQA0_<22> DQA0_<10> A13 DQ9__DQ17 VDDQ_M1 M1 3 DQA1_<22> DQA1_<10> A13
DQ9__DQ17 VDDQ_M1 M1 3 DQB0_<22> DQB0_<8> A13 DQ9__DQ17 VDDQ_M1 M1 3 DQB1_<25> DQB1_<1> F4 DQ6__DQ30 VDDQ_M14 M14 4V 4V 4V 4V 4V 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF
DQA0_<22> DQA1_<22> DQB0_<22> DQB1_<25>
23 DQA0_<23> DQA0_<8> A11 DQ8__DQ16 VDDQ_M3 M3 DQA1_<23> DQA1_<8> A11
DQ8__DQ16 VDDQ_M3 M3 DQB0_<23> DQB0_<10> A11 DQ8__DQ16 VDDQ_M3 M3 DQB1_<26> DQB1_<2> E2 DQ5__DQ29 VDDQ_N5 N5 4V 4V 4V 4V 4V 4V
3 DQA0_<23> 3 DQA1_<23> 3 DQB0_<23> 3 DQB1_<26>
24 DQA0_<24> DQA0_<0> F2 DQ7__DQ31 VDDQ_M12 M12 DQA1_<24> DQA1_<0> F2 DQ7__DQ31 VDDQ_M12 M12 DQB0_<24> DQB0_<0> F2 DQ7__DQ31 VDDQ_M12 M12 DQB1_<27> DQB1_<3> E4 DQ4__DQ28 VDDQ_N10 N10
3 DQA0_<24> 3 DQA1_<24> 3 DQB0_<24> 3 DQB1_<27>
3
25 DQA0_<25> DQA0_<1> F4 DQ6__DQ30 VDDQ_M14 M14 3 DQA1_<25> DQA1_<1> F4 DQ6__DQ30 VDDQ_M14 M14 3 DQB0_<25> DQB0_<1> F4 DQ6__DQ30 VDDQ_M14 M14 3 DQB1_<28> DQB1_<5> B2 DQ3__DQ27 VDDQ_P1 P1
DQA0_<25> DQA1_<25> DQB0_<25> DQB1_<28>
3
26 DQA0_<26> DQA0_<2> E2 DQ5__DQ29 VDDQ_N5 N5 3 DQA1_<26> DQA1_<2> E2 DQ5__DQ29 VDDQ_N5 N5 3 DQB0_<26> DQB0_<2> E2 DQ5__DQ29 VDDQ_N5 N5 3 DQB1_<29> DQB1_<7> B4 DQ2__DQ26 VDDQ_P3 P3
DQA0_<26> DQA1_<26> DQB0_<26> DQB1_<29>
DQA0_<27> DQA0_<4> E4 N10 DQA1_<27> DQA1_<3> E4 N10 DQB0_<27> DQB0_<3> E4 N10 DQB1_<30> DQB1_<4> A2 P12

)2 7 ON
27
3 DQ4__DQ28 VDDQ_N10 3 DQ4__DQ28 VDDQ_N10 3 DQ4__DQ28 VDDQ_N10 3 DQ1__DQ25 VDDQ_P12 +MVDD
DQA0_<27> DQA1_<27> DQB0_<27> DQB1_<30>
28 DQA0_<28> DQA0_<5> B2 DQ3__DQ27 VDDQ_P1 P1 DQA1_<28> DQA1_<5> B2 DQ3__DQ27 VDDQ_P1 P1 DQB0_<28> DQB0_<5> B2 DQ3__DQ27 VDDQ_P1 P1 DQB1_<31> DQB1_<6> A4 DQ0__DQ24 VDDQ_P14 P14 GND
3 DQA0_<28> 3 DQA1_<28> 3 DQB0_<28> 3 DQB1_<31>
29 DQA0_<29> DQA0_<7> B4 DQ2__DQ26 VDDQ_P3 P3 DQA1_<29> DQA1_<7> B4 DQ2__DQ26 VDDQ_P3 P3 DQB0_<29> DQB0_<7> B4 DQ2__DQ26 VDDQ_P3 P3 VDDQ_T1 T1 11 9 4 +MVDD GND
3 DQA0_<29> 3 DQA1_<29> 3 DQB0_<29>
3
30 DQA0_<30> DQA0_<3> A2 DQ1__DQ25 VDDQ_P12 P12 3 DQA1_<30> DQA1_<4> A2 DQ1__DQ25 VDDQ_P12 P12 3 DQB0_<30> DQB0_<4> A2 DQ1__DQ25 VDDQ_P12 P12 VDDQ_T3 T3
DQA0_<30> DQA1_<30> DQB0_<30>
3
31 DQA0_<31> DQA0_<6> A4 DQ0__DQ24 VDDQ_P14 P14 3 DQA1_<31> DQA1_<6> A4 DQ0__DQ24 VDDQ_P14 P14 3 DQB0_<31> DQB0_<6> A4 DQ0__DQ24 VDDQ_P14 P14 VDDQ_T12 T12
DQA0_<31> DQA1_<31> DQB0_<31>
VDDQ_T1 T1 VDDQ_T1 T1 VDDQ_T1 T1 VDDQ_T14 T14
VDDQ_T3 T3 VDDQ_T3 T3 VDDQ_T3 T3

1
C2600

C2601

C2602

C2643

C2604

C2605

C2606

C2607

C2608

C2609

C2610

C2611

C2612

C2613

C2614

C2615

C2616

C2617

C2618

C2619

C2620
VDDQ_T12 T12 VDDQ_T12 T12 VDDQ_T12 T12 MAB1_<8> J5 RFU_A12_NC +MVDD
3 MAB1_<8>
VDDQ_T14 T14 VDDQ_T14 T14 VDDQ_T14 T14 3
MAB1_<7> K4 A7_A8__A0_A10 VDD_C5 C5
MAB1_<7>
+MVDD 3
MAB1_<6> K5 A6_A11__A1_A9 VDD_C10 C10

F
MAB1_<6> 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
MAA0_<8> J5 J5 J5 MAB1_<5> K10 D11

0
RFU_A12_NC MAA1_<8> RFU_A12_NC +MVDD MAB0_<8> RFU_A12_NC +MVDD A5_BA1__A3_BA3 VDD_D11
3 MAA0_<8> 3 MAA1_<8> 3 MAB0_<8> 3 MAB1_<5>

2
MAA0_<7> K4 A7_A8__A0_A10 VDD_C5 C5 MAA1_<7> K4 A7_A8__A0_A10 VDD_C5 C5 MAB0_<7> K4 A7_A8__A0_A10 VDD_C5 C5 MAB1_<4> K11 A4_BA2__A2_BA0 VDD_G1 G1
3 MAA0_<7> 3 MAA1_<7> 3 MAB0_<7> 3 MAB1_<4>
MAA0_<6> K5 A6_A11__A1_A9 VDD_C10 C10 MAA1_<6> K5 A6_A11__A1_A9 VDD_C10 C10 MAB0_<6> K5 A6_A11__A1_A9 VDD_C10 C10 MAB1_<3> H10 A3_BA3__A5_BA1 VDD_G4 G4
3 3 3 3

0.1uF

0.1uF

0.1uF
MAA0_<6> MAA1_<6> MAB0_<6> MAB1_<3>

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF
3
MAA0_<5> K10 A5_BA1__A3_BA3 VDD_D11 D11 3 K10
MAA1_<5> A5_BA1__A3_BA3 VDD_D11 D11 3 MAB0_<5> K10 A5_BA1__A3_BA3 VDD_D11 D11 3
MAB1_<2> H11 A2_BA0__A4_BA2 VDD_G11 G11
MAA0_<5> MAA1_<5> MAB0_<5> MAB1_<2>
MAA0_<4> K11 G1 K11 G1 K11 G1 MAB1_<1> H5 G14

吳 13 jo ID
A4_BA2__A2_BA0 VDD_G1 MAA1_<4> A4_BA2__A2_BA0 VDD_G1 MAB0_<4> A4_BA2__A2_BA0 VDD_G1 A1_A9__A6_A11 VDD_G14
3 MAA0_<4> 3 MAA1_<4> 3 MAB0_<4> 3 MAB1_<1>
3
MAA0_<3> H10 A3_BA3__A5_BA1 VDD_G4 G4 3 H10
MAA1_<3> A3_BA3__A5_BA1 VDD_G4 G4 3 MAB0_<3> H10 A3_BA3__A5_BA1 VDD_G4 G4 3
MAB1_<0> H4 A0_A10__A7_A8 VDD_L1 L1 +MVDD
MAA0_<3> MAA1_<3> MAB0_<3> MAB1_<0>
MAA0_<2> H11 A2_BA0__A4_BA2 VDD_G11 G11 H11
MAA1_<2> A2_BA0__A4_BA2 VDD_G11 G11 MAB0_<2> H11 A2_BA0__A4_BA2 VDD_G11 G11 VDD_L4 L4
3 MAA0_<2> 3 MAA1_<2> 3 MAB0_<2>
MAA0_<1> H5 A1_A9__A6_A11 VDD_G14 G14 MAA1_<1>H5 A1_A9__A6_A11 VDD_G14 G14 MAB0_<1> H5 A1_A9__A6_A11 VDD_G14 G14 VDD_L11 L11 11 9 4 +MVDD
+MVDD
GND
3 MAA0_<1> 3 MAA1_<1> 3 MAB0_<1>
3
MAA0_<0> H4 A0_A10__A7_A8 VDD_L1 L1 3 MAA1_<0>H4 A0_A10__A7_A8 VDD_L1 L1 3 MAB0_<0> H4 A0_A10__A7_A8 VDD_L1 L1 VDD_L14 L14
MAA0_<0> MAA1_<0> MAB0_<0>
VDD_L4 L4 VDD_L4 L4 VDD_L4 L4 3 IN
WCKB1_0 D4 WCK01__WCK23 VDD_P11 P11
VDD_L11 L11 VDD_L11 L11 VDD_L11 L11 3 IN
WCKB1B_0 D5 WCK01#__WCK23# VDD_R5 R5
VDD_L14 L14 VDD_L14 L14 VDD_L14 L14 VDD_R10 R10

1
C2635

C2630

C2634
3 IN
WCKA0_0 D4 WCK01__WCK23 VDD_P11 P11 3 IN
WCKA1_0 D4 WCK01__WCK23 VDD_P11 P11 3 IN
WCKB0_0 D4 WCK01__WCK23 VDD_P11 P11 3 IN
WCKB1_1 P4 WCK23__WCK01 C2638 C2631 C2622 C2623 C2632

3
WCKA0B_0 D5 WCK01#__WCK23# VDD_R5 R5 3
WCKA1B_0 D5 WCK01#__WCK23# VDD_R5 R5 3
WCKB0B_0 D5 WCK01#__WCK23# VDD_R5 R5 3
WCKB1B_1 P5 WCK23#__WCK01# 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF

積 09 ne EN
IN IN IN IN
VDD_R10 R10 VDD_R10 R10 VDD_R10 R10 VSSQ_A1 A1 6.3V 6.3V 6.3V
4V 4V 4V 4V 4V
WCKA0_1 P4 WCK23__WCK01
WCKA1_1 P4 WCK23__WCK01
WCKB0_1 P4 WCK23__WCK01
EDCB1_2 R2 EDC3__EDC0 VSSQ_A3 A3
B 3 IN 3 IN 3 IN 3 OUT B

2
10uF

10uF

10uF
3 IN
WCKA0B_1 P5 WCK23#__WCK01# 3 IN
WCKA1B_1 P5 WCK23#__WCK01# 3 IN
WCKB0B_1 P5 WCK23#__WCK01# 3 OUT
EDCB1_3 R13 EDC2__EDC1 VSSQ_A12 A12
VSSQ_A1 A1 VSSQ_A1 A1 VSSQ_A1 A1 3 OUT
EDCB1_1 C13 EDC1__EDC2 VSSQ_A14 A14 +MVDD

3 OUT
EDCA0_3 R2 EDC3__EDC0 VSSQ_A3 A3 3 OUT
EDCA1_2 R2 EDC3__EDC0 VSSQ_A3 A3 3 OUT
EDCB0_3 R2 EDC3__EDC0 VSSQ_A3 A3 3 OUT
EDCB1_0 C2 EDC0__EDC3 VSSQ_C1 C1
3 OUT
EDCA0_2 R13 EDC2__EDC1 VSSQ_A12 A12 3 OUT
EDCA1_3 R13 EDC2__EDC1 VSSQ_A12 A12 3 OUT
EDCB0_2 R13 EDC2__EDC1 VSSQ_A12 A12 VSSQ_C3 C3 9 4 +MVDD GND
11
3 OUT
EDCA0_1 C13 EDC1__EDC2 VSSQ_A14 A14 3 OUT
EDCA1_1 C13 EDC1__EDC2 VSSQ_A14 A14 3 OUT
EDCB0_1 C13 EDC1__EDC2 VSSQ_A14 A14 3 BI
DDBIB1_2 P2 DBI3#__DBI0# VSSQ_C4 C4 GND

3 OUT
EDCA0_0 C2 EDC0__EDC3 VSSQ_C1 C1 3 OUT
EDCA1_0 C2 EDC0__EDC3 VSSQ_C1 C1 3 OUT
EDCB0_0 C2 EDC0__EDC3 VSSQ_C1 C1 3 BI
DDBIB1_3 P13 DBI2#__DBI1# VSSQ_C11 C11
VSSQ_C3 C3 VSSQ_C3 C3 VSSQ_C3 C3 DDBIB1_1 D13 DBI1#__DBI2# VSSQ_C12 C12
3 BI

源 05 pe TI
3 BI
DDBIA0_3 P2 DBI3#__DBI0# VSSQ_C4 C4 3 BI
DDBIA1_2 P2 DBI3#__DBI0# VSSQ_C4 C4 3 BI
DDBIB0_3 P2 DBI3#__DBI0# VSSQ_C4 C4 3 BI
DDBIB1_0 D2 DBI0#__DBI3# VSSQ_C14 C14

C2007

C2008

C2010

C2000

C2001

C2012

C2013

C2015

C2016

C2017

C2018

C2019

C2020

C2021

C2022

C2023

C2024

C2025
1

1
3 BI
DDBIA0_2 P13 DBI2#__DBI1# VSSQ_C11 C11 3 BI
DDBIA1_3 P13 DBI2#__DBI1# VSSQ_C11 C11 3 BI
DDBIB0_2 P13 DBI2#__DBI1# VSSQ_C11 C11 VSSQ_E1 E1
3 BI
DDBIA0_1 D13 DBI1#__DBI2# VSSQ_C12 C12 3 BI
DDBIA1_1 D13 DBI1#__DBI2# VSSQ_C12 C12 3 BI
DDBIB0_1 D13 DBI1#__DBI2# VSSQ_C12 C12 VSSQ_E3 E3
3 BI
DDBIA0_0 D2 DBI0#__DBI3# VSSQ_C14 C14 3 BI
DDBIA1_0 D2 DBI0#__DBI3# VSSQ_C14 C14 3 BI
DDBIB0_0 D2 DBI0#__DBI3# VSSQ_C14 C14 VSSQ_E12 E12 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
VSSQ_E1 E1 VSSQ_E1 E1 VSSQ_E1 E1 3 +MVDD IN
RASB1B G3 RAS#__CAS# VSSQ_E14 E14

2
VSSQ_E3 E3 VSSQ_E3 E3 VSSQ_E3 E3 3
CASB1B L3 CAS#__RAS# VSSQ_F5 F5

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
IN

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF
VSSQ_E12 E12 +MVDD VSSQ_E12 E12 VSSQ_E12 E12 R2603 1 2 CLKB1B
VSSQ_F10 F10
RASA0B G3 E14 3 RASA1B G3 E14 RASB0B G3 E14 1 60.4R
2 CLKB1 H2
3 +MVDD IN RAS#__CAS# VSSQ_E14 IN RAS#__CAS# VSSQ_E14 3 +MVDD IN RAS#__CAS# VSSQ_E14 R2604 VSSQ_H2

3 IN
CASA0B L3 CAS#__RAS# VSSQ_F5 F5 3 IN
CASA1B L3 CAS#__RAS# VSSQ_F5 F5 3 IN
CASB0B L3 CAS#__RAS# VSSQ_F5 F5 3
60.4R
IN
CKEB1 J3 CKE# VSSQ_H13 H13
1 2 CLKA0B F10 1 2 CLKA1B F10 1 2 CLKB0B F10 J11 K2

01 i( AL
R2003 VSSQ_F10 R2203 VSSQ_F10 R2403 VSSQ_F10 3 IN CK# VSSQ_K2 +MVDD
1 60.4R
2 CLKA0 H2 1 60.4R
2 CLKA1 H2 1 60.4R
2 CLKB0 H2 J12 K13 GND
R2004 VSSQ_H2 R2204 VSSQ_H2 R2404 VSSQ_H2 3 CK VSSQ_K13
60.4R 60.4R 60.4R
IN
3 IN
CKEA0 J3 CKE# VSSQ_H13 H13 3 IN
CKEA1 J3 CKE# VSSQ_H13 H13 3 IN
CKEB0 J3 CKE# VSSQ_H13 H13 VSSQ_M5 M5
3 IN
J11 CK# VSSQ_K2 K2 3 IN
J11 CK# VSSQ_K2 K2 3 IN
J11 CK# VSSQ_K2 K2 VSSQ_M10 M10
3 IN
J12 CK VSSQ_K13 K13 3 IN
J12 CK VSSQ_K13 K13 3 IN
J12 CK VSSQ_K13 K13 3 IN
CSB1B_0 G12 CS#__WE# VSSQ_N1 N1
VSSQ_M5 M5 VSSQ_M5 M5 VSSQ_M5 M5 3 IN
WEB1B L12 WE#__CS# VSSQ_N3 N3 C2135 C2136 C2137 C2127 C2131

VSSQ_M10 M10 VSSQ_M10 M10 VSSQ_M10 M10 VSSQ_N12 N12 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF

3 IN
CSA0B_0 G12 CS#__WE# VSSQ_N1 N1 3 IN
CSA1B_0 G12 CS#__WE# VSSQ_N1 N1 3 IN
CSB0B_0 G12 CS#__WE# VSSQ_N1 N1 VSSQ_N14 N14 4V 4V 4V 4V 4V

3 IN
WEA0B L12 WE#__CS# VSSQ_N3 N3 3 IN
WEA1B L12 WE#__CS# VSSQ_N3 N3 3 IN
WEB0B L12 WE#__CS# VSSQ_N3 N3 1 2
R2700 1% J13 UNNAMED_4_170BALLGDDR5_I308_ZQ
ZQ VSSQ_R1 R1
VSSQ_N12 N12 VSSQ_N12 N12 VSSQ_N12 N12 120R J10 SEN VSSQ_R3 R3
VSSQ_N14 N14 VSSQ_N14 N14 VSSQ_N14 N14 VSSQ_R4 R4

(0
1 2
R2002 1% J13 UNNAMED_4_170BALLGDDR5_I13_ZQ
ZQ VSSQ_R1 R1 1 2
R2302 1% J13 UNNAMED_4_170BALLGDDR5_I27_ZQ
ZQ VSSQ_R1 R1 1 2
R2400 1% J13 UNNAMED_4_170BALLGDDR5_I171_ZQ
ZQ VSSQ_R1 R1 VSSQ_R11 R11
120R J10 R3 120R J10 R3 120R J10 R3 DRAM_RST J2 R12

裴
SEN VSSQ_R3 SEN VSSQ_R3 SEN VSSQ_R3 3,4 IN RESET# VSSQ_R12 +MVDD
VSSQ_R4 R4 VSSQ_R4 R4 VSSQ_R4 R4 J1 MF VSSQ_R14 R14 GND

VSSQ_R11 R11 VSSQ_R11 R11 VSSQ_R11 R11 VSSQ_V1 V1 11 9 4 +MVDD

3,4 IN
DRAM_RST J2 RESET# VSSQ_R12 R123,4 IN
DRAM_RST J2 RESET# VSSQ_R12 R12 3,4 IN
DRAM_RST J2 RESET# VSSQ_R12 R12 VSSQ_V3 V3
J1 MF VSSQ_R14 R14 J1 MF VSSQ_R14 R14 J1 MF VSSQ_R14 R14 VSSQ_V12 V12
VSSQ_V1 V1 VSSQ_V1 V1 VSSQ_V1 V1 VSSQ_V14 V14
VSSQ_V3 V3 VSSQ_V3 V3 VSSQ_V3 V3 A5 Vpp_NC

1
C2145

C2100

C2102

C2103

C2104

C2106

C2107

C2108

C2109

C2110

C2111

C2112

C2113

C2114

C2116

C2117

C2118
VSSQ_V12 V12 VSSQ_V12 V12 VSSQ_V12 V12 +MVDD 1
R2699 2 1% V5 Vpp_NC1

00 RM 亮
V14 V14 V14 1 2.37K
2 B5
VSSQ_V14 VSSQ_V14 VSSQ_V14 R2698 1% VSS_B5
A5 A5 A5 1 5.49K
2 VREFD1_B1 A10 B10
Vpp_NC Vpp_NC Vpp_NC C2698 VREFD1 VSS_B10 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
1 2 V5 1 2 V5 1 2 V5 1uF V10 D10
+MVDD R2099 1% Vpp_NC1 +MVDD R2299 1% Vpp_NC1 +MVDD R2499 1% Vpp_NC1 VREFD2 VSS_D10

2
6.3V
1 2.37K
2 B5 1 2.37K
2 B5 1 2.37K
2 B5 G5
R2098 1% VSS_B5 R2298 1% VSS_B5 R2498 1% VSS_B5 VSS_G5

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF
1
C2003 2
5.49K VREFD1_A0 A10 VREFD1 VSS_B10 B10 1
C2298 2
5.49K VREFD1_A1 A10 VREFD1 VSS_B10 B10 C2498 1 2
5.49K VREFD1_B0 A10 VREFD1 VSS_B10 B10 VSS_G10 G10
1uF V10 D10 1uF V10 D10 1uF V10 D10 H1
6.3V VREFD2 VSS_D10 6.3V VREFD2 VSS_D10 6.3V VREFD2 VSS_D10 VSS_H1
VSS_G5 G5 VSS_G5 G5 VSS_G5 G5 VSS_H14 H14
VSS_G10 G10 VSS_G10 G10 VSS_G10 G10 VSS_K1 K1 +MVDD
C VSS_H1 H1 VSS_H1 H1 VSS_H1 H1 J14 VREFC VSS_K14 K14 +MVDD
GND C

11 A工 樂
VSS_H14 H14 VSS_H14 H14 VSS_H14 H14 VSS_L5 L5 11 9 4 +MVDD

VSS_K1 K1 VSS_K1 K1 VSS_K1 K1 +MVDD R2709 1 2 1% VSS_L10 L10

J14 K14 J14 K14 J14 K14 1 2.37K
2 P10
VREFC VSS_K14 VREFC VSS_K14 VREFC VSS_K14 R2710 1% VSS_P10
L5 L5 L5 1 5.49K
2 VREFC_B1 J4 T5
VSS_L5 VSS_L5 VSS_L5 C2700 ABI# VSS_T5
VSS_L10 L10 VSS_L10 L10 +MVDD R2497 1 1% 2 1% VSS_L10 L10 1uF
6.3V VSS_T10 T10 C2236 C2237 C2238 C2227 C2235

1
C2124

C2125

C2130
+MVDD R2297 1 1% 2 1% VSS_P10 P10 +MVDD R2097 1 1%
2 1% VSS_P10 P10 R2496 1 2
2.37K
1% VSS_P10 P10 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF
1 2.37K
2 J4 T5 1 2.37K
2 J4 T5 5.49K
C2496 1 2 J4 T5
VREFC_B0 4V 4V 4V 4V 4V
R2296 1% ABI# VSS_T5 R2096 1% ABI# VSS_T5 ABI# VSS_T5
1 5.49K
2 VREFC_A0 T10 1 5.49K
2 VREFC_A1 T10 1uF T10 ADBIB1
C2296 VSS_T10 C2098 VSS_T10 VSS_T10 3
1uF 1uF
6.3V IN 6.3V 6.3V 6.3V

2
6.3V 6.3V

10uF

10uF

10uF
60
ADBIA0 ADBIA1 ADBIB0
3 IN 3 IN 3 IN

)
GND GND

程
+MVDD

11 9 4 +MVDD

1)

1
C2205
課
6.3V

2
+MVDD

1uF
+MVDD
11 9 4 +MVDD +MVDD

11 9 4 +MVDD GND

+MVDD +MVDD +MVDD

C2416

C2417

C2418

C2419

C2420

C2421

C2422

C2423

C2424

C2425

C2426
1

+MVDD +MVDD +MVDD

MC2517

11 9 4 11 9 4 11 9 4
C2500

C2501

C2502

C2503

C2504

C2505

C2507

C2508

C2513

C2518
1

MC2516
C2708

C2709

C2710

C2712

C2714

C2716

C2718

C2720
1

6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V MC2510
1uF 1uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2

1
C2337

C2338

C2339

C2032
2

6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V

C2030

C2031

C2233

C2230
1

1
1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

2
1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

6.3V 6.3V 6.3V

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

10uF

10uF
6.3V 6.3V 6.3V 6.3V 6.3V

2
10uF

10uF

10uF

10uF

10uF

10uF
+MVDD +MVDD

2
+MVDD 11 9 4 +MVDD GND 11 9 4 +MVDD

+MVDD 11 9 4 +MVDD GND

GND
D +MVDD
GND
GND
D
GND
1

1
C2437

C2440

C2429

C2738

C2739

C2536 C2537 C2531 C2526

C2530

C2533

C2534
1

4.7uF 4.7uF 4.7uF 4.7uF C2730 C2733 C2726 C2727

4V 4V 4V 4V 4.7uF 4.7uF 4.7uF 4.7uF
6.3V 6.3V 6.3V 6.3V 6.3V
4V 4V 4V 4V
6.3V 6.3V 6.3V
2

2
10uF

10uF

10uF

10uF

10uF
2

2
10uF

10uF

10uF

GND
GND
GND
GND

GND

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Thursday, July 04, 2013 Sheet 4 of 20

1 2 3 4 5 6 7 8
 Oland GPIOs Strap CF XTAL OSC

PN 2280007900G for 1Mbit (PM25LV010A-100SCE)

U1E

00
BIOS1
+3.3V_BUS 60mA +3.3V_BUS VIDEO BIOS
AF23 VDDR3 GPIO_0 AH20 GPIO_0 FIRMWARE
OUT

1
AF24 VDDR3 GPIO_1 AH18 GPIO_1
OUT
BIOS

C1 AG23 VDDR3 GPIO_2 AN16 GPIO_2

OUT

1
1uF R14
6.3V
AG24 VDDR3

2
M
BIOS(113?)
GPIO_5_AC_BATT AH17 +3.3V_BUS
4.7K U11
GPIO_6_TACH AJ17 GPIO6
OUT 16

2
15,17
SCL AK26 SCL GPIO_7_BLON AK17 GPIO_7_VDDCI_VID0
12
GPIO_22_R 1 CE VDD 8

0
OUT OUT

1
15,17
SDA AJ26 SDA GPIO_8_ROMSO AJ13 GPIO_8 3 6
RP1C 5 GPIO_8_R 2 SO HOLD 7
BI 33R
33R
GPIO_9_ROMSI AH15 GPIO_9 1 8
RP1A 3 WP SCK 6 C4

RD 17 SI
AJ16 GPIO_10 2 7 4 5 0.1uF
GPIO_10_ROMSCK RP1B GND SI GPIO_9_R
6.3V
AK16 33R
GPIO_11
GPIO_11 5

2
GPIO_12 AL16 GPIO_12
5 PM25LD010C-SCE

1,17
SMBCLK AJ23 SMBCLK GPIO_13 AM16 GPIO_13
5 5 GPIO_9_R
OUT
1,17 BI
SMBDATA AH23 SMBDATA GPIO_14_HPD2 AM14 GPIO_14_HPD2
IN 8
GPIO_10_R

GPIO_15_PWRCNTL_0 AM13 GPIO_15_VDDC_VID0

OUT 15
GPIO_16 AK14 GPIO_16_VDDCI_VID1
OUT 12 PIN BASED STRAPS
GPIO_17_THERMAL_INT AG30 GPIO_17_THERMINT
17
IN
GPIO_18_HPD3 AN14 +3.3V_BUS STRAP_TX_CFG_DRV_FULL_SWING
GPIO_19_CTF AM17 GPIO_19_CTF
OUT 16 Strap to control Transmitter Full/Half Swing for Mode

(C 96 C
4.7K
AF35 NC#75 GPIO_20_PWRCNTL_1 AL13 GPIO_20_VDDC_VID1
15 DNI 1
R1 2 GPIO_0
5 0=Transmitter Half Swing Enabled.
OUT 4.7K
AG36 NC#74 GPIO_21 AJ14 GPIO_21_MVDD_VID
11 MR1 1 2 1=Transmitter Full Swing Enabled.
OUT
AJ27 RSVD#AJ27 GPIO_22_ROMCSB AK13 GPIO_22 4 5
RP1D
AK27 AG32 33R GPIO_29_VDDC_VID2
RSVD#AK27 GPIO_29 15 STRAP_TX_DEEMPH_EN
OUT 4.7K
GPIO_30 AG33 GPIO_30_VDDC_VID3
15 DNI 1
R2 2 GPIO_1
GPIO_1 5 PCI Express Interface Transmitter De-emphasis Enable
OUT 4.7K
AN36 NC#73 CLKREQB AN13 CLKREQB
5 MR2 1 2 0: Tx de-emphasis disabled
AP37 NC#72 GENERICA AJ19 1: Tx de-emphasis enabled
GENERICB AK19 DNI PCIe Gen3 capability
4.7K
+1.8V GENERICC AJ20 DNI 1
R3 2 GPIO_2
GPIO_2 5 1 = PCIe Gen3 is supported Cape Verde default 0

)2 7 ON
4.7K
GENERICD AK20 MR3 1 2 0 = PCIe Gen3 is not supported
1 GENERICE_HPD4 AJ24
GENERICF_HPD5 AH26 DNI VGA DISABLE : 1 for disable (set to 0 for normal operation)
4.7K
R98 GENERICG_HPD6 AH24 DNI 1
R5 2 GPIO_9_R
GPIO_9_R 5
1K 4.7K
HPD1 MR5 1 2
HPD1 AK24 7
IN
1 2

TEST_PG AH16 TEST_PG GPIO(13,12,11) - CONFIG[2..0]

4.7K
DNI 1
R6 2 GPIO_13
GPIO_13 5 100 - 512Kbit M25P05A (ST)
4.7K
MR6 1 2 DNI CONFIG[2] 101 - 1Mbit M25P10A (ST)
R33
1K 4.7K 101 - 2Mbit M25P20 (ST)
1 2 GPIO_12

F
DNI R7 GPIO_12 5
101 - 4Mbit M25P40 (ST)

0
4.7K
MR7 1 2 CONFIG[1] 101 - 8Mbit M25P80 (ST)
2

4.7K
OLAND M2 GDDR5 DNI 1
R8 2 GPIO_11 GPIO_11
5 100 - 512Kbit Pm25LV512 (Chingis)
4.7K
MR8 1 2 CONFIG[0] 101 - 1Mbit Pm25LV010 (Chingis)

吳 13 jo ID
VIP_DEVICE_STRAP_DIS
V2SYNC H2SYNC ? RESERVED:

Internal use only. Other logic must not affect these signals
1R4 2 10K CLKREQB
5
during RESET.

AUD[1:0]:

積 09 ne EN
4.7K
DNI R10 1 2 V1SYNC
AUD[1] 6 HSYNC 00 - No audio function;
4.7K OUT
MR101 2 AUD[0] VSYNC 01 - Audio for DisplayPort only;
10 - Audio for DisplayPort and HDMI if dongle is detected;
DNI 11 - Audio for both DisplayPort and HDMI.
U1D 4.7K
DNI 1
R11 2 H1SYNC
OUT 6 HDMI must only be enabled on systems that are legally entitled
4.7K
+1.8V MR111 2 . It is the responsibility of the system designer to
ensure that the system is entitled to support this feature
180mA 10mA/bit AF15 VDDR4 DBG_DATA0 AU1
AG11 VDDR4 DBG_DATA1 AU3
1

4.7K
AG13 AW3

源 05 pe TI
VDDR4 DBG_DATA2 R13 1 2 GPIO_8_R
GPIO_8_R
5 Internal use only. Other logic must not

C6 AD12 VDDR4 DBG_DATA3 AP6 affect these signals

1uF 4.7K during RESET.
6.3V
AF11 VDDR4 DBG_DATA4 AW5 MR131 2
AG15 VDDR4 DBG_DATA5 AU5
2

AF12 VDDR4 DBG_DATA6 AR6

AF13 VDDR4 DBG_DATA7 AW6
DBG_DATA8 AU6
DBG_DATA9 AT7 DNI
4.7K
DBG_DATA10 AV7 DNI R95 1 2 GENLK_VSYNC
IN 6 CEC_DIS
DBG_DATA11 AN7

01 i( AL
4.7K
MR951 2
DBG_DATA12 AV9 DNI
AR1 NC#1 DBG_DATA13 AT9 SMS_EN_HARD
4.7K
DBG_DATA14 AR10 R96 1 2 GENLK_CLK
IN 6
AP8 DBG_CNTL0 DBG_DATA15 AW10
AW8 NC#2 DBG_DATA16 AU10 DNI
4.7K
AR3 NC#3 DBG_DATA17 AP10 MR961 2
DBG_DATA18 AV11
AR8 NC#4 DBG_DATA19 AT11
AU8 NC#5 DBG_DATA20 AR12
AW12

(0
DBG_DATA21
+1.8V DBG_DATA22 AU12

裴
1 221R
2 VREFG AH13 AP12
R17 DBG_VREFG DBG_DATA23
110R
R18 1 2
1C8 20.1uF
6.3V OLAND M2 GDDR5

Place the crossfire

00 RM 亮
testpoints near the ASIC and
not the connector

+3.3V_BUS
B2
120R
VDD33_100M 2 1

11 A工 樂
VDD33_27M 2 B31

1
120R

Please pay attention to the grounding Y1 XIN_OSC C9 C10

XOUT_OSC 1 3 0.1uF 0.1uF
strategies for these filter capacitors to 6.3V 6.3V
2 4 +3.3V_BUS

2
maintain a close loop for current. 27.000MHz
U12
U1F
2 1
C11 XTALOUT 10 XTALIN 1 1 2
C12

2
12pF 12pF
+1.8V 50V 50V
75mA AM32 DP_VDDR VDD_100M 4 R20 R21

60
AF30 2 5.1K 5.1K
R22 1 5 8
XO_IN2 CLK_100M
NC_XTAL_PVDD 100M_OUT VDD_27M
1

0R

1
MR22
C13 C14 C15 NC_XTAL_PVSS AF31 2 1 SS_SEL0 7 SS_SEL0
10uF 1uF 0.1uF AN32 0R 3 SS_SEL1
6.3V 6.3V 6.3V DP_VSSR SS_SEL1
2 R26 1
CLK_27M 9

程
27M_OUT
2

2
0R 6
GND_100M
+0.95V XO_IN2 AW35 GND_27M 2 R28 R29
MR26 5.1K 5.1K
140mA 1 2 GND_PAD 11
AN31 0R
DP_VDDC

1
1

1)
DNI SL16010DC

C45
C31 C16 C17 XO_IN AW34 XO_IN
4.7uF 1uF 0.1uF 2 1
6.3V 6.3V 6.3V
12pF
+1.8V
2

1 2

1 2

50V
1 B52 75mA
+SPLL_PVDD AM10 SPLL_PVDD
1

課
120R
R37

C18 C19 C20

1M

3
4
27.000MHz
4.7uF 1uF 0.1uF AN10 AV33 XTALIN
6.3V 6.3V 6.3V SPLL_PVSS XTALIN

Y2
2

1
2

C44
+0.95V
1 B62
+SPLL_VDDC
150mA AN9 SPLL_VDDC XTALOUT AU34 XTALOUT 2 R36 1 2 1
UNNAMED_21_CAP_I204_B
1

120R 0R 12pF
50V
C21 C22 route 50ohms single-ended/100ohms diff
1uF 0.1uF and keep short
6.3V 6.3V
+1.8V
1 2

1 2

1 B72
UNNAMED_21_BEAD_I209_B
200mA CLKTESTA AK10 CLKTESTA 1 C232 CLKTESTA_C 1 R24 2
1

120R H7 0.1uF 51.1R

MPLL_PVDD 6.3V
C24 C34 C35 C26 C27 H8 MPLL_PVDD CLKTESTB AL10 CLKTESTB 1 C282 CLKTESTB_C 1 R25 2
10uF 4.7uF 4.7uF 1uF 0.1uF 0.1uF 51.1R
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2

OLAND M2 GDDR5

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Friday, July 05, 2013 Sheet 5 of 20

 1 2 3 4 5 6 7 8

OPTIONAL ESD PROTECTION DIODES

remove ESD

00
See BOM for qualified filters

Pseudo differential RGB should be routed from the ASIC to the display

connector without switching reference plane or running over split plane.

U1G

0 M
+1.8V B1700
A 2 1 +VDD1DI AC33 VDD1DI R AD39 R_DAC1 A

RD 17 SI
1

1
120R AVSSN AD37

1
C1700 C1701
1uF 0.1uF AC34
6.3V 6.3V VSS1DI R1711 MR1731
150R

2
0R
G AE36 +5V_VESA

2
+1.8V AVSSN AD35 _
R_VGA
6
B1701
2 1 +AVDD_DAC1 AD34 AVDD
G_DAC1

1
120R

(C 96 C

1
C1702 C1703 B AF37 B_DAC1
R1704 R1705
1uF 0.1uF AE34 AE38 2.2K 2.2K
6.3V 6.3V AVSSQ AVSSN R1712 MR1732
150R

2
0R

2
G_VGA
_ 6
HSYNC AC36
R1700
1 2 RSET AB34 RSET VSYNC AC38
499R

)2 7 ON

1
R1707
8
DDC1DATA 2 1 DDCDATA_DAC1_R
8
BI BI
DDCVGACLK AJ30 R1713 MR1733 33R
DDCVGADATA AJ31 150R DDC1CLK 2 R1706
1 DDCCLK_DAC1_R TO DVI CONNECTOR
0R 8 IN OUT 8
33R

2
_
B_VGA
6
OLAND M2 GDDR5

0 F
DDCVGACLK

6
HSYNC_VGA
6

1
吳 13 jo ID

1
DDCVGADATA
6 C1741
12pF

24R
MR1708 50V
_

2
U1700A

2
_
5
H1SYNC 2 3 HSYNC_DAC1_B
OUT
B MC74VHCT125ADTR B

積 09 ne EN

1
+5V_VESA

4
MC74VHCT125ADTR

5
V1SYNC 5 6 VSYNC_DAC1_B
OUT

2
1
U1700B C1760

源 05 pe TI

24R
MR1709

10V
1uF
1
2
C1712
+5V_VESA _
VSYNC_VGA
U1700D 6

1
1 2

14
0.1uF
J1501
6.3V
9 8 C1740
12pF TOWS_TIN_VGAF_1
U1700C 50V
16 SHIELD COMMON

01 i( AL
MC74VHCT125ADTR
_

L1730

L1720
13 10
MC74VHCT125ADTR 6 GND-R
6
6
R_VGA 1 2 1 2 R_VGA_R 1 R 11 ID0
7

1
1 11
UNNAMED_28_CAP_I310_A
7 GND-G
MC74VHCT125ADTR 0.047uH 0.047uH
R1734 C1731 C1734
G_VGA_R 2 G 12SDA
12 11 150R 8pF 12pF 8 GND_B
50V 50V
402 402
B_VGA_R 3 B HSYNC
13

2
U1700E 9 5V

1
4 ID2 VSYNC
14

(0
D2011

L1731

L1721
10 GND

裴
10
6
G_VGA 1 2 1 2 5 GND 15SCL

1
5 15
0.047uH
UNNAMED_28_CAP_I308_A
0.047uH VVVV302-01S

1
R1735 C1732 C1735 D4501

2
150R 8pF
50V
12pF
50V
17 SHIELD
402
402

2
VVVV302-01S change to VGA type-A

1
00 RM 亮
D4502

L1732

L1722

2
+3.3V_BUS
6
B_VGA 1 2 1 2

1
0.047uH VVVV302-01S
C 0.047uH
UNNAMED_28_CAP_I304_A

HSYNC_VGA
C
R1736 C1733 C1736

2
150R 8pF 12pF
402 50V 402 50V
U1H

2
1
VSYNC_VGA

11 A工 樂
MLPS R2749

1
SI2304DS
R1051 1 2 5.1K PS_0 27K D4505 D4506
+1.8V 6 +5V_VESA

Q2525
R1052 1 2 5.1K

2
C1052 1 2 0.1uF 16V 6
PS_0 AM34 PS_0
VVVV302-01S VVVV302-01S
6
PS_1 AD31 PS_1 CEC_1 AC30 CEC1 2 3 CEC1_HDMI
7
IN

2
1

1
MLPS 6
PS_2 AG31 PS_2
+1.8V R1053 1 2 5.1K PS_1
6 R1744 R1745

60
R1054 1 2 5.1K PS_3 AD33 2.2K
6 PS_3
1 2 0.1uF AD29 GENLK_CLK 2.2K

)
C1054 16V GENLK_CLK OUT 5

2
GENLK_VSYNC AC29 GENLK_VSYNC
5
TMDP_EN
7,8
OUT IN R1746
DDCVGACLK 2 1 DDCCLK_VGA

程
IN
33R
MLPS
R1747
+1.8V R1055 1 2 5.1K PS_2
6 DDCVGADATA 2 1 DDCDATA_VGA
BI
R1056 1 2 5.1K AF32 NC#25 SWAPLOCKA AJ21 33R

1
1)
C1056 1 2 0.1uF 16V V13 NC#28 SWAPLOCKB AK21 D4503 D4504
U13 NC#27
AG21 NC#26
AC32 NC#24 VVVV302-01S VVVV302-01S

課
MLPS AA29 NC#23

2
+1.8V R1057 1 2 5.1K PS_3
6 AC31 NC_SVI2
R1058 1 2 5.1K AD30 NC_SVI2
C1058 1 2 0.1uF 16V AD32 NC_SVI2 NC#39 AF33

OLAND M2 GDDR5

D D

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Friday, July 05, 2013 Sheet 6 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

OPTIONAL ESD protection diodes

00
remove ESD
U1I

NC#6 AH12
NC#7 AP13

M
NC#8 AP14
NC#9 AP15

0
NC#10 AT13
A NC#11 AN24 A

RD 17 SI
AN17 DP_VSS NC#12 AP20
AN19 DP_VSS NC#13 AP21
AN27 DP_VSS NC#14 AP22
AN29 DP_VSS NC#15 AP23
AP16 DP_VSS NC#16 AP24
AP17 DP_VSS NC#17 AP25
AP18 DP_VSS NC#18 AP26
AP19 DP_VSS NC#19 AU18
AP27 AU28

(C 96 C
DP_VSS NC#20
AP28 DP_VSS NC#21 AV19
AP29 DP_VSS NC#22 AV29
AP30 DP_VSS NC#29 L27
AR18 DP_VSS NC#30 N12
AR28 DP_VSS NC#31 AG12
AV17 DP_VSS NC#32 M12
AV27 DP_VSS NC#40 AR24

)2 7 ON
AW14 DP_VSS NC#41 AR14
AW16 DP_VSS NC#42 AT25
AW20 DP_VSS NC#43 AT15
AW22 DP_VSS NC#44 AV25
AW24 DP_VSS NC#45 AV15
AW26 DP_VSS NC#46 AU26 8
DPA_A0P 1 2
C3530 DPA_0P
IN 0.1uF
AW30 DP_VSS NC#47 AU16
AW32 DP_VSS NC#48 AR26 8
DPA_A0N 1 _ 2
C3531 DPA_0N
IN 0.1uF
AR16

F
NC#49

0
NC#50 AT27 8
DPA_A1P _ 1 2
C3532 DPA_1P
IN 0.1uF
AL30 NC#AL30 NC#51 AT17
AL29 NC#AL29 NC#52 AU30 8
DPA_A1N 1 _ 2
C3533 DPA_1N
IN 0.1uF
AN21 AR20

吳 13 jo ID
NC#AN21 NC#53
AK30 NC#AK30 NC#54 AV31 8
DPA_A2P 1 2
C3534 _ DPA_2P
IN 0.1uF
AM30 NC#AM30 NC#55 AT21
AM29 NC#AM29 NC#56 AT31 8
DPA_A2N 1 _ 2
C3536 DPA_2N
IN 0.1uF
AM21 NC#AM21 NC#57 AV21
AK29 NC#AK29 NC#58 AR32 8
DPA_A3P _ 1 2
C3537 DPA_3P
IN 0.1uF
NC#59 AU22
AW28 NC#AW28 NC#60 AU32 8
DPA_A3N 1 _ 2
C3538 DPA_3N
IN
B AW18 NC#AW18 NC#61 AR22 14 8 7 0.1uF
B

積 09 ne EN
NC#62 AT33 _
NC#63 AT23
NC#64 AV23
NC#65 AU24

1
NC#66 AT29
NC#67 AR30 R2713 R2714 R2715 R2716 R2717 R2718 R2719 R2720
499R 499R 499R 499R 499R 499R 499R 499R
NC#68 AV13
NC#69 AU14

2
源 05 pe TI
NC#70 AT19 DPA_GND

NC#71 AU20

3
Q2701
TMDP_EN 1 2N7002E
OLAND M2 GDDR5 6,8 IN

01 i( AL
_

2
GND

1 2
remove colay DP

(0
+5V_VESA R2701
+5V_VESA 2.2K
7

裴
1 _ R2703 2
2.2K
7 +5V_VESA
_

8
DDC2CLK 1 0R 2
R2528 DPA_AUXP
IN

1
00 RM 亮
_ C2722

8 DDC2DATA 1 0R 2
R2529 DPA_AUXN
1uF
BI
_

2
1

1
C _ D2005 D4507 C
+3.3V_BUS ESD-MLVG04025R0QV05BP
ESD-MLVG04025R0QV05BP
+3.3V_BUS VVVV302-01S VVVV302-01S

2
11 A工 樂
7

3
MJ2501
Q2513 1 1 UNNAMED_7_NPN_I268_B
R25272 HPD_DPA 19
MMBT3904 10K
18 HP_DET
_ 17 +5V

2
HPD1 GND X1
5 OUT _ SHELL1
16
SDA

1
15 X2
R2530
SCL SHELL2

60
10K
14 8 7 14 MEC1
CEC1_HDMI 13 NC MEC1

)
6 IN

2
GND CE Remote
_
DPA_3N 12

程
11 CK-
DPA_3P 10 CK_Shield
CK+
DPA_2N 9
D0-

1)
8
DPA_2P 7 D0_Shield
D0+ MEC2
DPA_1N 6 MEC2
D1-

課
5 X3
DPA_1P 4 D1_Shield SHELL3
D1+ X4
DPA_0N 3 SHELL4
2 D2-
DPA_0P 1 D2_Shield
D2+
HDMI19PSM_BLACK-RH-5

D D

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Friday, July 05, 2013 Sheet 7 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

U1J
+0.95V

00
TXCAP_DPA3P AP34 DPA_A3P
7
10 2 +0.95V AK33 DP_VDDC TXCAM_DPA3N AR34 DPA_A3N
7 7
AK34 DP_VDDC TX0P_DPA2P AW37 DPA_A2P
7 7
AL33 DP_VDDC TX0M_DPA2N AU35 DPA_A2N
7 7

1
10V AM33 DP_VDDC TX1P_DPA1P AR37 DPA_A1P
7 7
C1523 C1524 C1525 AN33 DP_VDDC TX1M_DPA1N AU39 DPA_A1N
7 7

M
4.7uF 1uF AP31 AP35 DPA_A0P
6.3V 6.3V DP_VDDC TX2P_DPA0P 7 7
0.1uF
AP32 DP_VDDC TX2M_DPA0N AR35 DPA_A0N
7 7

2
0
AP33 DP_VDDC 7
A TXCBP_DPB3P AK35 DPB_TXCAP
8
A

RD 17 SI
+1.8V TXCBM_DPB3N AL36 DPB_TXCAN
8
TX3P_DPB2P AJ38 DPB_TX0P
8
16 14 9 2 +1.8V AF34 DP_VDDR TX3M_DPB2N AK37 DPB_TX0N
8
AG34 DP_VDDR TX4P_DPB1P AH35 DPB_TX1P
8

1
10V AH34 DP_VDDR TX4M_DPB1N AJ36 DPB_TX1N
8
C1520 C1521 C1522 AJ34 DP_VDDR TX5P_DPB0P AG38 DPB_TX2P
8
4.7uF 1uF 0.1uF
6.3V 6.3V
AL38 DP_VDDR TX5M_DPB0N AH37 DPB_TX2N
8
AM37 DP_VDDR

2
(C 96 C AF39
AH39
DP_VSSR
DP_VSSR

)2 7 ON
AK39 DP_VSSR
AL34 DP_VSSR
AM35 DP_VSSR
AN34 DP_VSSR AUX1N AL27
AN38 DP_VSSR AUX1P AM27
AP39 DP_VSSR
AR39 DP_VSSR DDC1CLK AM26 DDC1CLK
6
OUT
AU37 DP_VSSR DDC1DATA AN26 DDC1DATA
6
BI

0 F
AUX2N AM20
AN20

吳 13 jo ID
AUX2P DPB_GND
1
BTX2P 2
R1501
AM19 DDC2CLK DPB_TX2P 1 2 499R BTX2P
DDC2CLK OUT 8 7 C1501 8
2 1 DPEF_CALR AM39 AL19 DDC2DATA 0.1uF
R1500 DP_CALR DDC2DATA BI 7 6.3V
150R DPB_TX2N 1 2 BTX2M
8 C1502 8
0.1uF 2 1 1 2
6.3V
BTX1P R1503 BTX2M R1502
DPB_TX1P 1 2 499R 499R BTX1P
8 C1503 8
OLAND M2 GDDR5 0.1uF
6.3V
B 8
DPB_TX1N 1 2
C1504
BTX1M
8 B

積 09 ne EN
0.1uF 2 1 2 1
6.3V R1505 BTX1M R1504
DPB_TX0P 1 2 499R 499R BTX0P
8 C1505 8
0.1uF
6.3V
8
DPB_TX0N 1 2
C1506
BTX0M
8
0.1uF 2 1 2 1
6.3V
BTXCP R1507 BTX0M R1506
DPB_TXCAP 1 2 499R 499R BTXCP
8 C1507 8
0.1uF
6.3V
8
DPB_TXCAN 1 2
C1508 BTXCM
BTXCM
8

源 05 pe TI
0.1uF 2 1
6.3V R1508
499R
+12V_BUS

16 15 14 13 11 1 +12V_BUS

3
R1544

01 i( AL
10K
Q1501
1 2N7002E

2
14

TMDP_EN
6,7 OUT

2
1
OPTIONAL ESD PROTECTION DIODES C1543
0.1uF
16V 8
U102 8

2
1 NC 10

(0
BTX0P BTX0P
BTX0M 2 NC 9
BTX0M

裴
BTXCP 4 7 BTXCP
NC
BTXCM 5 NC 6
BTXCM

ESD-ESD3V3U4ULC-RH
3

+5V_VESA

00 RM 亮
VVVV302-01S
D0G-05A0300-I14 J1500
ESD_2_5X1
COMMON X1 SHIELD1
C C
8 X2 SHIELD2
MEC1 SHIELD3
U103 +5V_VESA
MEC2 SHIELD4
BTX2P 1 NC 10
BTX2P
2 TX0-
NC 9 17
BTX2M BTX2M BTX0M

11 A工 樂
BTX0P 18 TX0+
BTX1P 4 7 BTX1P BTX1M 9 TX1-
BTX1M 5 NC 6 BTX1M BTX1P 10 TX1+ 17 9 1
NC TX2-
BTX2M 1
ESD-ESD3V3U4ULC-RH BTX2P 2 TX2+
3

3 SHLD24
VVVV302-01S 11 SHLD13
D0G-05A0300-I14 19 SHLD05

60
ESD_2_5X1 12 TX3-
COMMON 13 TX3+

)
4 TX4-
5 TX4+

程
20 TX5-
21 TX5+
DDCCLK_DAC1_R 6 DDCC
6 IN
DDCD
6
DDCDATA_DAC1_R 7
BI

1)
2 1
C1526 14 VDDC
1uF 15 GND
10V
22 SHLDC
+3.3V_BUS
BTXCM 24 TXC-

課
BTXCP 23 TXC+
17 16 15 14 10 7 1 +3.3V_BUS 8 VSYNC
16 HPD
24 16 8

Q1502
3 1 HPD2_IN 1 2
R1518
MMBT3904 10K
2

GPIO_14_HPD2
5 OUT
1

D D
R1517
10K
2

DVI_24P-5_451

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Friday, July 05, 2013 Sheet 8 of 20

1 2 3 4 5 6 7 8
 +VDDC

00
Oland Power & GND

1
C117 C118 C119 C88 C89 C106 C107 C108
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V

2
0 M

1
RD 17 SI
C109 C110 C111 C112 C113 C114 C115 C116
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
+MVDD 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
4 +MVDD U1L

2
11
U1K

B9 VSS VSS A3
AC7 VDDR1 VDDC AA15 C1 VSS VSS A37

1
(C 96 C
AD11 VDDR1 VDDC AA17 C39 VSS VSS AA16
AF7 VDDR1 VDDC AA20 C182 C168 C169 C170 C171 C172 C173 C85 E35 VSS VSS AA18
AG10 AA22 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF E5 AA2
VDDR1 VDDC 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VSS VSS
AJ7 VDDR1 VDDC AA24 F11 VSS VSS AA21

2
AK8 VDDR1 VDDC AA27 F13 VSS VSS AA23
AL9 VDDR1 VDDC AB16 F15 VSS VSS AA26

1
G11 VDDR1 VDDC AB18 F17 VSS VSS AA28
G14 VDDR1 VDDC AB21 C183 C184 C185 C186 C187 C188 C189 C190 C79 F19 VSS VSS AA6

)2 7 ON
1
G17 AB23 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF F21 AB12
VDDR1 VDDC 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VSS VSS
C141 G20 VDDR1 VDDC AB26 F23 VSS VSS AB15

2
0.1uF G23 AB28 F25 AB17
10V VDDR1 VDDC VSS VSS
G26 VDDR1 VDDC AC17 F27 VSS VSS AB20

2
G29 VDDR1 VDDC AC20 F29 VSS VSS AB22
H10 VDDR1 VDDC AC22 F31 VSS VSS AB24
J7 VDDR1 VDDC AC24 F33 VSS VSS AB27
1

1
J9 VDDR1 VDDC AC27 F7 VSS VSS AC11

F
K11 AD18 F9 AC13

0
C134 C135 C136 C137 C138 C139 C140 VDDR1 VDDC C176 C177 C178 C191 C301 C302 VSS VSS
1uF 1uF 1uF 1uF 1uF 1uF 1uF K13 AD21 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF G2 AC16
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VDDR1 VDDC 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VSS VSS
K8 VDDR1 VDDC AD23 G6 VSS VSS AC18
2

1 2

1 2

1 2

1 2

1 2

1 2
L12 VDDR1 VDDC AD26 H9 VSS VSS AC2

吳 13 jo ID
L16 VDDR1 VDDC AF17 J2 VSS VSS AC21

1
L21 VDDR1 VDDC AF20 MC176 MC177 MC178 MC191 MC301 MC302 J27 VSS VSS AC23
1

L23 AF22 10uF 10uF 10uF 10uF 10uF 10uF J6 AC26

MC131 VDDR1 VDDC 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VSS VSS
4.7uF L26 AG16 J8 AC28
MC130 VDDR1 VDDC VSS VSS

2
6.3V
4.7uF L7 AG18 K14 AC6
VDDR1 VDDC Overlap cap pair foorprints (0805 with 0603) VSS VSS
2

6.3V
M11 VDDR1 K7 VSS VSS AD15
2

N11 VDDR1 VDDC AH27 L11 VSS VSS AD17

P7 VDDR1 VDDC Y23 L17 VSS VSS AD20
R11 Y26 L2 AD22

積 09 ne EN
VDDR1 VDDC VSS VSS
1

U11 VDDR1 VDDC AH22 L22 VSS VSS AD24

1
C130 C131 U7 VDDR1 L24 VSS VSS AD27
10uF 10uF Y11 L6 AD9
6.3V 6.3V VDDR1 C192 C300 VSS VSS
Y7 AH28 100uF 100uF M17 AE2
VDDR1 VDDC VSS VSS
2

6.3V 6.3V
VDDC M26 M22 VSS VSS AE6

2
VDDC N24 M24 VSS VSS AF10
VDDC R18 N16 VSS VSS AF16
R21 N18 AF18

源 05 pe TI
VDDC VSS VSS
VDDC R23 N2 VSS VSS AF21
VDDC R26 N21 VSS VSS AG17
VDDC T17 N23 VSS VSS AG2
N26 VSS VSS AG6
VDDC T20 N6 VSS VSS AG9
VDDC T22 R15 VSS VSS AJ10
VDDC T24 R17 VSS VSS AJ11
VDDC U16 R2 VSS VSS AJ2

01 i( AL
VDDC U18 R20 VSS VSS AJ28
VDDC U21 R22 VSS VSS AJ6
VDDC U23 R24 VSS VSS AK11
VDDC U26 R27 VSS VSS AK31
VDDC V17 R6 VSS VSS AK7
VDDC V20 T11 VSS VSS AL11
VDDC V22 T13 VSS VSS AL14
VDDC V24 T16 VSS VSS AL17
VDDC V27 T18 VSS VSS AL2

(0
VDDC Y16 T21 VSS VSS AL20

裴
VDDC Y18 T23 VSS VSS AL23
+1.8V VDDC Y21 T26 VSS VSS AL26
+1.8V VDDC Y28 U15 VSS VSS AL32
16 14 8 2
+0.95V U17 VSS
U2 VSS VSS AL6
250 mA AF26 VDD_CT VSS AL8
AF27 VDD_CT U20 VSS VSS AM11

00 RM 亮
1

AG26 VDD_CT BIF_VDDC T27 U22 VSS VSS AM31

C161 C162 C163 AG27 VDD_CT U24 VSS VSS AM9
1uF 1uF 0.1uF N27 U27 AN11
6.3V 6.3V 6.3V BIF_VDDC VSS VSS

1
M18 VDDCI U6 VSS VSS AN2
2

R13 VDDCI C75 C77 C76 V11 VSS VSS AN30

AA13 4.7uF 1uF 1uF V16 AN6
VDDCI 6.3V 6.3V 6.3V VSS VSS
AB13 VDDCI 2 V18 VSS VSS AN8

2
AC12 VDDCI V21 VSS VSS AP11

11 A工 樂
+VDDCI AC15 VDDCI V23 VSS VSS AP7
Overlap cap pair foorprints AD13 VDDCI V26 VSS VSS AP9
+VDDCI (0805 with 0603) T12 VDDCI W2 VSS VSS AR5
AD16 VDDCI W6 VSS VSS B11
M15 VDDCI Y15 VSS VSS B13
1

M16 VDDCI Y17 VSS VSS B15

C196 MC196 C195 C194 C193 C87 C86 T15 VDDCI Y20 VSS
10uF 4.7uF 1uF 1uF 0.1uF 0.1uF 0.1uF M23 Y22 B17
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VDDCI VSS VSS
N13 Y24 B19

60
VDDCI VSS VSS
2

N15 VDDCI Y27 VSS VSS B21

)
N17 VDDCI AH21 VSS VSS B23
V15 VDDCI TS_A AL31 AG20 VSS VSS B25

程
N20 VDDCI VSS B27
N22 VDDCI AG22 NC VSS B29
Y13 VDDCI A39 VSS_MECH#1 VSS B31
AW1 VSS_MECH#2 VSS B33
R12 AF28 AW39 B7

1)
VDDCI FB_VDDC VSS_MECH#3 VSS
1

R16 VDDCI
MC103 C90 C91 C92 AH29 FB_GND
4.7uF 0.1uF 0.1uF 0.1uF
6.3V 6.3V 6.3V 6.3V
AG28

課
FB_VDDCI
OLAND M2 GDDR5
2

OLAND M2 GDDR5

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connectorci20313 1.0

Date: Thursday, July 04, 2013 Sheet 9 of 20

 1 2 3 4 5 6 7 8

0.95V

00 M
0
A A

RD 17 SI
(C 96 C
)2 7 ON +3.3V_BUS

F
1
7
8
10
14
15
16
17 +3.3V_BUS

0
吳 13 jo ID
1

1
C815 C816 C817 C818
22uF 22uF 4.7uF 0.15uF
6.3V 6.3V 16V 16V

2
change to 0805
1.6uH,20%,DIP,18A,3.25mOhm +0.95V
8 2 +0.95V
B CHK_S2_4_9X4_9 B

積 09 ne EN
L801 2.2uH

1
U801 PIN7 IS PVDD AND PIN8 IS VDD FOR RT8015A 6 PVDD LX#1 3 UNNAMED_8_APW7153B_I36_LX
C820 C821 C822 C823 C824
U801 4 22uF 22uF 10uF 10uF 0.1uF
LX#2
6.3V 6.3V 6.3V 6.3V 10V

1
R813 10K
1 2

2
+3.3V_BUS
R805 7 VDD

源 05 pe TI
17 16 15 14 10 8 7 1 +3.3V_BUS GND 16V 100K
FB 9 15+0.95V_FB C832
0.1uF
1 2UNNAMED_8_CAP_I42_B

2
2 1 8 UNNAMED_8_APW7153B_I36_POK
POK C819 22pF
R819
C805 COMP 10 1
UNNAMED_8_APW7153B_I36_COMP
21 2
UNNAMED_8_CAP_I39_A
50V 50V
1000pF NS800
R809 13K
1 2 1 SHDN/RT 1 2
1

GND 2
324K NS_VIA
R820

01 i( AL
1M
5 PGND TH#11 11
TH#12 12
2

TH#13 13
+0.95V_EN# GND
UP1706S

UNNAMED_8_MOSN_I64_D
3

(0
Q848
+0.95V_EN 1 2N7002E
15

裴
IN
2

1
00 RM 亮
R830
52.3K
402
C 3160169200G 0.955V C

2
RFB2
3160174200G 0.945V

11 A工 樂
60 程 )
D
1) 課 D

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Friday, July 05, 2013 Sheet 10 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

MVDD

00 M
0
A A

RD 17 SI
(C 96 C
)2 7 ON
R243 EMI
2 1
4.7ohm C733
5% DNI 220pF_50V
R238
2 1 DNI
4.7ohm
5%

0 F
C731
220nF_16V 1.6uH,20%,DIP,18A,3.25mOhm OCP fix at MAX 12A +MVDD

1
U4501

吳 13 jo ID
+MVDD_Source

BST
12 2 L701 0.68uH
VIN-1 SW-1 3
SW-2

C342

C338

C339

C340

C341

C4538

C4539

C4540
19
VIN-2 C732 C730 C729 C728 C727 C725 C4544 C4545 C724
+12V_BUS +3.3V_BUS +MVDD 2 R239 1 22uF/6.3V C4536 C4537

2
DNI DNI DNI DNI 14 MVDD_FB 470PF_50V 22uF/6.3V 22uF/6.3V 22uF/6.3V 22uF/6.3V 22uF/6.3V 22uF/6.3V22uF/6.3V 820uF_2.5V 820uF_2.5V
FB 5%
10uF_16V

10uF_16V

10uF_16V

10uF_16V

10uF_16V

10uF_16V

10uF_16V

10uF_16V
B R240 DNI DNI B

積 09 ne EN
1M 10K_%1 DNI DNI
1

Rt

1
R248 R245 6 near source
5.1K 5.1K VINLDO

2
DNI R230
15 5% R231 2 R242 1 MVDD_FB
2

GND EN1 0OHM 5% GND

17 DNI 0OHM 499R_1%
IN
15

1
EN2 NB675

源 05 pe TI
13 5
PG VDDQSEN
1

R246
10K

C334
MVDD_FB
OUT
2

18 7
NC/LP# VTT

01 i( AL

2
1uF_16V
9 +3.3V_BUS R241
VTTSEN

C335
6.65K

1
16 Rb

1
VCC

C331
DNI R751

2
4 10.5K
R752
VTTREF

0.1uF_16V
PGND-1
PGND-2
PGND-3
PGND-4
DNI

2
AGND
10K A1GND

(0
DNI

1
1uF_6.3V
UNNAMED_14_MOSN_I329_D

3
8

10
11
20
21
R244
A1GND GPIO_21_MVDD_VID
Q755
2 1 1 2N7002E
5 IN
5%
0OHM GND DNI

2
2
00 RM 亮
MR752

A1GND 10K

C DNI C

1
GND

A1GND

11 A工 樂
60 程 )
D
1) 課 D

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Thursday, July 11, 2013 Sheet 11 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

VDDCI

00 M
0
A A

RD 17 SI
(C 96 C
)2 7 ON
0 F
R4526 EMI
2 1

吳 13 jo ID
4.7ohm C4517
5% DNI 220pF_50V
R4532 DNI
2 1
4.7ohm
5%
C4525
B 220nF_16V 1.6uH,20%,DIP,18A,3.25mOhm OCP fix at MAX 12A B

積 09 ne EN
+VDDCI

1
U4502

BST
+VDDCI_Source
12 2 L901 1.6uH
VIN-1 SW-1 3
SW-2

C4526

C4508

C4509

C4510

C4511

C4541

C4542

C4543
19
VIN-2 C4516 C4524 C4523 C4522 C4521 C4515 C4546 C4513 C4514 C4512
+12V_BUS +3.3V_BUS +VDDCI 2 R4525 1 820uF_2.5V 22uF/6.3V 22uF/6.3V

2
源 05 pe TI
DNI DNI DNI DNI 14 VDDCI_FB 220PF_50V 22uF/6.3V22uF/6.3V 22uF/6.3V22uF/6.3V22uF/6.3V22uF/6.3V
FB 5%

10uF_16V

10uF_16V

10uF_16V

10uF_16V

10uF_16V

10uF_16V

10uF_16V

10uF_16V
DNI R4527 DNI DNI
1M 10K_%1
1

Rt

1
R4523 R4521 6 near source
5.1K 5.1K VINLDO

2
R4530
DNI 15 5% R4531 2 R4529 1 VDDCI_FB 12
OUT
2

GND EN1 0OHM 5% GND

499R_1%

01 i( AL
IN
15 17 DNI 0OHM

1
EN2 NB675
13 5
PG VDDQSEN
1

R4522
10K

C4519
2

18 7
NC/LP# VTT

(0 裴 1uF_16V
9
VTTSEN

C4520
16
VCC

C4518
4 DNI
VTTREF VDDCI_FB

0.1uF_16V
00 RM 亮
PGND-1
PGND-2
PGND-3
PGND-4
OUT 12

AGND
+3.3V_BUS

1uF_6.3V
C C

1
8

10
11
20
21

1
R956 R951
R4524 10.5K 29.4K
A2GND R950

2
2 1 DNI 30.9K
R952

2
402
5% Rb

11 A工 樂

2
0OHM GND 10K

1
DNI

1
C4548
A2GND 1000pF A2GND
R4536 10V
GPIO_7_VDDCI_VID0 10.2K
5 IN

2
2
GND

60

1
MR952 A2GND

)
C4547
10K 0.1uF
+3.3V_BUS 10V

3
VDDCI Low Side Divider

2
DNI
Q955
1 2N7002E

2
1)
UNNAMED_14_MOSN_I314_D
R953

2
3
10K

DNI

1
Q956 A2GND

課
GPIO_16_VDDCI_VID1 1 2N7002E
5 IN

2
DNI

2
MR953
10K

DNI

1
A2GND

D D

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Thursday, July 11, 2013 Sheet 12 of 20

1 2 3 4 5 6 7 8
 +12V_BUS

16 15 14 13 11
8 1 +12V_BUS

1
C4527
00
L602

10uF_16V
0.33uH

2
8x8 TH
_ Overlap
_ +VDDC_Source +VDDC_Source

0
RD 17 SI
13 +VDDC_SOURCE 13 +VDDC_SOURCE

C676 Input Bulk CAP C682

C4528

C4529

C4530

C4531

C4532

C4533

C4534

C4535
270uF 270uF
COMMON COMMON
20% 20%
16V 16V

10uF_16V

10uF_16V

10uF_16V

10uF_16V

10uF_16V

10uF_16V

10uF_16V

10uF_16V
OCCAP OCCAP

(C 96 C
5.5A@105C 5.5A@105C
Mirrored on PCB 0.010R 0.010R
GND GND GND GND GND
_ _

5
6
7
8
9

5
6
7
8
9
9
8
7
6
5

9
8
7
6
5
_ _ _ _ _ _ _ _

SI7336ADP

SI7336ADP
Mirrored on PCB Mirrored on PCB Mirrored on PCB Mirrored on PCB

Q612

Q602
SI7336ADP

SI7336ADP
Q601

Q611
Input MLCC

)2 7 ON

1
2
3
4

1
2
3
4
603
X _

4
3
2
1

4
3
2
1
QR602
_ X Input MLCC VDDC_UGATE_2 1 2 VDDC_UGATE2_CTR
13
603

5%
0R
13
VDDC_UGATE1_CTR 1 R601 2 VDDC_UGATE_1 +VDDC
_
L601 L612

5%
13 VDDC_PHASE_1 13 VDDC_PHASE_2
0R
_
1 2 13 13 +VDDC 1 2

0 F
0.3uH 0.3uH
_ _

2
1

1
Pass transistor Circuit Q661 and R661 for 8V Gate Drive R606

9
8
7
6
5

9
8
7
6
5

1
吳 13 jo ID
2R2 2R2
NS602 R616

9
8
7
6
5

9
8
7
6
5
805 NS_VIA 805
NS601 NS611

2 1

2 1
NS_VIA NS_VIA

SI7336ADP

SI7336ADP
This Circuit is only for 8V gate drive circuit application. _ NS612 _

2
Q603

Q604
UNNAMED_24_CAP_I70_B NS_VIA UNNAMED_24_CAP_I148_B

SI7336ADP

SI7336ADP
Assume VCC consumes 200mA total including 5VCC providing X X

Q624

Q623
buffered output source a minimum 20mA requirement C606 C616
603 X X 603

1
2200pF 2200pF
P(Q_8VCC)max=(12V-8V)*0.2A=800mW

1
GND

1
_ _
R617

4
3
2
1

4
3
2
1
261R

積 09 ne EN
GND GND
_ _ R607

4
3
2
1

4
3
2
1
1%
261R GND GND
_ _

2
1%
13
VDDC_LGATE1_CTR 1 R603 2 VDDC_LGATE_1
Place across
X Place across

2
0R
+12V_BUS LS MOSFET
X
LS MOSFET
603 603
_
QR604

RC snubber values shown RC snubber values shown R623

VDDC_LGATE_2 1 2 VDDC_LGATE2_CTR
13

CCSN1

CCSN2
CCSP1

CCSP2
16 15

FB_S

FB_S
0R
13 1 2 VDDC_LGATE_1_1 are for reference only, are for reference only,
+12V_BUS 0R
8 1 _
12V Bus power for 12V Gate Drive

tuning is required tuning is required

11

R624
_

源 05 pe TI
14
2

1% Route like differential pair Route like differential pair

VDDC_LGATE_2_2 1 2
3

10K 0R
R661

13

13

13
_

13

13

13
1

Q661 +VDDC
1

SI2304DS 1
R670 X
2R2

BAT54KFILM +VDDC
13
2

R699

Optional D611

01 i( AL
_ X
2 1 1 2
Optional
5%

1
X 0R
Rdroop _
C649 C650 C646 C647 C658 C661 C648 C656 C659 C679
1

0.1uF 0.015uF 10uF 10uF 0.1uF 0.015uF 10uF 10uF 10uF 10uF
2

402 402 402 402

C670 1% 0805 6.3V 0805 6.3V
_ _ _ X _ X X 0805 6.3V _ 0805 6.3V
X 0805 6.3V
X 0805 6.3V

2
2

10uF 100K
16V R664
GND GND GND GND GND GND GND GND GND GND
_ R632 C694
2

1uF
0R

(0
1
13

13

_ 15 X 15
1

2R686 0R

裴
1 VCCDRV
13
BOOT2

X
2
1uF 16V

OUT

GND
IN

UNNAMED_24_CAP_I61_B
Output MLCC Output MLCC
VDDC_EN 2R685X 0R
1 SS_ICOMP
C612

15 13

15
2

_ 2R684_ 0R
1 VDDC_REFIN
15 13 +VDDC
1

D601
VDDC_PWR_GOOD

Optional
VDDC_LGATE2_CTR
VCCDRV

VDDC_PHASE_2

X
VCC

VDDC PWM WHOLE CHIP ENABLE

00 RM 亮
VDDC_UGATE2_CTR

VDDC_REFIN

BAT54KFILM
VDDC_LGATE1_CTR 13 +VDDC
X 13 THE RESISTERS SHARE PAD
1

13
R698

C602 VDDC_PHASE_1
13 13
1 2 1 2
UNNAMED_24_CAP_I5_A

C641 C642 C643 C644

24

23

22

21

20

19
5%

0R 1uF 16V
_ _
820uF_2.5V 820uF_2.5V 820uF_2.5V 820uF_2.5V
PHASE1

PHASE2
LGATE1

LGATE2
VCC

VCCDRV

R634
10K 6.3 x 9 mm, TH 6.3 x 9 mm, TH 6.3 x 9 mm, TH 6.3 x 9 mm, TH
1% _ _ _ _

11 A工 樂
R636
1%
PGD 2

1K

13
VDDC_UGATE1_CTR 1 UGATE1 U601 UGATE2 18 _ 1 2 5VCC
13 14 GND GND GND
UP1610
BOOT1 2 BOOT1 BOOT2 17 X
Overlap the footprints for MR655 and C655
0R
C660 2 1
MR655
2 1 3 5VCC POK 16 C654
R654 5% Output Bulk CAPs
6.3V 1 2X 2
UNNAMED_24_CAP_I38_B
0.0022uF 1
150R
1uF 4 AGND REFIN 15 50V
_ X C655 X +VDDC

60
0R
14
5VCC
1 2 5 MODE 13
SS/EN 14 SS_ICOMP 1 2
0.022uF
OUT

)
MR610

UNNAMED_24_RES_I10_A
25V
1

R610
6 CSP1 FB 13 _ VDDC_FB
15
X IN
1

程
SHARE PAD NS600
2
0R

0R
PIN5 PH2 EN PGND1 25 50V 2 1 FB_S
13
220pF R658
-HI, PH 2 DISABLE,PH1 ENABLED; PGND2 26 C607 C3 NS_VIA
2

-LO, PH 1 AND PH 2 ENABLED. _ PGND3 27 1 X R6532 2 1

UNNAMED_24_CAP_I37_B
C653
2

300R 2200pF
28
COMP
CSN1

CSN2

CSP2

1)
PGND4 R3
IOUT

X X
1
RT

_ R651 _
GND
1K
1 2 1% VDDC_SV 2 R600 1 VDDC_ASIC_FB +VDDC
7

10

11

12
1 CSN1
CSP1

0R
RFB1
_
1
CSN2

603
CSP2

_ _

課
R656
1

0R
UNNAMED_24_CAP_I24_A
2 1 Reserve for C601
Loop Measurement 0.1uF
R605 R615 R662 C638 6.3V
Rdroop

360R 360R 56K 1000PF _ GND

C1 R652
X
2

1% 1% 1% 6.3V

2
10K
_ 1 2
UNNAMED_24_CAP_I28_A
UNNAMED_24_CAP_I28_B
C652 2 1 2 R657 1 5%
2

0.01uF 0R 300R
C604 _ _ C614 _ R1 R696
2 1 2 1 UNNAMED_24_RES_I25_A _ _ X
R656, R657 SHARE PAD
1

1
16V

16V
1uF

1uF

C651 1 2
UNNAMED_24_CAP_I29_B

1
10pF
_ _ R655 R663 C2 _
33.2K 100K _
Close to U601 Type III Compensation
1% 1%
1

6.3V Rdroop option

2

2
1

0.1uF
C605 C615 _ X
0.1uF R655=33.2k---->Freq.=300kHz
R604 6.3V R614 +VDDC LOAD
560R 560R
X X
2

1% 1%
Choosing Different Gate Drive
2

_ _
CCSP2
13 5V Gate Drive
Populate R631,R632 and Do Not Populate R630,R670,C660,R661,Q661
CCSN2
13
8V Gate Drive
CCSN1
13 Populate R630, C660, R661,Q661, and Do Not Populate R631,R632,R670
MICRO-STAR INT'L CO.,LTD
CCSP1
13 12V Gate Drive
Popualte R630,C660,R670, and Do Not Populate R631,R632,R661,Q661 MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Wednesday, July 10, 2013 Sheet 13 of 20

 1 2 3 4 5 6 7 8

00
Linear Regulators
LDO #1: Vin = 3.00V to 3.60V (3.3V +/- 9%) Vout = +1.8V +/- 2%; Iout = 1.6A (TBV) RMS MAX

M
PCB: 50 to 70mm sq. copper area for cooling

0
Regulators for +5V, +5V_VESA and +5V_VESA2
A A

RD 17 SI
(C 96 C
5V regulator change to SOT223 package

+12V_BUS

F501

)2 7 ON
200mA +5V_VESA

4
U400 1206
COMMON

4
ADJ/GND
3 2 1 2
VIN VOUT
POLYSWITCH

1.8V WORST-CASE REQUIREMENT

ER304

1
EC133 RC1117S_SOT223 EC135 EC134

F
+3.3V_BUS 121

0
17 16 15 14 10 8 7 1 +3.3V_BUS 10uF 10uF 10uF
Est. Current
Display Config

Vout=1.25V* [1+(ER305/ER304) ]

吳 13 jo ID
DVI+HDMI+DP 1330mA

ER305
1/4W@1206 365
17 +3.3V_BUS
10 8 7 1 +3.3V_BUS
1

16 15 14
+1.8V
B +5V C866 B

積 09 ne EN
16 9 8 2 +1.8V
10uF
6.3V
1

+5V
2

R862 R863
10K 10K 1 R8602
DNI
+1.8V_LDOOUT

1
U861 0R
2

3 VIN VOUT 6 R865 C865 C862 C861 C864

13K 33pF 10uF 10uF 0.1uF
R5
1% 50V 6.3V 6.3V 16V
4 VDD FB 7 LDO1_FB DNI +12V_BUS +5V

2
源 05 pe TI
1

15
+1.8V_EN 2 EN NC 5 LDO1_REFIN R4
IN

1
THMPAD

C868
1uF MR451
15
+1.8V_LDO_POK 1 POK GND 8 R864 R450 1 20R
6.3V OUT 1%
10K 360R
2

GS7133SO-R
9

2
R451
1 20R 5VCC
13
IN

01 i( AL
1 R8662 VOUT = Vref x (1 + R5/R4)
0R

1
BZT52C5V1
D450
2
(0 裴
00 RM 亮
C C

11 A工 樂
60 程 )
D
1) 課 D

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Thursday, July 04, 2013 Sheet 14 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

+3.3V_BUS +3.3V_BUS
VDDC Low Side Divider
Power Management - Power Gating and Dynamic Voltage Control
12V_BUS & 3V3_BUS POWER SEQUENCING

17 VDDC_FB
+3.3V_BUS +12V_BUS +12V_BUS 13 IN

00

1
14
8

1
1 +3.3V_BUS 15 14 13 11 8 1 +12V_BUS 13 11 8 1 +12V_BUS
C681 R688

1
7 16 16 15 14 0.1uF 3.24K
10 10V 1% +3.3V_BUS R671 R672
20K 20K
16 R678 R676

2
2
+1.8V_EN U680 20K 20K
R857 Node 1
OUT 14

2
2
1 VCC VID0 8 GPIO_15_VDDC_VID0
5 15
UNNAMED_14_RES_I261_B UNNAMED_14_RES_I265_B VDD_FB_IN1

1
10K

R689
2 GND VID1 7 GPIO_20_VDDC_VID1
5 15 R673 VDDC_FB_IN2
1

3
R839
SCL 3 6 VDDC_REF 1 2 VDDC_REFIN 20K
R852 5,17 IN SCL VREF OUT 13 R650

1
0
PSEQ_N1 2 1 1 SDA 4 5 0R 20K
R850 Q852 5,17 BI SDA R1

1
1

1
A 2.32K 11.3K 5.1K UNNAMED_14_CAP_I10_A MMBT3904 UNNAMED_14_RES_I251_A
Q606
RFB2 A

RD 17 SI

2
3

1
2N7002E 402
PSEQ_N3 C846 Place close uP1801AMT8 C680 5
GPIO_15_VDDC_VID0 1
IN
2

2
15
1 0.1uF to its CTLR 0.033uF
Q850 10V 16V R687 +3.3V_BUS

2
MMBT3904 5.49K
Node 3

2
1%
UNNAMED_14_NPN_I18_E
MR673

2
Vref: R688/R687=1V 20K

3
R674

1
3
20K
PSEQ_N2 1 Q851 Q607

1
MMBT3904 GPIO_20_VDDC_VID1 1 2N7002E

(C 96 C
Node 2 GPIO_20_VDDC_VID1
5 IN
1

2
1

R851

2
2

1
1K
R853
1K
MR674 R679
2

20K 20K
2

2
1
+12V_BUS +3.3V_BUS

)2 7 ON
R680
20K

2
UNNAMED_14_MOSN_I279_D
R675

3
20K

1
+12V_BUS

1
Q608
R833 2N7002E
5
GPIO_29_VDDC_VID2 1
IN

F
5.1K

2
0
2

2
1

+1.8V MR675
+0.95V_EN
20K
R832
OUT 10

吳 13 jo ID
+3.3V_BUS

1
5.1K

1
2

1
R831 R888
1 2 1 UNNAMED_14_NPN_I304_B
Q838 R677
1

2
5.1K
MMBT3904 5.1K C898
UNNAMED_14_MOSN_I277_D

3
0.1uF

2
R885

2
10V
1K 20K

2
Q609
2

1
3

B 5
GPIO_30_VDDC_VID3 1 2N7002E B

積 09 ne EN
+1.8V_LDO_POK R845 IN
4 2 1 1 Q839
IN 5.1K MMBT3904

2
2
VDDC_EN

VDDC_EN
13,15 MR677
OUT
2
1

R876
CTF_PWROFF_B 1 2 UNNAMED_14_CAP_I165_A

IN
3
20K
0R C848
1

0.1uF R838
2 1 1 UNNAMED_14_NPN_I174_B
Q1

1
10V
5.1K MMBT3904
R886
2

1K UNNAMED_14_CAP_I170_A
2

源 05 pe TI
C839
2

0.1uF
10V
PSEQ_N3
2

R875
1 2 15
0R
R874
1 2 +1.8V_EN
15 14 +12V_BUS
0R
16 15 14 13 11 8 1 +12V_BUS

01 i( AL
MVDD_EN
OUT 11
+3.3V_BUS
2

R843
5.1K
1

PSEQ_MVDD_EN
R846
DNI
PWR_ENABLE# 2 1 1 Q842
2

5.1K

(0
R841 MMBT3904

裴
2
3

5.1K
1

Q840
VDDC_PWR_GOOD 1 2 1 UNNAMED_14_MOSN_I190_G 2N7002E VDDCI_EN
R1693 12
IN 1K OUT
2

00 RM 亮
1

R847
2 1 1 UNNAMED_14_NPN_I195_B
Q843
1

5.1K
C841 MMBT3904
1uF
C C840 C
2

6.3V
0.1uF
2

10V
2

+12V_BUS

11 A工 樂
60 程 )
1

+MVDD_Source
L702 R4534 R702

1)
0.47uH 0R 0R
1

BACO
2

課
VDDC_EN
OUT 13,15
3 VDDC_EN

R1027 10K
2,16,17
PX_EN 1 UNNAMED_14_NPN_I216_B
Q1014
IN MMBT3904
1

+VDDCI +12V_BUS
2

+VDDCI_Source C1031 R1030

D +VDDC 1uF 10K D
6.3V
DNI
2

B629 DNI
1 2 2R921 0R
1
60R
L921 0.47uH
B639 DNI 1 2
1 2
60R 2R4535 0R
1
MICRO-STAR INT'L CO.,LTD
MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connectorci20313 1.0

Date: Friday, July 05, 2013 Sheet 15 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

GPIO6 is 0: Fan stop

GPIO6 is PWM: Fan running
Install R4520

GPIO6 is 1: Fan stop

00
Mechanical and Thermal Management Install R4516 Q4511,R4519 GPIO6 is PWM: Fan running

+1.8V

14 9 8 2 +1.8V +12V_BUS
U1M

M
AJ32 TSVDD DPLUS AF29 GPU_DPLUS
17
OUT

1
0
AJ33 AG29
A
C4020
1uF
TSVSS DMINUS C4004
0.0022uF
R4102
1K 2pin fan A
+3.3V_BUS

RD 17 SI
6.3V 50V
GPIO_28_FDO AK32 GPU_DMINUS
+3.3V_BUS
OUT 17
16 15 14 13 11 8
4pin fan

2
15 +3.3V_BUS +3.3V_BUS

1
8 7 1 +3.3V_BUS 8 7 1 +3.3V_BUS
14 10 17 16 15 14 10
OLAND M2 GDDR5 17 16
R237
2K
1.風扇直接灌12V
PWM_B 上件(R253 B201 )

1
DNI R250 不上件(R249 R4510)
<BOMOPTION>

2
R4104 R4100 R206 1 2 2.用公版PWM線路
5.1K _
2.61K 20K 上件( R250 B201 R253 Q4507)
不上件(R249 R4510 B200 R251 U203)

3
0OHM

(C 96 C
Socket 6090034500G

2
TS_FDO01 R4101
2 TS_FDO 1 1 R234 21K 1 N36370229
Q201 3.用NVT3943線路
Q4100 _ X
上件(R249 R251 B200)
1.2K MMBT3904
不上件(R250 R253 B201 R4510 )

1
2N7002E
DNI _
_

2
1
80200515A0G 17 IN R4409
20K
Bracket VGA DP DVI MR4104
10K
Q4510

3
2

1
)2 7 ON
Bracket 8020051500G VGA HDMI DVI 1 UNNAMED_15_RES_I299_A
R4500 20K 2 1 UNNAMED_15_NPN_I301_B
DNI
1 UNNAMED_15_NPN_I317_B
DNI
5% Q4500
DNI MMBT3904 MMBT3904
1,2,16
PERST#_BUF 3 D1720
IN

2
DNI
Bracket 8020052800G DP DVI 1 PX_EN 2 VOUT_FAN
BAT54S R4514
If Critical Temperature is reached this will force the fan to run at full 5% 20K
speed while power is removed from GPU & rest of the board.

2
R4517
7121000100G
This is an open collector signal. Active level is hard pull down to ground.
1 2
20K
DNI
Fansink 7122000100G For 75W board 5%
PX_EN

F
2 15 16 17
7120781200G

0
R249
+12V_BUS

3
Critial Temperature Fault U203 3943_VOUT1 2
R4057 1K
2 1 PWM_ENB 1

吳 13 jo ID
Q4011
MMBT3904 8 1 0OHM
VIN Vout

1
DNI C4402 _

2
1 2
R4062 R4063 7 2
FON# FB

1
0R 0.1uF 100K PWMOUT_J 1 J4001
16V
Critial Temperature Fault C236 FANOUT_P 6 3 GPIO_6_J 2

2
10uF_16V SD# PWMOUT

1
MALE
16V R232 10uF 3 2.0MM
5 4 0OHM C238 4 N/A
_

2
B DCIN PWMIN 13.3K 5% B
DCIN 16V

GND
+3.3V_BUS

積 09 ne EN
DNI
17 16 15 14 10 8 7 1 +3.3V_BUS R208 _ _

2
1 2 _
1

1
100K NCT3943S

9
1
R4411 R4407 1 R207 2 _ R215
10K 20K
Place close to its CTLR C237 1 2 5%
2

DNI _ 16V 0.1uF _

4.99K
2

MMBT3906
Q4400 1 CTF2_GAT
_
_

2
CTF2: R4051=20K, R4053 DNI, C4401=0.1UF;
CTF_PWROFF_B
OUT 15

源 05 pe TI
3

3
CTF_BYPASS 16 17 CTF_BYPASS 2 1
R4051
CTF_PWROFF 1 Q4010 PWMIN
1K MMBT3904
1

2
R4404 R4405 C4401 R4053
2

20K 20K 0.1uF 100K

16V
R4038

R4408
2

2
01 i( AL
TCRIT 1 2
1K

17 IN 0R
1

UNNAMED_15_NPN_I128_C
3

CTF2_RESET
GPIO_19_CTF 1 R4400 47K
2 47K
2 R4402
1 1 Q4401 +12V_BUS +3.3V_BUS
IN
MMBT3904
2
1

UNNAMED_15_CAP_I127_A

1
3
R4403
100K
C4400
0.01uF BACO

(0
D4400 CTF_BYPASS B201 B200
10V OUT 17 220R 220R

裴
2

BAT54S

2
X _
2

PERST#_BUF
16 2 1

00 RM 亮
C4009
1uF
16V
_

2
C R4508 20K
C
1 R4510
AO3415L 0R
Q4507
5%
_
use NCT3943 baco
X

11 A工 樂
FAN_EN

3
_ R251
1 2 FANOUT_P

R4507 0OHM
20K R253
5% _
1 2 VOUT_FAN
+3.3V_BUS
_

60
+3.3V_BUS
0OHM

)
Q4502 X
1

MMBT3906
2

8
7

DNI C4500

程
R4512 U4500
2,15,17 IN
PX_EN 1
1K
2 1 R4502
100K
0.1uF +12V_BUS
2 5
PR
Vcc

D Q
2

+12V_BUS 5%
3

1)
1 C Q 3 1
R4509 2
1M
1

3
CL

5%
R4516

DNI R4004
5%

CTF_BYPASS R4506 1 10K

Q4503 20K
NC7SZ74K8X Q4506
1 UNNAMED_15_NPN_I269_B
R4503 C4507 5%
4
6

課
MMBT3904
MMBT3904

33K
20K

0.1uF
UNNAMED_15_CAP_I277_A _
_ _
2

2
5%
C4502
OUT 5
2

2
3

3
10uF
6.3V
R4515 100K Q4505
PERST#_BUF 1 2 1 R4505 20K 1
IN
2
1

MMBT3904
MMBT3904

UNNAMED_15_CAP_I344_A
5%
C4506 Q4509 _
_ R4005 GPIO_6_J
2

2
3

1uF Q4508 1K
16V
1 UNNAMED_15_MOSN_I312_G 2N7002E _
2

Rectangular Heatsink 8W
R4006
3.83K
2

3
R4504 Q4504
20K 1
D 5%
MMBT3904 _ D
_
_

2
MICRO-STAR INT'L CO.,LTD
MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Friday, July 05, 2013 Sheet 16 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

7120781200G
(19) Debug Circuits HS2A
HS2B HS2C HS2D

00 M
PCB1
9 17 16 25 24 32

10
11
12
13
14
15

18
19
20
21
22
23

26
27
28
29
30
31
0
AMD

1
2
3
4
5
6
7
8
PCB
A A

RD 17 SI
PCB(109-C576xx-00)
JTAG

U1N

TESTEN AD28 TESTEN

17
JTAG_TRSTB AM23 JTAG_TRSTB
17
JTAG_TCK AK23 JTAG_TCK
17
JTAG_TDI AN23 JTAG_TDI
17
JTAG_TDO AM24 JTAG_TDO
17 BKT1
AL24 JTAG_TMS

(C 96 C
JTAG_TMS 17 +3.3V_BUS
BRKT
MEC1 HDMISCREW DNI
OLAND M2 GDDR5 17 16 15 14 10 8 7 1 +3.3V_BUS
+3.3V_BUS Bracket Components
1
MT200
7 1 +3.3V_BUS COMMON COMMON
HEADER_RECEPT_2X4
17 16 15 14 10 8

17
JTAG_TDO 7 8

1
17
JTAG_TDI 5 6

)2 7 ON
17
JTAG_TMS 3 4 R436 MEC_SCREW GND
JTAG_TCK 1 2 1K MEC_SCREW
17

MECH. MOUNTING TOP

DNI
1 8 MEC2

2
17 TESTEN

2
3
4
5
6
7
J4004
MOUNTING_8PINS_1

1
620NOPN029 COMMON
+3.3V_BUS
R437
2 1K
R38 1
JTAG_TRSTB
17 +3.3V_BUS
17
16
15
14
10
1
7
8
1K

F
2
1
0
MEC_SCREW
R39
1K
DNI MEC3
JTAG_TRSTB

吳 13 jo ID 2
engineering board pull high
COMMON
production board pull down

MEC_SCREW FAN
COOLING SOLUTION
B MEC4
<PCB Footprint> B

積 09 ne EN
COMMON
No connected mounting pins
+3.3V_BUS
LM96163 FOR BACKUP THERMAL CONTROL APPLY
17 16 15 14 10 8 7 1 +3.3V_BUS COMMON
VVVV302-01S
+3.3V_BUS
HEATSINK
1

17 16 15 14 10 8 7 1 +3.3V_BUS MEC_SCREW
C4003 C4002 C4001
100pF 1uF 10uF
50V 6.3V 6.3V

源 05 pe TI
2

2
1

R4017 R4018 R4011

4.7K 4.7K 10K
2

U4001

,15
SCL 1 2
R4001 17 SCL_R
SMBCLK 10 TCRIT 1 TCRIT
16
IN OUT

01 i( AL
100R

5,15
SDA 1 2
R4002 17 SDA_R
SMBDAT 9 VDD 2
BI 100R J11 J12 J13 J14
TACH 8 3 GPU_DPLUS
D+ 16
IN 3 1 3 1
GPIO_17_THERMINT 1 2 THERMINT 7 4 GPU_DMINUS 4 2 4 2
R4080 ALERT D- DNI
5 OUT 0R IN 16
X_PIN1*2 X_PIN1*2 impedence impedence
GND6 5 1 2
LM63_PWM TS_FDO
PWN R4081
OUT 16
33R

11 GND GND GND GND

(0
MR4001 100R
THMPAD GND GND

裴
1,5
SMBCLK 1 2 SCL_R
17 TOP BOT TOP BOT
IN LM96163CISD
SMBDATA 1 2 SDA_R
17 MEM DATA Signal end MEM DATA Signal end Diffenential_Memory Clock PEX_PCIE Signal
1,5 BI
MEM to GPU :0.13mm/ 45ohm MEM to GPU :0.13mm/ 45ohm trace width=0.13mm / 80ohm trace width=0.11mm / 85ohm
MR4002 100R Air Gap：0.19mm Air Gap：0.14mm

00 RM 亮
C C

11 A工 樂
FM1 FM4 FM9 FM11

XXXV302-01S XXXV302-01S XXXV302-01S XXXV302-01S

APPLY APPLY APPLY APPLY

OPT OPT OPT OPT

60
F_PAD_X F_PAD_X F_PAD_X F_PAD_X

)
FM5 FM8 FM10 FM12

程
XXXV302-01S XXXV302-01S XXXV302-01S XXXV302-01S
APPLY APPLY APPLY APPLY

1)
OPT OPT OPT OPT

F_PAD_X F_PAD_X F_PAD_X F_PAD_X

D
課 D

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Thursday, July 11, 2013 Sheet 17 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

00 M
0
A MVDD SOURCE A

RD 17 SI
1.5A
1.5V@10A

sDVI-I HPD4 DDC1

HDMI/DP HPD2 DDC2/AUX2

12V_BUS

(C 96 C
VGA DDCVGA
5.5A VDDCI SOURCE 1.05V@6A
0.6A

)2 7 ON
B
0
吳 13 jo ID F VDDC PHASE1 SOURCE

2.7A
VDDC@25A

積 09 ne EN
VDDC PHASE2 SOURCE

2.7A VDDC@25A
GPIO15 VDDC_VID0

源 05 pe TI
GPIO20 VDDC_VID1

GPIO29 VDDC_VID2

GPIO30 VDDC_VID3
FAN

01 i( AL
0.5A
GPIO7 VDDCI_VID0 DEFAULT 1

GPIO16 VDDCI_VID1

GPIO21 MVDD_VID

(0 裴
00 RM 亮
0.95V SOURCE 0.95V@2A
C 1.5A
C

11 A工 樂
60
3.3V_BUS 1.8V_LDO

)
0.5A 1.8V@0.5A
3A

1) 程 3.3V@60mA

D
課 D

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Thursday, July 04, 2013 Sheet 18 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

MEMORY CHANNEL A & B

Debug

00
GDDR5 4pcs 64Mx32 (1GB)

0 M
A A

RD 17 SI CH A&B

(C 96 C
)2 7 ON
JTAG/I2C
GPIO

POWER REGULATORS

From +12V

F
OPTIONAL

0
+VDDC RGB Filters

+MVDD sVGA

FAN

吳 13 jo ID
VGADDC

From +12V LINEAR:

ROM
Straps
+5V_VESA, +5V_VESA2

B B

積 09 ne EN
From +12V_BUS SL TMDS HDMI

TMDP-A AC Coupling Caps Connector

BIOS
+5V

From +3.3V_BUS converter(+0.95V):

5V_VESA
Thermal

源 05 pe TI
PCIE_VDDC, DPLL_VDDC, DDC AUXDDC2
Speed control
DPx_VDD10, SPV10, MEM_VREF
DisplayPort
GPIO17
& temperature
INTERRUPT HPD1 Connector

OPTIONAL
From +3.3V Direct:
sense D+/D-

VDDR3, AVDD
FAN Temp. Sensing

01 i( AL
TS_FDO
Built-in PWM +3.3V_BUS
From 3.3V Linear (1.8V)

Overlap

PCIE_PVDD, PCIE_VDDR, VDDR4,

Dynamic Power Management

DPLL_PVDD, SPV18, MPV18, DL TMDS

VDD1DI, VDD2DI, AVDD, AVDDQ, AC Coupling Caps

(0
TMDPB sDVI-I

裴
DPx_PVDD, DPx_VDD18, VDD_CT,
POWER DELIVERY
TSVDD

DACVGA Connector
RGB Filters

00 RM 亮
Oland AUXDDC1

C HPD2 5V_VESA
C

100MHz

XO_IN2

11 A工 樂
27MHz

XO_IN Clock

Temperature Critical
CTF XTALIN

PCI-Expressx8 27MHz Xtal

Power Sequencing

60
Circuit

程 ) Oland GDDR5 1GB

HDMI/DP sDVI-D sVGA

1)
+3.3V_BUS
+12V_BUS

PCI-Express x8 Bus

D
課 D

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Thursday, July 04, 2013 Sheet 19 of 20

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

DATE
TITLE SCHEMATIC NO.

00
Oland XT GDDR5 1GB sDVI-I+HDMI/DP+VGA 105-C576XX-00

NOTE: REV
THIS SCHEMATIC REPRESENTS THE PCB, IT DOES NOT REPRESENT ANY SPECIFIC SKU.

M
REVISION HISTORY
FOR STUFFING OPTIONS (COMPONENT VALUES, DNI PLEASE CONSULT THE PRODUCT SPECIFIC BOM.

PLEASE CONTACT AMD REPRESENTATIVE TO OBTAIN LASTEST BOM CLOSEST TO THE APPLICATION DESIRED. P00

0
A A

RD 17 SI
SCH PCB
DATE REVISION DESCRIPTION
REV REV

00 00 2012/12/04

(C 96 C
)2 7 ON
Page6.change J1501 to type-A and add ESD
Page7.remove DP and add ESD
Page8.add ESD

B
Page10.change 0.95V converter and change L801
Page11.change MVDD PWM IC to converter and change L701
Page12.change VDDCI PWM IC to converter and change L901
Page13.change L601/L612
0
吳 13 jo ID F B

積 09 ne EN
Page14.change 5V Regulator
Page16.add Fan IC + 4pin Fan

源 05 pe TI
01 i( AL
(0 裴
00 RM 亮
C C

11 A工 樂
60 程 )
D
1) 課 D

MICRO-STAR INT'L CO.,LTD

MS-V302
MSI
Size Document Description Rev
Custom PCI-E Edge Connector 1.0

Date: Thursday, July 04, 2013 Sheet 20 of 20

1 2 3 4 5 6 7 8