Tle 2027

TLE2027, TLE2037, TLE2027A, TLE2037A, TLE2027Y, TLE2037Y
EXCALIBUR LOW-NOISE HIGH-SPEED

PRECISION OPERATIONAL AMPLIFIERS
SLOS192C − FEBRUARY 1997 − REVISED APRIL 2010
D Outstanding Combination of dc Precision D, JG, OR P PACKAGE

and AC Performance: (TOP VIEW)
Unity-Gain Bandwidth . . . 15 MHz Typ
Vn . . . . . 3.3 nV/√Hz at f = 10 Hz Typ, OFFSET N1 1 8 OFFSET N2
2.5 nV/√Hz at f = 1 kHz Typ IN − 2 7 VCC +
VIO . . . . 25 μV Max IN + 3 6 OUT
AVD . . . . 45 V/μV Typ With RL = 2 kΩ, VCC − 4 5 NC
19 V/μV Typ With RL = 600 Ω
D Available in Standard-Pinout Small-Outline
FK PACKAGE
Package (TOP VIEW)
D Output Features Saturation Recovery
OFFSET N1
OFFSET N2
Circuitry
D Macromodels and Statistical information
NC
NC
NC
description
3 2 1 20 19
The TLE20x7 and TLE20x7A contain innovative NC 4 18 NC
circuit design expertise and high-quality process IN − 5 17 VCC +
control techniques to produce a level of ac NC 6 16 NC
performance and dc precision previously unavail- IN + 7 15 OUT
able in single operational amplifiers. Manufac- NC 8 14 NC
9 10 11 12 13
tured using Texas Instruments state-of-the-art
Excalibur process, these devices allow upgrades
VCC −
NC
NC
NC
NC
to systems that use lower-precision devices.
In the area of dc precision, the TLE20x7 and
TLE20x7A offer maximum offset voltages of
100 μV and 25 μV, respectively, common-mode
rejection ratio of 131 dB (typ), supply voltage
rejection ratio of 144 dB (typ), and dc gain of
45 V/μV (typ).
AVAILABLE OPTIONS
PACKAGED DEVICES
VIOmax AT CHIP
SMALL CHIP CERAMIC PLASTIC
TA
25°C FORM‡
OUTLINE† CARRIER DIP DIP
(Y)
(D) (FK) (JG) (P)
TLE2027ACD — — TLE2027ACP TLE2027Y
25 μV
TLE2037ACD — — TLE2037ACP TLE2037Y
0°C to 70°C
TLE2027CD — — TLE2027CP TLE2027Y
100 μV
TLE2037CD — — TLE2037CP TLE2037Y
TLE2027AID — — TLE2027AIP
25 μV —
TLE2037AID — — TLE2037AIP
40°C to 105°C
−40
TLE2027ID — — TLE2027IP
100 μV —
TLE2037ID — — TLE2037IP
TLE2027AMD TLE2027AMFK TLE2027AMJG TLE2027AMP
25 μV —
TLE2037AMD TLE2037AMFK TLE2037AMJG TLE2037AMP
55°C to 125°C
−55
TLE2027MD TLE2027MFK TLE2027MJG TLE2027MP
100 μV —
TLE2037MD TLE2037MFK TLE2037MJG TLE2037MP
† The D packages are available taped and reeled. Add R suffix to device type (e.g., TLE2027ACDR).
‡ Chip forms are tested at 25°C only.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2002−2006, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
1
description (continued)
The ac performance of the TLE2027 and TLE2037 is highlighted by a typical unity-gain bandwidth specification
of 15 MHz, 55° of phase margin, and noise voltage specifications of 3.3 nV/√Hz and 2.5 nV/√Hz at frequencies
of 10 Hz and 1 kHz respectively. The TLE2037 and TLE2037A have been decompensated for faster slew rate
(−7.5 V/μs, typical) and wider bandwidth (50 MHz). To ensure stability, the TLE2037 and TLE2037A should be
operated with a closed-loop gain of 5 or greater.
Both the TLE20x7 and TLE20x7A are available in a wide variety of packages, including the industry-standard
8-pin small-outline version for high-density system applications. The C-suffix devices are characterized for
operation from 0°C to 70°C. The I-suffix devices are characterized for operation from − 40°C to 105°C. The
M-suffix devices are characterized for operation over the full military temperature range of − 55°C to 125°C.
symbol
OFFSET N1
IN + +
OUT
IN − −
OFFSET N2
2 •
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
TLE202xY chip information

This chip, when properly assembled, displays characteristics similar to the TLE202xC. Thermal compression
or ultrasonic bonding may be used on the doped-aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS

(1) VCC+
(6) (4) OFFSET N1
(3) (7)
IN + +
(8) (7) (6) (6)
OUT
(2)
IN − −
(4)
(8)
OFFSET N2
VCC −
(5)
90
(3)
(7)
(4)
CHIP THICKNESS: 15 MILS TYPICAL

(2)
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
(1) (2) (3) ALL DIMENSIONS ARE IN MILS.
(8)
(1) PIN (4) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
73
3
4
equivalent schematic
OFFSET N2 V CC+
OFFSET N1
R9 R15 R20
Q5 R1 R4
Q2 Q10 Q42 R25 Q61
Q49 Q58
R2 R5 Q27
Q9 C1
Q36 Q46 Q55
Q13 Q30
Q6
R21 Q56
Q3 Q11 Q14
R8 R11 R16 Q38
Q59
Q19 Q32 Q39 Q57
IN + Q12 Q17 R17 Q37
Q25 Q28 OUT
Q4 Q8 C3
Q1 Q7 Q44
R22
IN − Q43 Q52
C2 R13 Q48
Q50 Q62
Q47
4 4
C4
Q18
4 4
Q34 Q53
Q23 Q24 Q41
Q20
Q33
Q21 Q54
Q15 Q51
Q60
Q26 Q29
www.ti.com
Q45 R23
Q22 Q35 Q40
Q16 Q31
R24 R26
R6 R7 R10 R12 R14 R18 R19
R3
VCC −
44 4 4
4
ACTUAL DEVICE COMPONENT COUNT

COMPONENT TLE2027 TLE2037
Transistors 61 61
Resistors 26 26
epiFET 1 1
Capacitors 4 4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 V
Supply voltage, VCC − . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 19 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.2 V
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC±
Input current, II (each Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Total current into VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Total current out of VCC − . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 105°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
Case temperature for 60 seconds, TC: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . 300°C
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC + and VCC − .
2. Differential voltages are at IN+ with respect to IN −. Excessive current flows if a differential input voltage in excess of approximately
±1.2 V is applied between the inputs unless some limiting resistance is used.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE

TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 105°C TA = 125°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING
D 725 mW 5.8 mW/°C 464 mW 261 mW 145 mW
FK 1375 mW 11.0 mW/°C 880 mW 495 mW 275 mW
JG 1050 mW 8.4 mW/°C 672 mW 378 mW 210 mW
P 1000 mW 8.0 mW/°C 640 mW 360 mW 200 mW
recommended operating conditions

C SUFFIX I SUFFIX M SUFFIX
UNIT
MIN MAX MIN MAX MIN MAX
Supply voltage, VCC ± ±4 ± 19 ±4 ± 19 ±4 ± 19 V
TA = 25°C −11 11 −11 11 −11 11
Common mode input voltage,
Common-mode voltage VIC V
TA = Full range‡ −10.5 10.5 −10.4 10.4 −10.2 10.2
Operating free-air temperature, TA 0 70 −40 105 −55 125 °C
‡ Full range is 0°C to 70°C for C-suffix devices, − 40°C to 105°C for I-suffix devices, and − 55°C to 125°C for M-suffix devices.
www.ti.com 5
TLE20x7C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless

otherwise noted)
TLE20x7C TLE20x7AC
PARAMETER TEST CONDITIONS TA† UNIT
MIN TYP MAX MIN TYP MAX
25°C 20 100 10 25
VIO Input offset voltage V
μV
Full range 145 70
Temperature coefficient of
αVIO input offset voltage
Full range 0.4 1 0.2 1 μV/°C
Input offset voltage

VIC = 0, RS = 50 Ω 25°C 0.006 1 0.006 1 μV/mo
long-term drift (see Note 4)
25°C 6 90 6 90
IIO Input offset current nA
Full range 150 150
25°C 15 90 15 90
IIB Input bias current nA
Full range 150 150
−11 −13 −11 −13
25°C to to to to
Common mode input
Common-mode 11 13 11 13
VICR RS = 50 Ω V
voltage range −10.5 −10.5
Full range to to
10.5 10.5
25°C 10.5 12.9 10.5 12.9
RL = 600 Ω
Maximum positive peak Full range 10 10
VOM + V
p voltage
output g swingg 25°C 12 13.2 12 13.2
RL = 2 kΩ
Full range 11 11
25°C −10.5 −13 −10.5 −13
RL = 600 Ω
Maximum negative peak Full range −10 −10
VOM − V
output voltage swing 25°C − 12 −13.5 − 12 −13.5
RL = 2 kΩ
Full range − 11 − 11
VO = ± 11 V, RL = 2 kΩ 25°C 5 45 10 45
VO = ± 10 V, RL = 2 kΩ Full range 2 4
Large-signal
Large signal differential 25°C 3.5 38 8 38
AVD VO = ± 10 V
V, RL = 1 kΩ V/ V
V/μV
voltage amplification Full range 1 2.5
VO = ± 10 V, 25°C 2 19 5 19
RL = 600 Ω Full range 0.5 2
Ci Input capacitance 25°C 8 8 pF
Open-loop output
zo IO = 0 25°C 50 50 Ω
impedance
Common-mode
Common mode rejection VIC = VICRmin, 25°C 100 131 117 131
CMRR dB
ratio RS = 50 Ω Full range 98 114
VCC ± = ± 4 V to ± 18 V,
25°C 94 144 110 144
Supply voltage rejection
Supply-voltage RS = 50 Ω
kSVR dB
ratio (ΔVCC ± /ΔVIO) VCC ± = ± 4 V to ± 18 V,
Full range 92 106
RS = 50 Ω
25°C 3.8 5.3 3.8 5.3
ICC Supply current 0
VO = 0, No load mA
Full range 5.6 5.6
† Full range is 0°C to 70°C.
NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
6 www.ti.com
TLE20x7C operating characteristics at specified free-air temperature, VCC ± = ±15 V, TA = 25°C

(unless otherwise specified)
TLE20x7C TLE20x7AC
PARAMETER TEST CONDITIONS UNIT
RL = 2 kΩ, TLE2027 1.7 2.8 1.7 2.8
CL = 100 pF
pF,
See Figure 1 TLE2037 6 7.5 6 7.5
SR Slew rate at unity gain RL = 2 kΩ, V/μs
TLE2027 1.2 1.2
CL = 100 pF,
TA = 0°C to 70°C,
TLE2037 5 5
See Figure 1
volt-
Equivalent input noise volt RS = 20 Ω, f = 10 Hz 3.3 8 3.3 4.5
Vn nV/√Hz
age (see Figure 2) RS = 20 Ω, f = 1 kHz 2.5 4.5 2.5 3.8
Peak-to-peak equivalent in-
VN(PP) f = 0.1 Hz to 10 Hz 50 250 50 130 nV
put noise voltage
cur-
Equivalent input noise cur f = 10 Hz 10 25 10 25
In pA/√Hz
rent f = 1 kHz 0.8 1.8 0.8 1.8
VO = + 10 V,
AVD = 1, TLE2027 < 0.002% < 0.002%
See Note 5
THD Total harmonic distortion
VO = + 10 V,
AVD = 5, TLE2037 < 0.002% < 0.002%
See Note 5
Unity-gain bandwidth RL = 2 kΩ,
B1 TLE2027 9(6) 13 9(6) 13
(see Figure 3) CL = 100 pF
MHz
RL = 2 kΩ,
GBW Gain bandwidth product TLE2037 35 50 35 50
CL = 100 pF
Maximum output
output-swing
swing TLE2027 30 30
BOM RL = 2 kΩ kHz
bandwidth TLE2037 80 80
Phase margin at unity gain RL = 2 kΩ, TLE2027 55° 55°
φm (see Figure 3) CL = 100 pF TLE2037 50° 50°
NOTE 5: Measured distortion of the source used in the analysis was 0.002%.
NOTE 6: This parameter is not production tested
www.ti.com 7
TLE20x7I electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless

otherwise noted)
TLE20x7I TLE20x7AI
25°C 20 100 10 25
μV
Full range 180 105
Full range 0.4 1 0.2 1 μV/°C

VIC = 0, RS = 50 Ω 25°C 0.006 1 0.006 1 μV/mo
25°C 6 90 6 90
Full range 150 150
25°C 15 90 15 90
Full range 150 150
−11 −13 −11 −13
25°C to to to to
Common mode input
VICR RS = 50 Ω V
Full range to to
10.4 10.4
25°C 10.5 12.9 10.5 12.9
RL = 600 Ω
VOM + V
p voltage
output g swingg 25°C 12 13.2 12 13.2
RL = 2 kΩ
Full range 11 11
25°C −10.5 −13 −10.5 −13
RL = 600 Ω
VOM − V
RL = 2 kΩ
VO = ± 11 V, RL = 2 kΩ 25°C 5 45 10 45
VO = ± 10 V, RL = 2 kΩ Full range 2 3.5
Large-signal
Large signal differential 25°C 3.5 38 8 38
AVD VO = ± 10 V
V, RL = 1 kΩ V/ V
V/μV
voltage amplification Full range 1 2.2
25°C 2 19 5 19
VO = ± 10 V
V, RL = 600 Ω
Full range 0.5 1.1
Open-loop output
zo IO = 0 25°C 50 50 Ω
impedance
Common-mode
CMRR dB
VCC ± = ± 4 V to ± 18 V,
25°C 94 144 110 144
kSVR dB
Full range 90 105
RS = 50 Ω
25°C 3.8 5.3 3.8 5.3
ICC Supply current VO = 0,
0 No load mA
Full range 5.6 5.6
†Full range is − 40°C to 105°C.
8 www.ti.com
TLE20x7I operating characteristics at specified free-air temperature, VCC ± = ±15 V, TA = 25°C

TLE20x7I TLE20x7AI
RL = 2 kΩ, TLE2027 1.7 2.8 1.7 2.8
CL = 100 pF
pF,
See Figure 1 TLE2037 6 7.5 6 7.5
TLE2027 1.1 1.1
CL = 100 pF,
TA = − 40°C to 85°C,
TLE2037 4.7 4.7
See Figure 1
Equivalent input noise RS = 20 Ω, f = 10 Hz 3.3 8 3.3 4.5
Vn nV/√Hz
voltage (see Figure 2) RS = 20 Ω, f = 1 kHz 2.5 4.5 2.5 3.8
Peak-to-peak equivalent
VN(PP) f = 0.1 Hz to 10 Hz 50 250 50 130 nV
input noise voltage
Equivalent input noise f = 10 Hz 10 25 10 25
In pA/√Hz
current f = 1 kHz 0.8 1,8 0.8 1.8
VO = + 10 V,
AVD = 1, TLE2027 < 0.002% < 0.002%
See Note 5
VO = + 10 V,
AVD = 5, TLE2037 < 0.002% < 0.002%
See Note 5
Unity-gain bandwidth RL = 2 kΩ,
B1 TLE2027 9(6) 13 9(6) 13
(see Figure 3) CL = 100 pF
MHz
RL = 2 kΩ,
GBW Gain bandwidth product TLE2037 35 50 35 50
CL = 100 pF
Maximum output
output-swing
swing TLE2027 30 30
BOM RL = 2 kΩ kHz
Phase margin at unity RL = 2 kΩ , TLE2027 55° 55°
φm gain (see Figure 3) CL = 100 pF TLE2037 50° 50°
NOTE 6: This parameter is not production tested.
www.ti.com 9
TLE20x7M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless

otherwise noted)
TLE20x7M TLE20x7AM
25°C 20 100 10 25
μV
Full range 200 105
Full range 0.4 1* 0.2 1* μV/°C

VIC = 0, RS = 50 Ω 25°C 0.006 1* 0.006 1* μV/mo
25°C 6 90 6 90
Full range 150 150
25°C 15 90 15 90
Full range 150 150
−11 −13 −11 −13
25°C to to to to
Common mode input
VICR RS = 50 Ω V
Full range to to
10.3 10.4
25°C 10.5 12.9 10.5 12.9
RL = 600 Ω
VOM + V
p voltage
output g swingg 25°C 12 13.2 12 13.2
RL = 2 kΩ
Full range 11 11
25°C −10.5 −13 −10.5 −13
RL = 600 Ω
VOM − V
RL = 2 kΩ
VO = ± 11 V, RL = 2 kΩ 25°C 5 45 10 45
VO = ± 10 V, RL = 2 kΩ Full range 2.5 3.5
Large-signal
L i l diff
differential
ti l
AVD 25°C 3.5 38 8 38 V/μV
voltage amplification VO = ± 10 V
V, RL = 1 kΩ
Full range 1.8 2.2
VO = ± 10 V
V, RL = 600 Ω 25°C 2 19 5 19
Open-loop output
zo IO = 0 25°C 50 50 Ω
impedance
Common-mode
CMRR dB
VCC ± = ± 4 V to ± 18 V,
25°C 94 144 110 144
kSVR dB
Full range 90 105
RS = 50 Ω
25°C 3.8 5.3 3.8 5.3
ICC Supply current VO = 0,
0 No load mA
Full range 5.6 5.6
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
† Full range is − 55°C to 125°C.
10 www.ti.com
TLE20x7M operating characteristics at specified free-air temperature, VCC ± = ±15 V, TA = 25°C

TLE20x7M TLE20x7AM
RL = 2 kΩ, TLE2027 1.7 2.8 1.7 2.8
CL = 100 pF
pF,
See Figure 1 TLE2037 6* 7.5 6* 7.5
TLE2027 1 1
CL = 100 pF,
TA = − 55°C to 125°C,
TLE2037 4.4* 4.4*
See Figure 1
Equivalent input noise RS = 20 Ω, f = 10 Hz 3.3 8* 3.3 8*
Vn nV/√Hz
voltage (see Figure 2) RS = 20 Ω, f = 1 kHz 2.5 4* 2.5 4*
Peak-to-peak equivalent
VN(PP) f = 0.1 Hz to 10 Hz 225 375* 225 375* nV
input noise voltage
Equivalent input noise f = 10 Hz 25 25
In pA/√Hz
current f = 1 kHz 2.5 2.5
VO = + 10 V,
AVD = 1, TLE2027 < 0.002% < 0.002%
See Note 5
VO = + 10 V,
AVD = 5, TLE2037 < 0.002% < 0.002%
See Note 5
Unity gain bandwidth
Unity-gain RL = 2 kΩ, TLE2027 7* 13 9* 13
B1 MHz
(see Figure 3) CL = 100 pF TLE2037 35 50 35 50
Maximum output
output-swing
swing TLE2027 30 30
BOM RL = 2 kΩ kHz
Phase margin at unity RL = 2 kΩ, TLE2027 55° 55°
φm gain (see Figure 3) CL = 100 pF TLE2037 50° 50°
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
www.ti.com 11
TLE20x7Y electrical characteristics, VCC± = ±15 V, TA = 25°C (unless otherwise noted)

TLE20x7Y
MIN TYP MAX
VIO Input offset voltage 20 μV
0.006 μV/mo
long-term drift (see Note 4) VIC = 0, RS = 50 Ω
IIO Input offset current 6 nA
IIB Input bias current 15 nA
−13
VICR Common-mode input voltage range RS = 50 Ω to V
13
RL = 600 Ω 12.9
VOM + Maximum positive peak output voltage swing V
RL = 2 kΩ 13.2
RL = 600 Ω −13
VOM − Maximum negative peak output voltage swing V
RL = 2 kΩ −13.5
VO = ± 11 V, RL = 2 kΩ 45
VO = ± 10 V, RL = 1 kΩ 38
AVD Large-signal differential voltage amplification V/μV
VO = ± 10 V,
19
RL = 600 Ω
Ci Input capacitance 8 pF
zo Open-loop output impedance IO = 0 50 Ω
VIC = VICRmin,
CMRR Common-mode rejection ratio 131 dB
RS = 50 Ω
VCC ± = ± 4 V to ± 18 V,
kSVR Supply-voltage rejection ratio (ΔVCC ± /ΔVIO) 144 dB
RS = 50 Ω
ICC Supply current VO = 0, No load 3.8 mA
12 www.ti.com
TLE20x7Y operating characteristics at specified free-air temperature, VCC ± = ±15 V

TLE20x7Y
MIN TYP MAX
RL = 2 kΩ, CL = 100 pF, TLE2027 2.8
SR Slew rate at unity gain V/ s
V/μs
See Figure 1 TLE2037 7.5
RS = 20 Ω, f = 10 Hz 3.3
Vn Equivalent input noise voltage (see Figure 2) nV/√Hz
RS = 20 Ω, f = 1 kHz 2.5
VN(PP) Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 10 Hz 50 nV
f = 10 Hz 10
In Equivalent input noise current pA/√Hz
f = 1 kHz 0.8
VO = + 10 V, AVD = 1,
TLE2027 < 0.002%
See Note 5
VO = + 10 V, AVD = 5,
TLE2037 < 0.002%
See Note 5
TLE2027 13
B1 Unity gain bandwidth (see Figure 3)
Unity-gain RL = 2 kΩ
kΩ, CL = 100 pF MHz
TLE2037 50
TLE2027 30
BOM Maximum output-swing
output swing bandwidth RL = 2 kΩ kHz
TLE2037 80
TLE2027 55°
φm Phase margin at unity gain (see Figure 3) RL = 2 kΩ
kΩ, CL = 100 pF
TLE2037 50°
www.ti.com 13
PARAMETER MEASUREMENT INFORMATION

Rf 2 kΩ
15 V 15 V
− −
VO VO
RI
VI + +
− 15 V CL = RL = 2 kΩ − 15 V
20 Ω 20 Ω
100 pF
(see Note A)
NOTE A: CL includes fixture capacitance.
Figure 1. Slew-Rate Test Circuit Figure 2. Noise-Voltage Test Circuit
Rf
10 kΩ
15 V
15 V
100 Ω −
VI −
RI VO
VO
VI +
+
− 15 V CL = 2 kΩ
−15 V CL = 2 kΩ 100 pF
100 pF (see Note A)
(see Note A)
NOTE A: CL includes fixture capacitance. NOTES: A. CL includes fixture capacitance.

B. For the TLE2037 and TLE2037A,
AVD must be ≥ 5.
Figure 3. Unity-Gain Bandwidth and Figure 4. Small-Signal Pulse-

Phase-Margin Test Circuit (TLE2027 Only) Response Test Circuit
14 www.ti.com
typical values
Typical values presented in this data sheet represent the median (50% point) of device parametric performance.
initial estimates of parameter distributions

In the ongoing program of improving data sheets and supplying more information to our customers, Texas
Instruments has added an estimate of not only the typical values but also the spread around these values. These
are in the form of distribution bars that show the 95% (upper) points and the 5% (lower) points from the
characterization of the initial wafer lots of this new device type (see Figure 5). The distribution bars are shown
at the points where data was actually collected. The 95% and 5% points are used instead of ± 3 sigma since
some of the distributions are not true Gaussian distributions.
The number of units tested and the number of different wafer lots used are on all of the graphs where distribution
bars are shown. As noted in Figure 5, there were a total of 835 units from two wafer lots. In this case, there is
a good estimate for the within-lot variability and a possibly poor estimate of the lot-to-lot variability. This is always
the case on newly released products since there can only be data available from a few wafer lots.
The distribution bars are not intended to replace the minimum and maximum limits in the electrical tables. Each
distribution bar represents 90% of the total units tested at a specific temperature. While 10% of the units tested
fell outside any given distribution bar, this should not be interpreted to mean that the same individual devices
fell outside every distribution bar.
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
5
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
VCC± = ±15 V 95% point on the distribution bar
(5% of the devices fell above this point.)
ÎÎÎÎÎÎÎÎ
VO = 0
4.5 No Load
ÎÎÎÎÎÎÎÎ
I CC − Supply Current − mA
Sample Size = 835 Units 90% of the devices were within the upper
From 2 Water Lots and lower points on the distribution bar.
4 5% point on the distribution bar

(5% of the devices fell below this point.)
3.5
2.5
− 75 − 50 − 25 0 25 50 75 100 125 150
TA − Free-Air Temperature − °C
Figure 5. Sample Graph With Distribution Bars
www.ti.com 15
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage Distribution 6, 7
ΔVIO Input offset voltage change vs Time after power on 8, 9
IIO Input offset current vs Free-air temperature 10
vs Free-air
Free air temperature 11
IIB Input bias current
vs Common-mode input voltage 12
II Input current vs Differential input voltage 13
VO(PP) Maximum peak-to-peak output voltage vs Frequency 14, 15
Maximum (positive/negative) peak output vs Load resistance 16, 17
VOM
voltage vs Free-air temperature 18, 19
vs Supply voltage 20
vs Load resistance 21
AVD Large signal differential voltage amplification
Large-signal
vs Frequency 22 − 25
vs Free-air temperature 26
zo Output impedance vs Frequency 27
CMRR Common-mode rejection ratio vs Frequency 28
kSVR Supply-voltage rejection ratio vs Frequency 29
vs Supply voltage 30, 31
IOS Short-circut
Short circut output current vs Elapsed time 32, 33
vs Free-air temperature 34, 35
ICC Supply current
vs Free-air temperature 37
Small signal 38, 40
Voltage follower pulse response
Voltage-follower
Large signal 39, 41
Vn Equivalent input noise voltage vs Frequency 42
Noise voltage (referred to input) Over 10-second interval 43
B1 Unity gain bandwidth
Unity-gain
vs Load capacitance 45
Gain bandwidth product
vs Load capacitance 47
SR Slew rate vs Free-air temperature 48, 49
vs Supply voltage 50, 51
φm Phase margin vs Load capacitance 52, 53
vs Free-air temperature 54, 55
Phase shift vs Frequency 22 − 25
16 www.ti.com
DISTRIBUTION
INPUT OFFSET VOLTAGE
INPUT OFFSET VOLTAGE CHANGE
16
14
ÎÎÎÎÎÎÎÎÎÎÎÎ
1568 Amplifiers Tested From 2 Wafer Lots
VCC± = +15 V
12
vs
TIME AFTER POWER ON
ÎÎÎÎ
TA = 25°C
VIO − Change in Input Offset Voltage − μV

D Package
Percentage of Amplifiers − %
12
10
10
8
8
6
6
4
ÎÎÎÎÎÎÎÎÎÎÎ
ÁÁÁÁÁÁ 4
ÁÁ ÎÎÎÎÎÎÎÎÎÎÎ
ÁÁÁÁÁÁ 50 Amplifiers Tested From 2 Wafer Lots
ÁÁ ÎÎÎÎ ÁÁÁÁÁÁ
2 2 VCC± = ±15 V
AVIO
TA = 25°C
0
− 120 − 90 − 60 − 30 0 30 60
VIO − Input Offset Voltage − μV
90 120
ÁÁ ÎÎÎÎΔ
0
0
D Package
10 20 30 40
t − Time After Power On − s
50 60
Figure 6 Figure 7
INPUT OFFSET VOLTAGE CHANGE INPUT OFFSET CURRENT †

vs vs
ÁÁÁÁÁÁÁ
TIME AFTER POWER ON FREE-AIR TEMPERATURE
ÁÁÁÁÁÁÁ
6 30
VIO − Change in Input Offset Voltage − μV
VCC± = ±15 V
ÁÁÁÁÁÁÁ
VIC = 0
5 25 Sample Size = 833 Units
ÁÁÁÁÁÁÁ
I IO − Input Offset Current − nA
From 2 Wafer Lots
4 20
3 15
2
50 Amplifiers Tested From 2 Wafer Lots
10
ÁÁ ÎÎÎÎ
IIO
1 VCC± = ±15 V 5
TA = 25°C
ÁÁ ÎÎÎÎ
AVIO
P Package
Δ
0 0
0 20 40 60 80 100 120 140 160 180 − 75 − 50 − 25 0 25 50 75 100 125 150
t − Time After Power On − s TA − Free-Air Temperature − °C
Figure 8 Figure 9
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
www.ti.com 17
INPUT BIAS CURRENT † INPUT BIAS CURRENT

vs vs
ÁÁÁÁÁÁÁÁ
FREE-AIR TEMPERATURE COMMON-MODE INPUT VOLTAGE
60 40
ÁÁÁÁÁÁÁÁ
VCC ± = ± 15 V VCC± = ± 15 V
ÁÁÁÁÁÁÁÁ
50 35 TA = 25°C
VIC = 0
ÁÁÁÁÁÁÁÁ
Sample Size = 836 Units
IB − Input Bias Current − nA
IB − Input Bias Current − nA

40 From 2 Wafer Lots 30
30 25
20 20
10 15
0 10
IIIB
IIIB
−10 5
−20 0
−75 −50 −25 0 25 50 75 100 125 150 −12 −8 −4 0 4 8 12
TA − Free-Air Temperature − °C VIC − Common-Mode Input Voltage − V
Figure 10 Figure 11
TLE2027
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE †
INPUT CURRENT vs
ÎÎÎÎÎ
vs FREQUENCY
DIFFERENTIAL INPUT VOLTAGE
ÁÁÁÁÁ ÎÎÎÎÎ
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
30
1 VCC± = ±15 V
ÁÁÁÁÁ ÎÎÎÎÎ
RL = 2 kΩ
0.8 VCC ± = ± 15 V
ÁÁÁÁÁ
VIC = 0 25
0.6 TA = 25°C
IIII − Input Current − mA
0.4 20
0.2
0 15
TA = 125°C
− 0.2
10
− 0.4
− 0.6
5
− 0.8 TA = − 55°C
−1 0
− 1.8 − 1.2 − 0.6 0 0.6 1.2 1.8 10 k 100 k 1M 10 M
VID − Differential Input Voltage − V f − Frequency − Hz
Figure 12 Figure 13
18 www.ti.com
TLE2037
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE † MAXIMUM POSITIVE PEAK
vs OUTPUT VOLTAGE
ÎÎÎÎÎ
ÁÁÁÁÁ
FREQUENCY vs
LOAD RESISTANCE
ÁÁÁÁÁ
ÎÎÎÎÎ
30
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
OM + − Maximum Positive Peak Output Voltage − V

14
VCC ± = ± 15 V
25
ÁÁÁÁÁ
ÎÎÎÎÎ
RL = 2 kΩ
12
20 10
ÎÎÎÎ 8
ÎÎÎÎ
15
TA = 125°C
6
10
4
ÁÁÁÁÁÁ
TA = − 55°C
ÁÁÁ ÁÁÁÁÁÁÁÁ
5
2 VCC ± = ± 15 V
ÁÁÁ ÁÁÁÁÁÁÁÁ
VO(PP)
TA = 25°C
VVOM+
0
ÁÁÁ ÁÁ
0
10 k 100 k 1M 10 M 100 M 100 1k 10 k
f − Frequency − Hz RL − Load Resistance − Ω
Figure 14 Figure 15
MAXIMUM NEGATIVE PEAK MAXIMUM POSITIVE PEAK
OUTPUT VOLTAGE OUTPUT VOLTAGE †
vs vs
ÎÎÎÎÎ
LOAD RESISTANCE FREE-AIR TEMPERATURE
OM + − Maximum Positive Peak Output Voltage − V
OM − − Maximum Negative Peak Output Voltage − V
13.5
ÎÎÎÎÎ
− 14
VCC± = ± 15 V
− 12 13.4
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
RL = 2 kΩ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
From 2 Wafer Lots
− 10
13.3
−8
13.2
−6
13.1
ÁÁÁÁÁ −4
ÁÁÁÁÁ VCC ± = ± 15 V
ÁÁ 13
ÁÁ ÁÁÁÁÁ ÁÁ
−2
TA = 25°C
VVOM+
ÁÁ ÁÁ
VVOM−
0 12.9
− 75 − 50 − 25 0 25 50 75 100 125 150
ÁÁ
100 1k 10 k
RL − Load Resistance − Ω TA − Free-Air Temperature − °C
Figure 16 Figure 17
www.ti.com 19
LARGE-SIGNAL DIFFERENTIAL
MAXIMUM NEGATIVE PEAK VOLTAGE AMPLIFICATION
OUTPUT VOLTAGE † vs
vs SUPPLY VOLTAGE
FREE-AIR TEMPERATURE 50
ÎÎÎÎ
OM − − Maximum Negative Peak Output Voltage − V
ÎÎÎÎÎ
− 13 TA = 25°C
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
VCC ± = ± 15 V RL = 2 kΩ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
RL = 2 kΩ
Voltage Amplification − V/ μ V
40
AVD − Large-Signal differential

− 13.2 Sample Size = 831 Units
ÎÎÎÎÎÎ
From 2 Wafer Lots RL = 1 kΩ
30
− 13.4
20
− 13.6
ÁÁ
ÁÁ
RL = 600 Ω
AVD
ÁÁ
10
− 13.8
ÁÁÁ
ÁÁÁ
VVOM−
− 14 0
ÁÁÁ − 75 − 50 − 25 0 25 50 75 100 125 150 0 4 8 12 16 20
TA − Free-Air Temperature − °C ⎟ VCC±⎟ − Supply Voltage − V
Figure 18 Figure 19
VOLTAGE AMPLIFICATION
vs
LOAD RESISTANCE
50
ÁÁÁÁ
ÁÁÁÁ
VCC± = ± 15 V
ÁÁÁÁ
TA = 25°C
40
30
ÁÁ
20
ÁÁ
AVD
ÁÁ 10
0
100 200 400 1k 2k 4k 10 k
RL − Load Resistance − Ω
Figure 20
20 www.ti.com
TLE2027
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
160 75°
AVD− Large-Signal Differential 140 Phase Shift 100°

Voltage Amplification − dB
120 125°
AVD
100 150°
Phase Shift
80 175°
60 200°
ÁÁ
ÁÁ
AVD
40 225°
VCC± = ± 15 V
RL = 2 kΩ
20 CL = 100 pF 250°
TA = 25°C
0 275°
0.1 100 100 k 100 M
f − Frequency − Hz
Figure 21
TLE2037
vs
FREQUENCY
160 75°
140 ÎÎÎÎÎ
ÎÎÎÎÎ
Phase Shift 100°
ÎÎ
AVD − Large-Signal Differential
125°
120
100 ÎÎ AVD
150°
Phase Shift
80 175°
Á ÁÁÁÁÁ
60 200°
Á 40
ÁÁÁÁÁ
VCC± = ± 15 V 225°
AVD
Á 20 ÁÁÁÁÁ
RL = 2 kΩ
ÁÁÁÁÁ
CL = 100 pF
TA = 25°C
250°
0 275°
0.1 100 100 k 100 M
f − Frequency − MHz
Figure 22
www.ti.com 21
TLE2027
vs
FREQUENCY
6 100°
3 125°
AVD− Large-Signal Differential
0 150°
−3 175°
Phase Shift
AVD
−6 200°
Phase Shift
−9 225°
ÁÁ
ÁÁ ÎÎÎÎÎ
− 12 250°
AVD
VCC± = ± 15 V
ÁÁ − 15
ÎÎÎÎÎ
RL = 2 kΩ
275°
ÎÎÎÎÎ
CL = 100 pF
TA = 25°C
− 18 300°
10 20 40 70 100
Figure 23
TLE2037
vs
FREQUENCY
30 100 °
25
ÎÎÎ ÎÎÎÎÎ
AVD Phase Shift
125 °
AVD − Large-Signal Differential
20 150 °
15 175 °
Phase Shift
10 200 °
5 225 °
ÁÁ ÁÁÁÁÁ
ÁÁ ÁÁÁÁÁ
0 VCC± = ± 15 V 250 °
AVD
RL = 2 kΩ
ÁÁÁÁÁ −5 CL = 100 pF 275 °
ÁÁÁÁÁ
TA = 25°C
−10 300 °
1 2 4 10 20 40 100
Figure 24
22 www.ti.com
VOLTAGE AMPLIFICATION †
vs OUTPUT IMPEDANCE
FREE-AIR TEMPERATURE vs
FREQUENCY
60
ÁÁÁÁÁ
100
VCC ± = ± 15 V
VCC ± = ± 15 V
ÁÁ ÁÁÁÁÁ TA = 25°C
ÎÎÎÎÎ ÁÁ
z o − Output Impedance − Ω
ÎÎÎÎÎ
10
50 RL = 2 kΩ AVD = 100
ÎÎÎÎÎ RL = 1 kΩ 1
See Note A
ÁÁ 40
ÁÁ AVD = 10
ÁÁ ÁÁ
AVD
zo
ÁÁ
−10
30
−75 −50 −25 0 25 50 75 100 125 150 −100
10 100 1k 10 k 100 k 1M 10 M 100 M
TA − Free-Air Temperature − °C
f − Frequency − Hz
NOTE A: For this curve, the TLE2027 is AVD = 1 and the
TLE2037 is AVD = 5.
Figure 25 Figure 26
COMMON-MODE REJECTION RATIO SUPPLY-VOLTAGE REJECTION RATIO

vs vs
FREQUENCY FREQUENCY
140
ÎÎÎÎÎ
ÁÁÁÁ 140
ÎÎÎÎÎÎ
ÁÁÁÁ
ÁÁÁÁ
ÎÎÎÎÎ
ÎÎÎÎ ÁÁÁÁ
ÎÎÎÎ
VCC ± = ± 15 V
CMRR − Common-Mode Rejection Ratio − dB
VCC ± = ± 15 V
KSVR − Supply-Voltage Rejection Ratio − dB
TA = 25°C
ÁÁÁÁ
120 TA = 25°C 120
ÎÎÎÎ
100 100
kSVR −
80 80
60
40
60
40
ÎÎÎ
ÎÎÎ kSVR +
20 20
0 0
10 100 1k 10 k 100 k 1 M 10 M 100 M 10 100 1k 10 k 100 k 1 M 10 M 100 M
f − Frequency − Hz f − Frequency − Hz
Figure 27 Figure 28
www.ti.com 23
SHORT-CIRCUIT OUTPUT CURRENT SHORT-CIRCUIT OUTPUT CURRENT

vs vs
ÁÁÁÁÁ ÁÁÁÁÁÁ
SUPPLY VOLTAGE SUPPLY VOLTAGE
44
−42
VID = 100 mV VID = − 100 mV
OS − Short-Circuit Output Current − mA

VO = 0 42 VO = 0
ÁÁÁÁÁ
ÎÎÎÎ ÁÁÁÁÁÁ
−40 TA = 25°C TA = 25°C
P Package P Package
40
−38
38
−36
36
−34
34
ÁÁ ÁÁ
ÁÁ ÁÁ
−32 32
IIOS
IIOS
−30 30
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
⎟ VCC±⎟ − Supply Voltage − V ⎟ VCC±⎟ − Supply Voltage − V
Figure 29 Figure 30
SHORT-CIRCUIT OUTPUT CURRENT SHORT-CIRCUIT OUTPUT CURRENT

vs vs
ELAPSED TIME ELAPSED TIME
− 45
ÁÁÁÁÁ
VCC ± = ± 15 V
44
ÁÁÁÁÁ
ÁÁÁÁÁ ÁÁÁÁÁ
VCC ± = ± 15 V
VID = 100 mV VID = 100 mV
− 43
ÁÁÁÁÁ
VO = 0
ÁÁÁÁÁ
VO = 0
ÁÁÁÁÁ
ÎÎÎÎ ÁÁÁÁÁ
ÎÎÎÎÎ
TA = 25°C 42 TA = 25°C
P Package P Package
− 41 40 ÁÁÁÁÁ
− 39 38
ÁÁÁ
ÁÁÁ ÁÁ
− 37 36
IIOS
IIOS
ÁÁÁ − 35
0 30 60 90 120 150 180
ÁÁ 34
0 30 60 90 120 150 180
t − Elasped Time − s t − Elasped Time − s
Figure 31 Figure 32
24 www.ti.com
SHORT-CIRCUIT OUTPUT CURRENT † SHORT-CIRCUIT OUTPUT CURRENT †
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
− 48
ÁÁÁÁÁ
ÁÁÁÁÁVCC ± = ± 15 V
46
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC ± = ± 15 V

ÁÁÁÁÁ ÁÁÁÁÁ
VID = 100 mV VID = − 100 mV
− 44 VO = 0
VO = 0 42
− 40 ÁÁÁÁÁP Package
38
ÁÁÁÁÁ
P Package
− 36
34
− 32
ÁÁ ÁÁ
ÁÁ ÁÁ
30
− 28
IIOS
IIOS
ÁÁ − 24
− 75 − 50 − 25 0 25 50 75 100 125 150
ÁÁ 26
− 75 − 50 − 25 0 25 50 75 100 125 150
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C
Figure 33 Figure 34
SUPPLY CURRENT † SUPPLY CURRENT †

vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
6
ÁÁÁÁ 5
ÁÁÁÁÁÁÁ
ÁÁÁÁ ÁÁÁÁÁÁÁ
VO = 0 VCC ± = ± 15 V
VO = 0
ÎÎÎÎ ÁÁÁÁÁÁÁ
No Load
5 TA = 125°C No Load
ÁÁÁÁÁÁÁ
4.5 Sample Size = 836 Units
I CC − Supply Current − mA
CC − Supply Current − mA
From 2 Wafer Lots

4
ÎÎÎÎ
ÎÎÎÎ
TA = 25°C 4
3
ÎÎÎÎ
ÎÎÎÎ
TA = − 55°C 3.5
ÁÁ
ÁÁ
2
ÁÁ
ÁÁ
ICC
IICC
3
1
0 2.5
0 2 4 6 8 10 12 14 16 18 20 − 75 − 50 − 25 0 25 50 75 100 125 150
⎟ VCC±⎟ − Supply Voltage − V TA − Free-Air Temperature − °C
Figure 35 Figure 36
www.ti.com 25
TLE2027 TLE2027
VOLTAGE-FOLLOWER VOLTAGE-FOLLOWER
SMALL-SIGNAL LARGE-SIGNAL
PULSE RESPONSE PULSE RESPONSE
100
ÎÎÎÎÎ 15
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
VCC± = ±15 V VCC± = ±15 V
RL = 2 kΩ RL = 2 kΩ
ÎÎÎÎÎ CL = 100 pF
10
ÎÎÎÎÎCL = 100 pF
ÎÎÎÎÎ ÎÎÎÎÎ
TA = 25°C TA = 25°C
VO − Output Voltage − mV
50 See Figure 4 See Figure 1
VO − Output Voltage − V
5
0 0
−5
− 50
− 10
− 100 − 15
0 200 400 600 800 1000 0 5 10 15 20 25
t − Time − ns t − Time − μs
Figure 37 Figure 38
TLE2037 TLE2037
VOLTAGE-FOLLOWER VOLTAGE-FOLLOWER
SMALL-SIGNAL LARGE-SIGNAL
PULSE RESPONSE
ÎÎÎÎÎÎ
PULSE RESPONSE
100 15
ÎÎÎÎÎÎ
VCC ± = ± 15 V
AVD = 5
10 RL = 2 kΩ
ÎÎÎÎÎ
CL = 100 pF
50
O − Output Voltage − mV
ÎÎÎÎÎ
TA = 25°C
O − Output Voltage − V
5 See Figure 1
0 0
ÁÁÁÁÁÁ
ÁÁ ÁÁÁÁÁÁ ÁÁ
VCC ± = ± 15 V
AVD = 5 −5
ÁÁ ÁÁÁÁÁÁ ÁÁ
VO
VO
RL = 2 kΩ
− 50
V
ÁÁÁÁÁÁ
CL = 100 pF
TA = 25°C − 10
See Figure 4
− 100 − 15
0 100 200 300 400 0 2 4 6 8 10
t − Time − ns t − Time − μs
Figure 39 Figure 40
26 www.ti.com
EQUIVALENT INPUT NOISE VOLTAGE NOISE VOLTAGE

vs (REFERRED TO INPUT)
ÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ
FREQUENCY OVER A 10-SECOND INTERVAL
10 50
nV/ Hz
VCC ± = ± 15 V
VCC ± = ± 15 V
V n − Equivalent Input Noise Voltage − nVHz
RS = 20 Ω 40
TA = 25°C f = 0.1 to 10 Hz
ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ
8 See Figure 2 TA = 25°C
30
ÁÁÁÁÁÁÁ
From 2 Wafer Lots 20
Noise Voltage − nV
6 10
4 − 10
− 20
2 − 30
Vn
− 40
0 − 50
1 10 100 1k 10 k 100 k 0 2 4 6 8 10
f − Frequency − Hz t − Time − s
Figure 41 Figure 42
TLE2027
UNITY-GAIN BANDWIDTH TLE2037
vs GAIN-BANDWIDTH PRODUCT
SUPPLY VOLTAGE vs
20
ÁÁÁÁÁ SUPPLY VOLTAGE
ÁÁÁÁÁ
RL = 2 kΩ 52
CL = 100 pF f = 100 kHz
TA = 25°C
ÁÁÁÁÁ RL = 2 kΩ
ÁÁÁÁÁ
18 See Figure 3 CL = 100 pF
Gain-Bandwidth Product − MHz
B1 − Unity-Gain Bandwidth − MHz
TA = 25°C
51
16
50
14
49
12
10 48
0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20
| VCC± | − Supply Voltage − V ⎟ VCC±⎟ − Supply Voltage − V
Figure 43 Figure 44
www.ti.com 27
TLE2027
UNITY-GAIN BANDWIDTH TLE2037
vs GAIN-BANDWIDTH PRODUCT
LOAD CAPACITANCE vs
16 LOAD CAPACITANCE
ÁÁÁÁÁÁ
VCC± = ±15 V 52
ÁÁÁÁÁÁ
RL = 2 kΩ VCC± = ±15 V
TA = 25°C RL = 2 kΩ
ÁÁÁÁÁÁ
See Figure 3 TA = 25°C
B1 − Unity-Gain Bandwidth − MHz
Gain-Bandwidth Product − MHz

12
51
8 50
4 49
0 48
100 1000 10000 100 1000 10000
CL − Load Capacitance − pF CL − Load Capacitance − pF
Figure 45 Figure 46
TLE2027
SLEW RATE † TLE2037
vs SLEW RATE †
ÎÎÎÎÎÎ
ÁÁÁÁÁ
3
ÁÁÁÁÁ
ÎÎÎÎÎÎ
10
VCC ± = ± 15 V
2.8
ÁÁÁÁÁ AVD = 5
ÁÁÁÁÁ
RL = 2 kΩ
9
CL = 100 pF
ÁÁÁÁÁ
SR − Slew Rate − V/ μ s
SR − Slew Rate − V/ μs
See Figure 1
2.6
8
2.4
ÎÎÎÎÎ
7
ÎÎÎÎÎ VCC± = ±15 V
ÎÎÎÎÎ
AVD = 1
2.2 6
RL = 2 kΩ
ÎÎÎÎÎ
CL = 100 pF
See Figure 1
2 5
− 75 − 50 − 25 0 25 50 75 100 125 150 − 75 − 50 − 25 0 25 50 75 100 125 150
Figure 47 Figure 48
28 www.ti.com
TLE2027
PHASE MARGIN TLE2037
PHASE MARGIN
vs
vs
SUPPLY VOLTAGE
ÎÎÎÎÎ ÁÁÁÁÁ
SUPPLY VOLTAGE
58°
52°
RL = 2 kΩ
AVD = 5
56° CL = 100 pF
RL = 2 kΩ
TA = 25°C 50°
CL = 100 pF
See Figure 3
54° TA = 25°C
48°
φ m − Phase Margin
52°
46°
50°
44°
ÁÁ 48°
ÁÁ 46°
42°
40°
44°
42° 38°
0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20
| VCC± | − Supply Voltage − V ⎟ VCC±⎟ − Supply Voltage − V
Figure 49 Figure 50
TLE2027
PHASE MARGIN TLE2037
vs PHASE MARGIN
LOAD CAPACITANCE vs
60°
ÎÎÎÎÎ LOAD CAPACITANCE
ÁÁÁÁÁ
60°
VCC± = ±15 V VCC ± = ± 15 V
RL = 2 kΩ RL = 2 kΩ
50° TA = 25°C
TA = 25°C
ÎÎÎÎÎ
50°
See Figure 3
40°
40°
30°
ÁÁ
30°
ÁÁ 20° 20°
10° 10°
0°
0° 100 1000 10000
100 1000
CL − Load Capacitance − pF CL − Load Capacitance − pF
Figure 51 Figure 52
www.ti.com 29
TLE2027
PHASE MARGIN † TLE2037
vs PHASE MARGIN †
65°
ÎÎÎÎÎ 55°
ÁÁÁÁÁÁ
ÎÎÎÎÎ ÁÁÁÁÁÁ
VCC± = ±15 V VCC ± = ± 15 V
RL = 2 kΩ AVD = 5
60°
ÎÎÎÎÎ
TA = 25°C
ÁÁÁÁÁÁRL = 2 kΩ
ÁÁÁÁÁÁ
See Figure 3 53°
CL = 100 pF
55°
51°
50°
ÁÁ
ÁÁ 45°
49°
47°
40°
45°
35° − 75 − 50 − 25 0 25 50 75 100 125 150
− 75 − 50 − 25 0 25 50 75 100 125 150
Figure 53 Figure 54
30 www.ti.com
APPLICATION INFORMATION
input offset voltage nulling

The TLE2027 and TLE2037 series offers external null pins that can be used to further reduce the input offset
voltage. The circuits of Figure 55 can be connected as shown if the feature is desired. If external nulling is not
needed, the null pins may be left disconnected.
1 kΩ
VCC +
10 kΩ
VCC + 4.7 kΩ
4.7 kΩ
IN − − IN − −
OUT OUT
IN + + IN + +
VCC − VCC −
(a) STANDARD ADJUSTMENT (b) ADJUSTMENT WITH IMPROVED SENSITIVITY
Figure 55. Input Offset Voltage Nulling Circuits
voltage-follower applications
The TLE2027 circuitry includes input-protection diodes to limit the voltage across the input transistors; however,
no provision is made in the circuit to limit the current if these diodes are forward biased. This condition can occur
when the device is operated in the voltage-follower configuration and driven with a fast, large-signal pulse. It
is recommended that a feedback resistor be used to limit the current to a maximum of 1 mA to prevent
degradation of the device. Also, this feedback resistor forms a pole with the input capacitance of the device.
For feedback resistor values greater than 10 kΩ, this pole degrades the amplifier phase margin. This problem
can be alleviated by adding a capacitor (20 pF to 50 pF) in parallel with the feedback resistor (see Figure 56).
CF = 20 to 50 pF
IF ≤ 1 mA
RF
VCC
−
VO
VI
+
VCC −
Figure 56. Voltage Follower
www.ti.com 31
macromodel information
Macromodel information provided was derived using Microsim Parts™, the model generation software used
with Microsim PSpice ™. The Boyle macromodel (see Note 6) and subcircuit in Figure 57, Figure 58, and
Figure 59 were generated using the TLE20x7 typical electrical and operating characteristics at 25°C. Using this
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
• Maximum positive output voltage swing • Gain-bandwidth product
• Maximum negative output voltage swing • Common-mode rejection ratio
• Slew rate • Phase margin
• Quiescent power dissipation • DC output resistance
• Input bias current • AC output resistance
• Open-loop voltage amplification • Short-circuit output current limit
NOTE 6: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
99
3 +
VCC + dln
9 egnd 92
rc1 c1 rc2 + − fb ro2 90 91
rp + −
1 11 12 vb + dip
IN + + − hlim vip vin
vc − − +
IN − Q1 Q2 r2 C2
2 − 6 7
dp 13 53 +
14 ree
cee ga vlim
re1 re2 dc gcm
−
8
10 ro1
lee
54 de
VCC − − + 5
4 ve
OUT
Figure 57. Boyle Macromodel
PSpice and Parts are trademarks of MicroSim Corporation.
32 www.ti.com
macromodel information (continued)

.subckt TLE2027 1 2 3 4 5 q2 12 1 14 qx
* r2 6 9 100.0E3
c1 11 12 4.003E-12 rc1 3 11 530.5
c2 6 7 20.00E-12 rc2 3 12 530.5
dc 5 53 dz re1 13 10 −393.2
de 54 5 dz re2 14 10 −393.2
dlp 90 91 dz ree 10 99 3.571E6
dln 92 90 dx ro1 8 5 25
dp 4 3 dz ro2 7 99 25
egnd 99 0 poly(2) (3,0) rp 3 4 8.013E3
(4,0) 0 5 .5 vb 9 0 dc 0
fb 7 99 poly(5) vb vc vc 3 53 dc 2.400
ve vlp vln 0 954.8E6 −1E9 1E9 1E9 ve 54 4 dc 2.100
−1E9 vlim 7 8 dc 0
ga 6 0 11 12 vlp 91 0 dc 40
2.062E-3 vln 0 92 dc 40
gcm 0 6 10 99 .modeldx D(Is=800.0E-18)
531.3E-12 .modelqx NPN(Is=800.0E-18
iee 10 4 dc 56.01E-6 Bf=7.000E3)
hlim 90 0 vlim 1K .ends
q1 11 2 13 qx
Figure 58. TLE2027 Macromodel Subcircuit
.subckt TLE2037 1 2 3 4 5 q2 12 1 14 qz
* r2 6 9 100.0E3
c1 11 12 4.003E−12 rc1 3 11 471.5
c2 6 7 7.500E−12 rc2 3 12 471.5
dc 5 53 dz re1 13 10 A448
de 54 5 dz re2 14 10 A448
dlp 90 91 dz ree 10 99 3.555E6
dln 92 90 dx ro1 8 5 25
dp 4 3 dz ro2 7 99 25
egnd 99 0 poly(2) (3,0) rp 3 4 8.013E3
(4,0) 0 .5 .5 vb 9 0 dc 0
fb 7 99 poly(5) vb vc vc 3 53 dc 2.400
ve vip vln 0 923.4E6 A800E6 ve 54 4 dc 2.100
800E6 800E6 A800E6 vlim 7 8 dc 0
ga 6 0 11 12 2.121E−3 vlp 91 0 dc 40
gcm 0 6 10 99 597.7E−12 vln 0 92 dc 40
iee 10 4 dc 56.26E−6 .model dxD(Is=800.0E−18)
hlim 90 0 vlim 1K .model qxNPN(Is=800.0E−18
q1 11 2 13 qx Bf=7.031E3)
.ends
Figure 59. TLE2037 Macromodel Subcircuit
www.ti.com 33
REVISION HISTORY
Changes from Revision B (October 2006) to Revision C

• Changed values of Vn, VN(PP), and In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 11
34 www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
5962-9089601M2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9089601M2A
TLE2027MFKB
5962-9089601MPA ACTIVE CDIP JG 8 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 9089601MPA Samples
& Green TLE2027M
5962-9089603Q2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9089603Q2A
TLE2027AMFKB
5962-9089603QPA ACTIVE CDIP JG 8 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 9089603QPA Samples
& Green TLE2027AM
TLE2027AMD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 2027AM Samples
TLE2027AMFKB ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9089603Q2A
TLE2027AMFKB
TLE2027AMJG ACTIVE CDIP JG 8 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 TLE2027 Samples
& Green AMJG
TLE2027AMJGB ACTIVE CDIP JG 8 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 9089603QPA Samples
& Green TLE2027AM
TLE2027CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 2027C Samples
TLE2027CDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 2027C Samples
TLE2027CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 2027C Samples
TLE2027ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 2027I Samples
TLE2027IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 2027I Samples
TLE2027MD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 2027M Samples
TLE2027MFKB ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9089601M2A
TLE2027MFKB
TLE2027MJGB ACTIVE CDIP JG 8 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 9089601MPA Samples
& Green TLE2027M
Addendum-Page 1
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TLE2037AMD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 2037AM Samples
TLE2037AMDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 2037AM Samples
TLE2037CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 2037C Samples
TLE2037CDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 2037C Samples
TLE2037CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 2037C Samples
TLE2037ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 2037I Samples
TLE2037IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 2037I Samples
TLE2037IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 2037I Samples
TLE2037MD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 2037M Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLE2027, TLE2027M, TLE2037A :
• Catalog : TLE2027
• Automotive : TLE2037A-Q1
• Enhanced Product : TLE2027-EP, TLE2027-EP
• Military : TLE2027M
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Apr-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLE2027CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLE2027IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLE2037CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLE2037IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLE2027CDR SOIC D 8 2500 340.5 336.1 25.0
TLE2027IDR SOIC D 8 2500 340.5 336.1 25.0
TLE2037CDR SOIC D 8 2500 340.5 336.1 25.0
TLE2037IDR SOIC D 8 2500 340.5 336.1 25.0
TUBE

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9089601M2A FK LCCC 20 1 506.98 12.06 2030 NA
5962-9089603Q2A FK LCCC 20 1 506.98 12.06 2030 NA
TLE2027AMD D SOIC 8 75 505.46 6.76 3810 4
TLE2027AMFKB FK LCCC 20 1 506.98 12.06 2030 NA
TLE2027CD D SOIC 8 75 507 8 3940 4.32
TLE2027CD D SOIC 8 75 505.46 6.76 3810 4
TLE2027CDG4 D SOIC 8 75 505.46 6.76 3810 4
TLE2027CDG4 D SOIC 8 75 507 8 3940 4.32
TLE2027ID D SOIC 8 75 507 8 3940 4.32
TLE2027ID D SOIC 8 75 505.46 6.76 3810 4
TLE2027MD D SOIC 8 75 505.46 6.76 3810 4
TLE2027MFKB FK LCCC 20 1 506.98 12.06 2030 NA
TLE2037AMD D SOIC 8 75 505.46 6.76 3810 4
TLE2037AMDG4 D SOIC 8 75 505.46 6.76 3810 4
TLE2037CD D SOIC 8 75 505.46 6.76 3810 4
TLE2037CD D SOIC 8 75 507 8 3940 4.32
TLE2037CDG4 D SOIC 8 75 505.46 6.76 3810 4
TLE2037CDG4 D SOIC 8 75 507 8 3940 4.32
TLE2037ID D SOIC 8 75 507 8 3940 4.32
TLE2037ID D SOIC 8 75 505.46 6.76 3810 4
TLE2037MD D SOIC 8 75 505.46 6.76 3810 4
GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4229370\/A\
www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8 5
0.280 (7,11)
0.245 (6,22)
1 4
0.065 (1,65)
0.045 (1,14)
0.063 (1,60) 0.310 (7,87)

0.020 (0,51) MIN
0.015 (0,38) 0.290 (7,37)
0.200 (5,08) MAX

Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0°–15°
0.015 (0,38)
0.100 (2,54) 0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated

Tle 2027

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Tle 2027

Uploaded by

Copyright:

Available Formats

TLE2027, TLE2037, TLE2027A, TLE2037A, TLE2027Y, TLE2037Y

EXCALIBUR LOW-NOISE HIGH-SPEED

D Outstanding Combination of dc Precision D, JG, OR P PACKAGE

All trademarks are the property of their respective owners.

TLE202xY chip information

BONDING PAD ASSIGNMENTS

CHIP THICKNESS: 15 MILS TYPICAL

ACTUAL DEVICE COMPONENT COUNT

DISSIPATION RATING TABLE

recommended operating conditions

TLE20x7C electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless

Input offset voltage

TLE20x7C operating characteristics at specified free-air temperature, VCC ± = ±15 V, TA = 25°C

TLE20x7I electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless

Input offset voltage

TLE20x7I operating characteristics at specified free-air temperature, VCC ± = ±15 V, TA = 25°C

TLE20x7M electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless

Input offset voltage

TLE20x7M operating characteristics at specified free-air temperature, VCC ± = ±15 V, TA = 25°C

TLE20x7Y electrical characteristics, VCC± = ±15 V, TA = 25°C (unless otherwise noted)

TLE20x7Y operating characteristics at specified free-air temperature, VCC ± = ±15 V

PARAMETER MEASUREMENT INFORMATION

NOTE A: CL includes fixture capacitance.

Figure 1. Slew-Rate Test Circuit Figure 2. Noise-Voltage Test Circuit

NOTE A: CL includes fixture capacitance. NOTES: A. CL includes fixture capacitance.

Figure 3. Unity-Gain Bandwidth and Figure 4. Small-Signal Pulse-

initial estimates of parameter distributions

4 5% point on the distribution bar

Figure 5. Sample Graph With Distribution Bars

VIO − Change in Input Offset Voltage − μV

INPUT OFFSET VOLTAGE CHANGE INPUT OFFSET CURRENT †

From 2 Wafer Lots

INPUT BIAS CURRENT † INPUT BIAS CURRENT

IB − Input Bias Current − nA

OM + − Maximum Positive Peak Output Voltage − V

AVD − Large-Signal differential

ÁÁÁ − 75 − 50 − 25 0 25 50 75 100 125 150 0 4 8 12 16 20

TA − Free-Air Temperature − °C ⎟ VCC±⎟ − Supply Voltage − V

AVD− Large-Signal Differential 140 Phase Shift 100°

ÁÁÁÁÁ −5 CL = 100 pF 275 °

COMMON-MODE REJECTION RATIO SUPPLY-VOLTAGE REJECTION RATIO

SHORT-CIRCUIT OUTPUT CURRENT SHORT-CIRCUIT OUTPUT CURRENT

OS − Short-Circuit Output Current − mA

SHORT-CIRCUIT OUTPUT CURRENT SHORT-CIRCUIT OUTPUT CURRENT

OS − Short-Circuit Output Current − mA

OS − Short-Circuit Output Current − mA

SUPPLY CURRENT † SUPPLY CURRENT †

From 2 Wafer Lots

50 See Figure 4 See Figure 1

EQUIVALENT INPUT NOISE VOLTAGE NOISE VOLTAGE

Gain-Bandwidth Product − MHz

ÎÎÎÎÎ VCC± = ±15 V

input offset voltage nulling

Figure 55. Input Offset Voltage Nulling Circuits

Figure 56. Voltage Follower

Figure 57. Boyle Macromodel

PSpice and Parts are trademarks of MicroSim Corporation.

macromodel information (continued)

Figure 58. TLE2027 Macromodel Subcircuit

Figure 59. TLE2037 Macromodel Subcircuit

Changes from Revision B (October 2006) to Revision C

OTHER QUALIFIED VERSIONS OF TLE2027, TLE2027M, TLE2037A :

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product