A O.

5V 6-bit Scalable Phase Interpolator

Satoshi Kumaki , Abul Hasan Johari \ Takeshi Matsubara \ Isamu Hayashi , and Hiroki Ishikuro
l 2 l

I
Department o/Electric and Electrical Engineering, Keio University, Yokohama, Japan
3-14-1, Hiyoshi, Kohoku-ku, Yokohama, 223-8522, JAPAN
2
Extremely Low Power R&D Dept., STARe, Tokyo, Japan
kumaki@kuro.elec.keio.ac.jp

Abstract- This paper proposes a scalable phase interpolator (PI)

with dual-input inverter. A pseudo-pipelined architecture is
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proposed to realize resolution scalability and to reduce the '

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circuit size and power consumption. By using a simple

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,

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architecture, the proposed circuit operates at 0.5V at which

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conventional analog PI cannot operate. Slew rate of inverter -
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chain is controlled by current starving technique to support

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phase interpolation at wide input frequency range. The PI was
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designed in 65nm-CMOS technology. The circuit simulation

confirms 6-bit phase resolution, DNL of 0.41 LSB, and INL of
1.25 LSB. The power consumption is 0.12 JJWIMHz.
(a) Analog phase interpolator (b) I-bit phase interpolator

Keywords- phase interpolator, multi-phase oscillator, PLL, DLL. Fig. I Design of conventional interpolator

uses simple inverters, it can operate at ultra low supply

I. INTRODUCTION
Phase interpolator has been used in various applications
such as polar modulation circuit in wireless transceiver, phase
locked loop (PLL), and delay locked loop (DLL). Phase
interpolator determines their performance. Various techniques
have been proposed which use multi-phases to improve the
circuit performance.
The circuit that operates at ultra low supply voltage has
been researched actively for such application of wireless
sensor networks. In such applications, the circuit should
operate around O.5V to use environmental power generated by
energy harvesting technique. In order to use a PLL or DLL in
low supply voltage, phase interpolator that operates at ultra
low voltage will be strongly required.
Conventional phase interpolator is designed as pair of
differential amplifier with shared road resistors (Fig.l(a»
which acts as an analog adder circuit. The inputs of the two
differential amplifiers are two phase small swing sinusoidal
signals and the output signal has a phase interpolated by the
ratio of tail currents. This conventional interpolator is
difficult to use under ultra low voltage, because it becomes
difficult to generate a sinusoidal signal. Furthermore, the
circuit consumes constant power even if the input signal
frequency is low. To solve these problems, the other
interpolators use more digital-like technique (Fig.l(b». Such
interpolator uses a middle phase of two input signals
generated by dual-input inverter [ 1]. Because this architecture
voltage and power is consumed only at the transition of the
input signal. In addition, the area becomes very small thanks
to the simple structure. But this method also has problems.
The circuit size and power consumption becomes large if high
resolution phase interpolation is required. The accuracy of the
interpolation strongly depends on the relation between the
delay and slew rate of two input signals. Therefore, it is
difficult to use in wide frequency range.
This paper reports the phase interpolator operating at ultra­
low voltage. To realize phase resolution scalability, we
proposed pseudo-pipelined architecture. Each pipeline stage
consists of I-bit dual input inverter. The simple architecture
makes it possible to operate less than O.5V. The simulation
results of the phase interpolator designed in 65nm-CMOS
technology is described.
II. PROPOSED ARCHITECTURE
A. Phase Resolution Scalable Interpolator
The conventional multi-bit interpolator [ 1] and proposed
pseudo-pipelined interpolator are shown in Fig.2(a) and
Fig.2(b), respectively. The boxes in each interpolator indicate
I-bit interpolators. The I-bit cell that has two input and three
outputs are connected in series. At the output of the 1bit cell,
the upper side port has the same phase with the upper side
input port signal and the lower side port has the same phase
with the lower side input port signal. The middle port of the

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 ,poutO ..................

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IP;no ....-....
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(a) Conventional multi-bit interpolator (Case of 3bit resolution.) (b) Proposed multi-bit interpolator (Case of 3bit resolution)

Fig.2 Comparison between the conventional interpolator (a), and proposed pipelined interpolator(b) .

TABLE I
Comparison of design

Conventional(a) Proposed(b)

Number of cells 2N_l N+1

Number of 2: 1MUXs 2N_l N

output has the middle phase of the upper side and lower side
input port signals.
In the conventional multi-bit interpolator, I-bit cells are
connected like a tree [ 1]. This structure has problem of circuit
size. Improvement of the resolution by I-bit doubles both the
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circuit size and ower consumption. The number of required
I-bit cell is 2 - 1 to realize an N-bit phase resolution.
Therefore, it is difficult to realize an interpolator with
resolution higher than 5bit.
Proposed design has pseudo-pipelined structure, and
achieves interpolation by selecting the two adjacent phases by
multiplexers (MUXs). Number of used I-bit cells in this
design with N-bit resolution is only N+ 1, which is much fewer
than 2N- 1 in conventional phase interpolator. The proposed
design solves problem of circuit size, and brings scalability.
The resolution can be easily extended by changing number of
connected stages.
B. Slew rate control
In the I-bit interpolator cell that uses dual-input inverter,
the relation between the delay and slew rate of the two input
signals become important. As shown in Fig.3(c), if the rise
time of input signal is much shorter than the delay between
the two input signals, there is a period when the VmI is high
whereas Vin2 is low. In this duration, the outputs of two
inverters collide and interpolator output keeps mid-level. This
drastically degrades the accuracy of interpolation. To keep
the accuracy, the slew rate control becomes very important.
The rise time should 10 times longer than the delay time
between the two inputs. Since the delay time depends on the
operating frequency, the optimum slew rate also depends on
the operating frequency. Therefore, the adaptive slew rate
control becomes important to support a wide operating
frequency range.

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 multi phase
PI
oscillator

Frequency MSB LSB

Ctrl Phas e Ctrl Phas e Ctrl

Fig. 4 Control architecture

(a) Dual input inverter (b) Design of controllable inverter

Fig.6 shows the cases when the input delays are 500ps and
Vin1 Vin1 5ns. Since the I-bit interpolation cell generates middle phase
of the two inputs, the output delay normalized by the input
Vin2 Vin2 delay should be 0.5 for correct operation. From this figure, it
can be said that the rise/fall time should enough long
Vout Vout compared with the input delay for accurate interpolation. The
ratio between rise/fall time and input delay is needed to be 5
t t times longer than the input delay.
(c) Without slew control (d) With slew control Fig.7 shows relationship between control code of the phase
and output signal delay normalized by the delay between the
Fig. 3 Slew rate control
two input signals. If it is ideal phase interpolator, the results
In our interpolator, the rise time can be controlled by become linear line from 0 to 63/64. This figure indicates that
current starving technique (Fig.3(b)). The transistors M2 and the proposed PI with slew rate (rise/fall time) control has
M3 control the current flow of the inverter. The M2 and M3 nearly ideal operation at various input delay, whereas the PI
also act as a resistor divider and increase the accuracy of the without slew rate control has strong non-linearity and phase
interpolation. The isolation between the input and output of error.
each stage is also improved by M2 and M3.
The proposed PI can be applied in the multi-phase
generator in PLL or DLL. Architecture shown in Fig.4 can be
assumed. In this architecture, the delay cells in oscillator and
1-bit cell
I-bit cells in the interpolator use same current staved inverter
and they has same delay time at the same digital control word.
The control circuit in the PLL or DLL sets the control word of rise time input delay output delay
oscillator according to the operating frequency. Since the
Fig. 5 Definition of signal parameter in I-bit cell
delay of the I-bit cells in the interpolator matches with the
delay of the cells in the oscillator, same control word can be
used to control the delay in interpolators. Coarse phases are 0.8
generated by multi-phase VCO and fine phase can be --SOOps _ris e
'"
'" --SOOps _fall
generated by using the outputs of VCO and PI. By combining 0; 0.7
" -Sns _ris e
these two phase control, high resolution phase can be :::J
....
Q. -Sns _fall
generated. '"
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III. SIMULATION RESULTS :;
.s- 0.5
The proposed pipelined PI was designed in 65-nmCMOS. :::J
0
By defining the rise time, input delay, and output delay as
0.4
shown in Fig.5, circuit simulations were carried out.
0.1 10 100
Fig.6 shows relationship between rise/fall time and
ris e fall time I de lay time
accuracy of I-bit interpolation stage. In the simulation, we
input the signals that have variable delay between each signals. Fig. 6 Simulated accuracy of I-bit cell

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 --withc ontrol 1ns
� TABLE II Performance of PI
Qj
"0
-o-withc ontrol 10ns
<> -- without c ontrol 1ns Technology 65nmCMOS
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c:
e 48/64 Supply Voltage O.5V

� Power Consumption O.12J.lW/MHz

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32/64 1.25LSB @delay: IOns
Qj
INL
"0 2.07LSB @delay: Ins
� 16/64
O.4ILSB @ delay: IOns
DNL
� 0 ���:::::;::=::==:::=;:=:::l O.9ILSB @ delay: Ins

o 10 20 30 40 50 60
Since the input delay of the subsequent stage becomes half
MUX c ontrol c ode
of the previous stage, the slew rate of that stage should be
Fig. 7 Simulated normalized output delay vs. input code controlled as the rise/fall time becomes shorter than that of the
previous stage. Therefore, the backend stage should biased by
larger current than the front-end stage. If the input signal
1.2 ...----, delay becomes smaller, the bias current of the backend stage
--delay: 1ns
becomes inadequate for short rise/fall time. This slightly
0.8
-0- delay: 10ns degrades the phase linearity of the input delay of lnsec
0.4 compared with that of IOnsec.
III
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The performance of the designed PI is summarised in
d- 0 Table.2.
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IV. CONCLUSIONS
.Q.8
Resolution scalable phase interpolator with dual-input
-1.2 -I---..----.-.-....J inverter and pseudo-pipelined architecture was proposed. The
o 10 20 30 40 50 60 slew rates of each pipelined stage are controlled to support
MUX control code wide input frequency range. The PI designed in 65-nm
CMOS technology can operate at O.5V and circuit simulation
Fig. 8 Simulated DNL vs. input code
achieved the 6-bit phase resolution. The DNL and INL are
OA ILSB and 1.25LSB respectively at IOns input delay. The
3 �-------,
DNL and INL are O.9ILSB and 2.07LSB respectively at Ins
--delay: 1ns input delay.
2 -o-delay: 10ns

iii'
CI) ACKNOWLEDGMENT
d- O
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This work was carried out as a part of the Extremely Low
�
-1 Power (ELP) project supported by METI and NEDO.

-2

REFERENCES
-3
[1] Bruno W. Garlepp, Kevin S. Donnelly et al., "A Portable Digital DLL
0 10 20 30 40 50 60
for High-Speed CMOS Interface Circuit", 1999 JSSC, pp632-644
MUX control code [2] Pavan Lumar Hanumolu, Vododymyr Kratyuk, Gu-Yeon Wei, Un-Ku
Moon, "A Sub-Picosecond Resolution 0.5-1.5 GHz Digital-to-Phase
Fig. 9 Simulated INL vs. input code Converter", 2008 JSSC, pp414-424
[3] Mohamed Benyahia et ai, "A digitally controlled 5GHz Analog Phase
Interpolator with 10GHz LC PLL", 2007 DTIS, pp130-135
Fig.8 and Fig.9 are simulated DNL and INL respectively. [4] Rainer Kreienkamp, Ulrich Langmarm et ai, "A 10-Gb/s CMOS Clock
At the input delay of Insec, the DNL is OA ILSB and INL is and Data Recovery Circuit With an Analog Phase Interpolator", 2005
1.25LSB. JSSC, pp736-743

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