School of Arts and Sciences

Department of Mathematics and Computer Science

Course name: Computer Organization Lab Course Code: CSC322 Time Allowed: 120 min.
Academic year: 2022-2023 (Fall)
Exam type: Midterm ☐ Final ☒
Exam date and time: Tuesday, December 12, 2022, 14:45 – 16:45
Exam room: AKSOB 904
Authorized Documents: none
Authorized Calculator (non-programmable): ☒ yes ☐ no
Course instructor: Dr. Karim Ishak
Number of pages: 8 pages

Student Name:_______________________________________ Student ID:_______________

Exercise 1 (6 pts):
The objective of this exercise is to design a full-subtractor in 2 ways: first using a half-
subtractor, then using a full adder.
The calculation method and truth table of a half-subtractor (1 bit subtractor) are shown below.

a) Give the equation of the outputs using minimal number of gates.

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 b) Draw the circuits of a half-subtractor and write the Verilog module corresponding to this
circuit.

A full-subtractor can be represented in 3 ways: from the truth table, using a half-subtractor, or
using a full-adder.
c) Give the equation of the outputs using minimal number of gates, based on the following
truth table.

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A full-subtractor using 2 half-subtractors is shown on the figure below.

d) Give the Verilog code of a full-subtractor module using the half-subtractor module
coded above.

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To subtract 2 4-bit operands, we can do an addition of the first operand with the 2’s
complement of the second operand. So, a full-adder can be used for this purpose. The figure
below shows a full-adder (FA) for 2 4-bit operands.

We remind you that, for an addition, the C0 input is set to 0. In order to use this full-adder to do
a subtraction of 2 4-bit operands, the operand A is added to the 1’s complement of the operand
B with the input C0 set to 1.
e) It is considered that the FA Verilog module is defined as FA (A,B,C0,S,C4) where the
inputs are A[3:0], B[3:0], and C0, and the outputs are S[3:0], and C4. Using this FA
module, write the Verilog module corresponding to a full-subtractor to subtract 2 4-bit
operands.

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Exercise 2 (6 pts):
You are asked to make a logic circuit with 3 inputs (a0, a1, a2) and 2 outputs (f0, f1), which gives
as output the number of 1 applied to the inputs. The outputs f0, f1 correspond to the bits
values representing the number of 1 in the inputs. For example, if we have 2 inputs set to 1 and
one input set to 0, in this case the number of 1 is 2, so in binary 10 (1 for f0 and 0 for f1, and so
on).
a) Give the truth table of this circuit.

b) Determine the logical functions f0 and f1 of this circuit.

c) Simplify the functions f0 and f1.

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 d) Write the Verilog code corresponding to the simplified functions.

Exercise 3 (4 pts):

Consider the following Verilog module:

module test(in,slt,out);
input in, [1:0]slt;
output reg [3:0] out;
always @ (in or slt)
begin
case (slt)
2'b00: out[0]=in;
2'b01: out[1]=in;
2'b10: out[2]=in;
2'b11: out[3]=in;
endcase
end
endmodule
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a) Give the value of the output (value of each bit) for the following input values:
i) in=0, slt[1:0]=10

ii)in=0, slt[1:0]=01

iii) in=1, slt[1:0]=10

b) If we modify the always block as follows:

always @ (in and slt)
begin
case (slt)
2'b00: out[0]=in;
2'b01: out[1]=in;
2'b10: out[2]=in;
2'b11: out[3]=in;
endcase
end
What will be the values of the output for the following input values?
i) in=0, slt[1:0]=10

ii) in=0, slt[1:0]=01

iii) in=1, slt[1:0]=10

c) The code given in part a) corresponds to a de-multiplexer where one output is selected
by the selector to get the value of the input. If we add one more bit for the slt input, in a
way that the chosen output corresponds to the modulus of the slt input value, ex.: if the
slt input value is 101(i.e. 5 in decimal), the selected output will be out[3] because
3%8=3.
Modify the Verilog code in a) in order to take into account this modification.

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 Exercise 4 (4 pts):
Prove the equivalence of the following equations basing on Boolean algebra theorems.

a)

b) xy + yz + xyz + x = x + yz

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