EMISY second test exemplary questions solved

3. Describe the difference between microprocessor, microcontroller and DSP

Microprocessor is general purpose, programmable IC, which has only CPU inside it, without
any RAM, ROM or I/O ports.

Microcontroller is an IC with CPU, fixed amount of RAM, ROM and other peripherals all
embedded on a single chip. It usually designed for a specific task.

DSP is a specialized microprocessor, suited for high performance, repetitive, numerically

intensive tasks. DSPs often have two, four or more multipliers that allow more multiply-
accumulate operations per instruction cycle.

4. List the main features of Z80 memory & I/O architecture and resulting control bus
signals.

Separated I/O and memory address space. Common data and program memory address
space. Intel control signals convention.
5. List the main features of 8080 memory & I/O architecture and resulting control bus
signals.

Common I/O and data memory address space. Separated program memory address space.
Intel control signals convention.

6. List the main features of 8085 memory & I/O architecture and resulting control bus
signals.

Separated I/O and memory address space. Common data and program memory address
space. Intel control signals convention.

7. List the main features of 8051 memory & I/O architecture and resulting control bus
signals.

Separated I/O and memory address space. Common data and program memory address
space. Intel control signals convention.

8. List the main features of 6800 memory & I/O architecture and resulting control bus
signals.

Common address space for all devices. Motorola control signals convention.

9. Describe the main differences between Intel and Motorola control signal conventions
and draw exemplary timing diagrams
Intel convention – separate, negative strobes for write (~W) and read (~R).

Motorola convention – control signal for operation mode – read/not write (R/~W) and
positive enable (E) strobe.

10. Draw an exemplary timing diagram and describe read and write operations with
Motorola control signals

11. Draw an exemplary timing diagram and describe read and write operations with Intel
control signals

12. Describe what a memory map is and

how/why it is helpful

It’s an abstract idea that shows how different devices (RAM, ROM, I/Os) are placed in
available address space of microprocessor. It is especially helpful in the designing stage,
when choosing the best address decoding scheme.

13. Describe full and partial address decoding and their advantages & drawbacks

Full address decoding: All the address lines are used to specify the address location. Each
physical memory location is identified by unique address.
Partial address decoding: Only a subset of address lines are needed to point to physical
location. Each physical memory location is identified by several possible addresses (using all
combinations of address lines that were not used).

14. Design address decoding of a given xxx circuit

15. Describe most common methods of address decoding implementation

Gates
Direct control by address lines
Decoders/demultiplexers
Programmable chip select
Programmable logic circuits (GALs)

16. Describe combined address decoding and control

Combined address decoding and control is used when the controlled device has no chip
select inputs, eg. Output registers, input buffers, etc.

17. What is the reason for bus multiplexing and how can it be implemented?

Multiplexing of data and address busses is implemented to reduce the pin count on
microprocessor chip. The address information is emitted at the beginning of a memory cycle
and external logic is expected to latch that address. Then the bus becomes the data bus and
required data is transferred to or from memory using the latched address.

18. Describe the difference between latch and D-type edge-triggered flip-flop

Latch is level triggered. It will follow the input as long as the enable is true. Once the enable
goes false, output will stay at the last known value.
D-type flip-flop is edge triggered. The output will not change until the edge will not appear
on enable. At that point, input will be written on the output, which will stay in that state
until next edge.

19. Which of the two (latch or D-type edge-triggered flip-flop) is used in bus multiplexing
and why?

Latch

20. What are the reasons for signal buffering?

Bus loading resulting from digital logic inputs connected to the signal lines. Capacitive bus
loading. Interoperation of circuits powered from different supply voltages. Separation of the
signal lines from external circuits.
21. What are the most important differences between bipolar and CMOS digital logic
circuits?

Power dissipation on CMOS is much lower than for bipolar circuits. CMOS memory chips
have higher noise immunity than bipolar memory chips. Bipolar circuit are generally used
where highest logic speed is necessary.

22. What are the main differences between xxC and xxCT CMOS digital logic circuits?

xxC works with CMOS-level inputs, while xxCT works with TTL-level inputs and outputs. xxC
allows relatively wide supply voltage range (2-6V) and prefers signals close to 0V for low and
close to Vdd for high. xxCT works only with supply voltage of 5V +/- 10%, and valid inputs are
0V for low and ~2.4 – 5 V for high.

23. Describe how would you check if driving capabilities of a particular digital output are
sufficient

One have to check if output minimum and maximum output current provided by this digital
output is greater or equal than the sum of minimum and maximum input currents of all
devices connected to this output.

24. What problems may occur when using circuits from different logic families (and what
can be done about it)?

Problem would be that TTL and CMOS families operate on different voltage levels. There are
few solutions to this problem eg.
 TTL-to-CMOS interface can use a pull-up resistor
 CMOS-to-TTL interface can use CMOS buffer IC
 TTL-to-CMOS interface can use a transistor
 TTL-to-CMOS interface can use a TTL open-collector buffer IC

25. What problems may occur when using circuits powered from different voltages (and
what can be done about it)?

26. Design a uP system of given program/data memory capacity with given components
(uP, ROM, RAM, etc.)
--------

27. Describe algorithm of checking time dependencies

 Determine connections between circuits being checked

 Get appropriate time charts from the datasheets
 Find corresponding time markers on the time charts
  For each required time dependency define formulas describing the same timing on
both time charts
 From each pair of such formulas calculate value of parameter being analyzed
 From all calculated values select one being considered worst case

28. Why is it important to check time dependencies in circuit under design? Describe how
would you do it.

Time dependency of memory has explicit influence on maximum clock frequency of the
system.

29. Calculate max. system clock frequency in a system based on a given uP and memory
------

30. Select appropriate memory speed grade for a system based on a given uP and memory
and defined system clock frequency
------

31. How can latch influence the timing characteristics of the multiplexed bus and what can
you do about it?

32. List and briefly describe the most common addressing modes

 Immediate – value to be stored in memory is included in the instruction (immediately

follows the operation code in memory)
 Register – value to be stored in memory is held in one of 8 registers R0-R7
 Direct – value to be stored in memory is directly retrieved from another location in
memory.
 Indirect – value to be stored in memory is retrieved from a memory location that is
stored in a register.
 Indirect with offset – value to be stored in memory is retrieved from a memory
location that is a sum of a value stored in register and in pointer register.
 Relative -

33. What if the function of EA pin in 8051 microcontroller?

By applying logic zero to this pin, P2 and P3 are used for data and address transmission with
no regard to whether there is internal memory or not. It means that even there is a program
written to the microcontroller, it will not be executed. Instead, the program written to
external ROM will be executed. By applying logic one to the EA pin, the microcontroller will
use both memories, first internal then external (if exists).

34. What is the concept of SFR registers in 8051?

Special function registers (SFRs) in 8051 take up 128 bytes of internal RAM memory, but only
a portion of this space is used. To distinguish between upper half of internal RAM and SFR
registers different modes of addressing are used to access both of them
All registers that control or are directly used by CPU are placed in SFR memory space, eg.
ACC, B, PSW, SP etc. On the other hand, SFRs are kind of interface between CPU and
peripheral devices inside microcontroller.

35. Describe internal structure of the P1 I/O port lines in 8051 microcontroller

36. What are read-modify-write instructions (give examples and describe how they work)?

Reading of the state of a port can be done in two ways. Either by reading the state of input
lines, or reading the state of port register. Instructions that perform the latter one are called
read-modify-write instructions.
ANL (logical multiplication)
ORL (logical sum)
XRL (logical sum modulo 2)
JBC (jump if bit is 1 and zeroing of bit)
CPL (bit complement)
INC (byte increment)
DEC (byte decrement)

37. Explain the main difference between read-modify-write and read/write instructions on
an example?

Let’s assume that P1.0 line is used as an input and P1.1 line is controlling base of bipolar
transistor. Because P1.0 has to work as an input, 0 bit in P1 register has to be high. To
control transistor 1 bit in P1 register has to be high - if transistor is to be active – and low –
for transistor to be cut-off. Furthermore, let’s assume that external circuit is pulling P1.0
input line low, and transistor is active, then performing instruction:
ANL P1, #0FFH
will make no change in the state of P1 port. If we would perform:
MOV A, P1
ANL A, #0FFH
MOV P1, A
Then the state of P1 port would change, because in the second case MOV instruction is
performing read operation from P1 port lines not register.

38. What are the output current capabilities of a digital I/O in 8051 and AVR
microcontrollers?
39. What are the most common system clock solutions (and their advantages / drawbacks)?

 External oscillator
 Onboard oscillator with external crystal or ceramic resonator
 Onboard PLL-based oscillator with external crystal resonator
  Onboard oscillator with external LC or RC circuit
 Onboard RC oscillator
 Onboard high-precision oscillator

40. Describe purpose and results of reset in a uP system

Because after turning microprocessor on, the state of its registers and internal RAM memory
is undefined, resetting is crucial for uP to operate properly. Resetting of uP means that most
of its SFRs will take values set by a manufacturer. Eg. Program counter is set to 0000H, stack
pointer to 07h, and port registers to 0FFH.

41. Describe typical system reset implementation circuits

Depending on whether system has to be reset with high or low signal, we connect capacitor
( capacitance of few micro Farads) between RESET pin and either Vcc or Ground.

42. What is the main concept of interrupts?

Servicing an interrupt causes uP to stop executing software task and to perform a call to a
dedicated interrupt service routine. When uP finishes the routine it returns to the point at
which the program was stopped and execution of interrupted section of firmware is
resumed.

43. What are typical applications of interrupts?

Main reason for invention of interrupts was need for hardware triggered change in program
flow in response to external events. They can be also used for simplification of the software
and diagnostic purposes (detection of division by 0, stack overflow or underflow, etc.).

44. Describe (in details) what happens when an interrupt is required

During every machine cycle the state of interrupt pointers is tested. Interpretation of this
test is performed during next cycle. If any of interrupt pointers is set, and this interrupt is
allowed to realize, the interrupt circuit will carry out hardware generated procedure long call
instruction

45. What are the main problems with level-sensitive interrupts?

Interrupt signal must be active long enough to be noticed by the interrupt system.
Interrupt signal must not be active too long or it will be recognized as multiple request.

46. Describe how the edge-triggered interrupts work (are detected by a uC/uP)?

Edge-triggered interrupts are detected by a flip-flop that is set in response to the active edge
of the interrupt signal, but it does not mean that the flip-flop is directly triggered by the
interrupt signal.
47. What is interrupt masking and is it always possible?

Masking an interrupt means making it insensitive to the active interrupt request signal.

48. What is the main purpose of introducing the interrupt priority?

Making it possible, to resolve existence at the same time of a few different interrupt sources
with different address vectors.

49. What is a fixed-address interrupt vector concept?

In this interrupt system the address vectors of the interrupts are fixed and cannot be
changed.

50. Describe interrupt system in Motorola 6800 microprocessor

Motorola 6800 is an example of uP with software defined interrupt address vectors.

It is invoked by execution of the SWI instruction.

51. Describe interrupt system in 8051 microcontroller

Interrupt system in 8051 uC has levels of priority (IP register); fixed natural priority within
level; individual enable bits and global interrupt enable bit; priority can by dynamically
changed at run-time

52. Why saving and restoring PSW when servicing interrupts is usually necessary?

Because, servicing an interrupt does not push PSW on stack or store its value in any other
way.

53. What can be done if saving PSW is not hardware supported?

It should be included in the interrupt handler routine written by designer of the system.

54. Describe the main difference between RET and RETI instructions and a result of using
RET instead of RETI

RET is used for returning from standard routine. RETI restores the interrupt system to the
state from before the interrupt (eg. Restores PSW if automatically pushed onto the stack).

55. Describe how the 8051 timers count external pulses

When T0 or T1 work as a counter its contents is incremented in response to falling edge of
input signal. Detection of the edge is performed synchronously with machine cycle, so to
detect all impulses, all states of the tested lines have to last at least for one machine cycle.

56. Describe implementation of a simple keyboard

It is implemented by introducing buttons between mC inputs and ground.

57. What is key debouncing and how can be implemented?

It is an answer to mechanical phenomenon of bouncing of the key, every time key is presses
or released it will bounce for a short time (few milisec.) during that time buttons get
connected and disconnected repeatedly. The simplest way to prevent false reading is to wait
for 30 ms. since the moment of detection and perform another detection.

58. Describe implementation of a matrix keyboard

In matrix keyboard buttons are placed on crossconnections between rows and columns. If
columns are outputs and rows work as inputs, when we write ‘0’ to a column and read states
of its rows if no button was pushed all inputs will be high. But, if one of the keys will be
pushed it will be read as ‘0’.

59. What are the most common kinds of display and their main features?

LED displays: LED diode; 7-segment; 16-segment

 Forward voltage vs current char. Similar to standard diode
 LED brightness is proportional to the average value of its forward current
 Noticeable brightness 0.5-1.0 mA If max = 20mA
LCD displays: with individual driven segments; alphanumeric; graphic
Fluorescent displays: alphanumeric; graphic

60. Describe how an LED should be driven and explain why

61. Describe What the 7-segment displays are and how they work?

This type of displays consist of 7 segments each consisting of 8 LEDs which are connected by
a common cathode or anode.

62. Describe the concept of dynamic LED display

Dynamic LED display uses the inertia of the human eye, which, if the picture is repeated with
frequency of few tens of Hertz sees it as static one. Few segments of LEDs are connected
together. At given moment of time only one segment is active and displays a character. After
a delay of eg. 1 ms this segment is deactivated and next one is powered up. If this is
repeated in a cycle with high enough frequency, displayed pattern will be seen as a static
one.

63. Describe how a simple LCD display works

LCD accepts two types of signals, one is data, and another is control. These signals are
recognized by the LCD module from status of the RS pin. Now data can be read also from the
LCD display, by pulling the R/W pin high. As soon as the E pin is pulsed, LCD display reads
data at the falling edge of the pulse and executes it, same for the case of transmission.

64. What are the main advantages and drawbacks of multiplexed LCD displays?

Advantages: low power consumption; requires less I/O pins than similar non-multiplexed
LCD
Drawbacks: no direct access to individual segments; complex driving waveforms

65. What are the main features, advantages and drawbacks of alphanumeric LCD modules?

Features: 1-4 lines, 8-40 characters each; 4-bit, 8-bit standard uP interface (Motorola mode);
7-bit ASCII compatible, optional LED backlight; on-board LCD controller + character
RAM; 8 user-defined characters
Advantages: low power consumption; reasonable price; simple software initialization
Drawbacks: small characters

66. What are the main advantages and drawbacks of serial interfaces?

Advantages: smaller number of signal lines resulting in smaller packages and connectors;
easier PCB routing resulting in lower cost

67. What are the most common internal serial interfaces?

 UART/USART
 SPI
 I2C
 1-Wire
 CAN

68. Describe concept of asynchronous transmission (implemented with UART/USART)

UART is a well established standard for low cost, low speed serial communications over a simple 2-
wire (plus ground) interface.
Asynchronous communications differs from synchronous communications in that synchronization
between transmitter and receiver are encoded into the transmitted signal, rather than using a
separate wire to transfer the transmitter clock to the receiver.

69. Describe main features of the I2C interface

  Two signal lines (SDA, SCL)
 Multiple devices can be connected to the same I2C bus
 Bidirectional transmission
 Unique addresses (7-bit or 10-bit) of the devices
 Transmission controlled by a master
 Multiple masters allowed
 Simultaneous transmission conflicts resolved immediately without loss of data
 Transmission speed automatically adjusted to the slowest connected device
 Number of the devices limited only by the total bus lines capacitance of 400 pF

70. Describe main features of the 1-Wire interface

 Designed for systems with one master devise controlling many slaves
 Many peripheral devices using this interface
 Communication is precisely controlled by uC
 Easy software implementation

1-Wire is a device communications bus system designed by Dallas Semiconductor Corp. that
provides low-speed data, signaling, and power over a single signal. 1-Wire is similar in concept to I²C,
but with lower data rates and longer range. It is typically used to communicate with small
inexpensive devices such as digital thermometers and weather instruments.

One distinctive feature of the bus is the possibility to use only two wires: data and ground to
accomplish both communication and power transmission,.

Each 1-Wire chip has a unique ID code.

71. Describe main features of the SPI interface

 Sending data only in synchronous mode

 3 line transmission realization
 Full-duplex
 Slave or master modes
 Maximum speed of transmission equal to ¼ of uC clock frequency (but <1.5 Mb/s)
 Possibility of controlling of transmission speed (4 values)
 Bits can be send from most significant to least or inversely
 It can be used for programming program memory or EEPROM type memory

72. Compare single-ended and differential transmission

In single-ended signaling, the transmitter generates a single voltage that the receiver compares with a
fixed reference voltage, both relative to a common ground connection shared by both ends. In many
instances single-ended designs are not feasible. Another difficulty is the electromagnetic interference
that can be generated by a single-ended signaling system that attempts to operate at high speed.
Differential inputs provide a more stable reading when electromagnetic interference (EMI) or radio
frequency interference (RFI) is present, and therefore, it is recommended to use them whenever noise
is generally a problem.
Single-ended inputs are lower in cost, and provide twice the number of inputs for the same size wiring
connector, since they require only one analog HIGH (+) input per channel and one LLGND (-) shared
by all inputs.
Single-ended inputs save connector space, cost, and are easier to install.

73. Describe main features, advantages and drawbacks of the RS-232 interface

 Common computer and industrial interface

 Very low cost
 Very simple implementation
 Low speed
 Max distance limited to 15 meters
 Point-to-point connection
 Single-ended
 Non-standard voltage levels

74. Describe main features, advantages and drawbacks of the RS-485 interface

 Common industrial interface

 Very low cost
 Very simple implementation
 High speed
 Max distance of 1200 meters
 Multipoint connection possible
 Differential data transmission

75. Describe main features, advantages and drawbacks of the USB interface

 Network with master cpu in tiered star topology

 Up to 127 devices
 Data rated of 1.5 Mbps, 12 Mbps, 480 Mbps
 4 wires, max length 5m
 Differential data transmission
 Power distributed via the interface
 Auto configuration upon connection for real plug and play
 Assured bandwidth for real-time applications
 Requires substantial amount of firmware

76. Describe main features, advantages and drawbacks of the Ethernet interface

 Virtually unlimited number of hosts

 Twisted pair cable as the most common connection media
 Data rates 10, 100 Mbps, 1 Gbps over twisted pair
 Up to 100 m between the twisted pair nodes
 Differential data transmission
 Power over Ethernet possible
 Assured bandwidth for real-time applications
  Requires substantial amount of firmware

77. List basic DAC selection criteria

 Resolution
 INL and DNL, gain and offset errors
 Output signal (current or voltage)
 Bipolar or unipolar output
 Output voltage/current range
 Interal or external reference voltage
 Bandwidth of the reference signal in DAC is multiplying
 Maximum output current
 Speed
 Number of channels
 uP interface
 power consumption

78. What are typical properties of the internal DACs (inside microcontrollers)

 8-16 bits of resolution

 Speed up to Msps
 Usually resistor string technology resulting in guaranteed monotonic transfer
function
 Boundary code ranges are often excluded from the given linearity specifications
 Multiple channels (usually 1-4 DACs)

79. Describe how a voltage DAC can be implemented with a PWM

 Use a square wave of a frequency f, duty factor DF and voltage levels equal GND and
Vcc
 Pass the signal through a low pass filter, which corner frequency is much lower than f

80. What are the most common A/D conversion methods and what are their main features?

 Flash: fastest (up to few Gsps), but limited to low resolutions (6-8 bits); high power
consumption and high price; used only in most demanding applications and are to
fast to be served directly by uP
 Pipelined: most popular ADCs; sampling from a few Msps up to few hundreds Msps;
their resolution is in the range of 8-16 bits; moderate power consumption and
moderate price;
 Successive approximation (SAR): moderate speed (up to few Msps); low-to-moderate
resolution (8-18 bits); low power consumption; serial interface (SPI or I2C), resulting
in small form factor and low price; often available as multichannel converters
 Integrating (dual- or –multi-slope): low speed, up to ksps; moderate-to-high
resolution (12-28 bits); very good linearity, line rejection, low noise, low power
consumption; low to moderate price
  Sigma-delta: moderate speed (up to few Msps); high resolution (16-32 bits); line
rejection; low power consumption; low price and low noise

81. What are the main advantages of CMOS technology from the point of view of power
consumption?

Two important characteristics of CMOS technology is high noise immunity and low static
power consumption. Since transistor of the pair is always off, the series combination draws
significant power only momentarily during switching between on and off states.
Consequently, CMOS do not produce as much waste heat as other forms of logic

82. Describe the most common power saving modes

 Idle mode: is entered by setting appropriate control bit located in SFR area. When
this mode is entered the CPU is stopped, but peripherals and interrupt system still
work. Contents of the SFRs and internal memory are preserved. I/O pins are held in
the previous state, unless changed by working peripherals or forced externally. In
order to further reduce power consumption all the peripherals that are not currently
used should be switched off. Idle mode can be terminated by an interrupt or reset.
During idle mode power consumption is few times lower than during normal active
mode.
 Power down: this mode is entered by setting appropriate bit located in SFR area and
when this mode is entered the cock is stopped, as a result peripheral circuits don’t
work. Contents of the SFRs and internal memory is preserved and I/O pins are held in
the previous state unless forced externally. Power down mode can be terminated by
a hardware reset or by an external interrupt. During this mode power consumption is
reduced to the level of single microamperes and can be further lowered by reducing
Vcc.
 Slow down: is entered (QUIT) by setting (clearing) appropriate bit in SFR area, and
when this mode is entered, frequency of the clock is substantially lowered. Changing
of the clock frequency can be obtained by means of a clock divider, selection of
another clock source, or both. As a result CPU and peripherals work much slower
which may result in some side effects. Slow down can be used independently from
Idle or simultaneously with idle mode.

83. Describe the main methods of reducing power consumption in uP systems

 Use CMOS whenever possible

 Never leave CMOS inputs floating
 Use power saving modes efficiently
 Use lower frequency of operation
 Use lower supply voltage
 Select energy-efficient components
 Switch off all the peripherals which you don’t need at the moment
 Use LCD instead of LEDs
 Modern technology and higher level of integration usually result in lower power
consumption
  Remember that pull-ups, polarization resistors, etc. also draw current
 Use high efficiency DC/DC instead of linear regulators

84. Describe the main kinds of program memories

 Mask-ROM: lowest possible cost but only high volume orders. Price depends on the
order quantity. Contents of the program memory cannot be changed
 EPROM: user programmable, erasable; number of erase cycles strongly limited;
erasing by means of UV light, hence ceramic package with quartz window required.
High cost due to the package
 PROM/ OTP EPROM: User programmable, OTP = one time programmable. Plastic
package, lower cost.
 EEPROM (flash): user programmable, erasing/reprogramming possible, very high
number of erasing cycles. Similar cost to OTP. Usually ISP by means of SPI, JTAG,
UART
 ROM-less: cost like mask-ROM, but no on-board memory

85. Describe watchdog circuits

Watchdog circuits are used to prevent the microprocessor system from entering improper
state and/or if such a situation happens, to let the system get to a known (default) state.
Hence, use of a watchdog circuit increases reliability of the system. There are at least 3 kinds
of circuits that can be treated as watchdogs: 1).watchdog timers 2).watchdog oscillators
3).power supply monitoring circuits (voltage monitors)

1) A watchdog timer is a hardware timing device that triggers a system reset, or

similar operation, after a designated amount of time has elapsed. Kinds: -dedicated, internal ;
-optional, internal; -external. Watchdog timer clock sources : -system clock ; -dedicated
internal oscillator

2) Oscillator prevents the system from being left in random undetermined state if something
wrong happens to the system clock. Continuously compares system clock frequency with the
frequency of its dedicated oscillator. Puts the microcontroller in reset if the system clock
frequency is lower. Automatically switches internal microcontroller clock to the higher
frequency source

3) If the vcc is below certain warning level power supply monitoring circuit sets a flag and
also forces microcontr reset .