Chapter 5: Processor fundamentals:

Answers to coursebook questions and to

Worksheet questions
Syllabus section covered: 4.1

From the coursebook

Extension question 5.01
1 Memory capacity, hard disk capacity and processor clock speed.
Note that almost certainly the GB and TB will be based on the old-fashioned use of 1K = 1024.
2 A clock speed of 1.7 GHz implies 1 ÷ (1.7 × 109) s as the time between clock signals. This is 5.9 × 10–10 s, which
is the minimum time period that could separate successive activities.

Extension question 5.02

There is no correct answer here. It is possible that your technical staff can provide some technical specification
data.

Exam-style Questions
1 a Accumulator (1)
b i It stores the address of a memory location or an I/O component about to be used (for reading or
writing). (1)
ii An address as a binary value. (1)
iii The program counter (PC). (1)
c i It holds the instruction currently being executed. (1)
ii An instruction in a binary representation. (1)
iii Memory data register/memory buffer register (no marks given for acronyms). (1)
d 1 mark each for any of the following. (max 5)
 MDR contains a binary code that has been retrieved from memory using the data bus, may be a
datum, an address or an instruction, acts as a buffer to handle different speeds within the CPU and on
the data bus.
 MAR contains an address used to identify the memory location where data is to be stored or from
where data is to be retrieved, the address is transferred to the MAR from the PC
1 mark for each of the following. (max 6)

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 2 a  Data bus carries ‘data’ (1), which might be a data value, an instruction or an address (1), it carries it
between the processor and memory (1) in either direction (1). (max 2)
 Address bus carries an address (1) from the processor to the memory controller or an I/O component
(just ‘memory’ would also be acceptable) (1). (max 2)
 Control bus carries signals (1) between the processor and system components or devices (1) in either
direction (1) including clock signals (1). (max 2)
b i The number of individual wires that defines the number of bits carried simultaneously. (1)
ii The control bus (1) because it only carries signals which can be just one bit. (1)
iii The width of the address bus defines the number of addresses in memory that can be directly
accessed (1); a 32-bit bus can access 232 addresses, which is around 4 billion (1); a 64-bit bus can
access 264 which is approximately 1.8 × 1019 or about 20 billion (1).
3 a Definitions for MAR, PC, MDR and CIR as per coursebook with full names (8). [] means ‘contents of’ and
[[]] means ‘contents of the contents’ (2). ← indicates transfer from what is indicated on RHS to the
component identified on the LHS (1).
b 1 mark each for any of the following. (max 4)
 The first statement indicates an internal transfer between registers. However, when the very first
instruction is to be fetched there must be an address transferred into the PC (1) using the data bus (1).
 For the third statement, the address bus carries the address of the memory location (1) to the
memory controller (1), which then allows the data bus to retrieve the address content (1) and carry
this to the MDR (1).
 The other two statements involve only actions internal to the processor.
4 This is Question 5 in 9608 Paper 13 June 2015. At the time of writing the published mark scheme is available
on the Cambridge International School Support Hub (requires registration). The Examiners Report for the June
2015 series is also available there and this may contain comments specific to this question.
The following are what the author of this chapter in the Teacher Resource would suggest as reasonable
answers with alternatives suggested where appropriate. Where a suggested answer includes bullet points,
each bullet point would be worth one mark up to the maximum mark allocation for the question.
a Learners must see that the question is asking about the components of the system bus, so ‘system bus’
should not be included in the answer. Here are three possible names:
The data bus:
 is a bidirectional bus
 carries data where an individual datum could be a value, an instruction or an address.
The address bus:
 is a unidirectional bus
 carries an address from the CPU to the memory controller or to the I/O controller.
The control bus:
 is a bidirectional bus
 carries control or timing signals
 has a smaller width than either the address bus or the data bus.
b i There is an addition of 1 to the contents of the Program Counter and the result is stored in the
Program Counter. The effect can be described as the Program Counter being incremented.

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 ii The Memory Address Register contains an address. The contents of that address are copied to the
Memory Data Register.
iii The contents of the Memory Address Register are copied to the Current Instruction Register.
c The question asks only for what happens to registers. This can only be answered if it is understood that 35
is an operand, which is an address. There are then only two actions to describe:
 Address 35 is copied into the Memory Address Register.
 The contents of address 35 are loaded into the accumulator.
d i There are only two marks available, so two points will be sufficient:
 An interrupt is a signal.
 The signal is sent from a device in use or from currently running software to indicate that it needs
the attention of the processor.
ii The following statements relate to the immediate action when an interrupt is detected:
 The processor discontinues the processing that is underway.
 The contents of the registers are stored in memory so that the process can be re-started later.
 An interrupt service routine is initiated by loading the address of its first instruction into the
Program Counter.
When the interrupt has been serviced, the previously running process is loaded into the CPU so that
execution can continue.
However, checking for an interrupt is the final step in each iteration of the fetch–execute cycle. This
means that the servicing of an interrupt can itself be subject to an interrupt. Therefore, the processor
checks:
 for the presence of an interrupt following the execution of each instruction
 whether or not the interrupt flag has been set.
Cambridge International AS & A Level Computer Science 9608 paper 13 Q5 June 2015
5 This is Question 3 in 9608 Paper 11 June 2016. At the time of writing the published mark scheme is available
on the Cambridge International School Support Hub (requires registration). The Examiners Report for the June
2016 series is also available there and this may contain comments specific to this question.
The following are what the author of this chapter in the Teacher Resource would suggest as reasonable
answers with alternatives suggested where appropriate. Where a suggested answer includes bullet points,
each bullet point would be worth one mark up to the maximum mark allocation for the question.
a The question does not ask for the actions to be described in order. However, this is the best way to
approach the answer:
 The Program Counter holds the address of the next instruction to be fetched.
 This address is copied to the Memory Address Register.
 The content of the Program Counter is incremented.
 The instruction held in the address in the Memory Address Register is loaded into the Memory Data
Register.
 This is then copied to the Current Instruction Register.

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 b The statement identifiers are inserted in the order B, D, A, C. The text with the statements inserted would
read as follows:
 At the end of the cycle for the current instruction the processor checks if there is an interrupt.
 If the interrupt flag is set, the register contents are saved, the address of the Interrupt Service Routine
(ISR) is loaded to the Program Counter (PC) and when the ISR completes, the processor restores the
register contents.
 The interrupted program continues its execution.
Cambridge International AS & A Level Computer Science 9608 paper 11 Q3 June 2016

Worksheet 5.1: for testing basic understanding

1  A register is a storage unit with limited capacity of just a few bytes.
 A register is part of the processor (or microprocessor or CPU).
 A register has a very short access time.
 A register may be special purpose or general purpose.
 An assembly language or machine code language program can access an individual register.
Other possible answers could describe the function of specific registers or identify certain registers by name.
For example: the accumulator is a general-purpose register that stores data to be used by the ALU when
executing an instruction.
2

This is the diagram from the coursebook. If this question is tackled from memory, the starting point in the
thinking could be that the data bus has two-way transfers but the address bus only one-way. The MAR and
MDR each connect to the appropriate bus. Then the fact that the PC contains an address is the last clue
needed.

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 3 a Memory data register (MDR) and memory buffer register (MBR).
b The function of a buffer is to store temporary data that is being transferred. This is needed when data-
transfer rates are different in the two components that are connected to the buffer. This suggests that
MBR is more appropriate. The argument in favour of using MDR is that this distinguishes it clearly from
the memory address register (MAR).
c Both, because it connects to the data bus, which is bi-directional.
d The memory supplies the data coming into the processor. Data coming from inside the processor to the
MBR could be said to come from the ALU or from some general-purpose register such as the accumulator.
4 A False, B True, C False, D True, E True
The data bus carries whatever is stored or is to be stored in a memory location. This can be an instruction, an
address or a data item required by a program. Sensibly, the data bus width is equal to the word length or to
half the word length. The address bus width limits the size of memory that can be directly addressed: just
eight bits is inadequate.
5 They are not the same. The system bus connects the processor to the memory and to the I/O system. It
comprises the data bus, the address bus and the control bus. Its presence is essential for the operation of the
processor fetch–execute cycle.
A USB was once an optional extra but is now found in all small-scale computer systems. It is a bus that is part
of the construction of the computer system. Peripherals can be connected to the bus using a standard
hardware port (socket).
6  A fatal error in a program
 A hardware fault
 A need for I/O processing to begin
 User interaction
 A timer signal
This is the list given in section 5.08 of the coursebook. An example of a fatal error such as dividing by zero or
exceeding an array boundary could be given, and some reference to action by the OS scheduler would be
reasonable (section 20.02 in the coursebook).
7 MAR  [PC]
MDR  [[MAR]]
PC  [PC] + 1
CIR  [MDR]
or
MAR  [PC]
PC  [PC] + 1
MDR  [[MAR]]
CIR  [MDR]
The first step has to be to transfer the address held in the program counter to the memory address register.
The next two steps can happen in parallel. The last step is to load the instruction that has been read from
memory into the current instruction register.
Note the special meaning of the double brackets – the outer brackets say take the contents of the contents of
what is in the inner brackets.

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 8 E: Any program that is executing can be interrupted. Interrupts can be prioritised so that an interrupt service
routine can only be interrupted by a higher priority interrupt.

Worksheet 5.2: a more challenging question

1 a MAR ← [PC]
PC ← [PC] + 1
MDR ← [[MAR]]
CIR ← [MDR]
b i MAR ← [PC]. The address of the instruction to be executed; the transfer takes place inside the
processor.
PC ← [PC] + 1. There is no transfer, only an increment of 1 added to the address stored.
MDR ← [[MAR]]. The instruction to be executed is transferred using the data bus after the address has
been transferred to memory using the address bus.
CIR ← [MDR]. The instruction to be executed; the transfer takes place inside the processor.
ii MAR ← [PC]. During the processing of the previous instruction, the address of this next instruction was
stored in the program counter. This address now has to be transmitted to the memory address register
before the transfer on the address bus can take place.
PC ← [PC] + 1 PC ← [PC] + 1. The program counter has to be updated to contain the address of the
next instruction in the program. This will normally be stored in the next memory location so the
address is incremented by 1. However, the contents will be modified during the execution of the
instruction if this causes branching in the program.
MDR ← [[MAR]]. The instruction has to be transferred on the data bus to the memory data register.
This is the only mechanism for the content of a memory location to be transferred to the processor.
CIR ← [MDR]. The memory data register is merely a buffer. The instruction must be transferred to the
current instruction register. Only then can it be acted upon by the control unit.
iii The control unit controls the activities at each stage by sending appropriate signals along the control
bus and also receives signals from components external to the processor. So, the control unit causes
each activity as the previous one concludes.
MAR ← [PC]. This happens immediately following the execution of the previous instruction.
PC ← [PC] + 1. This happens immediately after the transfer of the original content has completed.
MDR ← [[MAR]]. This happens immediately after the transfer of the address of the instruction into the
MAR has completed. It can happen at the same time the content of the PC is being incremented.
CIR ← [MDR]. This happens after the transfer of the instruction. It is possible that two transfers take
place in overlapping time periods but the completion of the transfer into the MDR must precede the
completion of the transfer from the MDR.
c The control unit reads the instruction and decodes it before executing it.

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