INA106

INA
10 6

INA
106

SBOS152A – AUGUST 1987 – REVISED OCTOBER 2003

Precision Gain = 10
DIFFERENTIAL AMPLIFIER

FEATURES APPLICATIONS
● ACCURATE GAIN: ±0.025% max ● G = 10 DIFFERENTIAL AMPLIFIER
● HIGH COMMON-MODE REJECTION: 86dB min ● G = +10 AMPLIFIER
● NONLINEARITY: 0.001% max ● G = –10 AMPLIFIER
● EASY TO USE ● G = +11 AMPLIFIER
● PLASTIC 8-PIN DIP, SO-8 SOIC ● INSTRUMENTATION AMPLIFIER
PACKAGES

DESCRIPTION R1 R2
10kΩ 100kΩ
2 5
The INA106 is a monolithic Gain = 10 differential amplifier –In Sense
consisting of a precision op amp and on-chip metal film
7
resistors. The resistors are laser trimmed for accurate gain V+
and high common-mode rejection. Excellent TCR tracking
6
of the resistors maintains gain accuracy and common-mode Output
rejection over temperature.
4
V–
The differential amplifier is the foundation of many com- R3 R4
monly used circuits. The INA106 provides this precision 10kΩ 100kΩ
3 1
+In Reference
circuit function without using an expensive resistor network.
The INA106 is available in 8-pin plastic DIP and SO-8
surface-mount packages.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 1987-2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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SPECIFICATIONS
ELECTRICAL
At +25°C, VS = ±15V, unless otherwise specified.

INA106KP, U
PARAMETER CONDITIONS MIN TYP MAX UNITS
GAIN
Initial(1) 10 V/V
Error 0.01 0.025 %
vs Temperature –4 ppm/°C
Nonlinearity(2) 0.0002 0.001 %
OUTPUT
Related Voltage IO = +20mA, –5mA 10 12 V
Rated Current VO = 10V +20, –5 mA
Impedance 0.01 Ω
Current Limit To Common +40/–10 mA
Capacitive Load Stable Operation 1000 pF
INPUT
Impedance Differential 10 kΩ
Common-Mode 110 kΩ
Voltage Range Differential ±1 V
Common-Mode ±11 V
Common-Mode Rejection(3) TA = TMIN to TMAX 86 100 dB
OFFSET VOLTAGE RTI(4)
Initial 50 200 µV
vs Temperature 0.2 µV/°C
vs Supply ±VS = 6V to 18V 1 10 µV/V
vs Time 10 µV/mo
NOISE VOLTAGE RTI(5)
fB = 0.01Hz to 10Hz 1 µVp-p
fO = 10kHz 30 nV/√Hz
DYNAMIC RESPONSE
Small Signal –3dB 5 MHz
Full Power BW VO = 20Vp-p 30 50 kHz
Slew Rate 2 3 V/µs
Settling Time: 0.1% VO = 10V Step 5 µs
0.01% VO = 10V Step 10 µs
0.01% VCM = 10V Step, VDIFF = 0V 5 µs
POWER SUPPLY
Rated ±15 V
Voltage Range Derated Performance ±5 ±18 V
Quiescent Current VO = 0V ±1.5 ±2 mA
TEMPERATURE RANGE
Specification 0 +70 °C
Operation –40 +85 °C
Storage –65 +150 °C

NOTES: (1) Connected as difference amplifier (see Figure 1). (2) Nonlinearity is the maximum peak deviation from the best-fit straight line as a percent of full-scale peak-
to-peak output. (3) With zero source impedance (see “Maintaining CMR” section). (4) Includes effects of amplifiers’s input bias and offset currents. (5) Includes effect
of amplifier’s input current noise and thermal noise contribution of resistor network.

2
INA106
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PIN CONFIGURATION ELECTROSTATIC
Top View DIP/SOIC DISCHARGE SENSITIVITY
• (1) This integrated circuit can be damaged by ESD. Texas Instru-
Ref 1 8 NC ments recommends that all integrated circuits be handled with
10kΩ 100kΩ appropriate precautions. Failure to observe proper handling
–In 2 7 V+ and installation procedures can cause damage.
10kΩ ESD damage can range from subtle performance degrada-
+In 3 6 Output tion to complete device failure. Precision integrated circuits
100kΩ may be more susceptible to damage because very small
V– 4 5 Sense parametric changes could cause the device not to meet its
INA106 published specifications.

NOTE: (1) Pin 1 indentifier for SO-8 package.

Model number identification may be abbreviated
on SO-8 package due to limited available space. PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum located at the end of this
ABSOLUTE MAXIMUM RATINGS data sheet.

Power Supply Voltage ...................................................................... ±18V

Input Voltage Range ............................................................................ ±VS
Operating Temperature Range: P, U ................................ –40°C to +85°C
Storage Temperature Range ............................................ –40°C to +85°C
Lead Temperature (soldering, 10s): P .......................................... +300°C
Wave Soldering (3s, max) U .......................................................... +260°C
Output Short Circuit to Common .............................................. Continuous

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

INA106 3
SBOS152A www.ti.com
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±15V, unless otherwise noted.

SMALL SIGNAL RESPONSE

STEP RESPONSE (No Load)

50

Output Voltage (mV)

0

–50

2µs/div 2µs/div

SMALL SIGNAL RESPONSE TOTAL HARMONIC DISTORTION AND NOISE

(RLOAD = ∞, CLOAD = 100pF) vs FREQUENCY
1
A = 20dB, 3Vrms, 10kΩ load
50
Output Voltage (mV)

0.1
THD + N (%)

0
Inverting
Noninverting
0.01

–50
30kHz low-pass filtered
0.001
2µs/div 1k 10k 100k
Frequency (Hz)

MAXIMUM VOUT vs IOUT MAXIMUM VOUT vs IOUT

(Negative Swing) (Positive Swing)
–17.5 17.5
VS = ±18V
–15 15
VS = ±18V
–12.5 VS = ±15V 12.5
VS = ±15V
VOUT (V)

VOUT (V)

–10 VS = ±12V 10
VS = ±12V
–7.5 7.5

–5 5

–2.5 VS = ±5V 2.5

VS = ±5V
0 0
0 –2 –4 –6 –8 –10 –12 0 6 12 18 24 30 36
–IOUT (mA) IOUT (mA)

4
INA106
www.ti.com SBOS152A
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.

POWER SUPPLY REJECTION

CMR vs FREQUENCY vs FREQUENCY
110 140

100 120

PSRR (dB)
CMR (dB)

90 100
V–
80 80

70 60
V+

60 40
10 100 1k 10k 100k 1 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

APPLICATIONS INFORMATION
Figure 1 shows the basic connections required for operation Ref terminal will be summed with the output signal. The
of the INA106. Power supply bypass capacitors should be source impedance of a signal applied to the Ref terminal
connected close to the device pins as shown. should be less than 10Ω to maintain good common-mode
rejection.
V– V+
Figure 2 shows a voltage applied to pin 1 to trim the offset
1µF 1µF voltage of the INA106. The known 100Ω source impedance
of the trim circuit is compensated by the 10Ω resistor in
4 7
series with pin 3 to maintain good CMR.
INA106
R1 R2
10kΩ 100kΩ
V2 2 5
INA106

R1 R2
V2 2 5
R3
6
10kΩ
3 +
V3 VOUT = 10(V3 –V2)
–
R3 6
R4 10Ω VO
3
100kΩ V3

1 Compensates for
R4
some impedance
at pin 1. See text. +15V
1
499kΩ
FIGURE 1. Basic Power Supply and Signal Connections. VO = V2 – V3
100kΩ
Offset Adjustment Range = ±3mV

The differential input signal is connected to pins 2 and 3 as 100Ω

shown. The source impedance connected to the inputs must
be equal to assure good common-mode rejection. A 5Ω
mismatch in source impedance will degrade the common-
mode rejection of a typical device to approximately 86dB. If
the source has a known source impedance mismatch, an
additional resistor in series with one input can be used to
preserve good common-mode rejection.
The output is referred to the output reference terminal
(pin 1) which is normally grounded. A voltage applied to the
–15V
FIGURE 2. Offset Adjustment.
Referring to Figure 1, the CMR depends upon the match of
the internal R4/R3 ratio to the R1/R2 ratio. A CMR of 106dB
requires resistor matching of 0.005%. To maintain high
CMR over temperature, the resistor TCR tracking must be
better than 2ppm/°C. These accuracies are difficult and
expensive to reliably achieve with discrete components.

INA106 5
SBOS152A www.ti.com
 INA106 E1
A1
–In INA106
V1 10Ω 10kΩ 100kΩ 2 5
2 5 R2
Gain
200Ω Adjust

E0 6
6 R1
E0
R2 Output
V2 10Ω 10kΩ 100kΩ 3 1
3 1 CMR
200Ω Adjust

A2 E0 = 10(1 + 2R2 /R1) (E2 – E1)

To eliminate adjustment interactions,
first adjust gain with V2 grounded.
E2
+In
FIGURE 3. Difference Amplifier with Gain and CMR Adjust. To make a high performance high gain instrumentation amplifier, the INA106
can be combined with state-of-the-art op amps. For low source impedance
applications, OPA37s will give the best noise, offset, and temperature drift. At
source impedances above about 10kΩ, the bias current noise of the OPA37
reacting with input impedance degrades noise. For these applications, use an
INA106 OPA111 or a dual OPA2111 FET input op amp for lower noise. For an
electrometer grade IA, use the OPA128—see table below.
10kΩ 100kΩ
V2 2 5 Using the INA106 for the difference amplifier also extends the input common-
mode range of the instrumentation amplifier to ±10V. A conventional IA with
a unity-gain difference amplifier has an input common-mode range limited to
±5V for an output swing of ±10V. This is because a unity-gain difference amp
6
VO needs ±5V at the input for 10V at the output, allowing only 5V additional for
common-mode.
VO = –10V2 R1 R2 GAIN CMRR NOISE AT 1kHz
A1, A2 (Ω) (kΩ) (V/V) (dB) Ib (pA) (nV/ √Hz)
10kΩ 100kΩ
OPA37A 50.5 2.5 1000 128 40000 4
OPA111B 202 10 1000 110 1 10
3 1 OPA128LM 202 10 1000 118 0.075 38

FIGURE 6. Precision Instrumentation Amplifier.

Gain Error = 0.01% maximum
Nonlinearity = 0.001% maximum
Gain Drift = 2.ppm/°C
INA106
R1 R2
10kΩ 100kΩ
FIGURE 4. Precision G = –10 Inverting Amplifier. 2 5

R4 V0
INA106 6
V1 100kΩ
R1 R2 1
10kΩ 100kΩ V0 = V1 + 10 V3
2 5 R3
V3 10kΩ
3

R4 VO
6
VIN 100kΩ
1 VO = VIN FIGURE 7. Precision Summing Amplifier.
±100V R3
Safe Input 10kΩ INA106

3
10kΩ 100kΩ
2 5

This circuit follows an 11/1 divider with a gain of 11 for an overall gain of unity.
With an 11/1 divider, the input signal can exceed 100V without damage.
6
FIGURE 5. Voltage Follower with Input Protection. 100kΩ VO
1
VO = 11VIN
VIN 10kΩ
3 Gain Error =
0.01% maximum

FIGURE 8. Precision G = 11 Buffer.

6
INA106
www.ti.com SBOS152A
 PACKAGE OPTION ADDENDUM

www.ti.com 26-Feb-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

INA106KP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 INA106KP

INA106U ACTIVE SOIC D 8 75 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR INA

106U
INA106U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR INA
106U
INA106UE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR INA
106U

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 26-Feb-2022

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA106U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
INA106U/2K5 SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
INA106KP P PDIP 8 50 506 13.97 11230 4.32
INA106U D SOIC 8 75 506.6 8 3940 4.32
INA106UE4 D SOIC 8 75 506.6 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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