CEG3155 @all2014) Final Exam Page 2 of 20

Question 1 (20 marks)

Part A (5 marks):

Short questions. Answer true/false:

a) These two VHDL concurrent statements provide different results:

1) D <- A+C;
E <- B+D;

2) E <- B+D;
fulE< / +l"y hq ?w^ concurtq
D <- A+C;

b) Without an output register, the output of a Mealy FSM can contain glitches. True
c) Are these two rcalizations equivalent?

(],ilnr + ffi,t})+ V. 1tu

i - ... i b-
YF\

Yn* ) I fi+e

d) Assume the initial value of the counter is "1000". This counter counts through 4
different states.

lpDO
O/'o o
poto ' Fol*u
/rool
irto0
\
e) Assume the initial value of the counter is "1000". This counter counts through 4
dif[erent states.
r*rag{0}

Tr,*e

Answer Key T/F

a) Y
b) 1 /
c) T
d)
e)
rf
 CEG3155 (Fall 20L4) Final Exam Page 3 of 20

Part B (5 marks):

Explain the difference between these two VHDL statements and show their conceptual
implementations (i.e. draw the circuits):

if (a:'r?#.::r, uA<:a&,b;
u) S
fl) case ab is W
elseif (b:'1') when
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dout.- d; \ when "01" :) dout .- d;
else
dout <- e; end case
endif;

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tr:' x

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 Page 4 of 20
Exam
CEG3155 (Fall 20L4\ Final

Part C (5 marks):
the
it uses one adder' Show
tII combinational VHDL
KEWTIIS the
Rewrite :"d:.iil:i.::J"r:"?:Tat
designs'
conceptuar diagram
(i.e. draw the circuit) of both

with sel exP select

r a- a+b when "00" '
a*c when "01",
tr) \^,i+h ful*W Mfu,*
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 CEG3155 (Fall 2014) Final Exam Page 5 of 20

Part D (5 marks):

An ASM diagram is shown in the below figure. How many registers are needed in the
datapath? Show the implementation of the datapath logic for register c.

{_
l:
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Frl, lrl

c Iu"

40
*hr
CEG3155 (Fall 201,4) Final Exam Page 6 af 20

Question 2 (20 marks)

Part A (10 marks)

The following figure shows a parallel-in parallel out right shift register, Part a is the block
diagram and part b is the implementation using flip flops and multiplexers
Parallel Output
,rfrffii.H#tffil

03 Q2 Q1 Qs
O(Serial Outl

$l{$erial ln}
$h(Sflift Enable)
L{Load Enable}
Clock

{a) Blosk diagram

DsD2qD6
Parallel lntput

SI

sh
L
CLK
ibi lmplementation using flip4ops and MUXes

lnputs Next State Action

Sh (Shift) Ld (Load) Gls* Qz* Qr* Qo*
0 0 Qg Qz Qr Qo no change
0 1 Dg Dz Dr Do load
1 x SI Qs Qz Qr right shift

Show how to make the shift register reverse the order of its bits: i.e. Qs* : Qo,
Qz*: Qr, Qr*: Qz, Qo*: Qs
1. Use external connections between the Q output and D inputs, what should the
values of sh and L be for a reversal?

2. Change the internal circuitry to allow bit reversal, so that the D inputs may be
used for other purposes. Replace Sh and L with A and B and the register operate
accorclng the rollowm
dins to tne followine tabl A'
\,2 .

Inputs Next states Action

AB Qr* Qr* Q,* Qo*
00 Q: Qz Qr Qo No

01 SI Q, Qz Qr Right shift

10 Dl Dz Dr Do Load

11 Qo Qr Qz Q: Reverse bits
 tr

CEG3155 (Fall 2A1,4) Final Exam Page 7 of 20

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d.e t6nrl r-J'd-ia Ib

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CEG3155 (Fall 2014) Final Exam Page 8 of 20

Question 2 Part B (10 marks)

Write VHDL code for an 8-bit left-to-right shift register.

liku€5 IEEEi &*#u.*# ShS+ in q,**+ f* 6{rffi

rrfe teE. *+i-lag}n,*lld*,dI|
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i
b;n
r(7)
r(6do*nh 0) {,F tb}pnnn+r D;
*o # f,la]j
enl lrrh,\c+.#& b*\
 CEG3155 (Fall 20L4) Final Exam Page 10 of 20

Question 3 (20 marks):

Derive a 3-bit counter using D flip flops. The counting sequence is: 0, 4,2,6,1,5,3,7,0,
4,2, andso on. There is anlnput signal w, if w: 0, the counter stays in the same state
and if w: 1 the counter will go to the next state.

(i) Show the state diagram of the counter

(i1 St o* the state table of the counter for the next states and for the output
(iii;mit the simplified (use k-map) logic expression for the D inputs
(iv) Draw the circuit diagram

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i)
V*l

ii)
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 CEG3155 (Falt 2014) Final Exam Page lL of 20

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 Page 15 of 20
Exam
CEG3155 (Fatl 20L4) Final

Question 48 (20 marks)

,
J/,1
pattern il the communication
receiver'
to detectlh" "iOitiiO"
We wish to design an FSM ig"al' match' The match signal
The circuit has an input signal' *u..-in'
*;; of
i"p"t puttt* " 101010" is detected'
will be asserted 'I?* il, tto"t p"'ioJ *"" tL
",

ilft';?ffi il;"'li**X,
8],ff;;+ifitiming't#*;;;""; t;i'ffi! data-in', 0,, o,,
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i
(d) Showthe ".o,"n..

e)
 Page 16 of 20
CEG3155 (Falt 20L4) Final Exam

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 CEG3155 (Fall 2014) Final Exam Page 19 of 2A

Question 58 (20 marks)

A reduced-xor function works by applying xor operations over all bits of an input signal.
For example, let a7a6a5a4a3a2ala0 be an 8-bit signal. The reduced-xor of this signal is

y: a7 xor a6 xor a5 xor a4 xor a3 xor a2 xor al xor a0

Since this function retums 'f
if there are odd number of l's in its input, it can be used to
determine the odd parity of the input signal.

(a) Show conceptual design of reduced xor using 2 input xor gates so that the
propagation delay of the circuit (critical path) is equal to propagation delay
through 3 xor gates.
(b) Convert the reduced-xor circuit into a three-stage pipelined circuit. Show
conceptual design.
(c) Derive VHDL code for implementation in b).
(d) If the propagation delay through xor gate is 0.5 ns and Tcq:0.8 ns and Tsetup:O.2
ns compute the maximum clock frequency of the pipelined circuit. How long will
it take to compute 16 subsequent reduced xor operations on circuit implemented
in (a) and how long on the circuit implemented in (b).

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ffieP-
#*# b-$
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 Page 20 of 20
CWGiIfSS(FalI 2014) Final Exam

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