HD6303X,HD63A03X, HD63B03X CMOS MPU (Micro Processing Unit) ‘The HD6303X is a CMOS B:bit micro procesing unit (MPU) which neludes a CPU compatible with the HD6301¥1, 192 bytes of RAM, 24 parallel 10 pins, a Serial Communication Interface (SC) and va timers on chip © FEATURES Instruction Set Compatible with the HD6301V1 ‘© 192 Bytes of RAM © 24 Paralles UO Pins 16 1/0 Pine Port 2,6 B Input Pins Port 5 © Darlington Transistor Drive (Port 2,6) © 16B8it Programmable Timer Jnput Capture Regiter = Free Running Counter x1 Output Compare Register x 2 © 8.81 Reloadable Timer External Event Counter Squs 1 Seria Communication interface © Memory Ready Error Detection (Address Trap, Op Code Trap) Interrupts. 3 External, 7 Internal Up to 65x Bytes Address Space © Low Power Dissipation Mode ‘Sleep Mode Standby Mode {© Minimum Instruction Execution Time -0 Sus ie 2.0 Mis) © Wide Range of Operation Vee # 3~8V {f =0.1 ~ 05 MHz). f= 0.1~ 10MM; HO6303x Vee SV210% | #= 0.1 ~ 1.5 MHz; HDBSAOSX 40.1 ~2.0MHz; HD63B03X Wave Generation § PROGRAM DEVELOPMENT SUPPORT TOOLS ‘© Cross assembier and C compiler software for IBM PCS an ‘compatibies ‘© In circuit emulate for use with 1M PCs and compatibles r | HosaBo3Ke | HD6303XP, HD6SAOSXP. (0P-645) HD63B03xF HD63B03xCP HD6303XF,HOB3AO3XF, HD6303XCP,HDE63A03XCP. @ (P.80) (cP-68) @HITACHI 86 Hitachi America, Lid. « Hitachi Plaza © 2000 Sierra Point Phwy. « Brisbane, CA 94005-1819 » (415) 589-8300HD6303X, HD63A03X, HD63B03X (© PIN ARRANGEMENT: ‘© HD6303XP,HD63AO3XP,HD63BOSXP (# HD6303XxF,HO63A03XF,HD63BO3XF (Top View) (Top View) ¢ H06303XCP,HD63AO3XCP,HD63BO3XCP @HITACHI Hitachi America, Ltd. © Hitachi Plaza » 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 87HD6303X, HD63A03X, HD63B03X = BLOCK DIAGRAM 88 a sseba. PaxTind Pas Fourth - PaNSCLK) 6 Praf) wa Pulte) ar Pas(Tout2) o Pas Tout) Pane) os shoo Eb, 3 Ds gh—o zh &b-o ° ~f* ° Me g A B Lew Pso(TACH) bl A PoC) PMR) PoALT) “ a Poe ‘Address @us Butter @HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 + (415) 589-8300HD6303X, HD63A03X, HD63B03X ‘= ABSOLUTE MAXIMUM RATINGS m Symbol Value Unit Supply Varo Vee 03 ~ +70 v input aloe Vn =O.3~VeevO3 v Operating Temperature Toe o~ 470 *c Storage Temperature Tow =58~ 1150 *e NOTE) Tne product ha prvectoncroitin np eminal om iy walt wd gh ec Bute tu noo spy omrvatge ore han asim tem non npr impaoncspotection Excurs To smre nena parton, we earomend Vin. ‘Winer Yau Vee # ELECTRICAL CHARACTERISTICS ‘© DC CHARACTERISTICS (Vec = 5.0V10%, Vsg = OV, Ta = O~ 70°C, unlemotherwite noted.) item [ Symber Text Condition min | wo | max | Unit FES, STBY Vee-08 | - Input "Woh Vottoge [EXTAL Vw Veer |] Yes |v Other Input 20 | = Tapot Low” Walage | All inputs Ve 703 | - [os |v Top Letap Covent | RRC REE STE Ti as-vecow | - | - | 10 | oa Thre Sate (tfatned [ag~A rs, Da =D, RD, ; Wn, AW Pore 2For ral e 10 | ua ta utout “High” Voltage | Al! Outputs om Cutout “High” Voltage | At) Out v — =| % Ouipoi "Low Voreage | AN Outbuts Vou = = [oa tv Baringion Drive Ports 2,6 “ton | Vout=1.8V 10 | = | 100 | ma - Vn= OV, f= 1M Input Capacitance All lnputs a _ — [128 | oF Standby Current Won Operation | love =p 30 is0 [oa Sleeping = 1H =e [30 [ma tae | Steing (= 1 SMe = faa | 45 [ma Cee Sleeping (= 26H2""1 = [30] 60 _| ma aaa Operating (7 = TM = 79 [00 [ma lee [Operating = 1 SMH = [105 [ 150 mA Operating =a 700 ma AM Standby VoToae Vaan 7 mT = P-L TGygmin= Veg=10V. Vi non BBY 7A oops mina we 90108) “Conant Dissipation of te operating 0 iebig contin i praportoa! 12 the aerating requency. So he Wp. mee Cue stout Guten Our prvoneats Ms opmation sede sean he lima orm @HITACHI Hitachi America, Ltd » Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8900 89.HD6303X, HD63A03X, HD63B03X ‘¢ AC CHARACTERISTICS (Vc ~ 5.0V"10%, Vsg = OV, Te = 0~#70°C, unless otherwise noted.) BUS TIMING Tex Hos909x | _ HDSBAOSX 063805 tem Symbot | cotton — unit min | wo | max | min | wp [max | min | typ | max Gee Tine Toe + |= | 10 [osss}- | 10 [os] - | 10 | m “Enable Rise Time ter Es ee ee ee ee Enable Fail Time Te = eas [== es [= a8 Enable Pulse Width “High” Le PWen 450) = | soo} — [= [eof - [- tw Enable Pulse Width “Low” Level” [ PWee 450] — 300 a zz01| erate ‘Address, RIA Detay Time™ Tao = f= [a0 = [=e =e os ‘Data Delay Time Write | toow Ge nee ee ee ee OwaSetapTine [Reed [tose] -,, [82] —1-]m]—f - 1) =~ ts ‘Adress, RAW Hold Time” Tas eof [ps0 = = pas = Data Hoid Time oa soft =f so a a AO ne tan ° ° =o [== BO, WA Pulse wath” [Pave aso =e fo00t | =e =e [F>co| =e |e | TAB. W Day Time two Ee A RD Wi Hola Tine Tan =a) e908 |= =e | soe elo |e a “Eran Tine fon |e Fam [= |e 1009 emf en20| sie TIR Hold Time Ten wp-f-pop-)-,wl-t- [a MR Setup Time sanz epee 400) ze0| - | - [a0] —- | = [om AR Hot Time mel oe |= =e [soma |= a0 o [mm E Clock Pulse With ST MA Pena See fee ee Prosar Convorseuption [tes | fey | 200| - wo | — | -|a0] - | - | Procenor Contr Rise Time | or = [= [100 vo | — | — [ro | me Prosar Control Fall Time weer) 823 F009 P00 100 os BA Delay Time tea Fo 3 | — | — | 260 190 | = 160 | os “Orailaor Subiizaton Tine [me] Fat] 7] | - | ~o]-]-|~t— ms Reset Pulse Width - PWest | s{[-[-[3{-|[-T3f-J- le PERIPHERAL PORT TIMING Teme Joon ate Troan wosse0 |, _ . win | ye [wax | min | ty [max | min | wo | max] Brrpbeal B26 Teo 2.5.6 [tos | Fas | 200) - | — | 200] - zo] - | - | m Fawtime'* [Po28.6 [won | fies | 20) - | - | 200 - [ao] - | - | ‘Deay Time Enable leaale | Negative Tramivon to | ports2,6| two | Fins | - | - | 200] - | — | a00 200 | ne Peripheral Oata Va) l @HITACHI 90 Hitachi America, Lt.» Hitachi Ptaza + 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8900TIMER, SCI TIMING __HD6303X, HD63A03X, HD63B03X T_ ten HOSIIK HDEBAOSK HOBS005X, item symbol | cgi Unit ondiion [min [yp [max ve [mex] min [yp [max Timer VinputPunewias | iowr | Fee {20 | - [ = 20 | - | - [we FansmontarierOuwpun | ‘roo | Fa? | - | ~ | 4o0| - | - | 400 40] oe Sci Input |_Asvne. Mode | eae sg | =e] =v |e | eee ol fore Clock Cycle |” Clock Syne. iad Fig 48 [20 | — = [20] — — [20] — eye ‘SCI Transmit Data Delay 7 ~ Time (Clock Syne Mode) | "TP. Ww eke 200 | Sclferne Oars, | am | tae [a0 | — | - | am] - | - [a] - | - | ‘SCI Receive Data Hold Time Too | (Clock Syne, Mode) fon | Thiet = [1m] - = | 10 = " SCI Input Clock Pure width | trwsce oa | - [oe] oa] - 0s fos! -~ | 06 ] tec Tock Gye p= = pee] = P= ee Toe ut Clock Puke Width Figs EJs = [2m] = =e - ~ ner 19 SC pik Coa 1+ Tee alos sala lool Timer 1-2, SCI Input lock ot. | Fain text Sembee bee Bs @HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 » (415) 589-8300 a1HD6303X, HD63A03X, HD63B03X MPU Rend Tov 05-0 osv Figure 1 Bus Timing Figure 2 Memory Resdy and € Clock Timing @HITACHI 92 Hitachi America, Lid, « Hitachi Plaza + 2000 Sierra Point Pray. « Brisbane, CA 94005-1819 « (415) 589-8300HD6303X, HD63A03X, HD63B03X js - acre Incton Een ‘ony Ta Figure 3 HALT and BA Timing + 20vs4 nigh ew! when lock nput 28 inhi ev! when clock output Figure 4 SCI Clocked Synchronous Timing [MPU Ress [— MPU Wee t fe ety e ad \ ow \rosup = | OH fee Be srw Ty EN Be Bi TaD Mbae vod SRY Le TAY bata Vai ‘nous Ao Peo Per, (Ourputst Figure 5 Port Date Setup and Hold Times Pu Ress Figure 6 Port Data Delay Times. impu iei @HITACHI Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 EeHD6303X, HD63A03X, HD63B03X € Timer 1 FRC Pa. Pos Outputs {a} Timer 1 Output Timing Figure 7 Timer 2eteve Figure 8 Timer 1-2, SCI Input Clock Timing © JY $8 om | ee Soe! () Timer 2 Output Timing Timer Output Timing Vee Ai=2.240 ‘Test Point 120748 cree ¢ oF Egan (© =909F for Do~Ds, o~Ars, E ~30DF for Port 2, Port 6, A, WA, RVW, BA, CTR R122. Figure 9 Bus Timing Test Loads (TTL Load) LAL LL LLL OR ea a eu — ae Barasmeen a A a Figure 10 Interrupt Sequence @HITACHI 94 Hitachi America, Ltd, « Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300HD6303X, HD63A03X, HD63B03X LLL aren URW A Figure 11. Reset Timing ‘= FUNCTIONAL PIN DESCRIPTION © Vee. Vss Vcc and Vss provide power to the MPU with SV#107 sup. ply. In the cate of low speed operation (max = SOOKHZ), the MPU can operate with three through six volts, Two shouldbe tied to ground © xTAL, ExTAL These ‘two pins interface with an AT-cut parallel resonant cenystal Divdeby-four circuit i om chip. so if MHz crystal owtllator i used, the system clock is IMH> for example. AT Cut Paral 1 Resonant Crystal Osilator Co 7oF max Ry=600 max XTAL I Jeureu = 10pF 220 20%. (32 BM) extalp 4 ah Figuce 12 Crystal Interface EXTAL pin can be rived by the extemal clock of 45 10 $5% duty, and one fourth frequency of the external clock 's produced in the LSI. The external clock frequency should be less than four times of the maximum operable frequency. When using the external clock, XTAL pin should be open. Fig. 12 shows an example of the crystal interface. The crystal and CL1, CL2 should be mounted as close as posible to XTAL and EXTAL pins, Any line must noe cross the ine between the crystal osllator and XTAL, EXTAL. ° sey This pin makes the MPU! standby mode. In “Low” level, the ‘oscillation stops and the internat clock i stabilized to make feset condition, To retain the contents of RAM at standby mode, “0” should be written into RAM enable bit (RAME) RAME is the bit 6 of the RAM/port S control regster at $OO1. RAM is disabled by this operation and its contents i sustained Refer to “LOW POWER DISSIPATION MODE” for the standby mode © Reset (RES) ‘This pin revels the MPU fiom power OFF state and pro: vides a startup procedure. During power-on, RES pin must be held “Low level for atleast 20m. The CPU registers (accumlator, index register, stack pointer. condition code register except for interrupt mask bit), RAM and the data register of a port are not initialized during reset, 40 their contents are unknown inthis procedute To reset the MPU during operation, RES should be held Low" for at least 3 systemlock cycles. At the 3rd cycle during “Low” level, all the address buses become “High”. When RES remains “Low”, the address buses keep “High”. 1€ RES becomes “High”, the MPU stars the next operation (1) Lateh the vsiue ofthe mode program pins, MPs and MP, (2) Initialize each itennal register (Refer to Table 3). {G) Set the interrupt mask bit. For the CPU to recognize the rmaskable interrupts IRQ, , IRQs and IRQ,, this bit should be cleared in advance (4) Put the contents (= start address) of the last two addresses (SFFFE, SFFFF) into the program counter and start the program from this address. (Refer to Table 1) The MPU s usable to acepr eset Input until the clock @HITACHI Hitachi America, Ltd, © Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300 95HD6303X, HD63A03X, HD63B03X ‘becomes normal oscillation after power on (max. 20ms). During ‘this transient time, the MPU and I/O pins are undefined. Please bbe aware of this fr system designing. © Enable (€) This pin provides a TTL-compatible system clock to external circuits. Ite frequency is one fourth that ofthe crystal osilator ‘or extemal clock. This pin can drive one TTL load and 90pF capacitance. (© NonMaskable Interrupt (NM) When the falling edge of the input signal is detected at this pin, the CPU begins non-maskableinterupt sequence internally ‘As well at the IRQ mentioned below. the instruction being executed at NMI signal detection will proceed to its completion ‘The interrupt mask bit of the condition code register doesn't affect non-maskable interrupt at all. ‘When starting the acknowledge to the NMT, the contents of the program counter, index register, accumulators and condition code register will be saved onto the stack. Upon completion fof this sequence, a vector is fetched Irom SFFFC and SFFFD to transfer their contents into the program counter and branch to the non maskable interropt serve routine (ote) After reset start, the stack pointer shoul be initialized ‘on an appropreate memory area and then the falling edge shouldbe input to RT pin, © Interrupt Request (1A) FO) These are levelsensiive. pins which request an internal interrupt sequence to the CPU. At interrupt request, the CPU will complete the current instruction before its request acknowl fedgement. Uniess the intemupt mask in the condition code register i set, the CPU starts an interupt sequence; if set, the interrupt request willbe ignored. When the sequence starts, the contents of the program counter, index register, accumulators and condition code register will be saved onto the stack, then the CPU sets the interrupt mask bit and will not acknowledge the maskable request. During the last eyce, the CPU fetches vectors depicted an Table | and transfers their contents to the program counter and branches tothe service routine The CPU uses the external interrupt pins, IRQ, and IRQ. also as port pins Pip and Psy, 30 it provides an enable bit to Bit 0 and 1 of the RAM port $ control register at SOOL4. Refer to “RAM/PORT 5 CONTROL REGISTER" for the detail. When one of the internal intertupts, ICL, OCI, TOI, CML ot SIO 1s generated. the CPU produces internal interrupt signal (IRQ). IRQ, functions just the same as TRO, or TRO; except for its vector address. Fig. 13 shows the block diagram of the interrupt circuit Table T Interrupt Vector Memory Map Vector Priority |} el Interupt - Wight [_Fere_| Fre | AES + feeE FEF | TRAP | errc_| FFF | NMI FrFA | FFFB | SWI Goliware Inerapil Frfa | _FrFo | in, — FFE FFFT, ICI (Timer ¥ input Capture) Frea | FFF | OCT (Timer 1 Output Compare 7) FFF FFFS [TOI (Timer 1 Overtionl Frec | FFED ‘EMI (Timer 2 Counter Match) — freA] Free | TAG; tonex [FFG [FFF SiO_{RORFSORFE*TORET = @HITACHI 96 Hitachi America, Ltd, © Hitachi Plaza * 2000 Siera Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300HD6303X, HD63A03X, HD63B03X Fa aye 11 ee Figure 13. Interrupt Civeut Block Diagram © Mode Program (MP... MP, Tov apetate MPU. MP, put should e connected to “igh level and MP, shuld Be gommnscted te Lose™ Level (refer 10 he. 5) © Readineite (RW) ‘Th signal, usually be in cead state ("High"), shows whether the CPU is in read High) or write C°Low") state to the peripiecal of memory devices, This can drive one TTL load znd MOpP capacitance © R6.WR ‘These goals show active Yow ousputs when the CPU ss reading/weiting. 10 the peripherals or memories, This enables the CPU easy to access the peripheral LSI with RD and WR Input pins. ‘These pins can deve one TTL Toad and 30pF capac © Load Instruction Register (LIR) ‘The signal shows the instruction pecade being on dats bus (active how). Ths pin can drwe one TTL load and 30pf capucitance © Memory Ready (MR: Pos) Thm i the input control signal which stretches the system clock’ “High” penod 10 access lowspeed memories. Daring, this signal ts in “High”, the system clock operates in normal Sequence But this signal 01 “Low”, the “High” period ofthe yet clock will be ststched depending on sts “Low” level dovaton an integra multiples of the eycte tine, This allows the CPC tcintertave with low-speed memones see Fig. 2), Up 60 ‘9 yscan be stretched During iniewal address space aeeess or sonvabxl menin'y avcess. MR 1s prolubuted internally to prevent decrease of oper ation speed. Even in the halt state, MR can abso stretch “High” period of system clock 10 allow peripheral devices to access Towspeed memories. As this signals used also a Pep. an enable bit is provided at bit 2 of the RAM/port S control register at 30014" Refer to “RAMIPORT 5 CONTROL REGISTER” for smote details © Hae HALT: Pa) ‘This isan input control signal to stop instruction execution and to celeae buses. When this signal switches to "Low", the CPU stops to enter into the halt state after having executed the present instruction, When entering into the halt state, it mmskes BA (Px) “High” and also an address bus, data bus, RD, WR. R/W high impedance. When an interrupt is generated in the halt state, the CPU uses the interrupt handler after the hal is cancelled (Bote) 1 Please don’t ewitch the HALT signal to “Low” when the CPU executes the WAI instruction and isin the interupt wait state {0 avoid the tcouble of the CPU'S ‘operation after the halts cancelled When power is supplied with the condition that HALT fs slow”, MCU cannot sometimes release the teset_condition. even if RESET becomes “High HALT should he low before RESET rises up. (© Bur Available (BAD This an output conte! signal which is normally “Low’ but “Higi™ when the CPU aovepts HALT and celeasesthe buss. ‘The HD6H00 and HDG#O? mike BA “High” and release the buses at WAN execution, while dhe HD6303X doesn't make BA “High” under the sme condition, But if the FALT becomes @HITACHI Hitachi America, Ltd, « Hitachi Plaza © 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 + (415) 589-8900 97HD6303X, HD63A03X, HD63B03X “Low” when the CPU is in the interrupt wait state after having executed the WAI, the CPU makes BA "High" and releases the buses. And when the HALT becomes “High”, the CPU returns to the interrupt wait state = port ‘The HD6303X provides three 1/0 ports. Table 2 gwves the address of ports and the data ditection register and Fig, 14 the block diagrams of each pox. resi (DDR) of port 2 controls the 1/0 state, It provides two bits; Pont Writ Signal [Port ouput Enable ai bit 0 decides the 1/0 direction of Pag and bit 1 the HO direc: tion of Psy £0 Px 0” for input, "I" for output) Port 2 is also used as an 1/0 pin for the timers and the SCI. When used as an 1/0 pin for the timers and the SCI, port, 2 except Pap automaticaly becomes an input or an output depending on theit functions regardless of the data ditection registers value Port 2 Data Direction Register TLE Bye} xo: [A reset clears the DDR of port 2 and configures port 2 as an ‘input port. This port can drive one TTL and 30pF capaci tance. In addition, it can produce Ima current when Vout = 1LSV to drive directly the base of Darlington transistors Port Wei Sign ouput Tier. 2, Be Ouipar Testa eee Sel inpi Port 2 Port Raw Sina pat; at Ports au erp—fo © ren! Port 6, Port 2 (Bit 0) Figure 14 Port Block Diagram ots ‘An bit port for input only. The lower four bits ate alto usable a8 input pins for interrupt, MR and HALT. © Pons ‘An 8:it 1/0 port. This port provides an 8.bit DDR corre- sponding to each bit and can specify input or output by the bit (°0" for input, “1 for output). This port can drive one TTL load and 30pF capacitance. A reset clears the DDR of port 6. In addition, it can produce ImA current when Vout = 1 SV to drive directly the base of Darlington transistors These pins are data bus and can drive one TTL load and 90pF capacitance respectively. © Asma ‘These pins ate addzess bus and can drive one TTL load and 90pF capacitance respectively = RAMIPORT § CONTROL REGISTER ‘The control register located at $0014 controls on-chip RAM and port 5 RAW/Port 5 Control Regist ros 4 3p Eeeepow] — [= [oerome |] fore TAG; Enable Bit (IRQ, £, 1RO,E) and Pay as interrupt pins, waite these bits. When 0", the CPU doesn't accept an external imerrupt or a sleep cancelation by the extemal interupt These bits become “O” during reset. Bit 2 Memory Ready Enable Bit (MRE) ‘When using Py» as an input for Memory Ready signal, write 1" im this bit. When "0". the memory ready function is pro @HITACHI 98 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94006-1819 « (415) 589-8300hibited and Py can be used as 1/0 port. This bit becomes 1" during reset. Bit 3 Hatt Enable bit (MLTED ‘When using Pay #8 a input for Hat signs, write “1 se this bit, When "0", the halt function is prohibited and Py can be ‘sed as 1/0 port. This bit becomes “I” during reset (Note) When using Pe; and Pa as the input ports in mode t and 2, MRE and HLTE bit should be cleared just after the reset ‘Notice that memory ready and halt function is enable til MRE and HLTE bit is cleared. Bit 4, Bit S Not Used. Bit 6 RAM Enable (RAME) ‘Onchip RAM can be dlsabled by this control bit, By re setting the MPU, “I" is set to this bit, and on-chip RAM is ‘enabled. This bit can be wrtten "1" or “0 by software. When RAM is in disable condition (* logic 0"), on-chip RAM 1s invalid and the CPU can tead data from external memory ‘This bit should be "0" before getting into the standby mode to protect on-chip RAM daa, Bit 7 Standby Power Bit (STBY PWR) When Voe i not provided in standby mode, this bit is cleared. This i a flag for both readjwrte by software. If this bit {a et before standby mode, and remains set even after returning from standby mode, Vee volte is provided during standby made and the on-chip RAM datas valid et Figure 18 Operation Mode = MEMORY MAP ‘The MPU can address up to 65k bytes. Fig. 16 gives memory map of HD6303X. 32 intemal registers use addcesses from "00 as shown in Table 3. ‘Table 3 Internal Register [> te assans ‘Address | Registers: Rt Initialize at RESET 20 7 : : on Port 2 Data Direction Register ~ SFC of o3 Pon? RW Undefined oe = 7 os = = = 06" & = =_ or s = s 06 | Tier Canvas aw 0 38 Free Running Couser Ha aw $00 oA ‘Free Running Counter ("Low") RW ‘$00 : 08 ‘Output Compare Register 1("High") |__| FF CF ‘Output Compare Register 1 ("Low") RW SFE 00 input Capture Rests (a) ® 00 2 Taput Capture Regis Low” a 300 ¥ ina ConToU Sor Regier? aT 510 7 Tate Mode Corl Regier a 300 - WW Tx/Ax Control Status Register RW ‘$20. “7 Receive Dia Regier = 00 13 Transmit Date Register we $00 a TA Por 5 Control Ree ane Teo We “5 Pon 7 6 ov 6 Das Dicton Regie wo ‘conrmuel @HITACHI Hitachi America, Ltd, © Hitachi Plaza © 2000 Sierra Point Phuy. » Brisbane, CA 94005-1819 » (415) 589-8300 HD6303X, HD63A03X, HD63B03X 99HD6303X, HD63A03X, HD63B03X ‘Table 3 Interna! Register ‘aaress Registers RW | _tnitaize at RESET v Po RW Undetined fl 5 Ss = 9 ‘Output Compare Register 2 ("High") RW FF TA ‘Output Compare Register? "Low! RW FF 7 Timer Control/Status Regiter 3 aw $20 1c Tire Constant Register w FF 10, Timer 2 Up Counter aw ‘$00 1 Ss = ee Test Regier a = 6303 Expanded Mode 0000 7 Sone 001F 0040] ‘S006 } Sener S02, $04 506,607,518 Figure 16 HD6203X Memory Map = TIMER ‘The HD6303X provides @ bit programmable times which can simultaneously measure an input waveform and generate two independent output waveforms, The pulse widths of both Input/output waveforms vary from microseconds to seconds Timer Is confgutted as follows refer to Fig. 1. *Control/Status Register 1 (8 it) + ControlStatus Register 2(7 bit) + Free Running Counter (16 it) * Output Compare Register 1 (16 bt) + Output Compate Register 2 (16 bit) Input Capture Register (16 bit) ‘© Free-Running Counter (FRC! ($0009 : 000A) The key timer clement is 3 16-bit free-unning counter driven and incremented by system clock. The counter value it readable by software without affecting the counter. The counter is cleared by reset ‘When writing to the upper byte ($09). the CPU writes the preset value (SFFFS) into the counter (address $09, $0A) fegardless of the write data value, But when writing to the lower byte (SOA) after the upper byte writing, the CPU writes not only the lower byte data into lower 8 bit, but also the upper byte data into higher 8 bit of the FRC. ‘The counter will be as follows when the CPU writes to it by double store nstuctions (STD. STR ete.) sonwnie soa apa Li Po comme ave Wire Bara In te cae ofthe CPU te (SEAFOI tothe FRE Figure 17 Counter Weite Timing © Output Compare Register (OCR) ($0008, $000¢; OCR?) ($0019, $9014 ;0CR2) ‘The output compare register is'2 16-bit read/write register which can control an output waveform. The data of OCR is always compared with the FRC. When the data matches, output compare flag (OCF) in the timer control/status register (TCSR) is set. If an output enable bit (OE) in the TCSR? is "I", an output level bit (OLVL) in the TCSR will be output to bit | (Tout 1) and bit § (Tout 2) of port 2. To control the output level again by the next com: pare, the value of OCR and OLVL shoulé be changed, The (OCR is set to SFFFF at reset, The compare function is inhibited for a cycle just after a write to the OCR or to the upper byte (of the FRC. This is to begin the comparison after setting the 16-bit value valid nthe register and to inhibit the compare function at this cycle, because the CPU writes the upper byte to the FRC, and a the next cycle the counter i set to SFFFS. + For data wine 10 the FRC or the OCR. Zbyte tansler instruction (such a5 STX ete.) should be used © Input Capture Register (ICR) ($0000 : O00E) ‘Te input capture register fsa 16-bit read enly reqister which stores the FRCS value when exteenal input signal trnsition @ HITACHI 100 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300generates an input capture pulse. Such transition is controlled by input edge bit (IEDG) in the TCSR1 In order to input the external input signal to the edge Jdetecter, 2 bit of the DDR corresponding to bit O of port 2 should be cleared ("0"). When an input capture pulse occurs by the external input signal transition atthe next cycle of CPU's high byte read of the ICR, the input capture pulse willbe de- layed by one eyele, In order fo ensuze the input eapture oper ation, 2 CPU read of the ICR needs 2byte cansfer instruction, ‘The input pulse width should be atleast 2 system cycles, This register is cleared (50000) during reset ‘© Timer Control/Status Register 1 (TCSR1) ($0008) ‘The timer control statu register 1 san 8-it register. All bits are readable and the lower § bis ate also writable. The upper 3 bits ave read only which indicate the following timer status Bits ‘The counter value reached to $0000 as a result of countingup (TOF). ‘Armatch has occured between the FRC and the OCR 1 (ocFI) Defined transition of the timer input signal causes the counter to transfer its data tothe ICR (ICF). ‘The followings are each bit descriptions Bie Bit? HD6303X, HD63A03X, HD63B03X to the OCRI (S000B or $000C) after the TCSRI or ‘TCSR2 read ICE Input Capture Flag ‘This readonly bit is set when an input signal of port 2, bit 0 makes a transition as defined by IEDG and the FRC is transferred to the ICR. Cleared when reading the upper byte ($000D) of the ICR following the TCSRI of TSR? read. Bn? ‘© Timer Control/Stamu Regittr 2 (TCSR2) (S000F) ‘The timer contol/status register 2 isa 7-bit register. All bits ate readable and the lower 4 bits are also writable. But the Upper 3 bits are readonly which indicate the following timer Bit SA match hag occured between the FRC and the OCR? (0cF2), Bit 6 The same status fag as the OCF fag of the TCSRI bits, Bit 7 The same status flag asthe ICF flag of the TCSRI. bit 7 ‘The followings are the each bit descriptions. “Timer Control/Status Register 2 ‘OLVLI is transfered to port 2, bit 1 when a match cocurs between the counter and the OCRI. If bit 0 of the TCSR2 (OEI) is set 10 “I”, OLVLI will appear at bit 1 of port? Bit1 1EDG Input Edge “This bit determines which edge, rising oF falling, of input signal of port 2, bit © will trigger data transfer fom the counter to the ICR. For this function, the DDR corresponding to port 2, bit O should be cleared beforehand triggered on 2 falling edge High" to "Low" Iriggered on arising edge (Low to "High”) Bin2 ETO Enable Timer Overtiow Interrupt When this bit set, an internal interrupt (IRQs) by ‘Tor interrupt is enabled. When cleared, the interrupt is inhibited Bit3 EOC!) Enable Output Compare Interrupt ‘When this bit set, an iernal intertupt (IRQS) by Oct} interrupt enabled. When cleared, the interrupt ts inhibited. Bird EICI Enable Input Capture laterupt ‘When this bits set an internal antersupt (ROD) by sClintertupt enabled. When cleared the interrupt is inhibited Bits TOF Timer Overfow Flag "This read-only bit is set when the counter incre ments from SFFFF by 1. Cleared when the counters Gpper byte ($0009) 1s ready by the CPU ater the TCSR! read BA OCFI Output Compare Flag t ‘This read-only bit is set when «match occurs be tween the OCRI and the FRC. Cleared when writing the output compare register 1. When this bit is cleared, bit 1 of port 2 will bean 1/0 port. When set, it will be fan output of OLVLI automatically G€2 Output Enable 2 This bit enables the OLVL2 to appear at port 2, bit 5 when a match has occurred between the counter and the output compare register 2, When this bit is cleared, port 2, bit 5-will be an /O port. When set, it will bean Sutput of OLVL2 automatically, 842 OLVL2 Output Level 2 ‘OLVL2 is transferred 0 port 2, bit 5 when a match has occured between the counter and the OCR2. If bit $ of the TCSR2 (OE2) is set to "I", OLVL2 will appear at port 2, it S Bind EOcI2 Enable Output Compare interupt2 ‘When this bt is set, an internal intercupt (IRQs) by (OCI? interrupt is enabied. When cleared, the interupt is inhibited. Bit 4 Not Used BitS OCF2 Output Compare Fiag 2 ‘This read-only bit 1 Set when a match has occured between the counter and the OCR2. Cleared when waiting to the OCR2 (SOO19 ox SOOIA) after the TCSR2 Bint read Bité OCF1 Output Compare Flag} Bit? ICF Input Copture Fag OCF! and. ICF addtesses are partially decoded ‘The CPU read of the TCSRI/TCSR2 makes it possible to read OCFI and ICF into bit 6 and bit? Both the TCSRI and TCSR2 willbe cleared during reset (Note) If OEI or OE? is set to 1” before the first outpet compare match occurs after reset restart bit | or Bit S ‘of port 2 will produce “0” respectively @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy.» Brisbane, CA 94005-1819 + (415) 589-8300 101HD6303X, HD63A03X, HD63B03X & ta cs = pa Figure 18 Timer 1 Block Diagram = Timer 2 In addition to the timer 1, the HD6303X_provides an 8:it reloadable timer, which is capable of counting the extemal event. This timer 2 contains 2 timer output, so the MPU can fenerate three independent waveforms (refer to Fig. 19). The timer? is configured 2s follows: Control/Status Register 3(7 bit) it Up Counter Time Constant Register (8 bit) {© Timer 2 Up Counter (T2CNT) ($0010) ‘This is an it up counter which operates with the clock decided by CKSO and CKSI of the TCSR3. The CPU ean read the value of the counter without affecting the counter. In ad dition, any value can be written to the counter by software feven during count The counter is cleared when 4 match occurs between the ‘© Time Constant Reginr (TCONR) ($001C) ‘The time constant register 8 an Bit write only register, It is always compared with the counter. When a match has occurred, counter match flag (CMF) of the timer control status register 3 (TCSR3) is set and the value selected by TOSO and TOSI of the TCSR3 will appear at port 2, bit 6, When CMF is set, the counter willbe cleared simultane fusly and then start counting from $00. This enables regular interrupts and waveform outputs without any software support, The TCONR is set to "SEP" during reset. ‘¢ Timer ControW/Stanis Repstr 3 (TCSR3) ($0018) ‘The timer contolfstatus register 3 isa 7bit register. Al bite are readable and 6 bits except for CMF can be writen, ‘The followings ar each pin desenptions. Timer ControlStatus Regiser 3 counter and the TCONR or during reset. poe s 4 3p Po Ia wit operation s made by software to the counter atthe ew ecu] — [rae Ivor road cxeJoxsal soose cycle of counter clear, does not eset the counter but put the Write dats tothe counter, @HITACHI 102 Hitachi America, Ltd. » Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300HD6303X, HD63A03X, HD63B03X < HOGIOGK Internal Date € cock Bu > [——Tmert FRC fone Timer Trost i T é 1 ° Output ‘ i cme fecen] — | r2e [rossfroso|cxsifexso] s5sh3 ra, —-C} Figure 19 Timer exo aay CKSO_ Input Cock Select 0 CKS1_ Input Clock Select 1 Input clock to the counter is selected 26 shown in Table § depending on these two bits. When an external clock 1s selected, bit 7 of port 2 will be a clock input automatically, Timer 2 detects the rising edge of the ‘extemal clock and increments the counter, The exteinal flock is countable up to half the frequency of the system clack Table 4 Input Clock Seect ‘exs0 Taput Clock to the Counter o Eclock mee vf eee 1 0 | E etoek 138" —_ t 1 External clock aa 2 Block Diagram ‘Table 5 Timer 2 Output Select Tost | Toso Ter Output o ° Timer Output Inhibited ——_ ° D Togale Output” — ee a ST oot Soe duty to meerrerna aihout any tole PDO Bid T2E Timer 2 Enadi ‘When this bit 1s cleared, @ clock iput 10 the up ‘counter is prohibited and the up counter stops, When set ful" a clock stleted by CKS} and CKSO (Table 4) {snput tothe up counter (Note) Pyy_ outputs "0" when T2E bit cleared and timer 2 set in output enable condition by TOS! or TOSO. Tt alo uiputs "0" when T2E bit set "and timer 2 set in utp enable condition before the fst counter match Bt2 TOSO Taner Ousput Select 0 Bu Not Used Bit3 TOS Timer Output Stet | Bre ECM Enable Counter Match interupt ‘When a match occurs between the counter and the ‘Wen thin bts set_an intemal snterrupt (IRQS) By TCONR timer outputs shown in Tables wil appear at CoM isenabled. When cleared, the interrupt is inhibited ort 2 Bi 6 depending on these two bit When doth 7 CMF. Counter Match Flag FOs0 and TOSI ae “Obi 6 of port > wil be an 1D “This tad ony its set when a match oocuts between port. the up counter and the TCONR. Cleared by waiting "" by software we (unable to wate “I” by sof wate, Each bi of the TCSR3 is cleared during reset @HITACHI Hitachi America, Ltd. © Hitachi Ptaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94006-1819 + (415) 589-8300 103HD6303X, HD63A03X, HD63B03X ‘= SERIAL COMMUNICATION INTERFACE (Sci) The HD6303X SCI contains two operation modes: one is a9 asynchronous mode by the NRZ format and the other is clocked synchronous mode which transfers data synchronizing ‘withthe serial clock, The SCI consists of the following registers as shown in Fg, 20 Block Diagram + ControlStatus Register (TRCSR) + Rate/Mode Control Register (RMCR) + Receive Data Register (RDR) + Receive Data Shift Register (RDSR) Transmit Data Register (TDR) Transmit Data Shift Register (TDSR) The wil I/O hardware reautesanialztion by software for operation. The procedure is usualy as follows 1) Write & desirable operation mode into exch correspond: ing control bit ofthe RMCR. 2) Waite 2 desirable operation mode into each correspond ing control bit of the TRCSR When using bit 3 and 4 of port 2 for seria 1/0 only, there is ‘no problem even if TE and RE Bit are set. But when setting the baud rate and operation mode, TE and RE should be “0”, When slearing TE and RE bit and setting them again, more than 1 bit eyele of the current baud rate is necessary. It set in ess than | bit cycle, there may be a case that the intemal transmitfreceive initialization fal, © Asynchronous Mode AAn asynchronous mode contains the following two data formats | Start Bit + 8 Bit Date + 1 Stop Bit 1 Start Bit + 9 Bit Date + 1 Stop Bit In addition, if the 9th bit is set to.” bit data format, the format of TStaa bit + 8 Bit Data + 2 Stop Bit is also transferred Data transmission is enabled by setting TE bit ofthe TRCSR, then port 2, bit 4 wil become a serial output independently of the corresponding DDR. For data transmit, both the RMCR and TRCSR should be set under the desirable operating conditions. When TE bit is sel during this process, 10 bit preamble wil be sent in 8-bit data format and 11 bit in 9c data format. When the preemble is produced, the intemal synchronization will become stable and ‘the transmitter i eady 10 at ‘The conditions at this stage areas follows 1) If the TDR is empty (TDRE=1), consecutive 1s are produced to indicate the ile state when making 9 2) I the TDR contains data (TDRE=O), data is sent to the transmit data shift register and data transmit stars, During data transmit, a start bit of "0" i transmitted i ‘Then 82bit or 9bit data (Starts from bit O) anda stop bit axe transmitted. When the TDR is “empty”, hardware sets TDRE fag bit. the CPU doesn't respond tothe lag in proper timing (the TORE isin set condition til the next normal data transfer starts from the transmit data register to the transmit sift ceiser), “I” is ranserred instead of the start bic "0" and continues to be ttansfecred till data is provided to the data register. While the TDRE |s "1", 0" isnot transferred. Data receive is posible by setting RE bit, This makes port 2 bit 3 be a serial input, The operation mode of data receive is decided by the contents of the TRCSR and RMCR. The fist 0" (space) synchronizes the receive bit flow, Each bit of the following data willbe strobed in the middle. Ifa stop bit ve not *,a framing error assumed and ORFE is et When a framing error occurs, receive data i transferred to the receive data register and the CPU can read errorgenerating data, This makes it possible to detec a line break IF the stop bit is "I", data is transferred to the reovive data register and an interrupt flag RDRF is st. If RDRF is all set when receiving the stop bit of the next data, ORFE is st 10 Indicate overrun generation ‘When the CPU read the receive data register as a response to RDRE fag or ORFE Mag after having read TRCS. RDRF or ORFE is cleared. (Note) Clock Source in Asynchronous Mode MECCI : CCO= 10. the internal bit rate clock is provided at Pry regardless of the values for TE or RE. Maximum clock rate is E= 6. W both CCI and CCO ate set, an external TTL compa ble clock must be connected to Paz a sixteen times (16x) the desired bit rate, but not greater than E © Clocked Synchronous Mode In the clocked. synchronous mode, date transmit is Synchronized with the clock puke. The HD6303X SCT Provides functionally independent transmitter and teceiver which makes full duplex operation posible in the asynchronous ‘mode. But in the clocked synchronous mode an SCI clack 1/0 in is only Pz, 50. the simultaneous receive and transmit operation is not ‘availble. In this mode, TE and RE should not be in set condition (“1") simultaneously. Fig. 21 gives 3 synchronous clock and a data formal inthe clocked syneho- nous mode HITACHI 104 Hitachi America, Lid. Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94006-1819 « (415) 689-8300,HD6303X, HD63A03X, HD63B03X — T HOEIO3X Intnl = us : > | Figure 20. Serial Communication nterta Date transmit is realized by setting TE bit in the TRCSR Port 2, bit 4 becomes an output unconditionally independent of the value of the corresponding DDR. Both the RMCR and TRCSR should be set in the desirable ‘operating condition for data transmit When an external clock input is selected, data transmit i performed under the TDRE flag “0” from port 2, bit 4, sya Ehronizing with 8 clock pulses input from external to port 2 bit ‘Data is transmitted from bit O and the TDRE is set when the transmit data, shift register is “empty”, More than 9th clock pulee of external ae ignored re U ioe uU efector) eet Pee + Reston data inched 2 the 08 ee. Figure 21 ‘When data transmit i selected to the clock output, the MPU produces transmit data and synchronous clock at TORE flag lear Data receive is enabled by setting RE bit. Port 2, bit 3 will be a seal input. The operating mode of data receive is decided by the TRCSR and the RMCR. If the external clock input is selected, RE bit should be set when Put is “High, Then 8 external clock pulses and the synchronized receive dita ste input to port 2. bit 2 and bit 3 respectively. The MPU pot recene data into the feceive data shilt-repster by this clock and set the RDRF ‘Nag at the termination of & bit data receive, More than 9th clack pulse of external input ste ignored, When RDRF is cleared by reading the receive data register, the MPU starts dae output om a aling wt of a ynehronout lack to fling ee. Clocked Synchronous Mode Format receiving the next data, So RDRF should be cleared with P33 ope ‘When data receive is selected tothe clock output, 8 synchro: ous clocks are output {0 the extemal by vetting RE Bit, So re rive data should be input from extemal, synchronously with this clock. When the fist byte data is received, the RORF flag is set. After the second byte, recive operation is performed and ‘output the synchronous clock to the external by clearing the RDRE bit. ‘¢ Transmit Receive Control Status Register (TRCSA) ($0011) ‘The TRCSR ss composed of & bits which are all eadable. Bits 0 to 4 ate also writable. This fepster i initialized to $20 during reset, Each bit functions as follows @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 + (415) 589-8300 105HD6303X, HD63A03X, HD63B03X Biro Bat Biz Bia Bina Bis ‘Transmi Receive Control Status Register ronsfonre[rone] me | ae |v | re [we ]s0011 WU Wakeup: na typical multi-processor configuration, the software protocol provides the destination address at the first byte of the message. In order to make un: interested MPU ignore the remaining message, a wake-up function is available. By this, uninterested MPU can ie hibit all further receive processing tll the next message Then wake-up function is wregered by consecutive 1's with 1 frame length (10 bits for 8.1 data, I for 92it). The software protocol should provide the idle time between messages By setting this bit the MPU stops data receive tll the next message. The receive of consecutive “I” with one frame length wakes up and clears this bit and then the MPU restarts receive operation. However, the RE lag should be already set before setting this bit. In the clocked synchronous mode WU is not avaiable, so this Dit should not be st, TE. Transmit Enable ‘When this bit i et, transmit data will appear a port 2. bit alter one frame preamble i asynchronous made, ‘while in clocked “synchronous ‘mode it appeats im: mediately. This is executed regardless of the value of the corresponding DDR. When TE is cleared, the seral WO doesn’t affect port 2, bit 4 TIE. Transmit Interrupt Enable When this bit is set, an internal interupt (IRQs) ie ‘enabled when TDRE (bit 5) is set. When cleared, the interrupt i inhibited. RE Recewe Enable When set, 9 signal is input to the receiver from port 2, bit 3 regardless of the value of the DDR. When RE | cleared, the serial I/O doesnt affect port 2, bit 3 RIE Receive Interrupt Enable When this Bit 1s set, am internal interrupt. IRQ) is enabled when RDRF (bit 7) or ORFE (bit 6) is set When cleared, the interupt is inhibited TORE Transmit Data Register Empty TDRE is set when the TDR is transferred to the transmit data shift register in the asynchronous mode, while in clocked synchronous mode when the TOSR is “empty”. This bit is reset by reading the TRCSR and writing new transmit data to the transmit data repster TDRE is st to "1" during reset (Note) TDRE should be cleared in the transmittable state after Bie 106 the TE set CORFE Overrun Framing Error CORFE is set by hardware shen an overrun ota fram ing erzor is generated (during data receive only). An ‘overrun error occurs when new receive data is ready to be transfered tothe RDR during RORF sl being st A framing error occurs when 2 stop iti °O" But in locke synchronous mode, this bit not affected. Ths bit i cleared when reading the TRCSR, then the RDR, or daring reve. Bit? RORF "eceive ‘Data Register Full RDRF is act by hawae when the RDSR taser ted to the RDR.Clesred when reading the TRCSR. then the RDR. or diing eset. (Note) When afew bits ave at Between bit § to bit 7 inthe TRCSR, «read of the TRCSR sufficient for cleming those bis. Ie not neestay to ead the TRCSR eve time tocar each bt © Transmit Rate/Mode Control Register (RMCRD ‘The RMCR controls the following serial /0° ‘Baud Rate * Data Format “Clock Source * Port 2, Bit? Function In addition, if 9-it data format i st in the asynchronous ‘mode, the 9th biti putin this register, All bits ae readable and waitable except bit 7 (read only). This register is set £0 $00 during eset. ‘Transfer Rate/Mode Control Register Bo sso Birt ssi} Speed Select gins 852 ‘These bits control the baud rate used for the SCI. Table 6 lists the availble baud rates. The timer | FRC (SS2=0) and the timer 2 up counter (SS2=1) provide the intemal clock ta the SCI. When selecting the timer 2 asa baud rate source, it func: tions as a baud rate generator. The timer 2 generates the baud ‘ate listed in Table 7 depending on the value of the TCONR. (ote) When operating the SCI with intemal clock, donot perform write operation to the timer/counter which is the clock souree ofthe SCI Bk2 cco BR3 CCI} Clock Control/Format Select® Bina cee ‘These bits control the data format and the clock source (efer to Table 8) * ©C0, CCI and CC2 are cleated during reset and the MPU, goes to the clocked synchronous mode of the external sock operation. Then the MPU sets port 2, bit 2 into the clock input state. When using port 2, bit 2 as an ‘output port, the DDR of port 2 should be set to “I” and €C1 and CCO to “0” and “I” respectively. @HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300HD6303X, HD63A03X, HD63B03X Table 6 SCI Bit Times and Transfer Rates (1) Asynchronous Mode war TasTeMTe Tore Taso s52_s$1_ss0 E idee 7 oMie ata O00 a6 FEias 35a008aad | Tess 825008207 —] 15s 768008000 oo 7 cere 208,s'48008e0d | 128.8 7812 58004 | 104.248 9600800 0 1 0 e107 1 67ms 6008 | 1 O24ms 976.680ud | 833.315 12008aud ons £4096 6.87ms/150Baud || 4.096ms 744 180ud | 3333ms 300K 1 E e * | * | fi * When $52 8 I", Timer 2 provides SCI clocks. The baud rates show as follows withthe TCONR aN. ft input clock frequeney tothe faa Rae = SRT ( os ) N=0~255 {2) Cockes Synchronous Mode * aL aoune sours sour s2_ss1_ss0 € townie sie OMe sO as ra) Es16 reso | 1070s bn ays bt ° 1 0 cane 128,80 853.8 01 64,8 or ° 1 essi2 size | aan bt 256.5 bt it cates in the case of internal clock operation. In the case of external clock operation, the extemal clock is ‘opetatable up to DC ~ 1/2 system clock. ‘The bitrate is shown as Follows with the TCONR as N Bic Rate (sbi) = S01 (' input lock Frequency to >) N=0~285 and Time Constant Register Examole ‘Table 7. Baud Ra Garage Mt | zasvemre | sessemm | comme | sorsamie | Somme Saud Rat Gandy i oF 110 cr cs sae ae 150 127 191 207 | 288 5 0 |} tea 1 27 500 2 a | ost cy 103 1200 Neha) 2s er 2400 7 mf oR 5 25 ‘4800 3 5 7 2 ‘9600 1 2 3 1sz0 | ° 4 38600 ° E76 clock is input tothe timer 2 up counter and E clock otherwise @HITACHI Hitachi America, Ltd, « Hitachi Plaza # 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 * (415) 689-8300 107HD6303X, HD63A03X, HD63B03X Toole 8 SCI Format and Clock Source Control cz ect ccd | Forme | __ Moe [ioc Source [Pore on? Pon? Bina oo 0 ‘locked Syrenronous | External) | Input o 0 ‘Asynenronous Internat | Not Used ; o 1 Oo Asynchronous Iter Ou re ue ere oO 1 1 | Bbit dat Asynchronous | External Input 10 © Jarirdate | ctocked Synchronous | internal | Output 1 0 1 |9bitdats | Asynchronous tnernat | Not Use . 110 | bitdats | Asynehronout Inert — | Ouwur | ee start comut 111 Jovieaata | asynenronous externa | Ioput * Clock output regardless of the TRCSR. bit RE and TE. BAG TOS Transmit Oat Bit 8 When selecting 9-bit data format in the asynchron- ‘ous mode, this Bit i transmitted. as the 9th data. In transmitting 9bit data, write the 9th data into this bit ** Not used forthe SCI. 1m PRECAUTION 2 ‘When transmiting through clock-synchronous serial commun ‘ation interface, TE bit should not be cleared with TDRE of TRCSR. (sut)is "0" then write date tothe receive data register. ee asc dns taller ‘The TORE set and clear conditions of SC are shown as fllows When selecting 9.bi data format in the asynchronous om e = rode, this bit stores the 9th bit data. In veceiving 9-bit Set const coc data read this bit then the rosie data register. TDR = iranemit_—_| When wing 10 TR hit rogistor ater TASCA read, (asynchronous) | with TORE = 1, TORE Seneca Ton tore | 2 Tansmit shin ie cloared Inthe synchronous clocked receive operation wth clock- output, eee there ate thee cases fr clock pulse timing ater RDRF clear a3 (ackejeneeeus) shown below 3. RES <0 Please consider sbove in designing system, since transiting receiving time is not uniform ‘The lock-output of case I or case 2s determined by "I" or “0 of SC intemal operation clock of RDRF clearing cycle. In ation, inthe cas of ow voltage operation (Vee < 4.5) the clock-ourpat fof ease I may transfer to case 3. ROR read cycle (RORF clear) ro ‘fwansmit data is writen to TDR, and ten TE biti cleared with ‘TDRE = 0 0 stop transmitting, TDRE remains "0" Inthiscase, even if TEbitis set and transmit dais writen again, the TOR data is not tansmited. Please note hat TE bit must be cleared after the las dats hasbeen transmitted, (This caution is not applied to asynchronous serial commune sion interface.) A i Ls bio bint lock-output cae tu vito ese? ee vito cored a (note) Whenbitrateie 6/2, t= 8, and ty #28 E28, t= OE, 28. B16 ueBE Ge l6E, 6/512, t= 2568, = SIZE Precaution 1 Diagram @ HITACHI 108 Hitachi Americ, Ltd, « Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1619 « (416) 589-8300‘= TIMER, SCI STATUS FLAG Fable 9 shows the set and reset conditions of each status ‘agin the timer 1, timer 2 and SCI “ks for Timer { and Timer 2 status flag, ifthe set and reset condition occur simultaneously, the set Condition is prior to the eset condition, But in case of SCI contol status fag, the reset condition has priority, Especially as for OCFI and HD6303X, HD63A03X, HD63B03X (OCF? of Timer 1, the set signal is generated periodically when: ever FRC matches OCR after the st, and which can cause the ‘nclear of the flag. To cleat surely, the method is necessary to void the occurence of the set signal between TCSR Read and ‘OCR write. For example, match the OCR value to FRC first, and nent cead TCSR, and then write OCR at once. Table 9 Timer 1, Timer 2 and SCI Status Flag = —setonaion en Conaiion GE FRE = TER by ed no to Po Ted oe TESA or TOSRA ten TOR, wen Ire 2._FES-0 GF] OERTFRE + Ren ne TOSAT oc TORE tan we te Beeitoroonies wren oor =T Timer 7 = ocr OeRD-RC 1 Reaa ie TEORD he wie to he ORTH Senet wren cr 2-1 2 RES-0 [TOF FRCaSFFFF+I cycle 7. Read the TCSRI then FRCH, when TOF=1 2 ES Fine [eM [TENT =TCONR TT Wite "0" Te MF when GF a9 2_ RES BORE” | Reasne Shi Rage > ROR 1 Read ne TROSR then ROR. when RORFT 2 Riso GREE] Franpa Eivr(Avocivonos Mode Rea he TGR Then ROR, when ORFEST Stopotco 2 eso | 2. Overun Ear (nyneronos Mae) Sectee si Mepr S ROM wen scl non ToRE | 7 Annenonain Mode eid te TROSR hen wie Be TOR, FBR tiem Sit Rogie when TORE! 2, Cloke Syrcvonous Mose (Note) TORE sould erst after he TE st Svan Suit Rept ep" a. Res (ot 3, ater 3. For tcompie, “ERK mans High bye o JER ‘= LOW POWER DISSIPATION MODE ‘The HD6IOSX provides two low power dissipation modes sleep and standby '# Steep Mode The MPU goes to the sleep mode by SLP instruction execu: tion. In the seep mode, the CPU stops its operation, while the Fepislers contents are retained, In this mode, the peripherals except the CPU auch a8 timers, SCI ete, continue their func: tions The power dissipation of sleep-condition is one fifth that of operating condition. ‘The MPU returns from this mode by an inte goes to the reset state by RES and the bby STBY. When the CPU acknowledges an interupt request, it Cancels the seep mode, relums to the operation mode and branches to the interrupt routine, When the CPU masks this interupt, it cancels the sleep mode and executes the next instruction. However, for example if the timer 1 or 2 prohibits 2 timer interrupt, the CPU doesn't cancel the sleep mode be auie of no interrupt request. “This slep mode is effective to reduce the power disipation for a system with no need of the HD63O3X's consecutive operation © Standby Mode ‘The HDG303X stops all the clocks and goes to the reset state with STBY “Low”. In this mode, the power disipation i teduced conspicuously. All pins except for the power supply. the STBY and XTAL are detached from the MPU internally and go to the high impedance state In this mode the power is supplied 10 the HD6303X, so the contents of RAM is retained. The MPU retuins from this mode during reset. The followings are typical usage of this mode ‘ave the CPU information and SP contents on RAM by NMI. ‘Then disable the RAME bit of the RAM control register and set the STBY PWR bit to go to the standby mode, If the STBY PWR bit is still set at feset stat, that indicates the power is supplied to the MPU and RAM contents are retained properly So system can restore itself y returning their prestandby infor: mations 10 the SP and the CPU, Fig. 22 depicts the timing at ‘each pin with this example @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (416) 589-8300 109HD6303X, HD63A03X, HD63B03X j—! | fang Figure 22. Standby Mode Timing © TRAP FUNCTION The CPU generates an interrupt with the highest priority CRAP) when fetching an undefined instruction oF an insteve ion from non-memory space. The TRAP prevents the system burst caused by noise ora program error When fetching an undefined op code, the CPU saves CPU: fegisters as well asa normal interrupt and branches 0 the TRAP (SFFEE, SFFEE), This has the priority next co ces © Adres re ‘Whien in struction fetch i made from intenal register (S0000~S0OIF), the MPU genciates un interrupt as well a5 an ‘op code ervor. But on the system with nw memory in its ox ternal memory area, this function is not applicable if an in struction fetch ismade from the external non-memory ea This function is available only for an instruction fetch and is not applicable to the access of normal data read/write (Note) The TRAP interrupt provides 2 retry function different ly from other interrupts. This isa program flow return {0 the address where the TRAP occurs when a sequence returns to a main routine from the TRAP interrupt routine by RTI. The retry can prevent the system burst caused by nowe etc. However, if another TRAP occurs, the program repeats the TRAP interrupt forever, so the consider necessary in programming, = INSTRUCTION SET ‘The HD6303X provides object code upward compatible with the HD6801" to utilize all instruction” set of the HMCS6800. It also reduces the execution times of Key instruc tions for throughput improvement Bit manipulation instruction, change instruction of the index register and accumulator and sleep insttuction are alsa added The followings ae explained here + CPU Programming Model (refer to Fig. 23) + “Addressing Mode + Accumulator and Memory Manipulation Instruction (tefer to Table 10) + New Instuction * Index Register and Stack Manipulation Instruction (efer to Table 11) + Jump and Branch fasteustion (refer to Table 12) + Condition Code Register Manipulation (efer to Table 13) + Op Code Map (refer to Table 14) 23 depicts the HD6303X_ programming model, ‘The double accumulator D consists of aceumlator A and B, 30 when using the accumulator D, the contents of A and B ae destroyed Figure 23. CPU Programming Mode! © CPU Addressing Mode ‘Tae HD6303X provides 7 addressing modes. The addressing mode is decided by an instcuction type and code. Table 10 through 14 show addiessing mades of euch instwvetion with the execution times counted by the machine cycle When the clock frequency is 4 MH2, the machine cycle time @HITACHI 110 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94006-1819 « (415) 589-8300HD6303X, HD63A03X, HD63B03X becomes microseconds directly ‘Accumulator (ACCX) Addressing ‘Only an accumulator addressed and the accumulator A or Bis selected. This is 2 one byte instruction, Immediate Addressing ‘This adeessing locates a data in the second byte of an instruction, However, LDS snd LDX locate a data in the second lind thind byte exceptionally This addressing is a 2 or Sbyte Direct Addressing Tn this addressing mode, the second byte of an instruc tion shows the addres where a data is stored. 256 bytes ($0 tivough $255) canbe addressed directly. Execution times can be reduced by storing data inthis area go iti recommended to make it RAM for user’ data area in configurating a system ‘This is a 2byte instruction, while 3-byte with regard to AIM, (1M, EIM and TIM. Extended Addressing In this mode, the second byte shows the upper 8 bit of the bata sored addtess and the thitd byte the lower 8 bit, This indicates the absolute address of S-byte instruction in the memory. Indexed Addeessing “The second byte of an instruction and the lower 8 bit of the index regster are added in this mode. As for AIM, O1M, EIM and TIM. the third byte of a instruction and the lower & bits of the index riser are added ‘This cary is added to the upper 8 bit of the index register and the result is used for addressing the memory. The modified “Lddees is retained in the temporary address register, so the con ents of the index register doesn't change. This is a 2-byte instruction except AIM, OIM, EDM and TIM (3byte instruc: tion), Implied Addressing "An instruetion ae? specifies the addcess, That i, the instruction addresses a stack pointer, index register ec, This isa ‘one-byte instruction. Relative Addressing ‘The second byte of an instruction and the lower 8 bits of the program counter are added, The carry or borrow is added 10 the upper 8 bit. So addressing from ~126 to +129 byte of the ‘current instruction is enabled. This isa 2-byte instruction (Note) CLI, SEI Instructions and Interrupt Operation ‘When accepting the IRQ at a preset timing with CLI and. SEI instructions, more than 2 cycles ate neces: tary between the CLI and SEI instructions. For example, the following program (a) (b) don’t accept the IRQ but {e)accepts i. cu cu cu Noe SEI NoP NOP SEL SEI @ © © ‘The same thing can be said to the TAP instruction instead of the CLI and SEI instructions, @HITACHI itachi America, Ld. « Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-6300 WtHD6303X, HD63A03X, HD63B03X ‘Table 10 Accumulator, Memory Manipulation Instructions nme Oberon — : mee HH He (owe) Condition Coge Reger wil be expand in Nove of Te elt Bo erate (continued) @HITACHI 112 Hitachi America, Ld. © Hitachi Plaza © 2000 Sierra Point Phy. « Brisbane, CA 94005-1819 » (415) 589-8300HD6303X, HD63A03X, HD63B03X ‘Table 10 Accumulator, Memory Manipulation Instructions neato swnamene Taso [omRECr | ‘connec Soweto et orate | TM vel [afeofstat 1 T {note Condition Code Repster vl be expiied in Noe of Tale 13, @HITACHI Hitachi America, Ltd. « Hitachi Plaza + 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 113HD6303X, HD63A03X, HD63B03X In addition to the HDS80! instruction set, the HD6303X_ prepares the following new instructions aM aM) + 04) Executes “AND” operation to immediate data and the ‘memory contents and stores its result in the memory a +c11M) = 0) Executes “OR" operation to immediate dats and the memory contents and stores its result inthe memory aM = OH Executes “EOR” operation to immediate data and the memory contents and stores its result in the memory om EM Table 11 Index Register, Stack Manipul ™ (0) CIM) Executes “AND operation to immediate data and changes the relative la of the condition code register ‘These atea 3-byte instructions; the first byte is op code, the second immediate data andthe thitd address modifier. XGDx (acco) = (1x) Exchanges the contents of accumulator and the index register sir Goes to the sleep mode. Refer to “LOW POWER DIS. SIPATION MODE” for more details of the sleep mode. jon Instructions T ‘Aacrning Moos T ‘Conair Coe | serene Treats [SaGeT [WOE [ORES [arTED] ant Snen bITa RTE Jort=[otor]]o orf tator]=[otorl= Te CHALIESCaCa rele) | wo aHettat [fessional otrats pasa x, ort [ef sfoL ate To eticwca stents toffee Sere pste 1 |] a eerie pepe {oh feb ecoe ein Noe of Tao 13 @HITACHI 114 Hitachi America, Lid. © Hitachi Plaza © 2000 Siera Point Pkwy. « Brisbane, CA 94006-1819 (416) 589-8300HD6303X, HD63A03X, HD63B03X ‘Table 12. Jump, Branch Instructions (ove! "WAI ute RW mig, Acre us gots 19 FFF; Date Bus go to he tre ate @HITACHI Hitachi America, Lid. « Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 115HD6303X, HD63A03X, HD63B03X Table 13. Condition Code Register Manipul Jn lastructions ‘OP Operation Code iHexadecima) o Nomber of cu Cycle Mgp Content of memory location ponte toby Sack Pointe 2” Nomar ot Praga Brier geszoses ‘CONDITION coDE SYMBOLS Nogtve oa bith Zero (oye (eetow, 2 comatement (Cary/Borrow froma Bt? : Test Resi ¥ 00000000? 3 Test 8CO Character of igh oa byte eater tan 10? INot ceed previous seth © tenvi ten ' Lesa Condition Code Regn ram Stack, + Set when interupr occ. aewouty wt ¢ Non Makabie Interrupts equ to eet te wi sate * Set sezoring of Accurate A Table 14 OP Code Map ‘On each neruont of AIM, CIM. Em, THM @HITACHI 116 Hitachi America, Ltd. « Hitachi Plaza 2000 Sierra Point Pkwy, « Brisbane, CA 94005-1819 « (415) 589-8300© CPU OPERATION (© CPU Instruction Flow When operating, the CPU fetches an instruction from 2 memory and executes the requited function. This sequence Starts with RES cancel and repeats itself limitlssly if not affected by a special instruction or 2 control signal, SWI, RTL WAT and SLP instructions change this operation, while NMI TRO, , TRO; , 1RQ,, HALT and STBY control it. Fig. 24 gives the CPU mode transition and Fig. 25 the CPU system flow chart, Table 15 shows CPU operating states and port states, © Operation at Esch Instruction Cyate Table 16 shows the operation at each instruction cycle By the pipeline contro of the HD6303X, MULT, PUL, DAA, land XGDX instructions etc, prefetch the next instruction. So “tention is necessary to the counting of the instruction cycles because it i different from the usual one ~~~ op code fetch to the next instruction op code ‘Table 15 CPU Operation State and Port State Pon |_ Reset HALT Contra] Signal tT | is + RO We RAE CF OWA. iW 7, CR. HD6303X, HD63A03X, HD63B03X @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy, « Brisbane, CA 94005-1819 » (415) 889-6300 17HD6303X, HD63A03X, HD63B03X Figure 25. HD6303X System Flow Chart @HITACHI 118 Hitachi America, Ltd.» Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, GA 94006-1819 » (415) 589-8300HD6303X, HD63A03X, HD63B03X Table 16 Cycleby Cycle Operation ieee cyoee CYS ‘aogeess Bus aw! RO L* | om ‘Oma Bus oe 7 na RTT 7 [oes ors “toe 70 Gee fon i ‘ | Ritem eros on _ | Gocco arse ‘aia "Eni | (Op Code Addiess* 1 j | on enn | | (Continued @HITACHI Hitachi America, Ltd. © Hitachi Plaza # 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 » (415) 589-8300 119HD6303X, HD63A03X, HD63B03X EEE Toca] | nove tn [aw] #5 | wa] Tw a0 eae aco a | 2 | we TTT] | t | pean Aste usm fa | Te noe [tf | 1 | o | rescncom ate tome 56 1 op asta 1 ote eo an > | fom TTL Te Peete nares sen Sr om Gecmensownr2 | 8] 1 | 0 | smosces 3 ap cose Reanaret arr af ae PLT TS [a | tte nears use) i [ea oe (eye eee “00 1 8 see} a tos tor | | 3 | ixvonar rholadal Suto 2 | recone fe] i | t | eben ome nes S| op'cose a 18 |i [oo | tn peam so Toren ot a | os] 2 | treme olifels fiom | 8 [a | am iit Speman —f 8 ain PLT TE] t | ett acon asa / 4 | Stace Pomer—1 ° | 0 | 1 | win aaarens ses _ {fs | ton tle | t | 6 | maserers Op Coe sts 1 Bsa ae me tn |g | 3 | tomer 18 4 | a | opetenten mee fot | ® | 8 | re VE LL |S | mee nst usa fon & | terote 1 |e | | Newopmant one & | ceemssooner | | ot | o 7 | 2 | Op Code Address +2 | Lo on 1 | 3 oe Pr) 1a Ty | eect ners ase 2 | iron fled a] t | comes $ | cpemoacoonvs | 1 | 0 | t | 0 | noopecee aOR Op cea aaanarst fF te 8 | 3 | ixeome Jor po | 1 | a | Opera oon 2 | hone poisviols |e 1 § | Opeamsdonser | $ | 0 | ¢ | 0 | wntop cove ar 1) G5 oe tases 73 i om | 2 | eecweamene: [tot | t | om mn iif 1 | Retr Aste a fo | E | eons bre 1 | Somme 6 | (e+ Ottset fae ° + | New Operon Data 3 | eeeseaccmmes | 8 aS | 0 | nem openae (Continued) @HITACHI 120 Hitachi America, 1d. « Hitachi Plaza © 2000 Serra Point Pray. » Brisbane, CA 94005-1819 » (415) 569-6300HD6303X, HD63A03X, HD63B03X Taree Hoa a T sar Hose 5 raowte [AW] | WA] Ow ey sr t ae Ta prot oraeea |e aa eS Hay or TET eT 90 ——|—+-+ Hy Ge oo] S| 2 eee oT e+74 a s]3 cm 5 a Jela 1 al : Mom [ee $ ot : ar : o : ° Mew op cade (Continued @HITACHI Hitachi America, id. «Hitachi Plaza © 2000 Sierra Point Pkwy, « Brisbane, CA 94005-1619 « (415) 688-8300 121HD6303X, HD63A03X, HD63B03X Taran Waa RE WE® Teves] | Aawenta aw] A] WR Ow or ana eh tse Gon | cow ote Ne ns | mete | | fon hor ' | Pd | She tae i | 1x | as | Bik KOO oar TTT a [2 | i T]t] 1] 8 | Renu neces ase LE | ee pone ito} + | i | beaten sex Se i co altar Ty | esis acer 4 {opcemacions | * | o | $1 0 | nenoeeese FOL ++ Sresse agent — 1 1-8 hae 8s Soe alee TPS] tL | Rw ners ase 13 | Se pomerss rolls xs 7 | See pomers2 i [6 | tj 4 | Stone sect user a poo . 1a op tae > | bee ryefare 5 | 3 | Beh pone efifo: 5 _| 00 coae naorest tlo} to 2 | fee PPT T TT | Resear sa 5 | F ] Stee ronres PY o | tj ot | attire mse | oo | Serene fe) sy] t | Rie Asien wee Oe ory o | Femcp Car fen Rie WOT 1] Oped Riteset t+ Be Be 2 | me PY T] TG | renacaee use) 3 me PPL n't | nee aaa Sa >| a | fe Pr] t ttt] eee ses S| te ae eee sretet ts 16 | te Tt Lt | ae asset tse, + | te ie ee pete ‘Continoeah @HITACHI 122 Hitachi America, Ltd. « Hitachi taza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300HD6303X, HD63A03X, HD63B03X Tae Mae veins [eves og" ‘Addvess Bus Rw we | om Date Bus ‘mre a arena I eortee 2 | ier TT |e] t | ere nas usa 3 | See rome ° 2 faerAasrse 0) 2 | Sea pane ° © | + | rem aaoen we o | 3 | act pomer=2 ° 8 | + | Inacnegme as é 8 ft | 8 | a | ines epee ms Wels 8 fy | 8 | 1 | Memes * 8 L118 | 1_| Conan case neater 77 Sf Sp tole Resse PT 1 Ran cose 3 | Stack Pomter+ b fo jt | a | Connon 0) 6) Stack Pointer +4 1 ° 1 1 | inde Register (MS8I + | Sia roms PLS ] ot |e) ieee ngase ser a | Sta romese fc fe |b | mince Rte se: 3 | Sat pomers VPS ft] | ate sree ise 10 | moun asses | 8 11 | o | Res erate nine ar ee 3 o | t | 8] 1 | Rewenaserne asst i , ° © | 3 | mtuen adorns so )3 2 8 fe | 8 | t | Mcrnegeer use als et fe | | semen : ef} t fe | + | secmaae 8 | [8 | Satrone. 8 | 1 | 6 | 1 | comaon cos pega Bete | 2 [oo | 8 | a | Aeterna ma MF | Mes Adare 6 Oo | ot | t | ea Si Ae uss [it | Soaersmnaee | 1] 6 | Fin se Sor Rowen cr Dae t-3 || et Op ode i \ | 4 {eee | tiydy i qd 2 | Bose acousss | + | o | t | o | newroe cece wees Tew eeas rea 7 sero seo oct | 2 | 2 | ter TLS Tr Ye] renee Rete ese ter 2 | eeersann omer | | a | Fosse bec Rane me 0p Code Adress Yesn="0 © | Nem Op Code a has ase ramea a s | 3 | Stace Pomer 0 | 1 | 0 | 1 | Renan Acorns 088) & | Soa Pome of i 0 | 4 | acm aces ase, | amr aan tbo LS | o | free tag aoe @HITACHI Hitachi America, Ltd « Hitachi Paza » 2000 Sierra Point Phwy. « Brisbane, CA 94006-1819 » (416) 589-8300 123HD6303X, HD63A03X, HD63B03X = WARNING CONCERNING THE BOARD DESIGN oF OSCILLATION CIRCUIT When designing a board, note that crosstalk may disturb the ‘normal oscilation if signal lines are placed near the oxilation circuit as shown in Figure 26. Place the erystal and Cy. as close tothe HD6303X as possible, wos20ax Figure 26 Warning concerning board design of oxellation eireut (Top View! Figure 27 Example of Oscillation Circuits in Board Design © RECEIVE MARGIN OF THE Sci Table 17 Receive margin of the SCI contained in the HD6303X is yg pcr shown in Table 17 Wslerance civtorton tolerance Note" SCI Serial Communication Interface (tel re (rteh e. H06203x 237% 437% feta ee AcE te CEG) made a) avo tea Wave | er wanfoto-af oe Chara eagth Tol be -———_+ ‘= WARNING CONCERNING WAI INSTRUCTION f IF the HALT signals accepted by the MCU while the WAL in : 1 struction is executing, the CPU will not operate correctly after wal Twa wen HALT mode is canceled wating tr WAT ss scion which wats fran interop. The co es responding interrupt routine is executed after an interrupt {amb csi However, during. the execution of the WAL instruction, rona tr scorns ALT input makes the CPU malfunction and fetch an sbormsi eens vector fete for narupt interupt vectoring address. wee ee | In HALT mode, the CPU operates corectly without the WAL = Instruction, and WAL is executed correctly without HALT input, Therefore, if HALT input is necesaty. make interrupts wait during the loop routine, s shown in Figure 28 Figure 28 MAC function during WAL @HITACHI 124 Hitachi America, Ltd. « Hitachi Plaza # 2000 Sierra Point Pkwy. « Brisbane, GA 94005-1819 » (415) 589-8900oo WAT Lo0P| 1) MAL funevon 1). Recommended mathod Figure 20 Program to wait for interrupt = WRITE-ONLY REGISTER When the CPU reads a wrte-only register, the read data aiways SFF, regardless of the value in the write-only repist ‘Therefore, be careful of the reults of instructions which read “writeonly register and perform an arithmetic or logical opera tion on its contents, such as AIM, ADD, or ROL, is executed, ‘because the arithmetic or logical operation is always done with the data SEF. In particulars, don't use the AIM, OIM or EIM instruction to manipulate the DDR bit of PORT. HD6303X, HD63A03X, HD63B03X ‘= WARNING CONCERNING POWER START-UP RES must be held low for at least 20 ms when the power starts up. In this cat, the internal reset function is not effective ‘until the oscillation begins at power-on. The RES signal is input to the LSI in synchronism with the internal clock @ (shown in Figure 30.) "Therefore, after power starts up, the LSI conditions such as its UO ports and operating mode, are unstable. Fix the level of WO ports by means of an external circuit to determine the level for system operation during the oscillator stabilization time. z | inane FES pin past Figure 30. RES circuit, @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Phwy. » Brisbane, CA 94006-1819 + (415) 589-8300 125