ero INTEL 8085 MICROPROCESSOR ARCHITECTURE LEARNING OUTCOMES _Ater studying this chapter, You wil be ablo to understand the following: ‘= Pin details and layout of the 8085 microprocessor Internal functional operation of the 8085 microprocessor 39 Fegister and the purpose of each flag bit t registers, accumulator, and system bus used in the 8085 microprocessor 2 S 2.4 INTRODUCTION The microprocessor is a semiconductor device consisting of electronic logic circuits manufactured using either large-scale integration (LSI) or very large-scale integration (VLSI) technique. microprocessors WOERP (ie., interprets the nature of ‘astruction/command and develops clock-synchronized steps for execution), SSEME sPrpriae cont signals, and ally executes it The progam i in ive memory locations. The execution steps are repeated for all the instructions of the Program until the execution is terminated by hardware or software. The data required may be taken either from memory or from input ports; the results of the program may be either stored in the memory or transferred out i ‘output ports, jefore % execution, the complete program must be stored in the memory. Let us SSsume that the starting address of the stored program is 8800H. While running Program, the mic rected to ‘go’ from 8800H., Once it has roprocessor must be direc ‘go’ h “seeuted the instruction in 8800H, it goes to the next aces Bart (assuming instructions) and so on until it reaches the end of the program. Intel 8085 is an 8-bit microprocessor manufactured by Intel Corporation and ‘ Usually called a general-purpose 8-bit processor. It is upward compatible with Versi 8080, which was Intel's earlier product, There are bene of the 8085 microprocessor such as 8085. 8085AH-I, and ;20 MICROPROCESSORS AND MICROCONTROLLERS. om Fig. 2.1 A microprocessor system The function of ALU, as the name implies, is to perform arithmetic and logical operations. The control unit translates the i instructions and executes the desired task. hie mh a 2.2 ARCHITECTURE OF 8085 The block diagram explaining the architecture of Intel 8085 microprocessor is shown in Fig. 2.2. It is generally available as a 40-pin IC package and uses +5 V for power. It can run at a maximum frequency of 3 MHz. The modified versions of the 8085 processor have these minimum common features and functional similarities. The 8085 is called an 8-bit processor since its data length and data bus width is eight bits, It has an addressing capability of 16 bits, i.e., itcan address 2'°= 64KB of memory (1 KB = 1024 bytes). The processor contains five functional units: Gi) Arithmetic and logic unit (ii) General-purpose registers (iii) Special-purpose registers (iv) Instruction register and decoder (v) Timing and control unit 2.2.1 Arithmetic and Logic Unit , ALU is the circuitry that performs the actual numerical and logical operations: Addition (ADD), subtraction (SUB), increment (INR), decrement (DCR):INTEL 8085 MICROPROCESSOR ARCHITECTURE 21 Fig. 2.2 Functional block diagram of Intel 8085 and comparison (CMP) are the arithmetic operations possible in the 8085 microprocessor. The possible logical operations are AND (AND), OR (OR), exclusive OR (EXOR), complement (CMA), etc. flip-flop can only store one a ‘at a time, eight flip-flops are required K ster. “Hough the registers are all storage areas inside the microprocessor, they differ22 MICROPROCESSORS AND MICROCONTROLLERS: achieved by combining the register pairs B and C, D and E, and H and L to perform 16-bit operations. They are then named register pairs BC, DE, and HL, respectively. Among these pairs, HL’ has a special significances A few memory-related instructions of the 80857 8 lines (bidirectional) Pe heos (abdrectonen (refer instruction set) use : the HL pair as a memory -esuaaaanae¥ 1 Registers of intel 8085 pointer, For example, the instruction 2.2.3 Special-purpose Registers There are also special-purpose registers that are dedicated to a specific function The accumulator, flag register, program counter (PC), and stack pointer (SP) constitute the special registers in the 8085 microprocessor. 2.2.3.1 Accumulator The accumulator is an 8-bit register; it is a part of the ALU and is the most important register. It is used to store 8-bit data and to perform arithmetic and logical operations. The output of an operation is also stored in the lor. The accumulator is identified as register A in the instruction set The programmer can use it at any time to store an 8-bit binary number. ly eight bits long, it can only hold one byte at a time. Any previous data stored register will be overwritten as soon as new data is stored. The 8085 microprocessor communicates with input/output devices only through the accumulator. 2.2.3.2 Flag register This is a special 8-bit register. Each bit of the flag register is quite independent of the others. In all other registers, each bit is part of a single binary byte value and hence each bit would have a numerical value. their bit positions in the flag register are shown in Fig. 2.4, The remaining three bi’ (D1, D3, and D5) of the flag es remain — a Laie le show that they are not used and Esha aINTEL 8085 MICROPROCESSOR ARCHITECTURE 23 Any flag register bit is said to be ‘set’ when its value is 1 and ‘cleared’ ; " " clea i yalueis 0. The most commonly used flags are zero, carry, andign wr when its pe accessed externally, ¥- and sign. AC flag cannot The sign flag is just a copy of the hj MMSB) of the accumulator. A negative number has sy jon sigificantbit— number has a 0 in 2's complement representation, same . (It may be recalled that signed ma; anegative number and 0 to indicate signed arithmetic operations. : : gnitude numbers use 1 to indicate 4 positive number.) This flag can be used in It sets, Le. it changes to binary 1 if the result in the accumulator is zero; if not, it remains reset, i.e, at binary 0. When addition is carried out, it sometimes results in a ninth bit being carried oyer to the next byte. The C flag copies the value of the carry, which is an extra bit, from D7. It also reflects the value of the borrow in subtractions. eee The auxiliary carry flag is set when an auxiliary carry_is in the process of an arithmetic operation in the accumulator, ie, m bit D3 and passes on to D4 (HOmlinellowernibbie " it may also occur in the process of a subtraction operation. In other words, this flag is set if the subtraction operation results in borrow. Parity flag (P) ¢ content of the accumulator after an arithmetic operation erwise, the parity flag is reset. Itis set for operation in the even parity mode. 223.3 Program Counter (PC) =. other words, this register — ‘After execution of every instruction, the content of the memory location indicated by the PC is moved to the instruction register and the PC is loaded with the next address. , and hence the name program24 MICROPROCESSORS AND MICROCONTROLLERS Care must be taken by the programmer to ensure th, f data stored in the stack is retrieved properly, so that the data stored in the Stack p, the processor is not affected. 2.2.4 Instruction Register and Decoder i je content of the registe, | lecoded by the decoder circuitry, where the nature of the operation to be perform, is decided (interpreted), In addition, there are two temporary registers W and 7 which are controlled internally and not available for user access. 2.2.5 Timing and Control Unit The timing and control unit gets commands from the instruction decoder ani issues signals on the data bus, address bus, and control bus. The following section; explain the operation of the various buses and the timing. 22.5.1 Data Bus The microprocessor performs its functions using wires or lines called buses. For example, an 8-bit microprocessor normally uses eight wires to carry data between the microprocessor and the memory. To make their representation simple, the data wires with common functions are grouped together and referred to as the data bus A typical microprocessor communicates with memory and input/output devices using buses. There are three types of buses—the address bus, the data bus, and the control bus. eS a Information going into the microprocessor and results | microprocessor are through this data bus. lower group address lines AO-A7 is multiplexed with the data bus in order to reduce the pin count. Therefore, the multiplexed lower group of address lines and data lines is more generally 2.2.5.2 Address Bus ach peripheral and 'y 4 16-bit binary number called address, It follows that the maximum number of memory locations that can be addressed by the 8085 basic function is to identify a peripheral of memory location. The address bus lines are generally identified as AO-A15, The address bus has eight higher-order address lines (A8-A15), which are unidirectional, The lowe” order eight lines (AO-A7) are multiplexed (time-shared) with the eight data bis (D0-D7) and hence, they are bidirectional. When the instruction is executed, the® lines carry the address bits during the early part, and the eight data bits during !™ iINTEL 8085 MICROPROCESSOR ARCHITECTURE 25 later part. 2.2.5.3 Control Bus p © partly unidirectional and parth pidirectional. For a microprocessor to function correctly, these control signals a“ vital. The control bus typically consists of a number of single lines that coordinate and control microprocessor operations, " . 7 . Thus, they are individual lines that provide a pulse to indicate the Operation of the microprocessor. In fact, the microprocessor generates Specific control signals for every operation. which in tum are used to identify the type of device the Processor intends to communicate with. The following points describe the control and status signals of the 8085 processor: @ is a pulse that is provided when an address appears on the ADO-AD7 lines, after which it becomes 0, This signal can be used to enable a latch to save the address bits from the AD lines, thereby de-multiplexing the address bus and data bus. .--aiiaeaeicumadaliaal and that they are available on the data bus. Gia) URNBEGVE NOW OUEP HEY! The Write signal indicates that the data on the data bus are to be written into a selected memory or I/O location. Gv) it is a signal that distinguishes between a memory operation and an I/O operation. je 2.1 Status signals and @ associated operations BHAA to specify the kind of operation being performed. The status signals combine with /O signals to govern various operations; they are aes ORAS listed in Table 2.1. If both SO and S1 (ee are low, the operation of the processor |§ — “tends to halt. If SO is low and $1 is high, the processor reads data. If SO is __ high and S1 is low, the processor writes data onto a memory or V/O device. ‘If both SO and $1 are high, the fetch operation is performed. ‘The schematic representation of the 8085 bus structure, shown in Fig. 2.5, explains how the movement of data within the computer is seoomplod by a series of information, and control signals carried around inside the micro data, an external system. Hence, the buses are me @P| fh eel Ugh be Se 8085 processor accepts three more externally initiated signals—RESFT 1 Hold, and Ready as inputs. The following points explain these signals iy brief: (a) INTR (input): It is a general-purpose interrupt request signal. It is an active high signal. (b) INTA (output): Itis used to acknowledge an interrupt. It is an active lov. signal. © d than INTR interrupts. The priority order is RST 7.5, RST 6.5, and RST a (da) overridden by any‘commands1t has the highest priority interrupts. (e) RESET IN (input): counter is set to zero and the processor is feset. It is an active lon signal. (f) RESET OUT (output): beeen (h) HLDA (output): It is a acknowledge signal that is sent in Tesponse o the Hold request, During the Hold state, the peripheral (I/O) devices get control over the data and address buses for data transfer to and fro! memory. This operation is called direct memory access (DMA). DM* is useful when high-speed peripherals want to transfer data to and fro! memory. The processor does not intervene during this period. aGRRE IF this signal o: lo for an integral number of clock Ready signal must be synchron) 2.3 PIN LAYOUT AND DESCRIPTION of SIG A microprocessor is a very small ele: tronic actos. Since it is susceptible to damage encapsulated in plastic or ceramic, as show, n in Fig. 2.6. The size of the microprocessor makes it impractical to give electric al connections directly to the circuit Hence. the case is moulded with connecting pins. which in tum connect to the main circuit board. The size, shape, and number of pins on the microprocessor are dependent on the amount of data it is designed to handle, The typical pin layout and signal grou in Figs 2.7 (a) and 2.7 (b), respectively. Intel 8085 has 40 pins; for power supply. The signals can be classified into six (i) Address bus ps of the 8085 microprocessor ARCHITECTURE 27 I "en the processor is allowed to wait until Ready becomes high The | with the processor clock NALS circuit, typically 12 an inch (12mm) due to moisture and abrasion, it i oat oe A 7 Ceramic or plastic Fig. 2.6 Microprocessor C package are shown juency, and requires +5V_ groups: (ii) Data bus (ai) Control and status signals (iv) Power supply and system clock (v) Externally initiated signals (vi) Serial I/O signals Mien 5) oe 40 > V,. <2 30 > Holo "Fowa RESET OUT <—3 38 —> HLDA SOD<—4 37 —> CLK (OUT) aoe <4s 36 > RESET N TRAP <6 35 —> READY RST75 <—7 4 > 10M RST6S «6 3s RSTS5 «<—9 32 > RD ' ” 31 > WR 30 —> ALE 2 —» 90 > MS 21 > Aud 26 > AI3 5 eae u ce Att 23 > Ato 2 Ad 21 me AB Fig, 2.7 (a) Pin diagram of the 8085 RESETOUT CLK (OUT (b) {b) Signal groups of the 808528 MICROPROCESSORS AND MICROCONTROLLERS The functions of each pin are described in Sections 2.3.1-2.3.5. 2.3.1 Address and Data Buses : The 16-bit address bus and 8-bit data bus are split into the following two BroUp, (i) ie most Signitic, eight bits of memory addresses and the eight bits of the 1/0 address., ie transported on these lines. modes, 2.3.2 Control and Status Signals The 8085 uses various control signals for fetching and executing instructions. Th. operations that take place upon execution are indicated by the status signals. Th: following points explain the control and status signals of the 8085: (Address Latch Enable (output: This Tt occurs during the first clock cycle of a State and enables the address to be stored in a latch or a register. ALE can also be used to strobe the status information (ii) ut): These signals are used to indicate the kind of operation being performed, as given in Table 2.1. = (iii) IO/M (output; three-state): W/O device. access and logic 0 indicates memory access. This t stated during hold and halt modes. (iv) RD (output; three-state): Read is an active low signal that indicates that data is (v) ‘output; three-state): ae is an active low si, a that indicates that the one is mee on ma data bus at the trailing edge of the WR signal. 2.3.3 Externally Initiated Signals ollowing points explain these externally initiated smimiesiteiemmenteanlLDAthggsh seco ly microprocessor system because it determines the address at whic! program execution begins. In most microprocessor-based systems, IN signal is applied as soon as the power is turned on, A power-on re circuit is used to do this. i @INTEL 8005 MICROPROCESSOR ARCHITECTURE 29 (i) SENOUT Coury): This output signal indicates that the CPU is being reset. It can be used as a reset signal for peripheral chips. The si hs synchronized to the processor clock Peripheral chips: The'signal ts (iii) RBAAYKGinpur); This signal is used to interface aor ' the fast microprocessor. If Ready is oe oe oneal sitces wis indicates that the memory or peripheral is rea Sea oho ——— Ready is low, the CPU waits for it to hd ee dipaecbiserngiti= = , 80 high before completing the read or write cycle. (BGIANGHPAD Hold isan active high signal ySd if ihe eireeH tranister OF data between a peripheral device and memory locations. This type of data transfer is calledvasdifectimemiory access (DMA), During this transfer, the microprocessor loses control over the address and data buses and these buses are tri-stated. Logic 1 on the Hold pin indicates that another controller, generally the DMA controller, is requesting the use of the address and data buses. The CPU, upon receiving the hold request, will relinquish the use of thevbuses:after completing the Current instruction, An acknowledge signal is sent out by the processor and the address, data, RD, WR, and 1O/M lines fare tri-stated. The processor can regain control over the buses only after the Hold signal is removed. (v) HEDA (output): Hold acknowledge, an active high signal, indicates that the CPU has received the hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the hold request is removed. The CPU takes the buses half a clock cycle after HLDA goes low. INTR (input): Interrupt request is a general-purpose interrupt. It is sampled only during the last clock cycle of the instruction, If INTR is high, the program counter (PC) will not be allowed to increment and an INTA will be issued. Program execution can be shifted to the interrupt service routine by inserting an RST or CALL instruction on the data lines during this cycle. (vii) INTA (output): Interrupt aoknowledgelis an active low signal used instead ‘of RD. after an interrupt request has been accepted, This signal is used t0 read the opcode from the data bus and execute it. (viii) RST 7.5, RST 6.5, RST 5.5—srestant interrupts (input): These three inputs ae (gaya imterrapeSiGHAIs similar to INTR. They ar used to make the processor execute a subroutine ja(a/predefinedadessaHowever, these interrupts do not have an acknowledgement signal. x : “restart interrupt. It is (iv) (i RRR CR te swoon ssn or mmm To ic xa once ne soe sven oO oes30 MICROPROCESSORS AND MICROCONTROLLERS accumulator whenever a RIM instruction is executed. (ii) RIM and SIM instructions have been explained in detail in Chapter 5 2.3.5 Power Supply and System Clock : The following pins are available’ in the 8085 chip to provide power and ¢ signal to the processor: (i) X1, X2 (input): A microprocessor needs a square wave (clock) si. to ensure that all internal operations are synchronized. A crystal or Re £ or L-C network is connected to these two pins. refore, clock circuits include i /-tWO Cifcuit so thay a double-frequency crystal can be used. clock signal, the mic CLK (output): This output clock pin is used to provide the clock Signal to the rest of the system. (ii) Power supplies: V..—+5 V supply; V,,—ground reference. 2.4 MICROCOMPUTER SYSTEM BASED ON 8085 To make a complete microcomputer system, the 8085 microprocessor has to be interfaced with the memories and input and output devices. The id are of two types—RAM and ROM. ROM is necessary to store fixed These programs are executed when the system is powered up. RAM is required in any system to store temporary programs and data. A specific memory location is selected from the memory devices by issuing the address for that memory location and the control signals discussed in Section 2.3.2. The microprocessor is the master in any microcomputer system as it issues the required control signals to the peripherals. Each location in a memory is given a number, called an address. The maximum number of locations that can be addressed will depend on the number of bits in the address. Generally 2" is the number of memory locations addressed, where n is the number of bits in the address. Memory interfacing is explained in detail in Chapter 6. Similar to memory locations, each input and output device is also selected by giving a particular address. Any microprocessor-based system. in addition to memory and V/O devices, has features such as interrupt, serial dal transfer, etc. A detailed study of 8085-based system is presented in Chapter 8. ee ee