Tessent Defectsim User

Tessent® DefectSim User’s Manual
Software Version 2020.1
Document Revision 17
Unpublished work. © Siemens 2020
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Revision History ISO-26262
Revision Changes Status/

Date
17 Modifications to improve the readability and comprehension of Released
the content. Approved by Lucille Woo. Mar 2020
All technical enhancements, changes, and fixes listed in the
Tessent Release Notes for this product are reflected in this
document. Approved by Ron Press.
the content. Approved by Lucille Woo. Dec 2019
the content. Approved by Lucille Woo. Sep 2019
14 Documentation-only updates to improve the readability and Released
comprehension of the content. Approved by Lucille Woo. May 2019
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Tessent® DefectSim User’s Manual, v2020.1
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4 Tessent® DefectSim User’s Manual, v2020.1
Table of Contents
Revision History ISO-26262
Chapter 1
Tessent DefectSim Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Product Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 2
Tessent DefectSim Usage Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Summary of All Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 3
Step 1 - Create .defectsim Control File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
File Names and Directories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
top_circuit_suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
top_circuit_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
circuit_simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
spectre_lang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
working_directory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
include_measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
process_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
primitive_subcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
allow_nested_primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
custom_defect_models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
modules_directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
gatemodules_directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
mmodels_directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
schematics_directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
layouts_directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
flat_layouts_directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
include_defectsim_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
custom_models_procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
primitive_libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
x_primitives_template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
x_primitive_main_instance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Sampled Outputs and Tested Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
sampling_start_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
sampling_activity_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
sampling_activity_start_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
sampling_activity_interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
sampling_interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
simulation_end_time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Tessent® DefectSim User’s Manual, v2020.1 5

Table of Contents
sampling_threshold_voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
simdefects_start_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
digital_output_signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
digital_output_signals_safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
digital_output_signals_safe_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
test_parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
test_parameters_safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
target_number_defects_to_simulate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
seed_for_random_selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
comment_characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
hierarchy_separator_character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
stop_on_detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
reuse_initial_DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
parallel_simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
include_Func_for_DCLat_simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
eldo_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
analysis_eldo_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
simgood_eldo_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
simdefects_eldo_options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
afs_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
analysis_afs_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
simgood_afs_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
simdefects_afs_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
afs_use_spice_tran . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
questa_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
analysis_questa_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
simgood_questa_options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
simdefects_questa_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
defect_coverage_calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
RL_column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
D_column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
number_of_summary_backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
use_questa_to_list_defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
instance_parameters_in_fault_models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
reuse_sim_files_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
reuse_sim_files_defect_free_high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
reuse_sim_files_defect_free_low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
reuse_sim_files_defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
reuse_sim_files_undetected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
force_lowest_level_for_defects_listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
hierarchy_separator_for_XML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
user_defined_good_vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
report_controllability_in_summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
report_observability_in_summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
report_stress_coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
report_activity_coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
report_coverage_per_defect_type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
report_csv_with_summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table of Contents
alternative_defect_insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
insert_defect_in_all_if_clauses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
re_measure_good_circuit_simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
V_observable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
V_observability_ignore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
I_active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Iac_active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
V_active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Vac_active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
V_stress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
I_stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
connect_node0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PMHF_reference_FIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
simdefects_cptime_per_defect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Defect Injection Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SM_elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
no_short_defects_between_nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
no_short_defects_to_node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
no_defects_to_node0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
no_defects_in_subcircuit_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
no_defects_in_subcircuit_instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
no_defects_in_elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
no_defects_in_top_elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
defects_only_in_subcircuit_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
defects_only_in_subcircuit_instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
defects_only_in_elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
R_parasitic_insignificant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Basic Defect Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
float_high_voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
float_low_voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
stuck_on_defect_resistance_LW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
short_defect_resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
open_defect_resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
open_defect_R_ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Pre- and Post-Layout Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
always_add_default_defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
merge_parallel_elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
merge_parallel_primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
merge_parallel_subcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
C_parasitic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
C_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
C_defect_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
C_defect_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
C_defect_X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
R_parasitic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
R_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
R_defect_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
R_defect_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
R_defect_X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table of Contents
L_parasitic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
L_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
L_defect_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
L_defect_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
L_defect_X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Pre-Layout Relative Likelihood (RL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
RL_transistor_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
RL_transistor_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
RL_capacitance_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
RL_capacitance_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
RL_resistance_max. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
RL_resistance_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
RL_inductance_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
RL_inductance_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
RL_transistor_stuck_on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
RL_transistor_stuck_off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
RL_xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
unit_RL_M_design_LW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
RL_resistance_H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
RL_resistance_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
unit_RL_R_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
R_leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
RL_capacitance_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
RL_capacitance_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
unit_RL_C_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
RL_inductance_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
RL_inductance_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
unit_RL_L_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
RL_diode_short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
RL_diode_open. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
RL_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
RL_bipolar_base_open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
RL_bipolar_emitter_open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
fpitch_default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
tfin_default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Post-Layout Relative Likelihood (RL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
RL_opens_default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
RL_R_parasitic_redundant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
RL_shorts_default. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
unit_RL_R_parasitic_LW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
unit_RL_C_parasitic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
unit_RL_R_parasitic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
unit_RL_L_parasitic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Chapter 4
Step 2 - Prepare Top-Level, Subcircuit, and Module Directories . . . . . . . . . . . . . . . . . . . 87
Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Subcircuit Directories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table of Contents
Subcircuit File Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Circuit-Under-Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Simulation Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Process Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Chapter 5
Step 3 – Generate User-Defined Analog Defect and Fault Models . . . . . . . . . . . . . . . . . . 103
Chapter 6
Step 4 - Netlist Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Chapter 7
Step 5 - Defect Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Chapter 8
Step 6 - Simulate Defect-Free Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
simulate_defect_free . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Running Questa ADMS GUI in Display Mode to View Waveforms . . . . . . . . . . . . . . . . . . 122
Chapter 9
Step 7 - Simulate Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Example Output defectsim_summary File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Example Output defectsim_tolerance_summary File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Chapter 10
Step 8 - Simulate Undetected Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Chapter 11
Step 9 - Combine Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Chapter 12
Accuracy of Reported Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Relative Likelihoods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Process Corners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Number of Defects Simulated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table of Contents
Appendix A
Example Complete Testcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Appendix B
Recommended Usage Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Appendix C
Using UNIX Regular Expressions (regexp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Appendix D
Example File Preparation Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Appendix E
Measuring Typical Stuck-on Resistance for L=W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Appendix F
Defining Custom Analog Defect Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Appendix G
How Tessent DefectSim Measures Activity Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Explanations and Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Appendix H
Working with DefectSim Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Developing Realistic Models of Defects and Faults You Want to Detect. . . . . . . . . . . . . . . 175
Developing Circuit Block Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Diagnosing Inactive Defect Sites. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Diagnosing Undetected Defects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Reducing Test Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Appendix I
Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
The Tessent Documentation System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Mentor Support Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Third-Party Information
End-User License Agreement
with EDA Software Supplemental Terms

List of Figures
Figure 1-1. Number of Defects vs. Their Likelihood . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 1-2. Overview of Software Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 1-3. Default Injected Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 2-1. Testbench Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4-1. Parasitic Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 9-1. Waveform Viewing in EZwave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 9-2. 95% Confidence Interval vs. Defect Coverage and Defects Simulated . . . . . . . 134

List of Figures

Chapter 1
Tessent DefectSim Introduction
Tessent DefectSim (Defect Simulator) automatically inserts potential shorts, opens, and
parametric defects into an analog, mixed-signal, or digital circuit netlist to determine test
coverage of those defects in simulation (also known as fault grading).
The Tessent DefectSim tool runs transistor-level simulations of a circuit, whether it is analog or
digital, hierarchical or flat, pre-layout or post-layout subcircuit netlists, or any combination. It
allows you to use any stimuli, and almost any output analysis.
It is not usually practical to include a whole IC in a single simulation unless you have Hardware
Description (HDL) models for many of the circuit blocks. To measure coverage for a whole IC,
you should perform defect simulation for one reasonably-sized circuit block at a time, accessing
the analog block’s inputs and outputs via test buses (which may be actual or virtual), and
applying digital stimulus that would be generated by the other blocks of the IC.
Note
This software requires the Eldo® simulator to be already installed, as well as Questa®
ADMS™ if used.
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Product Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Product Overview
General purpose, digital circuit fault simulators for ICs were in common use and commercially
available between 1980 and 2000– they were efficient, effective, and essential for evaluating
new design-for-test (DFT) techniques. Now, digital fault simulators are built into digital
automatic test pattern generation (ATPG) tools. The same cannot be said for analog circuit fault
simulators, though many academic proposals have been published since 1990. Commercial use
has been hindered by the lack of a standard parametric fault model, and extremely long fault
simulations times – a defect-free analog circuit may require hours or days to simulate and
simulating thousands of possible defects would require years. Most proposed analog fault
simulators reduce a SPICE-type simulator’s accuracy to accelerate the simulation, which can
make it difficult to distinguish truly detected defects from faulty results caused by the reduced
accuracy.
Tessent DefectSim uses Mentor Graphics Eldo simulator, without affecting its accuracy, and
uses many different techniques to greatly reduce simulation time compared to simulating each
possible defect the same way that a defect-free netlist is simulated. For netlists that have no
Product Capabilities
layout information, the default defects simulated comprise stuck-on and stuck-off transistors,
shorted/open diodes, and large variations (that would be caused by a random defectivity, not by
normal variation) in values for designed-in resistors, capacitors, and inductors. For netlists
extracted with parasitics from layouts, the default defects simulated comprise shorts across
parasitic capacitances, since they indicate connector proximity, and opens in parasitic
resistances and inductances, since they indicate connector length, and shorted diodes. User-
defined defect models are permitted and Tessent DefectSim automation simplifies their
creation.
The simulation testbench is provided by you, and you may be able to use the same mixed-signal
stimulus and response analysis that you would use during circuit design. Digital outputs must be
voltages that can be compared to a threshold voltage (that you choose) to produce binary values
that can be compared to expected values (obtained from the defect-free circuit), and analog
parameters must be tested in TRAN, AC, or DC modes using EXTRACT and MEAS lines or
ADE expressions. There may be any number of outputs, preferably sampled multiple times in
the simulation, and hundreds of analog parameters tested.
When the Tessent DefectSim tool simulates a pre-layout hierarchical netlist containing no node
adjacency information, by default two possible defects are assumed for each element type.
Default defects injected pre-layout are: transistor stuck on/off, diode short/open, and resistance/
capacitance/inductance increased or decreased by 50 percent (or any percentage you choose).
The likelihood of these defects is (optionally) proportional to the expected layout area of the
elements. Any number of user-defined defect models may be applied per element, and user-
defined calculations for likelihoods are also permitted.
For a post-layout netlist, connector adjacency is inferred from parasitic capacitance in the
extracted netlist, and connector length is read directly from the extracted netlist (parasitic
extraction tools like Calibre® can place these dimensions as comments in the netlist) or a default
value is used. The default post-layout defects injected are: shorted parasitic capacitances and
diodes, and opened parasitic resistances. By default, the likelihood of a short occurring is
assumed to be proportional to the capacitance, since that value is proportional to how close two
connectors are to each other and the distance for which they are close. By default, the likelihood
of an open occurring is assumed to be proportional to the connector’s length divided by its
width, and also proportional to the number of vias or contacts (since each has a parasitic
resistance). Any number of user-defined defect models may be applied per post-layout element,
as well as the calculations for their likelihoods.
The likelihood of a defect is an important consideration since it varies tremendously, as shown

in Figure 1-1. The time to simulate each potential defect is usually constant, so it is more cost-
effective to use available simulation time to simulate the defects that are more likely.
Nevertheless, at least some of the least-likely defects must be simulated to assess total coverage.
Figure 1-1. Number of Defects vs. Their Likelihood
The Tessent DefectSim methodology for reducing simulation time comprises multiple
strategies, with a combined potential to reduce simulation time by many orders of magnitude
compared to Eldo classic running on parallel CPUs simulating the tests that would be performed
on ATE.
Random selection of defects to be simulated, regardless of the total number of potential defects,
allows you to simulate less than a few hundred defects to estimate the true coverage within a
few percent – this reduces simulation time by 10~1000X. Compared to the estimation accuracy
of simple random sampling, likelihood-weighted random sampling reduces the number of
samples needed by up to 4X.
• High-Level Models — Automatically substituting macromodels (that you created),

RTL models, or VerilogA models for the portions of the circuit that do not contain the
particular defect being simulated can reduce simulation time by 3~30X.
• Efficient Testbenches — Using tests that avoid averaging, or that apply a worst-case bit
pattern to a SerDes, or that skip a transient settling time, for example, can reduce
simulation time by 2~30X.
• Avoiding Unnecessary Simulation — The DC operating point is computed for the
defect-free circuit and reused for each circuit with an injected defect, each defect
simulation stops as soon as the defect is detected, and only undetected defects are
simulated at process corners; these reduce time by 2~10X.
• Eldo-Premier, Questa ADMS — Eldo Premier reduces simulation time by 1.5~3X,
compared to classic Eldo, without reducing accuracy if many portions of the circuit are
inactive at times, which is true for most logic gates. Questa ADMS allows simulating
large logic blocks as Verilog/VHDL RTL, which can reduce simulation time by 3~30X.
• Parallel Simulation on Multiple CPU Cores — Fault simulation is significantly more
efficient on parallel processors than when simulating a single instance (of a fault-free
circuit) with multi-threading since there is no inter-dependence between the parallel

simulations.
When simulating a manufacturing test, the outputs of the Tessent DefectSim tool are an
estimate of the test’s likelihood-weighted defect coverage, and a list of the undetected defects.
Since it is likelihood-weighted, the value can be used to estimate defective parts per million
(DPPM) for that circuit by using the classic Williams & Brown equation: D = 1-Y(1-C), where D
is the defect level or the likelihood that a device that passes the test is actually defective, Y is the
yield, and C is the likelihood-weighted defect coverage (the Seth & Agarwal equation is also
commonly used). The estimated coverage is more accurate for post-layout netlists, since each
defect’s likelihood can be estimated based on the layout. The estimate’s precision is
proportional to the square root of the number of defect samples simulated.
Some defects do not cause a circuit to fail any of its specifications. One common example is an
open in one of many transistors in parallel - it would often be indistinguishable from acceptable
process variations. Another common example is a short that causes an increase in IDDQ but
there are no limits for IDDQ - in this case, a test specification should be added since the defect
is a reliability risk.
Undetected defects that are very unlikely to occur should not be ignored since there are many
more of them that were not chosen for simulation, the sum of all their likelihoods is comparable
to individual more-likely defects, and there are usually systematic reasons for their not being
detected (for example, no IDDQ test, or no reset, or non-optimal stimulus frequency).
Figure 1-2 provides an overview of the Tessent DefectSim commands and the files they use and
generate. The tool uses Eldo to extract information about elements in the netlist and for all
simulations.
• Netlists in HSpice format are handled by Tessent DefectSim and Eldo without
modification, except for adding .OPTION COMPAT to the process file or the
<CUT>.circuit file.
• Netlists in Spectre format are handled by Tessent DefectSim with minor modifications.
Only tran, ac, and dc analysis is permitted, and any parametric measurements must be
performed using Eldo/HSpice commands .EXTRACT or .MEASURE, and/or Spectre
asserts or ADE expressions. The <CUT>.defectsim file must contain the setting
spectre_lang on.
Figure 1-2. Overview of Software Steps
Figure 1-3 shows schematics of the different defects that are injected by Tessent DefectSim.
Defect simulation should be performed early in a design, before all subcircuit layouts are
complete or available while there is time to change the architecture to include more test access
or DFT to enhance coverage if needed. Simulation time is usually significantly faster then than
for post-layout simulations, especially compared to simulation of flat post-layout netlists.
Figure 1-3. Default Injected Defects
Chapter 2
Tessent DefectSim Usage Overview
As shown in the figure below, a testbench applies test stimuli and analyzes the outputs of the
circuit-under-test (CUT). The testbench may include EXTRACT or MEAS or asserts or ADE
expression lines that test parameters. And it may include simulator options that affect
simulation accuracy/speed and information saved. In the filename, <CUT> must be upper case.
<CUT>.testbench is an optional file – its contents may be included within the <CUT>.circuit
file instead. Having a separate <CUT>.testbench file allows you to include parameter settings,
stimuli, analysis, or circuitry that you plan to change for different test conditions without editing
the <CUT>.circuit file–defects are not injected in any <CUT>.testbench circuitry.
Figure 2-1. Testbench Overview
Most defects can be detected at nominal process, voltage, and temperature (PVT), but some
defects may only be detectable at best or worst case supply voltage and temperature conditions
or a process corner. You should choose the ‘typical’ process for the first simulation, since it
represents the most likely circuit parameters, and then simulate undetected defects at process
corners. The first test condition used should reflect your planned manufacturing test sequence –
some companies test first at wafer-sort using an extreme temperature, and then test packaged
devices at room temperature, and some companies do the opposite.
You indicate the process file name in the <CUT>.defectsim file. Tessent DefectSim simulates
with one process file at a time. You may combine the result summaries for different process
files by using the create_combined_summary command.
The netlist in the CUT file may have any number of inputs and outputs with any voltage range,
but outputs that you list as digital_output_signals in <CUT>.defectsim are compared to a single
threshold voltage (that you set in <CUT>.defectsim) to produce a pattern of 1s and 0s; you may
add level-translators in the testbench. Tested parameters may be measured at specific times or
intervals – note that some functions prevent AUTOSTOP and thus prevent quitting each defect
simulation as soon as the defect is detected.
Note
You should first perform defect simulation with only schematic netlists (and macromodels,
if available) to achieve fastest simulation time and easiest resolution of undetected defects.
After more than 95 percent coverage is achieved, re-run simulations with hierarchically
extracted layout netlists for the subcircuits. Lastly, if simulation time will not be impractically
long, simulate a a flat-extracted layout netlist.
Note
<CUT> is used throughout this manual to indicate the root name of your top circuit,
testbench, and defectsim files. In <CUT>.defectsim, you specify any suffix for your top-
level circuit file, but the other two file names, <CUT>.defectsim and <CUT>.testbench, are
mandatory. To simplify explanations in this manual, only <CUT>.circuit will be shown for the
circuit filename.
See “Example File Preparation Procedure” on page 157 for an example file preparation
procedure.
Note
Eldo checks out a number of Eldo licenses that is proportional to the number of CPUs or
threads running in parallel. When the file being run contains a .DEFECTSIM line which
Tessent DefectSim adds automatically, Eldo also checks out an equal number of Tessent
DefectSim licenses, and then creates a .sig file for each .chi and .aex file generated. Tessent
DefectSim only reads these files if their .sig files are correct. If no Tessent DefectSim licenses
are available, Eldo will issue a warning that the results will not be usable by Tessent DefectSim;
if insufficient licenses are available, Eldo will reduce the number of CPUs or threads used.
Summary of All Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Summary of All Commands

In Steps 1 and 2, you create all files and directories needed to run a defect simulation.
Example files are provided in “Example Complete Testcase” on page 145.
The primary files and directories are as follows:
• <CUT>.circuit — Can be any circuit netlist, and may have multiple .INCLUDE lines
and subcircuit instances (but no subckt lines). Instead of 'circuit', a different suffix may
be specified in top_circuit_suffix.
• <CUT>.testbench — Provides stimuli, power, analyses, and Eldo output options. This
file is optional—its contents may be included in <CUT>.circuit.
• <CUT>.defectsim — Lists signals or parameters to be tested, and all defect simulation
options.
• modules_directory — Contains highest-level Verilog/VHDL modules.
• gatemodules_directory — Contains lowest-level Verilog/VHDL modules that typically
begin with `celldefine, such as for logic gates, op-amps, and comparators.
• mmodels_directory — Contains VerilogA models and subcircuits containing only HDL
models or Eldo macromodels.
• schematics_directory — Contains design-intent subcircuit netlists.
• layouts_directory — Contains layout-extracted subcircuit netlists.
• flat_layouts_directory — Contains flat-layout-extracted netlist of most of the CUT.
To run individual commands, enter the following on the command line:
defectsim <CUT> (<CUT> may include a hierarchical path)
followed by one of the following commands (see Steps 1 to 8 for details):
• help command_name — To see list of allowed options.

• create_defectsim_config — To create a <CUT>.defectsim file containing all parameters
and their default settings. If the file already exists, <CUT>.defectsim_default will be
created instead. See “Step 1 - Create .defectsim Control File” on page 27.
Options: (none)
• create_consolidated_modules — To copy all found HDL modules into the modules,
gatemodules, and mmodels directories, as appropriate, with one file per module, and
create a subcircuit wrapper for each module in the mmodels directory.
Options: -input_filename filename [-force_overwrite]
• create_consolidated_subcircuits — To copy all found subcircuit files into the mmodels,

schematics, layouts, and flat_layouts directories, with one file per directory per
subcircuit. See “Step 2 - Prepare Top-Level, Subcircuit, and Module Directories” on
page 87.
Options: [[-schematics | -layouts | -mmodels]| [-output_directory directory]] [[-input
filename [-create_all_files [-separate_testbench]] [-no_comments] [-force_overwrite]] |
-overwrite]
• create_primitive_subcircuit_list — To create a list file of the subcircuits in the
schematics_directory that appear to be primitives.
Options: [directory] [-output_filename filename] [-replace]
[-add_single_instance_primitives]
• create_defect_models — To create custom defect models for any or all circuit element
types. See “Step 3 – Generate User-Defined Analog Defect and Fault Models” on
page 103.
Options: -output_file prefix [-type basic | ieee2427hard | ieee2427soft | ieee2427]
[-element r|c|l|d|m|q ] [-add_to_config]
• create_fault_models — To create custom fault models for listed primitive subcircuits
based on custom templates. If <CUT>.defectsim contains primitive_circuits list_file
prefix.defectsim_defective_subcircuits, it will read the first file and create the second
file, otherwise it will provide the file with prefix indicated.
Options: [templates_file] [-input_file list_file] [-output_file prefix] [-add_to_config]
[-generate_default_templates] [-replace]
• create_defect_sites_list — To create a list of all potential defect sites, based on pre- and
post-layout netlist information. See “Step 4 - Netlist Analysis” on page 109.
Options: [-treat_parallel_resistors_as_redundant | -reuse_parallel_resistors_file |
-generate_parallel_resistors_file_only ]
Options: [-reuse_simulation_files]
• create_activity_results — To measure activity at all defect sites in the defect-free circuit,
and optionally create potential defect sites list with activity-based RL values.
Options: [-activity_based_rl]
• create_defects_to_simulate — To randomly select defect sites and inject appropriate
defects. See “Step 5 - Defect Injection” on page 115.
• simulate_defect_free -view_highest — To simulate the good (defect-free) circuit, using
highest-level netlists, and capture defect-free output voltages as 1 or 0, or using the
lowest-level netlists, and ensure they deliver the same results.
Options: [-view_highest | -view_lowest] [-reuse_simulation_files | -re_measure]
• simulate_defects — To simulate the randomly selected defects, and summarize the

results. See “Step 7 - Simulate Defects” on page 125.
Options: [-calculate_lfm summary1 n1 summary2 n2 ...] [[-undetected summary_file]
[-suffix suffix] [-summary_only] [-only_defects { Dn, Dm, ..., Dx-Dy }] [-except_defects
{ Dn, Dm, ..., Dx-Dy }] [-reuse_simulation_files | -re_measure]
• create_combined_summary — To combine summaries from different tests, test
conditions, or process to produce a combined coverage and matrix, and list only defects
undetected by all. See “Step 9 - Combine Summaries” on page 139.
Options: -input_files { summaryFile1 summaryFile2 ... } [-replace] [-output_file
filename]
• create_combined_activity — To combine <CUT>.good_results files from different tests
or test conditions to produce a combined activity summary. See “Step 9 - Combine
Summaries” on page 139.
Options: -input_files { good_results1 good_results2 ... } [-replace] [-output_file
filename]
• create_combined_defect_tolerance — To combine
<CUT>.defectsim_tolerance_summary files from different tests or test conditions to
produce a combined defect tolerance summary. See “Step 9 - Combine Summaries” on
page 139.
Options: -input_files { tolerance_summary1 tolerance_summary2 ... } [-replace]
[-output_file filename]
• create_combined_summaries_of_circuits — To combine <CUT>.defectsim_summary
files from different circuits to produce a combined defect coverage summary.
Options: -input_files { summary1 summary2 ... } [-replace] [-output_file filename]
• delete_generated_files — To delete all Tessent DefectSim tool-generated files in the
current directory and in the defectsim_*outdir sub-directories.
• dofile filename — To run the commands listed in filename.
Note
You may run Tessent DefectSim without specifying a CUT argument if “-dofile
filename” is entered with no command, and the filename specified includes a set_cut
command.
• set_defectsim_config_value — To modify a <CUT>.defectsim parameter from within a

dofile, a script, or within interactive mode. If multiple values are provided, they must be
within braces ({}). The file contents are automatically re-read by Tessent DefectSim
after the command.
Options: config_parameter value1 | { value1 value2 ... } | [-default | -comment_out]]
Examples:
set_defectsim_config_value test_parameters { abc def }
set_defectsim_config_value test_parameters -comment_out
set_defectsim_config_value rl_resistance_h -default
set_defectsim_config_value simulation_end_time 20u
• report_defectsim_config_value — To report the value of a <CUT>.defectsim parameter

from within a dofile, a script, or within interactive mode. If the values of multiple
parameters are requested, they must be within braces.
Options: config_parameter | { config_parameter1 config_parameter2 ... }
Examples:
report_defectsim_config_value { test_parameters \
test_parameters_safety }
report_defectsim_config_value target_number_defects_to_simulate
Unambiguous shortened versions of the commands are accepted. Here are some examples:
• create_consolidated_subcircuits may be invoked as follows:

cr_con_sub
or
c_c_s
but not by “create_con”.

• create_defect_sites_list may be invoked as follows:
cr_def_sites
or
c_d_s
but not by “create_defect”.

• create_defects_to_simulate may be invoked as follows:
cr_def_to_sim
or
c_d_t
but not by “create_defect”.

• simulate_defect_free -view_highest may be invoked as follows:
sim_def_free
or
sim_def_fr -v_hi
but not by “simulate_defect” (which will run simulate_defects).

• simulate_defect_free -view_lowest may be invoked as follows:
sim_def_fr -v_lo
or
s_d_f -v_l
but not by “simulate_defect_free”.

Except for one primary output file per command, and files that you instruct Eldo to create, all
Tessent DefectSim tool-generated files are in sub-directory defectsim_outdir.
Tessent DefectSim may also be run in interactive mode. To initiate interactive mode, enter the
command
defectsim <CUT>
To run multiple commands, without entering interactive mode, enter the commands within
quotes and separated by semicolons:
defectsim <CUT> “<command>; <command>; <command>”
Steps must be run in sequence to ensure appropriate files are available for each subsequent step.
Tessent DefectSim will report an error message if you run commands in the wrong order. Here
is the only exception:
• simulate_defect_free -view_lowest is not needed and will not run when there is only one
directory of subcircuits.
To quit out of a command immediately, even if it is running Eldo, enter Ctrl-C. (You can ignore
any error message about the .sig file not matching the .chi file.)
In addition to the commands on the preceding page, the following useful commands are
available in interactive mode:
• echo — Display value of a parameter

• help — Prints this list of options (plus some others not applicable to Tessent DefectSim)
• help command — Prints syntax for a command
• history — Lists all commands previously entered in current session
• q — Exits (quits) Tessent DefectSim
• report_config_option variable — Lists value of a variable or .defectsim setting (use
braces around a list)
• set_cut — Reads the <CUT>.defectsim or <CUT>-<test>.defectsim file.

• read_config — Re-reads <CUT>.defectsim file (in case you edited it)
• set variable value — Sets a variable to a value (use quotes around a list)
• system Linux command — Runs a Linux command from within DefectSim
Interactive mode can be faster than non-interactive mode because the license manager is
invoked only when entering interactive mode, and <CUT>.defectsim is read only once (so if
you edit that file while in interactive mode, you must run read_config). To run a list of
commands, put each interactive command on a separate line in a text file, for example mydofile,
then in interactive mode, enter the command “dofile mydofile”. Here are example contents of a
dofile:
create_defect_sites_list
system cp INPUT.potential_defect_list INPUT.potential_defect_list_save
create_defects_to_sim
simulate_defect_free
sim_defect_free -view_low
simulate_defects
Here is an illustrative example of interactive mode:
defectsim> report_config_option schematics_directory

- schematics_directory: example_schematic_netlists
defectsim> report_config_option {schematics_directory layouts_directory

c_design c_defect_h c_defect_l}
- layouts_directory:
- c_design: 1e-13
- c_defect_h: 50
- c_defect_l: 50
defectsim> set myoptions "schematics_directory layouts_directory"

schematics_directory layouts_directory
defectsim> report_config_option $myoptions

- layouts_directory:
defectsim> system pwd

/home/user/DefectSim/testcases/demo/EXAMPLE_PLL
0
defectsim> q
DefectSim closed
Chapter 3
Step 1 - Create .defectsim Control File
Create a <CUT>.defectsim file to define subcircuit directories, control simulation time, provide
defect options, and define signals/parameters tested.
You can create a default <CUT>.defectsim using the following command:
defectsim <CUT> create_defectsim_config
In that file, you may use an environmental variable in the path name for any file, using the
syntax $variable.
Any setting that shows values 1/0, on/off, or yes/no, respectively, may be set to any of those six
values.
// All lines are optional. Parameter names are case-insensitive.

// Line continuation character is \ at end of line, preceded by a space.
// Most values below are default, but some are just examples. See detailed definitions for
// default values.
// File names and directories

top_circuit_suffix .circuit // Suffix of top-level SPICE/Spectre file; its prefix
// must be the same as .defectsim file
top_circuit_type prelayout // Indicates whether top-level elements are pre- or
// post-layout
circuit_simulator eldo // Sets simulator to Eldo or Questa ADMS
spectre_lang off // Sets default netlist interpretation to Spectre
working_directory ../defectsim // All output files and sub-directories are put here
include_measures my_extracts // An optional file containing EXTRACT/MEAS lines
process_file ./initial.process // File containing process parameters for first
// simulation
primitive_subcircuits list netlists // Filename containing list of primitive subcircuits
// and filename with user-provided defective
// subcircuit netlists
allow_nested_primitives off // Prevent defect insertion within
// lower levels
custom_defect_models defect_netlists // Filename with user-provided defect netlists
mmodels_directory ./mmodels // One or more directories containing higher-level
// models of subcircuits, with .sub or .scs suffix
schematics_directory ./schematics // One or more directories containing design-intent
// netlists, with .sub or .scs suffix
layouts_directory ./layouts // One or more directies containing
// layouts-extracted netlists, with .sub or .scs
// suffix
flat_layouts_directory ./flat // One or more directories containing flat layout-
// extracted netlists with .sub or .scs suffix
include_defectsim_file ../proj2/abc.defectsim // Includes content of another .defectsim
// file
custom_models_procedures my_procs // File containing procs can be called by
// defect/fault models
primitive_libraries pdk_library2 // Identifies the primitive subcircuits based on the
// header comment
x_primitive_main_instance main // Identifies the main instance within a primitive;
// x may be R, C, L, D, M, or Q
x_primitives_template res // Identifies the type of primitive;
// x may be R, C, L, D, M, or Q
// Sampled outputs, and tested parameters

sampling_start_time 0 // Time at which output voltages are first sampled
sampling_activity_start_time 0 // Time at which activity is first sampled
sampling_activity_interval 50n // Time between consecutive samples for activity
sampling_activity_delay 0n // Delay added to measure activity
sampling_interval 100n // Time between consecutive samples of output
// voltages
simulation_end_time 1000n // Time at which transient simulation ends
sampling_threshold_voltage 0.5 // Outputs are captured as 0 or 1 relative to
// this voltage
simdefects_start_time 100n // Start defect simulation at t>0 to save time
digital_output_signals out1 out2 // Output signals sampled to compare good and
// defective circuits
digital_output_signals_safety out2 // Outputs of Safety Mechanism (SM)
digital_output_signals_safe_mode 1 // SM output logic value that activates safe mode
test_parameters gain THD // Name of extracted parameter value that has lower
// and upper test limits

test_parameters_safety THD delay // Safety specifications
// General parameters
target_number_defects_to_simulate 10 // Target number of defects to simulate
seed_for_random_selection 123456 // Positive integer seed <4G for selecting defects
// randomly
comment_characters ! // Comment characters recognized by Tessent
// DefectSim, in addition to ‘*’
hierarchy_separator_character . // Character to be used when reading hierarchical
// names and nodes
stop_on_detection on // Stops each defect’s simulation as soon as a
// difference is detected
reuse_initial_DC on // Uses initial DC voltages from good circuit for
// defective circuits
parallel_simulation .MPRUN * options // Eldo command to run defect simulations in parallel
include_Func_for_DCLat_simulation on // Function included with Safety Mechanism
eldo_options // Options used by all commands that call
// Eldo
analysis_eldo_options // Options used by Eldo when
// create_defect_sites_list calls it
simgood_eldo_options // Options used by Eldo when simulate_defect_free
//calls it
simdefects_eldo_options // Options used by Eldo when simulate_defects calls it
afs_options // Options used by AFS when any command
//calls it
analysis_afs_options // Options used by AFS when
//create_defects_sites_list calls it
simgood_afs_options // Options used by AFS when
// simulate_defect_free calls it
simdefects_afs_options // Options used by AFS when
// simulate_defects call it
afs_use_spice_tran on // Expect .tran line instead of tran when the
// simulator is AFS
questa_options // Options used by Questa ADMS by all commands
// that call it
analysis_questa_options -topspice mytop // Options used by Questa when
// create_defect_sites_list calls it
simgood_questa_options -topspice mytop // Options used by Questa when simulate_defect_free
// calls it
simdefects_questa_options -topspice mytop // Options used by Questa when simulate_defects
// calls it
defect_coverage_calculation // Uses new or old formula to calculate defect

// coverage, or applies uniform weighting
RL_column 95 // All [pxxxRL=nnn.nnn] values are written starting
// in this column
D_column 115 // All Dnn values are written starting in this column
number_of_summary_backup 9 // Max number of summaries, each with .bak#
use_questa_to_list_defects on // Uses Questa ADMS, instead of Eldo, to list defects
instance_parameters_in_fault_models 1 // If set to 0, it disables use of
// $instance(<parameter>) in expressions.
warn_if_missing_instance_parameters 0 // Lists up to this number of parameters
reuse_sim_files_analysis 0 // create_defect_sites_list will reuse sim file
reuse_sim_files_defect_free_high 0 // simulate_defect_free -view_high will reuse sim
// files
reuse_sim_files_defect_free_low 0 // simulate_defect_free -view_low will reuse sim files
reuse_sim_files_defects 0 // simulate_defects will reuse sim file
reuse_sim_files_undetected 0 // simulate_defects will reuse sim file

force_lowest_level_for_defects_listing on // off reduces number of excluded defects
// listed without RL, but may cause .BIND problems
hierarchy_separator_for_XML .X / // In output XML file, replace first character(s) with
// second
user_defined_good_vector filename // Uses this file as good_vector, instead of default

// in outdir
report_controllability_in_summary on // When on, difference in voltages across defect site
// are reported
report_observability_in_summary on // When on, reports port voltages of subcircuits
// containing defect
report_stress_coverage on // Reports this coverage in .good_results
report_activity_coverage on // When on, reports whether each defect site is
// active/inactive
report_csv_with_summary off // .csv files can be generated for use in Excel
report_coverage_per_defect_type on // Separate results for shorts, opens, variations.
alternative_defect_insertion off // Injects defects without using .BIND for faster
// elaboration
remove_eldo_instance_escaping_for_bind on // Works around Eldo bug handling escapes in
//Spectre subckt names
remove_eldo_wrong_escaping_on_list 0 // Use when \<1\> causes problems
use_include_in_defectsim_libs on // off will use old method of copying all subckts to
// HIGHEST and LOWEST
ifstatement_check off // Disables reporting that a circuit
// element is in an if statement
insert_defect_in_all_if_clauses off // Disables auto-insertion of defects in
// if-else clauses
re_measure_good_circuit_simulation off// Disables auto re-running of defect-free circuit
// to obtain test limit parameter values
V_observable 100m // Minimum voltage change for a subcircuit port to be
// declared observable
V_observability_ignore 1m // Minimum voltage change for a subcircuit port to be
// reported
I_active 1u // Minimum current to be considered active defect site
Iac_active 0.1u // Minimum current change to be considered active
// defect site
V_active 0.1 // Minimum voltage to be considered active defect site
Vac_active 0.01 // Minimum voltage step to be considered active defect
// site
V_stress 0.5 // Minimum node-pair voltage for an element to be
// declared stressed
I_stress 1m // Minimum node current for an element to be
// declared stressed
connect_node0 VSS // Connects this node to node 0 in netlist
PMHF_reference_FIT 1e-12 // ISO 26262 metric PMHF calculated relative to this
simdefects_cptime_per_defect 200 // Sets max CPU time (in seconds) per defect
// simulated
// Defect injection exclusions

SM_elements x3 // Instances in Safety Mechanism
no_short_defects_between_nodes VDD VSS // Two nodes that should have no inserted shorts
// connect between them
no_defects_to_node0 // Node that should have no inserted shorts
// connected to 0
no_defects_in_subcircuit_names // Do not list defects in subcircuits with these
// names
no_defects_in_subcircuit_instances // Do not list defects in these subcircuit instances

no_defects_in_elements // Do not select potential defect lines containing
// this text
no_defects_in_top_elements ^R // Do not list top-level elements with these instance
// names
defects_only_in_subcircuit_names // Only list defects in subcircuits with these names
defects_only_in_subcircuit_instances // Only list defects in these subcircuit instances
defects_only_in_elements // Only select potential defect lines containing
// this text
R_parasitic_insignificant 5 // Layout resistances less than this are set to 0
// Basic defect values

float_high_voltage 1.0 // Voltage that open circuits tie to via
// open_defect_R_ratio x open_defect_resistor
float_low_voltage 0.0 // Voltage that open circuits tie to via
// open_defect_R_ratio x open_defect_resistor
// All the following lines can be in a shared file that is named by include_defectsim_file
stuck_on_defect_resistance_LW 1000 // Fesistance of stuck-on transistor with L/W=1.0
// for default models
short_defect_resistance 10 // Short circuit (bridge) resistance
open_defect_resistance 1G // Open circuit resistance (G indicates giga)
open_defect_R_ratio 10 // Ratio of pull-up/down resistance to
// open_defect_resistor
// Pre/post-layout defect parameters

always_add_default_defects on // Defaults used even if there are user-defined
// defects
merge_parallel_elements on // On merges the elements and increases m

merge_parallel_primitives on // On merges the subcircuits and increases m
merge_parallel_subcircuits on // On merges non-primitives and increases m
C_parasitic 10f // Smaller capacitances in schematic are assumed
// to be parasitic
C_design 100f // Larger capacitances in layout netlist are assumed
// to be designed
C_defect_H 20 // Designed capacitors increase by this %,
// when defective too high
C_defect_L 50 // Designed capacitors decrease by this %,
// when defective too low
C_defect_X 1 // User-defined parameter for custom defect models and
// primitive subcircuit fault models; 'X' may be any
// letter.
R_parasitic 10 // Smaller resistances in schematic are assumed to
// be parasitic
R_design 100 // Larger resistances in layout netlist are assumed
// to be designed
R_defect_H 10 // Designed resistors increase by this %, when
// defective too high
R_defect_L 50 // Designed resistors decrease by this %, when
// defective too low
R_defect_X 1 // User-defined parameter for custom defect models and
// primitive subcircuit fault models; 'X' may be any
// letter.
L_parasitic 1n // Smaller inductances in schematic are assumed to
// be parasitic
L_design 10n // Larger inductances in layout netlist are assumed
// to be designed
L_defect_H 10 // Designed inductors change by this %, when

// defective too high
L_defect_L 50 // Designed inductors change by this %, when
// defective too low
L_defect_X 1 // User-defined parameter for custom defect models
// and primitive subcircuit fault models; 'X' may be
// any letter.
// Pre-layout relative likelihoods

RL_transistor_max 100 // Maximum RL for transistors
RL_transistor_min 0.01 // Minimum RL for transistors
RL_capacitance_max 100 // Maximum RL for capacitor
RL_capacitance_min 0.01 // Minimum RL for capacitor
RL_resistance_max 100 // Maximum RL for resistor
RL_resistance_min 0.01 // Minimum RL for resistor
RL_inductance_max 100 // Maximum RL for inductor
RL_inductance_min 0.01 // Minimum RL for inductor
RL_transistor_stuck_on 1.0 // Relative likelihood (RL) of transistor stuck on
RL_transistor_stuck_off 1.0 // RL of transistor stuck off
RL_xx 1 // User-defined parameter for custom
// defect models and primitive subcircuit fault
// models; 'xx' may be any
// letters, digits, or _
unit_RL_M_design_LW 1e-15 // If>0, makes RL of transistor defect proportional
// to L x W
RL_resistance_H 1.0 // RL of designed resistance varying too high
RL_resistance_L 1.0 // RL of designed resistance varying too low
unit_RL_R_design 10000 // If >0, makes RL of designed resistors proportional
// to resistance
R_leakage 1e10 // Resistors with larger values will be assigned
// RL=0
RL_capacitance_H 1.0 // RL of designed capacitance varying too high
RL_capacitance_L 1.0 // RL of designed capacitance varying too low
unit_RL_C_design 1e-13 // If >0, makes RL of designed capacitors proportional
// to capacitance
C_parasitic_insignificant 1e-16 // Smaller capacitances will be assigned RL=0
// default setting is 0
RL_inductance_H 1.0 // RL of designed inductance varying too high
RL_inductance_L 1.0 // RL of designed inductance varying too low
unit_RL_L_design 1e-12 // If >0, makes RL of designed inductors proportional
// to inductance
L_parasitic_insignificant 1e-16 // Smaller inductances will be assigned RL=0;
// default setting is 0
RL_diode_short 1.0 // Relative likelihood of diode shorted
RL_diode_open 1.0 // Relative likelihood of diode open
RL_model nmos 1 pchan 1.5 // Relative likelihood for different model types
RL_bipolar_base_open 0.1 // Relative likelihood of bipolar transistor base open
// defect
RL_bipolar_emitter_open 0.1 // Relative likelihood of bipolar transistor emitter
// open defect
fpitch_default 50n // Sets the default FPITCH in finFET RL calculations
tfin_default 5n // Sets the default TFIN in finFET RL calculations
// Post-layout relative likelihoods

RL_opens_default 0.1 // RL of open resistor or inductor when no size info
RL_R_parasitic_redundant 0 // Sets RL of any redundant resistors
// (i.e., in parallel in layout)
RL_shorts_default 0.2 // RL of capacitor short if prelayout parasitic
unit_RL_R_parasitic_LW 0.5 // Resistor L/W on unknown level whose RL of open is 1

unit_RL_R_parasitic_LW 0.5 1.0 metal1 // As above + resistor L/W and known level whose RL
// of open is 1
unit_RL_C_parasitic 10f // Capacitance whose RL of short is 1.0; always
// proportional to C
unit_RL_R_parasitic 1000 // If >0, forces RL of parasitic resistors
// proportional to resistance
unit_RL_L_parasitic 1e-12 // If >0, makes RL of parasitic inductors proportional
// to inductance
File Names and Directories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Sampled Outputs and Tested Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Defect Injection Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Basic Defect Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Pre- and Post-Layout Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Pre-Layout Relative Likelihood (RL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Post-Layout Relative Likelihood (RL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
File Names and Directories
File Names and Directories

The following describe the parameter settings in detail.
top_circuit_suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
top_circuit_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
circuit_simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
spectre_lang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
working_directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
include_measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
process_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
primitive_subcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
allow_nested_primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
custom_defect_models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
modules_directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
gatemodules_directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
mmodels_directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
schematics_directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
layouts_directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
flat_layouts_directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
include_defectsim_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
custom_models_procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
primitive_libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
x_primitives_template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
x_primitive_main_instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
top_circuit_suffix
Filename suffix for your top-level circuit to be simulated. The filename without its suffix must
be same <CUT> as the <CUT>.defectsim file.
The filename without its suffix must be same <CUT> as the <CUT>.defectsim file. Do not
include the initial period '.' in the suffix.
The default is circuit
top_circuit_type
top_circuit_type
This parameter indicates whether circuit elements at the top-level of the circuit are to be treated
as pre- or post-layout. For default defect models, if pre-layout, the elements are randomly varied
and the transistors are stuck-on or off. For default defect models, if post-layout, opens and
shorts are randomly injected only in the RCL elements. This setting does not affect defect
injection in the subcircuits. Choices are prelayout or postlayout.
The default is prelayout
circuit_simulator
This chooses the circuit simulator to be run by Tessent DefectSim: Eldo, Questa, or AFS.
The option 'questa' may be followed by the name of a dofile.
Example:
questa my.dofile
The default is eldo
spectre_lang
When this is set to on, any netlist file with suffix .scs is interpreted in Spectre format, and any
other suffix is recognized as Eldo or HSpice format.
In either case, within the netlist file, the language can be switched using simulator
lang=spectre or simulator lang=spice. You can control case sensitivity by adding
insensitive=yes|no to this line. By default, all Spectre sections are case-sensitive, and all Spice
sections are case-insensitive (-case is not supported).
The default is off
working_directory
The path to a directory where all Tessent DefectSim output files and sub-directories will be
placed instead of in the current directory (that must contain <CUT>.defectsim). This is useful if
you need to use a directory in which you can store larger files than the current directory allows.
This setting is added automatically in ADE to be consistent with the usual ADE configuration of
directories.
The default is ./
include_measures
include_measures
The name of a file containing .EXTRACT or .MEAS lines. If create_consolidated_subcircuits
encounters an INCLUDE line that points to that file (in any path), the INCLUDE line will be
commented out and not expanded as it would do for any other INCLUDE lines. This allows you
to later edit the include_measures file without having to re-run create_consolidated_subcircuits
to propagate the changes. Later steps will automatically check the contents of the file and call it
during simulation.
There is no default
process_file
Filename of process parameter file to be used for simulations. This should be nominal process
parameters initially, and then process corners in subsequent defect simulations (and optionally
using simulate_defects -undetected so that only defects that were undetected for the nominal
process are simulated for process corners).
The default is ./initial.process
primitive_subcircuits
The first listed filename contains a list of names of subcircuits that are to be considered as
potentially defective instead of each of the circuit elements within them.
You can define entire defective subcircuits, in addition to defective elements, and you can
define how their relative likelihood of being defective is calculated. This is suitable for
primitives in a process design kit (PDK), or for large circuits where a defect is not specific to
one element within the subcircuit. The named file must contain a list of subcircuit names, one
per line, each with their circuit type and optionally the name of an instance within the subcircuit
from which Tessent DefectSim can obtain instance-specific values to be used in defective
subcircuit or its RL calculation. Any text can be used for the circuit_type, and the corresponding
lines in the <CUT>.potential_defect_list will be sorted by the sub-instance type, and will
include the usual parameters for that circuit element type. If no sub-instance is provided, then
the lines will be placed (without any parameters) at the end of <CUT>.potential_defect_list.
You must provide the defective primitive subcircuit netlists within the second listed filename.
The file can be in any directory and have any name, but its suffix must be
.defectsim_defective_subcircuits. For more details, see “Step 3 – Generate User-Defined Analog
Defect and Fault Models” on page 103 and “Defining Custom Analog Defect Models” on
page 161. Syntax of each line in primitive_subcircuits file:
<subckt_name> <circuit_type> <sub_instance> <port> <port>
Example:
my_list_primitives my.defectsim_defective_subcircuits
allow_nested_primitives
There is no default
allow_nested_primitives
If a primitive subcircuit contains a primitive subcircuit, and you do not declare a main instance
for the higher-level subcircuit in the list of primitives, both will be listed in
<CUT>.potential_defect_list. Sometimes this is useful, for example, when you want to add
shorts from subcircuit terminals to VDD or VSS, in addition to the shorts in each transistor.
Other times, defects are only wanted in the higher-level subcircuit. To obtain this behavior, use:
allow_nested_primitives off
The default is on.
custom_defect_models
Filename that contains custom netlists for defects in individual circuit elements (R,C,L,M,D,Q).
These custom defect models use the syntax defined in “Defining Custom Analog Defect
Models” on page 161. The file can be in any directory and have any name, but its suffix must be
.defectsim_defect_models.
Example:
my.defectsim_defect_models
There is no default
modules_directory
A directory containing HDL modules. Each module must be in its own file of the same name
and case, with .v, .va, or .vhd as a suffix. create_consolidated_modules will automatically store
Verilog* and VHDL files (that do not begin with `celldefine) in this directory with the
appropriate suffix.
gatemodules_directory
A directory containing basic HDL modules. Each module must be in its own file of the same
name and case, with .v, .va, or .vhd as a suffix. create_consolidated_modules will automatically
store Verilog* and VHDL files (that begin with `celldefine) in this directory with the
appropriate suffix.
mmodels_directory
mmodels_directory
One or more directories that contain higher-level models of subcircuits in your CUT – these
must be subcircuits that contain macromodels, simplified circuits, or Verilog-A models. If
subcircuits contain HDL model instances that are Verilog-A, then Eldo can be the circuit
simulator, but if the models instances are Verilog RTL, Verilog-AMS, VHDL, etc., then the
circuit simulator must be Questa ADMS. It is not necessary that subcircuits have high-level
netlists, and no defects will be injected into subcircuits that only have high-level netlists. Every
subcircuit must be in its own file, with .sub suffix, or with .scs suffix if you set spectre_lang on.
If multiple directories are listed, they must not contain duplicate subcircuits.
create_consolidated_modules will automatically store Verilog-A files in this directory with file
extension .va.
The default is mmodels
schematics_directory
One or more directories that contain subcircuits in your CUT that represent the design intent,
typically derived from a schematic typically excluding parasitic elements. In these subcircuits,
any resistors, capacitors, or inductors having values less than parameters R_parasitic,
C_parasitic, or L_parasitic, respectively, are treated as parasitics. It is not necessary that all
subcircuits have design-intent netlists. Every subcircuit must be in its own file or the same
name, with .sub suffix, or with .scs suffix if you set spectre_lang on. If the file is case sensitive,
the case of the filename must match the case of the subcircuit name; if case-insensitive, the
filename must be upper case (except the suffix). If multiple directories are listed, they must not
contain duplicate subcircuits.
The default is schematics
layouts_directory
One or more directories that contain subcircuits in your CUT that are typically extracted
hierarchically from layouts and include layout-extracted parasitic elements.
However, in these subcircuits, any resistors, capacitors, or inductors having values greater than
parameters R_design, C_design, or L_design, respectively, are treated as design-intent. It is not
necessary that all subcircuits have layout netlists. Every subcircuit must be in its own file of the
same name, with .sub suffix, or with .scs suffix if you set spectre_lang on. If the file is case
sensitive, the case of the filename must match the case of the subcircuit name; if case-
insensitive, the filename must be upper case (except the suffix). If multiple directories are listed,
they must not contain duplicate subcircuits.
The default is layouts
flat_layouts_directory
flat_layouts_directory
Directory that contains subcircuits in your CUT typically extracted flat from layouts so that all
cross-coupling parasitic capacitances are included. This directory will be searched by Tessent
DefectSim before searching layouts_directory.
Every subcircuit must be in its own file, with .sub suffix, or with .scs suffix if you set
spectre_lang on. If the file is case sensitive, the case of the filename must match the case of the
subcircuit name; if case-insensitive, the filename must be upper case (except the suffix). If
multiple directories are listed, they must not contain duplicate subcircuits. To minimize
simulation and diagnosis time, it is recommended that you first achieve high coverage using
only mmodels and schematic netlist directories, then add a hierarchical layouts directory, and
lastly add a flat layouts directory.
You may list multiple directories—an error will be reported if there are any duplicate
subcircuits. This allows you to list corporate libraries of subcircuit netlists in addition to a
directory of your design’s subcircuits. If you use this feature, when you use the
create_consolidated_subcircuits command, be sure that the input file includes only your
design’s subcircuits. You may use environmental variables within path names.
Example:
mydesign_subcircuits /corporate_dir/$Process/std_cells
There is no default
include_defectsim_file
You may split a <CUT>.defectsim file into two files, so that one can be a shared project file
with settings for defect likelihoods and defect parameters, and the other can be a circuit-specific
file in the working directory. The file listed for this setting must have suffix .defectsim, and it
may contain settings only for: RL_*, unit_*, [RCL]_*, stuck_*, short_*, open_*,
defect_coverage_*, *_append, defects_only_*, no_defects_*.
If a setting exists in both files, the setting in <CUT>.defectsim will be used—a warning will be
reported that this happened. You may add _append to defects_only_* or no_defects_* settings
in the included file to append values to those in <CUT>.defectsim—a note will be reported to
indicate this happened.
There is no default
custom_models_procedures
This setting enables you to use procedures from an external file in defect model Tcl expressions
and RL calculations.
primitive_libraries
Syntax:
custom_models_procedures <file>
See “Defining Custom Analog Defect Models” on page 161 for details and example file
contents.
primitive_libraries
This setting enables the create_primitive_subcircuits_list command to identify primitive
subcircuits based on the header comment added by the create_consolidated_subcircuits
command.
Syntax:
primitive_libraries <regexp> <regexp> ...
Example:
primitive_libraries pdk_library2
This command would identify the following subcircuit:
“* Subcircuit extracted from /home/process1/pdk_library2/process2/

nand2.scs”
x_primitives_template
This setting allows the create_primitive_subcircuits_list command to select the template used
for each primitive subcircuit based on the name of the subcircuit.
All parts of the syntax are case-insensitive, except the regexp:
x_primitives_template <default_template> \
<template1> <regexp> \
<template2> <regexp2> ...
‘x’ can be one of the following values: R, C, L, D, M, or Q.
Examples:
R_primitives_template DEFECTSIM_IEEE2427HARD_R \
DEFECTSIM_IEEE2427HARD_R1 polyR \
DEFECTSIM_IEEE2427HARD_R2 metalR
C_primitives_template DEFECTSIM_IEEE2427HARD_C
M_primitives_template DEFECTSIM_IEEE2427HARD_M \
custom_template_M HV[np]mos
x_primitive_main_instance
x_primitive_main_instance
This setting allows the create_primitive_subcircuits_list command to identify the primary or
most representative instance within a primitive.
All parts of the syntax are case-insensitive, except the regexp:
x_primitive_main_instance main <regexp> <regexp> ...
‘x’ can be one of the following values: R, C, L, D, M, or Q.
Examples:
R_primitive_main_instance main R1 R_middle

C_primitive_main_instance main C1
M_primitive_main_instance main M[01]
Sampled Outputs and Tested Parameters
Sampled Outputs and Tested Parameters

The following describes the sampled outputs and tested parameters.
sampling_start_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
sampling_activity_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
sampling_activity_start_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
sampling_activity_interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
sampling_interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
simulation_end_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
sampling_threshold_voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
simdefects_start_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
digital_output_signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
digital_output_signals_safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
digital_output_signals_safe_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
test_parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
test_parameters_safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
sampling_start_time
This parameter sets the time at which the first sample of any output signal is captured, compared
to sampling_threshold_voltage, and saved as a binary value. This number should be the earliest
time that digital outputs of your circuit have meaningful, deterministic values (and the earliest
time at which any measurement is performed). It should also be just before the end of a clock
period. For the defect-free circuit, reference values are stored at this time instant; for the
defective circuit, values are compared to reference values at this time instant. You may use
standard SPICE format for time units (p=pico, n=nano, u=micro, m=milli, or scientific
notation). For AC or DC mode simulation, the value must be 0.
The default is 0
sampling_activity_delay
For purposes of measuring activity at a potential defect site, the signal is sampled beginning at
sampling_start_time + sampling activity_delay, and every sampling_interval thereafter. The
best time to sample digital outputs to get a reliable logic value is just before transitions, but the
best time to sample activity is during transitions. This setting allows you to delay the time at
which voltages and currents are sampled, so that activity is maximum at each site.
The default is 0
sampling_activity_start_time
sampling_activity_start_time
For purposes of measuring activity at a potential defect site, the signal is sampled starting at
sampling_start_time + sampling_activity_delay, unless sampling_activity_start_time is defined,
in which case it takes priority. If explicitly set, its value must be greater than
sampling_start_time.
Example: 20n
The default is sampling_start_time + sampling_activity_delay
sampling_activity_interval
For purposes of measuring activity at a potential defect site, the signal is sampled at the end of
every sampling_interval, unless sampling_activity_interval is defined, in which case it takes
priority.
Example: 2.5u
The default is sampling_interval
sampling_interval
This parameter sets the time increment at which samples of digital_output_signals are captured
as binary values, after the sampling_start_time. This number is typically equal to a multiple of a
clock period of your circuit. The number of sampling instants will be approximately equal to 1+
(simulation_end_time - sampling_start_time) /sampling_interval. For the defect-free circuit,
reference values are stored at these time instants; for the defective circuit, values are compared
to reference values at these time instants. You may use standard SPICE format for time units
(p=pico, n=nano, or scientific notation).
The default is (simulation_end_time - sampling_start_time)/10
Note
Choosing a sampling interval much smaller than the signal periods can cause Eldo to skip
sampling instants (as in “Example Complete Testcase” on page 145), leading to incorrect
defect coverage. You can force finer resolution from Eldo by using .OPTION HMAX=t, where
t is less than or equal to your sampling interval divided by 10. In any case, sampling_interval
must be larger than 100 ps.
simulation_end_time
This parameter sets the duration of your transient simulation time. To ensure that the last sample
can be performed, this number must be slightly longer than sampling_start_time plus an integer
sampling_threshold_voltage
multiple of sampling_interval. Also ensure that all parameters are measured prior to
simulation_end_time. You may use standard SPICE format for time units (p=pico, n=nano,
u=micro, m=milli, or scientific notation). For AC or DC mode simulation, the value must be 0.
The default is 1000.0n
sampling_threshold_voltage
This is the voltage that digital_output_signals are compared to, to generate binary values. If two
voltage values are provided, then signal voltages below the first value are captured as logic 0,
voltages between the first and second value are captured as X, and voltages above the second
value are captured as logic 1.You may use standard SPICE format for the voltage units
(u=micro, m=milli, or scientific notation).
If circuit_simulator is AFS, then you may set different voltage threshold pairs for different nets,
using the following syntax:
v0default v1default v0 v1 ( net1 net2 ... ) v0 v1 ( net3 net4 ... ) ....
Examples:
300m 2.7
0.3 0.7 2.0 2.5 (out1 out2) 400m 600m out3
The default is 0.5
simdefects_start_time
Simulation for each defect (and the defect-free circuit) begins at time zero, by default. For some
circuits, when the first measurement or significant digital output value occurs much later than
time zero, the simulation time per defect can be reduced significantly by starting the simulation
of each defect just before the first measurement or digital sample. For safety-related defect
tolerance simulations, often a circuit must tolerate defects injected at t1>0. For both these
scenarios, setting simdefects_start_time to t1 causes the internal voltages of the defect-free
simulation internal voltages to be saved at time t1, and the simulation of each defect to start at
time t1 (initializing nodes to voltages saved from the defect-free circuit). The value must be less
than or equal to sampling_start_time and less than the time at which any measurements occur.
Example: 200n
The default is 0
digital_output_signals
digital_output_signals
These output voltages are sampled, starting at sampling_start_time. They may be signals from
the CUT, or they may be signals from the testbench that are the result of a comparison between
analog parameters (like jitter or linearity) and test limits. All these circuit output signals are
compared to sampling_threshold_voltage to generate binary values. For the defect-free circuit,
only the binary values (0, 1, or X) are stored as reference values; for the defective circuit, only
the binary values are compared to the reference values. Signal names are separated by spaces,
and up to 53 signals may be listed. If you have more than 53 signals to test, then combine them
using combinational logic gates and list the combinational output signals instead. The number
of instants that digital signals will be sampled is equal to 1 + (simulation_end_time –
sampling_start_time) / (sampling_interval). The maximum is 10k. If stop_on_detection is on,
then sampling (and simulation) will stop as soon as all defects are detected.
Example:
out1 out2
There is no default
digital_output_signals_safety
The signals listed for digital_output_signals_safety must be the digital output(s) of any Safety
Mechanism, self-check or self-monitor circuit in the CUT when simulating <CUT>.circuit.
When simulating <CUT>-<SMtest>.circuit, the digital outputs signals must be those of any
second-level Safety Mechanism if there is one and blank if there is not. These signals are
usually a subset of the signals listed for digital_output_signals.
The output of an internal SM, that puts the main Function into a safe state but is not accessible
during test, may be listed in digital_output_signals_safety and not in digital_output_signals. A
change in logic value for any self-monitor output signal, relative to the defect-free simulation, is
interpreted by Tessent DefectSim as the self-monitor detecting a defect (Tessent DefectSim
assumes the signal puts the system into a safe state). Note that this setting will automatically
cause a defectsim_tolerance_summary to be generated, and disable stop_on_detection, which
will likely increase simulation time.
There is no default
digital_output_signals_safe_mode
For cases where a Safety Mechanism's digital output signals switch back and forth between 0
and 1 when the input to it is faulty, use this setting to indicate the logic value for which these
output signals put the system into a safe state. This setting only has an effect when simulating
<CUT>-<SMtest>.circuit and SM_elements is in <CUT>-<SMtest>.defectsim.
test_parameters
During defect simulation of <CUT>.circuit, Tessent DefectSim will only check each listed
signal at times when it has this logic value in the defect-free case. The signals listed must be a
subset of digital_output_signals_safety. If you list a single logic value and no signals, this is the
same as listing this value for all signals.
The syntax is as follows:
digital_output_signals_safe_mode node1 value1 node2 value2 ...
Examples:
digital_output_signals_safe_mode 1
digital_output_signals_safe_mode tristate_enable 0 warning_light 1
There is no default
test_parameters
For this parameter, you provide the labels that you used in EXTRACT/MEAS, ADE
expressions, or Spectre asserts. The results are stored by Eldo in defectsim_outdir/<CUT>.aex.
Each measurement line must provide two limits that are constants (not expressions), and the
UBOUND limit minus the LBOUND limit must produce a positive result. You may EXTRACT
or MEASure any number of parameters but the number listed as test parameters must be less
than 600.
Example: if you had the following in <CUT>.testbench
.extract tran label=Fout

+ wfreq(v(n1),50n,150n)
+ LBOUND=490meg UBOUND=510meg
.four label=FreqResp v(vout) tstart=1u tstop=2u
.extract four label=THD
+ disto(four(FreqResp),2meg, 2meg, 10meg)
+ LBOUND=0 UBOUND=0.5
which measures the average frequency of voltage signal n1 in the time interval 50~150 ns, and
the total harmonic distortion (%) in voltage signal Vout during the time interval 1~2us, then you
could use the following:
test_parameters Fout THD
There is no default
Note
Measurements involving Fourier transforms, or average values without start and end times,
prevent stop_on_detection (AUTOSTOP), which increases simulation time (even if they are
used in your testbench but not in <CUT>.defectsim).
test_parameters_safety
Note
You can use a parameter for LBOUND or UBOUND, but not an expression. If you use an
expression for LBOUND or UBOUND or for min or max of an ADE expression or Spectre
assert, Tessent DefectSim reports “LBOUND/UBOUND not defined” and the measured value
does not appear in the results.
test_parameters_safety
The measurement labels listed for test_parameters_safety are typically different than those for
test_parameters, even if the same parameters are measured, but they may be a subset (a warning
will be issued). Manufacturing test_parameters typically use tighter, guard-banded LBOUND
and UBOUND values to detect more defects, whereas test_parameters_safety should equal the
datasheet-specified limits or safety goals. Note that this setting will automatically disable cause
a defectsim_tolerance_summary to be generated, and stop_on_detection, which will likely
increase simulation time.
There is no default
General Parameters
General Parameters
The following section lists the general parameters.
target_number_defects_to_simulate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
seed_for_random_selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
comment_characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
hierarchy_separator_character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
stop_on_detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
reuse_initial_DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
parallel_simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
include_Func_for_DCLat_simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
eldo_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
analysis_eldo_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
simgood_eldo_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
simdefects_eldo_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
afs_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
analysis_afs_options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
simgood_afs_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
simdefects_afs_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
afs_use_spice_tran . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
questa_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
analysis_questa_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
simgood_questa_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
simdefects_questa_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
defect_coverage_calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
RL_column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
D_column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
number_of_summary_backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
use_questa_to_list_defects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
instance_parameters_in_fault_models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
reuse_sim_files_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
reuse_sim_files_defect_free_high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
reuse_sim_files_defect_free_low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
reuse_sim_files_defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
reuse_sim_files_undetected. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
target_number_defects_to_simulate
force_lowest_level_for_defects_listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
hierarchy_separator_for_XML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
user_defined_good_vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
report_controllability_in_summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
report_observability_in_summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
report_stress_coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
report_activity_coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
report_coverage_per_defect_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
report_csv_with_summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
alternative_defect_insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
insert_defect_in_all_if_clauses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
re_measure_good_circuit_simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
V_observable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
V_observability_ignore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
I_active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Iac_active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
V_active. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Vac_active. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
V_stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
I_stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
connect_node0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PMHF_reference_FIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
simdefects_cptime_per_defect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
target_number_defects_to_simulate
The defects simulated are randomly selected from a list of potential defects, with the likelihood
of the defect being selected for simulation proportional to the relative likelihood of the defect
occurring. The exact number of defects simulated is usually within a few percent of this
number, unless you choose a value that exceeds the number of defects in the list of potential
defects (in which case, all defects in the list are applied), or many defects have the exact same
likelihood, or a few defects have much larger likelihoods than all the other likelihoods. You
may also use “all” (without the quotes).
The default is 10
seed_for_random_selection
seed_for_random_selection
When no value is declared, every run (simulation of all selected defects) of the fault simulator
selects different defects and produces a slightly different estimate of coverage—the true
coverage lies within the 95% confidence interval stated in defectsim_summary, an average of 19
times out of 20 (the 99% confidence interval is equal to 1.3 times the 95% value). The results
always list the actual seed used, even if none was supplied by the user. If you want to rerun the
fault simulation using the same randomly selected faults, then reuse the
seed_for_random_selection from that run. The value may be any positive integer less than 4.2
billion (232).
The default is 123456
comment_characters
All characters that you use in your netlist to indicate comments must be listed here, except *.
Multiple characters may be declared (example: !$). A comment character must be the first
character of a line or else immediately preceded and followed by a space.
Note
Eldo uses * as the default comment character. It is the only character used by Tessent
DefectSim when writing files, and it must not be declared explicitly as a comment character
in this section.
Eldo interprets the * comment character. For example, if the variable, $value, is equal to 100,
then the line:
* original resistance is $value
is interpreted in the defective model as:
* original resistance is 100
Eldo does not interpret any other comment character.
Tip
The # character should not be used as a comment character in this context.
The default is * (and it must not be listed)
hierarchy_separator_character
When reading or appending hierarchical netlists, this character is used between the instance
names of each level in the hierarchy.
stop_on_detection
The default character is .
stop_on_detection
The simulation of each defect stops as soon as any difference between the sampled defective
circuit and the good circuit outputs is detected. Setting this off increases simulation time
(possibly a lot) but allows you to analyze the output defect matrix to reduce test time.
The default is on
reuse_initial_DC
When simulating each defect, the initial DC voltages obtained for the defect-free circuit with
the highest-level models available for each subcircuit are reused for defective subcircuits.
Setting this off might allow simulation of problematic circuits (like oscillators) to converge or
converge faster, but increases simulation time for most circuits. This parameter is automatically
set to off if circuit_simulator questa. Generally, if DC convergence time is more than 5 percent
of simulation time, use the default setting, but otherwise, set it off. In rare cases, the simulation
results (hence coverage) can differ slightly from run to run when this setting is on.
The default is on
parallel_simulation
When simulating defects, this line is inserted in the Eldo file exactly as supplied to perform
parallel simulations on multiple CPU cores. Typically the command may be simply .MPRUN,
which uses all available cores of the present computer node, but you can specify remote
computers or a specific number of CPU cores – please consult the Eldo Reference Manual to see
.MPRUN options.
Example:
.MPRUN ALL
There is no default
include_Func_for_DCLat_simulation
This setting only applies to the functional safety flow. When this is set on, it indicates that the
Function circuitry is or was included while measuring the Diagnostic Coverage w.r.t. Latent
defects (DC-Lat) in the Safety Mechanism (SM) circuitry, only injecting defects in the SM, and
applying a stimulus directly to the SM. When later simulating the Function+SM, and injecting
defects in both, DefectSim will be able to track whether a defect appears as both Latent and
Safe, in which case it will be designated as only Latent.
eldo_options
The default is on
eldo_options
This defines the Eldo options that Tessent DefectSim uses when calling Eldo for any command,
in addition to any analysis, simgood, and simdefects options.
You can use this to add any number of command line options allowed by Eldo, except -i or -eil
or -nochi or use_proc or -auto or -outpath. Any double quotes in any option must be preceded
by a backslash escape: \”
Example:
-case
There is no default
analysis_eldo_options
This defines the Eldo options that Tessent DefectSim uses when calling Eldo for
create_defect_sites_list. You can use this to add any number of command line options allowed
by Eldo, except -eil or -nochi or -premier or -auto or -outpath. Any double quotes in any option
must be preceded by a backslash escape: \"
Example:
-case
There is no default
simgood_eldo_options
This defines the Eldo options that Tessent DefectSim uses when calling Eldo for the
simulate_defect_free command. You may use this to add any number of command line options
allowed by Eldo, such as Premier. Any double quotes in any option must be preceded by a
backslash escape: \"
Example:
-premier
There is no default
simdefects_eldo_options
simdefects_eldo_options
This defines the Eldo options that Tessent DefectSim uses when calling Eldo for the
simulate_defects command. You may use this to add any number of command line options
allowed by Eldo, such as Premier or multi-threading. Any double quotes in any option must be
preceded by a backslash escape: \"
Example:
-premier -use_proc max 2
There is no default
afs_options
This defines AFS options that Tessent DefectSim uses when calling Eldo for any command, in
addition to any analysis, simgood, and simdefects options. You can use this to add any number
of command line options to AFS.
There is no default
analysis_afs_options
This defines AFS options that Tessent DefectSim uses when calling AFS for
create_defect_sites_list. You can use this to add any number of command line options allowed
by AFS.
There is no default
simgood_afs_options
This defines AFS options that Tessent DefectSim uses when calling AFS for the
allowed by AFS.
There is no default
simdefects_afs_options
This defines AFS options that Tessent DefectSim uses when calling AFS for the
allowed by AFS.
There is no default
afs_use_spice_tran
afs_use_spice_tran
This <CUT>.defectsim setting enables the use of HSPICE .tran syntax for the AFS circuit
simulator.
To activate this setting, use:
afs_use_spice_tran on
The default is off.
questa_options
This defines the Questa ADMS options that Tessent DefectSim uses when calling Questa
ADMS for any command, in addition to any analysis, simgood, and simdefects options.
You can use this to add any number of command line options allowed by Questa ADMS.
Typically, you should use at least -topspice option to indicate the name of the top-level SPICE
netlist.
Example:
-topspice mytop
There is no default
analysis_questa_options
This defines Questa ADMS options that Tessent DefectSim uses when calling Questa ADMS
for create_defect_sites_list. You can use this to add any number of command line options
allowed by Questa.
There is no default
simgood_questa_options
for simulate_defect_free. You can use this to add any number of command line options allowed
by Questa.
There is no default
simdefects_questa_options
simdefects_questa_options
for simulate_defects. You can use this to add any number of command line options allowed by
Questa.
There is no default
defect_coverage_calculation
This selects how defects are weighted in the defect coverage calculation. RLweighted_advanced
weights each simulated defect by its RL value when RL>RLthreshold (these defects are always
selected), and otherwise by RLthreshold (these defects are selected randomly).
RLweighted_uniform gives each defect equal weighting so that Tessent DefectSim can
duplicate results from (less precise) classic fault simulators. RLweighted_simple weights every
simulated defect by its RL value, which seems intuitively correct but gives the least accurate
estimate. You should always use the default setting unless benchmarking against old fault
simulators.
Example:
RLweighted_uniform
The default is RLweighted_advanced
RL_column
This sets the column number in which the RL values are displayed in
<CUT>.potential_defects_list such that all RL values are aligned vertically to allow easier
visual inspection. For lines containing more than this number of characters, the RL value is
moved right.
The default is 95
D_column
If the lengths of defect model names differ greatly, such as for preLRL and
pre_source_gate_short, it can be difficult for a person to read defect serial numbers because
they are in widely differing columns. D_column sets the column number for these serial
numbers.
The default value is RL_column+18
number_of_summary_backup
number_of_summary_backup
Each time simulate_defects is run, it generates <CUT>.defectsim_summary. If this filename
already exists, the old file is renamed to <CUT>.defectsim_summary.bak#, where # is
incremented each time, to the maximum set by this parameter.
The default is 9
use_questa_to_list_defects
Setting this on causes Tessent DefectSim to use Questa ADMS to list the circuit elements that
are potential defect sites. By default, Eldo is used, after automatically removing all HDL model
calls (except to VerilogA models), which is faster but not suitable for Verilog-on-top designs.
The default is off unless circuit_simulator is questa.
instance_parameters_in_fault_models
When set to 1, this setting allows you to use the parameters defined by .PARAM (or parameter
in Spectre) within Tcl expressions in UDAFMs by surrounding the parameter name with
“$instance()”. For example, if in your bipolar transistor subcircuit, you have the line .param
bjt_area=5e-12, and you want the subcircuit's RL value to be proportional to bjt_area, then in
the UDAFM you could have $RL = $instance(bjt_area)/1e-12
The default is 1
reuse_sim_files_analysis
Setting this to 1 allows re-running create_defect_site_list without it invoking Eldo or AFS (to
list all subcircuits and their instances). For very large circuits, this can save simulation time.
Default value is 0
reuse_sim_files_defect_free_high
Setting this parameter to 1 allows re-running simulate_defect_free without it invoking Eldo or
AFS. This can avoid a long re-simulation if there was a small error in a Tessent DefectSim file
that would not affect the simulation results (<CUT>.good_results), or if a new version of
simulate_defect_free fixes a parsing error.
The default is 0
reuse_sim_files_defect_free_low
reuse_sim_files_defect_free_low
Setting this parameter to 1 allows re-running simulate_defect_free without it invoking Eldo or
AFS. This can avoid a long re-simulation if there was a small error in a Tessent DefectSim file
that would not affect the simulation results (<CUT>.defect0_results), or if a new version of
simulate_defect_free fixes a parsing error.
The default is 0
reuse_sim_files_defects
Setting this parameter to 1 allows re-running simulate_defects without it invoking Eldo or AFS.
This can avoid a long re-simulation if there was a small error in a Tessent DefectSim file that
would not affect the simulation results (<CUT>.defect_results), or if a new version of
simulate_defects fixes a parsing error.
The default is 0
reuse_sim_files_undetected
Setting this parameter to 1 allows re-running simulate_defects without it invoking Eldo or AFS.
This can avoid a long re-simulation if there was a small error in a Tessent DefectSim file that
would not affect the simulation results (<CUT>.defect_results), or if a new version of
simulate_defects -undetected fixes a parsing error.
The default is 0
force_lowest_level_for_defects_listing
When defects_only_in_instances is used for only a few instances, CUT.potential_defect_list
will still contain potential defects for all instances but with no RL assigned for the excluded
instances.
Setting this parameter off uses the original approach in which Tessent DefectSim uses .BIND to
access the lowest level netlist version for only the selected instances so that the
.potential_defect_list includes only defects from those instances, making the list much shorter
for large circuits but sometimes causing problems.
Default value is on
hierarchy_separator_for_XML
This parameter allows you to change the instance path syntax for defects listed in
<CUT>.defectsim_undetected.xml, <CUT>.defectsim_untolerated.xml, and
<CUT>.defectsim_inactive.xml by simulate_defects. By default, it is the same as in
user_defined_good_vector
<CUT>.defectsim_summary. All instances of the first listed character(s) are replaced by the
second listed character(s), then the very first character of the second-listed character(s) is
prepended to the top-level of the instance path, and lastly, the very first character of the second-
listed character(s) replaces any remaining instances of the very first character of the first
character(s).
Example:
.X_ /
causes
X_abc.X_def.R21
to become
/abc/def/R21
The default is .X /
user_defined_good_vector
Setting this parameter to a filename causes Tessent DefectSim to use the file contents as
expected logic values for digital_output_signals during defect simulations, instead of those in
the default file defectsim_outdir/<CUT>.good_vector.
You can copy the default file to your working directory and then edit it to insert X for any logic
values that are don’t care. The default file in defectsim_outdir is overwritten every time the
simulate_defect_free command is run, and all files in defectsim_outdir are deleted when you
run the delete_generated_files command, so this setting ensures you will not lose any edits you
made. This setting has no effect when the AFS simulator is used—as a workaround when using
AFS, you may edit the logic values at the top of <CUT>.good_results to insert any X, but you
must save a backup of this file since it will be overwritten next time simulate_defect_free -
view_lowest is run.
The default is defectsim_outdir/<CUT>.good_vector
report_controllability_in_summary
Setting this parameter off disables Tessent DefectSim writing a couples lines of diagnostic
information to the <CUT>.defect_summary file for each undetected defect. When on, the
voltage across each simulated defect site is saved at every sampling_interval, for the defect-free
and defect simulations, and a summary of the differences between the voltages is reported in the
summary file. The setting does not affect writing the information in the <CUT>.defect_results.
These voltages are also plotted, in case the plots are not in your .PROBE list, to help you
diagnose why the defects are undetected—when many defects are simulated the list can be long
report_observability_in_summary
and appears at the top of the list of waveforms in EZwave, so you can disable this by setting this
parameter to printfile_only.
The default is printfile_only
report_observability_in_summary
Setting this parameter on enables Tessent DefectSim, for each defect, to compare voltages at
ports of the hierarchy of subcircuits containing a defect, before and after defect insertion.
Starting from the lowest-level subcircuit containing the defect, each subcircuit's port voltages
are monitored, and the lowest-level subcircuit for which no voltages changed by more than
V_observable is noted and its largest voltage delta reported. This helps you to diagnose where
in your design the defect first becomes unobservable.
The default is on
report_stress_coverage
For assessing the quality of burn-in or over-voltage stress test stimuli, stress coverage can be
reported in <CUT>.good_results.
A circuit element is declared stressed when the maximum or average voltage across its nodes, or
current through them, exceeds V_stress or I_stress, respectively. For MOS transistors, the
average Vgs and Vds and maximum Id are monitored, and for bipolar transistors, the average
Vcb and Vce and maximum Ie are monitored. In custom models, $stress_nodes identifies the
node/port for current monitoring, or nodes/ports for voltage monitoring; $stress_statistic
identifies whether maximum or average value is compared to the threshold.
The default is off
report_activity_coverage
Setting this parameter off disables Tessent DefectSim monitoring voltages at all defect sites and
disables reporting in <CUT>.good_results whether each defect site is active or inactive. The
four thresholds for activity are set by I_active, Iac_active, V_active, and Vac_active. The
threshold that is relevant to a specific defect site depends on the circuit element type and the
defect type.
The default is on
report_coverage_per_defect_type
Setting this parameter on causes separate coverages to be reported in the summary for shorts,
opens, variations, and other. 'Shorts' includes preHRL MOS, preHRL diode, postRL diode, and
report_csv_with_summary
postRL capacitors. 'Opens' includes preLRL MOS, preLRL diodes, postRL resistors, and
bipolar opens. 'Variations' includes preLRL and preHRL resistors, capacitors, and inductors.
For custom defect models and defective subcircuit models, the defect type is set using
$defect_type. “Defining Custom Analog Defect Models” on page 161.
The default off
report_csv_with_summary
Setting this on causes simulate_defects to generate two .csv files (comma separated values)
containing results for each defect, and results for the tested parameters. These files can be read
directly by any spreadsheet program. A <CUT>.defectsim_summary.defsum file will also be
generated that can be read using the amsrb command. You can generate these files for a
previous defect simulation by running simulate_defects -summary_only.
The default is off
alternative_defect_insertion
Setting this parameter on causes Eldo to inject defects without using .BIND statements, to avoid
re-elaboration for each defect simulated. This may facilitate faster parallel simulation for large
circuits with short tests whose simulation time is dominated by circuit matrix elaboration time.
This setting has no effect when the AFS simulator is used.
The default is off
insert_defect_in_all_if_clauses
By default, Tessent DefectSim injects defects in all clauses of an if-else statement, including
multi-line clauses.
To disable this behavior, use:
insert_defect_in_all_if_clauses off
The default is on.
Note
This setting does not handle a Spectre netlist in which the element type differs between the
clauses, but the instance name does not.
For example, setting insert_defect_in_all_if_clauses to off would not be effective in the case
where “a2 ... nmos ...” is in the if clause, and “a2 ... resistor ...” is in the else clause.
re_measure_good_circuit_simulation
re_measure_good_circuit_simulation
By default, Tessent DefectSim reruns the defect-free simulation to obtain test limit parameter
values when measurement lines use parameters as bounds, instead of numbers.
To disable this behavior, use:
re_measure_good_circuit_simulation off
The default is on.
V_observable
For purposes of reporting observability, this sets the minimum absolute value of the change in
voltage, at a port of a subcircuit containing a defect, to be declared observable.
Example:
25m
The default value is 100m
V_observability_ignore
For purposes of reporting observability, this sets the minimum absolute value of the change in
voltage, at a port of a subcircuit containing a defect, to be reported as a non-zero change.
Example:
20u
The default is 1m
I_active
For purposes of reporting activity coverage, this sets the minimum absolute value of the current
through a potential defect site to be reported as active in <CUT>.good_results. If the current
through a potential defect site is less than this, the site will be reported as inactive.
The default is 1u
Iac_active
For purposes of reporting activity coverage, this sets the minimum absolute value of the change
in current, from one sample to the next (as set by sampling_interval), through a potential defect
V_active
site to be reported as active in <CUT>.good_results. If the change in current through a potential

defect site is less than this, the site will be reported as inactive.
The default is 0.1u
V_active
For purposes of reporting activity coverage, this sets the minimum absolute value of the voltage
for a potential defect site to be reported as active in <CUT>.good_results. If the voltage across
a potential defect site is less than this, the site will be reported as inactive.
The default is 0.1
Vac_active
For purposes of reporting activity coverage, this sets the minimum absolute value of the change
in voltage, from one sample to the next (as set by sampling_interval), for a potential defect site
to be reported as active in <CUT>.good_results. If the change in voltage across a potential
defect site is less than this, the site will be reported as inactive.
The default is 0.01
V_stress
For purposes of reporting stress coverage, this sets the minimum absolute value of the average,
maximum, rms, or exponential (set by $stress_statistic) voltage across two nodes of a defect site
to be reported as stressed in <CUT>.good_results. You can set a different $stress_scale_factor
in each defect model so that a single V_stress value can be used (e.g., 1).
If the voltage across the nodes is less than this, the site will be reported as unstressed.
Example:
0.5
The default is same value as float_high_voltage
For the exponential stress statistic, T/tBD is calculated and is always compared to 1. T/tBD is
obtained from the classic equation for time-dependent dielectric breakdown (TDDB) time:
where Eox is the oxide field, Xeff is the effective oxide thickness, Vox is the voltage across the
oxide, and G (=350 MV/cm) and τ0=1e-11 are the slope and intercept of the ln(tBD) versus 1/Eox
I_stress
plot, respectively1. If a constant voltage Vox is applied for duration T greater than tBD, the oxide
is predicted to break down. Therefore, if T/tBD >1, breakdown is predicted. To calculate time-
to-breakdown for a varying Vox, Tessent DefectSim integrates that ratio over the simulation
time T.
Tessent DefectSim calculates T/tBD as:
$stress_scale_factor × $sampling_activity_interval × [sum of all exp(-1 × $stress_exponent /

voltage)], so you should set the stress scale factor as 1/ τ0=1E11 multiplied by the intended
stress duration divided by the simulated stress duration (for example, 1/1e-3*1e11=1e14), and
the stress exponent as GXeff volts (>0), e.g. 100. If the value reported exceeds 1, the oxide is
predicted to breakdown. You can adjust the stress scale factor so that V_stress can be a value
different than 1. The value can only increase during the integration interval, which is the
duration of the simulation; if a test actually applies the simulated pattern multiple times, then
V_stress can be scaled down proportionally. TBBD is only pertinent for thin oxides, hence
MOS transistors and capacitors. If you set report_stress_coverage on, and use custom defect or
fault models, but some of them do not contain $stress_nodes, then a NOTE will be reported that
some models are missing stress nodes and they will be listed in <CUT>.no_stress_nodes.
I_stress
For purposes of reporting stress coverage, this sets the minimum absolute value of the average,
maximum, or rms (set by $stress_statistic) current through a node of a defect site to be reported
as stressed in <CUT>.good_results. If the current through the node is less than this, the site will
be reported as unstressed.
Example
10u
The default is same value as I_active
1. Moazzami et al, Temperature Acceleration of Time-Dependent Dielectric Breakdown, IEEE Trans. on

Electron Devices, Nov. 1989.
connect_node0
connect_node0
If a separate <CUT>.testbench and <CUT>.circuit are used, and node 0 is only declared in the
testbench, then Eldo will error out due to no node 0. This can be fixed by adding connect_node0
<n1>.
There is no default
PMHF_reference_FIT
The ISO 26262 probabilistic metric for random hardware failures (PMHF) is based on the value
provided for this parameter. PMHF = [(100%-%SPFM)xRLsum + (100%-%DC-
Lat)xSM_RLsum] × PMHF_reference_FIT.
Example:
1e-12
which means: 1 failure per 1012 hours, if RLSum=1
There is no default
simdefects_cptime_per_defect
In your netlist file, you could set .OPTION CPTIME_PER_RUN=100s to limit the CPU time
for each defect’s simulation to 100 seconds, for example. However, that would also limit the
defect-free simulation time to this value. simdefects_cptime_per_defect sets a CPU time limit
(in seconds) that is applied only during defect simulation. If this CPU time limit is exceeded for
a defect, Eldo will continue to simulate the remaining defects, and the defectsim_summary
defect matrix will show E for that defect to indicate error.
Example:
200
The default value is twice the CPU time of the defect-free simulation (for -view_high or
-view_low) or 60 seconds, whichever is the longest.
Defect Injection Exclusions
Defect Injection Exclusions

All these parameters affect the results of create_defect_sites_list, except where noted.
SM_elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
no_short_defects_between_nodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
no_short_defects_to_node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
no_defects_to_node0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
no_defects_in_subcircuit_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
no_defects_in_subcircuit_instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
no_defects_in_elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
no_defects_in_top_elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
defects_only_in_subcircuit_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
defects_only_in_subcircuit_instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
defects_only_in_elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
R_parasitic_insignificant. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SM_elements
Instance names of subcircuits and circuit elements in a Safety Mechanism (SM). This identifies
the subset of a CUT in which defects are to be injected when running defectsim <CUT>-
<SMtest>simulate_defects while injecting a faulty stimulus at the SM's inputs (over-driving
any signal from the main function). The output file will be
<CUT>-<SMtest>.defectsim_dclat_summary
Any UNIX regular expression (see “Using UNIX Regular Expressions (regexp)” on page 155)
may be used (^[A-Z] if a node starts with a letter, [0-9] is any digit, etc.). Multiple instance
names may be listed separated by spaces; instance names containing any of the expressions are
included—only instance names are searched. Unless using case-sensitive mode, netlist text is
converted to upper case before selection.
Example:
^x[345] ^rsm[1-9]
There is no default
no_short_defects_between_nodes
Pairs of nodes between which no short circuit defect should be injected.
may be used (^[A-Z] if node starts with a letter, [0-9] is any digit, etc.). Multiple nodes may be
no_short_defects_to_node
listed separated by spaces; nodes containing any of the expressions are excluded. Unless using
case-sensitive mode, netlist text is converted to upper case before selection.
Example:
*OUT$ ._IN VDD VSS
There is no default
no_short_defects_to_node
Nodes to which no connected short circuit defect should be injected.
may be used ([^[A-Z] if node starts with a letter, [0-9] is any digit, etc.). Multiple expressions
may be listed separated by spaces; nodes containing any of the expressions are excluded. Unless
using case-sensitive mode, netlist text is converted to upper case before selection.
Example:
*\._AVDD[1-9] AVSS.
There is no default
no_defects_to_node0
In some circuits, node 0 is a special node that does not represent a physical node. In this case,
any resistors, capacitors, or inductors connected to that node should be excluded as potential
defect sites. You may exclude any or all of these elements as potential defects using this
parameter. Valid values are R, C, L, D, any pair of these, or all four. You may insert spaces
between the letters but they are not essential. If you use node 0 as your ground or VSS node,
then you should use the default blank setting.
Example:
RC
There is no default
no_defects_in_subcircuit_names
When injecting defects, all instances of subcircuits with these names, and within contained
subcircuits, are excluded as candidate locations.
may be used. ([^[A-Z] if node starts with a letter, [0-9] is any digit, etc.). Multiple expressions
no_defects_in_subcircuit_instances
may be listed separated by spaces; names containing any of the expressions are excluded.
Unless using case-sensitive mode, netlist text is converted to upper case before selection.
Example:
^NAND.$ NOR[3-9]
There is no default
no_defects_in_subcircuit_instances
When injecting defects, all these instances of subcircuits are excluded as candidate locations.
Instances may include hierarchy. Any UNIX regular expression (see “Using UNIX Regular
Expressions (regexp)” on page 155) may be used ([^[A-Z] if node starts with a letter, [0-9] is
any digit, etc.). Multiple expressions may be listed separated by spaces; instances containing
any of the expressions are excluded. Unless using case-sensitive mode, netlist text is converted
to upper case before selection. Note that excluding defects in “X1” (by writing ^X1$) does not
exclude defects in its subcircuits—if you want to exclude those too, then also write ^X1\..*
Example:
^X1$ X3\.X[3-9]
There is no default
no_defects_in_elements
This only affects the results of create_defects_to_simulate. When selecting defects for
simulation, any lines in <CUT>.potential_defect_list containing this text are ignored as
candidates for <CUT>.sim_defect_list.
may be used. Multiple expressions may be listed separated by spaces; lines containing any of
the expressions are ignored. Expressions are case-sensitive.
Example:
^R.*DUMMY (top-level dummy resistors)
Example:
pre[LH]RL= (pre-layout elements)
There is no default
no_defects_in_top_elements
no_defects_in_top_elements
In some cases, the circuit-under-test is surrounded by top-level circuit elements that comprise a
testbench, and when the testbench is changed, <CUT>.potential_defect_list changes and
prevents create_combined_summary from combining the results for the testbenches. When
injecting defects, instances of top-level elements with these names are excluded.
may be listed separated by spaces; names containing any of the expressions are included. Unless
There is no default
defects_only_in_subcircuit_names
When injecting defects, instances of subcircuits with these names, and within contained
subcircuits, are included as candidate locations.
may be listed separated by spaces; names containing any of the expressions are included. Unless
Example:
^NAND.$ NOR[3-9]
There is no default
defects_only_in_subcircuit_instances
When injecting defects, only these instances of subcircuits are included as candidate locations.
Instances may include hierarchy. Any UNIX regular expression (see “Using UNIX Regular
Expressions (regexp)” on page 155) may be used ([^[A-Z] if node starts with a letter, [0-9] is
any digit, etc.). Multiple expressions may be listed separated by spaces; instances containing
any of the expressions are included. Unless using case-sensitive mode, netlist text is converted
to upper case before selection. Note that choosing defects in only “X1” (by writing ^X1$) does
not include defects in its subcircuits - if you want to include those too, then also write ^X1\.
Example:
^X2\. X[468]$
There is no default
defects_only_in_elements
defects_only_in_elements
This only affects the results of create_defects_to_simulate.
When selecting defects for simulation, any lines in <CUT>.potential_defect_list that do not
contain this text are ignored as candidates for <CUT>.sim_defect_list. Any UNIX regular
expression (see “Using UNIX Regular Expressions (regexp)” on page 155) may be used.
Multiple expressions may be listed separated by spaces; lines containing any of the expressions
are sampled. Expressions are case-sensitive.
Example:
layer=via
There is no default
R_parasitic_insignificant
When a numeric resistance value is supplied for this, all resistances less than this value are set to
zero by create_defect_site_list and create_defects_to_simulate. When most netlists have layout-
extracted netlists, this setting typically allows defect and defect-free (-view_lowest) simulations
to run 2~8X faster because zero-value resistances are eliminated by Eldo, which reduces the
netlist size (in some cases the size becomes similar to the schematic netlist). To ensure that
simulation accuracy is not affected significantly, you should compare results for default and
R_parasitic_insignificant 10, and if accuracy is noticeably affected reduce the value by 2X.
Always re-run create_defect_site_list and create_defects_to_simulate after changing the setting.
The setting affects only the lowest view (even if it is schematic), and only affects resistances
that appear as numbers in the subcircuit; resistances that are parameters or appear as L= and W=
will not be affected (we may address these in a future release). An alternative approach is to use
Eldo’s .TICER command that ensures accuracy up to a target frequency but may not reduce
simulation time as much.
The default is 0
Basic Defect Values
Basic Defect Values

All these parameters affect the results of create_defects_to_simulate.
float_high_voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
float_low_voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
stuck_on_defect_resistance_LW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
short_defect_resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
open_defect_resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
open_defect_R_ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
float_high_voltage
When an open circuit defect resistor is inserted, a weak pull-up resistance to this voltage is also
inserted.
The default is 1
float_low_voltage
When an open circuit defect resistor is inserted, a weak pull-down resistance to this voltage is
also inserted.
The default is 0
stuck_on_defect_resistance_LW
Resistance, in ohms, that is applied between the source and drain of a stuck-on MOS transistor
having length/width = 1, for the model specified, for the default defect model. The resistance
value is multiplied by L/W of the defective transistor.
You must provide a default value, and then you may provide values for specific transistor
models, for example one for PMOS and one for NMOS (that you obtain from simulation). See
“Measuring Typical Stuck-on Resistance for L=W” on page 159. You may provide any number
of resistance model pairs. You may use standard SPICE format for time units (k=kilo, or
scientific notation).
Example:
stuck_on_defect_resistance_LW 5000 \
2200 NMOS_VLT \
3500 PMOS_VLT \
7500 XMOS
The default is 1000
short_defect_resistance
There is no default model
short_defect_resistance
Resistance that is applied across a capacitance as a short circuit defect for the default defect
model. You may use standard SPICE format for time units (k=kilo, or scientific notation).
The default is 10
open_defect_resistance
For the default defect model, the resistance that is inserted in series with a resistor or inductor as
an open circuit defect is open_defect_R_ratio times this value, and the resistance to the
float_high/low_voltage is equal this value. You may use standard SPICE format for time units
(meg=mega, g=giga, or scientific notation).
The default is 1G
open_defect_R_ratio
For the default defect model, when an open circuit defect resistor is inserted, the resistance of
the inserted weak pull-up or pull-down resistance (randomly selected) has this ratio to the
inserted open_defect_resistance.
The default is 10
Pre- and Post-Layout Parameters
Pre- and Post-Layout Parameters

All these parameters affect the results of create_defect_sites_list.
always_add_default_defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
merge_parallel_elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
merge_parallel_primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
merge_parallel_subcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
C_parasitic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
C_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
C_defect_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
C_defect_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
C_defect_X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
R_parasitic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
R_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
R_defect_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
R_defect_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
R_defect_X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
L_parasitic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
L_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
L_defect_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
L_defect_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
L_defect_X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
always_add_default_defects
When user-defined analog defect models (UDADMs) are provided, Tessent DefectSim will still
list default models for preLRL, preHRL, and postRL, unless UDADMs are provided for those
defect names too. For circuit elements that have user-defined models, to use only those models
and not any default models, set this parameter off.
The default is on
merge_parallel_elements
This merges parallel identical instances of circuit elements. This is useful when a schematic
contains multiple instances in parallel, instead of using M>1, and you want the defect model to
be based on the total number in parallel since an open in 1 of 10 transistors in parallel would be
indistinguishable from a 10% process variation.
merge_parallel_primitives
The parallel instances must be on consecutive lines in a subcircuit netlist, or use instance[n:m]
syntax (Eldo has the same requirement when it merges elements to reduce simulation time). The
changes are done in only <CUT>.CELLS_HIGHEST_NETLISTS and
<CUT>.CELLS_LOWEST_NETLISTS so that the original .sub or .scs files are not changed.
The default is on
merge_parallel_primitives
This merges parallel identical instances of primitive subcircuits.
This is useful when a schematic contains multiple instances in parallel, instead of using M>1,
and you want the fault model to be based on the total number in parallel since an open in 1 of 10
transistors in parallel would be indistinguishable from a 10% process variation. The subcircuits
must be in the list of primitive_subcircuits. The parallel instances must be on consecutive lines
in a subcircuit netlist, or use instance[n:m] syntax (Eldo has the same requirement when it
merges elements to reduce simulation time). The changes are done only in
<CUT>.CELLS_HIGHEST_NETLISTS and <CUT>.CELLS_LOWEST_NETLISTS so that the
original .sub or .scs files are not changed.
The default is on
merge_parallel_subcircuits
This merges parallel identical instances of non-primitive subcircuits.
This is useful when a schematic contains multiple instances in parallel, instead of using M>1,
and you want a defect to be injected in all of the instances. The subcircuits must not be in the list
of primitive_subcircuits. The parallel instances must be on consecutive lines in a subcircuit
netlist, or use instance[n:m] syntax (Eldo has the same requirement when it merges elements to
reduce simulation time). The changes are done only in <CUT>.CELLS_HIGHEST_NETLISTS
and <CUT>.CELLS_LOWEST_NETLISTS so that the original .sub or .scs files are not changed.
The default is on
C_parasitic
When a netlist in the schematic_directory is used, all resistors, capacitors, and inductors (RCL)
are assumed to be design-intent.
However, RCL values less than R_parasitic, C_parasitic, or L_parasitic are considered as
parasitic which means the potential defect is an open (in resistor or inductor) or short (across
capacitor), whereas the potential defect for larger values is a variation as specified by
R_defect_L/H, C_defect_L/H, or L_defect_L/H. You may use standard SPICE format for time
units (f=femto, p=pico, n=nano, or scientific notation).
C_design
The default is 0 (all schematic RCL are assumed design-intent)
C_design
When a netlist in the layouts_directory is used, all RCL values are assumed to be parasitic.
However, RCL values larger than R_design, C_design, or L_design are considered design-
intent, which means the potential defect is a variation as specified by R_defect_L/H,
C_defect_L/H, or L_defect_L/H, whereas the potential defect for smaller capacitances is a short
circuit. You may use standard SPICE format for time units (f=femto, p=pico, n=nano, or
scientific notation).
The default is 1e+12 (all layout RCL are assumed parasitic)
C_defect_H
When a netlist in the schematics_directory is used, all RCL are assumed to be design-intent. A
defective RCL value is higher by this percentage.
The default is 50. The permitted range is 0 to 10000
C_defect_L
defective RCL value is lower by this percentage.
C_defect_X
This value can be used in any custom defect model that is defined in the file named by
custom_defect_models, and in any custom primitive subcircuit fault model that is defined in file
named by primitive_subcircuits. 'X' can be any letter.
There is no default
R_parasitic
See “C_parasitic” on page 73.
R_design
R_design
See “C_design” on page 74.
R_defect_H
See “C_defect_H” on page 74.
R_defect_L
See “C_defect_L” on page 74.
R_defect_X
There is no default
L_parasitic
See “C_parasitic” on page 73.
L_design
See “C_design” on page 74.
L_defect_H
L_defect_H
L_defect_L
L_defect_X
There is no default
Pre-Layout Relative Likelihood (RL)
Pre-Layout Relative Likelihood (RL)

RL_transistor_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
RL_transistor_min. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
RL_capacitance_max. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
RL_capacitance_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
RL_resistance_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
RL_resistance_min . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
RL_inductance_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
RL_inductance_min. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
RL_transistor_stuck_on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
RL_transistor_stuck_off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
RL_xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
unit_RL_M_design_LW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
RL_resistance_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
RL_resistance_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
unit_RL_R_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
R_leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
RL_capacitance_H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
RL_capacitance_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
unit_RL_C_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
RL_inductance_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
RL_inductance_L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
unit_RL_L_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
RL_diode_short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
RL_diode_open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
RL_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
RL_bipolar_base_open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
RL_bipolar_emitter_open. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
fpitch_default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
tfin_default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
RL_transistor_max
RL_transistor_max
Maximum value for RL. This also applies to user-defined defects, but not to user-defined faults
(subcircuits). This reflects the fact that defects have a maximum size above which they are
extremely unlikely.
The default is 100
RL_transistor_min
Minimum value for RL. This also applies to user-defined defects, but not to user-defined faults
(subcircuits). This reflects the fact that defects whose size is less than the technology minimum
dimension will not cause a short or open.
The default is 0.01
RL_capacitance_max
extremely unlikely.
Default value is 100
RL_capacitance_min
Default value is 0.01
RL_resistance_max
extremely unlikely.
RL_resistance_min
RL_resistance_min
RL_inductance_max
extremely unlikely.
RL_inductance_min
RL_transistor_stuck_on
For the default defect model, the RL that a transistor (n-channel or p-channel MOS) is stuck on.
The default is 1.0
RL_transistor_stuck_off
For the default defect model, the RL that a transistor (n-channel or p-channel MOS) is stuck off.
The default is 1.0
RL_xx
named by primitive_subcircuits. 'xx' can be a combination of any letters, digits, or _. It must be
set to a numeric value.
unit_RL_M_design_LW
Example:
RL_gate2drain_short 2.3
There is no default value
unit_RL_M_design_LW
For the default defect model, this is the gate length times width (i.e., gate area) of a transistor
whose RL of being stuck on/off is RL_transistor_stuck_on/off; RL is proportional to gate length
multiplied by width. If 0, this parameter is ignored, and the RL equals RL_transistor_stuck_on
or off.
The default is 1e-12
RL_resistance_H
For the default defect model, the RL that a defect causes the resistance/capacitance/inductance
of a designed element to vary too high.
The default is 1.0
RL_resistance_L
of a designed element to vary too low.
The default is 1.0
unit_RL_R_design
For the default defect model, this is the designed resistance whose RL of being too high or low
is RL_resistance_H or L; RL is proportional to resistance. If 0, this parameter is ignored, and
the RL for designed resistors equals RL_resistance_H or L.
The default is 1k
R_leakage
Subcircuits sometimes contain high resistances to model field oxide leakage or to improve DC
convergence, and they are not potential sites for an open circuit. Any resistors that have a
resistance greater than R_leakage have RL=0.000. For exceptions, you can find these in
<CUT>.potential_defect_list and change them to non-zero values.
The default is 1e10
RL_capacitance_H
RL_capacitance_H
The default is 1.0
RL_capacitance_L
The default is 1.0
unit_RL_C_design
For the default defect model, this is the designed capacitance whose RL of being too high or low
is RL_capacitance_H or L; RL is proportional to capacitance. If 0, this parameter is ignored,
and the RL for designed capacitors equals RL_capacitance_H or L.
The default is 10f
RL_inductance_H
The default is 1.0
RL_inductance_L
The default is 1.0
unit_RL_L_design
For the default defect model, this is the designed inductance whose RL of being too high or low
is RL_inductance_H or L; RL is proportional to inductance. If 0, this parameter is ignored, and
the RL for designed inductors equals RL_inductance_H or L.
RL_diode_short
RL_diode_short
For the default defect model, the RL that a defect causes a diode to be short-circuited. The
resistance of the short is the short_defect_resistance and is applied to pre-layout and post-layout
netlists. This affects preHRL and postRL for diodes.
The default is RL_shorts_default
RL_diode_open
For the default defect model, the RL that an open defect occurs in a diode. The resistance of the
open is the open_defect_resistance and is applied only to pre-layout netlists (since a layout
contains a contact to the diode, and the contact is already subject to open defects). This affects
preLRL for diodes.
The default is RL_opens_default
RL_model
The RL for each element can be model dependent. This allows you to indicate that different
types of NMOS transistors, or different types of resistors, for instance, have different defect
likelihoods. You can also set the RL to zero for some elements using this parameter. The RL for
the element is multiplied by the value provided.
Example:
RL_model NMOS_VLT 1.5 \

PMOS_VLT 0.7 \
R_poly 8 \
C_peri 0
There is no default value (in effect, it is 1.0 for all models)
RL_bipolar_base_open
For the default defect model, the RL that the connection to the base of a bipolar transistor will
be open. This affects preHRL for bipolar transistors.
The default is 0.1
RL_bipolar_emitter_open
For the default defect model, the RL that the connection to the emitter of a bipolar transistor will
be open. This affects postLRL for bipolar transistors.
The default is 0.1
fpitch_default
fpitch_default
The formula for calculating the width of any finFET listed in the <CUT>.potential_defect_list
file is:
(((NFIN-1) × FPITCH) + TFIN) × NF
In the case where the finFET transistor default FPITCH value is not already set, use the
following command:
fpitch value
The default is 50n.
tfin_default
The formula for calculating the width of any finFET listed in the <CUT>.potential_defect_list
file is:
(((NFIN-1) × FPITCH) + TFIN) × NF
In the case where the finFET transistor default TFIN value is not already set, use the following
command:
tfin value
The default is 5n.
Post-Layout Relative Likelihood (RL)
Post-Layout Relative Likelihood (RL)

RL_opens_default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
RL_R_parasitic_redundant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
RL_shorts_default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
unit_RL_R_parasitic_LW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
unit_RL_C_parasitic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
unit_RL_R_parasitic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
unit_RL_L_parasitic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
RL_opens_default
For the default defect model, this RL is applied to all parasitic resistors for which no length/
width dimensions are provided. You should set this value relative to RL_shorts_default and
unit_RL_C_parasitic.
The default is 0.1
RL_R_parasitic_redundant
For the default defect model, this sets the RL used by create_defect_sites_list
-treat_parallel_resistors_as_redundant for all resistors that are in parallel with others in the same
layout subcircuit’s netlist to allow you to reduce or eliminate the likelihood of simulating open
defects in redundant paths. Some duplicate contacts or vias are not redundant because they
decrease voltage drop significantly; to increase the likelihood of simulating these cases, leave
the parameter undefined.
Example:
0.001
There is no default value
RL_shorts_default
For the default defect model, this RL is applied to parasitic capacitances. For most nanometer
CMOS technology nodes, the likelihood of opens is less than the likelihood of shorts, so you
should set this value relative to RL_opens_default.
The default is 0.2
unit_RL_R_parasitic_LW
For the default defect model, this is the length divided by width of a parasitic resistor whose RL
of an open equals 1. This parameter should be repeated for all layers (for example, poly, metal1,
contact). Provide a first value with no layer, as a default.
Example:
1.2 0.5 poly 1.5 metal1
The default is 1.0
unit_RL_C_parasitic
For the default defect model, this is the parasitic coupling capacitance whose RL of a bridging
short between its nodes is RL_shorts_default. You should choose a value that centers the range
of RL values around 1 to prevent RL for defects becoming so small that they can never be
simulated. Adjust it if you get warnings that an RL value is unusually high or you observe too
many minimum values (.001). You may use standard SPICE format for time units (f=femto,
p=pico, or scientific notation).
The default is 10f
unit_RL_R_parasitic
For the default defect model, this is the parasitic resistance whose RL of an open circuit is
RL_opens_default; RL is proportional to resistance. If 0, this parameter is ignored, and the RL
for parasitic resistors is proportional to the resistor’s length divided by width if known, else it
equals RL_opens_default.
The default is 1k
unit_RL_L_parasitic
For the default defect model, this is the parasitic inductance whose RL of an open circuit is
RL_opens_default; RL is proportional to inductance. If 0, this parameter is ignored, and RL for
parasitic inductors equals RL_opens_default.
unit_RL_L_parasitic
Chapter 4
Step 2 - Prepare Top-Level, Subcircuit, and
Module Directories
Run the create_consolidated_subcircuits command to search through the listed file of

concatenated subcircuits, extracting and creating an individual .sub file for each subcircuit, in
the relevant directory listed in <CUT>.defectsim, in the format required by Tessent DefectSim.
You should run this command for your top-level file to ensure all required subcircuits are
collected, but you may run it on other files. Unless you use the -create_all_files option, this
command also creates the file notSubckts.defectsim that contains all lines from the input file that
were not found within subcircuit netlists.
The options -mmodels -schematics, -layouts, and -flat_layouts indicate the type of directory that
subcircuit files will be copied to, with the name of the directory specified in <CUT>.defectsim
(the directory will be created if it does not exist).
The option -create_all_files generates <CUT>.circuit and initial.process files instead of

notSubckts.defectsim and adds lines to <CUT>.defectsim if appropriate; alternative file names
may be specified by top_circuit_suffix and process_file settings in <CUT>.defectsim. If you
also use the option -separate_testbench, then <CUT>.testbench will be created containing
voltage/current sources and EXTRACT/MEAS lines that would otherwise be placed in
<CUT>.circuit.
The option -no_comments omits comment lines in the created files, which often makes the files
easier to read.
create_consolidated_subcircuits
{ -output_directory <output_directory> | -layouts | -schematics | -mmodels }
[ -overwrite | { -input_files <input_files> }
[ -create_all_files [ -separate_testbench ] [ -no_comments ] ]
[ -force_overwrite ]
[ -top_level_only ] ]
• Required input file

o <CUT>.defectsim
o file (must be in working directory)
• Output files (in mmodels_directory, schematics_directory, layouts_directory, or
flat_layouts_directory)
o <subcircuitname>.sub
o notSubckts.defectsim (in current directory, unless -create_all_files is used)
Step 2 - Prepare Top-Level, Subcircuit, and Module Directories
o <CUT>.global_signals (in current directory, unless -create_all_files is used)

The files produced by this command are in the format required by subsequent Steps:
• <CUT>.circuit will contain the original .TRAN/tran line with start, step, and stop
values replaced by parameters that Tessent DefectSim will set according to the values in
<CUT>.defectsim.
• Each subcircuit is contained within one file named <SUBCIRCUIT>.sub where
<SUBCIRCUT> is the upper-case name of the contained subcircuit (may be mixed-case
within the file). If Eldo will be run in case-sensitive mode, then SUBCIRCUIT should
use the same case as within the file.
• Each <SUBCIRCUIT>.sub contains only one subcircuit, with no .INCLUDE lines – if
there were any, they are expanded.
• A subcircuit calls other subcircuits only if they are in one of the three directories.
directory_type is one of mmodels, schematics, layouts, or flat_layouts
<CUT>.global_signals contains all .GLOBAL signals found in the files, without duplicates.
If a file with .sub suffix already exists in the target directory, the new version is created with
suffix .sub_temporary. Rerun the command with -overwrite instead of -input to force all files
with .sub_temporary suffix to overwrite all corresponding files with .sub suffix.
When create_defect_sites_list is run later, the port signal order of the highest-level available
netlist is inserted in the subcircuits in <CUT>.CELLS_LOWEST_LEVEL_NETLISTS and in
<CUT>.CELLS DEFECTIVE_NETLISTS.
This command resolves lines in your netlist or subcircuits containing .INCLUDE fname by
fetching the contents of file fname and inserting them into the created .sub file. Similarly, the
command resolves lines containing .LIB fname or .LIB fname libtype by fetching the contents
of the called library file or library file section, respectively. Any lines in the input file, files
called by .LIB , and files called by .INCLUDE, that are not in subcircuits, are written to the file
notSubckts.defectsim for you to put in the process, testbench or circuit files. .ADDLIB directory
is not recognized—you can concatenate the directory’s contents (or a subset) into a single file,
then run create_consolidated_subcircuits on that file.
If spectre_lang is on, then created subcircuit files will be given .scs suffix instead of .sub.
If some of the subcircuits have equivalent hardware description language (HDL) modules, in
addition to schematic and/or layout netlists, run the create_consolidate_modules command to
copy all modules into appropriate local directories and to create subcircuit wrappers that
instantiate them so that the modules will be used when the defect being simulated is not in that
subcircuit.
create_consolidated_modules –input file [-force_overwrite]
Usage Notes
• file contains one or more modules. Lines in it with ìnclude “file” are recognized and
searched if the file is found, otherwise ignored (but noted).
The HDL modules will be automatically put into files in modules_directory,
gatemodules_directory, or mmodels_directory (as defined in <CUT>.defectsim), one module
per file of the same name with an appropriate suffix, according to the following rules:
• mmodels_directory if HDL is Verilog-A (all model lines are within analog begin; end);
• gatemodules_directory if HDL is not Verilog-A, and there is a `celldefine wrapper;
• modules_directory for all other modules.
• An appropriate file suffix will be added (.v, .va, .vhd).
• No module name can be used in more than one of these directories.
• A subcircuit file (containing only an instance of the module) in SPICE, or Spectre
syntax if spectre_lang on, will be created in mmodels_directory for every HDL module,
so that they can be used by simulate_defect_free -view_highest, and so that schematic,
layout, or defective subcircuits can be substituted (if they exist) by simulate_defect_free
-view_lowest and simulate_defects.
• If all HDL modules are Verilog-A, then in <CUT>.defectsim you may set
circuit_simulator eldo.
• If any modules are Verilog or Verilog-AMS, you must set circuit_simulator questa.
No compile is needed for Verilog-A modules, but before running Tessent DefectSim, all other
HDL modules must be compiled using, for example,
valog modules_directory/*.va
vlog modules_directory/*.v
valog gatemodules_directory/*.va
vlog gatemodules_directory/*.v
valog mmodels_directory/*.va
Usage Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Subcircuit Directories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Circuit-Under-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Simulation Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Process Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Usage Notes
The following usage notes apply:
• You should always use -create_all_files unless you only want to update the directory of
subcircuits.
Usage Notes
• Text lines in notSubckts.defectsim should be copied into <CUT>.testbench,

<CUT>.circuit, and/or process_file, as appropriate.
• If you modify the contents of any library files that are called by subcircuits, you must re-
run create_consolidated_subcircuits to regenerate the .sub files so that the library
contents are copied again into those files.
• When you use -create_all_files, the values found in any .TRAN or tran lines are
automatically copied into relevant settings in <CUT>.defectsim.
Subcircuit Directories
Subcircuit Directories
You declare directory names in the <CUT>.defectsim configuration file.
This file is described in “Step 1 - Create .defectsim Control File” on page 27; any of the
directories may be empty:
• schematics directory — All pre-layout subcircuit netlists, typically generated from

schematics or generated by manual editing – elements are assumed to be design-intent.
• mmodels directory — Contains the following:
o Higher-level versions of subcircuits in your CUT. These must be subcircuits but may
contain Eldo macromodels, simplified circuits, or Verilog-A behavioral models, to
accelerate simulation, that can be substituted on-the-fly for subcircuits that do not
contain the defect being simulated. These higher-level models should include input
capacitance, delay, and output resistance. If you are using Questa ADMS, you may
also use Verilog/VHDL RTL models.
o No defects are injected into these higher-level subcircuit netlists, even if they
contain transistors or RCL elements (resistor, capacitor, or inductor).
• layouts and flat_layouts directories — Contains the following:
o Layout-extracted netlists of your CUT and/or subcircuits in your CUT. The netlists
should include parasitic resistances (preferably with length, width, and layer, as
comments) and coupling capacitances, extracted from the layout using ‘coupled RC’
mode; do not use ‘decoupled’ mode (which replaces all coupling capacitances with
equivalent capacitances to node 0, thus they would wrongly be considered as
potential shorts to node 0) nor ‘coupled C only’ mode.
o You should not lump series parasitic resistances or parallel coupling capacitors
during parasitic extraction (see Figure 4-1), because these provide useful
information about all potential opens and shorts. The random defect selection
algorithm in the Tessent DefectSim tool does not assign defects to all locations, but
the longer a connection, the more parasitics it has, and the more likely that a defect
in it is selected for simulation.
Figure 4-1. Parasitic Extraction
Subcircuit File Requirements
Caution
A flat-extracted netlist prevents substituting schematic or high-level models that
reduce simulation time, whereas a purely hierarchical netlist permits substituting
higher-level netlists to accelerate simulation but does not include all coupling
capacitances (which indicate potential shorts). You should extract a hierarchical
netlist initially to determine defect coverage more quickly. When coverage exceeds
95%, then you could use a flatter netlist in a flat_layouts directory to verify coverage
of additional coupling defects.
Here is a quick guide to using Calibre to extract the netlist (from the Calibre xRC User’s
Manual), after you have opened the Calibre GUI:
1. Specifying Inputs
a. Click on Layout tab to provide layout filename, type, and so on.
b. Click on Netlist tab to provide schematic filename, top cell in that file, and so on.
c. Click on H-cells/X-cells to optionally provide a list of cells to be extracted flat
2. Specifying Outputs
a. Choose extraction mode xRC
b. Choose extraction level — click Hierarchical
c. Choose extraction type — click R+C+CC
d. Consider inductance option only if you are working with very high frequencies
e. Click the Netlist tab
i. From the drop-down list, choose Eldo as the output format
ii. For the source for net and instance names, choose Schematic
iii. Provide the PEX netlist filename that you want
f. Click the Reports tab
i. Specify an LVS Report filename that you want (so schematic names used)
3. Run PEX
Subcircuit File Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

The following list identifies the subcircuit file requirements.
Each subcircuit in each of the three directories must be in a separate file, there must not be any
.INCLUDE statements, and the file suffix must be “.sub” or “.scs”. A subcircuit reference may
call a subcircuit in any of the three directories. Subcircuits may be nested, but the internal
subcircuits can only be used within that top subcircuit.
Note
Important: The port node signal names must be the same in all versions of the subcircuit,
i.e., the mmodel, the schematic-derived netlist, the layout-extracted netlist, and the HDL
module. Differences could cause tests to fail in simulate_defect_free which prevents you from
running simulate_defects (since it would falsely report all defects detected).
• The command create_consolidated_subcircuits (described in “Step 2 - Prepare Top-

Level, Subcircuit, and Module Directories” on page 87) should be used to automatically
generate the contents of the four directories of subcircuit netlists so that they meet the
requirements stated above.
• If any subcircuits include circuit elements that are not potential defect sites, then you can
add a suffix to each such instance name, such as “_no_defects” so that you can later
exclude those elements from defect injection. For example, the netlist of a resistor cell
might include a parasitic capacitance to substrate, to which a short is almost impossible;
the capacitor line should be edited so it becomes C1_no_defects n1 n2 1pF, then in
your <CUT>.defectsim file, include the line no_defects_in_elements no_defects.
• The Eldo version. To run the Tessent DefectSim tool, the environment variable
MGC_AMS_HOME must be defined as a path to the Mentor Graphics AMS software,
as normally done when preparing to use eldo. It must point to version 2019.2 or later.
Eldo must be in the bin directory of the directory identified by MGC_AMS_HOME.
Example Subcircuit Files Using Eldo/Spice

myschematics directory contents
INV.sub
.subckt inv out in vdd vss * pin order in mmodels will be used
m1 vdd in out vdd pmos W=10n L=0.5n
m2 vss in out vss nmos 0.5n 10n * if no W/L= shown, first number is L
.ends
CAP.sub
.subckt cap top bottom substrate
c1 top bottom 1p * design-intent - defect will be a variation
r1 bottom substrate 10G * ignored if .defectsim contains R_leakage 1e-9
c2 bottom substrate 1f * parasitic - defect will be a short
.ends
mymmodels directory contents
INV.sub
.subckt inv in out vdd vss
inv3 in out vhi=2.5 vth=1.25 tpd=0.5n cin=100f * ideal inverter
.ends
Example Files Using Verilog-A for Eldo or Questa ADMS

myModules.va contents
ìnclude "disciplines.vams"
module resistor(n1, n2);
inout n1, n2;
electrical n1, n2;
branch(n1,n2) res;
parameter real P=1;
analog begin
I(res) <+ V(res)/P;
end
endmodule
process file contents
.option vaopts="-nocheck" Example of how to supply options to be used by Verilog-A compiler

.verilog myModules.va Points to a file containing Verilog-A modules, to be compiled for Eldo
or
.hdl myModules Points to a file containing Verilog-A modules; default suffix is .va
Eldo searches path provided, or searches path given by -hdlpath in Eldo call
.model resistor macro lang=veriloga Declares a model (i.e., group of defined parameters)
.model resist50 macro lang=veriloga mod=resistor P=50 A model based on a model
in myschematics directory
.subckt myresistor node1 node5

Rabc1 node1 node2 50
.ends
in mymmodels directory
.subckt myresistor node1 node5

Yabc1 resistor node1 node2 param: P=50 * Instantiates an HDL module
Yabc2 resist50 node2 node3 * Instantiates an HDL module
Xabc3 node3 node4 resistor P=50 * May instantiate a Verilog-A module
.ends
Example Files Using Verilog/VHDL Models Only for Questa ADMS

Caution
The top level of your netlist hierarchy must be in Eldo, HSpice, or Spectre format.
<CUT>.defectsim file contents
schematics_directory schematics The usual lines, when using Eldo

...
circuit_simulator questa Special line to invoke Questa ADMS instead of Eldo
(it is commented out in the example file supplied)
Files named <CELL>.sub or <cell>.sub in the directories listed in your .defectsim file must be
SPICE subcircuits. Files that contain only HDL syntax must use suffix .a, .va, or .vhd.
mmodels/logic.v contents
`timescale 100ps/10ps Eldo updates digital values based on timescale

module DFFR_X1 (CK, D, RN, Q, QN, VDD, VSS);
input CK, D, RN, VDD, VSS;
output Q, QN;
reg Q;
always @(posedge CK or negedge RN) begin
if (~RN) Q <= 1'b0;
else Q <= D;
end
assign QN = ~Q;
endmodule
Prior to running simulate_defect_free, compile this Verilog model using vlog mmodels/*.v
<CUT>.circuit contents (abbreviated)
...
.MODEL DFFR_X1 macro lang=verilog * only for modules that have no corresponding subcircuit
.DEFHOOK a2d_def d2a_def
.MODEL d2a_def D2A mode=std_logic
+ vhiref=VDD vloref=VSS trise=0.1n tfall=0.1n rrise=1k rfall=1k
.MODEL a2d_def A2D mode=std_logic
+ vhiref=VDD vloref=VSS vthrel=0.5 c=10f
.DIGLEVEL volt4logic1=3.3 * only for Eldo 2019.4_2 or later
Consult Questa Reference Manual for details about .DEFHOOK, and .MODEL A2D, D2A, and
std_logic.
...
schematics/DFFR_X1.sub contents (abbreviated)
.SUBCKT DFFR_X1 CK D RN Q QN VDD VSS
M_i_0 VSS CK net_000 VSS NMOS_VTL W=0.18U L=0.05U
...
.ENDS
Defects will be injected into this netlist
For a circuit that instantiates Verilog/VHDL:
All .MODEL and .DEFHOOK lines must be placed in <CUT>.circuit.
In an analog-on-top circuit, all, Verilog/VHDL modules that do not have a corresponding

subcircuit file must be called using this syntax:
.MODEL <modulename> MACRO LANG=<HDL> MOD=<source_name> LIB=<source_lib>

Yxxx <modulename> <node1> <node2> ...
Questa ADMS accepts this format for any HDL, but Eldo accepts it for only Verilog-A.
Circuit-Under-Test
Note
A subcircuit can have a SPICE netlist and an HDL model; Tessent DefectSim injects defects
in only the SPICE netlist.
Prior to running simulate_defect_free and simulate_defects, if they invoke Questa ADMS you
must compile HDL models by using one or more of the following commands (as needed, with
appropriate file names and extensions):
vlib mylib Creates a library named mylib

vmap work mylib Defines mylib as the working library
vlog *.v Compiles all .v files as Verilog in working library
valog *.va Compiles all .va files as Verilog-AMS in working library
vlog -sv *.sv Compiles all .sv files as System Verilog in working library
vcom *.vhd Compiles all .vhd files as VHDL in working library
vacom *.vhda Compiles all .vhda files as VHDL-AMS in working library
Note
If <CUT>.defectsim contains circuit_simulator questa when you run simulate_defect_free
or simulate_defects, any errors found by Questa ADMS are reported in a transcript file
saved in defectsim_outdir. The name of each file is Questa_transcript, followed by one of the
following suffixes: _list_subcircuits, _cut_lowest_level, _good_cir, _defect0, _defects_cir, and
_undetected_cir, and errors found by Eldo are reported in the .chi files in defectsim_outdir.
Circuit-Under-Test
Prepare a <CUT>.circuit file that contains your circuit-under-test; <CUT> must be upper-case.
A SPICE .sub file may contain .INCLUDE for portions of the circuit, but must not contain any
lines with “.SUBCKT”. Similarly, a Spectre .scs file may contain include for portions of the
circuit but must not contain and subckt lines. The Tessent DefectSim tool looks for these in the
layouts, schematics, and mmodels directories. If a subcircuit is used in your circuit that is not in
one of these directories, then the tool issues a warning that no defects can be injected into that
subcircuit.
Note
This User’s Manual refers to this file as <CUT>.circuit, but you may use a different suffix
and declare it in <CUT>.defectsim using top_circuit_suffix.
Tessent DefectSim identifies potential defect locations using the lowest-level (most detailed)
version of each subcircuit. simulate_defect_free -view_highest uses the highest-level (fastest
simulating) version of each subcircuit to produce the reference “good” result, and subsequently
using -view_lowest checks that the lowest-level version produces the same test result.
During defect simulations, to minimize simulation time, simulate_defects uses the highest-level
versions of subcircuits for the defect-free portions of the circuit and the lowest-level version for
the subcircuit instance containing the defect.
Circuit-Under-Test
The top-level of the CUT may contain transistors, diodes, and RCL elements but since it is not
in a directory that indicates whether it is pre- or post-layout, you must indicate whether the top-
level is to be treated as design-intent (pre-layout, which is default) or layout-extracted (post-
layout) by setting the top_circuit_type parameter (pre-layout is default). This does not affect
how each subcircuit is treated.
You may include power supplies and stimulus generation in this file or in the <CUT>.testbench
file. Note that the testbench file is not used during the create_defect_sites_list step, so DC
convergence or the value of voltage-dependent circuit elements may require the power supplies
to be in the <CUT>.circuit file (if any voltage is a parameter, it can be defined in the
<CUT>.circuit file and then re-defined in <CUT>.testbench to permit varying its value within
the testbench).
• Lines that must be included in a SPICE/Spectre <CUT>.circuit:

o .TRAN/tran line containing a stop and step time, or a .AC/ac or .DC/dc line
containing start=, step=, and stop=.
o .OPTION COMPAT if netlist is in HSpice format; alternatively, this may be placed
in the process file since it is automatically included.
o A node 0. This may be added using .CONNECT VSS 0.
o .PARAM - if any parameters are used in the circuit, they must be defined within it;
alternatively, they may be defined in an .INCLUDE file or the process file. They
must not be defined in <CUT>.testbench because that file is not used during the
analysis step, but they may be re-defined in the testbench.
o Any circuit elements whose parameters are required by another circuit element; for
example, if a model depends on a voltage or current source, then that source must be
in <CUT>.circuit instead of the <CUT>.testbench.
• Lines that must not be included in a SPICE <CUT>.circuit:
o .LIB — Use defectsim create_consolidated_subcircuits to automatically put all
library subcircuits in schematics, layouts, or mmodels directories.
o .ADDLIB — Only.LIB is supported, and only when running
create_consolidated_subcircuits.
o .ALTER, alter, altergroup — Not permitted because Tessent DefectSim uses
.ALTER to inject defects.
o .OPTION NOTRC — Any circuit elements after this line are not included in
<CUT>.potential_defect_list (because Eldo excludes them from .OPTION LIST).
o .OPTION NOCHI — The .chi output file is read by Tessent DefectSim.
Simulation Testbenches
Example SPICE Circuit Files

CUT.circuit * prefix must be upper-case, .circuit is default suffix
X1 in1 out1 pwr vssd inv * pin order same as mmodels version
.connect vssd 0 * must have a node 0 in circuit
CUT.spice * .spice declared as suffix in CUT.defectsim file

.option compat
.temp 30
.param vdd3=3 * can change parameter settings in .testbench
.param amplitude=0.5 offset=amplitude*2 frequency=1k
X2 in3 out4 pwr vss2 inv

x3 out4 vss2 cap
R2 out4 vss2 10k * the defects applied to this depend on top_circuit_type
VSS vss 0 0 * power and stimulus preferred in this file

VDD pwr vdd3 0 * but may be in .testbench instead
Vstimulus in 0 sin(offset amplitude frequency)
Notes:
• In your schematic and its netlist, at least one terminal of each unused transistor should
be labeled using a suffix such as “_NC1”, or “_noconnect2”, or “_dummy3”, as done in
circuit board design, so that later the transistors can be excluded from defect injection by
using, for example:
no_defects_in_elements _NC[0-9]*
Any transistors with their source and drain connected to the same node are recognized as
an MOS capacitor.
Your testbench-related text may be in <CUT>.testbench file or in <CUT>.circuit file.
Examples are provided in “Example Complete Testcase” on page 145 and “Recommended
Usage Flows” on page 149.
A SPICE file may contain .EXTRACT and .MEAS (or. MEASURE) lines to measure analog
parameters; the end of each such line must include lower and upper test limits, using LBOUND
and UBOUND. Any .EXTRACT or .MEAS lines that do not have test limits cause a warning.
The .EXTRACT line must also contain LABEL=<label>, and that label must be in the list of
test_parameters in your <CUT>.defectsim file.
Note
You may include DC and/or AC analyses and corresponding .EXTRACT and .MEAS lines,
but only after any .EXTRACT TRAN or .MEAS TRAN lines.
The file may also include your simulator options to control simulation accuracy, DC
convergence, log file contents, plot/probe voltages, etc.
A basic summary of the results produced by Tessent DefectSim for the good (defect-free) and
defective circuits are <CUT>.good_cir and <CUT>.defects_cir. These files are re-used by later
commands, so do not edit them.
• Lines that should be included in <CUT>.testbench, if the file exists:

o Any stimulus “circuitry” that produces all input signals and DC voltages that the
CUT requires; signals may also come from a .TVINCLUDE input test vector file.
o Any analysis “circuitry” (an example is provided in “Recommended Usage Flows”
on page 149) that produces output signals is periodically sampled by the Tessent
DefectSim tool to produce a reference “good” output pattern. If the output is invalid
or indeterminate at times, you must mask those values (replace 0/1 with X) at those
times in defectsim_outdir/<CUT>.good_vector. If you have at least one EXTRACT
or MEAS to measure a parameter, with test limits, then you are not required to list
any nodes as digital_output_signals in <CUT>.defectsim.
o Any EXTRACT or MEAS lines that produce measurements for test_parameters
listed in the <CUT>.defectsim file must contain LABEL=<unique_label>,
LBOUND=nn, and UBOUND=mm, where nn and mm are constants (numbers, not
expressions) that are the test limits. The label (and filename) in the line must begin
with an alphanumeric character and be in <CUT>.defectsim test_parameters. Use no
spaces around =.
• Lines that must not be included in <CUT>.testbench:
a. Any .OPTION that changes the output file format, such as NOASCII, ENGNOT.
b. .TVINCLUDE or .VEC that calls a file with output vectors (input vectors are
acceptable).
c. .ADDLIB n<5 – n=1,2,3,4 is reserved for Tessent DefectSim usage for CUT
subcircuits.
d. .ALTER is reserved for Tessent DefectSim usage.
e. .END — It is added automatically by Tessent DefectSim.
Example Testbench Files

CUT.testbench
VDD vdd 0 3
Vin in 0 pwl(0 0 1m 3 2m 3 4m 0) dc 0.0 ac 0.5 * simple pulse
.extract tran label=delay
+ tpdud(v(in) v(out) vth=1.5)) lbound=0.5n ubound=2.5n
* no spaces around =
* file will be created in defectsim_outdir
.probe v
CUT.testbench
.temp 80
.param vdd3=2.7
.param amplitude=1
.extract tran label=rise

+ valat(v(out),at=3n)-valat(v(out),at=2n) lbound=0 ubound=1.5n
.dc
.extract dc label=vdc v(out) lbound=-0.1 ubound=0.1
.ac lin 20 1000 20000

.extract ac label=vac max(v(in),100,20000)
+ lbound=0.4 ubound=0.6
.probe v(in) v(out)
CUT.testbench (when Questa ADMS will be used)

R1 indicator 0 1k * this simply adds indicator as a signal to force
C1 indicator 0 1p * this ensures above R will not be pruned by Eldo
* alternatively, you can use .OPTION RGND to automatically add a resistor
* to ground on all HDL signals
Y1 digital_core wide_bus other_signals
Corresponding qadms.do
add wave wide_bus
when {$now == 0} {force -source indicator 0}
when {$now == 1.23us} {
if {[examine -hex wide_bus] == FFFF} {
force -source indicator 1
} else {
force -source indicator 0
}
}
# in .defectsim, you can list “indicator” in digital_output_signals
run -all
quit
Testbenches must be written consistent with good test engineering practices. Here are some
guidelines:
• In <CUT>.defectsim, define sampling_start_time and sampling_interval for the

digital_output_signals so that sampling instants occur when these digital signal values
are deterministic, for every process corner. For example, sample clocked data outputs
immediately before the active edge of the clock; do not sample the output of a free-
running oscillator or PLL, since a small change in process, or jitter, could cause a
Process Files
different digital result in <CUT>.good_results. See “Step 6 - Simulate Defect-Free

Circuit” on page 119 for details.
• Non-deterministic outputs, like that of an oscillator or PLL, should be measured with
upper and lower test limits, for example, as pulse width or frequency. They should not
be sampled as synchronous digital outputs.
• Leakage current for input pins (IIL/IIH) or power supply pins (e.g., IDDQ) may be
extracted as the current flowing through the voltage source that drives the pin. For
example:
V1 pin VSS PWL(0 0V 1m 0 2m 3V)
.EXTRACT LABEL=pinIIL VALAT(i(pin),at=1m) LBOUND=-1u UBOUND=1u
Process Files
There must be a process parameter file that defines all the models and their parameter values, or
that contains .INCLUDE lines that reference such files. The file may have any name as long as
it is listed in <CUT>.defectsim as process_file process_file_name.
For fastest overall defect simulation time, it is most efficient to use nominal process parameter
values first since they are the most likely values. After measuring defect coverage for all tests
using ‘typical’ process, you can proceed to measure coverage of defects that were undetected by
using simulate_defects -undetected if the expected digital results are the same (parametric test
limits may differ), you then combine the second defect coverage with the coverage for nominal
process (and conditions) by using create_combined_summary.
The process file should not contain or reference any subcircuits—Tessent DefectSim expects to
access all subcircuits in the mmodels, schematics, or layouts directories listed in
<CUT>.defectsim.
Any subcircuits that are only in mmodels_directory, and not in the schematics_directory, will
not have defects injected in them.
Alternatively, if the process file that contains subcircuits cannot be modified (and you do not
want a local copy of them), then they must be excluded from <CUT>.list_of_potential_defects
by listing them in <CUT>.defectsim using one or more of:
no_defects_in_subcircuit_names <unix_expression> <unix_expression> ...

no_defects_in_subcircuit_instances <unix_expression> <unix_expression> ...
or by excluding them from random selection by using:
no_defects_in_elements <unix_expression> <unix_expression> ...
See “Using UNIX Regular Expressions (regexp)” on page 155 for examples.
Process Files
Chapter 5
Step 3 – Generate User-Defined Analog
Defect and Fault Models
Run the create_defect_models command to generate editable analog defect models for any or
all circuit element types (resistors, capacitors, inductors, diodes, and/or transistors), and use
these instead of the default models.
create_defect_models -output_file prefix
-type basic | ieee2427hard | ieee2427soft | ieee2427
[-element r|c|l|d|m|q ] [-add_to_config] [-replace]
The output file will be <prefix>.defectsim_defect_models. For element, you may list any one or
multiple letters from the list shown; for example, -element rcl. If -element is not used, models
will be generated for all element types.
The -type basic will generate models equivalent to the default ones used by DefectSim, which
allows you to see and change them. -type ieee2427hard will generate the “hard” defect models
(opens and shorts) defined by the proposed IEEE P2427 Standard for Analog Defect Coverage.
-type ieee2427soft will generate the “soft” defect models (variations in first-order
characteristics - you will need to edit these), and -type ieee2427 will generate hard and soft
defect models for each circuit element type.
The IEEE P2427 hard defect models include an open in each circuit element terminal: one open
for R, C, L, and diodes; two opens (gate and drain) for MOS; three for BJT. Hard defect models
also include a short between terminal pairs unless the nodes are already tied together in the
design: one short for R, C, L, and diodes, and three shorts for MOS and BJT. No defects
involving the bulk node are included - if these nodes are not always connected to power rails in
a design, models should be provided that insert defects involving the bulk node.
The IEEE P2427 soft defect models include: a 50% increase and decrease in R, C, or L; a 50%
increase in length or width for MOS; a 50% increase and decrease in diode VJ; a 50% increase
and decrease of BJT beta for BJTs. You will likely need to change the name of VJ and BF in the
models to suit your technology file.
The -add_to_config option automatically adds a line in <CUT>.defectsim that calls the
generated file. This allows you to run create_defect_model -type ieee2427hard, then
immediately afterwards run create_defect_sites_list.
The defect model names must begin with “pre” or “pos” followed by any number of letters;
Tessent DefectSim will automatically add “RL as a suffix unless the last two letters are already
“RL”. “pre” indicates the model is applicable to prelayout (schematic) circuit elements, and
Step 3 – Generate User-Defined Analog Defect and Fault Models
“pos” indicates the model is for post-layout circuit elements. For examples, see the IEEE2427
model names at the end of this Step.
The default defects for preLRL, preHRL, and postRL will also be listed for each circuit element
unless user-defined defect models are provided for them. You can disable use of the default
defect models by setting always_add_default_defects off in <CUT>.defectsim.
Run the create_primitive_subcircuit_list command to generate a list file of the subcircuits in the
schematics_directory that appear to be primitives.
create_primitive_subcircuit_list [directory] [-output_filename filename] [-replace] \

[-add_single_instance_primitives] [-ignore_subcircuit regexp]
The schematics_directory indicated in <CUT>.defectsim will be searched, unless you provide a

different directory. The output list file will be the file name indicated by the
primitive_subcircuits line in <CUT>.defectsim, unless you provide a different filename. Any
subcircuit names that contain the regexp text specified by -ignore_subcircuit are not listed.
A primitive is a single schematic circuit element (resistor, capacitor, inductor, diode, MOS
transistor, or bipolar transistor) that has a subcircuit. The criteria used by
create_primitive_subcircuit_list include whether the subcircuit has: more than one element
(unless -add_single_instance_primitives is used), suitable number of ports (e.g., 2 or 3 for a
resistor), recognizable port names (e.g., d g s for an MOS transistor, and not VDD or VSS), and
no subcircuits within. The list will also include the primary sub-instance within each subcircuit,
based on the first element instance found that begins with R, C, D, M, or Q, as appropriate. The
selection works perfectly for many libraries, but you should always check the output list file and
diagnostic messages. When followed by use of create_fault_models, and used with
create_defect_models, generation of custom models for all elements and primitive subcircuits in
a cell library is fully automated.
Run the create_fault_models command to generate custom analog fault models for any or all
primitive circuit types (resistors, capacitors, inductors, diodes, transistors, comparators, op-
amps, logic gates, etc.), based on template models in a file you provide.
create_fault_models [template_file] [-input_file_list listfile] [-output_file prefix]

[-add_to_config] [-replace] [-generate_default_templates]
The output file will be <prefix>.defectsim_defective_subcircuits. Unless you use -input_file

list_file, <CUT>.defectsim indicates which list file will be used by primitive_circuits list_file.
The optional -generate_default_templates switch creates a default.defectsim_template file in
your working directory. This enables you to edit the IEEE P2427 defect models and rerun the
command with that file as the template_file. In the list, each line has the syntax shown in
“Defining Custom Analog Defect Models” on page 161:
<subcircuit_name> <your_label> <sub_instance> <$port_n> <$port_m>

Examples:
pch3 myMtemplate1 - $port_1 $port_2
nchan myMtemplate2 m1
pch notemplate m1
rpoly myRtemplate1 r1
bip1 myQtemplate1 Q1 $port_2 $port_4
nmos1 defectsim_ieee2427hard_m M1
diode5 defectsim_ieee2427hard_d D1
resist1 defectsim_ieee2427hard_r R0
<your_label>, which is case-insensitive, can indicate the template model used; the command
ignores any line containing a label that does not correspond to a template. If no template file is
specified, then the built-in templates for defectsim_ieee2427 models will be accessed. A
template must have the same format as defined in “Defining Custom Analog Defect Models” on
page 161, except the following additional variables are available in a template:
• $subckt_header will be replaced by the entire subckt line of each subcircuit line in the
list file that has that template name.
• $subckt_body will be replaced by the entire subcircuit netlist contents, except the top
“subckt” line and the last “end” line.
• $subckt_body_without_instances will be replaced by the entire subcircuit netlist
contents, except the top “subckt” line, any instances of circuit elements or subcircuits,
and the last “end” line: in other words, all model and parameter definitions.
• $subckt_name will be replaced by the subcircuit’s name, which allows you to instantiate
the original subcircuit and, for example, connect a resistive short across its terminal.
This is much more efficient than $subckt_body because it inserts much fewer lines for
Eldo to parse.
• $pass_instance_parameters will be replaced by param1=param1 param2=param ... for
all parameters that were within the subcircuit.
• $defectNumber will be replaced by the number of the defect (from
<CUT>.sim_defect_list), for example D123.
• $subckt_footer will be replaced by .ends $subckt_name_DEFECTSIM_$defectNumber
or the Spectre equivalent. Alternatively, you can simply insert .ends or ends without any
other text.
A template must use the port names and port order that is common to all primitive subcircuits
that use that template. For example, “d g s b” is used for most MOS transistor subcircuits. A
template file can have a model like this example (template variables are in red font):
<component myMtemplate1, defect_model pre_short>

$subckt_header
$defect_description = words describing the defect
$defect_type = open | short | variation | other
$subckt_body or $subckt_body_without_instances, or X1 d g s b $subckt_name
X1 $subckt_ports $subckt_name $pass_instance_parameters
X2 $subckt_port_1 $subckt_port_2 ABC
R_defect d s $short_defect_resistance
$subckt_footer (auto-inserts .ends $subcktname_DEFECTSIM_$defectNumber)
$RL = [some Tcl expression]
<endcomponent myMtemplate1>
The names of the models generated for -type ieee2427 have descriptive names, in a consistent
number of characters, and unique (case-insensitive) RL settings, all with default value 1:
Element Model name RL setting

Resistor pre_open__ RL_resistance_o
Resistor pre_short_ RL_resistance_s
Resistor pos_open__ RL_opens_default
Resistor pre_max___ RL_resistor_x
Resistor pre_min___ RL_resistor_n
Capacitor pre_open__ RL_capacitance_o
Capacitor pre_short_ RL_capacitance_s
Capacitor pos_short_ RL_shorts_default
Capacitor pre_max___ RL_capacitor_x
Capacitor pre_min___ RL_capacitor_n
Inductor pre_open__ RL_inductance_o
Inductor pre_short_ RL_inductance_s
Inductor pos_open__ RL_opens_default
Inductor pre_max___ RL_inductor_x
Inductor pre_min___ RL_inductor_n
Diode pre_open__ RL_diode_open
Diode pre_short_ RL_diode_short
Diode pos_open__ RL_diode_open
Diode pos_short_ RL_diode_short
Diode pre_vmax__ RL_resistor_x
Diode pre_vmin__ RL_resistor_n
MOS pre_dg_short__ RL_transistor_t
MOS pre_gs_short__ RL_transistor_u
MOS pre_ds_short__ RL_transistor_v
MOS pre_drai_open_ RL_transistor_d
MOS pre_gate_open_ RL_transistor_g
MOS pre_gain_max__ RL_transistor_x
MOS pre_gain_min__ RL_transistor_n
Bipolar pre_base_open_ RL_bipolar_b
Bipolar pre_coll_open_ RL_bipolar_c
Bipolar pre_emit_open_ RL_bipolar_e
Bipolar pre_cb_short__ RL_bipolar_t
Bipolar pre_be_short__ RL_bipolar_u
Bipolar pre_ce_short__ RL_bipolar_v
Bipolar pre_gain_max__ RL_bipolar_x
Bipolar pre_gain_min__ RL_bipolar_n
Chapter 6
Step 4 - Netlist Analysis
Run the create_defect_sites_list command to determine which netlists (schematic, layout, etc.)
are available for each subcircuit, run Eldo to find all RCL elements, diodes, MOS transistors,
finFETs and bipolar transistors in your netlist, and calculate pre- or post-layout RL values for
each one. Note that <CUT>.testbench is not used by this step.
The option -activity_based_rl only updates the RL values in <CUT>.potential_defect_list,
based on $RL_activity expressions in custom defect models, if you have previously run
create_activity_results (described later in this Step). With this option, Eldo is not run, so you
can modify $RL_activity expressions and quickly see the effect on the RL values.
The option -treat_parallel_resistors_as_redundant creates a file that lists all parallel resistors
found in layouts directory .sub files, and then assigns all these resistors postRL=0.000 in
<CUT>.potential_defects_list so that they are not randomly selected for open circuit defect
injection, and so that you can easily find the lines to edit the RL values if you wish.
The option -generate_parallel_resistors_file_only generates the <CUT>.parallel_resistors file,

but does not proceed to generate the list of potential defects. This command should be used
when any subcircuit netlists have more than a few hundred resistors because generating the file
might take an hour or more, so the file should be reused rather than generated each time you run
create_defect_sites_list. The option -reuse_parallel_resistors_file reuses an existing
<CUT>.parallel_resistors file.
create_defect_sites_list [-activity_based_rl]
[-treat_parallel_resistors_as_redundant
| -reuse_parallel_resistors_file
| -generate_parallel_resistors_file_only ]
• Required input files

o <CUT>.circuit
o <CUT>.defectsim
o process_file
• Output files
o <CUT>.potential_defect_list (in current directory)
List of potential defect sites, with relative likelihood (RL) values. Note that the listed
elements may have many parameters in your netlist but only the nodes, RCL values,
model, length and width are shown for file conciseness and because Tessent
DefectSim does not use any other data to compute RL values. The RL= values are
written in a column of your choosing unless the existing line is too long, in which
case it is appended after a space.
Example:
R23 N1 N2 6.2 [preLRL= 1.000] D1
C17 n3 n4 8.9P [preHRL= 1.000] D2
X5.C89 X2.X7.n3 VSS 2.4F [postRL= 0.500] D3
X5.M2 X5.n2 X5.n2 VDD VDD NMOS1 50N 300N [preHRL= 1.000] D4
X2.X7.C18 X2.X7.n5 VSS 1.2F [postRL= 0.120] D5
X2.X7.R29 X2.X7.n2 VDD 0.3 [postRL= 0.053] D6
Meaning of the first four characters in [ ] is as follows:

• pre/pos — Defect site in schematic (pre) / (post) layout netlist
• L — Default defect is lower value for R,C,L, MOS stuck-off, emitter open,
diode open
• H — Default defect is higher value for R,C,L, MOS stuck-on, base open, diode
short
o <CUT>.potential_defect_list_activity_RL (if option -activity_based_rl was used)
Same content as <CUT>.potential_defect_list except RL values are activity based.
o <CUT>.activity_rl_summary
This file shows previous and new RL values, and other information.
o <CUT>.instances_pruned (in ./defectsim_outdir)
List of all non-excluded subcircuit instances used, grouped by subcircuit name,
indicating whether they have netlists in mmodel, schematic, or layout directories.
Example:
NAND2 mmodel schematic layout
X2
-
GATE3 schematic layout
X2.X7
o <CUT>.CELLS_LOWEST_LEVEL_NETLISTS (in ./defectsim_outdir)

An include line for every non-excluded subcircuit used from lowest-level available
(from schematics_directory or layouts_directory orflat_layouts_directory).
o <CUT>.CELLS_HIGHEST_LEVEL_NETLISTS (in ./defectsim_outdir)
An include line for every non-excluded subcircuit used from highest-level available
(from mmodels_directory, schematics_directory, or layouts_directory).
o <CUT>.parallelResistors (if -treat_parallel_resistors_as_redundant option was
used)
o <CUT>.circuit_defectsim_analysis (if HDL models used) and

<CUT>.defectsim_empty_veriloga_module.va (in ./defectsim_outdir)
These are temporary files created so that Eldo can list potential defect sites.
Example console listing for the simple op-amp in “Example Complete Testcase” on page 145.
Reading OA.defectsim
Using Eldo Version: 16.1
----------------------------------
---- Pre-layout netlist analyzer ----
Running eldo to find subcircuits... DONE

Running eldo to find subcircuit instances... DONE
Creating OA.CELLS_HIGHEST_LEVEL_NETLISTS
Creating OA.CELLS_LOWEST_LEVEL_NETLISTS
Creating OA.cut_lowest_level
Running eldo to find potential defects... DONE
Creating OA.potential_defect_List
---- Pre-layout netlist analyzer. Runtime: 3.0 sec ----
---- Postlayout netlist analyzer ----
Updating resistors in EXAMPLE_OA.potential_defect_list... DONE 0.00 sec

Updating inductors in EXAMPLE_OA.potential_defect_list... DONE 0.00 sec
Updating capacitors in EXAMPLE_OA.potential_defect_list... DONE 0.00 sec
Updating transistors in EXAMPLE_OA.potential_defect_list... DONE 0.00 sec
32 potential defects listed.

Histogram of RL values
0 RL values >1000
0 RL values >100 <=1000
2 RL values >10 <=100
4 RL values >1 <=10
21 RL values >0.1 <=1
0 RL values >0.01 <=0.1
5 RL values >0 <=0.01
0 RL values =0
---- Post-layout netlist analyzer. Runtime: 0.04 sec ----

DefectSim closed.
Example file FILTER.parallelResistors
<subckt: OA >
R142
R143
R156 (Note: 3 resistors are listed when 1 resistor is in parallel with 2 in series)
<endsubckt: OA >
<subckt: BUFFER >
R17
R94
<endsubckt: BUFFER >
Usage Notes
The create_activity_results commands allows relative likelihood (RL) values to be based on

circuit activity measured during defect-free simulation, using mathematical expressions that
you write in each custom defect model (UDADM) and/or each defective subcircuit netlist
(UDAFM).
create_activity_results [-activity_based_rl]
In UDADMs or UDAFMs, you insert the expression for $RL_activity on a line immediately
after the expression for $RL. See “Defining Custom Analog Defect Models” on page 161 for
details about creating expressions for $RL_activity. Run this command only for applications
requiring functional safety during usage, and only after running create_defective_sites_list. In
effect, this new command runs the following:
• create_defects_to_simulate, with target_number_defects_to_simulate set to all

• simulate_defect_free, with only the lowest view
• for –activity_based_rl option, it also runs create_defect_sites_list –activity_based_rl
Required input file:
• <CUT>.potential_defect_list
Output file:
• <CUT>.activity_results
This file list sampled voltages and currents are all defect sites, in the defect-free circuit.
• <CUT>.potential_defect_list_activity_RL
This file is generated only if –activity_based_rl option used. It is same format as
<CUT>.potential_defect_list, but the RL values are updated for all defect sites that have
$RL_activity expressions in their custom defect models or defective subcircuit models.
Usage Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Usage Notes
The following lists the usage notes when performing netlist analysis.
• You should examine the .chi files in defectsim_outdir to check for errors or significant
warnings before proceeding to simulate_defect_free, to avoid errors in (the much
longer) simulate_defect_free simulation. However, if you have a <CUT>.testbench, you
can ignore warnings such as “unbiased nodes” or “no DC path to ground” because
during this analysis step Eldo is invoked without <CUT>.testbench. You may include
the DC sources in <CUT>.circuit to avoid these warnings and possibly get faster DC
convergence. Any .OPTION lines needed for DC convergence should be in process_file.
Usage Notes
• If a subcircuit is called with an M (multiplier value) and an M value is also used within
the subcircuit, then the product of the two M values is used by Eldo. The product of M
values is also used by DefectSim to calculate the RL value and to scale the defect
properties. However, note that M instances of the defective subcircuit instance will be
connected in parallel, and this might reduce the total inserted resistance or increase the
total inserted capacitance.
• A warning is issued if any subcircuits contain if-else-endif. If either clause instantiates
circuit elements, you must comment out either the if clause, or the else clause, and the if-
else-endif lines, for schematics/layouts since Tessent DefectSim cannot tell which
clause is invoked.
• The calculations for the RL value of each potential defect can get complicated, so it is
simpler to consider each parameter setting in <CUT>.defectsim individually. As an
example, here is the calculation (in pseudo-code) for the default defect model for
resistors; all other elements use a subset of this calculation (<CUT>.defectsim file
parameters in bold font, and the resistor’s resistance is R):
if (model = a value in RL_model list),
RL_model=list value
else
RL_model=1
if (schematic R > R_parasitic) or (layout R >= R_design),

if unit_RL_R_design > 0,
preLRL = R * RL_model * RL_resistance_L / unit_RL_R_design
preHRL = R * RL_model * RL_resistance_H / unit_RL_R_design
else
preLRL = RL_model * RL_resistance_L
preHRL = RL_model * RL_resistance_H
else
if unit_RL_R_parasitic_LW > 0,
postRL = R * RL_model * RL_opens_default /
else
if (L= & W= & layer= for the resistor is found in the .sub file)
postRL = L / W * RL_model * RL_opens_default /
else
postRL = RL_model * RL_opens_default
• If the .sub file that contains a resistor is greater than 10,000 lines (because it is a flat-
extracted layout netlist), the time for create_defect_sites_list can dramatically increase
because each time a resistor is found in defectsim_outdir/<CUT>.cut_lowest_level.chi,
it is searched for in the .sub file so that its length, width, and layer can be found (in the
comment field for the resistor). If the resistors do not have this information, this is a
waste of time that can be avoided by setting unit_RL_R_parasitic > 0. The default is
1000.
Usage Notes
Chapter 7
Step 5 - Defect Injection
Run the create_defects_to_simulate command to randomly select defect sites and insert defects.
The option -activity_based_rl only causes the command to read
<CUT>.potential_defect_list_activity_RL instead of <CUT>.potential_defect_list.
create_defects_to_simulate [-activity_based_rl]
• Additional required input files

o <CUT>.potential_defect_list or <CUT>.potential_defect_list_activity_RL
o <CUT>.CELLS_LOWEST_LEVEL_NETLISTS (in ./defectsim_outdir)
<CUT>.CELLS_HIGHEST_LEVEL_NETLISTS (in ./defectsim_outdir)
• Output files
o <CUT>.sim_defect_list
List of the defects selected for simulation.
Example:
M82 ND NB NS NB XMOS 100N 200N [preRL= 1.000] D1
C19 N5 N6 9.3F [preRL= 1.000] D28
X3.C19 N3 N2 9.3F [posRL= 9.300] D96
o <CUT>.circuit_alters (in ./defectsim_outdir)

Eldo-format file containing all of the defects to simulate.
Example:
* Simulation 1 of 98
.ALTER # D1: MOS transistor stuck-on in top-level
* Defect location: M82 ND NG NS NB XMOS L=100N W=200N [preRL=
1.000]
* Defect location in subckt names:
M82 ND NB NS NB XMOS L=100N W=200N
* Simulation 2 of 98
.ALTER # D2: short circuit in instance X5.X3 of subcircuit NAND2
* Defect location: X5.X3.C19 N3 N2 8.9F [postRL= 9.300]
* Defect location in subckt names: MYBLOCK.LOGICGATES.NAND2
R_C19_DEFECTSIM N3 N2 100
.BIND INST=X5.X3 TO_SUBCKT=NAND2_DEFECTSIM_D96
DEFAULT_MAPPING=by_name
+ FILE=<CUT>.CELLS_DEFECTIVE_NETLISTS
o <CUT>.CELLS_DEFECTIVE_NETLISTS (in ./defectsim_outdir)
Usage Notes
Concatenation of all subcircuits from lowest-level netlists, with one defect inserted
in each. Some subcircuits might be included multiple times, each with a different
defect.
Example portion of a file:
...
.SUBCKT INV_X1_DEFECTSIM_D20 A ZN VDD VSS
* transistor stuck-off
* original: M_i_0 ZN A VSS VSS NMOS_VTL W=0.09U L=0.05U
M_i_0 ZN VSS VSS VSS NMOS_VTL W=0.09U L=0.05U
+ AS=0.004P AD=0.004P PS=0.180000U PD=0.180000U
M_i_7 ZN A VDD VDD PMOS_VTL W=0.135000U L=0.05U AS=0.009P

AD=0.009P
+ PS=0.27U PD=0.27U
.ENDS
...
----------------------------------
---- Random defect injector ----
Reading OA.sim_defect_list file

11 randomly selected defect locations (seed = 729249926). You requested
10.
Defect locations saved in OA.sim_defect_list file
Creating OA.circuit_alters file
Creating OA.CELLS_DEFECTIVE_NETLISTS file
---- Random defect injector. Runtime: 0.0 sec ----

DefectSim closed.
Usage Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Usage Notes
The following lists the usage notes when performing defect injection.
• This is the fastest step (about 5 seconds to select each hundred defects); the most time-
consuming step is simulate_defects. To avoid wasting simulation time when running
simulate_defects, you should first set target_number_defects_to_simulate in
<CUT>.defectsim to an integer less than 5, so that only a few defects are selected by
create_defects_to_simulate, and then run through all remaining Tessent DefectSim steps
to check for any problems.
Usage Notes
• You can set seed_for_random_selection in <CUT>.defectsim to the value reported

when you previously ran create_defects_to_simulate, so that the same random defects
are selected, thus allowing you to see whether any simulation problems are now fixed
for those defects.
• The top line of <CUT>.sim_defect_list contains “Max Defect ID = Dnnnn” to indicate
the highest numbered defect in <CUT>.potential_defect_List. The line also contains
“RLthreshold = n.nnn”, which is calculated based on the sum of all RL values, their
distribution, and target_number_defects_to_simulate; elements with RL values less than
this threshold are selected randomly; elements with larger RL values are always selected
(that is, nonrandomly). The top line also includes sumRLN, which is the sum of all RL
values, after defects_only_in_elements and no_defects_in_elements are accounted for,
and it includes totalSumOfRL, the sum of all RL values in the original
potential_defect_list. If include_func_for_DCLat_simulation is on, this is indicated.
Usage Notes
Chapter 8
Step 6 - Simulate Defect-Free Circuit
Run the simulate_defect_free command to simulate the good circuit (no defects injected) using
the highest-level netlists (the default option -view_highest) and then lowest-level netlists
(option -view_lowest), to obtain the reference output pattern and initial DC voltages for use
during defect simulations. You must run -view_lowest after -view_highest. If any of the
extracted/measured parameters are outside its upper or lower limits, then a warning is reported
that you will not be able to run simulate_defects until all tests pass for the defect-free circuit.
This command also reports the activity coverage of a test stimulus (without affecting simulation
time) in <CUT>.good_results. Activity coverage is similar to toggle coverage in digital
circuits, and is the likelihood-weighted percentage of potential defect sites that are active
enough to allow injected defects to be detected (assuming the defect’s effect was observable at
an output of the CUT). You should modify the test until you achieve high activity coverage
before proceeding to simulate defects. For more details, see “How Tessent DefectSim Measures
Activity Coverage” on page 173.
To have multiple tests in a working directory, each must be in a separate <CUT>-<test>.circuit

and/or <CUT>-<test>.testbench. A separate defectsim_outdir-<test> sub-directory will be
created for each test. You can combine all their respective summary files. Each additional test
must have a <CUT>-<test>.defectsim file containing only settings for any or all of the
following: sampling_start_time, sampling_interval, simulation_end_time,
sampling_threshold_voltage, sampling_activity_delay, test_parameters, digital_output_signals,
digital_output_signals_safety, test_parameters_safety, user_defined_good_vector. To simulate
the additional tests, invoke Tessent DefectSim using <CUT>-<test> as the circuit-under-test
name.
simulate_defect_free . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Usage Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Running Questa ADMS GUI in Display Mode to View Waveforms . . . . . . . . . . . . . . . 122
The simulate_defect_free command simulates the good circuit (no defects injected).
simulate_defect_free [-view_highest | -view_lowest]

o <CUT>.good_output_vector (in ./defectsim_outdir), when -view_lowest is used

• Output files
o <CUT>.good_cir or <CUT>.good_cir.scs
When option -view_highest is used, this file calls the above files and is run by Eldo.
o <CUT>.good_results
When option -view_highest is used, this file contains binary samples of sampled
good-circuit outputs, and parameter measurements.
Example:
DefectSim outputs: OUT EN Q7 Q8
TIME BUS(DefectSim_Outputs)
4.00000E-08 1010
9.00000E-08 1011
1.40000E-07 1001
1.50000E-07 1001
*Test parameters
gain = 1.03426e+00
o <CUT>.good_output_vector (in ./defectsim_outdir)

When option -view_highest is used, this file contains the logic values captured at the
sampling interval. If any logic values detected later by simulate_defects differ from
these values, the defect is declared detected. You may change any logic values to X
to “mask” those that are don’t-care (because the logic value captured may vary due
to process variations). This file becomes a required input file when -view_lowest is
used. If you make any changes, save this file as any filename in your current
directory and add the following line in <CUT>.defectsim so that next time
simulate_defect_free generates the file, it does not over-write your edited version:
user_defined_good_vector filename
Example (corresponding to the above example):

Original With masking
UNITS PS UNITS PS
OUTPUTS OUT EN Q7 Q8; OUTPUTS OUT EN Q7 Q8;
RADIX > 1111 RADIX > 1111
@40000 >1010 @40000 >xx10
@90000 >1011 @90000 >101x
@140000 >1001 @90000 >1001
@150000 >1001 @90000 >10x1
o <CUT>.initial_dc (in ./defectsim_outdir)

When option -view_highest is used, and reuse_initial_dc settings is used, this file
contains the saved DC voltages for all nodes, to reuse for defect simulation.
o <CUT>.defect_free_v_measurements (in ./defectsim_outdir)
Usage Notes
Voltages across each potential defect site. A similar file is created for currents.
o <CUT>.defect0_cir or <CUT>.defect0_cir.scs
When option -view_highest is used, this file calls some of the above files.
o <CUT>.defect0_results
----------------------------------
---- Runs Spice simulator for defect-free circut ----
Creating OA.cir_dc_temp
Reuse initial DC is on - Running eldo on OA.cir_dc_temp... DONE
Creating OA.good_cir
Running eldo - good simulation
Simulation progress : 10% (t = 19.0000 U)
Creating OA.good_results
---- Runs Spice simulator for defect-free circuit. Runtime: 5.0 sec ----
DefectSim closed.
Usage Notes
When simulating a defect-free circuit, the following usage notes apply.
• If there is only one directory of subcircuits, the -view_lowest option will report an error
and not run because the results would always be identical to running -view_highest and
a waste of simulation time.
• You should examine the Eldo output files in the defectsim_outdir sub-directory to
ensure that there were no significant warnings.
• Note: If you make changes to the netlist (or any subcircuits) to address a problem
reported by Eldo, in some cases you must re-run create_defect_sites_list and
create_defects_to_simulate so that the corrected netlist and subcircuits propagate to the
files used by simulate_defect_free. You can check the contents of
CELLS_HIGHEST_LEVEL_NETLISTS to see which subcircuits are access by an
Running Questa ADMS GUI in Display Mode to View Waveforms
include statement, and which copied into this file because changes to them were
required.
• simulate_defect_free -view_lowest checks that results are the same as for
simulate_defect_free -view_highest. You will not be able to proceed to simulate_defects
until both -view_highest and -view_lowest pass the test, unless you only have one
directory of subcircuits. simulate_defects allows you to waive this requirement by using
-no_lowest_view_results.
• If <CUT>.circuit or <CUT>.testbench contains .PROBE V (to save all waveforms) or
.PROBE V(node1) V(node2*) ..., then you can view the waveforms using Mentor
Graphics EZwave tool by entering the following command:
ezwave defectsim_outdir/<CUT>.good_cir.wdb &
After the EZwave GUI displays, click on the database folder in the top-left window, and
then on the TRAN folder—this lists all probed node signals in the lower-left window.
Double-click on any node name to view its waveform.
• Since -simulate_defect_free -view_highest uses the highest-level netlists for each
subcircuit, if some subcircuits have higher-level and lower-level netlists, then
simulate_defect_free simulation time can be less than for only one level. Simulation
acceleration achieved by Tessent DefectSim should be compared to -view_lowest run
time, not -view_highest run time.
• simulate_defect_free simulates a circuit at nominal process or a process corner. Before
proceeding to simulate_defects, be sure that the test limits (LBound and UBound of each
.EXTRACT) are suitable for all process corners, so that yield is acceptable. Otherwise,
an unrealistically high coverage of defects may be reported. (A test that fails all ICs
achieves 100 percent defect coverage, but 0 percent yield; the objective is to achieve the
highest yield and defect coverage combination that is profitable.)
Running Questa ADMS GUI in Display Mode to

View Waveforms
After running Tessent DefectSim that invokes Questa ADMS, examine the transcript file (the
default log file from Questa ADMS) if there were errors, or to check for unexpected warnings.
You can view waveforms captured by .PROBE V immediately after running
simulate_defect_free using EZwave and loading in defectsim_outdir/<CUT>.good_cir.wdb
Alternatively, you can view the waveforms in Questa ADMS, but you will need to re-run the
simulation.
This command opens the Questa GUI, and loads the PLL's good circuit, ready for simulation:
vasim -cmd PLL.good_cir -eldoopt <eldo options, if any>
• Re-size the Instance, Objects, and Wave sub-windows, if necessary; their sizes are auto-
saved.
• If you have .PROBE V, then all waveforms are saved when you simulate.
• Click Simulate then select Run, and select Run -All.
• Note that there may be two overlapping windows that display waveforms, and each is
accessible by clicking on its tab at the bottom of the GUI. By default, the Wave tab
shows analog and digital waveforms in EZwave, and the Wave1 tab shows HDL digital
waveforms in ModelSim.
• To view a node’s waveform, left-click on the subcircuit instance in the Instance
window, then right-click on the signal in the Objects window, and select Add Wave.
• Note that in the EZwave window you cannot view waveforms for nodes that are only
connected to HDL models. The waveform can be viewed if you connect, for example, a
1G ohm resistor between that node and ground.
Chapter 9
Step 7 - Simulate Defects
Run the simulate_defects command to simulate the circuit with each of the defects in
<CUT>.sim_defect_list. All the results and settings are output to an easy-to-read
<CUT>.defectsim_summary and/or <CUT>.defectsim_tolerance_summary file (if either is
accidentally deleted, you can skip the long simulation and only re-create that summary by using
-summary_only.)
You must have run simulate_defect_free -view_highest, and if there is more than one directory
of subcircuits, you must also have run it with -view_lowest, both with zero fails. If the latter
simulation time would be too long, you can override this requirement by running
simulate_defects with option -no_lowest_view_results.
If you have additional testbenches, each with a <CUT>-<test>.defectsim, <CUT>-

<test>.circuit and/or <CUT>-<test>.testbench, then invoke this command using <CUT>-
<test> instead of <CUT>. You should not re-run create_defect_sites_list or
create_defects_to_simulate, since the exact same defects must be simulated for additional
testbenches.
simulate_defects [-suffix <suffix>] [-calculate_lfm <summary1> <n1> <summary2> <n2> ...

[-summary_only] [-only_defects { Dn, Dm, ..., Dx-Dy } ] [-except_defects { Dn, Dm, ..., Dx-Dy }]
[-no_lowest_view_results]
You can measure ISO 26262-defined diagnostic coverage with respect to latent faults (DC-Lat),
if the CUT has a Safety Mechanism (SM) / self-monitor circuit. You must have a <CUT>-
<SMtest>.defectsim file that lists the test-related settings for the SM portion of the circuit, and it
must ensure defects are injected in only the SM circuitry by using SM_elements (it must not
contain any other defect exclusions). The applied stimulus for the SM must overdrive the
signals from the main Function into the SM, and the stimulus must cause the SM to report a
failure—the stimulus represents one of two defects occurring simultaneously in the CUT; the
second defect will be injected into the SM. Digital outputs of the SM must be listed as
digital_output_signals and if the SM has BIST outputs (a second level SM) then they must be
listed as digital_output_signals_safety— if there is no second level SM, you must set
digital_output_signals_safety "". See digital_output_signals_safe_mode for details on how to
tell Tessent DefectSim how to interpret SM outputs. The output file will be
<CUT>.defectsim_dclat_summary. Run defectsim EXAMPLE_TMRFF create_example to
obtain an example of this procedure.
The -calculate_lfm option allows you to measure the ISO 26262-defined latent fault metric
(LFM). The circuit-under-test must have one or more SM each of whose DC-Lat has been
measured using the option -calculate_dclat, and a resulting <CUT>.defectsim_dclat_summary.
After the option, list the relevant dclat_summary files, each followed by an integer that indicates
how many of those safety mechanisms are in the CUT.
The –only_defects option simulates only the defects you list that are a subset of the defects in
<CUT>.sim_defect_list. You may also use –except_defects (which has higher priority). This is
useful when an additional testbench is intended to detect only a subset of the defects, and you do
not want to simulate the others that were randomly selected. You may list individual defects or
ranges. The list must be enclosed by braces, with a space between braces, commas as delimiters,
and hyphen to indicate a range. If you select a subset for CUT-SM, with SM_elements defined,
you must use the same subset for CUT -calculate_lfm (without SM_element defined). If you run
this command with different subsets, and give each output summary a unique name (they will
automatically get suffixes .bak1, .bak2, …), then you can use create_combined_summary on the
resulting output summaries.
-undetected is documented in “Step 8 - Simulate Undetected Defects” on page 137.

o <CUT>.good_results
o <CUT>.good_output_vector (in ./defectsim_outdir) or the file listed for
user_defined_good_vector in <CUT>.defectsim
o <CUT>.dclat_summary (if -calculate_lfm option is used)
• Output files
o <CUT>.defect_results
List of all defect simulation results, with either zero errors or time of first error.
Example:
Outputs: OUT EN Q7 Q8
D0 defect-free
4.00000E-08 1010
9.00000E-08 1011
1.40000E-07 1001
1.50000E-07 1001
D1: RESISTANCE R14 50% LOW, IN INSTANCE X1 OF SUBCIRCUIT A

total number of checkbus errors : 0
D2: CAPACITANCE C3 50% LOW, IN INSTANCE X1 OF SUBCIRCUIT B

at time 9.000000e-08, output EN is 1 and should be 0
at time 9.000000e-08, output Q8 is 0 and should be 1
D3: TRANSISTOR M5 STUCK-ON, IN INSTANCE X3 OF SUBCIRCUIT B

at time 4.000000e-08, output Q7 is 1 and should be 0
o <CUT>.defectsim_summary (if <CUT>.defectsim contains values for

digital_output_signals or test_parameters)
Usage Notes
o <CUT>.defectsim_tolerance_summary (if at least one <CUT>.defectsim setting

ends in _safety)
o <CUT>.defect_v_measurements (in ./defectsim_outdir)
Voltages across each defect. A similar file is created for currents.
o <CUT>.defectsim_undetected.xml (if hierarchy_separator_for_XML is used)
----------------------------------
---- Runs spice simulator for defective circuits ----

Reading OA.instances_pruned file
Reading OA.good_results file
Creating OA.good_output_vector file
Creating OA.defects_cir file
Running Eldo - defects simulation
Simulating....
1 .ALTER * D1: RESISTANCE R144 50% LOW, IN INSTANCE X1 OF SUBCIRCUIT OA

2 .ALTER * D9: RESISTANCE RFB 50% LOW
...
11 .ALTER * D32: TRANSISTOR M136 STUCK-ON, IN INSTANCE X1 OF SUBCIRCUIT OA
Eldo simulation: DONE

Creating OA.defect_results file
Reading OA.good_results file
Reading OA.defects_cir.chi file
---- Runs Spice simulator for defective circuits. Runtime: 8.0 sec ----
DefectSim closed.
Usage Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Example Output defectsim_summary File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Example Output defectsim_tolerance_summary File . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Usage Notes
Use the following guidance when performing the simulate defects step.
• This is the most time-consuming step. See Usage note for create_defects_to_simulate
about how to avoid wasting time in this step due to simulation convergence problems.
• To diagnose any simulation problems, examine the Eldo output files in the
defectsim_outdir sub-directory.
Usage Notes
• Caution: If you make changes to the netlist (or any subcircuits) to address a problem
reported by the Eldo tool, then you might need to re-run create_defect_sites_list and
create_defects_to_simulate so that the corrected netlist and subcircuits propagate to the
files used by simulate_defect_free and simulate_defects. You can also set
seed_for_random_selection in <CUT>.defectsim to the value reported when you
previously ran -create_defects_to_simulate, so that the same defects are selected.
• A listing of all defects simulated is included at the end of the output summary file(s).
• If your file contains .PROBE V, you can view the waveforms in EZwave by entering the
following command:
ezwave &
After the GUI displays, click OpenFile icon, select defectsim_outdir/

<CUT>.defects_cir.wdb, click the database folder, then the TRAN folder, then double-
click any node name to view its waveform for all simulated defects. If you hover the
cursor over a waveform, the defect that caused it is displayed, as shown in Figure 9-1 for
the op-amp in “Example Complete Testcase” on page 145. If you first open
OA.good_cir.wdb and display V(VOUT)—it plots in green; then open
OA.defects_cir.wdb and display the same node—it plots in yellow to allow an easy
comparison.
Figure 9-1. Waveform Viewing in EZwave
• You can set stop_on_detection off in <CUT>.defectsim so that each defect’s simulation
runs to completion despite detecting the defect—this requires more simulation time but
is useful for test time optimization because the defect detection matrix in
<CUT>.defectsim_summary shows all time instants when a defect was detected, instead
of just the first instant.
Example Output defectsim_summary File
• If defect simulation fails to converge for some defects, you can set reuse_initial_dc off
in <CUT>.defectsim so that DC convergence is done without reusing DC values from
the defect-free circuit; then run simulate_defects.
• By default, the CPU time per defect is limited to twice the CPU time reported for the
defect-free circuit. If this time is exceeded, an 'E' (indicating error) will be shown for
that defect in the defect detection matrix in the output summary. You can increase this
time by setting CPU_time_per_defect to a larger time, and re-run simulate_defects for
that defect (and others) using the -only_defects option, and then use
create_combined_summary to merge the results into a single summary.
• You can view the sites of the undetected defects in your schematic editor, such as
Mentor’s Pyxis, or in Cadence’s Virtuoso if you have Artist Link, by opening the AMS-
Results_Browser, accessing the <CUT>.defectsim_summary file, selecting the instance
of an undetected defect, and then pressing Ctrl-K. Optionally, you can also select
undetected defects in <CUT>.defectsim_undetected.xml if its generation was enabled in
<CUT>.defectsim.
• You can also view the results in a sortable table. Enter the command amsrb
<CUT>.defectsim_summary.defsum
To generate that .defsum file, re-run simulate_defects with the -summary_only option. If
you always want that .defsum file produced, in <CUT>.defectsim you must have
ade_interface on. If you always want the corresponding .csv files, you must have
report_csv_with_summary on. Note that these files are produced only for .good_results,
.defectsim_summary, and .defectsim_tolerance_summary, but not yet for any combined
summary files.
Example Output defectsim_summary File

It contains weighted defect coverage, defect detection matrix, and undetected defects.
A 99% confidence level is reported if ISO 26262 metrics are also being measured. The
confidence level will be reported as “N/A” (not applicable) if the number of defects randomly
selected is less than 2. Note that only defects whose RL value is less than RLthreshold are
randomly selected—those with higher RL values are always selected.
Example Output defectsim_tolerance_summary File
DefectSim summary of test coverage for TMRFF.scs

Likelihood-weighted defect coverage: 34.36%
99% confidence interval: +/- 12.05%
shorts coverage: 37.35% (of 24 defects, RLsum = 23.123)
opens coverage: 32.26% (of 34 defects, RLsum = 32.719)
Legend
-: not detected
U: failed Upper bound for parameter
L: failed Lower bound for parameter
d: detected because Parameter could not be measured
D: Detected by digital output sample
d: detected by digital output sample earlier, then autostopped
E: Error on alter during defective simulation (not counted for defect coverage calculations)
Parameter Digital samples Delta Cumul. 99% Conf. Bin

1 12345 RL Coverage Coverage Interval Bin RL
Defect
D761 - ----- 0.005 1.72% 1.72%
D1284 - ----- 0.975 1.75% 65.63% +/-12.05% 1 27.919
D1133 U ----- 0.011 1.72% 1.72%

D390 U ----- 0.129 1.72% 6.87% +/-6.94% 2 0.177
D1060 - DD-D- 0.007 1.72% 1.72%

D779 - DD-D- 0.323 1.72% 6.87% +/-6.94% 3 0.428
Parameters LowerLimit Defect0Circuit UpperLimit Coverage +/- 99% confidence

1 IDDQ1 -1.000000e-6 8.052300e-06 10.000000e-6 17.18% +/- 9.80%
Sample Cumulative Delta Cumulative Delta List

Coverage Coverage # defects # defects of defects
1 18.90% 18.90% 11 11 D126 D202 D256 D775 D779 D852
2 25.78% 6.87% 15 4 D323 D355 D367 D775 D779 D848 D852
Param 34.36% 6.87% 20 4 D390 D824 D1133 D1184
undet. - - - 38 D88 D170 D761 D780
UNDETECTED DEFECTS======
(ordered by decreasing likelihood)
Defect 1273: [pre-layout, relative likelihood 0.975] trans. M10 stuck-off, in inst. X4 of
subcircuit NOR
ACTIVE X4.M10 OUT QB1 X4.N11 VDD PMOS_VTL 50.00000N 195.00000N
* Alter 34 defect location in subckt names: NOR3AND2
Mode Max_absolute Avg_absolute Max_relative Avg_relative (for Vdefect-Vgood)

TRAN -1.07 V -72.22 mV >999.99% >999.99%
Lowest-level instance for |Vdefect-Vgood| < V_observable at all port signals: X4
Largest |Vdefect-Vgood| observed: 962.378mV at port 7, name ZN
Example Output
defectsim_tolerance_summary File
The following is an example defectsim_tolerance_summary file.
Likelihood-weighted +/- 99% confidence interval

Safe defects: 77.66% +/- 10.71% (% that pass Spec)
Latent defects: 3.27% +/- 5.21% (% that fails SM)
Monitor coverage: 27.49% +/- 11.39% (% detected by SM)
Defect tolerance (SPFM): 93.13% +/- 6.94% (% that pass Spec, or detected
by SM)
Diagnostic coverage (DC-Res): 63.64% +/- 12.19% (% of Spec-failing defects
detected by SM)
Diagnostic coverage (DC-Lat): 83.57% +/- 9.65% (% not latent of defects in SMs)
Non-latent defects (LFM): 95.92% +/- 5.67% (% not latent of tolerated
defects in Func + SMs)
Probabilistic metric (PMHF): 5.1e-12 (likelihood of untol. defects,
w.r.t. 1e-12/hr)
Safe undetected: 65.64% +/- 12.05% (% that pass Spec, and not
detected by SM)
Safe detected: 12.02% +/- 8.60% (% that pass Spec, but detected
by SM)
Unsafe detected: 15.47% +/- 9.44% (% that fail Spec, and detected
by SM)
Unsafe undetected: 6.87% +/- 6.94% (% that fail Spec, but not
detected by SM)
Legend
- no failure or detection
U failed Upper bound for parameter
L failed Lower bound for parameter
D Detected by a digital output of Function
F Specification or digital output Failed
F Monitor indicated Fail
N defect Not tolerated (Function failed but not indicated by SM)
Parameter
1 Func Safety Delta Cumul. 99% Conf. Bin
Dig Spec Mon Tol RL Coverage Coverage Interval Bin RL ISO_Class
Defect
D761 - - - - - 0.005 1.72% 1.72%
D1284 - - - - - 0.975 1.75% 62.19% +/-12.28% 1 27.019 Safe
D1011 - - - F - 0.002 1.72% 1.72%
D1291 - - - F - 0.450 1.72% 15.47% +/-9.44% 2 1.165 MPF-Det
D824 U - F - N 0.021 1.72% 5.16%
D390 U - F - N 0.129 1.72% 6.87% +/-6.94% 4 0.177 Residual
D1290 - - - - - 0.450 1.72% 1.72%
D1292 - - - - - 0.450 1.72% 3.44% +/-5.31% 5 0.900 MPF-Lat
Parameters LowerLimit Defect0Circuit UpperLimit Coverage +/- 99% confidence interval

1 IDDQ1_spec -1.000000e-6 8.052300e-06 1.500000e-5 17.18% +/- 9.80%
Func Dig 1.72% +/- 4.11
UNTOLERATED DEFECTS======
(ordered by decreasing likelihood)
Defect 390: [post-layout, relative likelihood 0.129] resistor R_x_PM_DFFR_X1\%5_r36 open
circuit floating high, in instance X2 of subcircuit Dffr
ACTIVE X2.R_x_PM_DFFR_X1\%5_r36 X2.N_5_M1_g X2.N_5_M18_g 1.294800E+02
* Alter 9 defect location in subckt names: Dffr
The metrics in the defectsim_tolerance_summary file are calculated as follows:
Safe defects
• % that do not cause Function fail and are not Latent, of all defects in Function+SM
Latent defects
• % that are Latent, of all defects in Function+SM

Safety Mechanism coverage
• % detected by SM, of all defects that cause Function fail

Defect tolerance (SPFM)
• From ISO 26262: (λMPF + λS) / (λRF + λMPF + λS)
• % that are tolerated, of all defects in Function+SM

Diagnostic coverage (DC-Res)
• From ISO 26262: λMPF / (λRF + λMPF)
• % that are tolerated, of all defects in Function+SM that cause Function fail
Diagnostic coverage (DC-Lat)
• From ISO 26262: 1 – λMPF,L / λ
• % that are not detected by 2nd-level SMs, of all Latent defects in 1st-level SMs
Non-latent defects (LFM)
• From ISO 26262: 1 – λMPF,L/(λ – λRF)
• % that are not Latent, of all tolerated defects in Function+SM

Probabilistic metric (PMHF)
• Failure rate due to untolerated or latent defects

• [(100% – %SPFM + %Latent)×RLsum] × $pmhf_reference_fit
Pass, undetected
• % that do not cause a Function fail and are not detected by SM, of all defects in
Function+SM
Pass, detected
• % that do not cause a Function fail but are detected by SM, of all defects in
Function+SM
Fail, detected
• % that cause a Function fail but are detected by SM, of all defects in Function+SM
Fail, undetected
• % that cause a Function fail and are not detected by SM, of all defects in Function+SM
Usage Notes
• In the defect matrix:
o U — Indicates test failed Upper limit for parameter in that column, and is detected.
o L — Indicates test failed Lower limit for parameter in that column, and is detected.
o - — Indicates test did not fail at that sample time (hence, not detected yet), or the
parameter in that column did not fail either limit.
o D — Indicates test failed at that sample time, and is detected.
o d — Indicates simulation stopped for that defect at D, so defect is already detected,
or the parameter in that column could not be measured and is hence detected.
• The undetected defects are listed in decreasing likelihood. Each randomly-selected low-
likelihood defect represents many defects and should, therefore, be treated as equally
important to detect.
• The table of voltages and percentages for each undetected defect can help you diagnose
why the defect was not detected. Each value is a summary of the differences between the
voltages across the potential defect site (during defect-free simulation) and the voltages
across the defect (during defect simulation). Max_absolute is the maximum difference
between the two voltages at each sampling instant (voltages are sampled once every
sampling_interval), and Avg_absolute is the average difference. If a test is sensitive to
very small voltages, then the percentage difference will probably be more useful:
Max_relative is the maximum percentage difference between the two voltages relative
to the defect-free value, and Avg_relative is the average percentage difference. In all
cases, a small difference indicates that the defect site is not being stimulated by the test
pattern (i.e, the defect site is not controllable), and this is likely why the defect is
undetected; if the difference is large, then it is more likely that the observation instant,
test access, or the test limits should be changed (i.e., the defect site is not observable).
• The confidence interval follows the general trend shown in Figure 9-2.
Figure 9-2. 95% Confidence Interval vs. Defect Coverage and Defects Simulated
• The 99% Confidence Interval is equal to 1.3 times the 95% Confidence Interval.
• Here are example steps for measuring ISO 26262 metrics for a Function circuit (FUNC)
that has a voltage monitor as its Safety Mechanism (SM).
First Step — Measure DC-Latent for the SM portion of the CUT, by applying an
intentionally erroneous stimulus directly to the inputs of the SM so that its expected
output is the value that would put a system containing Function into a safe state. Assume
one SM comprises two voltage monitors that each output logic 1, one whenever the
monitored Function voltage is too low, and the other whenever that voltage is too high.
o Create FUNC-sm1.defectsim file with all the usual settings for files, tests, RL values,
etc. for the FUNC+SM. Then create SM.defectsim containing only test-related
settings, such as sampling_interval, simulation_end_time, test_parameters, etc. The
digital output (that puts the system into a safe state) of the SM must be listed for
digital_output_signals, and set digital_output_signals_safety "" (unless the SM has
its own BIST with its own outputs). Set defects_only_in_elements ^X1\. for
example, if the SM instance is X1, so that defects are only injecting in the SM. All
other setting will be obtained automatically from the FUNC.defectsim file (which
must contain include_Func_for_DCLat_simulation on).
o Create a testbench in FUNC-sm1.circuit that applies a marginally too-low voltage to
the SM, immediately followed by a marginally too-high voltage (in FUNC-
sm1.defectsim, list the two voltage monitor output nodes in digital_output_signals).
Set sampling_interval with sufficient timing resolution to sample the digital output
values of interest soon enough.
o Run create_def_sites and create_def_to_sim.
o During sim_def_free, Tessent DefectSim will capture the logic 1 values.
o During sim_def –calc_dclat, any defects that cause the output to be logic 0 are latent
defects and reported as such in FUNC-sm1.defectsim_dclat_summary.
o If there are multiple SMs, do the above steps for each SM, eg. FUNC-sm1, FUNC-
sm2.
Second Step — Measure all metrics for the Function circuit, with its one or more SM
circuits.
o Create a testbench in FUNC.circuit that applies one or more of the stimuli for which
the Function+SM must achieve safety goals, i.e. always be safe.
o In FUNC.defectsim, list the Function’s digital outputs in digital_output_signals, but
list the two SM output nodes in digital_output_signals_safety. If you are
simultaneously simulating a manufacturing test and an in-usage specification test,
and the SM’s outputs are accessible by the tester during manufacturing test, the
output nodes should be listed in both lines, otherwise just in the latter.
o Also list the safe value for the SM nodes as digital_output_signals_safe_mode 1
o Also list any parameters measured by the manufacturing test for test_parameters,
and any that are safety goals (typically with looser limits) for
test_parameters_safety. If you are only simulating an in-usage specification test for
assessing functional safety, then do not list any test_parameters or
digital_output_signals; only list those ending in _safety.
o Run create_defect_sites_list, create_defects_to_sim, and sim_defect_free.
o Run simulate_defects -calc_lfm FUNC-sm1.defectsim_dclat_summary
o If Function uses two of SM1, then instead run:
sim_def –calc_lfm FUNC-sm1.defectsim_dclat_summary 2
o If Function uses one SM1 and two SM2, then instead run:
sim_def –calc_lfm FUNC-sm1.defectsim_dclat_summary 1 FUNC-
sm2.defectsim_dclat_summary 2
Chapter 10
Step 8 - Simulate Undetected Defects
Run the following command to simulate only defects not detected by previous defect
simulations run for different testbenches or process corners.
If you have additional testbenches, each must have a <CUT>-<test>.defectsim, <CUT>-
<test>.circuit and/or <CUT>-<test>.testbench, and this command must be invoked using
<CUT>-<test> instead of <CUT>.
simulate_defects -undetected <summary_file> [-suffix <suffix>]
You may use either CUT-<test>, or -suffix <suffix>, or both.
Use the -suffix suffix option to simulate additional process corners when the same
<CUT>.good_output_vector and the same parametric tests can be used. The undetected defects
are those listed in summary_file; the details for each defect are fetched from
<CUT>.circuit_alters in the defectsim_outdir directory. <CUT>.testbench is used unless
<CUT>.testbench_<suffix> is found. process_file is used unless process_file_<suffix> is
found.
If the subcircuit contents change, even slightly, for different process corners, then you will need
to re-run create_consolidated_subcircuits to fetch those subcircuits and the corner's process file
(which you must rename to be the same as the one you used initially but with a _suffix that you
must reference with the -suffix option. Do not re-run create_defect_sites_list or
create_defects_to_simulate, since you must use the exact same <CUT>.potential_defect_list.
• Addtional required input files

o <CUT>-<test>.defectsim (if applicable)
o <CUT>-<test>.circuit (if applicable)
o process_file or process_file_<suffix>
o <CUT>.sim_defects_list
o <CUT>.good_output_vector (in ./defectsim_outdir)
o <CUT>.defectsim_summary file
• Output files
o <CUT>.defectsim_summary_<suffix>
o ./defect_outdir-<test> or ./defectsim_outdir-<test>_<suffix>
Step 8 - Simulate Undetected Defects
Usage Notes
Usage Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Usage Notes
In your current directory for tests at different test conditions and process corners, you may have
many testbenches, each with a different _suffix, and many process files, each with a different
_suffix, that use the same .defectsim , .good_output_vector, and test the same parameters. Here
is an example:
1. Create files proc and ABC.circuit for initial nominal simulations.
2. Create two additional testbenches:
ABC-maxvdd.circuit
ABC-minvdd.circuit
3. Create two process corners (<CUT>.defectsim contains process_file proc):
proc_slow
proc_fast
4. ABC simulate_defect_free, ABC-maxvdd simulate_defect_free, and ABC-minvdd
5. ABC simulate_defects — Simulates nominal testbench and nominal proc
6. ABC simulate_defects -undetected ABC.defectsim_summary -suffix slow — Simulates
nominal testbench and proc_slow
7. ABC simulate_defects -undetected ABC.defectsim_summary_slow -suffix fast —
Simulates nominal testbench and proc_fast
8. ABC-maxvdd simulate_defects -undetected ABC.defectsim_summary -suffix
typical_summary — Simulates ABC-maxvdd and nominal proc
9. ABC-minvdd simulate_defects -undetected ABC-maxvdd.defectsim_summary -suffix
typical_summary — Simulates ABC-minvdd and nominal proc
10. ABC-maxvdd simulate_defects -undetected ABC-maxvdd.defectsim_summary -suffix
fast — Simulates ABC-maxvdd and proc_fast
11. ABC-minvdd simulate_defects -undetected ABC-mavdd.defectsim_summary_fast
-suffix slow — Simulates ABC-minvdd and proc_slow
12. create_combined_summary -in { list all summaries }
Chapter 11
Step 9 - Combine Summaries
Run either of the following commands to combine multiple summary files into a single overall
summary. The summary files can have any name and be in any directory, but they must have
been generated for the same CUT and defects (and random seed)—any differences result in an
Error message. The tests, test limits, test conditions, and process may differ. The output file
includes the <CUT>.defectsim parameter settings that are common to all the summary files.
create_combined_summary -input_files { <summaryFile1> <summaryFile2 ... } [-replace]
[-output_file <filename>]
create_combined_activity -input_files { <good_results1> <good_results2> } [-replace]
[-output_file <filename>]
create_combined_defect_tolerance -input_files { <tolerance_summary1>
<tolerance_summary2> } [-replace] [-output_file <filename>]
create_combined_summaries_of_circuits -input_files { <summary1> <summary2> ... }
[-output_filename <filename>] [-replace]
Only the last command listed above combines summaries from different circuits (with different
defect lists).
• Required input files

o summaryFile1, summaryFile2, ... or good_results1, good_results2, ...
o At least one of the summary files must list in its DEFECTS SIMULATED section all
the defects in <CUT>.sim_defect_list; this is typically the summary file from the
first run of simulate_defects.
• Output files
o <CUT>.defectsim_summaries_combined or <CUT>.defectsim_activity_combined
or <CUT>.defectsim_tolerance_combined
Weighted defect coverage, defect detection matrix, and defects that were not
detected by any of the tests.
Example:
Combined likelihood-weighted defect coverage: 71.43%
DefectSim combined summary file

Summary Files
000
123
Defect
D3 ---
D7 DD-
D12 -DD
D13 DDD
D14 ---
D16 D-D
D24 D--
Summary filenames FileDate & Time Coverage

OA.defectsim_summary 11/27/2013 14:02:20 57.43%
OA.defectsim_oldsummary 11/25/2013 10:31:09 50.85%
sim2/OA.defectsim_summary 11/28/2013 12:55:17 48.11%
FILES===================
Top circuit: OA.circuit
Process files:
1. subcircuits/AMI.process_nom
GENERAL=================
Number of defects simulated 7 out of 26
Defects were randomly selected using seed 1059826082
EXCLUSIONS, DESIGN/PARASITICS, RELATIVE LIKELIHOODS
UNDETECTED DEFECTS, ordered in decreasing likelihood
Defect 14 [pre-layout, relative likelihood 1.000] transistor

stuck-off,
in instance X1.X3.X21 of subcircuit OPAMP
* Alter 3 defect location in subckt names: TOP.AMPLIFIER.OPAMP
Defect 3 [post-layout, relative likelihood 0.231] open circuit,

floating high, in instance X1.X2.X17
* Alter 29 defect location in subckt names: TOP.BIAS.MIRROR
DEFECTS SIMULATED
1 .ALTER # D3: RESISTANCE R144 50% LOW, IN INSTANCE X1 OF
SUBCIRCUIT OA
2 .ALTER # D7: RESISTANCE RFB 50% LOW, RL= 1.000
...
Example console listing:
----------------------------------
Reading OA.defectsim_summary_1
Comparing files
Merging results
Creating OA.defectsim_summaries_combined
DefectSim closed.
Chapter 12
Accuracy of Reported Coverage
There are sources of inaccuracy in the Tessent DefectSim tool’s estimate of defect coverage,
and average quality level, which are described in detail in this section.
Topics include the following:
Relative Likelihoods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Process Corners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Number of Defects Simulated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Relative Likelihoods
Tessent DefectSim provides an estimate of a test’s defect coverage, weighted by your estimates
of the relative likelihood of each defect type. As you use Tessent DefectSim, you will probably
adjust these likelihoods to make the results more consistent with observed defects or failure
modes, and thus make the coverage estimate more accurate with continued usage from design to
design.
If all the relative likelihoods were accurate, then an accurate estimate of average quality level
can be calculated, in defective parts per million (DPPM), for devices passing these tests; the
defect-level would be calculated using the Williams-Brown equation: DL = 1 - Y(1-C), where DL
is defect level (multiply by 1000000 to get DPPM), Y is true yield (estimated using test yield),
and C is weighted fault coverage. The Seth-Agarwal equation is also commonly used.
Unfortunately, some likelihood dependencies cannot be modeled in the present version of
Tessent DefectSim, including the following:
• The likelihood of shorts across parasitic capacitances depends on the mask levels, but
netlists may not contain this information, and if they do, Tessent DefectSim presently
does not read that information (as it does for parasitic resistances). For example, shorts
between adjacent wires are more likely than shorts between mask levels, however, inter-
layer capacitances are typically much smaller and will thus have much smaller RL
values anyway.
• Large contacts (between metal and diffusion) are less likely to have an open defect, but
all contacts are treated as equally likely to have an open.
Accuracy of Reported Coverage
Process Corners
Process Corners
The most likely value of any process parameter is its nominal value, so you should perform fault
simulation for typical process parameters first (this is required by the proposed IEEE P2427
standard). It is very likely that a defect detected for the typical process will also be detected at
process corners, so simulation time can be saved by not re-simulating the detected defects at
process corners. Some defects might only be detected at a process corner, for instance parallel
transistors added to ensure sufficient drive for that process corner. However, some defects
might be detected only at typical process and not at process corners.
Number of Defects Simulated

The precision of the defect coverage estimate is roughly (depending on the weighting)
proportional to the square root of the number of defects simulated.
And randomly selecting defects according to their likelihood of occurrence allows higher
estimation accuracy than any other random selection method—for the distribution of
likelihoods shown in Figure 1-1 on page 15 estimation accuracy is the same as would be
achieved for 4X more defects selected with simple random sampling (SRS).
When there is a large number of potential defect sites (thousands or millions), the number of
such potential sites is mostly irrelevant. An analogous case is a political survey prior to a
national election involving a hundred million voters—it is only necessary to poll a few thousand
randomly selected voters to produce an estimate that is “accurate to within 3 percentage points,
19 times out of 20”. It is essential, though, that the selection be truly random so that there is no
bias in the estimate.
Appendix A
Example Complete Testcase
You can create any of three different testcases that are ready to run, using the following
command:
defectsim <CUT> create_example_testcase [-directory my_directory]
• CUT must be one of the following: EXAMPLE_OA, EXAMPLE_PLL,

EXAMPLE_PLL2, EXAMPLE_TMRFF
The command will create a sub-directory (default name is <CUT>) containing all needed files
and a README file. EXAMPLE_OA is a simple op-amp (similar to the example testcase text
shown below), and all steps can be run in less than a minute using only Eldo. EXAMPLE_PLL
is a simple PLL, for which all steps can be run in a few minutes using Eldo and VerilogA.
EXAMPLE_PLL2 is the same PLL with more hierarchy and Verilog RTL and hence it
simulates in Questa ADMS. EXAMPLE_TMRFF is a triple-module-redundancy flip-flop, with
all lines in a single file input.scs, in Spectre format; this example demonstrates
create_consolidated, Spectre simulation, and measuring defect tolerance, and simulates in less
than a minute.
The following is a complete example testcase.
OA.circuit
* this file calls only the op-amp, and uses it in inverting mode
X1 Vpin Vnin Vout VDDL VDD VSS OA
Rin Vin Vnin 100k
Rfb Vout Vnin 100k
Rdummy vss 0 1e-12
OA.sub
* ITC97 benchmark op-amp, including AMI process file (next page)
.subckt OA Vpin Vnin Vout VDDL VDD VSS
M105 VDD net14 net14 VDD CMOSP L=4u W=15u
R144 net14 VSS 110k
M116 VDDa net14 net15 VDD CMOSP L=4u W=35u
M135 VDDb net14 Vout VDD CMOSP L=4u W=100u
M124 net15 Vnin net32 VDD CMOSP L=4u W=60u
M125 net15 Vpin net19 VDD CMOSP L=4u W=60u
M127 net32 net32 VSS VSS CMOSN L=4u W=27.5u
M126 net19 net32 VSS VSS CMOSN L=4u W=27.5u
M136 Vout net19 VSS VSS CMOSN L=4u W=100u
C145 net19 net22 1.27p
R145 net22 Vout 8.75k
* manually added parasitic capacitances
cc_1 net15 net32 0.1f
cc_2 net19 net32 0.1f
cc_3 net14 VSS 0.1f
* manually added parasitic resistances
rr_4 VDDa VDD 10
rr_5 VDDb VDD 20
* manually added parasitic inductance
Lin VDDL VDD 1n
.ends
OA.defectsim
top_circuit_type prelayout
process_file AMI.process_nom
schematics_directory subcircuits
target_number_defects_to_simulate 30
sampling_start_time 5u
sampling_interval 10u
simulation_end_time 150u
sampling_threshold_voltage 1v
digital_output_signals Vout
C_parasitic 10f
R_parasitic 50
L_parasitic 1n
RL_opens_default 1
float_high_voltage 3
open_defect_R_ratio 20
short_defect_resistance 90
open_defect_resistance 5G
stuck_on_defect_resistance_LW 1500 1500900 CMOSN 1800 CMOSP
RL_column 65
test_parameters propdelay thd pk2pk
OA.testbench
* Testbench for simple op-amp
vVDD VDDL 0 3v
vVSS VSS 0 0
Cout Vout VSS 0.5e-12

* STIMULUS
* sin(v0 va freq )
vin Vin 0 sin(1v 0.5v 10k )
vref Vpin 0 1v
* ANALYSIS
.four label=freqresp v(vout) tstart=50u tstop=150u nbpt=32
.extract four label=thd
+ disto(four(freqresp), 10k, 10k, 100k) lbound=0 ubound=10
.extract tran label=propdelay

+ tpddd(v(vin), v(vout),vth=1) lbound=49n ubound=51n
.extract tran label=pk2pk

+ max(v(vout), 50u, 150u)-min(v(vout), 50u, 150u) lbound=900m ubound=1100m
* SAVE ALL NODE VOLTAGES FOR VIEWING

.probe v
AMI.process_nom
* from http://www.mosis.org/Technical/Testdata/ami_c5n_corner_bsim3.txt
* This is a 0.5/0.6 um process, measured values for typical n, typical p
* Parameters are extracted from process corner wafers provided by AMI
* DATE: May 22/02, Tech: AMI_C5N, LOT: T22Y_TT (typical), WAF: 3104
* Temperature_parameters=Optimized
.option compat * this line inserted for Eldo
.MODEL CMOSN NMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 1.39E-8
+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = 0.6696061
+K1 = 0.8351612 K2 = -0.0839158 K3 = 23.1023856
+K3B = -7.6841108 W0 = 1E-8 NLX = 1E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 2.9047241 DVT1 = 0.4302695 DVT2 = -0.134857
+U0 = 458.439679 UA = 1E-13 UB = 1.485499E-18
+UC = 1.629939E-11 VSAT = 1.643993E5 A0 = 0.6103537
+AGS = 0.1194608 B0 = 2.674756E-6 B1 = 5E-6
+KETA = -2.640681E-3 A1 = 8.219585E-5 A2 = 0.3564792
+RDSW = 1.387108E3 PRWG = 0.0299916 PRWB = 0.0363981
+WR = 1 WINT = 2.472348E-7 LINT = 3.597605E-8
+ DWG = -1.287163E-8
+DWB = 5.306586E-8 VOFF = 0 NFACTOR = 0.8365585
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.0246738 ETAB = -1.406123E-3
+DSUB = 0.2543458 PCLM = 2.5945188 PDIBLC1 = -0.4282336
+PDIBLC2 = 2.311743E-3 PDIBLCB = -0.0272914 DROUT = 0.7283566
+PSCBE1 = 5.598623E8 PSCBE2 = 5.461645E-5 PVAG = 0
+DELTA = 0.01 RSH = 81.8 MOBMOD = 1
+PRT = 8.621 UTE = -1 KT1 = -0.2501
+KT1L = -2.58E-9 KT2 = 0 UA1 = 5.4E-10
+UB1 = -4.8E-19 UC1 = -7.5E-11 AT = 1E5
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 2E-10 CGSO = 2E-10 CGBO = 1E-9
+CJ = 4.197772E-4 PB = 0.99 MJ = 0.4515044
+CJSW = 3.242724E-10 PBSW = 0.1 MJSW = 0.1153991

+CJSWG = 1.64E-10 PBSWG = 0.1 MJSWG = 0.1153991
+CF = 0 PVTH0 = 0.0585501 PRDSW = 133.285505
+PK2 = -0.0299638 WKETA = -0.0248758 LKETA = 1.173187E-3
+AF = 1 KF = 0)
*
.MODEL CMOSP PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 1.39E-8
+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = -0.9214347
+K1 = 0.5553722 K2 = 8.763328E-3 K3 = 6.3063558
+K3B = -0.6487362 W0 = 1.280703E-8 NLX = 2.593997E-8
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 2.5131165 DVT1 = 0.5480536 DVT2 = -0.1186489
+U0 = 212.0166131 UA = 2.807115E-9 UB = 1E-21
+UC = -5.82128E-11 VSAT = 1.713601E5 A0 = 0.8430019
+AGS = 0.1328608 B0 = 7.117912E-7 B1 = 5E-6
+KETA = -3.674859E-3 A1 = 4.77502E-5 A2 = 0.3
+RDSW = 2.837206E3 PRWG = -0.0363908 PRWB = -1.016722E-5
+WR = 1 WINT = 2.838038E-7 LINT = 5.528807E-8
+ DWG = -1.606385E-8
+DWB = 2.266386E-8 VOFF = -0.0558512 NFACTOR = 0.9342488
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.3251882 ETAB = -0.0580325
+DSUB = 1 PCLM = 2.2409567 PDIBLC1 = 0.0411445
+PDIBLC2 = 3.355575E-3 PDIBLCB = -0.0551797 DROUT = 0.2036901
+PSCBE1 = 6.44809E9 PSCBE2 = 6.300848E-10 PVAG = 0
+DELTA = 0.01 RSH = 101.6 MOBMOD = 1
+PRT = 59.494 UTE = -1 KT1 = -0.2942
+KT1L = 1.68E-9 KT2 = 0 UA1 = 4.5E-9
+UB1 = -6.3E-18 UC1 = -1E-10 AT = 1E3
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 2.9E-10 CGSO = 2.9E-10 CGBO = 1E-9
+CJ = 7.235528E-4 PB = 0.9527355 MJ = 0.4955293
+CJSW = 2.692786E-10 PBSW = 0.99 MJSW = 0.2958392
+CJSWG = 6.4E-11 PBSWG = 0.99 MJSWG = 0.2958392
+CF = 0 PVTH0 = 5.98016E-3 PRDSW = 14.8598424
+PK2 = 3.73981E-3 WKETA = 5.292165E-3 LKETA = -4.205905E-3
+AF = 1 KF = 0)
Appendix B
Recommended Usage Flows
First get simulation of original circuit and tests running cleanly in Eldo or AFS. Then, to
measure the defect coverage of a manufacturing test using command line interface, perform the
following tasks (detailed descriptions for each setting and command are provided earlier in this
Manual and in Getting Started With DefectSim in ADE):
1. Run the following commands:
create_defectsim_config
create_con_sub -schem -input <netlist_including_everything> \
-create_all -force
2. In <CUT>.defectsim,
a. Add all top-level digital output nodes as digital_output_signals.
b. Set sampling_start_time to a time after all transients have settled, and just before an
active edge of a relevant input clock.
c. Set sampling_interval to an integer multiple of the period of the clock used by output
digital signals; simulation_end_time divided by sampling_interval should be less
than 100, but may be as large as 10,000.
d. Set sampling_activity_delay so its value plus sampling_start_time produces a time
that is in the middle of internal logic signal transitions (i.e., when digital signals are
most active). Alternatively, set sampling_activity_start_time instead, and optionally
set sampling_activity_interval to a different value than sampling_interval.
e. Set simulation_end_time, if it was not set automatically to value in your .TRAN line.
f. Ensure all measurements that are tests (with bounds) have labels, and that they are
listed for test_parameters. If they do not meet this criteria, you must modify the
original netlist and rerun create_consolidated_subcircuits, as in 1 above.
g. Use default settings, or choose a unit area for your technology, for example 1µm2
and then set relative likelihoods for each defect type for that area, as follows:
i. Set unit_RL_M_design_LW to 1e-12 (i.e., 1 µm2).
ii. Set unit_RL_C_design to capacitance that would occupy 1 µm2, e.g., 1f.
iii. Set unit_RL_R_design to resistance that a poly resistor with typical width would
have if its length x width was 1 µm2.
iv. Set RL_diode_short and RL_diode_open to relative likelihood of a 1 µm2 diode

having a defect, compared to likelihood of 1 µm2 capacitor having a defect.
v. Set RL_bipolar_base_open and RL_bipolar_emitter_open to relative likelihood
of a 1 µm2 bipolar transistor having a defect, compared to likelihood of 1 µm2
capacitor having a defect.
3. Run create_defect_models -out my -type ieee2427hard -add
4. Run create_primitive_subcircuit_list -out my.primitives
o Examine the generated list to see that it only contains subcircuits that you want
treated as primitives: apply defects to them but not to the elements within. Also
check that each primitive is assigned an appropriate default model, for example,
ieee2427hard_R is assigned to resistors, ieee2427hard_M is assigned to transistors,
and so on. If there are incorrect assignments, consider setting primitive_libraries and
X_primitive_subcircuits, where X is R, C, D, or M, to get the exact list of primitives
that you want.
5. Run create_fault_models -in my.primitives -out my -add
6. Run defectsim <CUT> create_defect_sites_list
a. Examine the generated <CUT>.potential_defect_list file to see if relative likelihood
(RL) values have a reasonable distribution (you can check the histogram data at
bottom of file to get an overview).
i. If RL values are above 1000, check whether they are part of the circuit-under-
test or they are off-chip circuitry. For the latter case, optionally add the
no_defects_in_top_elements setting to prevent them being listed as potential
defect sites, then rerun create_defect_sites_list.
b. Exclude any non-CUT circuit elements from defect injection, as follows:
i. Exclude any subcircuit names using no_defects_in_subcircuit_names.
ii. Exclude any subcircuit instances using no_defects_in_subcircuit_instances.
iii. Exclude any top-level elements using no_defects_in_top_elements.
iv. Exclude any dummy or spare instances using no_defects_in_elements.
c. If you added any no_defects_in_subcircuit_*, then re-run create_defect_sites_list.
i. Examine the generated .potential_defect_list file again.
7. Run defectsim <CUT> create_defects_to_simulate.
a. Initially use the default target number of defects to simulate: 10. If the number
selected is much less than the target:
i. Check<CUT>.sim_defects to see whether the defects selected have unusually
large RL values - if so, review step 4 above.
ii. Check whether <CUT>.potential_defect_list has a large number of defects with
exactly the same RL value, or RL=0 - if so, review step 3.g above.
8. Run defectsim <CUT> simulate_defect_free.
a. If any Errors are reported, check defectsim_outdir/<CUT>.good_cir.chi for an
explanation.
b. If any FAILs are reported, check the measured values and test limits in
<CUT>.good_results.
c. If no Errors or Fails are reported, check Activity coverage, and if it is less than 80%
do the following:
i. Check that V_active, I_active, Vac_active, and Iac_active are appropriate for
your circuit.
ii. Check if sampling_start_time + sampling_activity_delay + N×sampling_interval
produces time instants in the middle of logic transitions.
iii. Modify the stimulus to activate all portions of the circuit, or do this with another
testbench and combine the activity reports using create_combined_activity.
d. If you make changes to tests, re-run create_defects_to_simulate and
simulate_defect_free.
e. If you make changes to the circuit, also re-run create_defect_sites_list.
9. Run defectsim <CUT> simulate_defects.
a. If any Errors are reported, check defectsim_outdir/<CUT>.defect_cir.chi for an
explanation.
b. If no Errors, examine <CUT>.defect_summary.
i. Check how each defect was detected - parameter failed U or L test limit, or
digital output signal sample, or neither.
ii. Check details for undetected defects at bottom of file—see whether each is
undetected because of no significant change in voltage across the defect site
before and after defect injected (Vdefect-Vgood), and whether the reported
changes in subcircuit port signals are large enough to be observable.
To measure the defect tolerance and other ISO 26262 metrics of a circuit that has a Function
portion and a Safety Mechanism (SM) portion, using command line interface, perform the
following tasks:
1. Same as 1. for manufacturing test coverage earlier in this Appendix, except the circuit
stimulus should represent stimulus the circuit will receive in usage, and the test limits
must be safety goals.
2. Same as 2. for manufacturing test coverage earlier in this Appendix, except add all top-
level digital output nodes of the Function as digital_output_signals, add all top-level
digital output nodes of the SM as digital_output_signals_safety, and if the SM output is
only valid at certain times add digital_output_signal_safe_mode 1 (or 0) to indicate the
SM output logic value that activates a safe state.
3. Create <CUT>-<SMtest>.circuit
a. It must contain the same circuitry as <CUT>.circuit generated by
create_consolidated_subcircuits, but the stimulus applied must be applied directly to
the inputs of the SM and it must be marginally faulty; the input to the main Function
may be inactive. The marginally faulty stimulus should represent signal values that
the SM would receive from the Function when there is a marginally detectable
defect in the Function. For example, the inputs to an SM that monitors a regulator’s
output voltage, specified as Vnominal ±100 mV, would be Vnominal +105 mV for
some time interval, and then Vnominal -105 mV for some time interval. The output
of the SM should be at its safe-state-asserting value for all digital samples.
4. Create <CUT>-<SMtest>.defectsim with only these lines
a. SM_elements ^xsm, where xsm is a Unix regexp identifying characters of instance
names that are in the SM: typically a subcircuit instance and perhaps some single
elements.
b. digital_output_signals SMout, where SMout is the digital output of the SM
c. digital_output_signals_safety "", unless there is a BIST that tests the SM, in which
case provide its output node instead of "".
d. Set sampling_start_time, sampling_interval, simulation_end_time corresponding to
the stimulus used in <CUT>-<SM>.circuit.
5. Run the following commands and examine their working directory output files:
defectsim <CUT>-<SMtest> create_defect_sites_list
defectsim <CUT>-<SMtest> create_defects_to_simulate
defectsim <CUT>-<SMtest> simulate_defect_free
defectsim <CUT>-<SMtest> simulate_defects
defectsim <CUT> create_defects_to_simulate
defectsim <CUT> simulate_defect_free
defectsim <CUT> simulate_defects -calc_lfm <CUT>-
<SMtest>.defectsim_dclat_summary
Appendix C
Using UNIX Regular Expressions (regexp)
Some parameters in the .defectsim file allow you to include or exclude subcircuit instances and
names, nodes, and node pairs, by using UNIX regular expressions. These are very powerful, but
also very exact. This appendix provides handy guidelines.
To check an expression’s interpretation, go to the following URL:
http://www.regexper.com/
The “node name” below could also be “subcircuit name” or “subcircuit instance”; note that
subcircuit instances and node names may be hierarchical.
^ match expression at the start of a node name:
^n1 selects n1abc, and n1xy, but not an1c
$ match expression at the end of a node name:
n1$ selects abcn1, and xyn1, but not an1c
\ turn off the special meaning of the next character:
^n\^1 selects n^1abc, and n^1xy, but not n\^1
[] match any one of the enclosed characters; "-" indicates range:
a[1-58] selects a2 and a8, but not a6
[^ ] match any one character except those enclosed in [ ]:
b[^1-58] selects b0 and b7, but not b4
. match any single character:
c1. selects c12, and c19, but not c1
* match zero or more of the preceding character (or expression):
d1* selects d1, and d11, but not d12
? match zero or one of the preceding character (or expression):
h1? selects h1, and h11, but not h111
+ match one or more of the preceding character (or expression):
j1+ selects j11, and j111, but not j1
\{x,y\} match x to y occurrences of the preceding character:
e1\{2,4\} selects e11, and e1111, but not e1
\{x\} match exactly x occurrences of the preceding character:
f[1-4]\{3\} selects f123, and f234, but not f145
Using UNIX Regular Expressions (regexp)
\{x,\} match x or more occurrences of the preceding character:

g[6-9]\{2,\} selects g678, and g9876, but not g6
• An expression must not start with *, ?, or +
• ABC* does not mean “ABC followed by zero or more characters”; it means “ABC
followed by zero or more occurrences of C”.
o If you want to select nodes that contain ABC, just use ABC
o If you want only nodes that start with ABC, use ÂBC
o If you want only nodes that end with ABC, use ABC$
o If you want only nodes that have ABC in the middle, use .ABC.
Appendix D
Example File Preparation Procedure
Here are detailed steps to prepare files of a circuit for running in Tessent DefectSim, for a top-
level file called example.cir that contains Eldo commands, voltage sources, measurements, calls
to subcircuits, libraries, models and directories.
1. Check that the file runs cleanly in current directory – enter the command:
% eldo example.cir or eldo example.scs -spectre
Alternatively, if your circuit was simulated directly from a GUI, and you only have a
example.chi file, then you can produce the .cir file by running command:
% chi2cir example.chi example.cir
2. Create a text file EXAMPLE.defectsim with the following line (at least) that points to an
empty or non-existing directory:
schematics_directory <directory> and (if file is in Spectre format)
spectre_lang on
3. To fetch all needed subcircuit netlists into myschematics directory, and all lines for the
top-level circuit, testbench, and process, enter the command:
% defectsim EXAMPLE create_consolidated_subcircuits -schematics \
-input_files example.cir -create_all -no_comments
4. In EXAMPLE.circuit
a. Delete any analysis lines except .AC or .DC.
b. In any .EXTRACT or .MEAS lines, insert
LBOUND=<lower_limit>UBOUND=<upper_limit>.
For example:
EXTRACT TRAN LABEL=gain v(out)/v(in) LBOUND=0.9 UBOUND=1.1
c. If there is circuitry in which you do not want any defects injected because it is part of
surrounding circuitry or part of the testbench, then cut and paste it into new file
EXAMPLE.testbench.
Example File Preparation Procedure
5. Edit EXAMPLE.defectsim: to add at least the following essential information:

top_circuit_type prelayout // or postlayout
process_file EXAMPLE.process
target_number_defects_to_simulate 10 // small number, at first
digital_output_signals out1 out2 // ‘digital’ outputs
sampling_start_time 99ns // typical for 100ns clock

sampling_interval 100ns
simulation_end_time 10us
test_parameters gain slewrate // labels from .EXTRACT
6. Enter the command (usually runs in <1 minute)

% defectsim EXAMPLE create_defect_sites_list
7. If previous step was successful, enter the command

% defectsim EXAMPLE create_defects_to_simulate
8. If previous step was successful, then it appears that all files have been prepared
correctly, and you can proceed with simulate_defect_free -view_lowest, if you have
layout netlists, and then defect simulation.
Appendix E
Measuring Typical Stuck-on Resistance for
L=W
Here is an example Eldo file that measures the source-drain resistance of stuck-on n-channel
and p-channel MOS transistors:
* Circuit to measure resistances of stuck-on transistors having L/W=1
* Use the measured resistances as values for stuck_on_defect_resistance_LW
* replace with your process file

.INCLUDE AMI.process_nom
* replace '3' by your VDD voltage

.PARAM vdd=3
* replace 'CMOSN' and ‘CMOSP’ by your transistor models

* replace 1000n with your typical analog transistor minimum length
M1 vn vdd 0 0 CMOSN 1000n 1000n
M2 vp 0 vdd vdd CMOSP 1000n 1000n
* force gate and drain-source voltages

VDD vdd 0 (vdd)
VN vn 0 (vdd/2)
VP vdd vp (vdd/2)
* measures transistor's resistance (drain-source voltage divided by

* current)
.EXTRACT DC label=R_stuckon_nmos -v(VN)/i(VN)
.EXTRACT DC label=R_stuckon_pmos -v(VP)/i(VP)
.DC
* optional lines to minimize output listing

.NOTRC
.NOTRCMOD
.OPTION NOJWDB NOMOD NOOP PRINT_DC=0 PRINT_OPTION=0 PRINT_ACCT=0
MSGNODE=1
.END
Measuring Typical Stuck-on Resistance for L=W
Appendix F
Defining Custom Analog Defect Models
You can create a user-defined analog defect model (UDADM) for defects in individual circuit
elements, and user-defined analog fault model (UDAFM) for faults in whole subcircuits—
create_defects_to_simulate uses these when it creates
<CUT>.CELLS_DEFECTIVE_NETLISTS. In these files, you must also include a calculation
for RL.
The create_defect_model and create_fault_model commands can generate hundreds of custom
models based on a few templates that you create, which can be based on automatically
generated ones.
The RL calculation that you provide is used by the command create_defect_sites_list. You may
create a UDADM for preLRL, preHRL, and/or postRL of capacitors, resistors, inductors, and
diodes. For transistors, you may create a UDADM only for preLRL and/or preHRL. If you
define how RL is calculated, you must include a defect model or fault model too. Tessent
DefectSim uses your RL calculation when it creates <CUT>.potential_defect_list.
As described later in this Appendix, you may create any number of defect models per schematic
circuit element type (R,C,L,M,Q,D), and any number per layout parasitic circuit element type
(R,C,L,D). Similarly, you may also create any number of user-defined primitive subcircuit fault
models per schematic subcircuit, and any number per layout subcircuit.
Define defect models in a file whose suffix is .defectsim_defect_models, and put this name in
the custom_defect_models line of your <CUT>.defectsim file. Defects can be defined for
resistors, capacitors, inductors, diodes, MOS transistors, and bipolar transistors, and the model
or netlist that you provide will replace the line containing that circuit element.
For example, if transistor gate leakage is a special concern, you could define a defect model that
has gate-to-source or gate-to-drain leakage instead of a simple stuck-on or stuck-off defect. You
could also make the RL value have a non-linear dependence on the transistor’s area, for
example, decreasing the defect likelihood for transistors that are both wide and long.
Define fault models in a file whose suffix is .defectsim_defective_subcircuits, and put this name
as the second term in the primitive_subcircuits line in your <CUT>.defectsim file. The first
term must be the name of a file that lists the names of primitive subcircuits. Fault models are
entire defective subcircuits that will replace the defect-free subcircuit if that subcircuit is
randomly selected for simulation. Faulty subcircuits can be used for primitive subcircuits in
your PDK, so that you do not need a local copy of the subcircuit, and you can inject a defect into
only the primary circuit element of the primitive subcircuit. Faulty subcircuits can also be used
for more complex functions in which a fault is a change in behavior caused by no specific
defect; for example, an op-amp with insufficient open-loop gain.
The syntax for <CUT>.defectsim_defect_models and <CUT>.defectsim_defective_subcircuits

is shown below.
• A user-defined defect model or primitive subcircuit fault model must begin with a line in
the following format:
<component name , defect_model type>
where name is a circuit element type (R,C,L,M,Q,D) or a subckt name, and type is pre or
pos followed by any letters or digits. The prefix indicates whether the model should be
used for pre-layout (schematic) or post-layout (layout-extracted) subcircuit netlists.
Tessent DefectSim will append RL to the type if it does not already end in RL. Only
preLRL, preHRL, and postRL have default defect models.
• A user-defined defect model or primitive subcircuit fault model must have at least one
line in SPICE or Spectre syntax (which may be a comment) and must end with a line in
the following format:
<endcomponent name>
• Any line beginning with * will be written to the SPICE/Spectre model as a comment
line, and may contain Tcl expressions that will be interpreted. Problematic expressions
can be more easily diagnosed by putting each $variable in a comment line to see its
interpreted value in <CELLS>.CELLS_DEFECTIVE_NETLISTS.
• Any line beginning with # will be entirely ignored by Tessent DefectSim. These lines
may be used for comments that you don't want written into the defect model.
• To avoid unexpected results, expressions should use the following syntax (note space
after expr): [expr {put expression here}]
For the RL calculation text, the above syntax must not be used since only expressions
are allowed.
• An expression may call procedures defined in a custom_models_procedures file. You
can pass values to a proc using Tcl syntax: [procname value1 value2 …]. All variables
that may be used within a model or $RL calculation, such as $r_design and $value, may
also be used in a proc, but each must be preceded by ‘$::’ instead of only ‘$’. This may
be done in a UDADM, UDAFM, or a template (that is used by many UDAFMs).
The following example template calls the res_val and res_RL procedures from an
external file specified by custom_models_procedures:
<component MOS, defect_model pre_my_mos_model>
$subckt_header
$subckt_body
R_defect0 $node1 $node2 [res_val 1.33]
$subckt_footer
$RL = [res_RL]
<endcomponent MOS>
Below is the contents of the file indicated by custom_models_procedures:

proc res_val {procm} {
set val [expr {$procm * ($::value + \
$::short_defect_resistance)/2.0} * $::instance(area)]
return $val
}
proc res_RL {} {
set val {$::value * 5.0}
return $val
}
• The variables that you may use are the following (must be lower case and refer to nodes,
model, etc. of the circuit element instance or to the sub-instance listed for a primitive
subcircuit):
For all: $node1 $node2 $model $original_line $m (or $multiplier) $all_parameters,
and all .defectsim file parameter names listed in Step 1 - Create .defectsim Control File,
preceded by $
Also for R, resistor, C, capacitor, L, inductor, D, diode: $value
Also for R, resistor: $length $width $layer
Also for M, transistor: $node3 $node4 $length $width $all_other_parameters
(excludes $length and $width)
Also for Q, bipolar transistor: $node3 $node4
• You may use almost any Tcl expression. The arithmetic operators are: + - / * Exponent
is indicated using: **
Rules for multi-line Tcl expressions in UDAFM:
o The entire 'if' condition must be on the same line, with 3 braces: if { expression } {
o The line that contains 'else' must contain only: } else {
o The entire 'elseif' condition must be on the same line, with 4 braces:
} elseif { expression } {
o If multiple lines are to be output, use a single puts "one or more lines of text"
o Must end with a line containing only ] or }]
o The line starting with $RL must contain the entire 'if' condition.
Example:
r_df1_ $node1 $node1 \
[ if {$value < 100} {
puts "[expr 10*$value] * from if"
another line and expression"
} elseif {condition} {
puts ...
} else {
puts "[expr $value] * from else"
alternative line"
}]
$RL = [if {$value < 9750} {
puts "$rl_resistance_l* 18
+ 1 + ($value/$rl_resistance_l) "
} else {
puts "$rl_resistance_l* 22"
}]
• You should insert a line containing:

$defect_description = plain_text_without_quotes
and the text will be used in the defect coverage summary file.
• You should insert a line containing:
$defect_type = [open] | [short] | [variation] | [other]
to control how activity is measured for a UDAFM and how the defect is reported when
<CUT>.defectsim contains
report_coverage_per_defect_type on
• You may insert lines containing:

$stress_nodes = n1 [n2]
$stress_statistic = average | maximum | rms | exponential
$stress_exponent = value (typically 100, default is 0)
$stress_scale_factor = value (default is 1, typical for TBBD is
1e11)
where n1 and n2 are nodes (which may be ports) in the subcircuit. If one node is listed,
current into it is monitored; for a defective subcircuit model, the node must be a port of
the subcircuit, $port_1, for example (note that if the node/port is connected to VDD,
then IDD might be reported). If two nodes are listed, voltage across them is monitored.
The RMS value or the absolute value of the average or maximum voltage (or current),
multiplied by $stress_scale_factor, will be compared to V_stress (or I_stress). For
exponential, V_stress is compared to $stress_scale_factor × $sampling_activity_interval
× [sum of all exp(-1 × $stress_exponent / voltage)]. This is based on the basic equation
for time-dependent dielectric bias (TDDB). $stress_scale_factor should be set to 1/t0,
where t0=1e-11 s, the time intercept of a ln(tBD) plot, and $stress_exponent should be set
to GXox volts (must be >0), to give a time to breakdown (tBD) of 1 second. Any of the
values may be expressions. Temperature can be included in an expression by using

$defectsim_temp (it will have same value as Eldo's temper).
• For functional safety applications, where RL values must be based on activity in the
circuit, for any defect models of transistors you may insert a line containing:
$activity_rl_measurements = par1 par2 ..., where par1, par2 are each one of vgs, vgd,
vgb, vds, vdb, vsb, id, is, ib for MOS transistors, and vce, vcb, vbe, vcs, ves, vbs, ic, ib,
ie for bipolar transistors. To avoid creating an activity_results file that is very large, just
list the voltages and currents needed by your $RL_activity expression in the model.
• For functional safety applications, where RL values must be based on activity in the
circuit, you may insert immediately after the expression for $RL, an expression for
$RL_activity that can use any or all of the following variables:
o $v_measured, $i_measured = 0 or 1; 1 if voltage or current was successfully
measured
o $active, $stressed = 0 or 1; 1 if reported as active or stressed in CUT.good_circuit
o $RL_base = $RL
o $stress_value as calculated from $stress_scale_factor, $stress_exponential,
$stress_statistic
o $i_active, $v_active, $iac_active, $vac_active, $v_stress,
o $i_stress = value in <CUT>.defectsim
o $activity(par_suffix), where par is one of
• i, v for 2-terminal elements
• vgs, vgd, vgb, vds, vdb, vsb, id, is, ib for MOS transistors
• vce, vcb, vbe, vcs, ves, vbs, ic, ib, ie for bipolar transistors
• and suffix is one of max, delta, avg, rms (max=maximum; delta=maximum
delta; avg=average; rms=root mean square)
• $value, $length, $width, $m, $multiplier, $rl_model, $instance(par)
Examples
$RL_activity = $RL_base * $activity(vds_rms) * $activity(id_rms)
$RL_activity = $activity(v_rms)**2 / $value
To limit the number of voltages captured for transistors, par must be declared in a
line within the defective subcircuit body as, for example: $activity_rl_measurements
= vgd vsb idIf par_suffix was not measured, $activity(par_suffix) =
“UNMEASURED”.
• You may use a parameter of any sub-instance in the original subcircuit by using the
syntax: <instance>(<parameter>). For example, Rdefect n1 n2 $R23(value) M_defect
n1 n5 n6 n7 $M1(model) $M1(length) $M1(width).
The values most be one of those normally listed in <CUT>.potential_defect_list. If the
netlist is case-insensitive, the sub-instance must be upper-case; otherwise it must match
case of original netlist.
• $original_line recreates in a UDADM the line from the .sub or .scs file using the
parameters above; if there were more parameters, they are omitted (e.g., MOS
transistors do not include areas of source and drain; R, C, and L have constant values).
• For any variables that are arrays, except RL_model, you must use a lindex expression,
e.g.,
[expr {5 * [lindex $stuck_on_defect_resistance_lw 1]}]
• For RL_model, use e.g.,

[expr {5 * $rl_model_table(nmos1)}]
• There are no special line continuation characters; + appears in resulting text.

• All lines, even those preceded by a comment character, are used when creating
defectsim_outdir/<CUT>.CELLS_DEFECTIVE_NETLISTS
• Subcircuits must begin with a .subckt line and end with a .ends line, in Spice or Spectre
syntax as appropriate, followed by a $RL line.
• A subckt must not be named R, C, L, D, M, or Q.
• The .subckt line must contain the same name as the immediately preceding <component
line, and the line must not start with spaces or be preceded with a comment or blank line.
• $node1, $node2 etc. within a custom defective subcircuit refers to the nodes of the sub-
instance (not the subcircuit).
• $port_1, $port_2, etc. within a custom defective primitive subcircuit can be used to
refer to its port nodes.
• $instance(parameter) within a custom defective primitive subcircuit will have a value
specific to one instance, $toplevel(parameter) will have a value defined at the top-level
of your design for all instances, and $::env(parameter) will have a value that was
defined as an environmental variable at the system level.
• Any lines before a <component line, or after an <endcomponent line are ignored
(unless they start with $RL)—they will be treated as comments.
• Any line beginning with # will not be interpreted as Tcl. If it follows the .ends line but
precedes the <endcomponent line, then it will be treated as a comment.
• You may use conditional statements, like:

[if {condition1} {action if true} else {action if false}]
[if {condition1} {action if true} elseif {condition2} {action if 1
false and 2 true} else {action if both false}]
You can conditionally insert text or whole lines using {set abc {any text string}} as the
action. Note the text string within { } - it must not contain variables; if you want to use
variables in it, use quotes instead of braces. Also note that an expression must be written
on a single line.
• [ ] is always interpreted as enclosing a Tcl expression. If you don't want them
interpreted this way, insert \ before each bracket. Any line that begins with [ is treated as
an expression.
• ${SpiceSpectreFormat(R)} may be used in UDADM to make a resistor, capacitor, or
inductor syntax independent; eg. R_defect $node1 $node2
${SpiceSpectreFormat(R)}$value might produce within a SPICE file or Spectre
subcircuit, respectively:
R_defect vdd n45 500
R_defect vdd n45 resistor r=500
For the list of primitive circuits, there may be 2 to 5 terms per line. If no activity is to be
measured, indicate no_activity_measurement instead of ports. The two port numbers listed for
each subcircuit are the nodes through or across which activity will be monitored by Tessent
DefectSim to decide whether the subcircuit is active—they should be the two terminals of the
primary resistance, capacitance, inductance, diode, MOS transistor (its drain and source), or
bipolar transistor (its base and emitter). You do not need to list the ports if the listed
sub_instance type and port numbers are the same as the overall schematic element, i.e., ports 1
and 2 for R, C, L, and diode, or ports 1 and 3 for MOST, or ports 2 and 3 for BJT. The sub-
instance may be a circuit element (e.g., M1) in the listed primitive subcircuit, or a circuit
element within a sub-subcircuit (e.g., X5.M1) of the listed primitive subcircuit. The ports are
needed only if they are not the usual port positions for the sub-instance circuit element type. The
syntax of each line is:
<subckt_name> <your_label> <sub_instance> <$port_n> <$port_m>
Example contents of a file containing a list of primitive subcircuits:
AB resistor R1
CD capacitor C2 $port_2 $port_3
EF mos M3
GH module Q4 no_activity_measurement
JK my_mos - $port_1 $port_2
LM transistor XM.M1
nmos1 defectsim_ieee2427hard_m M1
diode5 defectsim_ieee2427hard_d D1
resist1 defectsim_ieee2427hard_r R0
* this is a comment
The sub-instance is optional but recommended because it enables DefectSim to list the primitive
subcircuit in the appropriate category of defects in .potential_defect_list. The sub-instance must
be a circuit element, not a subcircuit. If there is no primary sub-instance, then you may use '-' as
a placeholder. Any line beginning with '*' is ignored.
Example contents of name.defectsim_defective_subcircuits:
<component subckt_name , defect_model preHRL>

.subckt subckt_name n1 n2 n3 a=2 b=3
R1 n1 n2 [expr {$value * 5}] * note that variables are lower case
.PARAM def = $::env(abc)
.ends
$RL = equation uses DefectSim lower-case variables and $value, etc. of
sub-instance
<endcomponent subckt_name>
If the defect is randomly selected by create_defects_to_simulate, then the above defective

subcircuit netlist placed in <CUT>.CELLS_DEFECTIVE_NETLIST would appear as:
.subckt subckt_name_DEFECTSIM_D3 n1 n2 n3 a=2 b=3

R1 n1 n2 50 * note that variables are lower case
C1 n1 n2 [$instance(mycap) * $toplevel(allcaps) * $value]
.PARAM def = value_defined_by_environment_variable_abc
.ends
The example file listing below is similar to the default values for all elements. The actual
default models are more complicated since there are multiple default models for some circuit
elements and the choice of model depends on the value of some parameter (e.g., preLRL for a
resistor is inversely proportional to unit_RL_R_design only if unit_RL_R_design>0, otherwise
RL=RL_resistance_L; but if the resistor is in parallel with another, then RL=0).
Example contents of name.defectsim_defect_models:
<component R , defect_model preLRL>

# the resistor will be replaced by next 2 lines
* simplified default equivalent
R_DEFECTSIM $node1 $node2 [expr {(1-$r_defect_l/100.0) * $value}]
# Relative Likelihood calculation
$RL = $rl_resistance_l * $value / $unit_rl_r_design
<endcomponent R>
<component R , defect_model preHRL>

# the resistor will be replaced by next line
# note that 100.0 is used instead of 100 because a non-integer result is required
R_DEFECTSIM $node1 $node2 [expr {(1+$r_defect_h/100.0) * $value}]
$RL = $rl_resistance_h * $value / $unit_rl_r_design
<endcomponent R>
<component R , defect_model postRL>

# the resistor will be replaced by next 4 lines
R_DEFECTSIM $node1 $node2 [expr {$open_defect_resistance / $open_defect_r_ratio}]
R_DEFECTSIM0 $node1 DEFECTSIMV $open_defect_resistance
R_DEFECTSIM1 $node2 DEFECTSIMV $open_defect_resistance
V_DEFECTSIM DEFECTSIMV 0 [randomly_select $float_high_voltage $float_low_voltage]
$RL = $value / $unit_rl_r_parasitic
<endcomponent R>
<component C , defect_model postRL>

# the capacitor will be replaced by this line
R_DEFECTSIM $node1 $node2 $short_defect_resistance
$RL = $value / $unit_rl_c_parasitic
<endcomponent C>
<component D , defect_model preLRL>

# the diode will be replaced by this line
R_DEFECTSIM $node1 $node2 $open_defect_resistance
$RL = $rl_diode_open
<endcomponent D>
<component D , defect_model preHRL>

# the diode will be replaced by this line
R_DEFECTSIM $node1 $node2 $short_defect_resistance
$RL = $rl_diode_short * $rl_model_table(mydiode)
<endcomponent D>
<component M , defect_model preLRL>

# the transistor will be simply deleted because there is no component replacement
$RL = $rl_transistor_stuck_off
<endcomponent M>
<component M , defect_model preHRL>

# the transistor will be replaced by next 2 lines
R_DEFECTSIM $node1 $node3

+ [expr {$length/$width * [lindex $stuck_on_defect_resistance_lw 1]}]
<endcomponent M>
Other example models that are noteworthy

# provide original line for comparison
* $original_line
M_DEFECT $node1 $node2 $node3 $node4 faulty$model $length $width
* This calls eg. faulty NMOS instead of NMOS model, with varied W, L, Vt, ...
* so that a defective transistor has e.g., 1.2*Vt and 1.5*W, or 0.8*Vt and 1.5*L
* Any test that detects variations will detect stuck-on/off and less drastic defects.
<endcomponent M>

# provide original line for comparison
* $original_line
* This is like a transistor with an open gate, making it barely on, almost stuck-off
R_DEFECT $node1 $node3 5e7
<endcomponent M>
<component R , defect_model preHRL>

# the resistor will be replaced by next line
* This uses an embedded ‘if’ to set defective resistance to one of only two values.
* Placeholder parameter ‘abc’ is used to insert the result of the multiplication.
R_DEFECT $node1 $node2 [if {$value > 1e4} {set abc 10*$value} else {set abc 2*$value}]
$RL= $rl_resistance_h
<endcomponent M>
<component M , defect_model preBRL>

# Original line will be provided for the model and Rdg_defectsim resistor will be inserted to
make drain-gate short
$original_line
* drain-gate short
Rdg_defectsim $node1 $node2 200
$RL=$rl_transistor_b
<endcomponent M>
<component M , defect_model preCRL>

$original_line
* gate-source short
Rgs_defectsim $node2 $node3 200
$RL=$rl_transistor_c * $rl_transistor_b * $length * $width
<endcomponent M>
These examples show how the defect model can depend on which nodes of a transistor are tied
to a single node.
<component NMOS5 , defect_model preHRL>

.subckt NMOS5 B D G S
* nodes connected to M1: D=$node1 G=$node2 S=$node3 B=$node4
[if {$node1==$node3} {set abc {R_defect D G 100}} else {set abc {R_defect D S 100}}]
.ends
$RL = [if {($node1==$node2) && ($node2==$node3)} {set abc 0}} else {set abc
$rl_transistor_stuck_on}]
<endcomponent NMOS5>
In this example, $port_1 could be used, instead of $node1, to refer to the port nodes of the
subcircuit.
<component NMOS5 , defect_model preLRL>

.subckt NMOS5 B D G S
* nodes connected to M1: D=$node1 G=$node2 S=$node3 B=$node4
[if {$node1==$node3} {set abc {* open capacitor}} else {set abc {* open transistor}}]
.ends
$RL = [if {($node1==$node2) && ($node2==$node3)} {set abc 0} else {set abc
$rl_transistor_stuck_off}]
<endcomponent NMOS5>
Appendix G
How Tessent DefectSim Measures Activity
Coverage
When simulate_defect_free is run, Tessent DefectSim automatically measures the activity at

each potential defect site that was selected by create_defects_to_simulate.
This does not increase the simulation time (therefore, you could temporarily set higher
target_number_defects_to_simulate) and is run by default (to disable this, set
report_controllability_in_summary off in CUT.defectsim). This is similar to toggle coverage in
purely digital circuits, and is a measure of the controllability of defect sites, and an estimate of
the maximum defect coverage that the stimulus could be achieved if you had perfect
observability for all defect sites—it is independent of what is actually observed (measured or
digitally sampled). If activity coverage is too low, you should improve the stimulus before
proceeding to run simulate_defects.
Table G-1. Tessent DefectSim Activity Coverage
Circuit Element Type Potential Defect Type Electrical Property Monitored
Design-intent resistor Variation (preLRL, preHRL) Voltage across the resistor
Parasitic resistor Open (postRL) Current into node1 of the resistor
&& dv/dt at node1 of the resistor
Design-intent capacitor Variation (preLRL, preHRL) Current into node1 of the capacitor
Parasitic capacitor Short (postRL) Voltage across the capacitor
Design-intent inductor Variation (preLRL, preHRL) Voltage across the inductor
Parasitic inductor Open (postRL) Current into node1 of the inductor
Diode Variation in knee voltage Current into node1 of the diode
Diode Open (preLRL) Current into node1 of the diode
Diode Short (preHRL) Voltage across the diode
MOS transistor Variation in threshold or gain Current into drain of the transistor
MOS transistor Stuck off (preLRL) Current into drain of the transistor
MOS transistor Stuck on (preHRL) dv/dt across source and drain
Bipolar transistor Variation in threshold or gain Current through the emitter
Bipolar transistor Open in base (preLRL) Current through the emitter
Bipolar transistor Open in emitter (preHRL) Current through the emitter
How Tessent DefectSim Measures Activity Coverage
Explanations and Assumptions
Voltage and current are sampled at sampling_start_time + sampling_activity_delay + N ×

sampling_interval.
Voltage and current steps are differences between consecutive samples.
Voltage - if absolute value of voltage exceeds V_active at any sampling instant, defect site is
ACTIVE
Current - if absolute value of current exceeds I_active at any sampling instant, defect site is
ACTIVE
dv/dt - if absolute value of voltage step exceeds Vac_active at any sampling instant, defect site
is ACTIVE
di/dt - if absolute value of current step exceeds Iac_active at any sampling instant, defect site is
ACTIVE
Activity Coverage is the likelihood-weighted percentage of sites that are ACTIVE.
Explanations and Assumptions

The following are assumptions regarding the activity coverage.
• If voltage across an element is too small, then a variation or short will not be detected
(but an open might be detected), for example a 0.1 ohm resistor.
• If current through an element is too small, then a variation or open will not be detected
(but a short might be detected), for example capacitor across VDD/VSS.
• If current through drain or emitter is too small, then a variation, stuck-off, or open
emitter will not be detected (but stuck-on or open base might be detected), for example
in non-switching logic gate.
• If current change through drain or emitter is too small, then a stuck-on or open base will
not be detected (but stuck-off or open emitter might be detected), for example transistor
in bias chain.
• For a resistor in series with an MOST gate, current and voltage will be approx. zero,
therefore we must monitor changes in voltage of one of its nodes to detect activity.
• Highest frequency of interest is assumed to be 1/ (2 × sampling_interval), even if no
digital outputs.
Appendix H
Working with DefectSim Results
This Appendix describes tasks that are normally performed by a Mixed-Signal Design-For-Test
(DFT) Engineer - someone who understands analog/mixed-signal (A/MS) circuit block design
and SPICE-level simulation, datasheets (customer expectations), and production testing vs.
simulation testbenches. Many companies have multiple DFT engineers for digital circuitry, but
very few have DFT engineers for analog circuitry, mostly because there are very few, if any,
systematic methods and tools for analog DFT.
Industrial digital fault simulators were available in the 1980s and led to the development of
systematic DFT methods such as scan and memory BIST, and eventually automated test pattern
generation (ATPG) software that inherently includes digital fault simulation for scan-testable
circuitry. But for A/MS circuits, there were no comparable tools until the introduction of
Tessent DefectSim in 2012.
With that history in mind, the IEEE P1687.2 Analog Test Access Working Group is developing
a systematic way to implement analog DFT consistent with what companies already do in an ad
hoc fashion, and developing a way to describe analog tests generically. This should lead to the
development of A/MS DFT tools, equivalent to those available for digital circuitry. Until then,
the tasks of these future tools must be implemented manually. This document concisely
describes those tasks for a block circuit-under-test (CUT) within an IC.
Developing Realistic Models of Defects and Faults You Want to Detect . . . . . . . . . . . . 175
Developing Circuit Block Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Diagnosing Inactive Defect Sites. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Diagnosing Undetected Defects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Reducing Test Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Developing Realistic Models of Defects and

Faults You Want to Detect
Tessent DefectSim inserts default defect models.
These models are shown in “Default Injected Defects” on page 18. The default models are
suitable for initial defect simulations of any circuit where design-intent circuit elements are not
subcircuits, thus every resistor, capacitor, and so on, in the flat netlist is a design-intent separate
resistor, capacitor, and so on. In many cases, design-intent circuit elements are actually
subcircuits in a PDK library. A schematic resistor's subcircuit might contain multiple resistors
in series with distributed capacitances to substrate— if 50% variations are injected in any one of
the multiple resistors, they probably won't be distinguishable from normal process variations
Developing Realistic Models of Defects and Faults You Want to Detect
and thus cause lower activity coverage and lower defect coverage than in silicon; their
capacitances to substrate do not present a reasonably likely opportunity for a short circuit to
substrate.
As described in “Defining Custom Analog Defect Models” on page 161 of this manual, a user-
defined analog defect model (UDADM) is a model you create for a single circuit element that is
not a subcircuit, and a user-defined analog fault model (UDAFM) is a model you create for a
whole subcircuit, which might be a PDK circuit element, or a function such as a comparator.
For PDK subcircuits, you should create custom fault models so that each subcircuit is treated as
a single circuit element. You should declare two ports for each such subcircuit so that activity in
it can be measured when assessing activity coverage.
You can make a UDADM/UDAFM conditional on its connections to ensure the defect/fault is
potentially detectable. For example, for an MOS transistor, if its gate and drain are tied to a
single node, then no short should be injected across the gate and drain; if its source and drain are
tied to a single node (but not to the gate), a model for a MOScap defect should be invoked. If all
ports of any PDK subcircuit are tied to the same node, then the circuit element is not being
used—you can prevent defects being simulated in it by setting its relative likelihood (RL) of a
defect to zero.
You should use the three commands described in Step 3 to automatically create IEEE2427hard
UDADMs and UDAFMs. The following details are about customizing them further, if you wish
to do so. RL for a circuit element should be proportional to its “critical area” (CA)—the area
that is susceptible to the defect size that is most likely in a fabrication process, generally
between 1X and 2X the fab node dimension (for example, 130~260 nm for a 130 nm process).
• The CA for MOS transistors might be simply proportional to their gate length times
width, up to some maximum value. To code this, choose a “reference area”, such as 0.1
µm2 (1e-13) and a maximum RL, such as 100. If different transistor models have
different critical areas for the same width and length, you can make change RL for each
model. Code it in CUT.defectsim as the following:
unit_RL_M_design_LW 1e-13
RL_transistor_A 100
RL_model nmos1 1 hvpmos 2.3
o In the UDADM or UDAFM for defect type 'preARL', use code such as:
$RL = [$length * $width * $rl_model / $unit_rl_m_design_lw]
o Tessent DefectSim will automatically include the relevant model multiplier.

o For UDADM, $length and $width are obtained from the instance.
o For UDAFM, $length and $width are obtained from the primary instance that you
designate in the list of primitive_subcircuits in CUT.defectsim.
o Note that $parameters must be lower case.
Developing Circuit Block Tests
• The CA for resistors can be simply proportional to their resistance, if resistors are
designed with a constant width and modeled with the same mask-level specific model,
e.g. poly2res. To code this, find the resistance of a resistor that is your constant width
and whose length is long enough that its width × length = reference area (e.g. 1e-13). If
this resistance is, for instance, 5 k for poly2res and 30 k for nwell (i.e. 6X higher), then
code in CUT.defectsim as:
unit_RL_R_design 5k
RL_model poly2res 1 nwell 6
o In the UDADM or UDAFM, use code such as:

$RL = [$value * $rl_model / $unit_rl_r_design]
• The CA for capacitors can be simply proportional to their capacitance (this is the
Tessent DefectSim default for all parasitic capacitances), but may differ depending on
whether capacitors are implemented in double poly, between metal layers, or within a
single metal layer (inter-digitated). Code this similarly to the way that is described for
resistors.
• The CA for bipolar transistors can be simply proportional to their area. Since area is not
included in some BJT models, sometimes an area parameter is defined for a custom
model, such as “si_area”. In CUT.defectsim, set the RL relative to the MOS reference
area, such as:
RL_bipolar_A 2.5
o In the UDADM or UDAFM, use code such as:

$RL = [$instance(si_area) * $rl_bipolar_a / $unit_rl_m_design_lw]
Creating user-defined models is a task that only needs to be done once per process technology
or once per PDK, and then the models can be used for any number of IC designs. You can
probably use the models for multiple technologies with only minor changes, such as the names
of the subcircuits or names of the ports. Consult “Defining Custom Analog Defect Models” on
page 161 for more details and examples. You can obtain simulatable examples by entering the
command:
defectsim EXAMPLE_OA create_example

For digital scan tests, ATPG tools deliver patterns that only work for a designated scan path in
one block of circuitry within an IC. The pattern comprises only 1s and 0s, and it is delivered at a
constant clock rate across a timing-insensitive ATE/IC interface. Presently, there is no ATPG
for testing non-scan logic, or A/MS circuits (or multiple scan blocks simultaneously).
One intent of the P1687.2 Analog Test Access Working Group is to extend IEEE 1687 (IJTAG)
to describing A/MS tests, so that eventually a generic A/MS test can be automatically translated
into a simulation testbench and also into an ATE test pattern, ensuring they that they are
equivalent. P1687.2 exploits analog test bus access for purely analog signals (block-level, for a
few blocks, or whole chip), and serial access to DAC inputs and ADC outputs for digitized
analog signals—tests via these paths can be more easily modified to apply at the top level
without needing to re-simulate at the top level. This means the tests could be simulated for a
circuit block, and when the block is later embedded within an IC, the patterns would be
automatically modified to run at the chip-level, as is already possible for digital patterns
developed in 1687-compatible format for testing digital blocks. Multiple EDA vendors provide
1687-based tools for digital design and test, but Mentor Graphics, a Siemens Business, provides
the most.
Until P1687.2-based automation is developed, you must manually generate testbenches and
equivalent ATE tests, and you should do this at the block-level, in a way that can be migrated to
the chip level.
Here is some guidance for creating A/MS testbenches to be run in Tessent DefectSim.
1. A/MS tests applied in DefectSim simulations should be equivalent to production ATE

tests that are planned or in use - they need not be exactly the same.
a. It is usually not practical to make simulation testbenches the same as ATE tests
because:
i. ATE/IC interfaces are not timing-insensitive.
ii. Test access is not systematic (no standards).
iii. Test stimulus/response description is not systematic (no standards).
iv. Tests include 1s and 0s, unique timing for every edge, analog waveforms, and
multiple stimulus/response domains (time, voltage, current, frequency,
temperature, …).
b. The path between IC pins and the circuit-under-test (CUT) can affect the stimulus
and response because:
i. Analog waveform bandwidth is affected by path characteristics.
ii. Digital stimulus and response are conveyed through surrounding blocks.
iii. The capacitance of the interface board and ATE channels greatly changes
signals.
c. Real ICs have noise, but simulations don't; therefore:
i. High precision measurements might require averaging of 4~32 samples in time.
ii. Simulation is noise free, so simulation time can be reduced by 4~32X compared
to ATE test.
2. Methods for applying ATE-equivalent tests in simulation to a block CUT:

a. When the surrounding blocks only convey signals to the CUT, or from the CUT,
then in digital simulation, you can apply ATE stimulus to the surrounding blocks
and capture the digital patterns in VCD (vector change dump) format that will be
applied to the CUT, and separately capture the patterns in VCD format that should
be output by the CUT. Then in the Tessent DefectSim testbench, use .TVINCLUDE
to apply the VCD pattern and/or to compare the CUT output to it. (See Eldo
Reference Manual regarding .TVINCLUDE. Also see “user_defined_good_vector”
on page 58.)
b. When the surrounding digital blocks drive analog inputs based on previous analog
outputs, then you should include the digital blocks in your Tessent DefectSim
simulation. If they are relatively small blocks (<10k logic gates), then they could be
simulated at the transistor level, but otherwise their Verilog RTL should be used, and
Questa ADMS instead of just Eldo. If most of the logic circuitry is tested by scan,
then Tessent DefectSim need not inject defects into these blocks. If it is not tested by
scan, you may provide for each logic gate a Verilog model and a subcircuit netlist—
Tessent DefectSim will use the latter only when a defect is injected in that logic gate.
c. Testing IDDQ can be useful for detecting stuck-on transistors in CMOS logic that
are difficult to detect digitally (an inverter with a stuck-on PMOS will still invert).
To do this test within an IC, other blocks must be disabled so they draw insignificant
current compared to the CUT. The IC should be designed with IDDQ testing-per-
block in mind, but if it is not, then do not simulate an IDDQ test (unless you just
want to see what the additional coverage would be).
d. If digital outputs of a CUT can be accessed only via a serial shift register, then the
simulation testbench for the CUT could monitor the digital outputs directly, but you
should use corresponding coarse timing resolution (one capture per 20 µs, for
instance). In CUT.defectsim, set sampling_interval to the coarse timing interval.
e. If analog outputs of a CUT can be accessed via an analog test bus, or inferred by the
voltage at an IC pin, then in the testbench it is sufficient to include measurements of
those CUT outputs in the list of test_parameters in CUT.defectsim.
f. If an analog output will be sampled many times in the ATE test to improve
measurement precision, it could be sampled just once in the (noise-free) simulation
testbench, and then the number of times it is sampled by ATE can be adjusted later
to achieve the required repeatability.
g. Jitter for a PLL or SerDes is typically measured across thousands of clock or data
edges. In a simulation testbench, you can simulate jitter measurement in as few as a
fifty edges, since there is no noise and the jitter will be dominated by non-random
phenomena. Deterministic jitter should be maximized by using a worst-case bit
sequence, or an alternative measurement method (that exploits access to internal
signals). For example, maximum inter-symbol interference (ISI) can be deduced by
Diagnosing Inactive Defect Sites
measuring a single phase delay difference between a maximum transition density

(1010) pattern and a minimum transition density pattern (0000100001).
3. DFT methods that facilitate applying ATE-equivalent tests to a block CUT during
simulation:
a. If analog outputs of a CUT cannot be accessed directly, and defect coverage without
accessing them is inadequate, then an analog test bus should be added to the IC
design.
b. Only the CUT's digital outputs that you can monitor from off-chip should be listed
as digital_output_signals in CUT.defectsim. If defect coverage without accessing
remaining CUT digital outputs is inadequate, then serial scan access to those signals
should be added to the IC design (preferably in a way that is compatible with 1687).
c. An on-chip DAC could be used to deliver analog signals via a local analog test bus,
and the input to the DAC shifted in serially. In this case, the simulation testbench can
apply the analog signal values directly, without including the analog test bus or
DAC.
d. An on-chip ADC could be used to monitor analog signals via a local analog test bus,
and the output of the ADC shifted out serially. In this case, the simulation testbench
can test the analog signals directly, without including the analog test bus or ADC
(but including equivalent loading).
e. Some companies develop proprietary data busses that allow them to systematically
convey patterns to/from any block within the IC, and develop custom software to
convert simulation testbench patterns into ATE patterns on these busses. This allows
them to ensure the simulation testbench is translated reliably to an ATE pattern.

This section covers how you go about diagnosing inactive defect sites.
The Tessent DefectSim command simulate_defect_free simulates your testbench after a
relatively small number (25~250) of potential defect sites has been randomly selected from a
large number (1k~1M) of potential defect sites. An outcome of the simulation is a
“good_vector”, which includes all digital_output_signals captured as 0/1 at the
sampling_interval, and an indication for every one of the randomly selected potential defect
sites as to whether it is active enough to detect the defect that will be injected there when
simulate_defects is run. This information is stored in CUT.good_results along with the
likelihood-weighted activity coverage, which you can consider as the maximum defect
coverage that simulate_defects is likely to achieve for this testbench.
The sampling_start_time and sampling_interval are used to capture digital_output_signals

values, but also to sample voltages and currents at the potential defects. Therefore, you should
provide values for these CUT.defectsim settings even if the CUT does not have digital outputs.
If the CUT has a clock, you should set sampling_interval to be equal to, or an integer multiple
of, the clock period - note that it is not practical to sample more than a thousand times in a single
testbench (because the results in the output summary file will be very difficult to read).
Start_sampling_time may be greater than the default zero if you want to avoid capturing output
values during initial transients, and to ensure each of the digital_signal_outputs is captured only
after they have settled from being updated by the previous clock edge (i.e., just before the next
active clock edge).
If you have multiple directories of subcircuits, one containing schematic subcircuits and another
containing macromodel versions of some of those subcircuit or layout-extracted versions, then
you must run simulate_defect_free twice, first without any options, and then with the
-view_lowest option. Activity for some defect sites can only be measured during the second run.
The Tessent DefectSim tool's measurement of activity coverage is a unique metric for analog
circuits, analogous to toggle coverage in digital circuits, but since it is analog, it is not as
definitive. A defect site might be relatively inactive, but due to high gain in the path to an
output, a defect at the site would still be detected. The type of activity measured by DefectSim
depends on the circuit element type (resistor, transistor, …), and on the type of defect that will
be injected at that site (short, open, variation, …), as described in “How Tessent DefectSim
Measures Activity Coverage” on page 173. Activity can be measured for custom fault models,
but you need to list the two ports of the subcircuit across which activity should be measured if
they are non-standard (standard is first two ports for R,L,C,D, and first and third port for
transistors).
Note that multiple testbenches can be applied, and their individual activity coverages combined
into a single result, just as their defect coverages, or defect tolerances, can be combined into a
single result. See “Step 9 - Combine Summaries” on page 139 for details.
Activity coverage (in CUT.good_results) can be improved using the following steps, in
sequence:
1. The four thresholds for activity (V_active, Vac_active, I_active, Iac_active) are
adjustable, and have default values. You can also adjust sampling_activity_delay, which
controls the instant at which activity is sampled relative to the instant at which digital
output signals are captured, since peak circuit activity usually occurs slightly after the
active edges of the clock. You should optimize the active thresholds for your VDD level
and type of circuit using a small circuit that simulates in less than a minute, which uses
your chosen cell library and VDD, and which has a testbench. You should optimize
sampling_activity_delay by adding a line .PROBE I(<vdd_source>) in your testbench,
where <vdd_source> is the instance name of the voltage source that provides power to
the CUT. For the small circuit, run create_defect_sites, create_defects_to_simulate, and
simulate_defect_free (possibly without and then with -view_lowest).
a. In EZWave (or another waveform viewer), open defectsim_outdir/
CUT.good_results.wfm (or defectsim_outdir/CUT.defect0_results.wfm if you used
-view_lowest), and observe the clock waveform (if there is a clock) and the current
through the VDD source. If the peaks in current occur systematically slightly after
Diagnosing Undetected Defects
the active clock edge, measure the phase delay to the current peak and set
sampling_activity_delay equal to this delay—it will be different for the simple
circuit than for the real CUT.
2. Re-run create_defects_to_simulate, simulate_defect_free, and run simulate_defects.
Is the activity coverage less than the defect coverage?
a. Yes — Decrease the activity threshold values by a factor of 2, re-run
create_defects_to_simulate and simulate_defect_free, then go to step a).
b. No — For each potential defect site listed, see whether there is essentially no activity
at all (e.g., <1 mV, <1 nA), or a small amount of activity. If there is a small amount
of activity, consider further decreasing the activity thresholds so that these sites are
counted as active.
3. For the remaining inactive sites, look at the circuit and internal waveforms to understand
why the stimulus is not causing activity at each site, and make changes to the stimulus,
such as:
a. Enable a different mode of operation that enables different paths in the circuit.
b. Change the time at which inputs are changed relative to other inputs.
c. Increase the applied frequency so that signals propagate through capacitors.
Note that activity coverage is not affected by which signals you measure, or any test
limits.
4. Make improvements to the stimulus until activity coverage is >90%. It is not essential
for it to be 100% since activity coverage is not an exact prediction of defect coverage, so
your time might be better spent analyzing undetected defects in the next step.
5. Copy the *_active settings into the CUT.defectsim file for your “real” CUT. You will
need to re-adjust sampling_activity_delay. To do this, again add a line .PROBE
I(<vdd_source>) in the testbench, where <vdd_source> is the instance name of the
voltage source that provides power to the CUT. Temporarily set simulation_end_time
equal to the duration of a couple clock cycles, then run create_defect_sites,
create_defects_to_simulate, and simulate_defect_free (possibly without and then with
-view_lowest) - ignore any test failures. As done previously, in EZWave, observe the
delay from active clock edge to peak IDD, and set sampling_activity_delay equal to this
delay.

The Tessent DefectSim command simulate_defects simulates your testbench and CUT with
each randomly selected defect injected, one at a time.
The defect coverage will likely be lower than you want, so this section describes how you can
increase the coverage. If you optimized the stimulus and controllability as described in the
previous section, then insufficient defect coverage is most likely due to the nature of the defects
injected, or the observability and response analysis (measurements, test limits, digital outputs,
and capture instants). To benefit from the Tessent DefectSim tool's analysis of undetected
defects, in CUT.defectsim be sure the following are set to their default values:
report_controllability_in_summary on
report_observability_in_summary on
First note that it is possible the defect coverage measured is too high—this could be due to a test
that fails the circuit when it is defect-free but varying due to process, VDD, or temperature
(PVT). You must ensure that any testbench passes defect-free circuits at process corners,
otherwise your yield would be too low (a test which fails all circuits achieves 100% fault
coverage, and a circuit which is not tested will have 100% yield—you are striving to create a
test that fails only truly defective circuits). Simulations at process corners with acceptable test
bounds are assumed to have been done during the design stage, before running Tessent
DefectSim, but the tests can be checked with simulate_defect_free by using process corner files
instead of typical, and applying worst-case test conditions (VDD, temperature).
Here are some examples of tests that are not process tolerant:
• Digital outputs sampled with finer resolution than one clock period, or unclocked digital
outputs that are sampled with resolution that is too small. Always use the coarsest
resolution practical.
• Sampling digital outputs from a free-running oscillator or unstable PLL—you should
measure a single rise-to-rise or rise-to-fall delay instead. Note that an arming sequence
might be needed to measure the intended pair of edges, and there might be arming-
sequence limitations in the ATE.
• Test limits that are too tight—ensure the limits are wide enough to accommodate normal
PVT variations, though it is common to make test limits valid for only one VDD voltage
and one temperature.
• Sampling a clocked digital output whose delay can vary across clock period
boundaries—after running simulate_defect_free, copy defectsim_outdir/
CUT.good_output_vector into your working directory, rename it, then edit it to replace
1 or 0 with X at any cycles where the logic value is subject to PVT variations. You must
also set user_defined_good_vector in CUT.defectsim to point to the edited file. You
may also adjust sampling_threshold_voltage or list a second voltage so that a voltage
between the two voltages is considered as X.
After ensuring you have PVT-tolerant tests, custom defect/fault models that model only defects
you care about, and test stimuli that activate almost all defect sites, the next step is to diagnose
why some defects are not detected by the response analysis.
In the CUT.defectsim_summary, there is a section titled UNDETECTED DEFECTS. For each

defect listed, you will see details like the following (available using create_example for
EXAMPLE_PLL1):
Defect 396: [pre-layout, relative likelihood 1.000] transistor MN3 stuck-on,in instance
XPLL.X17 of subcircuit LOGIC_OR2 * Alter 4 defect location in subckt names: PLL.LOGIC_OR2
Mode Max_absolute Avg_absolute Max_relative Avg_relative (for Vdefect-Vgood)TRAN
227.10 mV 224.62 mV >999.99% >999.99%
Lowest-level instance for |Vdefect-Vgood| < V_observable at all port signals:
XPLL.X17Largest |Vdefect-Vgood| observed: 3.300V at port 2, named B
Here is how to use this information provided for this undetected defect:
1. The defect headline indicates the type of defect: transistor MN3 stuck-on. (Presently,
the same label is used for all custom defects, but in Tessent v2018.2, you will be able to
provide a custom label.)
2. When viewing your schematic in ADE, Pyxis, or other supported viewer, you can
highlight the circuit element containing the undetected defect by opening the AMS-
Results Browser, selecting the instance path (red text in the code snippet above) and
pressing Ctrl-K.
The instance path is usually assigned automatically by the schematic capture tool, so an
equivalent to the instance path is listed, where each instance is replaced by the subcircuit
name that the designer chose, and thus it has more meaning, for example,
PLL.LOGIC_OR2.
3. Controllability information (purple text in the code snippet above) is provided to show
how much the defect affected the voltage across the defect site. If you previously
achieved high activity coverage, there should be no surprises in the controllability
information.
a. The Max_absolute value indicates that injecting the stuck-on transistor caused the
source-drain voltage to change (increase or decrease, we don't care) by a maximum
of 227 mV, when considering the voltages captured once per sampling_interval.
b. The Avg_absolute value of the voltage changes was 224 mV and is almost equal to
the maximum, which indicates this change was almost constant across all captured
voltages, so you could try to detect the defect at any convenient time.
c. If the Avg_absolute value is much less than the Max_absolute value, then the time at
which you should try to detect the defect must be chosen carefully. Check
CUT.defect_results to see all the voltages captured across defect site D396.
d. For high-gain circuits, the absolute value of changes is less important than the
relative change (in percent, relative to the defect-free value), so that is reported too.
In this case, it is over 1000%.
e. All voltages and currents captured are saved in CUT.defective_*_measurements and
CUT.defect_free_*_measurements (* is v or i), in the defectsim_outdir directory.
The values are saved with 10 digits of precision— if you have .OPTION
NUMDGT=3 in your testbench, it makes this file easier to read.
4. Observability information (green text in the code snippet above) is provided to show
how far from the defect site the effect of the defect propagates in any direction. Input
signal voltages typically are identical with and without the defect, but outputs from
lower level subcircuits that contain the defect are likely to be affected.
a. The voltages captured at each port of the subcircuit containing the defect site are
checked first to see whether the changes in voltages caused by the defect injection
exceed the threshold for observability. If a change is less than
V_observability_ignore (default is 1mV), which you set in CUT.defectsim, then
nothing is reported about that signal. If the change in at least one port signal exceeds
V_observable (default is 100 mV), then Tessent DefectSim saves this information in
CUT.defect_results and considers the next higher-level subcircuit; if no changes
exceed V_observable, then the instance one level lower is reported in the summary.
b. For this PLL example, the defect is in instance XPLL.X17 of LOGIC_OR2, and
caused a 3.3 V voltage change in port 2, named B, of the subcircuit. The subcircuit
one level higher is the top-level of the PLL, and since this defect is undetected, that
3.3 V change in the logic gates did not affect any output of the PLL at any time that
was captured, nor did it affect any parametric tests. The following is reported for this
defect in CUT.defect_results:
max|Vdefect-Vgood| Observable Port path
3.300V Yes XPLL.X17.1
3.300V Yes XPLL.X17.2
227.104mV Yes XPLL.X17.3
All of the LOGIC_OR2's ports changed by more than V_observable relative to their
values without the defect, and the largest change was reported in
CUT.defectsim_summary. Port 3 is the output, and the defect caused the output
levels to change by only 227 mV.
c. Next we can look in CUT.defective_observability_measurements, to understand
why the large voltage change on the OR gate's inputs did not affect its output.
# ALTER title # D396: TRANSISTOR MN3 STUCK-ON, IN INSTANCE XPLL.X17 OF SUBCIRCUIT
LOGIC_OR2
# TEMPERATURE = 2.500000e+01
# TIME
#VX(XPLL.X17.1) VX(XPLL.X17.2) VX(XPLL.X17.3) VX(XPLL.X17.4) VX(XPLL.X17.5)
0.000e+00 1.650e+00 1.650e+00 2.038e-01 3.300e+00 0.000e+00
4.000e-08 1.596e-07 1.718e-06 -5.198e-05 3.300e+00 0.000e+00
8.000e-08 3.300e+00 3.300e+00 2.271e-01 3.300e+00 0.000e+00
1.200e-07 3.300e+00 3.300e+00 2.271e-01 3.300e+00 0.000e+00
The output (port 3) remains at 227 mV for the rest of the simulation.
d. Using EZWave viewer, check the waveforms of the defect-free simulation.
Reducing Test Time
i. All the waveform databases are in defectsim_outdir directory. If only

simulate_defect_free was run, the waveforms will be in CUT.good_cir.wdb. If
simulate_defect_free -view_lowest was also run, then the waveforms of interest
will be in CUT.defect0.wdb.
ii. For this case, in the defect-free simulation, the output is a continuous logic 0.
5. Use a different stimulus so that the logic gate's output logic value changes some time
during the test, and its value propagates to an output of the PLL or affects a test
parameter.
Reducing Test Time

After you have improved your test to achieve a target defect coverage, you can investigate ways
to improve the test cost without reducing the coverage. Test cost is usually dominated by test
time, but sometimes a test requires more costly capabilities in an ATE, which increases the cost
per second and might limit the choice of testers. Some tests might require additional DFT circuit
area, or conversely prevent the implementation of multi-site testing. For the general case, an
overall minimum test cost is difficult to find, but some basic approaches can be used to find a
near-optimum.
Here are some ways to use Tessent DefectSim to reduce test time:
1. In each testbench, find the time, after which, no additional defects are detected.
In the above CUT.defectsim_summary defect detection matrix, no digital samples detect

any more defects after sample 3, which occurs at 120 µs (sampling_interval 60 µs,
sampling_start_time 0 µs). It appears the test could be shortened to 120 µs, except some
of the parameter tests detect defects at a later time— the last is at 960 µs. Therefore, the
test could be shortened to 1 ms (from 4.08 ms).
2. In the combined summary for all testbenches, identify those that do not detect additional
defects.
Reducing Test Time
In the example summary defect detection matrix below, the testbenches from Summary
Files 1 and 2 detect all the defects detected by the other testbenches, as do Summary
Files 9 and 11, and a few other pairs of testbenches. The test costs (test time, test
instruments used, multi-site test, and so on) for each of those tests should be considered
before deciding which pair of tests to choose.
Combined likelihood-weighted defect coverage: 89.2%3%
DefectSim combined summary file

Summary Files
000000000111
123456789012
Defect
D3 D-------D--D
D29 D--D----D-D-
D102 -D---D--DDD-
D548 D--D-D----D-
D1056 ------------
Summary filenames FileDate & Time Coverage

1. CUT.defectsim_summary 11/27/2017 14:02:20 77.15%
2. CUT-test2.defectsim_summary 11/27/2017 15:02:20 70.43%
10. CUT-test3.defectsim_summary 11/27/2017 16:02:20 8.67%
...
11. CUT.defectsim_summary_hot 11/27/2017 17:02:20 65.22%
12. sim2/CUT.defectsim_summary 11/27/2017 18:02:20 8.19%
3. For the tests selected from the combined summary, set stop_on_detection off in
CUT.defectsim, and then re-run simulate_defects. This will allow you to see all the times
that each defect is detected, instead of just the first time. Then you will be able to see
whether portions of the testbench can be re-ordered so that all defects are detected
sooner (for some tests, re-ordering the test pattern is not practical or would change the
coverage).
Reducing Test Time
Appendix I
Getting Help
There are several ways to get help when setting up and using Tessent software tools. Depending
on your need, help is available from documentation, online command help, and Mentor
Graphics Support.
The Tessent Documentation System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Mentor Support Services. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
The Tessent Documentation System

At the center of the documentation system is the InfoHub that supports both PDF and HTML
content. From the InfoHub, you can access all locally installed product documentation, system
administration documentation, videos, and tutorials. For users who want to use PDF, you have a
PDF bookcase file that provides access to all the installed PDF files.
For information on defining default HTML browsers, setting up browser options, and setting the
default PDF viewer, refer to the “Documentation Options” in the Mentor Documentation
System manual.
You can access the documentation in the following ways:
• Shell Command — On Linux platforms, enter mgcdocs at the shell prompt or invoke a
Tessent tool with the -manual invocation switch.
• File System — Access the Tessent InfoHub or PDF bookcase directly from your file
system, without invoking a Tessent tool. For example:
HTML:
firefox $MGC_DFT/docs/infohubs/index.html
PDF
acroread $MGC_DFT/docs/pdfdocs/_bk_tessent.pdf
• Application Online Help — ou can get contextual online help within most Tessent
tools by using the “help -manual” tool command. For example:
> help dofile -manual
This command opens the appropriate reference manual at the “dofile” command
description.
Getting Help
Mentor Support Services
Mentor Support Services

Mentor provides a range of industry-leading support services that keep design teams productive
and up-to-date with Mentor products.
A Mentor support contract includes the following:
• Software Updates — Get the latest releases and product enhancements to keep your
environment current.
• Mentor Graphics Support Center — Access our online knowledge base, personalized
to your Mentor products.
• Support Forums — Learn, share, and connect with other Mentor users.
• Technical Support — Collaborate with Mentor support engineers to solve complex
design challenges.
• Regular Communications — Receive the latest knowledge base articles and
announcements for your Mentor products.
• Mentor Ideas — Share ideas and vote for your favorites to shape future products.
More information is available here:
https://support.mentor.com
If your site is under a current support contract, but you do not have a Support Center login,
register today:
https://support.mentor.com/register
Third-Party Information
Provides information on open source and third-party software that may be included in Tessent products.
For third-party information, refer to the Third-Party Software for Tessent Products document. Additional open source
and third-party software information may be found in <your_Mentor_Graphics_documentation_directory>/legal
End-User License Agreement
with EDA Software Supplemental Terms
Use of software (including any updates) and/or hardware is subject to the End-User License Agreement together with the
Mentor Graphics EDA Software Supplement Terms. You can view and print a copy of this agreement at:
mentor.com/eula

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Tessent® DefectSim User’s Manual

Software Version 2020.1

Support Center: support.sw.siemens.com

Revision Changes Status/

Tessent® DefectSim User’s Manual, v2020.1

Revision History ISO-26262

Tessent® DefectSim User’s Manual, v2020.1 5

6 Tessent® DefectSim User’s Manual, v2020.1

Tessent® DefectSim User’s Manual, v2020.1 7

8 Tessent® DefectSim User’s Manual, v2020.1

Subcircuit File Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Tessent® DefectSim User’s Manual, v2020.1 9

10 Tessent® DefectSim User’s Manual, v2020.1

Figure 1-1. Number of Defects vs. Their Likelihood . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Tessent® DefectSim User’s Manual, v2020.1 11

12 Tessent® DefectSim User’s Manual, v2020.1

Tessent® DefectSim User’s Manual, v2020.1 13

The likelihood of a defect is an important consideration since it varies tremendously, as shown

14 Tessent® DefectSim User’s Manual, v2020.1

Figure 1-1. Number of Defects vs. Their Likelihood

• High-Level Models — Automatically substituting macromodels (that you created),

Tessent® DefectSim User’s Manual, v2020.1 15

circuit) with multi-threading since there is no inter-dependence between the parallel

16 Tessent® DefectSim User’s Manual, v2020.1

Figure 1-2. Overview of Software Steps

Tessent® DefectSim User’s Manual, v2020.1 17

Figure 1-3. Default Injected Defects

18 Tessent® DefectSim User’s Manual, v2020.1

Figure 2-1. Testbench Overview

Tessent® DefectSim User’s Manual, v2020.1 19

Summary of All Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

20 Tessent® DefectSim User’s Manual, v2020.1

Summary of All Commands

The primary files and directories are as follows:

defectsim <CUT> (<CUT> may include a hierarchical path)

followed by one of the following commands (see Steps 1 to 8 for details):

• help command_name — To see list of allowed options.

Tessent® DefectSim User’s Manual, v2020.1 21

• create_consolidated_subcircuits — To copy all found subcircuit files into the mmodels,

22 Tessent® DefectSim User’s Manual, v2020.1

• simulate_defects — To simulate the randomly selected defects, and summarize the

• set_defectsim_config_value — To modify a <CUT>.defectsim parameter from within a

Tessent® DefectSim User’s Manual, v2020.1 23

• report_defectsim_config_value — To report the value of a <CUT>.defectsim parameter

• create_consolidated_subcircuits may be invoked as follows:

but not by “create_con”.

but not by “create_defect”.

but not by “create_defect”.

24 Tessent® DefectSim User’s Manual, v2020.1

but not by “simulate_defect” (which will run simulate_defects).

but not by “simulate_defect_free”.

defectsim <CUT> “<command>; <command>; <command>”

• echo — Display value of a parameter

Tessent® DefectSim User’s Manual, v2020.1 25

• set_cut — Reads the <CUT>.defectsim or <CUT>-<test>.defectsim file.

Here is an illustrative example of interactive mode:

defectsim> report_config_option schematics_directory

defectsim> report_config_option {schematics_directory layouts_directory

defectsim> set myoptions "schematics_directory layouts_directory"

defectsim> report_config_option $myoptions

defectsim> system pwd

26 Tessent® DefectSim User’s Manual, v2020.1

defectsim <CUT> create_defectsim_config