= 0S INTEGRATED CIRCUITS MC1120P SERIES‘GENERAL INFORMATION MOS MC1120P series This low-cost MOS integrated circuit series is designed specifically for elec- tronic organ applications. CASE 93 (ro-n6) 03s 1 0 ESM ROE pT © Ma soesonimsareate sting am, © Aisin state re provi. FUNCTIONS AND CHARACTERISTICS (V; —10V, T, = 25°C) ‘output re | Loading | output | operating Totat casess | Factor | voltage | Frequency Power Each ‘swing Dissipation FUNCTION oto+75r¢ | output | volts hae typo, Dual Keyer Gate with Snub Inputs mcri20, 3 12 | dto100 10 Frequency Divider (Four Stage) McniZa 5 10 | Oto 100 190 MAXIMUM RATINGS RATING VALUE, UNIT Power Supply Voltage —40t0 403 Vee Input Voltage — MC1120P —40t0 403 Vide Mc1i24P —30t0- 40.3 Operating Temperature Ran 0t0 +75 °c ‘Storage Temperature Range 85 to $125 7e 7-2DUAL KEYER GATE MOS MC1120P series ith Snub Inputs MC1120P ‘A monolithic circuit consisting of two gates with key and snub inputs. '* Noise immunity = 1.0 Volt ¢ Minimum Fan-Out = 5 ‘© Temperature Range = 0 to +75°C 1 ta Snub #2 (1) 2 13 (YS Impure #1 Key #2E-00) 3 12 oa Output #2 F118) 4 u i Vs Fa CASE 93 8 10 (rosie) (5) Ourpur #1 i) 6 9 (CS Key #1 input #2300) 7 8 ona Snub #11311) Number in parenthesis = loading factor CIRCUIT SCHEMATIC 96 u O13 7-3MC1120P (continued) MAXIMUM RATINGS Rating Symbol} Value | Unit Source Voltage ¥, -401040.9] vae Tapa, Saub, Key Voltages “a0 10.3} Vae ‘Operating Temperature Range 7, ves |e “Storage Temperatore Range 7, “sto ae| ELECTRICAL CHARACTERISTICS (T,=25*C ues ctanis rte) ee ry ae “as [| [3 comenile Ta [ae [ar | vk [atonement ar PETS tee oe - os | - roo | wade | if: o |e |nis aces fe Gee tas | te i totes ooo ws ® » (on) | 3 | 70 = |uad | - | | as - a8 wamwoman Treo $2 [ise hat ts fs [ies carr oma Tie Te f= Test te Pe pedal © Tart om | az [evo] = | vac - ps ~ [uli TYPICAL APPLICATION som Fo Tees Closing of the organ key “enables” the KEYER GATE, permitting subsequent pulses applied to the signal input to ‘pass through the gate, and simultaneously charges capacitor C. When the key Is released the stored charge maintains the gate conduction until charge is removed. The SNUB line Provides @ means of varying the total resistance in parallel with the capacitor by controlling the series impedance of the MOS transistor. Therefore the length of time thet the note is sustained after the key Is relessed depends upon the snub voltage. 7-4FREQUENCY DIVIDER MC1124P A monolithic circuit consisting of four flip-flops with single rail inputs and Q and Q outputs. To le Frequency = DC to 500 kHz Immunity = 1.0 Volt Minimum Fan-Out = & ‘Temperature Range = 0 to +75°C MOS MC1120P series CASE 93 (T0116) i (6) “vs “Yoo 6) co) wo Number in parenthesis = load: Ing factor Note To cascade flip-lop stages, (trigger out) t0 Tin (trigger in) of the next stage. CIRCUIT SCHEMATIC Tina 08 tof Ba wt zy 75MC1124P (continued) MAXIMUM RATINGS ating ‘Symbol Valve Unie Drain Voltage Vpp | eas | vee “Trigger Input Voltage Vin ~30%090.3 | vac Operating Temperature Range 7) en *e Storage Temperature Range Ty | stones *e ELECTRICAL CHARACTERISTICS in ea Vonage OTA = PC Charateriste Symbot | under | Min | Max | unit PVTin | —-Vop[Vs i = [ats 1 aE | IDO. 5 VEE] Groans Apple fo pas Used eto Drain Sppiy Dra Garret | Typ ene [area Source Supaly Drain Gurreat [Ips |= [a [ona [fraser [fares Source Sopiy beatae Correa] Tyg m= 80 Puna | B fiasa sii TE Logical 70" Oat VoRRRE | Vg 5 ra) Coon 7 Fi $f cao]: i] on 2 i wf 0] goon 2 : mw | so] gl 2 i "Sagal Towa Vala | Y, 3 [- Paspwey a] a 2 T cs ‘ 2s af oon 2 i wf: [as s] ou 2 ; |? 135 {ou 2 Wages" Oupat VaraGe | Vo ee ey 1% 7 2 [ao |: i) ou 2 1 s [cio |: a] oon @ i a | Sin |: a] 2 i Wage ouipa Varaae] 1. fase] a] ar 2 7 a 2 |: [3s 1] on @ i 3 |: [os i] a @ i sf || a] it i i Teale Frequency Tron roo f= [ae Bee Test ingram TVR, — Precet to desired ouput Tevel by Applying “20 Wae To tpt Won open, TOGGLE FREQUENCY TEST DIAGRAMS AND WAVEFORMS Foue(14) = 1/2913) fout() = 1/4 fig 13) “IY Lr “0 | cout) L Tout10) = 172 fn) toutl6) = 172 nad ov ton 1d be 7-6