COA Merge

Bharati Vidyapeeth’s College of Engineering for Women, Pune
Department of Information Technology

Computer Organization and Architecture
Online Examination Question Bank
UNIT IV
Q.1) The smallest entity of memory is called as _______ .

a) Cell
b) Block
c) Instance
d) Unit
Q.2) An 24 bit address generates an address space of ______ locations .
a) 1024
b) 4096
c) 2 ^ 48
d) 16777216
Q.3) If a system is 64 bit machine , then the length of each word will be ____ .
a) 4 bytes
b) 8 bytes
c) 16 bytes
d) 12 bytes
Q.4) The type of memory assignment used in Intel processors is _____ .
a) Little Endian
b) Big Endian
c) Medium Endian
d) None of the above
Q.5) When using the Big Indian assignment to store a number, the sign bit of the number is
stored in _____ .
a) The higher order byte of the word
b) The lower order byte of the word
c) Can’t say
Q.6) To get the physical address from the logical address generated by CPU we use ____ .
a) MAR
b) MMU
c) Overlays
d) TLB
Q.7) _____ method is used to map logical addresses of variable length onto physical memory.
a) Paging
b) Overlays
c) Segmentation
d) Paging with segmentation
Q.8) During transfer of data between the processor and memory we use ______ .
a) Cache
b) TLB
c) Buffers
d) Registers
Q.9) Physical memory is divided into sets of finite size called as ______ .
a) Frames
b) Pages
c) Blocks
d) Vectors
Q.10) he DMA differs from the interrupt mode by
a) The involvement of the processor for the operation
b) The method accessing the I/O devices
c) The amount of data transfer possible
d) Both a and c
Q.11) The DMA transfers are performed by a control circuit called as
a) Device interface
b) DMA controller
c) Data controller
d) Over looker
Q.12) In DMA transfers, the required signals and addresses are given by the
a) ) Processor
b) Device drivers
c) DMA controllers
d) The program itself
Q.13) After the completion of the DMA transfer the processor is notified by
a) Interrupt signal
b) WMFC signal
c) None of the above
Q.14) The DMA controller has _______ registers
a) 4
b) 2
c) 3
d) 1
Q.15) hen the R/W bit of the status register of the DMA controller is set to 1,
a) Read operation is performed
b) Write operation is performed
c) both
Q.16) The controller is connected to the ____
a) Processor BUS
b) System BUS
c) External BUS
Q.17) Can a single DMA controller perform operations on two different disks simultaneously…?
a) True
b) False
Q.18) The technique whereby the DMA controller steals the access cycles of the processor to
operate is called
a) Fast conning
b) Memory Con
c) Cycle stealing
d) Memory stealing
Q.19) The technique where the controller is given complete access to main memory is
a) Cycle stealing
b) Memory stealing
c) Memory Con
d) Burst mode
Q.20) The controller uses _____ to help with the transfers when handling network interfaces.
a) Input Buffer storage
b) Signal enhancers
c) Bridge circuits
d) All of the above
Q.21) To overcome the conflict over the possession of the BUS we use ______
a) Optimizers
b) BUS arbitrators
c) Multiple BUS structure
Q.22) The registers of the controller are ______
a) 64 bits
b) 24 bits
c) 32 bits
d) 16 bits
Q.23) When process requests for a DMA transfer,
a) Then the process is temporarily suspended
b) The process continues execution
c) Another process gets executed
d) Both a and c
Q.24) The DMA transfer is initiated by _____
a) Processor
b) The process being executed
c) I/O devices
d) OS
Q.25) Add 01011101,R1 , when this instruction is executed then,
a) The binary addition between the operands takes place
b) The Numerical value represented by the binary value is added to the value of R1
c) The addition doesn’t take place , whereas this is similar to a MOV instruction
Q.26) If we want to perform memory or arithmetic operations on data in Hexa-decimal mode
then we use ___ symbol before the operand .
a) ~
b) !
c) $
d) *
Q.27) When generating physical addresses from logical address the offset is stored in _____ .
a) Translation look-aside buffer
b) Relocation register
c) Page table
d) Shift register
Q.28) The technique used to store programs larger than the memory is ______ .
a) Overlays
b) Extension registers
c) Buffers
d) Both b and c
Q.29) The unit which acts as an intermediate agent between memory and backing store to reduce
process time is _____ .
a) TLB’s
b) Registers
c) Page tables
d) Cache
Q.30) The Load instruction does the following operation/s,
a) Loads the contents of a disc onto a memory location
b) Loads the contents of a location onto the accumulators
c) Load the contents of the PCB onto the register
d) Both a and c
Q.31) Complete the following analogy :- Registers are to RAM’s as Cache’s are to _____ .
a) Hard disk
b) ROM
c) RAM
d) Fast solid state chips in the motherboard
Q.32) The BOOT sector files of the system are stored in _____ .
Q.33) The transfer of large chunks of data with the involvement of the processor is done by
_______ .
a) DMA controller
b) Arbitrator
c) User system programs
Q.34) Which of the following technique/s used to effectively utilize main memory ?
a) Address binding
b) Dynamic linking
c) Dynamic loading
d) Both b and c
Q.35) The standard SRAM chips are costly as
a) They use highly advanced micro-electronic devices.
b) They house 6 transistor per chip.
c) They require specially designed PCB’s.
d) None of the above.
Q.36) The drawback of building a large memory with DRAM is
a) The large cost factor.
b) The inefficient memory organization.
c) The Slow speed of operation.
d) All of the above.
Q.37) To overcome the slow operating speeds of the secondary memory we make use of faster
flash drives.
a) True
b) False
Q.38) The fastest data access is provided using _______.
a) Caches
b) DRAM’s
c) SRAM’s
d) Registers
Q.39) The memory which is used to store the copy of data or instructions stored in larger
memories, inside the CPU is called _______.
a) Level 1 cache
b) Level 2 cache
c) Registers
d) TLB
Q.40) The larger memory placed between the primary cache and the memory is called ______.
a) Level 1 cache
b) Level 2 cache
c) EEPROM
d) TLB
Q.41) The next level of memory hierarchy after the L2 cache is _______.
a) Secondary storage
b) TLB
c) Main memory
d) Register
Q.42) The last on the hierarchy scale of memory devices is ______.
a) Main memory
b) Secondary memory
c) TLB
d) Flash drives
Q.43) In the memory hierarchy, as the speed of operation increases the memory size also
increases.
a) True
b) False
Q.44) If we use the flash drives instead of the hard disks, then the secondary storage can go
above primary memory in the hierarchy.
a) True
b) False
Q.45) The reason for the implementation of the cache memory is

a) To increase the internal memory of the system
b) The difference in speeds of operation of the processor and memory
c) To reduce the memory access and cycle time
d) All of the above
Q.46) The effectiveness of the cache memory is based on the property of ________.
a) Locality of reference
b) Memory localization
c) Memory size
Q.47) The temporal aspect of the locality of reference means
a) That the recently executed instruction wont be executed soon
b) That the recently executed instruction is temporarily not referenced
c) That the recently executed instruction will be executed soon again
Q.48) The spatial aspect of the locality of reference means
a) That the recently executed instruction is executed again next
b) That the recently executed won’t be executed again
c) That the instruction executed will be executed at a later time
d) That the instruction in close proximity of the instruction executed will be executed
in future
Q.49) The correspondence between the main memory blocks and those in the cache is given by
_________.
a) Hash function
b) Mapping function
c) Locale function
d) Assign function
Q.50) The algorithm to remove and place new contents into the cache is called _______.
a) Replacement algorithm
b) Renewal algorithm
c) Updation
Q.51) The write-through procedure is used
a) To write onto the memory directly
b) To write and read from memory simultaneously
c) To write directly on the memory and the cache simultaneously
Q.52) The bit used to signify that the cache location is updated is ________.
a) Dirty bit
b) Update bit
c) Reference bit
d) Flag bit
Q.53) The copy-back protocol is used
a) To copy the contents of the memory onto the cache
b) To update the contents of the memory from the cache
c) To remove the contents of the cache and push it on to the memory
Q.54) The memory blocks are mapped on to the cache with the help of ______.
a) Hash functions
b) Vectors
c) Mapping functions
Q.55) During a write operation if the required block is not present in the cache then ______
occurs.
a) Write latency
b) Write hit
c) Write delay
d) Write miss
Q.56) In ________ protocol the information is directly written into main memory.
a) Write through
b) Write back
c) Write first
Q.57) The only drawback of using the early start protocol is _______.
a) Time delay
b) Complexity of circuit
c) Latency
d) High miss rate
Q.58) The method of mapping the consecutive memory blocks to consecutive cache blocks is
called ______.
a) Set associative
b) Associative
c) Direct
d) Indirect
Q.59) While using the direct mapping technique, in a 16 bit system the higher order 5 bits is used
for ________.
a) Tag
b) Block
c) Word
d) Id
Q.60) In direct mapping the presence of the block in memory is checked with the help of block
field.
a) True
b) False
Q.61) In associative mapping, in a 16 bit system the tag field has ______ bits.
a) 12
b) 8
c) 9
d) 10
Q.62) The associative mapping is costlier than direct mapping.
a) True
b) False
Q.63) The technique of searching for a block by going through all the tags is ______.
a) Linear search
b) Binary search
c) Associative search
Q.64) The set associative map technique is a combination of the direct and associative technique.
a) True
b) False
Q.65) The main memory is structured into modules each with its own address register called
______.
a) ABR
b) TLB
c) PC
d) IR
Q.66) When consecutive memory locations are accessed only one module is accessed at a time.
a) True
b) False
Q.67) In memory interleaving, the lower order bits of the address is used to
a) Get the data
b) Get the address of the module
c) Get the address of the data within the module
Q.68) The number successful accesses to memory stated as a fraction is called as _____.
a) Hit rate
b) Miss rate
c) Success rate
d) Access rate
Q.69) The number failed attempts to access memory, stated in the form of fraction is called as
_________.
a) Hit rate
b) Miss rate
c) Failure rate
d) Delay rate
Q.70) In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the
others are incremented by one, when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
Q.71) In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are
incremented by one and others remain same, in case of ______.
a) Hit
b) Miss
c) Delay
Q.72) If hit rates are well below 0.9, then they’re called as speedy computers.
a) TRUE
b) FALSE
Q.73) The extra time needed to bring the data into memory in case of a miss is called as _____.
a) Delay
b) Propagation time
c) Miss penalty
Q.74) The miss penalty can be reduced by improving the mechanisms for data transfer between
the different levels of hierarchy.
a) TRUE
b) FALSE
Q.75) The physical memory is not as large as the address space spanned by the processor.
a) TRUE
b) FALSE
Q.76) The program is divided into operable parts called as _________.
a) Frames
b) Segments
c) Pages
d) Sheets
Q.77) The techniques which move the program blocks to or from the physical memory is called
as ______.
a) Paging
b) Virtual memory organization
c) Overlays
d) Framing
Q.78) The binary address issued to data or instructions are called as ______.
a) Physical address
b) Location
c) Relocatable address
d) Logical address
Q.79) . __________is used to implement virtual memory organisation.
a) Page table
b) Frame table
c) MMU
Q.80) . ______ translates logical address into physical address.
a) MMU
b) Translator
c) Compiler
d) Linker
Q.81) The main aim of virtual memory organization is
a) To provide effective memory access.
b) To provide better memory transfer.
c) To improve the execution of the program.
d) All of the above.
Q.82) The DMA doesn’t make use of the MMU for bulk data transfers.
a) TRUE
b) FALSE
Q.83) The virtual memory basically stores the next segment of data to be executed on the
_________.
b) Disks
c) RAM
d) ROM
Q.84) The associatively mapped virtual memory makes use of _______.
a) TLB
b) Page table
c) Frame table
Q.85) In memory-mapped I/O…
a) The I/O devices and the memory share the same address space
b) The I/O devices have a separate address space
c) The memory and I/O devices have an associated address space
d) A part of the memory is specifically set aside for the I/O operation
Q.86) The usual BUS structure used to connect the I/O devices is
a) Star BUS structure
b) Multiple BUS structure
c) Single BUS structure
d) Node to Node BUS structure
Q.87) In Intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices..??
a) FALSE
b) TRUE
Q.88) The advantage of I/O mapped devices to memory mapped is
a) The former offers faster transfer of data
b) The devices connected using I/O mapping have a bigger buffer space
c) The devices have to deal with fewer address lines
d) No advantage as such
Q.89) The system is notified of a read or write operation by
a) Appending an extra bit of the address
b) Enabling the read or write bits of the devices
c) Raising an appropriate interrupt signal
d) sending a special signal along the BUS
Q.90) To overcome the lag in the operating speeds of the I/O device and the processor we use
a) Buffer spaces
b) Status flags
c) Interrupt signals
d) Exceptions
Q.91) The method of accessing the I/O devices by repeatedly checking the status flags is
a) Program-controlled I/O
b) Memory-mapped I/O
c) I/O mapped
d) None
Q.92) The method of synchronizing the processor with the I/O device in which the device sends
a signal when it is ready is
a) Exceptions
b) Signal handling
c) Interrupts
d) DMA
Q.93) The method which offers higher speeds of I/O transfers is
a) Interrupts
b) Memory mapping
c) Program-controlled I/O
d) DMA
Q.94) The process where in the processor constantly checks the status flags is called as
a) Polling
b) Inspection
c) Reviewing
d) Echoing
Q.95) What characteristic of RAM memory makes it not suitable for permanent storage?
a) too slow
b) unreliable
c) it is volatile
d) too bulky
Q.96) The idea of cache memory is based
a) on the property of locality of reference
b) on the fact that references generally tend to cluster
c) on the heuristic 90-10 rule
d) all of the above
Q.97) Which of the following is lowest in memory hierarchy?
a) Cache memory
b) Secondary memory
c) Registers
d) RAM
Q.98) If memory access takes 20 ns with cache and 110 ns without it, then the ratio ( cache uses
a 10 ns memory) is
a) 93%
b) 90%
c) 88%
d) 87%
Q.99) In a memory-mapped I/O system, which of the following will not be there?
a) LDA
b) IN
c) ADD
d) OUT
Q.100) Cache memory acts between
a) CPU and RAM
b) RAM and ROM
c) CPU and Hard Disk
d) None of these
Q.101) Write Through technique is used in which memory for updating the data
a) Virtual memory
b) Main memory
c) Auxiliary memory
d) Cache memory
Q.102) Generally Dynamic RAM is used as main memory in a computer system as it
a) Consumes less power
b) has higher speed
c) has lower cell density
d) needs refreshing circuitry
Q.103) Virtual memory consists of
a) Static RAM
b) Magnetic memory
c) Dynamic RAM
d) None of these
Q.104) If the main memory is of 8K bytes and the cache memory is of 2K words. It uses
associative mapping. Then each word of cache memory shall be
a) 11 bits
b) 21 bits
c) 16 bits
d) 20 bits
Q.105) Cache memory works on the principle of
a) Locality of data
b) Locality of memory
c) Locality of reference
d) Locality of reference & memory
Q.106) The main memory in a Personal Computer (PC) is made of
a) cache memory.
b) static RAM
c) Dynamic Ram
d) both (A) and (B) .
Q.107) Memory unit accessed by content is called
a) Read only memory
b) Programmable Memory
c) Virtual Memory
d) Associative Memory
Q.108) An interface that provides a method for transferring binary information between internal
storage and external devices is called
a) I/O interface
b) Input interface
c) Output interface
d) I/O bus
Q.109) An interface that provides a method for transferring binary information between internal
storage and external devices is called
a) I/O interface
b) Input interface
c) Output interface
d) I/O bus
Q.110) Status bit is also called
a) Binary bit
b) Flag bit
c) Signed bit
d) Unsigned bit
Q.111) An address in main memory is called
a) Physical address
b) Logical address
c) Memory address
d) Word address
Q.112) The performance of cache memory is frequently measured in terms of a quantity called
a) Miss ratio.
b) Hit ratio.
c) Latency ratio.
d) Read ratio.
Q.113) An interface that provides I/O transfer of data directly to and form the memory unit and
peripheral is termed as
a) DDA.
b) Serial interface.
c) BR.
d) DMA.
Q.114) Which of the following is a main memory
a) Secondary memory.
b) Auxiliary memory.
c) Cache memory.
d) Virtual memory.
Q.115) The memory unit that communicates directly with the CPU is called the
a) main memory
b) Secondary memory
c) shared memory
d) auxiliary memory.
Q.116) The average time required to reach a storage location in memory and obtain its contents
is called
a) Latency time.
b) Access time.
c) Turnaround time.
d) Response time.
Q.117) A page fault
a) Occurs when there is an error in a specific page.
b) Occurs when a program accesses a page of main memory.
c) Occurs when a program accesses a page not currently in main memory.
d) Occurs when a program accesses a page belonging to another program.
Q.118) 24 The average time required to reach a storage location in memory and obtain its
contents is called_____.
a) Latency time.
b) Access time.
c) Turnaround time.
d) Response time.
Q.119) Memory unit accessed by content is called______.
a) Read only memory
b) Programmable Memory
c) Virtual Memory
d) Associative Memory
Q.120) The main memory in a Personal Computer (PC) is made of_____.
a) cache memory.
b) static RAM
c) Dynamic Ram
d) Both A and (B).
Q.121) Cache memory works on the principle of_____.
a) Locality of data
b) Locality of memory
d) Locality of reference & memory
Q.122) 28 If the main memory is of 8K bytes and the cache memory is of 2K words. It uses
associative mapping. Then each word of cache memory shall be_____.
a) 11 bits
b) 21 bits
c) 16 bits
d) 20 bits
Q.123) Virtual memory consists of _______.
a) Static RAM
b) Dynamic RAM
c) Magnetic memory
d) None of these
Q.124) Generally Dynamic RAM is used as main memory in a computer system as it______.
a) Consumes less power
b) has higher speed
c) has lower cell density
d) needs refreshing circuitry
Q.125) Write Through technique is used in which memory for updating the data _____.
a) Virtual memory
b) Main memory
c) Auxiliary memory
d) Cache memory
Q.126) Cache memory acts between_______.
a) CPU and RAM
b) RAM and ROM
c) CPU and Hard Disk
d) None of these
Q.127) In a memory-mapped I/O system, which of the following will not be there?
a) LDA
b) IN
c) ADD
d) OUT
Q.128) If memory access takes 20 ns with cache and 110 ns without it, then the ratio (cache uses
a 10 ns memory) is _____.
a) 93%
b) 90%
c) 88%
d) 87%
Q.129) The idea of cache memory is based ______.
a) on the property of locality of reference
b) on the heuristic 90-10 rule
c) on the fact that references generally tend to cluster
d) all of the above
Q.130) The average time required to reach a storage location in memory and obtain its contents
is called the _____.
a) seek time
b) turnaround time
c) access time
d) transfer time
Q.131) What characteristic of RAM memory makes it not suitable for permanent storage?
a) Too slow
b) unreliable
c) it is volatile
d) Too bulky
Q.132) The access time of memory is ............... the time required for performing any single CPU
operation.
a) Longer than
b) Shorter than
c) Negligible than
d) Same as
Q.133) Memory address refers to the successive memory words and the machine is called as
............
a) word addressable
b) byte addressable
c) bit addressable
d) Tera byte addressable
Q.134) Virtual memory is –
a) an extremely large main memory
b) an extremely large secondary memory
c) an illusion of an extremely large memory
d) a type of memory used in super computers
Q.135) Which memory unit has lowest access time?
a) Cache
b) Registers
c) Magnetic Disk
d) Main Memory
Q.136) Cache memory-
a) has greater capacity than RAM
b) is f aster to access than CPU Registers
c) is permanent storage
d) f aster to access than RAM
Q.137) Which of the following memories must be refreshed many times per second?
a) Static RAM
b) ROM
c) EPROM
d) Dynamic RAM
Q.138) RAM stands for
a) Random origin money b. Random only memory
b) Read only memory d. Random access memory
c) None of these
d) ans Random access memory
Q.139) Run time mapping from virtual to physical address is done by
a) memory management unit
b) CPU
c) PCI
d) none of the mentioned
Q.140) Memory management technique in which system stores and retrieves data from
secondary storage for use in main memory is called
a) fragmentation
b) paging
c) mapping
Q.141) The address of a page table in memory is pointed by
a) stack pointer
b) page table base register
c) page register
d) program counter
Q.142) Program always deals with
a) logical address
b) absolute address
c) physical address
d) relative address
UNIT III
Q.1) …...Holds the last instruction fetched.

a) MAR
b) MBR
c) PC
d) IR
Q.2) The operation executed on data stored in registers is called
a) Macro-operation
b) Micro-operation
c) Bit-operation
d) Byte-operation
Q.3) Which statement is true regarding above micro operation?
a) There are three micro operations in a single clock pulse
b) There are two micro operations in a single clock pulse
c) There is one micro operation in a single clock pulse
d) None
Q.4) Which one is not a type of micro operation?
a) loading micro operation
b) Arithmetic micro operation
c) logical micro operation
d) shift micro operation
Q.5) instruction cycle code (ICC) 01 represents….
a) Fetch
b) Indirect
c) Execute
d) Interrupt
Q.6) A single micro-operation involves,
a) A simple ALU operations
b) Transfer between registers
c) Transfer between register and an external bus
d) All of these
a) Fetch
b) Indirect
c) Execute
d) Interrupt
a) Fetch
b) Indirect
c) Execute
d) Interrupt
a) Fetch
b) Indirect
c) Execute
d) Interrupt
Q.10) Instruction are fetched from successive memory locations until,
a) A next instruction is encountered.
b) A branch or jump instruction is encountered.
c) A previous instruction is encountered.
d) Both a and b.
Q.11) Micro-operations are,
a) Functional or atomic, operations of the processor.
b) Non-functional or nuclear operations of the ALU
c) Functional or gigantic operations of the processor
d) Both b and c
Q.12) Which is the first operation during fetch cycle?
a) Moves contents of memory location specified by MAR to MBR.
b) Increment PC by the instruction length.
c) Moves contents of MBR to IR.
d) Moves contents of PC to MAR.
Q.13) what is the next step after MBR <- Memory, PC<-PC+1 in instruction fetching micro-
operation.
a) IR ← (MBR)
b) Memory <- MBR
c) Memory <- IR
d) None of these
Q.14) what is the next step after MBR <- Memory in instruction fetching micro-operation.
a) PC-1
b) PC+1
c) PC-2
d) PC+2
Q.15) what is the next step after MBR <- Memory in instruction fetching micro-operation.
a) Memory <- MBR
b) Memory <- IR
c) PC+1
d) None of these
Q.16) what is the next step after MAR <- PC in instruction fetching micro-operation.
a) Memory <- MBR
b) Memory <- IR
c) MBR <- Memory
d) None of these
Q.17) The step just before the micro operation MBR <- Memory in instruction fetching micro-
operation is,
a) Memory <- MBR
b) Memory <- IR
c) PC+1
d) MAR <- PC
Q.18) The step just before the micro operation IR ← (MBR) in instruction fetching micro-
operation is,
a) Memory <- MBR,PC+1
b) Memory <- IR
c) PC+1
d) MAR <- PC
Q.19) The micro operation MBR <- Memory in instruction fetching micro-operation must
preceded by …
a) Memory <- MBR
b) Memory <- IR
c) PC+1
d) MAR <- PC
Q.20) The micro-operation MAR <- PC must in instruction fetching micro-operation succeeded
by,
a) Memory <- MBR
b) Memory <- IR
c) MBR <- Memory
d) None of these
Q.21) The micro-operation MAR <- PC is executed to,
a) Fetch an instruction.
b) Fetch data and instruction.
c) Fetch an address.
d) Both a and c.
Q.22) During instruction execution, PC is incremented by the length of,
a) Previously executed instruction.
b) Currently executing instruction.
c) Next instruction to be executed.
d) Smallest instruction executed.
Q.23) what is the next step after MAR <- (IR(Address)) in Micro-operation for Indirect Cycle
a) MBR <- Memory
b) IR(Address) <- (MBR(Address))
c) PC+1
d) PC-1
Q.24) what is the next step after MBR <- Memory in Micro-operation for Indirect Cycle.
a) MBR <- Memory
c) PC+1
d) PC-1
Q.25) The step just before the micro operation IR(Address) <- (MBR(Address)) in Micro-
operation for Indirect Cycle
a) MBR <- Memory
c) PC+1
d) PC
Q.26) The step just before the micro operation MBR <- Memory in Micro-operation for Indirect
Cycle
a) MBR <- Memory
c) MAR <- (IR(Address))
d) PC-1
Q.27) MBR <- Memory in Micro-operation for Indirect Cycle must preceded by….
a) MBR <- Memory
d) PC-1
Q.28) The micro-operation MAR <- (IR(Address)) in indirect cycle must succeeded by,
a) MBR <- Memory
d) PC-1
Q.29) Address of IR must be present in……... register.
a) MAR
b) MBR
c) PC
d) R1
Q.30) what is the next step after MBR <- PC in Micro-operation for Interrupt Cycle
a) MAR <- Save_Address,
b) PC <- Routine_Address,
c) Memory <- (MBR)
d) PC+1
Q.31) What is the next step after MAR <- Save_Address in Micro-operation for Interrupt Cycle.
a) PC <- Routine_Address
b) Memory <- (MBR)
c) PC+1
d) MBR<-PC
Q.32) The step just before the micro operation PC <- Routine_Address in Micro-operation for
Interrupt Cycle.
b) Memory <- (MBR)
c) MAR <- Save_Address
d) MBR<-PC
Q.33) The step just before the micro operation Memory <- MBR in Micro-operation for Interrupt
Cycle.
b) Memory <- (MBR)
d) MBR<-PC
Q.34) MAR <- Save_Address, PC <- Routine_Address in Micro-operation for Interrupt Cycle
must preceded by….
b) Memory <- (MBR)
d) MBR<-PC
Q.35) PC <- Routine_Address in Micro-operation for Interrupt Cycle must preceded by….
b) Memory <- (MBR)
d) MBR<-PC
Q.36) Memory <- (MBR) in Micro-operation for Interrupt Cycle must preceded by….
a) MAR ← Save_Address, PC ← Routine_Address
b) Memory <- (MBR)
d) MBR<-PC
Q.37) The micro-operation MBR <- PC in Interrupt Cycle must succeeded by,
a) MAR <- Save_Address
b) Memory <- (MBR)
c) MAR ← Save_Address, PC ← Routine_Address
d) MBR<-PC
Q.38) what is the next step after MAR ← (IR(address)) in Micro-operation for Execution Cycle
a) MBR ← Memory
b) R1 ← (R1) + (MBR)
c) PC+1
d) None of these
Q.39) What is the next step after MBR <- Memory in Micro-operation for Execution Cycle.
a) MBR ← Memory
b) R1 ← (R1) + (MBR)
c) PC+1
d) None of these
Q.40) The step just before the micro operation MBR ← Memory in Micro-operation for Execution
Cycle
a) MAR ← (IR(address))
b) R1 ← (R1) + (MBR)
c) PC+1
d) None of these
Q.41) The step just before the micro operation R1 ← (R1) + (MBR) in Micro-operation for
Execution Cycle
a) MBR ← Memory
b) R1 ← (R1) + (MBR)
c) PC+1
d) None of these
Q.42) R1 ← (R1) + (MBR) in Micro-operation for Execution Cycle must preceded by….
a) R1 ← (R1) + (MBR)
b) MBR ← Memory
c) PC+1
d) None of these
Q.43) MBR ← Memory in Micro-operation for Execution Cycle must preceded by….
a) R1 ← (R1) + (MBR)
b) PC+1
c) MAR ← (IR(address))
d) None of these
Q.44) The micro-operation MAR ← (IR(address)) in Execution Cycle must succeeded by,
a) R1 ← (R1) + (MBR)
b) PC+1
c) MBR ← Memory
d) None of these
Q.45) The micro-operation MBR <- Memory in Execution Cycle must succeeded by,
a) MAR ← (IR(address))
b) R1 ← (R1) + (MBR)
c) PC+1
d) None of these
Q.46) All operations and data transfers within the processor take place within time periods defied
by the,
a) Processor clock.
b) ALU clock.
c) Register clock.
d) None of these.
Q.47) The set of operations performed by the processor unit during an instruction execution is
called as,
a) Execution operations
b) Decode operations
c) Micro operations
d) Clock operation
Q.48) Data may loaded into MDR,
a) Only From memory bus
b) Only From internal processor bus
c) From PC register or MAR
d) Either from memory bus or from internal processor bus
Q.49) Which control signals will be generated by system, when contents of register R3 are
transferred the MAR?
a) R3out, MARin, Read
b) R3out, MARout, Read
c) R3in, MARin, Read
d) R3out, Read, MARin
Q.50) The control unit of a computer,
a) Stores data in the memory.
b) Accepts input data from keyboard.
c) Generates control signal to execute an instruction.
d) None of the above.
Q.51) which of the following is register to register transfer?
a) MAR <- MBR
b) R1 <- R2
c) ALU <- R1
d) Both a and b
Q.52) The control unit of computer
a) Performs ALU operations on the data
b) Controls the operation of the output devices
c) Is a device for manually operating the computer
d) Direct the other unit of computers
Q.53) The program counter
a) Is a register
b) During execution of the current instruction its content changes
c) Both A and B
d) None of these
Q.54) The control lines of the memory bus are connected to,
a) Control logic blocks
b) Instruction Decoder
c) MAR
d) Instruction Decoder and control logic blocks
Q.55) To fetch a word of information from memory, the processor has to specify the,
a) Address of the memory location and request a read operation.
b) Address of the memory location.
c) Request a read operation.
d) Request a write operation.
Q.56) The processor wait until and unless it receives,
a) Wait Memory Function Completed Signal.
b) Read and write signal.
c) Memory Function Completed Signal.
d) All of these.
Q.57) The control signals generated for the operation MAR <- PC are,
a) PCout, MARin
b) PCin, MARout
c) PCout, MARout
d) PCin, MARin
Q.58) In Branch instruction, the offset value is extracted by which register?
a) PC
b) IR
c) MAR
d) MBR
Q.59) Fill the correct singles in above control sequence step of fetch cycle, Zout, PCin, Yin, …….
a) MFC
b) WMFC
c) Zin
d) Write
Q.60) …….. means the content of register R2 are transferred into register R1.
a) R1 <- x
b) R1 <- R2
c) R2 <- R1
d) X <- x
Q.61) when an instruction is read from the memory, it is called
a) Memory Read cycle
b) Fetch cycle
c) Instruction cycle
d) Memory write cycle
Q.62) Which activity does not take place during execution cycle?
a) ALU performs the arithmetic & logical operation.
b) Effective address is calculated.
c) Next instruction is fetched.
d) Branch address is calculated & Branching conditions are checked.
Q.63) In every transfer, selection of register by bus is decided by:
a) Control signal
b) No signal
c) All signal
d) All of above
Q.64) Input to Control Unit are
a) IR
b) ALU flags
c) Clock
d) All of these
Q.65) While designing a Control unit, we have to consider various factors like
a) Amount of hardware used
b) the speed of operation
c) Cost of design
d) All of these
Q.66) The control signals for operation PC <- PC + 1 are,
a) PCout, ALUin, INC, Zout, PCin
b) PCout, ALUout, INC, Zout, PCin
c) PCin, ALUin, INC, Zout, PCin
d) PCout, ALUin, INC, Zin, PCin
Q.67) Which of the following registers is used to keep track of address of the memory location
where the next instruction is located?
a) Memory Address Register
b) Memory Data Register
c) Instruction Register
d) Program Register
Q.68) ….is not the transparent register present in single bus processor organization.
a) Y
b) R0
c) Z
d) Temp
a) Y
b) Temp
c) PC
d) Z
a) Y
b) Z
c) IR
d) Temp
a) Temp
b) MAR
c) Z
d) Y
a) MDR
b) Y
c) Z
d) Temp
Q.73) ….is the transparent register present in single bus processor organization.
a) Y
b) MAR
c) IR
d) MDR
Q.74) ….is the transparent registers present in single bus processor organization.
a) MAR
b) Z
c) IR
d) PC
Q.75) ….are the transparent registers present in single bus processor organization.
a) MDR
b) MAR
c) Temp
d) PC
a) PC & MAR
b) IR,MDR
c) Z & temp
d) PC & MDR
a) Y& Z
b) PC & MAR
c) IR,MDR
d) PC & MDR
a) PC & MAR
b) Y & temp
c) IR,MDR
d) PC & MDR
a) Y,Z & temp
b) PC & MAR
c) IR,MDR
d) PC & MDR
Q.80)
Q.81) Register transfer is controlled by ,
a) Riin
b) Riin and Riout
c) Riout
d) None of these
Q.82) Which of the following registers in single bus organization of processor are inaccessible to
programmer?
a) Y
b) Z
c) Temp
d) All of these
Q.83) In a single bus organization, …...data …….. can be transferred over the bus in a clock cycle.
a) Single, byte
b) Double, word
c) Single, word
d) Double, bit
Q.84) Data registers, ALU and interconnecting bus are referred to as,
a) Control Path
b) Processing Module
c) Data Path
d) Data Manipulator
Q.85) The control unit sends a control signal that opens gates between the
…….and the ……
a) MBR,IR
b) MDR,IR
c) PC,IR
d) MBR,PC
Q.86) Which is the correct sequence for Interrupt cycle?
a) t1:MBR <---(PC) t2:MAR<-- Save-address PC <-- Routine-address t3: Memory <--
(MBR)
b) t1:MAR <- (IR(Address)) t2:MBR <- Memory t3: IR(Address) <- (MBR(Address))
c) t1:MAR <- PC t2:MBR <- Memory t3: IR(Address) <- (MBR(Address))
d) None
Q.87) A control signal that opens the gates, allowing the contents of the data bus to be stored in the
……
a) MDR
b) MBR
c) IR
d) MAR
Q.88) All data transfer operations within the processor are,
a) Synchronous
b) Asynchronous
c) Symmetrical
d) Asymmetric
Q.89) In single bus organization, Which input of MUX gets operand directly form bus ?
a) A
b) B
c) Y
d) Either a or b
Q.90) In single bus organization, when fetch operation is performed, the requested data is received
from memory and it is stored into the,
a) MAR
b) MDR
c) Y
d) Z
Q.91) In single bus organization, to write a word of data into a memory location processor has to
load the address of the desired memory location in the,
a) MAR
b) MDR
c) Y
d) Z
Q.92) ……….. means the contents of memory location Y and register R1 are added and the result
is stored in memory location X.
a) R1 <- R2 + R1
b) X <- R1 + Y
c) R1 <- R2 – R1
d) X <- R1 – Y
Q.93) In state table method …operation is controlled by the control signal C0.
a) Clear A, Q -1 and count <- n
b) Decrement count
c) Shift right register A,Q, and Q -1
d) 2’s complement multiplicand
a) Transfer word on INBUS to B
b) Decrement count
a) Transfer word on INBUS to Q
b) Decrement count
c) Transfer word on INBUS to B
d) Shift right register A,Q, and Q -1
b) Shift right register A,Q, and Q -1
c) 2’s complement multiplicand
d) Transfer word on INBUS to Q
a) Shift right register A,Q, and Q -1
b) 2’s complement multiplicand
c) Transfer word on INBUS to Q
b) Decrement count
c) 2’s complement multiplicand
a) Decrement count
b) Transfer A to left input of adder
a) Transfer B to right input of adder
b) Transfer word on INBUS to Q
c) Transfer word on INBUS to B
a) Transfer Q to OUTBUS
b) Transfer adder output to A
c) Transfer A to OUTBUS
a) Transfer B to right input of adder
b) 2’s complement multiplicand
c) Transfer A to OUTBUS
d) Transfer Q to OUTBUS
a) Transfer Q to OUTBUS
b) Transfer A to OUTBUS
c) Transfer B to right input of adder
Q.104) ........... is implemented as a sequential circuit or a finite state machine that generates a
specific sequence of control signals to execute an instruction.
a) Micro programmed control unit
b) Hardwired control unit
c) Both a and b
d) None of these
Q.105) Hardwired control unit required the input from …….. to generate the control signals.
a) IR
b) IR and condition codes
c) IR and flag registers
d) IR, condition codes, flag registers, clock
Q.106) The information available in a state table may be represented graphically in a
a) simple diagram.
b) state diagram.
c) complex diagram.
d) data flow diagram.
Q.107) state table method is used to design_________
a) Hardwired Control Unit
b) Micro programmed Control Unit
c) both A & B
d) None
Q.108) _____is a type of microinstruction
a) Register transfer micro-operation
b) Arithmetic micro-operation
c) Logic micro-operation
d) All of these
Q.109) In micro programmed control unit, Hardware cost is more because of the control memory
& its access circuitry.
a) TRUE
b) FALSE
c) None of these
d) Both A & B
Q.110) A microinstruction has________
a) Control Field
b) Address Field
c) Both A & B
d) None of these
Q.111) Microprogramming is designing of
a) Control Unit
b) ALU
c) CPU
Q.112) Micro program is
a) The name of source program in micro computers
b) The set of instructions indicating the primitive operations in a system
c) Primitive form of macros used in assembly language programming
d) Program of very small size
Q.113) Microinstructions are stored in control memory groups, with each group specifying a
a) Subroutine
b) Routine
c) Vector
d) Address
Q.114) Control address register contains,
a) Address of next instruction
b) Next microinstruction
c) Address of next microinstruction
d) Address of current microinstruction
Q.115) Reading a microinstruction from memory is same as,
a) Executing a microinstruction
b) Sequencing a microinstruction
c) Reading from memory
d) Reading from control address register
Q.116) Microinstruction sequencing means
a) Get the next microinstruction from CBR
b) Get the next microinstruction for CAR
c) Get the next microinstruction from the control memory
d) All of these
Q.117) A micro programmed control unit is relatively simple logic circuit that is capable of,
a) Sequencing through microinstruction
b) Generating control signals to execute each microinstruction
c) Both a and b
d) None of these
Q.118) Which is midway between hardware and software ?
a) Middleware
b) Firmware
c) Micro program
d) Both b and c
Q.119) A micro programmed control unit consist of,
a) The control memory which stores the microinstructions.
b) Sequencing circuit that controls the generation of next address.
c) Decoders
d) All of these
Q.120) If the condition indicated by the condition bits is…... , execute the next microinstruction
a) TRUE
b) FALSE
c) none of these
d) both A & B
Q.121) If the condition indicated by the condition bits is ……., the next microinstruction to be
executed is indicated in the ……. field.
a) true, address
b) false, data
c) true, data
d) false, address
Q.122) The set of microinstructions
a) Instruction Register
b) control memory
c) sequencer
d) None of these
Q.123) The control address register contains the address of the next microinstruction to be …....
a) Read
b) Write
c) Fetch
d) None of these
Q.124) When a microinstruction is read from the control memory, it is transferred to a …….
a) IR
b) memory buffer register
c) control buffer register
d) None of these
Q.125) ……. a microinstruction from the control memory is the same as ……... that
microinstruction
a) Writing, executing
b) Reading, executing
c) Writing, fetching
d) Reading, fetching
Q.126) To execute an instruction, the sequencing logic unit issues a …….. command to the control
memory.
a) Write
b) READ
c) Both A and B
d) None of these
Q.127) The role of Microinstruction sequencing is ….…….
a) Get the next microinstruction from the control memory
b) Generate the control signals needed to execute the microinstruction.
c) fetch next microinstruction from the control memory
d) to store microinstruction to control memory
Q.128) A sequence of instructions is known as a ……..
a) Micro program
b) Microinstructions
c) Instruction code
d) None of these
Q.129) A micro program written as string of 0's and 1's is a
a) symbolic microinstruction
b) binary microinstruction
c) symbolic micro program
d) binary micro program
Q.130) Microinstructions are stored in control memory groups, with each group specifying a
a) Routine
b) Subroutine
c) Vector
d) Address
Q.131) Which microinstruction have higher encoding of control signals?
a) Horizontal Microinstruction
b) Vertical Microinstruction
c) Both a and b
d) Control instruction
Q.132) A micro program sequencer
a) generates the address of next micro instruction to be executed.
b) generates the control signals to execute a microinstruction.
c) sequentially averages all microinstructions in the control memory.
d) enables the efficient handling of a micro program subroutine.
Q.133) A micro program is sequencer that perform the…….. Operation.
a) Read
b) Read and write
c) Execute
d) read and execute
Q.134) In micro programming-
a) Horizontal micro instruction is faster
b) Vertical micro instruction is faster
c) h/w control unit is faster
d) None
Q.135) Control program memory can be reduced by
a) Horizontal format
b) Vertical format micro-program
c) Hardwired control unit
d) None
Q.136) The ………. method identifies functions within the machine and designates fields by
function type.
a) functional encoding
b) resource encoding
c) data encoding
d) None
Q.137) ……..views the machine as consisting of a set of independent resources and devotes one
field to each.
a) functional encoding
b) resource encoding
c) data encoding
d) None
Q.138) Speed of … control unit is low.
a) Hardwired
b) Micro programmed
c) both A & B
d) None
Q.139) Speed of … control unit is high.
a) Hardwired
b) Micro programmed
c) both A & B
d) None
Q.140) Cost of implementation of … control unit is more.
a) Hardwired
b) Micro programmed
c) both A & B
d) None
Q.141) Cost of implementation of … control unit is cheaper.
a) Hardwired
b) Micro programmed
c) both A & B
d) None
Q.142) Implementation approach of hardwired control unit is …...
a) sequential circuit
b) Programming
c) both A & B
d) None
Q.143) Implementation approach of micro programmed control unit is …...
a) sequential circuit
b) Programming
c) both A & B
d) None
Q.144) …..control unit is flexible.
a) Hardwired
b) Micro programmed
c) both A & B
d) None
Q.145) …..control unit is not flexible.
a) Hardwired
b) Micro programmed
c) both A & B
d) None
Q.146) ….control unit has complex decoding and sequencing logic.
a) Hardwired
b) Micro programmed
c) both A & B
d) None
Q.147) ….control unit has simple decoding and sequencing logic.
a) Hardwired
b) Micro programmed
c) both A & B
d) None
Q.148) …… is the application of hardwired control unit.
a) RISC
b) CISC
c) both A & B
d) None
Q.149) …… is the application of micro programmed control unit.
a) RISC
b) CISC
c) both A & B
d) None
Q.150) Control memory is present in………..control unit.
a) Hardwired
b) Micro programmed
c) both A & B
d) None
Q.151) Control memory is not present in………..control unit.
a) Hardwired
b) Micro programmed
c) both A & B
d) None
Q.152) Chip area required is less in….. Control unit.
a) Hardwired
b) Micro programmed
c) both A & B
d) None
Q.153) Chip area required is more in….. Control unit.
a) Hardwired
b) Micro programmed
c) both A & B
d) None
Q.154) Direct Encoding is….. Kind of microinstruction.
a) Horizontal
b) Vertical
c) both A & B
d) None
Q.155) Indirect Encoding is….. Kind of microinstruction.
a) Vertical
b) Horizontal
c) both A & B
d) None
Q.156) …..is kind of a microinstruction encoding needs multilevel decoder.
a) Horizontal
b) Vertical
c) both A & B
d) None
Q.157) …..is kind of a microinstruction encoding which does not need multilevel decoder.
a) Horizontal
b) Vertical
c) both A & B
d) None
Q.158) Packed encoding is….. Kind of microinstruction.
a) Vertical
b) Horizontal
c) both A & B
d) None
Q.159) Unpacked encoding is….. Kind of microinstruction.
a) Vertical
b) Horizontal
c) both A & B
d) None
Q.160) Hard encoding is….. Kind of microinstruction.
a) Vertical
b) Horizontal
c) both A & B
d) None
Q.161) Soft encoding is….. Kind of microinstruction.
a) Vertical
b) Horizontal
c) both A & B
d) None
Q.162) Hard microinstruction issued by ….microinstruction.
a) Vertical
b) Horizontal
c) both A & B
d) None
Q.163) Soft microinstruction issued by ….microinstruction.
a) Vertical
b) Horizontal
c) both A & B
d) None
UNIT I
Decimal signed number +10 in 2's complement notation
represented as ------------------ Decimal signed number -10 in 2's
Question Question complement notation represented as
------------------
11010
A A 11010
10110
B B 10110
10101
C C 10101
D 1010 D 1010
Answer D Answer B
Which one of the following signed number

Question Which one of the following signed number representation Question representation is preferred in signed
has unique representation for +0 &-0 ? arithmetics ?
A sign magnitude method A sign magnitude method
B 1's complement method B 1's complement method
C 2's complement method C 2's complement method
D none of this D none of this
Answer C Answer C
Question Question In which generation of computers history, the

What is the size of memory word in the first IAS computer? magnetic core memory was introduced ?
A 32 bits A Second generation
B 64 bits B Third generation
C 40 bits C Fourth generation
D 16 bits D Beyond fourth generation
Answer C Answer A
Question In IAS Computer ,which register is used to hold temporarily Question In IAS Computer the total number of
the fetched instruction from memory ? instructions are,
A IR A 42
B MBR B 110
C IBR C 21
D MAR D 16
Answer C Answer C
Question Question which of the following is NOT a computer

The basic system bus consists of ------------------- performance metric ?
A high speed bus &control bus A MIPS
B expansion bus B FLOPS
C address &data bus C RISC
D address, data &control bus D SPEC mark
Answer D Answer C
Question Question The Von Neumann Bottleneck is due to which

IBM PC's were originally based on which processor family ? of the following reasons ?
A A Mismatch in speed between secondary

Motorola 68000 family &Primary storage
B B Mismatch in speed between CPU &Primary

Intel 80x86 family storage
C Power PC family C Slow speed of I/O device
D none of these D low clock speed
Answer B Answer B
Question Question which register keeps track of instructions
IBM PC's were originally based on which processor family ? stored in memory?
A Motorola 68000 family A MAR
B Intel 80x86 family B IR
C Power PC family C Accumulator
D none of these D PC
Answer B Answer D
Question The instruction register IR stores what?

Question The read/write lines belong to which bus?
A instruction after decoding A data bus
B fetched instruction B control bus
C instruction address of next to be executed C bus address bus
D none of these D none of these
Answer B Answer B
Question Question The communication line between CPU

von Neumann architecture is of what type ? ,memory &peripherals is called
A SISD A Bus
B SIMD B interface
C MIMD C Media
D MISD D none of these
Answer A Answer A
Question Question Execution of two or more programs by a

what is the control unit's function in the CPU? single CPU is known as
A to transfer data to primary storage A Multiprocessing
B to store program instruction B time sharing
C to perform logic operation C Multiprogramming
D to generate control signals D none of these
Answer D Answer C
Question The language that the computer can understand &execute is Question
called Third generation of computers
A machine language A were first to use IC instead of transistors
B Application s/w B used transistors to replace vacuum tubes
C System S/W
C these were first to use artificial intelligence
D none of above D none of these
Answer A Answer A
Question The term 'baud' is a measure of Question A bootstrap is

A speed at which data travels over communication line A a memory device
B Memory capacity B a device to support computer
a small initialization program to start up
C instruction execution time C computer
D All of above D error detection technique
Answer A Answer C
Question Question which of the following register holds address

Which of the following is not hardware? of word in memory?
A Magnetic tape A MAR
B Printer B MDR
C VDU terminal C MBR
D Assembler D MVB
Answer D Answer A
Question Question
Mnemonics are used in which language Von Neumann architecture is also known as
A high level A HarVard architecture
B Assembly B Modern architecture
C machine C Princeton architecture
Answer B Answer C
Question which was the world's first general purpose electric digital Question ENIAC machine used which type of number
computer system ?
A IAS A Binary
B ENIAC B Hexadecimal
C VAX C Decimal
D RISC D Octal
Answer B Answer C
Question Which of following is the prototype of all general purpose Question

computers? Which registers are present in IAS computer?
A EDVAC A IP,CS
B ENIAC B DS,SI
C IAS C MAR,PC
D none of these D AX,BX
Answer C Answer C
Question Question The memory of IAS computer consist of how

What was the drawback of ENIAC ? many storage location/Words?
A Complex number system A 200
B less memory B 1500
C Tedious program entry &alteration difficult C 1000
D none of these D 2000
Answer C Answer C
Question From which generation of computer , the use of high level Question Von Neumann in 1946 designed new
language started? computer based on
A First A machine language concept
B Second B Assembly language concept
C Third C stored program concept
D Fourth D high level language concept
Answer B Answer C
Question What is Harvard architecture? Question What is Harvard architecture?

physically one storage for both instructions &data
A A Single storage for program &data
B B
physically one set of buses for instructions &data Seaparate storage for program &data
C physically separate storage &signal path ways for C

instructions &data Both A &B
Answer C Answer B
Question Control signals transmit which information between system Question

modules ? In Harvard architecture
A status information A CPU can read or write only data from memory a
B Command information B CPU can read only instruction from memory at a time
CPU can perform read/write data operation
C C &also reading instruction from memory
timing information concurrently
D both B &C D none of these
Answer D Answer C
What is the Specialty of high performance
Question Which signal indicates that system modules needs to access Question bus architecture over traditional bus
bus? architecture?
A Acknowledge A Expansion bus
B Bus grant B local bus
C Bus request C high speed bus
Answer C Answer C
Question Which signal causes the data from the addressed location to Question What is the impact if the width of data bus is
be placed on the bus? increased?
A Interrupt request A reduced speed of data transfer
B I/O write B Greater no of bits transferred at one time
C C Greater range of memory location

Memory Read referenced
D Memory write D none of these
Answer C Answer B
Question Question What is the impact of increasing address bus

Which signal is used to synchronize operations? width?
A Bus request A Speedy data transfer
B reset B large no of data transfer
C clock C increased addressing capacity
D none of these D decreased addressing capacity
Answer C Answer C
Question What will be the effect of connecting large no of devices to Question Memory-delay-line memory was used in
system bus? which computer generation?
A Performance will increase A First
B efficiency will increase B second
C System will be more economical C Third
D propagation delay will increase D Fourth
Answer D Answer A
Which architecture allows simultaneous

Question Question &independent instruction fetching from
Which is key feature of computers beyond fourth memory &load/store operation with
generation? memory?
A cache memories A von Neumann architecture
B Virtual memories B Harvard architecture
C Distributed system C RISC architecture
Answer C Answer B
Question Question Bit pair recording technique speeds up the

Which multiplication method speeds up the multiplication? multiplication for n-bit operands due to
A sequential bit binary multiplication A n summands
B Booth's algorithm B n/2 summands
C Bit pair recording C n/4 summands
Answer C Answer B
Question In restoring division algorithm ,when it is required to do Question In restoring division algorithm ,during
restore operation? restoring operation the quotient q0 is set to
A before subtraction A 0
B after subtraction B 1
C after unsuccessful subtraction C Previous status
D none of these D Inverted
Answer C Answer A
Question what is the advantage of non-restoring division algorithm?
Question What is long form of ENIAC?
Electronic Numerical Integrator and

A only two operation (add &Subtract) per cycle A
Computer
Electronic Numerical Integer and
B
only one operation (add) per cycle
B Compiler
Electronic Number Integrator and
C only one operation (add/subtract) per cycle
C Compiler
Electrical Number Integrator and
D none of these
D Computer
Answer C Answer A
Which kind of architecture is used in

Question What is long form of EDVAC?
Question EDVAC?
A Electrical Discrete Variable Computer A Harvard
B Electronic Difference Variable Compiler B Von Neumann
C Electrical Discrete Variable Compiler C Both of these
D Electronic Discrete Variable Computer D None of these
Answer D Answer B
Question Which basic components are used in ENIAC?

Question How many accumulators are used in ENIAC?
A Vacuum tubes A 10
B Transistor B 20
C Integrated Circuit C 30
D Gates D 40
Answer A Answer B
Which kind of number system is used by

Question What is the long form of IAS?
Question IAS?
A Institute of Advance Studies A Decimal
B Integration of Accumulator Storage B Binary
C Integration of Advance Storage C Hex
D Institute of Accumulator Studies D Octal
Answer A Answer B
In n-bit Booth's multiplication algorithm,

Question Question the largest number of operations
What is the size of IAS instructions? are------------------
A 30 bits A additions and log2n subtractions
B 20 bits B log2n additions and log2n subtractions
C 10 bits C (n-1) additions and (n-1) subtractions
D 5 bits D None of the above
Answer B Answer D
Performance of a pipelined processor suffers

Question The performance of a computer ______________ Question if
A Depends on disk and memory access time A The pipeline stages have different delays
Consecutive instructions are dependent on

B
B Does not depend on compiler each other
C Both A and B C The pipeline stages share hardware resources
D None of the above D All of these

Answer A Answer D
The concept of pipelining is most effective in improving

Question performance if the tasks being performed in different stages Question Native MIPS has MIPS measurement of
A Require different amount of time A MIPS = Instruction count/(Execution time)10^

B Require about the same amount of time B MIPS = Instruction count/(Execution time
Require different amount of time with time difference
C between any two tasks being same C MIPS = Instruction count/Execution time
Require different amount with time difference between
D any two tasks being different D MIPS = (Execution time)10^6
Answer B Answer A
Valid and unimpeachable measurement of performance

Question of any computer is Question Total amount of work done during execution,
in a given time is referred to as
A Clock rate A Response time
B Instruction set B Execution time
C Execution time C Through put
D Delay time D Delay time
Answer C Answer C
Question Performance X = 1/ Execution Time x given relation Question The clock rate of the processor can be
shows that improved by,
Improving the IC technology of the logic
A Performance is increased when execution time is decreas A
circuits
Reducing the amount of processing done
B B
Performance is increased when execution time is increas in one step
Performance is decreased when execution time is
C decreased C By using overclocking method
D None D All of the above
Answer C Answer D
For a given FINITE number of instructions to be

Question Question A processor performing fetch or decoding of
executed, which architecture of the processor provides different instruction during the execution of
faster execution? another instruction is called ______ .
A ISA A Super-scaling
B ANSA B Pipe-lining
C Super-scalar C Parallel Computation
D All of the above D None of these
Answer C Answer B
MFLOPS Rate = ( Number of executed

Question During the execution of the instructions, a copy of the Question floating point operations in a program)/
instructions is placed in the ______ . (_________* 106)
A Register A Execution Time
B RAM B Floating Time
C System heap C Elapsed time
D Cache D None of the above
Answer D Answer A
Operation performed by a processor, such as fetching an

Question instruction, decoding the instruction, performing an Question MFLOPS Rate = ( Number of executed
arithmetic operation, and so on, are governed by a System floating point operations in a program)/
__________ (_________* 106)
A Program A Execution Time
B Speed B Floating Time
C Clock C Elapsed time
D Address D None of the above
Answer C Answer A
Operation performed by a processor, such as fetching an

Question instruction, decoding the instruction, performing an Question __________ is useful in comparing two
arithmetic operation, and so on, are governed by a System processors w.r.t. speed in execution of
__________ floating point operations.
A Program A MFLOPS
B Speed B MIPS
C Clock C CPI
D Address D Throughput rate
Answer C Answer A
Question ________________ law states that the speed up to be Question
gained from using some faster mode of execution is limited
by the fraction of time the faster mode can be used. MIPS rate varies w.r.t a _______________
A Moore’s law A Clock Rate (f)
B Amdahl’s law B Instruction Count(Ic)
C Flynn’s law C CPI
D None of the above D All of the above
Answer B Answer D
_____________________ becomes an important parameter

Question for measuring the time needed to execute a program on a Question The size of the program is given in terms of
given machine. ______________.
A CPI A Instruction Count (Ic)
B IC B Machine Count
C Clock Rate C Clock rate
D MIPS D CPI
Answer A Answer A
Question Question Machine capability can be enhanced

A program can be made efficient: _____________________ with:______________
A With better algorithm A Better Hardware Technology
B With better data structure and language efficiency B Innovative architectural features
C Compiler technology C Efficient resource management
D All of the above D All of the above
Answer D Answer D
Performance of a program is affected by the way in which

Question the ____________ translates high level programs in to Question The three main parts of a stored program
machine code. computer are______,_____, and ______.
A Complier A CPU, memory , I/O
B Assembler B Register, Memory, Control Unit
C Linker C CPU,Register, ALU
D Debugger D CPU, I/O, Control Unit
Answer A Answer A
Question Which of the following is/are characteristics of a benchmark Question

program-------------- MFLOPS deals with------------------------
A It is written in a high-level language A Only floating-point instructions
It is representative of a particular kind of programming
B B
style Only integer instructions
C It can be measured easily C Both A and B
D All of the Above D None of these
Answer D Answer A
Which of the following instructions move

Question The basic elements of a digital computer must Question data between memory and ALU registers or
perform--------------- between two ALU registers?
Unconditional branch instructions
A Storage A
B Movement B Arithmetic instructions
C Processing C Address modify instructions
D All of The Above D Data transfer instructions
Answer D Answer D
Which of the following approach will achieve increased In ENIAC programming was done
Question processor speed? Question by-----------------
A Increase the hardware speed of the processor. A Manually
B Increase the size and speed of caches. B Automatically
C Make changes to the processor organization. C By setting switches
D All of the above D Both A and C
Answer D Answer D
While using Booth's Algorithm-------------- The evolution of computers has been
Question Question characterized by---------------
You will need twice as many bits in your product as you
A A Increasing processor speed
have in your original two operands.
You will need same bits in your product as you have in
B B
your original two operands. Decreasing component size
You will need half bits in your product as you have in your Increasing memory size
C original two operands. C
D None of the Above D Increasing I/O capacity and speed
Answer A E All of the Above
Answer E
The law stating that the maximum speedup of a parallel

What is usually regarded as the von
Question program is limited by the sequential fraction of the Question
Neumann Bottleneck?
initial sequential program is called
A Amdahls Law A Processor/memory interface
B Flynns Law B Control unit
C Moores Law C Arithmetic logical unit
D Van Neumanns Law D Instruction set
Answer A Answer A
Who is regarded as the founder of Computer

Question Question Von Neumann architecture is-----------------
Architecture?
A Alan Turing A SISD
B Konrad Zuse B SIMD
C John von Neumann C MIMD
D John William Mauchly D MISD
Answer C Answer A
In computers, subtraction is carried out generally Booth algorithm gives procedure for
Question Question
by------------- multiplying binary integers in-------
A 1's complement method A Signed magnitude representation
B 2's complement method B Unsigned representation
C Signed magnitude method C 2's complement representation
D BCD subtraction method D None of the above
Answer B Answer C
As of 2000, the reference system to find

Question Question the SPEC rating are built with -----------
Which one of the following is a multiplication algorithm? Processor
A Comparison method A Intel Atom SParc 300Mhz
B Restoring method B Ultra SPARC -IIi 300MHZ
C Quick sort algorithm C Amd Neutrino series
D Booth's algorithm D ASUS A series 450 Mhz
Answer D Answer B
During the execution of the instructions, a

The average number of steps taken to execute the set of
instructions can be made to be less than one by following Question copy of the instructions is placed in the
Question ---------------- -------------------
A ISA A Register
B Pipe-lining B RAM
C Super-scaling C System heap
D Sequential D Cache
Answer C Answer D
In Non-Restoring algorithms for division,

if number of bits in Q register is 4, then
Question Question
As of 2000, the reference system to find the how many number of cycles need to be
performance of a system is----------------- performed to get result?
A Ultra SPARC 10 A 4
B SUN SPARC B 3
C SUN II C 2
D None of these D 1
Answer A Answer A

Question Question if current value of A is negative i.e.
SPEC stands for----------------- (A<=0), then set Q0 =......?
A Standard Performance Evaluation Code. A 1
B System Processing Enhancing Code. B 0
C System Performance Evaluation Corporation. C Both A and B
D Standard Processing Enhancement Corporation. D None of these
Answer C Answer B

Question Question if current value of A is nonnegative i.e.
The clock rate of the processor can be improved by-------- (A>=0), then set Q0 =......?
A Improving the IC technology of the logic circuits A 1
B Reducing the amount of processing done in one step B 0
C By using overclocking method C Both A and B
Answer D Answer A

if previous value of A register is negative
Question For a given FINITE number of instructions to be Question i.e. (A<=0), then which of following
executed, which architecture of the processor provides operation need to be performed?
for a faster execution ?
A ISA A A<---A-M
B ANSA B A<---A+M
C Super-scalar C A<---M-A
D All of the above D A<---M+A
Answer C Answer B
if previous value of A register is
Question A processor performing fetch or decoding of different Question nonnegative i.e. (A>=0), then which of
following operations need to be
instruction during the execution of another instruction is performed?
called--------------
A Super-scaling A A<---A-M
B Pipe-lining B A<---A+M
C Parallel Computation C A<---M-A
D None of these D A<---M+A
Answer B Answer A

Question Question how divident value can be expressed?
In Non-Restoring algorithms for division, value of A (Where n is size of divisor)
and Q register are shifted towards ......... by 1 bit.
A Right A In the form n
B Left B In the form 2n
C Both A and B C In the form 3n
D None of these D In the form n/2
Answer B Answer B
After performing Non-Restoring

Question After performing Non-Restoring algorithms for Question algorithms for division, in which register
division, in which register value of quotient is returned? value of remainder is returned?
A In Q register A In Q register
B In M register B In M register
C In A register C In A register
D None of these D None of these
Answer A Answer C
Question In Non-Restoring algorithms for division, in which Question in which register two's complement of
register the value of dividend is stored? divisor bit is loaded?
A In M register A In M register
B In Q register B In Q register
C In A register C In A register
Answer B Answer A
In Restoring algorithms for division, if

result of (A<--A-M) operation is negative
Question In Restoring algorithm for division, if number of bits in Question i.e. (Most significant bit of A=1), then set
Q0 =..... ? And restore previous value of A
Q register is 4, then how many number of cycles need to .
be performed to get result?
A 1 A 0
B 2 B 1
C 3 C 1
D 4 D 10
Answer D Answer A
In Restoring algorithms for division, if result of (A<-- In Restoring algorithms for division,
Question A-M) operation is nonnegative i.e. (Most significant bit Question which of following option is important
of A=0), then set Q0 =..... ? And do not restore previous step?
value of A.
A 0 A A<---A-M
B 1 B A<---M-A
C 1 C A<---Q-M
D 10 D A<---A-Q
Answer B Answer A
In Restoring algorithms for division, how
Question In Restoring algorithms for division, value of A and Q Question divident value can be expressed?
register are shifted towards ......... by 1 bit. (Where n is size of divisor)
A Right A In the form n
B Left B In the form 2n
C Both A and B C In the form 3n
D None of these D In the form n/2
Answer B Answer B
In Booths algorithms for multiplication, if

least significant bit value of Q register i.e.
Question Question Q0 and Q-1 bits are 10, then which of
After performing Restoring algorithms for division, in following option is correct?
which register value of quotient is returned?
A In Q register A Addition and then Arithmetic Shift Right
B In M register B Only Arithmetic Shift Right
Subtraction and then Arithmetic Shift
C In A register C Right
Answer A Answer C
In Booths algorithms for multiplication, if

least significant bit value of Q register i.e.
Question Question Q0 and Q-1 bits are 11 and 00, then
After performing Restoring algorithms for division, in which of following option is correct?
which register value of remainder is returned?
In Q register Addition/Subtraction and then Arithmetic
A A
Shift Right
B In M register B Only Arithmetic Shift Right
C In A register C Both A and B
Answer C Answer B
In Booths algorithms for multiplication,
there is 1-bit register placed logically to
Question Question the right of the least significant bit of Q
In Restoring algorithms for division, in which register register and designated as ...........
the value of dividend is stored?
A In Q register A Q register
B In M register B M register
C In A register C Q-1 register
D None of these D A register
Answer A Answer C
In Booths algorithms for multiplication, if number of In Booths algorithms for multiplication,

Question multiplicand bits are 4, how many number of cycles Question What is initial content of Q-1 register?
need to be performed?
A 3 A Multiplier
B 4 B Multiplicand
C 5 C 0
D 2 D None of these
Answer B Answer C
In Booths algorithms for multiplication, if least In Booths algorithms for multiplication,

Question significant bit value of Q register i.e. Q0 and Q-1 bits Question
What is content of M register?
are 01, then which of following option is correct?
A Addition and then Arithmetic Shift Right A Multiplier
B Only Arithmetic Shift Right B Multiplicand
C Subtraction and then Arithmetic Shift Right C 0
Answer A Answer B
Which basic components are used in first
Question Question
Which is the first generation computer? generation computers?
A IAS A Vacuum tubes
B BM 7094 B Transistor
C DEC PDP C Integrated Circuit
D 8086 D Gates
Answer A Answer A
Which basic components are used in second generation Fourth generation computers came up
Question Question
computers? with concept of ------
A Vacuum tubes A VLSI
B Transistor B MSI
C Integrated Circuit C IC
D Gates D Parallel computing
Answer B Answer A
Which basic components are used in third generation In IAS computer, ------------ interprets
Question Question
computers? instructions from memory
A Vacuum tubes A Input unit
B Transistor B ALU
C Integrated Circuit C Control unit
D Gates D Accumulator
Answer C Answer C
In IAS computer, instruction and data

Question Which is first microprocessor developed by Intel? Question
were stored in------------memory
A 8008 A separate
B 8080 B distinct
C 4004 C same
D 4040 D large
Answer C Answer C
In IAS computer AC, MQ, MBR are the
Question Which representation gives two forms of zero? Question
part of----------------unit.
A Sign Magnitussigned magnitude representation A Input unit
B 1’s compleme 2’s complement representation B ALU
C 2’s compleme Both A &B C Control unit
D 9’s compleme None of these D Memory
Answer A Answer B
What is the result of performing arithmetic right shift In IAS computer IR, PC, MAR, IBR are
Question operation on the given number 11001011.
Question
the part of----------------unit.
A 11100101 A Input unit
B 1100101 B ALU
C 10010110 C Control unit
D 11100100 D Memory
Answer A Answer C
During execution of an instruction, an

Question third generation computers supported ______________ Question
operand can be stored in--------
A Microprogramming A IR
B Parallel processing B PC
C Resource sharing C MAR
D All above D MBR
Answer D Answer D
Register(s) used for temporary storage of

Question MDR is also known as------------- Question
operands and result, ----------
A Data Register A AC
B Address register B MQ
C Bus register C AC and MQ
D None D DR
Answer A Answer C
--------------------stores an op-code of the

--------------------stores an op-code of first instruction in instruction that is not to be executed
Question sequence when two instructions are fetched simultaneously Question immediately, when two instructions are
by program control unit. fetched simultaneously by program
control unit
A IR A IR
B IBR B IBR
C PC C PC
D MAR D MAR
Answer A Answer B
Von Neumann machines fetch ---------

Question Harvard architecture is used by------------ processor. Question
instruction(s) simultaneously.
A RISC A 1
B CISC B 2
C RISC and CISC C 3
D none D 4
Answer A Answer A
A bit pair recoding technique used in

Advantage of Harvard Architecture over Von Neumann,
Question -------------------.
Question Booth’s algorithm _________ the
multiplication process.
A greater flexibility in developing software A Speeds up
B more parallelism B Slows-down
C reliability C Stops
D all of above D None of these
Answer B
The representation of -12 in 2’s
Question The representation of +12 in 2’s complement form is----------- Question
complement form is-----------
A 1100 A 10001100
B 11111100 B 11110100
C 11110100 C 11110011
D 10001100 D 10001100
Answer A Answer B
In restoring division algorithm, if the

In case of unsigned method of multiplication , the register A
Question should be initialized with ------
Question result of subtraction is _____ then it needs
restoring of register A.
A Multiplier A Positive
B zero B Negative
C Multiplicand C Zero
D None of the above D None of these
Answer B Answer B
Which of following option is valid

Non-restoring division algorithm needs restoring of
Question remainder if remainder is ___
Question advantages of Booths Multiplication over
sequential multiplication?
To increase number of additions in partial
A Positive
A
product
To decrease number of additions in partial
B Negative B product
To provide same number of additions in
C Both A and B C partial product
Answer B Answer B
In Booths algorithms for multiplication, in

Which of following option is valid advantages of Booths
Question multiplication over sequential multiplication?
Question which register the value of multiplicand is
stored?
A It is works for 2's complement number. A In Q register
B It is not works for 2's complement number. B In M register
It is neither works for 2's complement number nor signed
C number C In A register

Answer A Answer B
In Booths algorithms for multiplication, in which In Booths algorithms for multiplication,

Question
Question register the value of multiplier is stored? What is initial content of A register?
A In Q register A Multiplier Value
B In M register B Multiplicand value
C In A register C 0
Answer A Answer C
In Booths algorithms for multiplication, What is content of Q In Booths algorithms for multiplication, What
Question register?
Question is content of M register?
A Multiplier A Multiplier
B Multiplicand B Multiplicand
C 0 C 0
Answer A Answer B
UNIT II
The code that indicates the operation to be performed is ______ addressing mode is used for the
Question
called as ___________. Question addressing local variables.
A Opcode A Immediate
B Operand B Direct
C Instruction C Register
D Program D Indexed
Correct Answer A Correct Answer C
_____ addressing mode is used for the accessing array MOV R0,300 is an example of _______
Question variables. Question addressing mode.
A Immediate A Immediate
B Direct B Direct
C Register C Register Indirect
D Indexed D Indexed
Correct Answer D Correct Answer A
The instructions that are used to move the data among ______ addressing mode is used for
Question CPU registers are in the group of ______________. Question Global variables.
A Data Transfer A Immediate
B Arithmetic and Logical B Direct
C Control Transfer C Register
D Miscellaneous D Indexed
Correct Answer A Correct Answer B
ADD is _____ address instruction. The instruction is made up of

Question Question ___________.
A 0 A Programs
B 1 B Subroutines
C 2 C Opcode and Operands
D 3 D None of the above
The ________ Flag is Set when there is a carry out of ____ addressing mode is used for holding
Question the lowest nibble of the result. Question accessing arrays through pointers.
A Carry A Immediate
B Auxiliary B Direct
C Overflow C Register Indirect
D Sign D Indexed
Correct Answer B Correct Answer C
Machine instructions are in the form of ______ A particular sequence of binary codes
Question Question used to perform particular task is known
as ______
A Binary Codes A Machine Language Program
B BCD Codes B Assembly Language Program
C Excess 3 Codes C
D Gray Codes D High level Language Program
Correct Answer A Correct Answer All of the above
A
Most of the times the result is stored in the ______ _________ receives code & data from
Question operand. Question ________ & executes the same
A Source A BIU, EU
B Destination B EU,BIU
C Both A and B C BIU,BIU
D None of the above D EU,EU
Correct Answer B Correct Answer A
_________ receives & sends data through ___________ What is Pipelining ?

Question Question
BIU, EU The process of inserting the instruction in
A A a pipe
EU,BIU The process of fetching the next
B B instruction when the present instruction is
being Executed
C BIU,BIU C The process of laying down the pipe
D EU,EU D All Of these
____ addressing mode is used for the PUSH and POP In what condition will Execution Unit
Question instructions. Question enter into wait state?
Auto Index Instruction to be executed is not in the
A A Queue.
Direct Instruction being executed is a control
B B transfer instruction
Register Indirect BIU can suspend fetching instruction
C C during execution of slow executing
instructions
D Indexed D All of the above
Correct Answer A Correct Answer
D
The main function of the ___________ is execution of ______ instruction copies the contents of
Question an instruction. Question memory location A in to Accumulator.
A BIU A STORE A
B EU B LOAD A
C ALU C MOV A
D FPU D None of these
Correct Answer B Correct Answer B
In MOV A,B instruction, the ___ register is a Source

operand and ____ register is a destination operand. The program statements used in the
Question Question
______ are converted in to machine codes
with the help of interpreter or complier.
A A, B A Machine Language Program
B B, A B Assembly Language Program
C A,A C High level Language Program
D B,B D All of the above
____ extra fetch cycles are required for Register Factor to be considered while deciding the
Question addressing mode. Question instruction length _____
A 0 A Memory size
B 0.5 B Memory organization
C 1 C Data bus size
D 2 D All of the above
Correct Answer A Correct Answer D
Question MOV R0, [R1+5] is an example of ___ Question MOV R0, R1 is an example of _____
A Immediate A Immediate
B Direct B Direct
C Register C Register
D Indexed D Indexed
Correct Answer D Correct Answer C
The ______ is an another name for data. The __ Flag copies the MSB of the result.
Question Question
A Opcode A Carry
B Source B Auxiliary
C Operand C Overflow
D Destination D Sign
Correct Answer C Correct Answer D
_______ addressing mode is used for the initialization The Numeric data types _________
Question of the variables. Question
A Immediate A Integer or Fixed point
B Direct B Point
C Register C Decimal
D Indexed D All of the above
MOV R0,[R1] is an example of _____ addressing mode. ADD X, Y is _____ address instruction.
Question Question
A Immediate A 0
B Direct B 1
C Register Indirect C 2
D Indexed D 3
Correct Answer C Correct Answer C
ADD X,Y,Z is _____ address instruction. The Operand may appear in the form of
Question Question ____________
A 0 A Address
B 1 B Numbers
C 2 C Characters and Logical data
Correct Answer D Correct Answer D
_______ instruction copies the contents of accumulator In LOAD A instruction the operand
Question in to memory location B. Question specified in the instruction is a _______
operand.
A STORE A A Destination
B LOAD A B Source
C MOV A C Source and Destination
In STORE B instruction the operand specified in the A variable length instruction based
Question instruction is a _______ operand. Question machine provides ______.
A Destination A Flexibility in addressing scheme
Source Large number of operations which have
B B different length of instructions
C Source and Destination C Both A and B
D None of these D None of the above
MOV R0, [300] is an example of _____ addressing Most of the computers use _______ code
Question mode. Question for characters represented by unique 7 bit
pattern.
A Immediate A Binary
B Direct B BCD
C Register Indirect C ASCII
D Indexed D Machine
There are so many addressing modes in the processor Operation Source1, Source 2, Destination
Question because of ______ Question is the general instruction format for ____
address instruction.
A Time and Space efficiency A 0
B Programming Flexibility B 1
C Economy C 2
D All of the above D 3
MOV R0, [R1]+ is an example of _____ In ____ address instructions, the locations
Question Question of all operands are defined implicitly.
A Immediate A 0
B Auto Increment B 1
C Register C 2
D Indexed D 3
Operation Source, Destination is the general instruction _________ instruction type includes Test
Question format for ____ address instruction. Question and Branch instructions.
A 0 A Logical
B 1 B Arithmetic
C 2 C Control
D 3 D Data Movement
How many extra fetch cycles are required for Direct How many extra fetch cycles are required
Question addressing mode? Question for Immediate addressing mode?
A 0 A 0
B 0.5 B 0.5
C 1 C 1
D 1.5 D 1.5
Correct Answer C Correct Answer A
_____ address instructions are found in machines that The instructions that are used to perform
Question store operands in a structure called a push down stack. Question operations like Call, Return are in the
group of
A 0 A Data Transfer
B 1 B Arithmetic and Logical
C 2 C Control Transfer
D 3 D Miscellaneous
Operation Source is the general instruction format for _________ instructions are the superset of
Question ____ address instruction. Question data storage instructions.
A 0 A Logical
B 1 B Arithmetic
C 2 C Control
D 3 D Data Movement
Correct Answer B Correct Answer D
____________ states that the contents of memory ADD X is _____ address instruction.
Question location LOC are transferred in to the processor register Question
R2.
A R2ß LOC A 0
B R2ß [LOC] B 1
C R2à LOC C 2
D R2à [LOC] D 3
How many extra fetch cycles are required for Register How many extra fetch cycles are required
Question addressing mode? Question for Indexed addressing mode?
A 0 A 0
B 0.5 B 0.5
C 1 C 1
D 1.5 D 1.5
The control unit provides signals that control the All the other elements of the computer
operation of the _____ and movement of data in to and system- control unit, registers, memory,
Question out of the ALU. Question I/O – are the main to bring data in to the
______for it to process and then to take
the result back out.
A FPU A FPU
B BIU B BIU
C EU C EU
D ALU D ALU
How many address instruction is MULT ? How many address instruction is MULT B
Question Question ?
A 0 A 0
B 1 B 1
C 2 C 2
D 3 D 3
The instructions that are used to perform branch _______ states that the contents of
Question operations are in the group of _____ Question processor register R2 are transferred in to
processor register R3.
A Data Transfer A R3ß R2
B Arithmetic and Logical B R3ß[R2]
C Control Transfer C R3à R2
D Miscellaneous D R3 à[R2]
Correct Answer C Correct Answer B
Pentium instruction format consists of ______ fields. A machine instruction has a number of
Question Question elements: _______
A 3 A Opcode
B 4 B References to the operands
5 A reference to the next instruction to be
C C executed
To have a less execution time we have to use ________ instruction is used to test the
Question instructions with _____ memory accesses. Question value of a data word or the status of a
computation.
A Maximum A Test
B Minimum B Arithmetic
C More C Control
D New D Data Movement
Question How many address instruction is STORE T ? Question The operation is to be performed on __
A 0 A Opcode
B 1 B Operand
C 2 C Instruction
D 3 D Program
_____ addressing mode is used for global addressing How many address instruction is MULT
Question mode. Question A,B ?
A Immediate A 0
B Direct B 1
C Register C 2
D Indexed D 3
How many extra fetch cycles are required for Register How many address instruction is LOAD
Question Indirect addressing mode? Question C?
A 0 A 0
B 0.5 B 1
C 1 C 2
D 1.5 D 3
The contents of register or memory location are denoted How many address instruction is MULT
Question by placing ______ brackets around the name of the Question C?
register or memory location.
A Curly A 0
B Square B 1
C Triangular C 2
D None of the above D 3
The logical address is converted into physical address How many address instruction is MULT ?
Question By _______ Question
A BIU A 0
B EU B 1
C Both A and B C 2
D None D 3
Correct Answer A Correct Answer A
How many extra fetch cycles are required for Auto The transfer of data between processor &
Question Index addressing mode? Question outside world is done by __________
A 0 A BIU
B 0.5 B EU
C 1 C Both A and B
D 1.5 D None
The _________ performs generation of Memory & I/O In what conditions will the execution unit
Question Address Question enter in to Wait state?
A Bus Interface Unit A 0
B Execution Unit B 1
C Both of These C 2
D None D 3
How many address instruction is STORE D ? Source and Result Operands can be in
Question Question areas: ________________
A 0 A Main /Virtual Memory or I/O Device
B 1 B Processor Register
C 2 C Immediate
If memory accesses are ____ then more time is required The instruction MOV R0, [R1+5] is an
Question to execute the instruction. Question example of ________ addressing mode.
A Less A Immediate
B More B Direct
C Few C Register
D None of the above D Indexed
How many address instruction is MULT A,B ? The ______ is that part of the computer
Question Question that actually performs arithmetic and
logical operations on the data.
A 0 A FPU
B 1 B BIU
C 2 C EU
D 3 D ALU
During Instruction execution, an instruction is read in to Arithmetic and Logic instructions are
Question an ________ in the Processor. Question comes under the ______________ type.
A IR A Data Storage
B PC B Data Processing
C MAR C Data Movement
D MDR D Control
Movement of data in to or out of register and or memory I/O instructions are comes under the
Question locations are comes under the _____________ types. Question __________ types.
A Data Storage A Data Storage

B Data Processing B Data Processing
C Data Movement C Data Movement
D Control D Control
Test and Branch instructions are comes under the ACß D is related to ________________
Question __________ types. Question instruction.
Data Storage STOR A
A A
B Data Processing B LOAD D

C Data Movement C LOAD A
D Control D STOR D
Correct Answer D Correct Answer B
Question ____________ are represented by abbreviations, called Question _________ address instructions are
mnemonics,
Operands that indicates the operation. applicable
Zero to a special memory
organization, called a stack.
A A
B Opcodes B One
C Instructions C Two
D All of the above D Three
Question _______________ type of numerical data are common Question IRA encoded characters are almost always
A in computers.
Binary integer/ fixed point A stored
5 and transmitted using _____ bit
B Binary floating point B patterns.
6
C Decimal C 7
D All of the above D 8
Question ___________ is used on IBM mainframes which is an 8 Question The signed integers are in the ____’s
A bit
BCD code. A complement
1 representation and may be
BINARY 16,32
2 or 64 bits long.
B B
C EBCDIC C 9
D ASCII D 10
Question The three _______ representations conform to the IEEE Question The floating point type actually refers to a
A 754 standard.
Floating Point A set
BIUof types that are used by the ______
B Arithmetic B and
EU operated on by floating point
C Logical C instructions.
FPU
D All of the above D ALU
Question ____________ instructions are used to branch to a different Question ___________ address instruction would
A set
Dataof Storage
instructions A reference
Zero the top two stack elements.
depending on the decision made.
B Data Processing B One
Data Movement Two
C C
D Branch D Three
Question The packed _____ data types were introduced to the Question ______ operation is use d to transfer word
A X86
SSE architecture as part of the extensions of the A or block from source to destination.
Move
B instruction
MMX set to optimize performance of multimedia B Store
applications.
C SIMD C Load
D None of the above D Exchange
________ operation which fetch operand from _____ operation is used to transfer word
Question specified location and execute an Question from memory to processor.
A instruction without modifying PC. A Move
B Jump B Store
C Return C Load
D Execute D Exchange
Correct Answer All of the above Correct Answer C
C
Each character in the ASCII code is represented by a _____ operation is used transfer a word
Question unique _____ bit pattern; thus the 128 different Question from top of the stack to destination
characters can be represented.
A 4 A PUSH
B 5 B POP
C 6 C Load
D 7 D Exchange
_____ operation is used transfer a word from source to In X86 data types, when data are accessed
top of the stack. across 32 bit bus, data transfer take place
Question Question in units of double words, beginning at
address divisible by ______.
A PUSH A 3
B Store B 4
C Load C 5
D Exchange D 6
____ operation is used to swap contents of source ad _____ operation can subtract 1 from
Question destination. Question operand.
A Move A SUB
B Store B Decrement
C Load C Store
D Exchange D Load
______ operation is used to transfer word from _____ operation can perform complement
Question processor to memory. Question of the operand.
A Move A NOT
B Store B Test
C Load C Load
D Exchange D None of the above
__________ operation stop program execution. A branch instruction in which the branch
Question Question is always taken is an
_____________branch.
A Halt A Conditional
B Return B Unconditional
C Execute C Transfer
D All of the above D none of the above
__________ branch to location X if result is positive. _______ operation stop program

execution; test specified condition
Question Question repeatedly; resume execution when
condition is satisfied.
A BRO X A Halt
B BRZ X B Return
C BRN X C Wait
D BRP X D Execute
Question _____ operation can change the sign of the operand. Question _____ operation can add 1 to operand.
A PUSH A ADD
B POP B Increment
C Negate C Store
D Exchange D Load
_________ operation transfer instructions to I/O _________operation transfer status
processor to initiate I/O operation. information from I/O system to specified
Question Question destination.
A Input A Input
B Start I/O B Start I/O
C Test I/O C Test I/O
D Output D Output
__________ transfer data from specified source to I/O Arithmetic operation may ____________
Question port or device. Question
A Input A involve data transfer, before and /or after
B Output B perform function in ALU
C Translate C set condition codes and flags
In data transfer, if memory is involved then : The ______________ instruction, also

Question Question called a jump instruction.
A determine memory address A System Control
perform virtual to actual memory address transformation Data transfer
B B
C Check cache and initiate memory read/write C Branch
D All of the above D Rotate
______________ operation place current program _________ operation replace contents of

Question control information in known location and jump to Question PC and other register from known
specified address. location.
A Jump A Jump
B Jump Conditional B Jump Conditional
C Jump to Subroutine C Jump to Subroutine
D Return D Return
_____________ operation is used for unconditional ___________ transfer data from specified
Question transfer which loads PC with the specified address. Question I/O port or device to destination.
A Jump A Input
B Return B Output
C Execute C Translate
The common places for storing the return address are The principal reasons for the use of
Question ______________ Question procedures are __________.
A Register A Economy
B Start of called procedure B Modularity
C Top of stack C Both A and B
D All of the above D None of the above
_____________ branch to location X if overflow _____________ branch to location X if

Question occurs. Question result is zero
A BRO X A BRO X
B BRZ X B BRZ X
C BRN X C BRN X
D BRP X D BRP X
_____________ instruction that branches from the __________ branch to location X if result
Question present location to the procedure. Question is negative.
A Return A BRO X
B CALL B BRZ X
C Branch C BRN X
D All of the above D BRP X
____________ allow large programming tasks to be _____________ instruction that returns

Question subdivided in to smaller units. Question from the procedure to the place from
which it was called.
A Procedures A Return
B Macro B CALL
C Both A and B C Branch
The entire set of parameters, including return address, What is not true about CISC?
Question that is stored for a procedure invocation is referred to as Question
a _____________.
A Stack Frame A A limited and simple instruction set.
B Top of stack B High dependency on microporgram
C Stack Pointer C A large number of addressing modes
D All of the above D Small set of general purpose registers
Question What is true about CISC? Question What is true about CISC?
A High dependency on microporgram A A large number of addressing modes
B Hardwired control unit B Hardwired control unit
C Simple instruction pipeline C Simple instruction pipeline
D A limited and simple instruction set D A limited and simple instruction set
Question What is true about RISC? Question What is true about RISC?
A A limited and simple instruction set. A Hardwired control unit
A large number of general purpose registers Register operands with limited addressing
B B modes
C Simple instruction pipeline C A single chip processor
D All of the above D All of these
Question The _________operation inverts a bit. Question What is not true about CISC?
A ADD A A large instruction set
B SUB B Variable instruction/data formats
C NOT C A large number of addressing modes
D OR D A large set of general purpose registers
Most machines also provide a variety of operations for

manipulating individual bits of a word or other __________________ instructions are those
addressable units, often referred to as bit __________. that can be executed only while the
Question Question processor is in a certain privileged state or is
executing a program in a special
privileged area of memory.
A Wrap around A System Control

B Twiddling B Data transfer
C Manipulation C Shift
D All of the above D Rotate
Which processor has the necessity of manual Which register of current procedure
optimization for the generation of assembly language resemble physically similar to the
code especially for the embedded systems? parameter register of called procedure
Question Question during register to register operation in an
overlapping window of RISC Processors?
A RISC A Local Register

B CISC B Temporary Register
C Both A & B C Parameter Register
The iconic feature of the RISC machine among the Both the CISC and RISC architectures
Question following are Question have been developed to reduce the
______.
A Reduced number of addressing modes A Cost
B Increased memory size B Time delay
C Having a branch delay slot C Semantic gap
Logical operation may ____________ What does the compact and uniform
Question Question nature of instructions in RISC processors
facilitate to?
A involve data transfer, before and /or after A compiler optimization
B perform function in ALU B Pipelining
C set condition codes and flags C large memory footprints
D All of the above D none of the above
What are the significant designing issues/factors taken What is true about RISC?
Question into consideration for RISC Processors? Question
A Simplicity in Instruction Set A Hardwired control unit
B Pipeline Instruction Optimization B A single chip processor
C Register Usage Optimization C On chip cache and FPU
D All of the above D All of these
The RISC processor has a more complicated design than The computer architecture aimed at
Question CISC. Question reducing the time of execution of
instructions is ________.
A 1 A CISC
B 0 B RISC
C None of the above C ISA
D D ENIAC
The CISC stands for Out of the following which is not a CISC
Question Question machine.
A Computer Instruction Set Compliment A IBM 370/168
B Complete Instruction Set Compliment B VAX 11/780
C Computer Indexed Set Components C Intel 80486
D Complex Instruction set computer D Motorola A567
Pipe-lining is a unique feature of _______. In CISC architecture most of the complex

Question Question instructions are stored in _____.
A CISC A Register
B RISC B Diodes
C ISA C CMOS
D ENIAC D Transistors
Which of the architecture is power efficient? Which of the following is not true about
Question Question RISC processors?
A CISC A addressing modes are less
B RISC B pipelining is key for high speed
C ISA C microcoding is required
D ENIAC D single machine cycle instructions
The RISC processors that support variable length ADD R,Y may mean add the value
instructions are from contained in data location Y to the
contents of register R. In this
Question Question example, ____ refers to the
address of a location in memory
and ____ refers to a particular
register
A Intel A Y,R
B Motorola B R,Y
C AMD C R,R
D Intel and Motorola D Y,Y
The packed SIMD data types were introduced to __________ Instructions are those that

the X86 architecture as a part of the extensions of can be executed only while the processor
the instruction set to optimize performance of is in a certain privileged state or is
multimedia applications. These extensions executing a program in a special
Question include _______ and ______.
Question privileged area of memory. Typically
these instructions are reserved for the use
of the OS.
A SIMD , SSE A Memory
B MMX, SSE B Logical
C SIMD, MMX C System Control
D none of these D Data Transfer
The SIB Byte consists of three fields: The _________ Because condition codes are set by
field specifies the Scale factor for Scaled indexing; The normal arithmetic and data movement
Question _______ field specifies the Index register, The _____ Question instructions, they should reduce the
field specifies the Base Register. number of _____________ and
___________ instructions needed.
A Base,Scale, Index A COMPARE, TEST

B Scale, Index, Base B TEST, COMPARE
C Scale, Base,Index C AND, TEST
D Index, Scale, Base D None of these
Correct Answer Correct Answer A
A ________ instruction, also called a JUMP instruction, Conditional codes add complexity to the
Question has as one of its operands the address of the next Question _________________
instruction to be executed.
A Branch A Software
B ALU B Hardware
C Memory C Both A and B
____________________ registers: Enable the machine User visible register is one that may be
or Assembly Language Programmer to minimize main referenced by means of the machine
Question memory references by optimizing use of registers. Question language that the processor executes. We
can characterize these in
_____________________.
A Control A General purpose

B Status B Data
C Data C Address and condition codes
D User Visible D All of the above
A _______ instruction can be followed by two branches, Condition codes are irregular, they are
one on less than or equal to zero and one on greater than typically not part of the main ______
Question zero. Question path, so they require extra
_____________ connections.
A COMPARE A Address, Hardware

B BRANCH B Data, Hardware
C AND C Address,Software
D None of these D Data, Software
A simple instruction format consists of _____bit _____________________ register: Used

opcode and ____ bit operand references so that by control unit to control the operation of
Question complete format is of 16 bits. Question processor and by privileged, operating
system programs to control the execution
of programs.
A 4,6 A Control and Status

B 6,4 B Status
C 2,5 C Data
D 5,2 D User Visible
Most machines also provide a variety of operations for Conditional instructions, such as
manipulating individual bits of a word or other BRANCH are simplified relative to
Question addressable units, often referred to as ___________ Question composite instructions, such as
______________ and _______________
A Byte Twiddling A COMPARE, TEST

B Bit Twiddling B TEST, BRANCH
C Nibble Twiddling C AND, TEST
The address size determines the __________ size in The conditional REP Prefix causes the
instructions and the size of address offset generated instruction to Repeat until the count in
Question during _______ address calculation. Question _______ goes to ______ or until the
condition is met.
A Effective, Displacement A CX, Zero

B Displacement, Effective B DX, Zero
C Displacement, Physical C AX, Zero
D Effective, Physical D BX, Zero
When the absolute _____ prefix is present, the operation The Procedure mechanism involves two
specified in the instruction is executed repeatedly on basic instructions: a ______ instruction
successive elements of the string, the number of that branches from the present location to
repetitions is specified in register CX. the procedure, and a ________ instruction
Question Question that returns from the procedure to the
place from which it was called.
A REPZ A CALL, RETURN

B REPNZ B RETURN,CALL
C REP C CALL, NOT
D REPE D NOT, CALL
To allow maximum flexibility in data structure and In a pipelined implementation, ________

efficient memory utilization, words need not be aligned codes require special synchronization to
at even numbered address; double word need not be avoid conflicts.
Question aligned at address evenly divisible by _____ and quad Question
words need not be aligned at address evenly divisible by
______ and so on.
A 8,4 A Condition
B 2,6 B Uncondition
C 6,2 C Both A and B
D 4,8 D None of the above
Many processor designs include a register or set of The control unit requests a memory read,
registers, often known as the and the result is placed on the data bus
Question _________________________, that contain status Question and copied into the _____ and then
information plus condition codes. moved to the ______
A Control Status Word A MAR,IR

B Program Status Word B MBR,PC
C Machine Status Word C MBR,IR
D Condition Status Word D MAR,PC
____________ contains the address of an instruction to _____________ contains the address of

be fetched and _____________ contains the instruction location in memory and _________
Question most recently fetched. Question contains a word of data to be written to
memory or the word most recently read.
A PC, IR A PC, IR
B IR,PC B MAR, MDR
C PC,MAR C MBR,MAR
D IR, MBR D MAR, MBR
_________ Flag is set if operation resulted in a carry Execution will involve reading and
(addition) in to or borrow(subtraction) out of a high storing operands and performance of
Question order bit. Used for multiword arithmetic Operation. Question some operation. Thus, ______ stage may
have to wait for some time before it can
empty its __________.
A Sign A Execution,IR
B Zero B Fetch, IR
C Overflow C Buffer, Execution
D Carry D Execution, Buffer
An instruction cycle include ______________ indicates whether the

________________________ processor is executing in supervisor or
user mode. Certain privileged instructions
Question Question can be executed only in supervisor mode,
and certain areas of memory can be
accessed only in supervisor mode.
A Fetch A Sign
B Execute B Zero
C Interrupt C Overflow
D All of the above D Supervisor
The PC contains the address of the next instruction to be The ___________ time will generally
Question fetched. This address is moved to the ____ and placed Question longer than the _____________ time.
on the address bus.
A MAR A Fetch, Interrupt
B MBR B Fetch, Execution
C MDR C Execution, Fetch
D IR D Interrupt, Execution
When a ___________ branch instruction is passed on A conditional branch instruction makes

from the fetch to _________ stage, the fetch stage the address of the next instruction to be
fetches the next instruction in memory after the branch fetched unknown. Thus, the ________
instruction. stage must wait until it receives the next
Question Question instruction address from the ___________
stage. The execute stage may then have to
wait while the next instruction is fetched.
A Conditional, Execute A Fetch, Interrupt

B Unconditional, Execute B Fetch, Execute
C Conditional, Interrupt C Execute, Fetch
D Unconditional, Interrupt D Interrupt, Execute
The fetch and indirect cycles are simple and predictable. The execute cycle may involve
The ____________ cycle takes many forms; the form transferring data among registers, read or
Question depends on which of the various machine instruction is Question write from memory or I/O, and/or the
in the _______. invocation of the ____________.
A Execute, PC A MAR
B Instruction, PC B ALU
C Execute, IR C PC
D Instruction, PC D IR
Once the Fetch cycle is over, the control unit examines Like fetch and indirect cycles, the
the contents of the _____ to determine if it contains an interrupt cycle is simple and predictable.
Question operand specifier using indirect addressing. Question The current contents of the ______ must
be saved so that processor can resume
normal activity after the _________.
A PC A PC, Interrupt
B IR B IR, Interrupt
C MAR C MDR, IR
D MDR D MAR,IR
If the branch is taken, the ______ instruction must be _______________ read the next expected
discarded and a new _______ fetched. instruction into a buffer and
Question Question ______________ determine the opcode
and operand specifier.
A Fetched, instruction A Fetch Instruction, Write Operand

B Conditional, instruction B Fetch Instruction, Decode Instruction
C Unconditional, MDR C Fetch Operand, Execute Instruction
D Fetched, PC D Fetch Operand, Decode Instruction
A resource hazard is sometimes referred to as a A ____________ hazard occurs when two

Question __________ hazard. Question or more instructions that are already in
pipeline need same resource.
A Data A Resource
B Control B Data
C Fetch C Control
D Structural D All of the Above
There are _________ hazards A pipeline hazard occurs when he

pipeline, or some portion of the pipeline,
must stall because conditions do not
Question Question permit continued execution. Such pipeline
stall is also referred to as a
__________________.
A Resource A Pipeline Bubble

B Data B Pipeline Fetch
C Control C Pipeline Hazard
Calculate Operands calculate _________ address of ________________ instruction perform

each source operand. This may involve displacement, the indicated operation and store the
Question register indirect, indirect or other forms of address Question result, if any, in the specified destination
calculation. operand location.
A Offset A Write Operand

B Effective B Decode
C Physical C Fetch
D Virtual D Execute
A ___________ hazard occurs when there is a conflict To gain speedup, the pipeline must have
Question in the access of an operand location. Question more stages like:___________
A Data A Fetch and decode instruction
B Control B Calculate and fetch Operands
C Fetch C Execute instruction and write operand
D Structural D All of the above
________ store the result in memory and ______________ hazards, also known as
______________ fetch each operand from memory. a be=ranch hazard, occurs when the
pipeline makes the wrong decision on a
Question Question branch prediction and therefore brings
instructions into the pipeline that must
subsequently be discarded.
A Write Operand, Fetch Operand A Control

B Fetch Operand, Write Operand B Resource
C Write Operand, Read Operand C Data
D Read Operand, Write Operand D None of the above
____________: Two instructions both write to the same _____________ approaches have been
location. A hazard occurs if the write operations take taken for dealing with the conditional
Question place in the reverse order of the intended sequence. Question branches.
Read after Write, Or true dependency Multiple streams and Prefetch branch
A A Target
B Write after Read or antidependency B Loop Buffer
C Write after Write or output dependency C Branch Prediction and Delayed branch
_____________: An instruction modifies a register or _____________ An instruction reads a

memory location and a succeeding instruction reads the register or memory location and a
data in that memory or register location. A hazard occurs succeeding instruction writes to the
Question if the read takes place before the write operation is Question location. A hazard occurs if the write
complete. operation completes before the red
operation takes place.
A Read after Write, Or true dependency A Read after Write, Or true dependency
B Write after Read or antidependency B Write after Read or antidependency
C Write after Write or output dependency C Write after Write or output dependency
D None of the above D None of the above
The problem with the Multiple Steams approach : ________________ When a conditional
branch is recognized, the target of the
branch is prefetched, in addition to the
Question Question instruction following the branch. This
targetis then saved until the branch
instruction is executed.
There are contention delays for access to the registers Loop Buffer
A and to memory. A
Additional branch instructions may enter the pipeline Delayed Branch
(either Stream) before the original branch decision is
B resolved. Each such instruction needs an additional B
stream.
C Both A and B C Multiple Streams

D None of the above D Prefetch Branch Target
If a _________ occurs to a target just a few locations The Loop buffer is similar in principle to
Question ahead of the address of the branch instruction, the target Question a _________ dedicated to instructions.
will already be in the _____.
A Branch, Buffer A RAM
B Buffer, Branch B Memory
C Loop Buffer, Branch C Cache
D Branch, Delayed Branch D ROM
A _____________ is a small, very High Speed memory With the use of _______, the loop buffer
maintained by the instruction fetch stage of the pipeline will contain some instruction sequentially
Question and containing the n most recently fetched instructions, Question ahead of the current instruction fetch
in sequence. address.
A Loop Buffer A Execution
B Delayed Branch B Decoding
C Multiple Streams C Prefetching
D Prefetch Branch Target D Delayed Branching
If the buffer contains 256 bytes, and byte addressing is __________ Approach is static: they do
used, then the least significant ____ bits are used to not depend on the execution history up to
Question index the buffer. The remaining most significant bits are Question the time of the conditional branch
checked to determine if the branch target lies within the instruction.
environment captured by the buffer.
A 4 A Predict Never Taken

B 6 B Predict Always Taken
C 8 C Predict by Opcode
D 10 D All of the Above
____________ Approach is Dynamic: they depend on __________ strategies attempt to improve

the execution history. the accuracy of prediction by recording
Question Question the history of conditional branch
instruction in a program.
A Taken / not taken Switch A Static Branch

B Branch History Table B Dynamic Branch
C Both A and B C Branch History Table
D None of the above D Predict by Opcode
The ___________ is a small cache memory associated Each entry in the Branch History Table
Question with the instruction fetch stage of the pipeline. Question consists of _______________
A Static Branch A The address of the branch instruction
Dynamic Branch Some number of history bits that record
B B the state of use of a branch instruction
C Branch History Table C Information about the target instruction
D Predict by Opcode D All of the Above
If a _____________ is to be taken, the hardware first In __________________ it is possible to

check whether the branch target is within the improve pipeline performance by
_____________ automatically rearranging instructions
Question Question within a program, so that branch
instructions occur later than actually
desired.
A Branch, Buffer A Branch prediction

B Buffer, Branch B Delayed Branch
C Loop Buffer, Branch C Multiple Streams
D Branch, Delayed Branch D Loop Buffer
____________ when Set, the processor will recognize Characteristics of Reduced Instruction Set
Question external interrupts. Question Architecture ________________
A Trap Flag A One instruction per cycle
B Interrupt Enable Flag B Register to register operation
Direction Flag Simple addressing modes and simple
C C instruction formats
D Carry Flag D All of the above
Complex instruction sets are intended to ________________ determines whether

__________________ string processing instructions increment
Question Question or decrement the registers SI and DI (or
ESI or EDI)
A Ease the task of Compiler writer. A Trap Flag

Improve execution efficiency, because complex Interrupt Enable Flag
B sequences of operations can be implemented in B
microcode.
Provide support for even more complex and Direction Flag
C sophisticated HLLs. C
D All of the above D Carry Flag
__________ when Set, causes an interrupt after the A __________________________ is

execution of each instruction. This is used for defined to be the time it takes to fetch two
Question debugging. Question operands from registers, perform ALU
operation, and sore the result in a register.
A Trap Flag A Instruction cycle

B Interrupt Enable Flag B Machine cycle
C Direction Flag C Execute cycle
D Carry Flag D Fetch cycle
The additional functionality that can be placed on the The advantage of RISC processors is
Question same chip of RISC is Question
A memory management units A can operate at high clock frequency
B floating point units B shorter design cycle
C memory management and floating point arithmetic units C simple and fast
D RAM, ROM D all of the mentioned
In order to implement complex instructions, CISC Which of the following is an application

Question architectures use Question of RISC architecture by adding more
instructions?
A Macroprogramming A multimedia applications
B Hardwire B telecommunication encoding
C Microprogramming C image conversion
D None D all of the mentioned
The number of clock cycles that take to wait until the The feature of hybrid CISC-RISC
Question length of instruction is known in order to start decoding Question architecture is
is
A 0 A consume a lot of power
B 1 B not applicable for mobile applications
C 2 C processed by RISC core
D 3 D all of the mentioned
The feature of RISC that is not present in CISC is The RISC architecture is preferred to
Question Question CISC because RISC architecture has
A branch prediction A Simplicity
B pipelining B Efficiency
C branch prediction and pipelining C High speed
D None D All of the mentioned
The disadvantage of CISC design processors is The number of clock cycles that take to
Question Question wait until the length of instruction is
known in order to start decoding is
A low burden on compiler developers A 0
B wide availability of existing software B 1
C complex in nature C 2
D none D 3
Which of the following processor belongs to hybrid The instructions that instruct the
Question RISC-CISC architecture? Question processor to make a decision about the
next instruction to be executed are
A Intel Pentium III A data dependency instructions
B Intel Itanium 64 B branch instructions
C AMD’s X86-64 C control transfer instructions
D All of the mentioned D none
The reason for which the RISC processor goes to idle When an instruction depends on the
Question state(or stall) is Question results of the previous instructions then
A delay in reading information from memory A error occurs
B poor instruction set design B software fault occurs
C dependencies between instructions C data dependency occurs
D all of the mentioned D hardware fault occurs
Which of the following is not a stage of pipeline of a Which of the following is true about
Question RISC processor? Question register windowing?
A read registers and decode the instructions A chips expose 32 registers to programmer
B fetch instructions from registers B puts demands on multiplexers
C write result into a register C puts enormous demands on register ports
D access an operand in data memory D all of the mentioned
The number of CPIs(Clock Per Instruction) for an

Question instruction of RISC processors is Question
A 0 A
B 1 B
C 2 C
D 3 D
Correct Answer B Correct Answer
UNIT III
The control unit of a computer------------------- While designing a control unit, we have to
Question Question consider various factors like:------------
A Stores data in the memory A Amount of hardware used

B Accepts input data from keyboard B The speed of operation
C Generates control signals to execute an instruction C Cost of design
D None of these D All the above
State table method is used to design----------------- A micro-programmed control

Question Question unit-----------
A Hardwired control unit A Is faster than hard wired unit
Microprogrammed control unit Facilitates easy implementation of new
B B instructions
Both (A) and (B) Is useful when very small programs are to
C C be run
None of these Usually refers to the control unit of
D D microprocessor
--------- Means, the contents of the register R2 are Micro-instruction formats is given
Question transferred into register R1. Question by------------------
A R1<-X A Horizontal micro-instruction
B R1<-R2 B Vertical micro-instruction
C X<-R1 C Both (A) and (B)
D X<-X D None of these
Input for control unit ---------------- The machine instruction consists

Question Question of--------------
A IR A Operation Code (opcode)
B ALU flags B Reference to source operand
C Clock C Reference to destination operand
D All the above D All the above
Z register stores the output of ALU and ---------------Specifies the address in

Question hence-------------- Question memory for a read or write operation.
A It helps in avoiding the loop-bank of result A MBR
B It helps in pipelining B MAR
C Both (A) and (B) C PC
D None of these D None of Above
----------------instructions are used to bring data to and A micro instruction has----------------

Question from the registers. Question
A Data transfer A Control field
B Arithmetic and logic operation B Address field
C Control transfer C Both (A) and (B)
D Miscellaneous D None of these
Zero flag is set to ‘0’ when the result--------------. An instruction add X,Y is a-----------
Question Question address instruction.
A Is negative A 0
B Is zero B 1
C Is not zero C 2
D Borrow or carry is generated D 3
The operation executed on data stored in registers is The control signals for the operation
Question called Question MDR←M(MAR) are-------------
A Macro-operation A Marout, ramout, mdrin, system
B Micro-operation B Marin, ramout, mdrin, system
C Bit-operation C Marout, ramin, mdrin, system
D Byte-operation D Marout, ramout, mdrout, system
Sign flag is set to ‘0’ when the result----------------- When the result is zero, --------------flag is
Question Question set to 1.
A Is negative A Sign
B Is zero B Zero
C Has arithmetic overflow C Parity
D Is positive D Both (A) and (B)
The micro instruction MAR <- PC is executed -------------- Means, the contents of the
Question to----------------- Question register R1 are transferred into register
R2.
A Fetch an instruction A R1<-X
B Fetch the data B R1<-R2
C Both (A) and (B) C X<-R1
D None of these D X<-X
An instruction add X,Y,Z is a----------operand ----------- Means, the contents of CPU

Question instruction. Question registers R1and R2 are added and the
result is stored in register R1.
A 0 A R1<-R2+R1
B 1 B X<-R1+y
C 2 C R1<-R2-R1
D 3 D X<-R1-y
Which of the following statement is FALSE? Sign flag is set to ‘1’ when the
Question Question result-----------------
A Address is a type of operand A Is negative
B Number or character is a type of operand B Is zero
C Logical data is a type of operand C Has arithmetic overflow
D None of the above D Borrow or carry is generated
Vertical micro-instructions are characterized An instruction add X is a------------

Question by------------------ Question address instruction.
A Short formats A 0
B Considerable encoding of the control information B 1
C Both (A) and (B) C 2
D None of these D 3
An instruction add is a-------------address instruction. Which of the following is used to handle

Question Question several branches?
A 0 A Bit-oring
B 1 B Wide-branch addressing
C 2 C Both (A) and (B)
D 3 D None of these
The timing of processor operations is controlled by the Micro-programmed control unit has
Question ---------------. Question ability to handle complex instructions as it
is based on-----------
A Control unit A Programming
B Control signals B Fixed sequential circuit
C Clock C Easy decoding logic
D None of the Above D Cheaper cost of implementation
Carry flag is set to ‘1’ when the result--------------. Overflow flag is set to ‘1’ when the
Question Question result-----------.
A Is negative A Is negative
B Is zero B Is zero
C Has arithmetic overflow C Has arithmetic overflow
D Borrow or carry is generated. D Borrow or carry is generated
Micro instruction specify----------------------- -------------- is a type of micro-instruction.

Question Question
A Address of operand to be used for execution A Register transfer micro-operations
B Address of operand to operate on operands B Arithmetic micro-operations
C Valid data required at any time C Logic micro-operations
D Control signals to be activated at any time D All the above
Gates and control signals are provided for ---------- is easier to design?
Question ------------------ Question
A Movement of Data A Hard-wired control unit
B Storage of Data B Micro-programmed control unit
C Both (A) and (B) C Both (A) and (B)
D None of the Above D None of these
Adding new instructions is a complex task Registers are used to --------------.

Question in--------------- Question
A Hard-wired control unit A Move data between processor.
B Micro-programmed control unit B Store data internal to the processor.
C Both (A) and (B) C Store data external to the processor
D None of the above D None of these
--------------- Signals are provided for movement of data. The decoding and sequencing logic of
Question Question --------- is simpler.
A Gates and control A Hard-wired control unit
B Control signals B Micro-programmed control unit
C Gates C Control unit of RISC processor
D None of the Above D None of these
Zero flag is set to ‘1’ when the result--------------. Design of ---------------------- is based on
Question Question Wilkes control unit.
A Is negative A Hard-wired control unit
B Is zero B Micro-programmed control unit
C Is not zero C Control unit of RISC processor
D Borrow or carry is generated D None of these
Memory buffer register (MBR) -------------is a type of operand.

Question contains----------------------- Question
A The value to be stored in memory A Address
B The last value read from memory B Number or character
C A or B C Logical data
D Both A and B D All of these
Horizontal micro-instructions are characterized When the result has arithmetic overflow
Question by--------------- Question ---------- flag is set to ‘1’.
A Long format A Sign
B High degree of parallelism B Carry
C Little encoding of control information C Overflow
D All of these D Both (A) and (C)
Question ------------ are type of microinstructions. Question
A Register transfer micro- operations A
B Arithmetic micro- operations B
C Logical micro- operations C
D All the above D
Correct Answer D Correct Answer
In --------------- ,the control memory is organized as a In a Micro-programmed unit, hardware

Question PLA. Question cost is more because of the---------
A State-table method A Control memory
B Delay-element method B Access circuitry
C Sequence-counter method C Both (A) and (B)
D Wilkes control method D None of these
In ----------- method, of micro-program, micro- Y register is added to ALU-----------

Question instructions are stored in the control memory of the Question
control unit.
A Hardwired control unit A As most operations require 2 operands
B Micro-programmed control unit B For concurrency
C Both (A) and (B) C Both (A) and (B)
D None of these D To Avoid feedback
The control signals generated for the operation MAR<- Program counter (PC) holds the address
Question PC are---------- Question of-----------------
A Pcout, marin A Next instruction to be fetched
B Pcin,marout B Current instruction to be fetched
C Pcout,, marin C Previous instruction to be fetched
D Pcin, marin D None of the above
Hard-wired control unit is more suited to ------------- Internal data paths are used to move data
Question processor. Question -------------
A RISC A Between registers
B CISC B Between register and ALU
C Both (A) and (B) C Both A and B
Micro-programmed control unit is built around--------- ---------------- needed to handle complex

Question Question instructions.
A Control memory A Hard-wired control unit
B Sequencing logic B Micro-programmed control unit
C Control signals C Both (A) and (B)
D All of these D None of the above
Basic functional elements of the processor are Micro-programmed control unit finds
Question ------------- Question more applications in ---------- processor.
A ALU A RISC
B Registers B CISC
C Control Unit C Both (A) and (B)
Micro-programmed control unit is implemented Implementation of micro-programmed

Question using----------- Question control unit is done by-----------
A Combination circuit A Sequential circuit
B Sequential circuit B Finite state machine
Programming Storing micro-program in the control
C C memory
A hardwired control unit is faster than micro- For memory transfer operations------------
Question programmed control unit as--------- Question register is used to access data on the data
bus.
A Logic is implemented using sequential circuit A MBR
B It is designed with minimum number of components B MAR
C Both (A) and (B) C IOAR
D Either (A) Or (B) but not both D IOBR
To fetch a word of data from memory, the processor has All data transfer and operations within the
Question to perform -------- operation. Question processor are--------------
A Read A Synchronous
B Write B Asynchronous
C Store C Symmetrical
D Load D Asymmetric
In case of direct addressing mode the operand address is ------------- are needed by the control unit
Question given to MAR from ------- Question to determine the status of the Processor.
A Z register A Clock
B Accumulator B Registers
C MBR C Flag
D Y register D Both A and B
---------is more suited to RISC processor. The address where micro instructions are
Question Question stored in control memory is generated
by---------
A Hard-wired control unit A Program counter
B Micro-programmed control unit B Instruction register
C Control unit of RISC processor C Address generator
D None of these D Micro program sequencer
The function of control unit of a computer is to The processor has to specify the
Question -------------- Question ----------------------------- to fetch a word
of information from memory,
Stores data in the memory. Address of the memory location and
A A request a read operation.
B Accepts input data from keyboard. B Address of the memory location.
C Generates control signal to execute an instruction. C Request a read operation.
D None of the above. D Request a write operation.
---------- finds more applications in CISC processor. The hardwired control unit can be
Question Question considered as a ---------------- machine
that changes status in every clock cycle.
A Hard-wired control unit A Sequential
B Micro-programmed control unit B State
C Control unit of RISC processor C Control
Instruction are fetched from successive memory Which of the following is TRUE?
Question locations until ------------ Question
A next instruction is encountered. Data registers, ALU and interconnecting
A A bus are referred to as Control Path.
A branch or jump instruction is encountered. Data registers, ALU and interconnecting
B B bus are referred to as Processing Module.
A previous instruction is encountered. Data registers, ALU and interconnecting

C C bus are referred to as Data Path.
Both (A) and (B). Data registers, ALU and interconnecting
D D bus are referred to as Data Manipulator.
Z register is added to ALU---------- Which of the following statement is

Question Question CORRECT?
For concurrency It is easy to add new instructions in Hard-
A A wired control unit.
Increasing through put It is easy to add new instructions in
B B Micro-programmed control unit.
Both (A) and (B) It is difficult to add new instructions in
C C Micro-programmed control unit.
D To Avoid feedback of output from ALU D None of these
The control lines of the memory bus are connected ---------- Means, the contents of CPU
Question to------------ Question registers R1 is subtracted from R2 and the
A Control logic blocks A R1<-R2+R1
B Instruction Decoder B X<-R1+y
C MAR C R1<-R2-R1
D Instruction Decoder and control logic blocks D X<-R1-y
Micro-operations are the ------- operations of a PC is incremented by the length

Question processor Question of----------------during instruction
execution.
A Functional A Previously executed instruction.
B Atomic B Currently executing instruction.
C None of these C Next instruction to be executed.
D All of these D Smallest instruction executed.
Data path inside a processor includes------------- Each instruction cycle begins with
Question Question ---------------
A Registers, ALU A Fetch
B ALU, Interconnecting Bus B Indirect
C Registers, ALU, Interconnecting bus C Interrupt
D None of these D Execute
Which of the following is caused by control Which of the following statement is

Question signals-------------- Question TRUE?
Opening of logic gates Fetch causes an instruction to be fetched
A A from memory.
Closing of logic gates Decode causes an instruction to be
B B fetched from memory.
None Execute causes an instruction to be
C C fetched from memory.
D Both A and B D None of the Above
A single micro-operation involves-------------- ----------- activity does not take place

Question Question during execution cycle.
A simple ALU operations ALU performs the arithmetic &logical
A A operation.
B Transfer between registers B Effective address is calculated.
C Tn Transfer between register and an external bus C Next instruction is fetched.
All the above Branch address is calculated & Branching
D D conditions are checked.
Internal data paths are used to move data ----------- Control signals activate ------- within the
Question Question ALU.
A Between registers A Logic circuits
B Between register and ALU B Gates
C None of the above C Both (A) and (B)
D Both (A) and (B) D None of the above
-------------- defines all the operations and data transfers In single bus organization, Which input of
Question within processor within time periods. Question MUX gets operand directly from bus ?
A Processor clock. A A
B ALU clock. B B
C Register clock. C Y
D None of these. D None of these
Instruction cycle is made up of shorter subcycles of For register transfer ---------- operation is
Question --------- Question used
A Fetch A MAR<- MBR
B Indirect B R1 <- R2
C Execute C ALU <- R1
D Any of these D Both A and B
Question ------------ uses clock to keep time. Question ---------task performed by control unit.
A Data Unit A Sequencing
B Register B Execution
C Control Unit C Both (A) and (B)
D All of these D None of the above
Which is the first operation during fetch cycle? With reference to bus ----------- Signals
Question Question are provided for movement of data from
register.
Moves contents of memory location specified by MAR Gates
A to MBR. A
B Increment PC by the instruction length. B Control signals
C Moves contents of MBR to IR. C Both A and B
D Moves contents of PC to MAR. D None of the Above
Control step counter is used in ----------------------- to In vertical organization grouping

keep track of the control steps. technique number of bits required in
Question Question micro instructions is------------than
horizontal organization grouping
technique.
A Hard wired control, A Lesser

B Vertical micro-programming, B More
C Horizontal micro-programming C Fixed
A micro program sequencer---------------------- In hardwired control unit the control

Question Question signals are identified by------------
Generates the address of next micro instruction to be Contents of the control step counter &
A executed. A instruction register
Generates the control signals to execute a Contents of the condition code flags
B microinstruction B
Sequentially averages all microinstructions in the MFC & Interrupt requests
C control memory C
Enables the efficient handling of a micro program All of the above
D subroutine D
To indicate Fetch instruction ----------- micro instruction The goal of both hardwired control and
Question used. Question microprogrammed control units is to
-------
A MAR->PC A Access memory
B PC->MAR B Generate control signals
C MAR->MBR C Access the ALU
D None of the above D Optimize the resources
The methods for the design of hardwired control unit Register transfer is controlled by
Question are--------------- Question -------------
A State table & delay element A Rin and Rout
B Sequence counter & PLA B Rin
C Both (A) and (B) C Rout
Micro instruction specify----------------------- Which operation is performed by register

Question Question transfer micro operation?
A Address of operand to be used for execution A Rdestination->Rsource
B Address of operand to operate on operands B MDR ->M(MAR)
C Valid data required at any time C PC -> PC+1
D Control signals to be activated at any time D None of the above
In single bus organization, the input of MAR is The control unit controls other units by
Question connected to the -------- and output connected to the Question generating -------------
-----------
A External bus, Internal bus A Control signals
B Internal bus, MBR B Timing signals
C Internal bus, External bus C Transfer signals
D All of these D Command Signals
Micro-operations are-------- In horizontal organization grouping
technique number of bits required in
Question Question micro instructions is------------than
vertical organization grouping technique.
A Fu Functional or atomic operations of the processor. A Lesser

B No Non-functional or nuclear operations of the ALU B More
C Functional or gigantic operations of the processor C Fixed
D Both A and C D None of the above
MFC stands for-------------- --------- bus structure is usually used to

Question Question connect I/O devices.
A Memory Format Caches. A Single bus
B Memory Function Complete. B Multiple bus
C Memory Find Command. C Star bus
D Mass Format Command. D Databus
---------- are numbers and encoded characters, generally RTN stands for----------
Question used as operands. Question
A Input A Register Transfer Notation
B Data B Register Transmission Notation
C Information C Regular Transmission Notation
D Stored Values D Regular Transfer Notation
Can you perform addition on three operands In single bus organization output of
Question simultaneously in ALU using Add instruction? Question MAR is connected to the -----------
A Yes A Internal bus
B Not possible using Add, we’ve to use AddSetCC B MBR
C Not permitted C External bus
In single bus organization, the input of MAR is The instruction, Add R1,R2,R3 in RTN
Question connected to the -------- Question is-------------- .
A External bus A R3=R1+R2+R3
B MBR B R3<-[R1]+[R2]+[R3]
C Internal bus C R3=[R1]+[R2]
D All of these D R3<-[R1]+[R2]
While using the iterative construct

Question Question (Branching) in execution, ----------
The Instruction fetch phase ends with-------------- instruction is used to check the condition.
A Placing the data from the address in MAR into MDR A TestAndSet
B Placing the address of the data into MAR B Branch
Completing the execution of the data and placing its TestCondn
C storage address into MAR C
D Decoding the data in MDR and placing it in IR D None of the above
When using Branching, the usual sequencing of the PC The type of control signal are generated
Question is altered. A new instruction is loaded which is called as Question based on-------
-------------.
A Branch target A Contents of the step counter
B Loop target B Contents of IR
C Forward target C Contents of condition flags
D Jump instruction D All of the above
---------- are the different type/s of generating control Which of the following is used to
Question signals. Question implement the delay element?
A Micro-programmed A D flip flop
B Hardwired B T flip flop
C Micro-instruction C SR flip flop
D Both (A) and (B) D JK flip flop
What does the end instruction do ? The two phases of executing an

Question Question instruction are--------------
A It ends the generation of a signal A Instruction decoding and storage
B It ends the complete generation process B Instruction fetch and instruction execution
It starts a new instruction fetch cycle and resets the Instruction execution and storage
C counter C
It is used to shift the control to the processor Instruction fetch and Instruction
D D processing
In ---------- the instructions are executed in the order of Which of the following statement is true?
Question increasing addresses. Question
A Queuing A A micro instruction has Control field.
B Execution B A micro instruction has Address field.
C Programming C Both (A) and (B)
D Straight line sequencing D None of these
What does the hardwired control generator consist of What does the RUN signal do?
Question --------------- Question
A Decoder/encoder A It causes the termination of a signal
Condition codes It causes a particular signal to perform its
B B operation
C Control step counter C It causes a particular signal to end
D All of the above D It increments the step counter by one
In micro-programmed approach, the signals are A word whose individual bits represent a
Question generated by ----------. Question control signal is -----------.
A Machine instructions A Command word
B System programs B Control word
C Utility tools C Co-ordination word
D None of the above D Generation word
A sequence of control words corresponding to a control The disadvantage/s of the hardwired

Question sequence is called --------. Question approach is-------------------------
A Micro routine A It is less flexible
Micro function It cannot be used for complex instructions
B B
C Micro procedure C It is costly
D None of the above D Both (A) and (B)
Question Which of the following statement is true? Question Which of the following statement is true?
In single bus organization, the output of MAR is In single bus organization, the input of
A connected to the External bus A MAR is connected to the External bus
B connected to the MBR. B MAR is connected to the MBR.
C connected to the Internal bus. C MAR is connected to the Internal bus.
D All of these D All of these
---------------- Instruction format has shorter instruction If IR is an 8-bit register, then instruction
Question formats. Question decoder generates------------ signals, one
for each instruction.
A Horizontal A 16
B Vertical B 255
C Diagonal C 256
D Orthogonal D 32
The special memory used to store the micro routines of Individual control words of the micro
Question a computer is -----------. Question routine are called as ----------.
A Control table A Micro task
B Control store B Micro operation
C Control mart C Micro instruction
D Control shop D Micro command
The -------- unit of a computer Generates control signals The case/s where micro-programmed
Question to execute an instruction. Question cannot perform
well---------------------------
Data When it requires to check the condition
A A codes
Control When it has to choose between the two
B B alternatives
C Both (A) and (B) C When it is triggered by an interrupt
D None of these D Both (A) and (B)
Which is the first operation during fetch cycle? ------------- techniques are used to reduce
Question Question the number of bits in the micro
instructions.
Moves contents of memory location specified by MAR Separating
A to MBR. A
B Increment PC by the instruction length. B Grouping
C Moves contents of MBR to IR. C Skipping
D Moves contents of PC to MAR. D Bit pairing
Instructions are fetched from successive memory Data may be loaded into
Question locations until---------------------- Question MDR-----------------------------
A A next instruction is encountered. A From memory bus.
B A branch or jump instruction is encountered. B From internal processor bus.
C A previous instruction is encountered. C From PC register or MAR
Both (A) and (B). Either from memory bus or from internal
D D processor bus.
Memory interleaving technique is used to address the In case of direct addressing mode the
Question memory modules in order to have-------------- Question operand address is given to MAR
from…………….
A Higher average utilization A Z register
B Faster access to a block of data B Accumulator
C Reduced complexity in mapping hardware C MBR
D Both (A) &(B) D Y register
Which of the following is/are FALSE about Horizontal Which of the following is TRUE?
Question micro-instructions? Question
Long format Control unit controls the timing of
A A processor operations.
High degree of parallelism Control signals controls the timing of
B B processor operations.
Little encoding of control information Clock controls the timing of processor
C C operations.
D None of the Above D None of the Above
----------- is implemented as a sequential logic circuit or ---------------- Instruction format has

Question a finite state machine that generates a specific sequence Question longer instruction formats.
of control signals to execute an instruction.
A Hardwired control unit A Horizontal
B Micro-programmed control unit B Vertical
C Both (A) and (B) C Diagonal
D None of these D Orthogonal
The control unit causes one Micro-operation (or a set of The --------------- causes the processor to
simultaneous micro-operations) to be performed For step through a series of micro-operations
Question each clock pulse. This is also referred to as the Question in the proper sequence, based on the
------------ program being Executed. It is called
as........
A Processor cycle time A Control unit, Sequencing

B Clock cycle time B Data Unit, Sequencing
C Both A and B C Data Unit, Execution
D None of these D Control Unit, Execution.
In single bus organization, the instruction decoder and Which of the following is FALSE?
Question control logic unit is responsible Question
for-----------------------------------------
Implementing the actions specified by the instruction Bit-oring is used to handle several
A loaded in the IR register. A branches.
Implementing the actions specified by the instruction Wide-branch addressing is used to handle
B loaded in the IBR register. B several branches.
Implementing the actions specified by the instruction Both (A) and (B)
C loaded in the MBR register. C
Implementing the actions specified by the instruction None of these
D loaded in the PC register. D
Question For memory transfer operations MBR register is used Question Data may be loaded into MDR----------
A To access data on the data bus. A From memory bus.
B To store data on the data bus. B From internal processor bus.
C To access data on the address bus. C From PC register or MAR
To store data on the address bus. Either from memory bus or from internal
D D processor bus.
------------ Means, the contents of the memory location The timing of processor operations is
Y and register R1 are added and the result is stored in synchronized by the -------- and
Question memory location X. Question controlled by the -------------
with----------------.
A R1<-R2+R1 A Clock, Control unit control signals

B X<-R1+y B Control unit, control signals, clock
C R1<-R2-R1 C Control Signal, Clock, Control Unit
D X<-R1-y D Clock, Control Signal, Control Unit
For memory transfer operation------------ register Shift micro-operation is subset

Question provides the address on the address bus. Question of---------------
A MDR A Register transfer micro-operations
B MAR B Arithmetic micro-operations
C IOAR C Logic micro-operations
D IOBR D None of these
Adding a new instructions is a simple task in------ For memory transfer operation--------
Question Question register is used to access data on the data
bus.
A Hard-wired control unit A MDR
B Micro-programmed control unit B MAR
C Both (A) and (B) C IOAR
D None of the above D IOBR
Bit-oring and wide-branch addressing are used ------------- Means, the contents of the
Question to--------------- Question memory location X are transferred into
register R1.
A Reduced complexity of branching A R1<-X
B Handle several branches B R1<-R2
C Both (a) and (b) C X<-R1
D None of these D X<-X
The------ of the current instruction are used to determine Memory buffer register (MBR) is
Question which micro-operations to perform during the execute Question connected to-----------------
cycle..
A Opcode A The address lines of the system bus.
B Addressing Mode B The address lines of the control bus.
C Operand C The data lines of the system bus.
D Both A and B D The data lines of the control bus.
Select the correct statement Hardwired control unit is

Question Question ----------------than micro-programmed
but-----------------?
A micro-programmed control unit is faster than Cheaper, more error prone
A hardwired control unit A
Micro-programmed control unit is implemented using Faster, more error prone
B programming B
C Design process of hardwired control unit 1’s complex C Less error prone, slower
D Both (B) and (C) D Faster, harder to change
To fetch an operand addressed using direct addressing, Arrange the following configurations for
the micro instruction executed is---------------- CPU in decreasing order of operating
Question Question speeds:Hard wired control, vertical micro-
programming, horizontal micro-
programming.
MAR<-PC Hard wired control, vertical micro-

A A programming, horizontal micro-
programming
MAR<-M(MDR) Hard wired control, horizontal micro-
B B programming, vertical micro-
programming
PC<-PC+1 Horizontal micro-programming, vertical
C C micro- programming, hard wired control
In case of direct addressing mode the operand address is Which of the following is the correct
Question given to MAR from-------- Question indirect cycle sequence of micro
Z register MAR ←MBR, MBR ← Memory,
A A IR(Address) ← (MBR(Address))
Accumulator MAR ← (IR(Address)), MBR ←
B B Memory, IR(Address) ←
(MBR(Address))
MDR MAR ← (PC), MBR ← Memory, PC ←
C C (PC) + 1, IR ← (MBR)
Y register MBR ← Memory, IR(Address) ←
D D (MBR(Address)), MAR ← (IR(Address))
Question Registers are used to ---------------------- Question External data paths-------------------

A Move data between processor. A Link registers to memory.
B Store data internal to the processor. B Link registers to I/O modules.
C Store data external to the processor C Link memory to registers.
D None of these D Both A and B
Micro-programmed control unit is ------------- than -----------signals are provided for

Question hardwired but ------------------>? Question movement of data ----------- from each
register.
A Cheaper, more error prone A Gates and control, onto and off the bus
B Faster, more error prone B Control signals, onto the bus
C Less error prone, slower C Gate, onto the bus
D Faster, harder to change D Gate, off the bus
Control signals are used to ------------------- ….. Means, the contents of the memory
Question Question location Y is subtracted from R1 and the
result is stored in memory location X.
A Activate an ALU function A R1<-R2+R1
B Activate a data path B X<-R1+y
C Both A and B C R1<-R2-R1
D None of these D X<-R1-y
A single micro-operation generally involves Flag are needed by the control unit to
Question ----------------------- Question determine -------------------
A A transfer between registers A The status of the Processor
A transfer between a register and an external bus The outcome of previous ALU operations
B B
C A simple ALU Operation. C The outcome of next ALU operations
D All of these D Both (A) and( B)
In hardwired control unit, the sequence of operations Which of the following is the correct
Question carried out is determined by ------------- Question fetch sequence?
Step counter MAR ←(PC), Memory ←( MBR) , PC <-
A A (PC) + 1, MBR ←( IR)
IR (PC) ←( MAR) , MBR ←Memory, MBR
B B ←( IR), PC ←( (PC) + 1
Wiring of the logic elements MAR ←(PC), MBR ←( Memory) ,
C C PC ←PC + 1, IR ← (MBR)
D Decoder D None of these
A single micro-operation involves----------- -------------means, contents of CPU

Question Question registers R1 and R2 are added and the
A A simple ALU operations A R1<-R2 + R1
B Transfer between registers B X<-R1 + y
C Transfer between register and an external bus C R1<-R2-R1
D All of these D X<-R1-y
Which activity does not take place during execution Which of the following is the correct
Question cycle? Question interrupt cycle sequence of micro-
operation?
ALU performs the arithmetic &logical operation. MBR ← PC, MAR ← Save_Address,
A A PC ← Routine_Address, Memory
←(MBR)
Effective address is calculated. MAR ← Save_Address, PC ←
B B Routine_Address, Memory ← (MBR),
MBR ←PC
Next instruction is fetched. MAR ← (IR(Address)), MBR ←
C C Memory, IR(Address) ←
(MBR(Address))
Branch address is calculated &Branching conditions are MAR ← Save_Address, MBR ← PC, PC
D checked. D ← Routine_Address, Memory ←(MBR)

Memory address register (MAR) is connected to the The micro-operation MAR ← PC must
Question ----------------- Question precede by,
A Data lines of System Bus A Memory ← MBR
B Address lines of the system bus B Memory ← IR
C Address lines of the data bus C MBR ← Memory
The instruction decoder in hardwired control unit The methods for the design of hardwired
Question generates ----------------- signal line for each machine Question control unit are
instruction.
A Required A Sate table &delay element
B All B Sequence counter &PLA
C A separate C Both( A) &(B)
D No D None of these
For the increment-and-skip-if-zero (ISZ) instruction, the In hardwired control unit, the sequence of
Question control unit will ------------- Question operations carried out is determined by
-------------
A Decrement the PC if the zero flag is set A Step counter
B Increment the PC if the zero flag is set B IR
C Increment the PC if the one flag is set C wiring of the logic elements
D Decrement the PC if the one flag is set D Decoder
When RUN control signal in hardwired control unit is The hardwired control unit can be
Question set to 1, it causes --------------- to be incremented by one Question considered as a ---------------- machine
at the end of every clock cycle. that changes status in every clock cycle.
A Counter A sequential
B MBR B state
C IR C control
D Incrementer D None of these
Select the wrong statement Hardwired control unit has little

flexibility, and the complexity of
Question Question instruction set it can implement, is limited
due to ----------------
A hardwired control unit is cheaper than micro- Software
A programmed control unit. A
A micro-programmed control unit is cheaper than Wiring of the logic elements
B hardwired unit B
It is easier to design micro-programmed control unit Wiring of the logic elements
C compare to hardwired unit C
New instructions can be added at ease in case of a Software
D micro-programmed control unit D
In state table design method of hardwired control unit, Microinstructions are stored in control
Question for input signals BEGIN, COUNT, Q0 &Q-1 , the Question memory groups, with each group
possible number of states are specifying a
A 4 A Routine
B 8 B Subroutine
C 16 C Vector
D 24 D Address
Select the wrong statement One subdivision that we found convenient

Question Question is fetch, indirect, execute, And interrupt,
with ------------
Hardwired control unit is used in RISC up Only fetch and execute cycles always
A A occurring.
Micro-programmed control unit is used in CISC up Only indirect and interrupt cycles always
B B occurring.
Control memory is present in hardwired control unit Only fetch and indirect cycles always
C C occurring.
Control memory is present in micro-programmed Only fetch and interrupt cycles always
D control unit D occurring.
In hardwired control unit, the control

A control character is sent at the beginning as well as at the hardware can be viewed as a state
Question end of each block in the Question machine changing state depending upon
synchronous-transmission in order to -------------------
contents of
A Synchronize the clock of transmitter and receiver. A IR

Supply information needed to separate the incoming bits Condition codes
B into individual character. B
C Detect the error in transmission and received system. C external inputs like MFC &internals
D Both (A) and (C). D All of them
The number of bits required in micro instructions is Identity which mutually exclusive control
------------in vertical organization grouping technique signals can be encoded in one group?
Question compared to horizontal organization grouping Question
technique.
A Lesser A Pcout,R1out,Zin
B More B Pcin,R1out,Zin
C Fixed C Read, Write
D None of the above D None of them
Which operation refers bitwise manipulation of contents WMFC signal is required in microroutine
Question of register: Question of which instruction?
A Logical micro operation A Add R1,R2
B Arithmetic micro operation B Mov R1,R2
C Shift micro operation C Mov (R1),R
D None of these D Sub R2,R1
Which control signal causes the processer's control Which activity does not take place during
Question circuity to wait for the arrival of MFC(memory function Question execution cycle?
completed) signal?
Wait ALU performs the arithmetic &logical
A A operation.
B Read B Effective address is calculated.
C WMFC C Next instruction is fetched.
MARin Branch address is calculated &Branching
D D conditions are checked.
Which the second step is during addition of the contents Which the third step is during add the
of register R1 to those of register R2 and storing the contents of register R1 to those of register
Question results in register R3? Question R2 and store the results in register R3?
A R2out, Select Y, Add, Zin A R2out, Select Y, Add, Zin

B Zout, R3in B Zout, R3in
C R1out, Yin C R1out, Yin
D Yin, R1out D Yin, R1out
Which is the straight forward register transfer the data In signal bus organization of the
Question from register to another register temporarily: Question processor activation MAR in signal cause
A Digital system A contents of bus internal to store in MAR

B Register B contents of if PC to store in MAR
C Data C contents of MDR to store in MAR
D Register transfer operations D contents of MAR to store to bus
Which is the first operation during fetch cycle? The control signals for operation PC ←
Question Question PC + 1 are
Moves contents of memory location specified by MAR PCout, ALUin, INC, Zout, PCin
A to MBR. A
B Increment PC by the instruction length. B PCout, ALUout, INC, Zout, PCin
C Moves contents of MBR to IR. C PCin, ALUin, INC, Zout, PCin
D Moves contents of PC to MAR. D PCout, ALUin, INC, Zin, PCin
Which approach is used in micro

Which control signals will be generated by system, when
contents of register R3 are programmed control to check the status of
Question Question condition codes?
Transferred the MAR?
A R3out, MARin, Read A Appropriate logic circuit

B R3out, MARout, Read B Appropriate programming logic
C R3in, MARin, Read C Conditional branch microinstructions
D R3out, Read, MARin D None of them
The goal of both hardwired control and What happens when

Question microprogrammed control units is to_______ Question 'END'microinstruction is active in
microroutine?
access memory µPC is loaded with starting microroutine
A A address for instruction fetch cycle
generate control signals µPC is loaded with starting microroutine
B B address for previous instruction
access the ALU µPC is loaded with starting microroutine
C C address for instruction execute cycle
D Optimize the resources D none of them
What is the advantages of multiple bus organization

over single bus organization within the process? Arrange the following configurations for
CPU in decreasing order of operating
Question Question speeds:Hard wired control, vertical micro-
programming, horizontal micro-
programming.
multiple internal transfer in parallel Hard wired control, vertical micro-
A A programming, horizontal micro-
programming
no need of using temp register Y,Z Hard wired control, horizontal micro-
B B programming, vertical micro-
programming
reduces no. of clock cycles required for execution Horizontal micro-programming, vertical
C C micro- programming, hard wired control
D All of them D None of these
----------- activity does not take place during execution The decoder/encode block in hardwired
cycle. control unit is --------------circuit that
Question Question generates the required control outputs,
depending on the state of all its inputs.
A ALU performs the arithmetic &logical operation. A Sequential

B Effective address is calculated. B Combinational
C Next instruction is fetched. C Both
Branch address is calculated & Branching conditions are None of these
D checked. D
The step decoder in hardwired control unit provides The hardwired control unit can be
Question ----------------- signal line for each step or time slot, in Question considered as a ---------------- machine
the control sequence. that changes status in every clock cycle.
A Required A sequential
B All B state
C A separate C control
D No D None of these
Micro-programmed control unit is -------------------than which operation is performed by register

Question hardwired but ----------------? Question transfer micro operation------------------
A cheaper, more error prone A Rdestination<-Rsource
B faster, more error prone B MDR <-M(MAR)
C less error prone, slower C PC <-PC+1
D faster, harder to change D None of the above
When RUN control signal in hardwired control unit is In hardwired control unit, the sequence of
Question set to 1, it causes ------------------- to be incremented by Question operations carried out is determined by
one at the end of every clock cycle. -------------
A Counter A step counter
B MBR B IR
C IR C wiring of the logic elements
D Incrementer D Decoder
In the hardwired control, the control units use Which of the following is the correct
Question --------------- logic circuits to interpret instructions and Question fetch sequence?
generate control signals.
Fixed MAR ←(PC), Memory ←( MBR) , PC <-
A A (PC) + 1, MBR ←( IR)
Varying (PC) ←( MAR) , MBR ←Memory, MBR
B B ←( IR), PC ←( (PC) + 1
Both (A) and (B) MAR ←(PC), MBR ←( Memory) ,
C C PC ←PC + 1, IR ← (MBR)
Which of the following is the correct interrupt cycle Which operation is extremely useful in
Question sequence of micro-operation? Question serial transfer of data:
MBR ←PC, MAR ← Save_Address, PC ← Logical micro operation
A Routine_Address, Memory ←(MBR) A
MAR ← Save_Address, PC ← Routine_Address, Arithmetic micro operation
B Memory ← (MBR), MBR ←PC B
MAR ← (IR(Address)), MBR ← Memory, Shift micro operation
C IR(Address) ← (MBR(Address)) C
MAR ← Save_Address, MBR ← PC, PC ← None of these
D Routine_Address, Memory ←(MBR) D
In single bus organization, the input of MAR is Which of the following is the correct
Question connected to the--------------- and outputis connected to Question indirect cycle sequence of micro
the ------------------.
External bus, Internal bus MAR ←MBR, MBR ←Memory,
A A IR(Address) ←(MBR(Address))
Internal bus, MBR MAR ←(IR(Address)), MBR ←Memory,
B B IR(Address) ←(MBR(Address))
Internal bus, External bus MAR ←(PC), MBR ←Memory, PC

C C ←(PC) + 1, IR ←(MBR)
All of these MBR ←Memory, IR(Address)
D D ←(MBR(Address)), MAR
←(IR(Address))
Micro-operations are--------------------------- When using Branching, the usual

sequencing of the PC is altered. A new
Question Question instruction is loaded which is called as
-------------.
A Functional or atomic operations of the processor. A Branch target

B Non-functional or nuclear operations of the ALU B Loop target
C Functional or gigantic operations of the processor C Forward target
D Both A and C D Jump instruction
Which control signals can be encoded in one group? The main advantage of multiple bus
Question Question organisation over single bus
is----------------
PCout,MDRout,Pcin Reduction in the number of cycles for
A A execution
B PCin,MDRin,Read B Increase in size of the registers
C Add,Sub,Read C Better Connectivity
D Pcin,MDRin,MARin D None of these
Which operation are binary type, and are performed on Highly encoded schemes that use compact
bits string that is placed in register codes to specify a small number of
Question Question functions in each micro instruction is
--------------------
A Logical micro operation A Horizontal organisation

B Arithmetic micro operation B Vertical organisation
C Both C Diagonal organisation
D None D None of the above
Delay element method is used to design ------------------ When using Branching, the usual
sequencing of the PC is altered. A new
Question Question instruction is loaded which is called as
--------------------
A Hardwired control unit A Branch target

B Microprogrammed control unit B Loop target
C Both A) and B) C Forward target
D None of the above D Jump instruction
The delay element are implemented by When the instructions are executed in the
Question ------------------and controlled by a common clock signal Question order of increasing addresses, it is
called-----------------
A D flip flop A Queuing
B T flip flop B Execution
C SR flip flop C Programming
D JK flip flop D Straight line sequencing
In a non-vectored interrupt, the address of interrupt CPU checks for an interrupt signal
Question service routine is ------------------ Question during------------------
A Obtained from interrupt address table. A Starting of last Machine cycle
B Supplied by the interrupting I/O device. B Last T-State of instruction cycle
C Obtained through Vector address generator device. C First T-State of interrupt cycle
D Assigned to a fixed memory location. D Fetch cycle
UNIT IV
Computer memory is organized into …........? What are kinds of methods of accessing
Question Question units of data?
A Standard A Sequential Access
B Rule B Direct Access
C Hierarchy C Random Access
D Level D All of Them
Which are Interrupt modes of 82C59 are possible? Which of following is not External
Question Question memory?
A Fully nested A Disk Memory
B Rotating B Tape Memory
C Special mask C RAM Memory
D All of these D Optical Disk
Which of following is not internal memory? Which of following statement is correct

Question Question w. r. to Memory management Unit?
Cache Memory Translates each virtual address into a
A A physical address in the memory
RAM Translates each virtual address into a
B B physical address in the secondary memory
C Disk Memory C Both A and B

D Registers D None of these
For random-access memory, the............... is key design How do you will explain unit of transfer
Question issue. Question characteristic of external memory?
Organization Number of electrical lines into and out of
A A memory.
B Physical arrangement of bits B Equal to word length
C Both A and B C Blocks
Normally, Semiconductor memory are …......... in Which of statement are correct w. r. to

Question nature. Question cache size?
Volatile The size of cache to be small enough so
A A that the overall average cost per bit is
close to that main memory.
Nonvolatile The size of cache to be large enough so
B B that overall average access time is close to
cache
C Both A and B C Both A and B
Which of following mapping techniques are used for Non erasable semiconductor memory are
Question mapping between cache line and main memory block? Question also called as...............?
A Direct A Random Access Memory
B Associative B Read Only Memory
C Set associative C Both A and B
Which of following is highest level of computer Which of following option is not

Question memory? Question replacement algorithm for cache mapping
A RAM A LRU, FIFO
B ROM B LFU, LRU
C Secondary Memory C LIFO, Priority
D Processor Register D Round Robin
The term applied to situations where the same value or Which of following statement is correct
Question related storage locations are frequently accessed called Question w. r. to Virtual Memory?
as .....................
Principle of refrence Facility that allows programs to address
A A memory from logical point of view.
Royality principal Same facility is without regard to the
B B amount of main memory physical
available.
C Principle of locality C Both A and B
In which term, we will measure the characteristic of Suppose there are L1, L2, and L3 cache
internal memory capacity? are placed between processor and main
Question Question memory, then which of following
statements is not valid?
Bit L2 cache is slower and larger in size than
A A L1 cache
Byte L3 cache is slower and smaller in size
B B than L2 cache
Words L2 cache is faster and larger in size than
C C L1 cache
Mbyte L3 cache is faster and smaller in size than
D D L3 cache
What is Addressable unit of transfer characteristics? In LRU, replacement algorithm for two-
way set associative cache mapping, which
Question Question of following bit uses as USE bit as 1?
A Word A When line is referenced

B Byte Level B When line is not referenced
D None of these D None of them
For random-access memory, the............... is key design What is the concepts of hit?
Question issue. Question
Organization If the accessed word is found in the faster
A A memory.
Physical arrangement of bits If the accessed word is not found in the
B B faster memory.
In which term, we will measure the characteristic of Which of following is lowest level of
Question external memory capacity? Question computer memory?
A Bit A RAM
B Byte B Tape
C Words C Secondary Memory
D Megabit D Cache Memory
What is Transfer rate for random access memory? Which of following is correct option for
Question Question write through cache write policy
It is 1/(Cycle time) All write operation are made to main
A A memory as well as cache
It is the data can be transferred into or out of memory. All write operation are made to only main
B B memory not cache
Which of following statement is advantage of logical Which of following options are valid for
Question cache? Question types of principle of locality?
Physical cache can respond before the MMU perform an Temporal
A address translation A
B Access speed is faster than physical cache. B Spatial
C Both A and B C Sequential
D None of these D All of these
How do you will explain unit of transfer characteristic Which of following statements is correct,
Question of internal memory? Question when physical cache is used?
Number of electrical lines into and out of memory. Stores data using main memory physical
A A addresses
Equal to word length Stores data using main memory logical
B B addresses
What is the concepts miss? Which are Interrupt modes of 82C59 are
Question Question possible?
If the accessed word is found in the faster memory, Fully nested
A called as hit A
If the accessed word is not found in the faster memory, Rotating
B called as miss B
C Both A and B C Special mask
Question What is the concepts of hit? Question What is logical cache?

If the accessed word is found in the faster memory. Is the virtual cache, stores data using
A A virtual addresses.
If the accessed word is not found in the faster memory. Is the physical cache, stores data using
B B physical addresses.
Both A and B Is the virtual cache, stores data using
C C physical addresses.
None of these Is the physical cache, stores data using
D D virtual addresses.
The term applied to situations where the same value or What is concepts of isolated I/O?
Question related storage locations are frequently accessed called Question
as .....................
Principle of refrence Address space for I/O same from that for
A A memory.
Royality principal Address space for I/O isolated from that
B B for memory.
Principle of locality Address space for I/O isolated from that
C C for I/O.
None of these Address space for I/O same from that for
D D I/O.
With memory mapped I/O, there is .................. address What is Transfer rate for non random
Question for memory location and I/O devices. Question access memory?
A Many A It is 1/(Cycle time)
A single It is the data can be transferred into or out
B B of memory.
C Most C Tn = TA+n/R
D None of these D Tn = Tn+R/n
Which of following is the option for off-line storage? Non erasable semiconductor memory are
Question Question also called as...............?
A Main Memory A Random Access Memory
B Magnetic Tape B Read Only Memory
C Magnetic Disk C Both A and B
D Cache Memory D None of these
Suppose there are L1, L2, and L3 cache are placed Which of following statement is correct
Question between processor and main memory, then which of Question w. r. to Virtual Memory?
following statements is valid?
L2 cache is slower and larger in size than L1 cache Facility that allows programs to address
A A memory from logical point of view.
L3 cache is slower and larger in size than L2 cache Same facility is without regard to the
B B amount of main memory physical
available.
In a volatile memory, information decays naturally or is Suppose there are L1, L2, and L3 cache
…...... when electrical power is switched off. are placed between processor and main
Question Question memory, then which of following
statements is not valid?
Saved L2 cache is slower and larger in size than
A A L1 cache
Lost L3 cache is slower and smaller in size
B B than L2 cache
Both A and B L2 cache is faster and larger in size than
C C L1 cache
None of these L3 cache is faster and smaller in size than
D D L3 cache
Suppose there are L1, L2, and L3 cache are placed Which of following is the option for off-
Question between processor and main memory, then which of Question line storage?
following statements is valid?
A L2 cache is slower and larger in size than L1 cache A Main Memory
B L3 cache is slower and larger in size than L2 cache B Magnetic Tape
C Both A and B C Magnetic Disk
D None of these D Cache Memory
Which of following statement is correct w. r. to Which of following technique is not more

Question Memory management Unit? Question efficiant?
Translates each virtual address into a physical address in Programmed I/O
A the memory A
Translates each virtual address into a physical address in Interrupt-driven I/O
B the secondary memory B
Which of following technique is not more efficiant? Which of following problem are there to
Question Question maintain cache coherency
A Programmed I/O A Bus watching with write-through
B Interrupt-driven I/O B Hardware transparency
C Both A and B C Noncacheble memory
D None of these D All of them
Normally, Semiconductor memory are …......... in With respect to nonvolatile memory,

Question nature. Question which of following statement is correct?
Volatile information decays naturally or is lost
A A when electrical power is switched off.
Nonvolatile Information once recorded remains
without deterioration until deliberately
B B changed; no electrical power needed to
retain information.

A disk is a circular platter constructed of .................... Nonvolatile memory is also called as

Question material, called as subtrate. Question ….......?
A Magnetic A Primary memory or auxiliary memory
B Nonmagnetic B Secondary memory or auxiliary memory
What is write back cache write policy? Which of following are cache coherence
Question Question policies
It minimizes memory write and update are made in Write go and write back
A cache A
When updates occurs, a dirty bit or use bit, associated Write go and write through
B with line is set B
A block is replaced it is written back to main memory if write through and write back
C and only if the dirty bit is set. C
D All of them D None of them
Normally, Magnetic-surface memory are …......... in Nonvolatile memory is also called as

Question nature. Question ….......?
A Volatile A Primary memory or auxiliary memory
B Nonvolatile B Secondary memory or auxiliary memory
For multiple-word I/O transfer, DMA is ........... efficient Which of following statement is the
Question than interrupt driven or programmed I/O. Question concept of Cache coherence
Less Multiple copies of the same data can exist
A A in different caches simultaneously
More If processor are allowed to update their
B B own copy freely, an inconsistent view of
memory can result
C Equal C It effect of multiprocessor system
D None of these D All of them
For multiple-word I/O transfer, DMA is ........... efficient Which of following cache coherence
Question than interrupt driven or programmed I/O. Question policy result in inconsistency?
A Less A Write through
B More B Write back
C Equal C Write go
............ is the most important components of external What is MESI protocol?
Question memory. Question
A RAM A Modified/Exclusive/Single/Invalid
B ROM B Modified/Exclusive-OR/Shared/Invalid
C Magnetic disk C Modified/Exclusive/Shared/Invalid
D Magnetic tape D None of them
Normally, Magnetic-surface memory are …......... in What is disadvantage of memory mapped

Question nature. Question of programmed I/O?
Volatile Valuable memory address space is used
A A up.
Nonvolatile Less valuable memory address space is
B B used up.
Both A and B Least valuable memory address space is
C C used up.
D None of these D None of thses
During read and write operation of magnetic disk, head In which of the following case write-
Question is stationary while ............ rotates beneath it. Question through policy result in inconsistency?
Head Inconsistency can occur unless other
A A cache monitor the memory traffic
Platter Receive some direct notification of update
B B
C Tail C Both A and B
Cache memory is also called as …........? Which of following technique is more

Question Question efficiant?
A Slower and cheaper memory A Programmed I/O
B Faster and cheaper memory B Interrupt-driven I/O
C Slower and expensive memory C Both A and B
D Faster and expensive memory D None of these
Question Cache memory is also called as …........? Question What is vector interrupt?
Slower and cheaper memory The processor uses the vector as pointer
A A to the apropriate service routine
Faster and cheaper memory This avoids the need to execute a general
B B interrupt routine first
C Slower and expensive memory C This is called as vectored interrupt
D Faster and expensive memory D All of these
If the processor is faster than the I/O module, In magnetic disk storage, concentric rings,
Question then.............. Question called as ................
A I/O module's time is wasteful A Platter
B Processor time is wasteful B Track
C Both will perform together C Sector
Which of following interrupt identification techniques Disadvantage of software poll interrupt

Question are going to be used when problem is occurred between Question identification techniques?
processor and I/O modules?
A Multiple interrupt lines A Not time consuming
B Software poll B Time consuming
C Daisy chain C vast
D Bus arbitration D None of these
Which of following is the valid option for programmed The occurance of interrupt can
Question I/O? Question be.................
Data are exchanged between external devices and I/O Predictable
A module A
Data are exchanged between processor and the I/O Unpredictable
B module B
D None of them D None of these
............ is the most important components of external A disk is a circular platter constructed
Question memory. Question of .................... material, called as
subtrate.
A RAM A Magnetic
B ROM B Nonmagnetic
C Magnetic disk C Both A and B
D Magnetic tape D None of these
In two-level cache, which of following statement is In two-level cache, which of following

Question correct and increases perfomance? Question statement is not correct ?
L1 cache is on-chip with processor and L2 as DRAM or L1 cache is on-chip with processor and
A ROM A L2 as DRAM or ROM
L1 cache is on-chip with processor and L2 as SRAM L1 cache is on-chip with processor and
B B L2 as SRAM
D None of them D None of them
Which of following are not valid options for functions In magnetic disk storage, adjacent tracks
Question of I/O module? Question separated by gaps, because...............
Processor communication They prevents or at least minimises, errors
A A
Device communication Minimises the interference of magnetic
B B fields
C Data buffereing C Both A and B
D Error correction D None of these
Advantage of on-chip cache The concept of cache on the same chip as

Question Question the processor called as ….....?
A Cache is reachable to the processor A Off-chip cache
B Speeds up the execution B On-chip cache
C Improves system performance C External cache
When cache memory was introduced at that time how Which of following are valid options for
Question many level of cache was there? Question functions of I/O module?
A One level cache A Processor communication
B Two level cache B Device communication
C Three level cache C Data buffereing
D All of them D All of them
The most commonly used text code in I/O module via Which of following is the distinguishing
Question keyboard/monitor is the ........... Question characteristics of RAM memory?
A ASCII (7 bit) A Volatile
B EBCDIC (8 bit) B Non-volatile
C IRA (7 or 8 bit) C Both A and B
Which of following is the distinguishing characteristics How is reading and writing operations are
Question of RAM memory? Question accomplished in RAM memory?
To read the data from and to write data into memory Through use of electromagnetic signals
A easily A
To read the data from and to write data into memory Through use of electrical signals
B rapidly B
When an update action performed on shared cache line, What is function of tranducer?
Question it must be announced to all other caches Question
by..................mechanism.
Unicast Converts data from electrical to other
A A forms of energy during output
Multicast Converts from other forms of signal to
B B electrical during input
C Broadcast C Both A and B
Which of following is valid option for functions of The basic unit of exchange in I/O module
Question status signal? Question via keyboard/monitor is the ...........
Report status, or perform some control function String
A perticular to the device A
B State of the device B Byte
C Both A and B C Character
DRAM is made with cells that stores data in the form of Which of following are characteristics of
Question ..................... Question RAM memory?
Charge on capacitors Must be provided with a constant power
A A supply
Flip-flops If power supply is interrupted, then the
B B data is going to be lost
C Both A and B C It can be used only as temporary storage
Which of following is not valid option for functions of Which of following approaches to snoopy
Question control signal? Question protocol have been explored?
A Send data to the I/O module (Input or Read) A Write-invalidate
B Accept data from the I/O module (output or Write) B Write-update
Report status, or perform some control function Both A and B
C perticular to the device C
D State of the device D None of them
Which of following terminal is used for indicating read For ................., the other terminal
Question or write. Question provides an electrical signal that sets the
state of the cell to 0 or 1.
A Select terminal A Writing
B Control terminal B Reading
C Sense terminal C Both A and B
D Data in terminal D None of these
Snoopy protocol is ideally suited for Which of following options are valid for
Question …..........multiprocessor Question interface to I/O module in the form of.......
A Ring-based A Control signal

B Bus-based B Data signal
C Both A and B C Status signal
D None of them D All of them
Which of following is the option for examples of Which of following terminal is used for
Question nonremovable disk? Question selecting a memory cell for a read or write
operation.
A Floppy disk and ZIP cartridge disk A Select terminal
B Hard disk B Control terminal
C Both A and B C Sense terminal
D None of these D Data in terminal
Which of following are examples of machine-readable For ................., control terminal is used
Question devices? Question for output of the cell's state.
A Magnetic disk & tape systems, sensors and actuators A Writing
B Video display terminals and printers B Reading
The basic element of a semiconductor memoryis called Which of following is the option for
Question as ............... Question examples of removable disk?
A Core A Floppy disk and ZIP cartridge disk
B Memory cell B Hard disk
Which of following are examples of human-readable Which of following statement is valid

Question devices? Question property for memory cell
Magnetic disk & tape systems, sensors and actuators Memory cells are capable of being written
A A into (at least once), to set the set.
Video display terminals and printers Memory cells are capable of being to
B B sence the state
Both A and B Memory cell exibit two stable states,
C C which can be used to represent binary 0
and 1
In earlier computers, the common form of random- In DRAM, the presence of charge in a
access storage for computer main memory employed an capacitor is interpreetd as...........
Question array of dougnut-shaped feromagnetic loops callled Question
as.............
A Cores A Binary 1
B Disk B Binary 0
C Flat C Nil
D None of thses D None of these
Which of following is valid option for I/O module Which of folowing are valid option for
Question functions? Question principal I/O techniques?
Interface to the processor and memory via system bus or Programmed I/O
A central switch A
Interface to on or more peripheral devices by tailored Interrupt I/O
B data link B
C Both A and B C Direct Memory Aceess
Semiconductor types random access memory These ................... involve using the
Question are...............? Question system clock to provide for transfer of
block of data.
A DRAM A DRAM
B SRAM B SRAM
C ROM C Both A and B
D Both A and B D None of these
Each bank is independently able to service memory Featuers of static random access memory
Question …...........or …............ , so that a system with K banks Question are............
can service K request simultaneously.
A Write or read A Faster, less expensive and less dense
B Read or read B Faster, more expensive and less dense
C Read or write C Slower more expensive and less dense
D Write or write D All of above
For WRITE MISS of MESI protocol, processor issues a The number chips can be grouped
signal on bus that means? together to form a memory bank, it is
Question Question possible to organize the memory banks in
a way called as.............
A Write-with-intent-to-modify (WWITM) A Main Memory

B Read-with-intent-to-modify (RWITM) B Interleaved Memory
C Read-with-intent-to-update (RWITU) C Both A and B
D Write-with-intent-to-modify (RWITU) D Only B
When WRITE HIT of MESI protocol occurs on the line In DRAM, the absence of charge in a
Question currently in the local cache, this effect depends on Question capacitor is interpreetd as...........
the..................... of that line in the local cache.
A Nest state A Binary 1
B Previous state B Binary 0
C Current state C Nil
When a READ MISS of MESI protocol occurs in the Which of following scheme needed to
local cache, …............ a memory read to read a line of maintain data integrity across both levels
Question main memory containing the missing address. Question of cache and all the caches in SMP
configuration.
A Processor-initiated A MESI protocol

B Bus-initiated B L1-L2 Cache consistency
C Only A C Both A and B
Question What are the kinds of DRAM? Question What is memory segmentation?
Synchronous DRAM This is one of the memory addressing
A A technique
RamBus DRAM This is one of the memory addressing
B B technique in which memory is subdivided
If the L1 cache has a write-back policy, the relationship Dynamic RAM require ...................
Question between the caches are ….….... Question charge refreshing to maintain data
storage.
A More complex A Aperiodic
B Less complex B Periodic
C NO complex C Both A and B
To provide cache consistency on …......, the data cache The presentation of separate state diagram
Question supports a protocol called as MESI protocol. Question for MESI protocol can be …............
A SMP A Processor-initiated
B NUMA B Bus-initiated
C Both A and B C Only A
D None of them D Both A and B
Write-invalidate approach is most widely used in Data are recorded on and later retrieved
Question commercially multiprocessor like.......... Question from the disk via conducting coil named
as...............
A Pentium 4 A Data
B PowerPC B Head
C Both A and B C Plotter
With Write-update snoopy protocol, there can What are features memory segmentation?
Question be.........writers as well as…......readers. Question
One, multiple Allows programmers to view memory as
A A consisting of multiple address spaces
Multiple, multiple Allows programmers to view memory as
B B segment
C Multiple, only one C Both A and B
With Write-invalidate protocol, there can ............. memory is used for cache
Question be.........readers but …......writer at time. Question memory.
A One, multiple A DRAM
B Multiple, one B SRAM
C Multiple, only one C ROM
............. memory is used for main memory. ..................... techniques are commonly
Question Question used in the memory systems.
A DRAM A Error detection
B SRAM B Error correction
C ROM C Fault tolerance
Question Memory segments may be................? Question Memory segments are of ......................?
A Program segments A Variable
B Data segments B Dynamic
C Both A and B C size
D None of these D All of above
Why do advanced DRAM organization have been Which of the following is size that floppy
Question introduced? Question disk can store?
To copensate for relatively high speed of DRAM 1.00 MB
A memory A
To copensate for relatively slow speed of DRAM 1.40 MB
B memory B
To copensate for relatively average speed of DRAM 1.44 MB
C memory C
D None of these D 2.00 MB
Charasteristics of SRAM and DRAM is the.................. In DRAM .......... is needed to retain data.
Question Question
A Volatile A No refresh
B Non-volatile B Refresh
C Both A and B C Calculation
............ will hold its data as long as power supplied to In SRAM memory, binary values are
Question cell Question stored using .....................
A DRAM A Charge on capacitors
B SRAM B Flip-flops
C ROM C Both A and B
DRAM is ............. device In compact disk, the begining or end of a

pit represents as .............. ; when no
Question Question change in elevation occurs between
intervals is reprented as .............
A Digital A Digital 1 and digital 0

B Analog B Digital 0 and digital 1
C Both A and B C Digital 1 and digital 1
D None of these D Digital 0 and digital 0
DRAM is ............. device The compact disk is a nonerasable disk

Question Question that can store more than ............ of audio
information on one side.
A Digital A 10 Minutes
B Analog B 20 Minutes
C Both A and B C 50 Minutes
D None of these D 60 Minutes
For write operation of DRAM, a voltage signal is The data capacity of compact disk (CD) is
Question applied to the bit line; a high voltage represents...... and Question about................
a low voltage represents.......
A 0 and 0 A 600 MB
B 0 and 1 B 650 MB
C 1 and 0 C 680 MB
D 1 and 1 D 750 MB
Question ROM means........................................ Question A ROM memory is ........................

A Temporary pattern of data that cannot be changed A Volatile
B Temporary pattern of data that can be changed B Nonvolatile
C Permanent pattern of data that cannot be changed C Both A and B
D Permanent pattern of data that can be changed D None of these
DRAM require supporting.......................circuitory. Which of following is option for

Question Question disadvantage CD-ROM?
A Refreshing A It is read only
B Norefreshing B It can not be updated
All refreshing Has access time much larger than that of
C C magnetic disk
D None of these D All of these.
What is miss rate? Which of following is the important

Question Question application of ROM memory?
The fraction of memory accesses found in a highest Mini programming
A level of the memory hierarchy. A
The fraction of memory accesses not found in a highest Macro programming
B level of the memory hierarchy. B
C Both A and B C Micro programming
The length of a cache line, not including tag and control Which of the following is not valid option
Question bits, is called as.............. Question for read-mostly memory?
A Cache line A EPROM
B Line size B EEPROM
C Both A and B C PROM
D None of these D Flash memory
Question Virtual memory means? Question The concept of page means ?

Main memory can act as a cache for the secondary A cache memory block
A storage A
B Implemented with magnetic disks B A virtual memory block
C Both A and B C A physical memory block
Which of the following statement is valid for EPROM The concept of page fault means?
Question memory? Question
A Read and written electrically A Cache memory miss
B Before write operation, all storage cells must be erased B Physical memory miss
C Both A and B C Virtual memory miss
What is RAID? The concept of demand paging

Question Question is......................
Redundant Array of Indiviual Disk To load an part of process into main
A A memory
Redundant Array of Independent Drum To load an entire process into physical
B B memory
Redundant Array of Independent Disk To load an part of process into physical
C C memory
Reluctantant Array of Independent Disk To load an entire process into main
D D memory
Which of following is option for advantage of using The magnetizable coating is applied to
Question constant angular velocity (CAV). Question both sides of platter called as ..................
disk.
Individual blocks of data can not be directly addressed Single sided
A by either track or sector. A
Individual blocks of data can be directly addressed by Double sided
B track and sector. B
Individual blocks of data can be directly addressed by Both A and B
C only sector. C
Individual blocks of data can be directly addressed by None of these
D only track. D
Operating system usually creates the space on disk for Which of following is correct option for
all the pages of a process when it creates the process types of I/O commands that an I/O
Question that space is know as................... Question module may receive when it is addressed
by the processor?
A Free space A Condition, Test, Read and Write

B Swap space B Control, Total, Read and Write
C Both A and B C Control, Test, Read and Write
D None of these D Control, Test, Read and Real
Which of following is correct option for control types of The information can be scanned at the
Question programmed I/O commands Question same rate by rotating disk at fixed speed,
is known as ..................
Used to test various status conditions associtited with an Linear Angular Velocity
A I/O module its peripheral. A
Causes the I/O module to obtain an item of datafrom Constant Angular Velocity
B peripheral and place it in internal buffer. B
Causes the I/O module to take an item of data from the Both A and B
C data bus and subequently trasmit that item to the C
peripheral
D Used to activate a peripheral and tell it what to do. D None of these
With memory mapped I/O, ........... read line

Question and ............write line are needed on the bus. Question
A A single and Many A
B Many and single B
C Many and many C
D A single and single D
Correct Answer D Correct Answer
Which of following is correct option for test types of

Question programmed I/O commands Question
Used to test various status conditions associtited with an
A I/O module its peripheral. A
Causes the I/O module to obtain an item of datafrom
B peripheral and place it in internal buffer. B
Causes the I/O module to take an item of data from the
C data bus and subequently trasmit that item to the C
peripheral
D Used to activate a peripheral and tell it what to do. D
Correct Answer A Correct Answer
Featuers of static random access memory are............ As we know with memory mapped I/O,
there is a single address space for memory
location and I/O devices. So, for example,
with 10 address lines, a combined how
Question Question many total memory locations and I/O
addresses can be supported?
A Faster, less expensive and less dense A 10

B Faster, more expensive and less dense B 20
C Slower more expensive and less dense C 1024
D All of above D 512
What is seek time of disk memory system? Which of following is more complex
Question Question process of TLB (translation-lookaside
buffer)?
A The time it takes to position the head at the track. A TLB hit
The time it takes for begining of sector to reach the TLB miss
B head. B
C The sum of seek time, if any, and rotational dealy C Both A and B
Which of following are valid option for possibilities of What is advantage of memory mapped I/O
Question TLB (Translation-Lookaside Buffer) miss? Question of programmed I/O?
The page is present in memory, and we need only create Less repertoire of instructions can be
A the missing TLB entry A used, allowing more efficient
programming
The page is not present in memory, and we need to Less repertoire of instructions can be
B transfer control to the operating system to deal with a B used, allowing less efficient programming
page fault
Both A and B Large repertoire of instructions can be
C C used, allowing less efficient programming
None of these Large repertoire of instructions can be
D D used, allowing more efficient
programming
Which of following page replacement policy can not be Which of following is correct option for
Question used by virtual memory paging scheme? Question write types of programmed I/O
commands
LRU Used to test various status conditions
A A associtited with an I/O module its
peripheral.
LIFO Causes the I/O module to obtain an item
B B of datafrom peripheral and place it in
internal buffer.
FIFO Causes the I/O module to take an item of
C C data from the data bus and subequently
trasmit that item to the peripheral.
None of these Used to activate a peripheral and tell it
D D what to do.
What is problem of programmed I/O? How does program and data are
Question Question transferred between processor and cache
memory?
The processor has to not wait for a long period of time Slower and in the forms byte
A for I/O module of concern to be ready for either A
reception or transmission of data.
The processor has to not wait for a long period of time Slower and in the forms words
B for I/O module of concern to be not ready for either B
reception or transmission of data.
The processor has to wait a long period of time for I/O Faster and in the forms byte
C module of concern to be not ready for either reception or C
transmission of data.
The processor has to wait a long period of time for I/O Faster and in the forms words
D module of concern to be ready for either reception or D
transmission of data.
What is rotational delay of disk memory system? What is disadvantage of memory mapped
Question Question of programmed I/O?
The time it takes to position the head at the track. Valuable memory address space is used
A A up.
The time it takes for begining of sector to reach the Less valuable memory address space is
B head. B used up.
The sum of seek time, if any, and rotational dealy Least valuable memory address space is
C C used up.
D None of these D None of thses
What is meaning of programmed Input/Output? What is meaning of intrrupt-driven

Question Question Input/Output?
In which I/O occurs under the direct and continuous In which I/O occurs under the direct and
A request of program requesting I/O operation A continuous request of program requesting
I/O operation
In which a program issues an I/O command and then In which a program issues an I/O
continues to execute, until it intrrupted by I/O hardware command and then continues to execute,
B to signal the end of I/O operation B until it intrrupted by I/O hardware to
signal the end of I/O operation
In which a specialized I/O processor takes over control In which a specialized I/O processor takes
C of an I/O operation to move a large block of data C over control of an I/O operation to move a
large block of data
With programmed I/O, there is a close correspondance Which of following statements are correct
between the I/O related instruction that the processor with respect to memory characteristics?
Question fetches from............. and the I/O commands that the Question
processor issues to ..................... to execute the
instructions.
A Memory and an I/O devices A Faster access time, greater cost per bit.
B Processor and an I/O module B Greater capacity, smaller cost per bit.
C Memory and an I/O module C Greater capacity, slower access time.
D Memory and an I/O devices D All of above
What is meaning of TLB (translation-lookaside buffer) Which of following are design issues
Question hit? Question arrises in implementing interrupt I/O?
The physical page number is used to form the address, There will be multiple I/O modules, how
A & the corresponding reference bit is turned on. A does the processor determines which
device issued the interrupt
If the processor is performing a write, the dirty bit is If multiple interrupts have occurred, how
B also B does the processor decide which one to
process
C turned on. C Both A and B
Correct Answer None of these Correct Answer C
C
The I/O module contans logic for performing a Which of following statements belongs to
Question communication function between......... and ............... Question principle of locality of reference?
Processor and bus The basis for the validity of condition of
A A decreasing frequency of access of the
memory by the processor.
Processor and memory The basis for the validity of condition of
B B decreasing cost per bit.
Peripheral and bus The basis for the validity of condition of
C C increasing the capacity of storage
None of these The basis for the validity of condition of
D D increasing the access time
What is meaning of Direct Memory Access? When interrupt is raised, which of

Question Question following the technigues are in use?
In which I/O occurs under the direct and continuous Multiple interrupt lines and software poll
A request of program requesting I/O operation A
In which a program issues an I/O command and then Daisy chain and bus arbistration
B continues to execute, until it intrrupted by I/O hardware B
to signal the end of I/O operation
In which a specialized I/O processor takes over control Both A and B
C of an I/O operation to move a large block of data C

Which of following addressing modes are availabel Which of following statements are
Question when the processor, main memory, an I/O share a Question correct, when virtual address is used?
common bus?
Memory mapped I/O The system designer may choose to place
A A cache between the processor and the
MMU.
Isolated I/O The system designer may choose to place
B B cache between the MMU and the main
memory.
Which of following interrupt identification techniques Which of following interrupt

Question are going to be used which is more efficient and and Question identification techniques that makes use
provides in a effect, a hardware poll? of vectored interrupts ?
A Multiple interrupt lines A Multiple interrupt lines
B Software poll B Software poll
C Daisy chain C Daisy chain
D Bus arbistration D Bus arbistration
Secondary or auxiliary memory are used to store Which of following interrupt

program and data and usually visible to programmer identification techniques are going to be
only in terms of …...... and.......... used when the processor detects and
interrupt , it brances to interrupt-service
Question Question routine whose job is to poll each I/O
module to determine which module cause
the interrupt?
A Bit and byte A Multiple interrupt lines

B Files and records B Software poll
C Bytes or words C Daisy chain
D All of them D Bus arbistration
Which of the following signal is provided in Intel 80386 Which of following are functional
Question with respect to the 82C59 Interrupt controller chip? Question terminals of memory cell for carrying an
electrical signal?
Single Interrupt Request (INTR) Select terminal, control terminal and data
A A in terminal
Singal Interrupt Acnowledgement (INTA) Select terminal, control terminal and
B B sense terminal
Which of following is the disadvantage of write through The starting location of in the memory to
cache write policy read from or write to, communicated
Question Question on .............. and stored by the DMA
module in its ................. register.
It generates substantial memory traffic and may create Data lines and control logic
A traffic A
It not generate substantial memory traffic and may Data lines and Memory buffer
B create traffic B
C Both A and B C Data lines andAdress
D None of them D Data lines and data count
Which of following statement is no valid property for What is Invalid state of MESI protocol?
Question memory cell Question
Memory cell exibit two stable states, which can be used The line in the cache does not contain
A to represent binary 0 and 1 A valid data
Memory cell exibit two semitable states, which can be The line in the cache does contain valid
B used to represent binary 0 & 1 B data
Memory cell exibit two correct states, which can be The line in the cache does available valid
C used to represent binary 0 & 1 C data
Memory cell exibit 2 semitable states, which can be The line in the cache does not available
D used to represent binary 0 & 1 D valid data
Featuers of dynamic random access memory are............ What are the features of ROM memory?
Question Question
A Faster, less expensive and less dense A It is nonvolatile memory
Faster, more expensive and less dense No power supply is required to maintain
B B the bit values in memory
Slower, less expensive and more dense It is possible to read ROM, but it is no
C C possible to write new data into it
D All of above D All of above
Due characteristics of SRAM are faster than DRAM, Which of following is valid
Question SRAM are used for...................... and DRAM are used Question characteristics of PROM?
for.............................
Main memory and cache memory More expensive, nonvolatile and may be
A A written only once
Main memory and Main memory Less expensive, volatile and may be
B B written only once
Cache memory and cache memory Less expensive, nonvolatile and may be
C C written only once
Cache memory and main memory Less expensive, nonvolatile and may be
D D written many times
Which of following is option for drawback programmed With respect to transfer of data, which of
Question I/O and Interrupt-driven I/O? Question following option is valid for programmed
I/O
The I/O transfer rate is limited by the speed with which Frees up the processor to some extent at
A the processor can test and service a device. A the expence of the I/O transfer rate.
The processor is tied up in managing an I/O transfer; a The processor is dedicated to the task of
B number of instruction must be executed for each I/O B I/O can move data at a rather high rate, at
transfer. the cost of doing nothing else.
D None of These D None of these
The DRAM cell's are .........densed and ...... expensive When a read or write is requested, using
Question than corresponding SRAM Question reador write control line
between................. and .....................
A Less and less A DMA module and processor
B Less and more B Processor and DMA module
C More and less C Address register and DMA module
D More and more D None of these
When large volume of data are to be moved, which of With respect to transfer of data, which of
Question the following techniques is more efficient? Question following option is valid for Interrupt-
driven I/O
Programmed I/O Frees up the processor to some extent at
A A the expence of the I/O transfer rate.
Interrupt-driven I/O The processor is dedicated to the task of
B B I/O can move data at a rather high rate, at
the cost of doing nothing else.
C Direct memory access C Both A and B
For read operation of DRAM, when the address line is The size of cell's in DRAM are
selected, the transitor turns ...... and charge stored on ..............and ............ than SRAM.
Question the ................ is fed out onto a bit line and to a sence Question
amplifier.
A Off and register A Coplex and Smaller

B On and capacitor B Simpler and smaller
C On and transistor C Simpler and larger
D None of these D Complex and larger
In DRAM memory, what does dynamic indicate? The number of words to be read or
written, again communicated
Question Question via .................. and stored in the
...........register.
Tendancy of the stored charge to leak in, even with Data lines and control logic
A power continuously applied. A
Tendancy of the stored charge to leak away, even with Data lines and Memory buffer
B power continuously applied. B
Tendancy of the stored charge to leak away, even no Data lines andAdress
C power supply applied. C
D None of these D Data lines and data count
Which of following is first step in the programmed I/O How an I/O related instruction are
Question techniques ? Question executed by the processor?
Firstly, it view from point of view of the I/O instructions The processor issues an address,
A executed by the processor A specifying the particular external device,
I/O module and I/O command
Firstly, it view from point of view of the I/O command The processor issues an address,
B issued by the processor to I/O module B specifying the particular I/O command,
external device and I/O module
Both A and B The processor issues an address,
C C specifying the particular I/O module,
external device and I/O command
How does program and block are transferred between
cache and main memory? How many total bits are required for a direct-
mapped cache with 16 KB of data
Question Question and 4-word blocks, assuming a 32-bit
address?
A Slower and in the forms words A 149 Mbit

B Slower and in the forms blocks B 148 Mbit
C Faster and in the forms words C 147 Kbit
D Faster and in the forms blocks D 174 Kbit
With programmed I/O, the ................... will perform the When the DMA module needs to use the
Question requested action and then set the appropriate bits in the Question system buses to transfer data, it sends a
I/O................. signal called .............. to the processor.
A I/O module and control register A HLDA
B I/O module and status register B HOLD
In virtual memory, we locate pages by using a table that Which of following statement is valid for
Question indexes the memory; this structure is Question translation-lookaside buffer (TLB)
called................and it resides in memory.
Page fault A cache that keeps track of recently used
A A address mappings to try to avoid an
access to the page table.
Page Table Main memory that keeps track of recently
B B used address mappings to try to avoid an
access to the page table.
What is concept of read-mostly memory? In virtaul memory, the virtual address is
Question Question broken into.........and ............
Read operation are far more frequent than write but on Physical page number and nopage offset
A nonvolatile storage A
Read operation are less frequent than write but on Physical page number and page offset
B nonvolatile storage B
Read operation are far more frequent than write but on Virtual page number and page offset
C volatile storage C
Read operation are less frequent than write but on Virtual page number and nopage offset
D volatile storage D
Which of the following is valid option for steps of the The 8237 has a set ......... set
control of transfer of data from an external device to the control/command registers to program
Question processor? Question and control DMA operation over ........ of
its channels.
A The I/O module returns the device status A Five and One
B The I/O module obtains a unit of data B One and Five
Data are transferred from I/O the module to the Both A and B
C processor C
What are two important characteristic of memory from There is a trade-off among, Which of
Question User's points of view? Question following three characteristics of
computer memory?
Location and Capacity Performance, Unit of transfer and
A A Capacity
B Performance and Unit of Transfer B Performance, Capacity and cost
C Access method and Unit of Transfer C Capacity, Access time and Performance
D Capacity and Performance D Capacity, Access time and Cost
Which of following is the option for outbound storage? How does cache Read operation
Question Question performed?
Main Memory, Processor Registers and Cache Memory Processor generates Read Address of
word, if the word is contained in the
A A cache, then it is delivered to the processor.
Processor Registers, Cache Memory, Magnetic Disk and If the required word is not contained in
Magnetic Tape the cache, then the block containing that
B B word is loaded into the cache and then
word is delivered to the processor.
C Magnetic Disk, DVD-RW, CD-ROM, and CD-RW C Both A and B

Magnetic Tape, Processor Registers, DVD-RW and None of these
D Main Memory D
Which of following statements improves the Which are states are there for MESI
Question performance and achieves zero-wait state transaction? Question protocol?
A L1 cache is off-chip and L2 cache on-chip. A Modified, Exclusive, Single and Invalid
L1 cache is off-chip and L2 cache off-chip. Modified, Exclusive-OR, Shared and
B B Invalid
L1 cache is on-chip and L2 cache off-chip. Modelled and Exclusive-OR, Shared and
C C Invalid
D L1 cache is on-chip and L2 cache external. D Modified, Exclusive, Shared and Invalid
Which of following is the option for inbound memory?

What is address length in all three types
cache mapping techniques?
(Where – w bits identify unique word or
Question Question byte within a block of main memory,
s bits specify one of 2^s blocks
of main memory)
Processor Registers, Cache Memory, Magnetic Disk and (s+w) bits

A Magnetic Tape A
Magnetic Disk and Magnetic Tape, CD-ROM, and CD- (s-w) bits
B RW B
Magnetic Tape, Processor Registers, DVD-RW and (s+w) bytes
C Main Memory C
Main Memory, Processor Registers and Cache Memory (s-w) bytes
D D
What are number of blocks in main

memory in all three types cache mapping
What is block size in all three types cache mapping techniques?
Question techniques? Question (Where – w - bits identify unique word or
(Where – w bits identify unique word or byte within a byte within a block of main memory,
block of main memory, s - bits specify one of 2^s
s bits specify one of 2^s blocks of main blocks of main memory
memory) r- bits specify line in cache )
A Line size = 2^w words or bytes A 2^w

B Line size = 2^r words or bytes B 2^s
C Line size = 2^s words or bytes C 2^r
What is the size of tag in associative cache mapping What is the size of tag in direct cache
techniques? mapping techniques?
(Where – w - bits identify unique word or byte within a (Where – w - bits identify unique word or
Question block of main memory, Question byte within a block of main memory,
s - bits specify one of 2^s blocks of main s - bits specify one of 2^s
memory blocks of main memory
r- bits specify line in cache ) r- bits specify line in cache )
A (s-r) bits A (s-r) bits

B s bits B s bits
C (s-d) C (s-d)
D None of them D None of them
What is the size of cache in all three types

What is number of addressable units in all three types cache mapping techniques?
cache mapping techniques? (Where – w - bits identify unique word or
Question (Where – w bits identify unique word or byte within a Question byte within a block of main memory,
block of main memory, s - bits specify one of 2^s
s bits specify one of 2^s blocks of main blocks of main memory
memory) r- bits specify line in cache )
A 2^(s+w) words or bytes A 2^(r+w) words or bytes

B 2^(s-w) words or bytes B 2^(r-w) words or bytes
C 2^(s+w) bit C 2^(r+w) bit
D 2^(s+w) blocks D 2^(r+w) blocks
What is Modified state of MESI protocol?
What are number of line in cache in all three

types cache mapping techniques?
Question Question (Where – w - bits identify unique word or
byte within a block of main memory,
s - bits specify one of 2^s blocks of
main memory
r- bits specify line in cache )
The line in cache has been not modified and available 2^w
A all cache A
The line in cache has been not modified and available 2^s
B only in this cache B
The line in cache has been modified and available only 2^r
C in this cache C
The line in cache has been modified and available all None of them
D cache D
Question What is Exclusive state of MESI protocol? Question What is Shared state of MESI protocol?
The line in cache is the other as that in main memory The line in cache is the other as that in
A and is not present in other cache A main memory and may be present in
another cache
The line in cache is the same as that in main memory The line in cache is the same as that in
B and is not present in other cache B main memory and may be not present in
another cache
The line in cache is the same as that in main memory The line in cache is the other as that in
C and is present in other cache C main memory and may be present in
another cache
The line in cache is the same as that in main memory The line in cache is the same as that in
D and is available in other cache D main memory and may be present in
another cache
Which of the following is the possible outcomes of Which of the following is the possible
Question READ MISS of MESI protocol? Question outcomes of READ MISS of MESI
protocol?
If one other cache has a clean copy of the line in the If one or other cache has a modified copy
exclusive state, it returns a signal indicating that it of the line, then that cache blocks memory
A shares this line. A read and provides the line to the
requesting cache over shared bus.
If one cache has a clean copy of the line in the exclusive If one or other cache has a modified copy
state, it returns a signal indicating that it shares this line. of the line, then that cache blocks memory
B B write and provides the line to the
requesting cache over shared bus.

Which of the following is the possible outcomes of Which of the following is the possible
Question READ MISS of MESI protocol? Question outcomes of READ MISS of MESI
protocol?
If one or more cache have clean copy of line in the If no other cache has a copy of line, then
A exclusive state, each of them signals that it shares the A no signals are returned.
line.
If one or more cache have clean copy of line in the If no other cache has a copy of line, then
B shared state, each of them signals that it shares the line. B signals are returned.
When a READ HIT of MESI protocol occurs on line When a WRITE MISS of MESI protocol
currently in the local cache, processor simply reads the occurs in the local cache.................... a
Question required item, why? Question memory read to read the line of main
memory containing the missing address.
A There is no state change A Processor-initiated

B The state remains modified-shared or exclusive B Bus-initiated
What is use of Exclusive state of WRITE HIT of MESI What is use of Modify state of WRITE
Question protocol? Question HIT of MESI protocol?
The processor already has exclusive control of this line, The processor has already has exclusive
and so it simply perform the update and transitions its control of this line and has the line
A copy of the line from exclusive to modified. A marked as modified, and so it simply
performs the update.
The processor already has shared control of this line, The processor has already has shared
B copy of the line from exclusive to modified. B marked as modified, and so it simply
The processor already has shared control of this line, The processor has already has exclusive
C copy of the line from shared to modified. C marked as update, and so it simply
What is use of Shared state of WRITE HIT of MESI What is disadvantage of programmed I/O
Question protocol? Question technique?
Before performing the update, the processor gain It is not time consuming process that
A exclusive ownership of the line. A keeps processor busy needlessly.
Before performing the update, the processor gain shared It is time consuming process that keeps
B ownership of the line. B processor idle needlessly.
Before performing the delete, the processor gain It is time consuming process that keeps
C exclusive ownership of the line. C processor busy needlessly.
None of these It is not time consuming process that
D D keeps processor idle needlessly.
UNIT I and UNIT II
1. In Booth’s non-restoring division algorithm, after performing left shift operation on A, Q

registers, if magnitude of A < 0 then?
a. Q0=0, A=A+M
b. A=A+M
c. Q0=1
d. A=A-M
2. In Booth’s bit-pair recoding, what version of multiplicand will be selected if consecutive
multiplier bits are 011?
a. 0*M
b. 1*M
c. -1*M
d. +2*M
3. What will be the result of Booth’s bit-pair recoding operation on this multiplier 111010?
a. 0-1-2
b. 0+2-1
c. 0+1+2
d. 0-10
4. In Booth’s restoring division algorithm, after performing operations (1) left shift operation on
A,Q and (2) A=A-M, if MSB of A is 0?
a. Q0=0, A=A+M
b. A=A+M
c. Q0=1
d. A=A-M
5. In Booth’s non restoring division algorithm, for Dividend=10000 and Divisor=100. How many
numbers of cycles are required to get the correct division result
a. 4
b. 5
c. 3
d. 6
6. In Booth's algorithm, if Multiplicand = +22 and Multiplier = -5, what is content of A, Q and Q-1
register after third cycle?
a. A=001000, Q=010111, Q-1=0
b. A=111001, Q=010111, Q-1=0
c. A=000001, Q=010111, Q-1=1
d. A=001000, Q=010111, Q-1=1
7. In Booth's algorithm, if Multiplicand = +15 and Multiplier = -6, what is content of A, Q and Q-1
register after fourth cycle?
a. A=11010, Q=01101, Q-1=0
b. A=11010, Q=01101, Q-1=1
c. A=11010, Q=11010, Q-1=1
d. A=10100, Q=11010, Q-1=1
8. In restoring division algorithm, if Dividend = 1010 and Divisor = 0011, what is content of A and Q
register after third cycle ?
a. A=10001, Q=0001
b. A=00010, Q=0011
c. A=00010, Q=0001
d. A=01001, Q=0101
9. In restoring division algorithm, if Dividend = 17 and Divisor = 03, what is content of A and Q
register after fourth cycle ?
a. A=111111, Q=10010
b. A=000010, Q=10010
c. A=000011, Q=00010
d. A=101001, Q=00101
10. In non-restoring division algorithm, if Dividend = 1100 and Divisor = 0011, what is content of A
and Q register after third cycle ?
a. A=11101, Q=0010
b. A=00001, Q=0010
c. A=00010, Q=0001
d. A=00000, Q=0011
11. In non-restoring division algorithm, if Dividend = 1011 and Divisor = 0101, what is content of A
and Q register after fourth cycle ?
a. A=11100, Q=0010
b. A=00001, Q=0010
c. A=00000, Q=0010
d. None of these
12. What will be the result of Booth recoding operation on 0011110?
a. 0+1000-10
b. 0+1000+10
c. 0+10000
d. 0-1000-10
a. 0*M
b. +1*M
c. -1*M
d. +2*M
14. n Booth’s bit-pair recoding, what version of multiplicand will be selected if consecutive
a. 0*M
b. +1*M
c. -1*M
d. +2*M
a. 0*M
b. +1*M
c. +2*M
d. -2*M
a. 0*M
b. +1*M
c. -1*M
d. +2*M
a. 0*M
b. +1*M
c. -1*M
d. +2*M
a. 0-1-2
b. 0+2-1
c. 1-2
d. 0-1-0
a. 0-1-2
b. 0+2-1
c. 12
d. 0-10
20. Calculate the CPU time of the system having CPI 1.43, clock rate 100MHz, and instruciton count
of 7*106 ?
a. 0.01sec
b. 0.1sec
c. 0.02sec
d. 0.2sec
21. Calculate the CPU time of the system having CPI 1.25, clock rate 100 MHz, and instruciton count
of 12*106 ?
a. 0.12sec
b. 0.125sec
c. 0.15sec
d. 0.2sec
22. Calculate the CPU time of the system having CPI 1.25, clock rate 100 MHz, and instruciton count
of 12millions ?
a. 0.12sec
b. 0.125sec
c. 0.15sec
d. 0.2sec
23. Calculate the CPU time of the system having CPI 1.43, clock rate 100MHz, and instruciton count
of 7 millions?
a. 0.01sec
b. 0.1sec
c. 0.02sec
d. 0.2sec
24. Calculate the CPI of the system having CPU time of 0.1sec, clock rate 100MHz, and instruciton
count of 7 millions?
a. 1
b. 1.1
c. 1.43
d. 1.7
25. Calculate the CPI of the system having CPU time of 0.1sec, clock rate 100MHz, and instruciton
count of 7*106 ?
a. 1
b. 1.1
c. 1.43
d. 1.7
-------
26. Which is the fastest memory in computer system?
a. Registers
b. RAM
c. ROM
d. Cache
27. What are the basic components of the CPU?
a. Registers
b. ALU
c. Control Unit
d. All of these
28. Which registers shows the status of the CPU?
a. Status /Flag Register
b. General Purpose Register
c. Special Purpose Register
d. Stack
29. What is mean by op-code?
a. Operation code
b. Output code
c. Organized code
d. Optional code
30. What are the sources of the operand?
a. Main memory
b. CPU registers and I/O devices
c. CPU register and ALU
d. Both 1 and 2
31. What is the correct sequence of execution of an instruction?
a. Decode-Fetch-Execute
b. Execute-Fetch-Decode
c. Fetch-Decode-Execute
d. None of these
32. What is the function of data movement instructions?
a. Processing of data
b. Movement of data
c. Mange the program flow control
d. Both 1 and 2
33. What is the function of data processing instructions?
a. Processing of data
b. Movement of data
c. Mange the program flow control
d. Both 1 and 2
34. Which instruction has one of the operand as an accumulator?
a. 1 address
b. 2 address
c. 3 address
d. 0 address
35. Which instruction has all implicit addresses?
a. 1 address
b. 2 address
c. 3 address
d. 0 address
36. How many addresses do the stack related instructions use?
a. 1 address
b. 2 address
c. 3 address
d. 0 address
37. Which of the following is a memory addressing mode?
a. Register addressing
b. Direct addressing
c. In-direct addressing
d. Both b and c
38. Which of the following is a fastest addressing mode?
c. Immediate addressing
d. None of these
39. In which of the following addressing modes one of the operand is data?
c. Immediate addressing
d. None of these
40. The instruction that are used to move the data among CPU registers are in the group of
a. Data Transfer Instruction
b. Logical Instrcution
c. Control Transfer Instruction
d. None of these
41. How many memory reference are required to fetch single indirection instuction ?
a. 1
b. 2
c. 3
d. 0
42. Next instruction reference is
a. explicitly in instruction
b. implicitly in instruction
c. Both a and b alternatively
d. Completely
43. The operation of the CPU is determined by the instruction it exectutes, referred to as
a. Computer instruction
b. Machine instruction
c. Next instruction
d. Both a and b
44. In instuction cycle state diagram, which is next step after instruction/ operation decoding?
a. Date operation
b. Operatnd fetch
c. Operand address calculation
d. Instruction address calculation
45. In instuction cycle state diagram, which is next step after instruciton address calculation?
a. Date operation
b. Instruction fetch
c. Operand address calculation
d. Instruction address calculation
46. In case of which instruction, system discard the next consecutive instruction?
a. Interupt
b. Branch
c. Jump
d. All of these
47. The ALU is that part of computer that actually performs arithmetic and logical operation on …..
a. Instructions
b. Data
c. Both data and instruction
d. None of these
48. Each instruction is represented by
a. Operand
b. Opcode
d. Sequence of bits
49. Logical instructions operate on,
a. Numeric data
b. Bits of word
c. Character data
d. Both numeric and character data
50. Branch instruction are used,
a. Branch to same set of instruction depending on addition
b. Branch to a different set of instructions depending on the decision made
c. Branch to different set of data based on decsion made
d. None of these
51. In case of one address instructions, which register is used as second operand ?
a. IR
b. AC
c. MQ
d. MBR
52. Which of the following is fastest instructi on?
a. Three Address
b. Two Address
c. One Address
d. None of these
53. Which of the following is slowest instruciton?
a. Three Address
b. Two Address
c. One Address
d. None of these
54. Which kind of instructions are widely used?
a. Three Address
b. Two Address
c. One Address
d. None of these
55. Which kind of instructions uses stack as memory?
a. Three Address
b. Two Address
c. One Address
d. None of these
56. Which is common representation for representing character data?
a. ASCII
b. EBCDIC
c. Unicode
d. All of these
57. PUSH and POP are,
a. Arithmetic operations
b. Data transfer operations
c. Logical operations
d. Transfer of control
58. Set and Reset are,
59. Test is,
60. Halt is,
61. Which kind of operations are performed in privileged state?
a. Input/ Output
b. Transfer of control
c. System control
d. All of these
62. In case of branch instructions,
a. One of its operands is the address of the next instructions.
b. One of its operand is AC
c. One of its operand is numeric
d. One of its operand in NULL
63. Procedure call instructions uses which type of memory
a. Stack memory
b. Sequential memory
d. None of these
64. Which kind of addressing mode do not require any memory reference?
a. Immediate
b. Register
c. Both a and b
d. Register indirect
65. Which kind of addressing mode do not require any memory reference?
a. Immediate
b. Register
c. Stack
d. All of these
66. Which kind of displacement based addressing uses PC as register?
a. PC addressing
b. Relative Addressing
c. Base register
d. Index
67. Incrementation operation uses which kind of displacement based addressing?
a. Base addressing
b. Index
c. Relative addressing
d. All of these
68. The CPU reads an instruction from memory is,
a. Decode operation
b. Fetch operation
c. Fetch data
d. Write data
69. Which registers helps to minimize the main memory references?
a. User-visible registers
b. Control registers
c. Status registers
d. Invisible registers
70. Which registers are partially visible to the programmer?
a. Address
b. Data
c. Stack pointer
d. Condition codes
71. Indirect cycle take place in case of which addressing modes?
a. Indirect
b. Relative addressing
c. Post indexing
d. All of these
72. Which of the following is correct sequence in case of indirect instructions?
a. Fetch-Decode-Execute
b. Fetch-Decode-Execute-Indirect
c. Fetch-Indirect-Decode-Execute
d. None of these
73. Contents of which register is used to fetch an instruction?
a. IR
b. PC
c. MAR
d. MBR
74. Which register stores the output of fetch cycle?
a. IR
b. PC
c. MAR
d. MBR
75. During which cycle contents of the PC must be saved to memory?
a. Fetch
b. Decode
c. Interrupt
d. Execute
76. Which of the following cycle calculate the effective address of each source operand?
a. Fetch operand
b. Decode operand
c. Calculate operand
d. Write operand
77. The PC will be updated. If there is,
a. Unconditional Branch
b. Conditional Branch
c. Interrupt
d. All of these
78. After updating PC, system should
a. Fetch instruction
b. Empty pipe and fetch instruction
c. Empty pipe
d. None of these
79. Machine cycle is,
a. Time taken to fetch operand.
b. Time taken to fetch operand and performa ALU operations.
c. Time taken to fetch operand, perform ALU operations and stores result in a registers.
d. None of these
80. The length of program is smaller in case of ,
a. CISC
b. RISC
c. Both of these
d. None of these
81. Which kind of architecture uses simpler addressing modes?
a. CISC
b. RISC
c. Both of these
d. None of these
82. Which kind of architecture uses simpler addressing modes?
a. CISC
b. RISC
c. Both of these
d. None of these
83. Which kind of architecture uses complex addressing modes?
a. CISC
b. RISC
c. Both of these
d. None of these
84. Which kind of architecture uses simpler instruction format?
a. CISC
b. RISC
c. Both of these
d. None of these
85. Which kind of architecture uses complex instruction format?
a. CISC
b. RISC
c. Both of these
d. None of these
86. How many registers are supported in case of MIPS?
a. 30
b. 31
c. 32
d. 33
87. What is size of cache in case of MIPS?
a. 124bytes
b. 128MB
c. 128Kbytes
d. 128kbits
88. MIPS R4000 support,
a. IEEE single precision format
b. IEEE dobule precision format
c. Both a and b
d. None of these
89. Which is first commercially available RISC processor?
a. MIPS
b. MPPS
c. VAX
d. MPIS
11/5/2020 coa.html
Computer Organization Questions and Answers –

Functional Units of a Computer
Next »
This set of Computer Organization Assessment Questions and Answers focuses on “Functional Units of a
Computer”.
1. The ______ format is usually used to store data.

a) BCD
R
b) Decimal
c) Hexadecimal
d) Octal
A
View Answer
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2. The 8-bit encoding format used to store data in a computer is ______

a) ASCII
b) EBCDIC
c) ANCI
d) USCII
View Answer
3. A source program is usually in _______

a) Assembly language
b) Machine level language
c) High-level language
d) Natural language
View Answer
4. Which memory device is generally made of semiconductors?

a) RAM
b) Hard-disk
c) Floppy disk
d) Cd disk
View Answer
5. The small extremely fast, RAM’s are called as _______

a) Cache
b) Heaps
c) Accumulators
d) Stacks
View Answer
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6. The ALU makes use of _______ to store the intermediate results.

a) Accumulators
Created by ASHUTOSH
b) Registers
c) Heap
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d) Stack
View Answer
7. The control unit controls other units by generating ___________

a) Control signals
b) Timing signals
c) Transfer signals
d) Command Signals
View Answer
8. ______ are numbers and encoded characters, generally used as operands.

a) Input
b) Data
R
c) Information
d) Stored Values
A
View Answer
9. The Input devices can send information to the processor.

a) When the SIN status lag is set
b) When the data arrives regardless of the SIN lag
c) Neither of the cases
d) Either of the cases
View Answer
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10. ______ bus structure is usually used to connect I/O devices.

a) Single bus
b) Multiple bus
c) Star bus
d) Rambus
View Answer
11. The I/O interface required to connect the I/O device to the bus consists of ______
a) Address decoder and registers
b) Control circuits
c) Address decoder, registers and Control circuits
d) Only Control circuits
View Answer
12. To reduce the memory access time we generally make use of ______
a) Heaps
b) Higher capacity RAM’s
c) SDRAM’s
d) Cache’s
View Answer
13. ______ is generally used to increase the apparent size of physical memory.
a) Secondary memory
b) Virtual memory
c) Hard-disk
d) Disks
View Answer
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14. MFC stands for ___________

a) Memory Format Caches
b) Memory Function Complete
c) Memory Find Command
d) Mass Format Command
View Answer
15. The time delay between two successive initiations of memory operation _______
a) Memory access time
b) Memory search time
c) Memory cycle time
R
d) Instruction delay
View Answer
A
Sanfoundry Global Education & Learning Series – Computer Organization and Architecture.
To practice all areas of Computer Organization Assessment Questions, here is complete set on 1000+
Multiple Choice Questions and Answers on Computer Organization and Architecture.
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Basic Operational Concept
« Prev Next »
R
This set of Computer Organization and Architecture Multiple Choice Questions & Answers (MCQs)
focuses on “Basic Operational Concept”.
A
1. The decoded instruction is stored in ______
a) IR
b) PC
c) Registers
d) MDR
View Answer
Answer: a
Explanation: The instruction after obtained from the PC, is decoded and operands are fetched and stored
in the IR.
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2. The instruction -> Add LOCA, R0 does _______

a) Adds the value of LOCA to R0 and stores in the temp register
b) Adds the value of R0 to the address of LOCA
c) Adds the values of both LOCA and R0 and stores it in R0
d) Adds the value of LOCA with a value in accumulator and stores it in R0
View Answer
Answer: c
Explanation: None.
3. Which registers can interact with the secondary storage?

a) MAR
b) PC
c) IR
d) R0
View Answer
Answer: a
Explanation: MAR can interact with secondary storage in order to fetch data from it.
4. During the execution of a program which gets initialized irst?

a) MDR
b) IR
c) PC
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d) MAR
View Answer
Answer: c
Explanation: For the execution of a process irst the instruction is placed in the PC.
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5. Which of the register/s of the processor is/are connected to Memory Bus?

a) PC
b) MAR
c) IR
d) Both PC and MAR
View Answer
R
Answer: b
A
Explanation: MAR is connected to the memory BUS in order to access the memory.
6. ISP stands for _________

a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure
View Answer
Answer: a
Explanation: None.
7. The internal components of the processor are connected by _______

a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Rambus
View Answer
Answer: b
Explanation: The processor BUS is used to connect the various parts in order to provide a direct
connection to the CPU.
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8. ______ is used to choose between incrementing the PC or performing ALU operations.

a) Conditional codes
b) Multiplexer
c) Control unit
d) None of the mentioned
View Answer
Answer: b
Explanation: The multiplexer circuit is used to choose between the two as it can give different results
based on the input.
9. The registers, ALU and the interconnection between them are collectively called as _____
a) process route
b) information trail
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c) information path
d) data path
View Answer
Answer: d
Explanation: The Operational and processing part of the CPU are collectively called as a data path.
10. _______ is used to store data in registers.

a) D lip lop
b) JK lip lop
c) RS lip lop
View Answer
R
Answer: a
A
Explanation: None.
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Choice Questions and Answers on Computer Organization and Architecture.

« Prev - Computer Organization Questions and Answers – Functional Units of a Computer
» Next - Computer Organization Questions and Answers – BUS Structure
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BUS Structure
R
« Prev Next »
A
focuses on “BUS Structure”.
1. The main virtue for using single Bus structure is ____________

a) Fast data transfers
b) Cost effective connectivity and speed
c) Cost effective connectivity and ease of attaching peripheral devices
View Answer
Answer: c
Explanation: By using a single BUS structure we can minimize the amount of hardware (wire) required
and thereby reducing the cost.
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2. ______ are used to overcome the difference in data transfer speeds of various devices.
a) Speed enhancing circuitory
b) Bridge circuits
c) Multiple Buses
d) Buffer registers
View Answer
Answer: d
Explanation: By using Buffer registers, the processor sends the data to the I/O device at the processor
speed and the data gets stored in the buffer. After that the data gets sent to or from the buffer to the
devices at the device speed.
3. To extend the connectivity of the processor bus we use ________

a) PCI bus
b) SCSI bus
c) Controllers
d) Multiple bus
View Answer
Answer: a
Explanation: PCI BUS is used to connect other peripheral devices that require a direct connection with
the processor.
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4. IBM developed a bus standard for their line of computers ‘PC AT’ called _____
a) IB bus
b) M-bus
c) ISA
View Answer
Answer: c
Explanation: None.
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5. The bus used to connect the monitor to the CPU is ______

a) PCI bus
R
b) SCSI bus
c) Memory bus
A
d) Rambus
View Answer
Answer: b
Explanation: SCSI BUS is usually used to connect video devices to the processor.
6. ANSI stands for __________

a) American National Standards Institute
b) American National Standard Interface
c) American Network Standard Interfacing
d) American Network Security Interrupt
View Answer
Answer: a
Explanation: None.
7. _____ register Connected to the Processor bus is a single-way transfer capable.

a) PC
b) IR
c) Temp
d) Z
View Answer
Answer: d
Explanation: The Z register is a special register which can interact with the processor BUS only.
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8. In multiple Bus organisation, the registers are collectively placed and referred as ______
a) Set registers
b) Register ile
c) Register Block
d) Map registers
View Answer
Answer: b
Explanation: None.
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9. The main advantage of multiple bus organisation over a single bus is _____
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
View Answer
Answer: a
Explanation: None.
10. The ISA standard Buses are used to connect ___________

a) RAM and processor
b) GPU and processor
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c) Harddisk and Processor
d) CD/DVD drives and Processor
A
View Answer
Answer: c
Explanation: None.
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Performance of a System
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« Prev Next »
focuses on “Performance of a System”.
1. During the execution of the instructions, a copy of the instructions is placed in the ______
a) Register
b) RAM
c) System heap
d) Cache
View Answer
Answer: d
Explanation: None.
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2. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can
execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the
execution of the same instruction which processor is faster?
a) A
b) B
c) Both take the same time
d) Insuf icient information
View Answer
Answer: a
Explanation: The performance of a system can be found out using the Basic performance formula.
3. A processor performing fetch or decoding of different instruction during the execution of another
instruction is called ______
a) Super-scaling
b) Pipe-lining
c) Parallel Computation
View Answer
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Answer: b
Explanation: Pipe-lining is the process of improving the performance of the system by processing
different instructions at the same time, with only one instruction performing one speci ic operation.
4. For a given FINITE number of instructions to be executed, which architecture of the processor
provides for a faster execution?
a) ISA
b) ANSA
c) Super-scalar
d) All of the mentioned
View Answer
Answer: c
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Explanation: In super-scalar architecture, the instructions are set in groups and they’re decoded and
executed together reducing the amount of time required to process them.
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5. The clock rate of the processor can be improved by _________
a) Improving the IC technology of the logic circuits
b) Reducing the amount of processing done in one step
c) By using the overclocking method
View Answer
Answer: d
Explanation: The clock rate(frequency of the processor) is the hardware dependent quantity it is ixed
for a given processor.
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6. An optimizing Compiler does _________

a) Better compilation of the given piece of code
b) Takes advantage of the type of processor and reduces its process time
c) Does better memory management
View Answer
Answer: b
Explanation: An optimizing compiler is a compiler designed for the speci ic purpose of increasing the
operation speed of the processor by reducing the time taken to compile the program instructions.
7. The ultimate goal of a compiler is to ________

a) Reduce the clock cycles for a programming task
b) Reduce the size of the object code
c) Be versatile
d) Be able to detect even the smallest of errors
View Answer
Answer: a
Explanation: None.
8. SPEC stands for _______

a) Standard Performance Evaluation Code
b) System Processing Enhancing Code
c) System Performance Evaluation Corporation
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d) Standard Processing Enhancement Corporation

View Answer
Answer: c
Explanation: SPEC is a corporation that started to standardize the evaluation method of a system’s
performance.
9. As of 2000, the reference system to ind the performance of a system is _____

a) Ultra SPARC 10
b) SUN SPARC
c) SUN II
View Answer
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Answer: a
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Explanation: In SPEC system of measuring a system’s performance, a system is used as a reference
against which other systems are compared and performance is determined.
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10. When Performing a looping operation, the instruction gets stored in the ______
a) Registers
b) Cache
c) System Heap
d) System stack
View Answer
Answer: b
Explanation: When a looping or branching operation is carried out the offset value is stored in the cache
along with the data.
11. The average number of steps taken to execute the set of instructions can be made to be less than one
by following _______
a) ISA
b) Pipe-lining
c) Super-scaling
d) Sequential
View Answer
Answer: c
Explanation: The number of steps required to execute a given set of instructions is suf iciently reduced
by using super-scaling. In this method, a set of instructions are grouped together and are processed.
12. If a processor clock is rated as 1250 million cycles per second, then its clock period is ________
a) 1.9 * 10-10 sec
b) 1.6 * 10-9 sec
c) 1.25 * 10-10 sec
d) 8 * 10-10 sec
View Answer
Answer: d
Explanation: None.
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13. If the instruction, Add R1, R2, R3 is executed in a system that is pipe-lined, then the value of S is
(Where S is a term of the Basic performance equation)?
a) 3
b) ~2
c) ~1
d) 6
View Answer
Answer: c
Explanation: S is the number of steps required to execute the instructions.
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14. CISC stands for _______
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a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
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c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation
View Answer
Answer: c
Explanation: CISC is a type of system architecture where complex instructions are grouped together and
executed to improve system performance.
15. As of 2000, the reference system to ind the SPEC rating are built with _____ Processor.
a) Intel Atom SParc 300Mhz
b) Ultra SPARC -IIi 300MHZ
c) Amd Neutrino series
d) ASUS A series 450 Mhz
View Answer
Answer: b
Explanation: None.

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Addressing Modes
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focuses on “Addressing Modes”.
1. The instruction, Add #45,R1 does _______

a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
View Answer
Answer: b
Explanation: The instruction is using immediate addressing mode hence the value is stored in the
location 45 is added.
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2. In the case of, Zero-address instruction method the operands are stored in _____
a) Registers
b) Accumulators
c) Push down stack
d) Cache
View Answer
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Answer: c
Explanation: In this case, the operands are implicitly loaded onto the ALU.
3. Add #45, when this instruction is executed the following happen/s _______
a) The processor raises an error and requests for one more operand
b) The value stored in memory location 45 is retrieved and one more operand is requested
c) The value 45 gets added to the value on the stack and is pushed onto the stack
View Answer
Answer: b
Explanation: None.
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4. The addressing mode which makes use of in-direction pointers is ______
a) Indirect addressing mode
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b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode
View Answer
Answer: a
Explanation: In this addressing mode, the value of the register serves as another memory location and
hence we use pointers to get the data.
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5. In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is ______
a) EA = 5+R1
b) EA = R1
c) EA = [R1]
d) EA = 5+[R1]
View Answer
Answer: d
Explanation: This instruction is in Base with offset addressing mode.
6. The addressing mode/s, which uses the PC instead of a general purpose register is ______
a) Indexed with offset
b) Relative
c) Direct
d) Both Indexed with offset and direct
View Answer
Answer: b
Explanation: In this, the contents of the PC are directly incremented.
7. When we use auto increment or auto decrements, which of the following is/are true?
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment, the operand is retrieved irst and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations
a) 1, 2, 3
b) 2
c) 1, 3
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d) 2, 3
View Answer
Answer: d
Explanation: In the case of, auto increment the increment is done afterward and in auto decrement the
decrement is done irst.
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8. The addressing mode, where you directly specify the operand value is _______
a) Immediate
b) Direct
c) De inite
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d) Relative
View Answer
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Answer: a
Explanation: None.
9. The effective address of the following instruction is MUL 5(R1,R2).

a) 5+R1+R2
b) 5+(R1*R2)
c) 5+[R1]+[R2]
d) 5*([R1]+[R2])
View Answer
Answer: c
Explanation: The addressing mode used is base with offset and index.
10. _____ addressing mode is most suitable to change the normal sequence of execution of instructions.
a) Relative
b) Indirect
c) Index with Offset
d) Immediate
View Answer
Answer: a
Explanation: The relative addressing mode is used for this since it directly updates the PC.
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20. Computer Organization Questions and Answers – Memory Locations and Addresses
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Numbers and Arithmetic Operations
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This set of Computer Organization Questions and Answers for Aptitude test focuses on “Numbers and
Arithmetic Operations”.
1. Which method/s of representation of numbers occupies a large amount of memory than others?
a) Sign-magnitude
b) 1’s complement
c) 2’s complement
d) 1’s & 2’s compliment
View Answer
Answer: a
Explanation: It takes more memory as one bit used up to store the sign.
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2. Which representation is most ef icient to perform arithmetic operations on the numbers?

a) Sign-magnitude
b) 1’s complement
c) 2’S complement
View Answer
Answer: c
Explanation: The two’s complement form is more suitable to perform arithmetic operations as there is
no need to involve the sign of the number into consideration.
3. Which method of representation has two representations for ‘0’?

a) Sign-magnitude
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b) 1’s complement
c) 2’s complement
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View Answer
Answer: a
Explanation: One is positive and one for negative.
4. When we perform subtraction on -7 and 1 the answer in 2’s complement form is _________
a) 1010
b) 1110
c) 0110
d) 1000
View Answer
Answer: d
Explanation: First the 2’s complement is found and that is added to the number and the over low is
ignored.
5. When we perform subtraction on -7 and -5 the answer in 2’s complement form is ________
a) 11110
b) 1110
c) 1010
d) 0010
View Answer
Answer: b
ignored.
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6. When we subtract -3 from 2 , the answer in 2’s complement form is _________

a) 0001
b) 1101
c) 0101
d) 1001
View Answer
Answer: c
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ignored.
7. The processor keeps track of the results of its operations using lags called ________
a) Conditional code lags
b) Test output lags
c) Type lags
View Answer
Answer: a
Explanation: These lags are used to indicate if there is an over low or carry or zero result occurrence.
8. The register used to store the lags is called as _________
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a) Flag register
b) Status register
A
c) Test register
d) Log register
View Answer
Answer: b
Explanation: The status register stores the condition codes of the system.
9. The Flag ‘V’ is set to 1 indicates that _____________

a) The operation is valid
b) The operation is validated
c) The operation has resulted in an over low
View Answer
Answer: c
Explanation: This is used to check the over low occurs in the operation.
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10. In some pipelined systems, a different instruction is used to add to numbers which can affect the
lags upon execution. That instruction is _______
a) AddSetCC
b) AddCC
c) Add++
d) SumSetCC
View Answer
Answer: a
Explanation: By using this instruction the condition lags won’t be affected at all.
11. The most ef icient method followed by computers to multiply two unsigned numbers is _______
a) Booth algorithm
b) Bit pair recording of multipliers
c) Restoring algorithm
d) Non restoring algorithm
View Answer
Answer: b
Explanation: None.
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12. For the addition of large integers, most of the systems make use of ______
a) Fast adders
b) Full adders
c) Carry look-ahead adders
View Answer
Answer: c
Explanation: In this method, the carries for each step are generated irst.
13. In a normal n-bit adder, to ind out if an over low as occurred we make use of ________
a) And gate
b) Nand gate
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c) Nor gate
d) Xor gate
A
View Answer
Answer: d
Explanation: None.
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14. In the implementation of a Multiplier circuit in the system we make use of _______
a) Counter
b) Flip lop
c) Shift register
d) Push down stack
View Answer
Answer: c
Explanation: The shift registers are used to store the multiplied answer.
15. When 1101 is used to divide 100010010 the remainder is ______

a) 101
b) 11
c) 0
d) 1
View Answer
Answer: d
Explanation: None.
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Memory Locations and Addresses
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focuses on “Memory Locations and Addresses”.
1. The smallest entity of memory is called _______

a) Cell
b) Block
c) Instance
d) Unit
View Answer
Answer: a
Explanation: Each data is made up of a number of units.
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2. The collection of the above mentioned entities where data is stored is called ______
a) Block
b) Set
c) Word
d) Byte
View Answer
Answer: c
Explanation: Each readable part of the data is called blocks.
3. An 24 bit address generates an address space of ______ locations.

a) 1024
b) 4096
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c) 248
d) 16,777,216
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View Answer
Answer: d
Explanation: The number of addressable locations in the system is called as address space.
4. If a system is 64 bit machine, then the length of each word will be _______
a) 4 bytes
b) 8 bytes
c) 16 bytes
d) 12 bytes
View Answer
Answer: b
Explanation: A 64 bit system means, that at a time 64 bit instruction can be executed.
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5. The type of memory assignment used in Intel processors is _____

a) Little Endian
b) Big Endian
c) Medium Endian
View Answer
Answer: a
Explanation: The method of address allocation to data to be stored is called as memory assignment.
6. When using the Big Endian assignment to store a number, the sign bit of the number is stored in _____
a) The higher order byte of the word
b) The lower order byte of the word
c) Can’t say
View Answer
Answer: a
Explanation: None.
7. To get the physical address from the logical address generated by CPU we use ____________
a) MAR
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b) MMU
c) Overlays
d) TLB
View Answer
Answer: b
Explanation: Memory Management Unit, is used to add the offset to the logical address generated by the
CPU to get the physical address.
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8. _____ method is used to map logical addresses of variable length onto physical memory.
a) Paging
b) Overlays
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c) Segmentation
d) Paging with segmentation
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View Answer
Answer: c
Explanation: Segmentation is a process in which memory is divided into groups of variable length called
segments.
9. During the transfer of data between the processor and memory we use ______
a) Cache
b) TLB
c) Buffers
d) Registers
View Answer
Answer: d
Explanation: None.
10. Physical memory is divided into sets of inite size called as ______
a) Frames
b) Pages
c) Blocks
d) Vectors
View Answer
Answer: a
Explanation: None.
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Memory Operations and Management
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focuses on “Memory Operations and Management”.
1. Add #%01011101,R1 , when this instruction is executed then _________

a) The binary addition between the operands takes place
b) The Numerical value represented by the binary value is added to the value of R1
c) The addition doesn’t take place, whereas this is similar to a MOV instruction
View Answer
Answer: a
Explanation: This performs operations in binary mode directly.
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2. If we want to perform memory or arithmetic operations on data in Hexa-decimal mode then we use
_________ symbol before the operand.
a) ~
b) !
c) $
d) *
View Answer
Answer: c
Explanation: None.
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3. When generating physical addresses from a logical address the offset is stored in __________
a) Translation look-aside buffer
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b) Relocation register
c) Page table
d) Shift register
View Answer
Answer: b
Explanation: In the MMU the relocation register stores the offset address.
4. The technique used to store programs larger than the memory is ____________
a) Overlays
b) Extension registers
c) Buffers
d) Both Extension registers and Buffers
View Answer
Answer: a
Explanation: In this, only a part of the program getting executed is stored on the memory and later
swapped in for the other part.
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5. The unit which acts as an intermediate agent between memory and backing store to reduce process
time is ___________
a) TLB’s
b) Registers
c) Page tables
d) Cache
View Answer
Answer: d
Explanation: The cache’s help in data transfers by storing most recently used memory pages.
6. Does the Load instruction do the following operation/s?

a) Loads the contents of a disc onto a memory location
b) Loads the contents of a location onto the accumulators
c) Load the contents of the PCB onto the register
View Answer
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Answer: b
Explanation: The load instruction is basically used to load the contents of a memory location onto a
register.
7. Complete the following analogy:- Registers are to RAM’s as Cache’s are to ___________
a) System stacks
b) Overlays
c) Page Table
d) TLB
View Answer
Answer: d
Explanation: None.
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8. The BOOT sector iles of the system are stored in ___________
a) Harddisk
b) ROM
c) RAM
d) Fast solid state chips in the motherboard
View Answer
Answer: b
Explanation: The iles which are required for the starting up of a system are stored on the ROM.
9. The transfer of large chunks of data with the involvement of the processor is done by _______
a) DMA controller
b) Arbitrator
c) User system programs
View Answer
Answer: a
Explanation: This mode of transfer involves the transfer of a large block of data from the memory.
10. Which of the following techniques used to effectively utilize main memory?
a) Address binding
b) Dynamic linking
c) Dynamic loading
d) Both Dynamic linking and loading
View Answer
Answer: c
Explanation: In this method only when the routine is required is loaded and hence saves memory.
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Instructions and Instruction Sequencing
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This set of Computer Organization Questions and Answers for Campus interviews focuses on
“Instructions and Instruction Sequencing”.
1. RTN stands for ___________

a) Register Transfer Notation
b) Register Transmission Notation
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c) Regular Transmission Notation

d) Regular Transfer Notation
View Answer
Answer: a
Explanation: This is the way of writing the assembly language code with the help of register notations.
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2. The instruction, Add Loc,R1 in RTN is _______

a) AddSetCC Loc+R1
b) R1=Loc+R1
c) Not possible to write in RTN
d) R1<-[Loc]+[R1]
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View Answer
A
Answer: d
Explanation: None.
3. Can you perform an addition on three operands simultaneously in ALN using Add instruction?
a) Yes
b) Not possible using Add, we’ve to use AddSetCC
c) Not permitted
View Answer
Answer: c
Explanation: You cannot perform an addition on three operands simultaneously because the third
operand is where the result is stored.
4. The instruction, Add R1,R2,R3 in RTN is _______

a) R3=R1+R2+R3
b) R3<-[R1]+[R2]+[R3]
c) R3=[R1]+[R2]
d) R3<-[R1]+[R2]
View Answer
Answer: d
Explanation: In RTN the irst operand is the destination and the second operand is the source.
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5. In a system, which has 32 registers the register id is __________ long.

a) 16 bit
b) 8 bits
c) 5 bits
d) 6 bits
View Answer
Answer: c
Explanation: The ID is the name tag given to each of the registers and used to identify them.
6. The two phases of executing an instruction are __________

a) Instruction decoding and storage
b) Instruction fetch and instruction execution
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c) Instruction execution and storage

d) Instruction fetch and Instruction processing
View Answer
Answer: b
Explanation: First, the instructions are fetched and decoded and then they’re executed and stored.
7. The Instruction fetch phase ends with _________

a) Placing the data from the address in MAR into MDR
b) Placing the address of the data into MAR
c) Completing the execution of the data and placing its storage address into MAR
d) Decoding the data in MDR and placing it in IR
View Answer
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Answer: d
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Explanation: The fetch ends with the instruction getting decoded and being placed in the IR and the PC
getting incremented.
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8. While using the iterative construct (Branching) in execution _____________ instruction is used to check
the condition.
a) TestAndSet
b) Branch
c) TestCondn
View Answer
Answer: b
Explanation: Branch instruction is used to check the test condition and to perform the memory jump
with the help of offset.
9. When using Branching, the usual sequencing of the PC is altered. A new instruction is loaded which is
called as ______
a) Branch target
b) Loop target
c) Forward target
d) Jump instruction
View Answer
Answer: a
Explanation: None.
10. The condition lag Z is set to 1 to indicate _______

a) The operation has resulted in an error
b) The operation requires an interrupt call
c) The result is zero
d) There is no empty register available
View Answer
Answer: c
Explanation: This condition lag is used to check if the arithmetic operation yields a zero output.
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Assembly Language
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focuses on “Assembly Language”.
1. __________ converts the programs written in assembly language into machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter
View Answer
Answer: c
Explanation: An assembler is a software used to convert the programs into machine instructions.
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2. The instructions like MOV or ADD are called as ______
A
a) OP-Code
b) Operators
c) Commands
View Answer
Answer: a
Explanation: This OP – codes tell the system what operation to perform on the operands.
3. The alternate way of writing the instruction, ADD #5,R1 is ______

a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way
View Answer
Answer: b
Explanation: The ADDI instruction, means the addition is in immediate addressing mode.
4. Instructions which won’t appear in the object program are called as _____
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives
View Answer
Answer: d
Explanation: The directives help the program in getting compiled and hence won’t be there in the object
code.
5. The assembler directive EQU, when used in the instruction: Sum EQU 200 does ________
a) Finds the irst occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
c) Re-assigns the address of Sum by adding 200 to its original address
d) Assigns 200 bytes of memory starting the location of Sum
View Answer
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Answer: b
Explanation: This basically is used to replace the variable with a constant value.
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6. The purpose of the ORIGIN directive is __________

a) To indicate the starting position in memory, where the program block is to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used
View Answer
Answer: a
Explanation: This does the function similar to the main statement.
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7. The directive used to perform initialization before the execution of the code is ______
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a) Reserve
b) Store
c) Dataword
d) EQU
View Answer
Answer: c
Explanation: None.
8. _____ directive is used to specify and assign the memory required for the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve
View Answer
Answer: d
Explanation: This instruction is used to allocate a block of memory and to store the object code of the
program there.
9. _____ directive speci ies the end of execution of a program.

a) End
b) Return
c) Stop
d) Terminate
View Answer
Answer: b
Explanation: This instruction directive is used to terminate the program execution.
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10. The last statement of the source program should be _______

a) Stop
b) Return
c) OP
d) End
View Answer
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Answer: d
Explanation: This enables the processor to load some other process.
11. When dealing with the branching code the assembler ___________
a) Replaces the target with its address
b) Does not replace until the test condition is satis ied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value speci ied by the DATAWORD directive
View Answer
Answer: c
Explanation: When the assembler comes across the branch code, it immediately inds the branch offset
and replaces it with it.
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12. The assembler stores all the names and their corresponding values in ______
A
a) Special purpose Register
b) Symbol Table
c) Value map Set
View Answer
Answer: b
Explanation: The table where the assembler stores the variable names along with their corresponding
memory locations and values.
13. The assembler stores the object code in ______

a) Main memory
b) Cache
c) RAM
d) Magnetic disk
View Answer
Answer: d
Explanation: After compiling the object code, the assembler stores it in the magnetic disk and waits for
further execution.
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14. The utility program used to bring the object code into memory for execution is ______
a) Loader
b) Fetcher
c) Extractor
d) Linker
View Answer
Answer: a
Explanation: The program is used to load the program into memory.
15. To overcome the problems of the assembler in dealing with branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler
View Answer
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Answer: d
Explanation: This creates entries into the symbol table irst and then creates the object code.

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Subroutines and Nesting
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focuses on “Subroutines and Nesting”.
1. The return address of the Sub-routine is pointed to by _______

a) IR
b) PC
c) MAR
d) Special memory registers
View Answer
Answer: b
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Explanation: The return address from the subroutine is pointed to by the PC.
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2. The location to return to, from the subroutine is stored in _______
a) TLB
b) PC
c) MAR
d) Link registers
View Answer
Answer: d
Explanation: The registers store the return address of the routine and is pointed to by the PC.
3. What is subroutine nesting?

a) Having multiple subroutines in a program
b) Using a linking nest statement to put many subroutines under the same name
c) Having one routine call the other
View Answer
Answer: c
Explanation: None.
4. The order in which the return addresses are generated and used is _________
a) LIFO
b) FIFO
c) Random
d) Highest priority
View Answer
Answer: a
Explanation: That is the routine called irst is returned irst.
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5. In case of nested subroutines the return addresses are stored in __________

a) System heap
b) Special memory buffers
c) Processor stack
d) Registers
View Answer
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Answer: c
Explanation: In this case, there will be more number of return addresses it is stored on the processor
stack.
6. The appropriate return addresses are obtained with the help of ____ in case of nested routines.
a) MAR
b) MDR
c) Buffers
d) Stack-pointers
View Answer
Answer: d
Explanation: The pointers are used to point to the location on the stack where the address is stored.
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7. When parameters are being passed on to the subroutines they are stored in ________
A
a) Registers
b) Memory locations
c) Processor stacks
View Answer
Answer: d
Explanation: In the case of, parameter passing the data can be stored on any of the storage space.
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8. The most ef icient way of handling parameter passing is by using ______

a) General purpose registers
b) Stacks
c) Memory locations
View Answer
Answer: a
Explanation: By using general purpose registers for the parameter passing we make the process more
ef icient.
9. The most Flexible way of logging the return addresses of the subroutines is by using _______
a) Registers
b) Stacks
c) Memory locations
View Answer
Answer: b
Explanation: The stacks are used as Logs for return addresses of the subroutines.
10. The wrong statement/s regarding interrupts and subroutines among the following is/are ______
i) The sub-routine and interrupts have a return statement
ii) Both of them alter the content of the PC
iii) Both are software oriented
iv) Both can be initiated by the user
a) i, ii and iv
b) ii and iii
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c) iv
d) iii and iv
View Answer
Answer: d
Explanation: None.
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Parameter Passing and Stack Frame
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This set of Computer Organization Questions and Answers for Entrance exams focuses on “Parameter
Passing and Stack Frame”.
1. The private work space dedicated to a subroutine is called as ________

a) System heap
b) Reserve
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c) Stack frame
d) Allocation
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View Answer
Answer: c
Explanation: This work space is where the intermediate values of the subroutines are stored.
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2. If the subroutine exceeds the private space allocated to it then the values are pushed onto _________
a) Stack
b) System heap
c) Reserve Space
d) Stack frame
View Answer
Answer: a
Explanation: If the allocated work space is exceeded then the data is pushed onto the system stack.
3. ______ pointer is used to point to parameters passed or local parameters of the subroutine.
a) Stack pointer
b) Frame pointer
c) Parameter register
d) Log register
View Answer
Answer: b
Explanation: This pointer is used to track the current position of the stack being used.
4. The reserved memory or private space of the subroutine gets deallocated when _______
a) The stop instruction is executed by the routine
b) The pointer reaches the end of the space
c) When the routine’s return statement is executed
View Answer
Answer: c
Explanation: The work space allocated to a subroutine gets deallocated when the routine is completed.
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5. The private space gets allocated to each subroutine when _________

a) The irst statement of the routine is executed
b) When the context switch takes place
c) When the routine gets called
d) When the Allocate instruction is executed
View Answer
Answer: c
Explanation: When the call statement is executed, simultaneously space also gets allocated.
6. _____ the most suitable data structure used to store the return addresses in the case of nested
subroutines.
a) Heap
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b) Stack
c) Queue
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d) List
View Answer
Answer: b
Explanation: None.
7. In the case of nested subroutines, the stack top is always _________

a) The saved contents of the called sub routine
b) The saved contents of the calling sub routine
c) The return addresses of the called sub routine
View Answer
Answer: a
Explanation: None.
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8. The stack frame for each subroutine is present in ______

a) Main memory
b) System Heap
c) Processor Stack
View Answer
Answer: c
Explanation: The memory for the work space is allocated from the processor stack.
9. The data structure suitable for scheduling processes is _______

a) List
b) Heap
c) Queue
d) Stack
View Answer
Answer: c
Explanation: The Queue data structure is generally used for scheduling as it is two directional.
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10. The sub-routine service procedure is similar to that of the interrupt service routine in ________
a) Method of context switch
b) Returning
c) Process execution
d) Method of context switch & Process execution
View Answer
Answer: d
Explanation: The Subroutine service procedure is the same as the interrupt service routine in all aspects,
except the fact that interrupt might not be related to the process being executed.
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Accessing I/O Devices
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focuses on “Accessing I/O Devices”.
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1. In memory-mapped I/O ____________
A
a) The I/O devices and the memory share the same address space
b) The I/O devices have a separate address space
c) The memory and I/O devices have an associated address space
d) A part of the memory is speci ically set aside for the I/O operation
View Answer
Answer: a
Explanation: Its the different modes of accessing the i/o devices.
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2. The usual BUS structure used to connect the I/O devices is ___________
a) Star BUS structure
b) Multiple BUS structure
c) Single BUS structure
d) Node to Node BUS structure
View Answer
Answer: c
Explanation: BUS is a collection of address, control and data lines used to connect the various devices of
the computer.
3. In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices.
a) False
b) True
View Answer
Answer: b
Explanation: This type of access is called as I/O mapped devices.
4. The advantage of I/O mapped devices to memory mapped is ___________

a) The former offers faster transfer of data
b) The devices connected using I/O mapping have a bigger buffer space
c) The devices have to deal with fewer address lines
d) No advantage as such
View Answer
Answer: c
Explanation: Since the I/O mapped devices have a separate address space the address lines are limited
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by the amount of the space allocated.

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5. The system is noti ied of a read or write operation by ___________

a) Appending an extra bit of the address
b) Enabling the read or write bits of the devices
c) Raising an appropriate interrupt signal
d) Sending a special signal along the BUS
View Answer
Answer: d
Explanation: It is necessary for the processor to send a signal intimating the request as either read or
write.
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6. To overcome the lag in the operating speeds of the I/O device and the processor we use ___________
A
a) BUffer spaces
b) Status lags
c) Interrupt signals
d) Exceptions
View Answer
Answer: b
Explanation: The processor operating is much faster than that of the I/O devices, so by using the status
lags the processor need not wait till the I/O operation is done. It can continue with its work until the
status lag is set.
7. The method of accessing the I/O devices by repeatedly checking the status lags is ___________
a) Program-controlled I/O
b) Memory-mapped I/O
c) I/O mapped
View Answer
Answer: a
Explanation: In this method, the processor constantly checks the status lags, and when it inds that the
lag is set it performs the appropriate operation.
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8. The method of synchronising the processor with the I/O device in which the device sends a signal
when it is ready is?
a) Exceptions
b) Signal handling
c) Interrupts
d) DMA
View Answer
Answer: c
Explanation: This is a method of accessing the I/O devices which gives the complete power to the
devices, enabling them to intimate the processor when they’re ready for transfer.
9. The method which offers higher speeds of I/O transfers is ___________

a) Interrupts
b) Memory mapping
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c) Program-controlled I/O
d) DMA
View Answer
Answer: d
Explanation: In DMA the I/O devices are directly allowed to interact with the memory without the
intervention of the processor and the transfers take place in the form of blocks increasing the speed of
operation.
10. The process wherein the processor constantly checks the status lags is called as ___________
a) Polling
b) Inspection
c) Reviewing
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d) Echoing
View Answer
A
Answer: a
Explanation: None.
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Interrupts – 1
A
« Prev Next »
focuses on “Interrupts – 1”.
1. The interrupt-request line is a part of the ___________

a) Data line
b) Control line
c) Address line
View Answer
Answer: b
Explanation: The Interrupt-request line is a control line along which the device is allowed to send the
interrupt signal.
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2. The return address from the interrupt-service routine is stored on the ___________
a) System heap
b) Processor register
c) Processor stack
d) Memory
View Answer
Answer: c
Explanation: The Processor after servicing the interrupts as to load the address of the previous process
and this address is stored in the stack.
3. The signal sent to the device from the processor to the device after receiving an interrupt is ___________
a) Interrupt-acknowledge
b) Return signal
c) Service signal
d) Permission signal
View Answer
Answer: a
Explanation: The Processor upon receiving the interrupt should let the device know that its request is
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received.
4. When the process is returned after an interrupt service ______ should be loaded again.
i) Register contents
ii) Condition codes
iii) Stack contents
iv) Return addresses
a) i, iv
b) ii, iii and iv
c) iii, iv
d) i, ii
View Answer
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Answer: d
Explanation: None.
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5. The time between the receiver of an interrupt and its service is ______
a) Interrupt delay
b) Interrupt latency
c) Cycle time
d) Switching time
View Answer
Answer: b
Explanation: The delay in servicing of an interrupt happens due to the time is taken for contact switch to
take place.
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6. Interrupts form an important part of _____ systems.

a) Batch processing
b) Multitasking
c) Real-time processing
d) Multi-user
View Answer
Answer: c
Explanation: This forms an important part of the Real time system since if a process arrives with greater
priority then it raises an interrupt and the other process is stopped and the interrupt will be serviced.
7. A single Interrupt line can be used to service n different devices.

a) True
b) False
View Answer
Answer: a
Explanation: None.
8. ______ type circuits are generally used for interrupt service lines.
i) open-collector
ii) open-drain
iii) XOR
iv) XNOR
a) i, ii
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b) ii
c) ii, iii
d) ii, iv
View Answer
Answer: a
Explanation: None.
9. The resistor which is attached to the service line is called _____

a) Push-down resistor
b) Pull-up resistor
c) Break down resistor
d) Line resistor
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View Answer
A
Answer: b
Explanation: This resistor is used to pull up the voltage of the interrupt service line.
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10. An interrupt that can be temporarily ignored is ___________

a) Vectored interrupt
b) Non-maskable interrupt
c) Maskable interrupt
d) High priority interrupt
View Answer
Answer: c
Explanation: The maskable interrupts are usually low priority interrupts which can be ignored if a higher
priority process is being executed.
11. The 8085 microprocessor responds to the presence of an interrupt ___________

a) As soon as the trap pin becomes ‘LOW’
b) By checking the trap pin for ‘high’ status at the end of each instruction fetch
c) By checking the trap pin for ‘high’ status at the end of execution of each instruction
d) By checking the trap pin for ‘high’ status at regular intervals
View Answer
Answer: c
Explanation: The 8085 microprocessor are designed to complete the execution of the current instruction
and then to service the interrupts.
12. CPU as two modes privileged and non-privileged. In order to change the mode from privileged to
non-privileged.
a) A hardware interrupt is needed
b) A software interrupt is needed
c) Either hardware or software interrupt is needed
d) A non-privileged instruction (which does not generate an interrupt)is needed
View Answer
Answer: b
Explanation: A software interrupt by some program which needs some CPU service, at that time the two
modes can be interchanged.
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13. Which interrupt is unmaskable?

a) RST 5.5
b) RST 7.5
c) TRAP
d) Both RST 5.5 and 7.5
View Answer
Answer: c
Explanation: The trap is a non-maskable interrupt as it deals with the ongoing process in the processor.
The trap is initiated by the process being executed due to lack of data required for its completion. Hence
trap is unmaskable.
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14. From amongst the following given scenarios determine the right one to justify interrupt mode of data
transfer.
A
i) Bulk transfer of several kilo-byte
ii) Moderately large data transfer of more than 1kb
iii) Short events like mouse action
iv) Keyboard inputs
a) i and ii
b) ii
c) i, ii and iv
d) iv
View Answer
Answer: d
Explanation: None.
15. How can the processor ignore other interrupts when it is servicing one ___________
a) By turning off the interrupt request line
b) By disabling the devices from sending the interrupts
c) BY using edge-triggered request lines
View Answer
Answer: d
Explanation: None.

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Interrupts – 2
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This set of Basic Computer Organization Questions and Answers focuses on “Interrupts – 2”.
1. When dealing with multiple devices interrupts, which mechanism is easy to implement?
a) Polling method
b) Vectored interrupts
c) Interrupt nesting
View Answer
Answer: a
Explanation: In this method, the processor checks the IRQ bits of all the devices, whichever is enabled
irst that device is serviced.
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2. The interrupt servicing mechanism in which the requesting device identi ies itself to the processor to
be serviced is ___________
a) Polling
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b) Vectored interrupts
c) Interrupt nesting
d) Simultaneous requesting
View Answer
Answer: b
Explanation: None.
3. In vectored interrupts, how does the device identify itself to the processor?
a) By sending its device id
b) By sending the machine code for the interrupt service routine
c) By sending the starting address of the service routine
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View Answer
A
Answer: c
Explanation: By sending the starting address of the routine the device ids the routine required and
thereby identifying itself.
4. The code sent by the device in vectored interrupt is _____ long.

a) upto 16 bits
b) upto 32 bits
c) upto 24 bits
d) 4-8 bits
View Answer
Answer: d
Explanation: None.
5. The starting address sent by the device in vectored interrupt is called as __________
a) Location id
b) Interrupt vector
c) Service location
d) Service id
View Answer
Answer: b
Explanation: None.
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6. The processor indicates to the devices that it is ready to receive interrupts ________
a) By enabling the interrupt request line
b) By enabling the IRQ bits
c) By activating the interrupt acknowledge line
View Answer
Answer: c
Explanation: When the processor activates the acknowledge line the devices send their interrupts to the
processor.
7. We describe a protocol of input device communication below:

i) Each device has a distinct address.
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ii) The BUS controller scans each device in a sequence of increasing address value to determine if the
entity wishes to communicate
iii) The device ready to communicate leaves its data in the I/O register
iv) The data is picked up and the controller moves to the step a
Identify the form of communication best describes the I/O mode amongst the following.
a) Programmed mode of data transfer
b) DMA
c) Interrupt mode
d) Polling
View Answer
Answer: d
Explanation: In polling, the processor checks each of the devices if they wish to perform data transfer
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and if they do it performs the particular operation.
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8. Which one of the following is true with regard to a CPU having a single interrupt request line and
single interrupt grant line?
i) Neither vectored nor multiple interrupting devices is possible.
ii) Vectored interrupts is not possible but multiple interrupting devices is possible.
iii) Vectored interrupts is possible and multiple interrupting devices is not possible.
iv) Both vectored and multiple interrupting devices are possible.
a) iii
b) i, iv
c) ii, iii
d) iii, iv
View Answer
Answer: a
Explanation: None.
9. Which table handle stores the addresses of the interrupt handling sub-routines?
a) Interrupt-vector table
b) Vector table
c) Symbol link table
View Answer
Answer: a
Explanation: None.
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10. _________ method is used to establish priority by serially connecting all devices that request an
interrupt.
a) Vectored-interrupting
b) Daisy chain
c) Priority
d) Polling
View Answer
Answer: b
Explanation: In the Daisy chain mechanism, all the devices are connected using a single request line and
they’re serviced based on the interrupting device’s priority.
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11. In daisy chaining device 0 will pass the signal only if it has _______
a) Interrupt request
b) No interrupt request
c) Both No interrupt and Interrupt request
View Answer
Answer: b
Explanation: In daisy chaining since there is only one request line and only one acknowledges line, the
acknowledge signal passes from device to device until the one with the interrupt is found.
12. ______ interrupt method uses register whose bits are set separately by interrupt signal for each
device.
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a) Parallel priority interrupt
b) Serial priority interrupt
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c) Daisy chaining
View Answer
Answer: a
Explanation: None.
13. ______________ register is used for the purpose of controlling the status of each interrupt request in
parallel priority interrupt.
a) Mass
b) Mark
c) Make
d) Mask
View Answer
Answer: d
Explanation: None.
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14. The added output of the bits of the interrupt register and the mask register is set as an input of
______________
a) Priority decoder
b) Priority encoder
c) Process id encoder
d) Multiplexer
View Answer
Answer: b
Explanation: In a parallel priority system, the priority of the device is obtained by adding the contents of
the interrupt register and the mask register.
15. Interrupts initiated by an instruction is called as _______

a) Internal
b) External
c) Hardware
d) Software
View Answer
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Answer: b
Explanation: None.
To practice basic questions and answers on all areas of Computer Organization, here is complete set on
1000+ Multiple Choice Questions and Answers on Computer Organization and Architecture.

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Exceptions
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« Prev Next »
focuses on “Exceptions”.
1. If during the execution of an instruction an exception is raised then __________

a) The instruction is executed and the exception is handled
b) The instruction is halted and the exception is handled
c) The processor completes the execution and saves the data and then handle the exception
View Answer
Answer: b
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Explanation: Since the interrupt was raised during the execution of the instruction, the instruction
cannot be executed and the exception is served immediately.
A
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2. _____ is/are types of exceptions.

a) Trap
b) Interrupt
c) System calls
View Answer
Answer: d
Explanation: None.
3. The program used to ind out errors is called __________

a) Debugger
b) Compiler
c) Assembler
d) Scanner
View Answer
Answer: a
Explanation: Debugger is a program used to detect and correct errors in the program.
4. The two facilities provided by the debugger is __________

a) Trace points
b) Break points
c) Compile
d) Both Trace and Break points
View Answer
Answer: d
Explanation: The debugger provides us with the two facilities to improve the checking of errors.
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5. In trace mode of operation is ________

a) The program is interrupted after each detection
b) The program will not be stopped and the errors are sorted out after the complete program is scanned
c) There is no effect on the program, i.e the program is executed without recti ication of errors
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d) The program is halted only at speci ic points

View Answer
Answer: a
Explanation: In trace mode, the program is checked line by line and if errors are detected then
exceptions are raised right away.
6. What is the operation in Breakpoint mode?

a) The program is interrupted after each detection
b) The program will not be stopped and the errors are sorted out after the complete program is scanned
c) There is no effect on the program, i.e the program is executed without recti ication of errors
d) The program is halted only at speci ic points
View Answer
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Answer: d
A
Explanation: The Breakpoint mode of operation allows the program to be halted at only speci ic
locations.
7. What are the different modes of operation of a computer?

a) User and System mode
b) User and Supervisor mode
c) Supervisor and Trace mode
d) Supervisor, User and Trace mode
View Answer
Answer: b
Explanation: The user programs are in the user mode and the system crucial programs are in the
supervisor mode.
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8. The instructions which can be run only supervisor mode are?

a) Non-privileged instructions
b) System instructions
c) Privileged instructions
d) Exception instructions
View Answer
Answer: c
Explanation: These instructions are those which can are crucial for the system’s performance and hence
cannot be adultered by user programs, so is run only in supervisor mode.
9. A privilege exception is raised __________

a) When a process tries to change the mode of the system
b) When a process tries to change the priority level of the other processes
c) When a process tries to access the memory allocated to other users
View Answer
Answer: d
Explanation: None.
10. How is a privilege exception dealt with?

a) The program is halted and the system switches into supervisor mode and restarts the program
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execution
b) The Program is stopped and removed from the queue
c) The system switches the mode and starts the execution of a new process
d) The system switches mode and runs the debugger
View Answer
Answer: a
Explanation: None.
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Direct Memory Access
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focuses on “Direct Memory Access”.
1. The DMA differs from the interrupt mode by __________

a) The involvement of the processor for the operation
b) The method of accessing the I/O devices
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c) The amount of data transfer possible
A
View Answer
Answer: d
Explanation: DMA is an approach of performing data transfers in bulk between memory and the external
device without the intervention of the processor.
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2. The DMA transfers are performed by a control circuit called as __________

a) Device interface
b) DMA controller
c) Data controller
d) Overlooker
View Answer
Answer: b
Explanation: The Controller performs the functions that would normally be carried out by the processor.
3. In DMA transfers, the required signals and addresses are given by the __________
a) Processor
b) Device drivers
c) DMA controllers
d) The program itself
View Answer
Answer: c
Explanation: The DMA controller acts as a processor for DMA transfers and overlooks the entire
process.
4. After the completion of the DMA transfer, the processor is noti ied by __________
a) Acknowledge signal
b) Interrupt signal
c) WMFC signal
View Answer
Answer: b
Explanation: The controller raises an interrupt signal to notify the processor that the transfer was
complete.
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5. The DMA controller has _______ registers.

a) 4
b) 2
c) 3
d) 1
View Answer
Answer: c
Explanation: The Controller uses the registers to store the starting address, word count and the status of
the operation.
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6. When the R/W bit of the status register of the DMA controller is set to 1.
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a) Read operation is performed
b) Write operation is performed
A
c) Read & Write operation is performed
View Answer
Answer: a
Explanation: None.
7. The controller is connected to the ____

a) Processor BUS
b) System BUS
c) External BUS
View Answer
Answer: b
Explanation: The controller is directly connected to the system BUS to provide faster transfer of data.
8. Can a single DMA controller perform operations on two different disks simultaneously?
a) True
b) False
View Answer
Answer: a
Explanation: The DMA controller can perform operations on two different disks if the appropriate
details are known.
9. The technique whereby the DMA controller steals the access cycles of the processor to operate is
called __________
a) Fast conning
b) Memory Con
c) Cycle stealing
d) Memory stealing
View Answer
Answer: c
Explanation: The controller takes over the processor’s access cycles and performs memory operations.
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10. The technique where the controller is given complete access to main memory is __________
a) Cycle stealing
b) Memory stealing
c) Memory Con
d) Burst mode
View Answer
Answer: d
Explanation: The controller is given full control of the memory access cycles and can transfer blocks at a
faster rate.
11. The controller uses _____ to help with the transfers when handling network interfaces.
a) Input Buffer storage
R
b) Signal enhancers
c) Bridge circuits
A
View Answer
Answer: a
Explanation: The controller stores the data to transfer in the buffer and then transfers it.
12. To overcome the con lict over the possession of the BUS we use ______
a) Optimizers
b) BUS arbitrators
c) Multiple BUS structure
View Answer
Answer: b
Explanation: The BUS arbitrator is used to overcome the contention over the BUS possession.
13. The registers of the controller are ______

a) 64 bits
b) 24 bits
c) 32 bits
d) 16 bits
View Answer
Answer: c
Explanation: None.
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14. When the process requests for a DMA transfer?

a) Then the process is temporarily suspended
b) The process continues execution
c) Another process gets executed
d) process is temporarily suspended & Another process gets executed
View Answer
Answer: d
Explanation: The process requesting the transfer is paused and the operation is performed, meanwhile
another process is run on the processor.
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15. The DMA transfer is initiated by _____

a) Processor
b) The process being executed
c) I/O devices
d) OS
View Answer
Answer: c
Explanation: The transfer can only be initiated by an instruction of a program being executed.
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Bus Arbitration
« Prev Next »
focuses on “Bus Arbitration”.
1. To resolve the clash over the access of the system BUS we use ______
a) Multiple BUS
b) BUS arbitrator
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c) Priority access
A
View Answer
Answer: b
Explanation: The BUS arbitrator is used to allow a device to access the BUS based on certain parameters.
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2. The device which is allowed to initiate data transfers on the BUS at any time is called _____
a) BUS master
b) Processor
c) BUS arbitrator
d) Controller
View Answer
Answer: a
Explanation: The device which is currently accessing the BUS is called as the BUS master.
3. ______ BUS arbitration approach uses the involvement of the processor.

a) Centralised arbitration
b) Distributed arbitration
c) Random arbitration
View Answer
Answer: a
Explanation: In this approach, the processor takes into account the various parameters and assigns the
BUS to that device.
4. The circuit used for the request line is a _________

a) Open-collector
b) EX-OR circuit
c) Open-drain
d) Nand circuit
View Answer
Answer: c
Explanation: None.
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5. The Centralised BUS arbitration is similar to ______ interrupt circuit.

a) Priority
b) Parallel
c) Single
d) Daisy chain
View Answer
Answer: d
Explanation: None.
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6. When the processor receives the request from a device, it responds by sending _____
a) Acknowledge signal
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b) BUS grant signal
c) Response signal
A
View Answer
Answer: b
Explanation: The Grant signal is passed from one device to the other until the device that has requested
is found.
7. In Centralised Arbitration ______ is/are is the BUS master.

a) Processor
b) DMA controller
c) Device
d) Both Processor and DMA controller
View Answer
Answer: d
Explanation: The BUS master is the one that decides which will get the BUS.
8. Once the BUS is granted to a device ___________

a) It activates the BUS busy line
b) Performs the required operation
c) Raises an interrupt
View Answer
Answer: a
Explanation: The BUS busy activated indicates that the BUS is already allocated to a device and is being
used.
9. The BUS busy line is made of ________

a) Open-drain circuit
b) Open-collector circuit
c) EX-Or circuit
d) Nor circuit
View Answer
Answer: b
Explanation: None.
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10. After the device completes its operation _____ assumes the control of the BUS.
a) Another device
b) Processor
c) Controller
View Answer
Answer: b
Explanation: After the device completes the operation it releases the BUS and the processor takes over it.
11. The BUS busy line is used __________

a) To indicate the processor is busy
b) To indicate that the BUS master is busy
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c) To indicate the BUS is already allocated
A
View Answer
Answer: c
Explanation: None.
12. Distributed arbitration makes use of ______

a) BUS master
b) Processor
c) Arbitrator
d) 4-bit ID
View Answer
Answer: d
Explanation: The device uses a 4bit ID number and based on this the BUS is allocated.
13. In Distributed arbitration, the device requesting the BUS ______

a) Asserts the Start arbitration signal
b) Sends an interrupt signal
c) Sends an acknowledge signal
View Answer
Answer: a
Explanation: None.
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14. How is a device selected in Distributed arbitration?

a) By NANDing the signals passed on all the 4 lines
b) By ANDing the signals passed on all the 4 lines
c) By ORing the signals passed on all the 4 lines
View Answer
Answer: c
Explanation: The OR output of all the 4 lines is obtained and the device with the larger value is assigned
the BUS.
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15. If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the
BUS based on the Distributed arbitration.
a) Device A
b) Device B
c) Insuf icient information
View Answer
Answer: b
Explanation: The device Id’s of both the devices are passed on the lines and since the value of B is
greater after the Or operation it gets the BUS.
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A

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Synchronous BUS
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focuses on “Synchronous BUS”.
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1. The primary function of the BUS is __________
A
a) To connect the various devices to the cpu
b) To provide a path for communication between the processor and other devices
c) To facilitate data transfer between various devices
View Answer
Answer: a
Explanation: The BUS is used to allow the passage of commands and data between cpu and devices.
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2. The classi ication of BUSes into synchronous and asynchronous is based on __________
a) The devices connected to them
b) The type of data transfer
c) The Timing of data transfers
View Answer
Answer: c
Explanation: The BUS is classi ied into different types for the convenience of use and depending on the
device.
3. The device which starts data transfer is called __________

a) Master
b) Transactor
c) Distributor
d) Initiator
View Answer
Answer: d
Explanation: The device which starts the data transfer is called an initiator.
4. The device which interacts with the initiator is __________

a) Slave
b) Master
c) Responder
d) Friend
View Answer
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Answer: a
Explanation: The device which receives the commands from the initiator for data transfer.
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5. In synchronous BUS, the devices get the timing signals from __________
a) Timing generator in the device
b) A common clock line
c) Timing signals are not used at all
View Answer
Answer: b
Explanation: The devices receive their timing signals from the clock line of the BUS.
R
6. The delays caused in the switching of the timing signals is due to __________
A
b) WMFC
c) Propagation delay
d) Processor delay
View Answer
Answer: c
Explanation: The time taken for the signal to reach the BUS from the device or the circuit accounts for
this delay.
7. The time for which the data is to be on the BUS is affected by __________
a) Propagation delay of the circuit
b) Setup time of the device
c) Memory access time
d) Propagation delay of the circuit & Setup time of the device
View Answer
Answer: d
Explanation: The time for which the data is held is larger than the time taken for propagation delay and
setup time.
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8. The Master strobes the slave at the end of each clock cycle in Synchronous BUS.
a) True
b) False
View Answer
Answer: a
Explanation: None.
9. Which is fed into the BUS irst by the initiator?

a) Data
b) Address
c) Commands or controls
d) Address, Commands or controls
View Answer
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Answer: d
Explanation: None.
10. _____________ signal is used as an acknowledgement signal by the slave in Multiple cycle transfers.
a) Ack signal
b) Slave ready signal
c) Master ready signal
d) Slave received signal
View Answer
Answer: b
Explanation: The slave once it receives the commands and address from the master strobes the ready
line indicating to the master that the commands are received.
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A

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Asynchronous BUS
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focuses on “Asynchronous BUS”.
A
1. The master indicates that the address is loaded onto the BUS, by activating _____ signal.
a) MSYN
b) SSYN
c) WMFC
d) INTR
View Answer
Answer: a
Explanation: The signal activated by the master in the asynchronous mode of transmission is used to
intimate the slave the required data is on the BUS.
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2. The devices with variable speeds are usually connected using asynchronous BUS.
a) True
b) False
View Answer
Answer: a
Explanation: The devices with variable speeds are connected using asynchronous BUS, as the devices
share a master-slave relationship.
3. The MSYN signal is initiated __________

a) Soon after the address and commands are loaded
b) Soon after the decoding of the address
c) After the slave gets the commands
View Answer
Answer: b
Explanation: This signal is activated by the master to tell the slave that the required commands are on
the BUS.
4. In IBM’s S360/370 systems _____ lines are used to select the I/O devices.
a) SCAN in and out
b) Connect
c) Search
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d) Peripheral
View Answer
Answer: a
Explanation: The signal is used to scan and connect to input or output devices.
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5. The meter in and out lines are used for __________

a) Monitoring the usage of devices
b) Monitoring the amount of data transferred
c) Measure the CPU usage
View Answer
R
Answer: a
A
Explanation: The line is used to monitor the usage of the device for a process.
6. MRDC stands for _______

a) Memory Read Enable
b) Memory Ready Command
c) Memory Re-direct Command
View Answer
Answer: b
Explanation: The command is used to initiate a read from memory operation.
7. The BUS that allows I/O, memory and Processor to coexist is _______
a) Attributed BUS
b) Processor BUS
c) Backplane BUS
d) External BUS
View Answer
Answer: c
Explanation: None.
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8. The transmission on the asynchronous BUS is also called _____

a) Switch mode transmission
b) Variable transfer
c) Bulk transfer
d) Hand-Shake transmission
View Answer
Answer: d
Explanation: The asynchronous transmission is termed as Hand-Shake transfer because the master
intimates the slave after each step of the transfer.
9. Asynchronous mode of transmission is suitable for systems with multiple peripheral devices.
a) True
b) False
View Answer
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Answer: a
Explanation: This mode of transmission is suitable for multiple device situation as it supports variable
speed transfer.
10. The asynchronous BUS mode of transmission allows for a faster mode of data transfer.
a) True
b) False
View Answer
Answer: b
Explanation: None.
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R
Sanfoundry Global Education & Learning Series – Computer Organisation and Architecture.
A
To practice all areas of Computer Organisation and Architecture, Here is a complete set of 1000+
Multiple Choice Questions and Answers on Computer Organisation and Architecture

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Interface Circuits
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focuses on “Interface Circuits”.
A
1. ______ serves as an intermediary between the device and the BUSes.
a) Interface circuits
b) Device drivers
c) Buffers
View Answer
Answer: a
Explanation: The interface circuits act as a hardware interface between the device and the software side.
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2. The side of the interface circuits, that has the data path and the control signals to transfer data
between interface and device is _____
a) BUS side
b) Port side
c) Hardwell side
d) Software side
View Answer
Answer: b
Explanation: This side connects the device to the motherboard.
3. What is the interface circuit?

a) Helps in installing of the software driver for the device
b) Houses the buffer that helps in data transfer
c) Helps in the decoding of the address on the address BUs
View Answer
Answer: c
Explanation: Once the address is put on the BUS the interface circuit decodes the address and uses the
buffer space to transfer data.
4. The conversion from parallel to serial data transmission and vice versa takes place inside the interface
circuits.
a) True
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b) False
View Answer
Answer: a
Explanation: By doing this the interface circuits provide a better interconnection between devices.
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5. The parallel mode of communication is not suitable for long devices because of ______
a) Timing skew
b) Memory access delay
c) Latency
View Answer
R
Answer: a
A
Explanation: None.
6. The Interface circuits generate the appropriate timing signals required by the BUS control scheme.
a) True
b) False
View Answer
Answer: a
Explanation: The interface circuits generate the required clock signal for the synchronous mode of
transfer.
7. The status lags required for data transfer is present in _____

a) Device
b) Device driver
c) Interface circuit
View Answer
Answer: c
Explanation: The circuit holds the lags which are required for data transfers.
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8. User programmable terminals that combine VDT hardware with built-in microprocessor is _____
a) KIPs
b) Pc
c) Mainframe
d) Intelligent terminals
View Answer
Answer: d
Explanation: None.
9. Which most popular input device is used today for interactive processing and for the one line entry of
data for batch processing?
a) Mouse
b) Magnetic disk
c) Visual display terminal
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d) Card punch
View Answer
Answer: a
Explanation: In batch processing systems the processes are grouped into batches and they’re executed
in batches.
10. The use of spooler programs or _______ Hardware allows PC operators to do the processing work at
the same time a printing operation is in progress.
a) Registers
b) Memory
c) Buffer
d) CPU
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View Answer
A
Answer: c
Explanation: When the processor is busy with the process the data to be printed is stored in the buffer.
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Standard I/O Interfaces
A
« Prev Next »
focuses on “Standard I/O Interfaces”.
1. ______ is used as an intermediate to extend the processor BUS.

a) Bridge
b) Router
c) Connector
d) Gateway
View Answer
Answer: a
Explanation: The bridge circuit is basically used to extend the processor BUS to connect devices.
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2. ________ is an extension of the processor BUS.

a) SCSI BUS
b) USB
c) PCI BUS
View Answer
Answer: c
Explanation: The PCI BUS is used as an extension of the processor BUS and devices connected to it, is like
connected to the Processor itself.
3. What is the full form of ISA?

a) International American Standard
b) Industry Standard Architecture
c) International Standard Architecture
View Answer
Answer: b
Explanation: The ISA is an architectural standard developed by IBM for its PC’s.
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4. What is the full form of ANSI?

b) Architectural National Standards Institute
c) Asian National Standards Institute
View Answer
Answer: a
Explanation: The ANSI is one of the standard architecture used by companies in designing the systems.
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5. The video devices are connected to ______ BUS.

a) PCI
R
b) USB
c) HDMI
A
d) SCSI
View Answer
Answer: d
Explanation: The SCSI BUS is used to connect the video devices to a processor by providing a parallel
BUS.
6. SCSI stands for ___________

a) Signal Computer System Interface
b) Small Computer System Interface
c) Small Coding System Interface
d) Signal Coding System Interface
View Answer
Answer: b
Explanation: The SCSI BUS is used to connect disks and video controllers.
7. ISO stands for __________

a) International Standards Organisation
b) International Software Organisation
c) Industrial Standards Organisation
d) Industrial Software Organisation
View Answer
Answer: a
Explanation: The ISO is yet another architectural standard, used to design systems.
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8. The system developed by IBM with ISA architecture is ______

a) SPARC
b) SUN-SPARC
c) PC-AT
View Answer
Answer: c
Explanation: None.
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9. IDE disk is connected to the PCI BUS using ______ interface.

a) ISA
b) ISO
c) ANSI
d) IEEE
View Answer
Answer: a
Explanation: None.
10. IDE stands for _________

a) Integrated Device Electronics
b) International Device Encoding
R
c) Industrial Decoder Electronics
d) International Decoder Encoder
A
View Answer
Answer: a
Explanation: The IDE interface is used to connect the hard disk to the processor in most of the Pentium
processors.
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A
Parallel Port
« Prev Next »
focuses on “Parallel Port”.
1. The _____ circuit enables the generation of the ASCII code when the key is pressed.
a) Generator
b) Debouncing
c) Encoder
d) Logger
View Answer
Answer: c
Explanation: The signal generated upon the pressing of a button is encoded by the encoder circuit into
the corresponding ASCII value.
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2. To overcome multiple signals being generated upon a single press of the button, we make use of ______
a) Generator circuit
b) Debouncing circuit
c) Multiplexer
d) XOR circuit
View Answer
Answer: b
Explanation: When the button is pressed, the contact surfaces bounce and hence it might lead to the
generation of multiple signals. In order to overcome this, we use Debouncing circuits.
3. The best mode of connection between devices which need to send or receive large amounts of data
over a short distance is _____
a) BUS
b) Serial port
c) Parallel port
d) Isochronous port
View Answer
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Answer: c
Explanation: The parallel port transfers around 8 to 16 bits of data simultaneously over the lines, hence
increasing transfer rates.
4. The output of the encoder circuit is/are ______

a) ASCII code
b) ASCII code and the valid signal
c) Encoded signal
View Answer
Answer: b
Explanation: The encoder outputs the ASCII value along with the valid signal which indicates that a key
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was pressed.
A
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5. The disadvantage of using a parallel mode of communication is ______

a) It is costly
b) Leads to erroneous data transfer
c) Security of data
View Answer
Answer: a
Explanation: The parallel mode of data transfer is costly as it involves data being sent over parallel lines.
6. In a 32 bit processor, the A0 bit of the address line is connected to _____ of the parallel port interface.
a) Valid bit
b) Idle bit
c) Interrupt enable bit
d) Status or data register
View Answer
Answer: d
Explanation: None.
7. The Status lag circuit is implemented using _____

a) RS lip lop
b) D lip lop
c) JK lip lop
d) Xor circuit
View Answer
Answer: b
Explanation: The circuit is implemented using the edge triggered D lip lop, that is triggered on the rising
edge of the valid signal.
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8. In the output interface of the parallel port, along with the valid signal ______ is also sent.
a) Data
b) Idle signal
c) Interrupt
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d) Acknowledge signal
View Answer
Answer: b
Explanation: The idle signal is used to check if the device is idle and ready to receive data.
9. DDR stands for __________

a) Data Direction Register
b) Data Decoding Register
c) Data Decoding Rate
View Answer
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Answer: a
Explanation: This register is used to control the low of data from the DATAOUT register.
A
10. In a general 8-bit parallel interface, the INTR line is connected to _______
a) Status and Control unit
b) DDR
c) Register select
View Answer
Answer: a
Explanation: None.
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Serial Port
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focuses on “Serial Port”.
1. The mode of transmission of data, where one bit is sent for each clock cycle is ______
a) Asynchronous
b) Parallel
c) Serial
d) Isochronous
View Answer
Answer: d
Explanation: In the isochronous mode of transmission, each bit of the data is sent per each cycle.
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2. The transformation between the Parallel and serial ports is done with the help of ______
a) Flip lops
b) Logic circuits
c) Shift registers
View Answer
Answer: c
Explanation: The Shift registers are used to output the data in the desired format based on the need.
3. The serial port is used to connect basically _____ and processor.

a) I/O devices
b) Speakers
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c) Printer
d) Monitor
View Answer
Answer: a
Explanation: The serial port is used to connect the keyboard and other devices which input or output
one bit at a time.
4. The double buffer is used for _________

a) Enabling retrieval of multiple bits of input
b) Combining the input and output operations
c) Extending the buffer capacity
R
View Answer
A
Answer: a
Explanation: None.
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5. ______ to increase the lexibility of the serial ports.

a) The wires used for ports is changed
b) The ports are made to allow different clock signals for input and output
c) The drivers are modi ied
View Answer
Answer: b
Explanation: The ports are made more lexible by enabling the input or output of different clock signals
for different devices.
6. UART stands for ________

a) Universal Asynchronous Relay Transmission
b) Universal Accumulator Register Transfer
c) Universal Asynchronous Receiver Transmitter
View Answer
Answer: c
Explanation: The UART is a standard developed for designing serial ports.
7. The key feature of UART is _________

a) Its architectural design
b) Its simple implementation
c) Its general purpose usage
d) Its enhancement of connecting low speed devices
View Answer
Answer: d
Explanation: None.
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8. The data transfer in UART is done in ______

a) Asynchronous start stop format
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b) Synchronous start stop format

c) Isochronous format
d) EBDIC format
View Answer
Answer: a
Explanation: This basically means that the data transfer is done in asynchronous mode.
9. The standard used in serial ports to facilitate communication is _____

a) RS-246
b) RS-LNK
c) RS-232-C
d) Both RS-246 and RS-LNK
R
View Answer
A
Answer: c
Explanation: This is a standard that acts as a protocol for message communication involving serial ports.
10. In a serial port interface, the INTR line is connected to _____

a) Status register
b) Shift register
c) Chip select
View Answer
Answer: a
Explanation: None.
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20. Computer Organization Questions and Answers – Synchronous BUS
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PCI BUS-1
« Prev Next »
focuses on “PCI BUS-1”.
1. The PCI follows a set of standards primarily used in _____ PC’s.

a) Intel
b) Motorola
c) IBM
d) SUN
View Answer
Answer: c
Explanation: The PCI BUS has a closer resemblance to IBM architecture.
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2. The ______ is the BUS used in Macintosh PC’s.

a) NuBUS
b) EISA
c) PCI
View Answer
Answer: a
Explanation: The NuBUS is an extension of the processor BUS in Macintosh PC’s.
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3. The key feature of the PCI BUS is _________

a) Low cost connectivity
b) Plug and Play capability
c) Expansion of Bandwidth
View Answer
Answer: b
Explanation: The PCI BUS was the irst to introduce plug and play interface for I/O devices.
4. PCI stands for _______

a) Peripheral Component Interconnect
b) Peripheral Computer Internet
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c) Processor Computer Interconnect
d) Processor Cable Interconnect
A
View Answer
Answer: a
Explanation: The PCI BUS is used as an extension for the processor BUS.
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5. The PCI BUS supports _____ address space/s.

a) I/O
b) Memory
c) Con iguration
View Answer
Answer: d
Explanation: The PCI BUS is mainly built to provide a wide range of connectivity for devices.
6. ______ address space gives the PCI its plug and plays capability.
a) Con iguration
b) I/O
c) Memory
View Answer
Answer: a
Explanation: The con iguration address space is used to store the details of the connected device.
7. _____ provides a separate physical connection to the memory.

a) PCI BUS
b) PCI interface
c) PCI bridge
d) Switch circuit
View Answer
Answer: c
Explanation: The PCI bridge is a circuit that acts as a bridge between the BUS and the memory.
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8. When transferring data over the PCI BUS, the master as to hold the address until the completion of the
transfer to the slave.
a) True
b) False
View Answer
Answer: b
Explanation: The address is stored by the slave in a buffer and hence it is not required by the master to
hold it.
9. The master is also called as _____ in PCI terminology.

a) Initiator
b) Commander
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c) Chief
d) Starter
A
View Answer
Answer: a
Explanation: The Master is also called as an initiator in PCI terminology as it is the one that initiates a
data transfer.
10. Signals whose names end in ____ are asserted in the low voltage state.
a) $
b) #
c) *
d) !
View Answer
Answer: b
Explanation: None.
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PCI BUS-2
« Prev Next »
This set of Computer Organization Interview Questions and Answers focuses on “PCI BUS-2”.
1. A complete transfer operation over the BUS, involving the address and a burst of data is called _____
a) Transaction
b) Transfer
c) Move
d) Procedure
View Answer
Answer: a
Explanation: None.
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2. The device connected to the BUS are given addresses of ____ bit.
a) 24
b) 64
c) 32
d) 16
View Answer
Answer: b
Explanation: Each of the devices connected to the BUS will be allocated an address during the
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initialization phase.
3. The PCI BUS has _____ interrupt request lines.

a) 6
b) 1
c) 4
d) 3
View Answer
Answer: c
Explanation: The interrupt request lines are used by the devices connected to raise the interrupts.
4. _____ signal is sent by the initiator to indicate the duration of the transaction.
R
a) FRAME#
b) IRDY#
A
c) TMY#
d) SELD#
View Answer
Answer: a
Explanation: The FRAME signal is used to indicate the time required by the device.
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5. ______ signal is used to enable commands.

a) FRAME#
b) IRDY#
c) TMY#
d) c/BE#
View Answer
Answer: d
Explanation: The signal is used to enable 4 command lines.
6. IRDY# signal is used for _______

a) Selecting the interrupt line
b) Sending an interrupt
c) Saying that the initiator is ready
View Answer
Answer: c
Explanation: The initiator transmits this signal to tell the target that it is ready.
7. The signal used to indicate that the slave is ready is _____

a) SLRY#
b) TRDY#
c) DSDY#
View Answer
Answer: b
Explanation: None.
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8. DEVSEL# signal is used _________

a) To select the device
b) To list all the devices connected
c) By the device to indicate that it is ready for a transaction
View Answer
Answer: c
Explanation: This is signal is activated by the device after it as recognized the address and commands put
on the BUS.
9. The signal used to initiate device select ________

a) IRDY#
R
b) S/BE
c) DEVSEL#
A
d) IDSEL#
View Answer
Answer: d
Explanation: This signal is used to initialization of device select.
10. The PCi BUS allows us to connect _______ I/O devices.

a) 21
b) 13
c) 9
d) 11
View Answer
Answer: a
Explanation: The PCI BUS allows only 21 devices to be connected as only the higher order 21 bits of the
32 bit address space is used to specify the device.
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Choice Questions and Answers on Computer Organisation and Architecture

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16. Computer Organization Questions and Answers – Basic Operational Concept
17. Computer Organization Questions and Answers – Address Translation – 2
18. Computer Organization Questions and Answers – PCI BUS-1
19. Computer Organization Questions and Answers – SCSI BUS-2
20. Computer Organization Questions and Answers – Interface Circuits
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SCSI BUS-1
« Prev Next »
focuses on “SCSI BUS-1”.
1. The key features of the SCSI BUS are _________

a) The cost effective connective media
b) The ability overlap data transfer requests
c) The highly ef icient data transmission
View Answer
Answer: b
Explanation: The SCSI BUS can overlap various data transfer requests by the devices.
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2. In a data transfer operation involving SCSI BUS, the control is with ______
a) Initiator
b) Target
c) SCSI controller
d) Target Controller
View Answer
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Answer: d
Explanation: The initiator involves in the arbitration process and after winning the BUS it’ll hand over the
control to the target controller.
3. In SCSI transfers the processor is not aware of the data being transferred.
a) True
b) False
View Answer
Answer: a
Explanation: The processor or the controller is unaware of the data being transferred.
4. What is DB(P) line?
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a) That the data line is carrying the device information
b) That the data line is carrying the parity information
A
c) That the data line is partly closed
d) That the data line is temporarily occupied
View Answer
Answer: b
Explanation: None.
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5. The BSY signal signi ies _________

a) The BUs is busy
b) The controller is busy
c) The Initiator is busy
d) The Target is Busy
View Answer
Answer: a
Explanation: This signal is generally initiated when the BUS is currently occupied in an operation.
6. The SEL signal signi ies _________

a) The initiator is selected
b) The device for BUS control is selected
c) That the target is being selected
View Answer
Answer: b
Explanation: This signal is usually asserted during the selection or reselection process.
7. ________ signal is asserted when the initiator wishes to send a message to the target.
a) MSG
b) APP
c) SMS
d) ATN
View Answer
Answer: d
Explanation: The ATN signal is short for attention, which is used to intimate the target that the initiator
sent a message to it.
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8. The MSG signal is used _________

a) To send a message to the target
b) To receive a message from the mailbox
c) To tell that the information being sent is a message
View Answer
Answer: c
Explanation: None.
9. _____ is used to reset all the device controls to their startup state.
R
a) SRT
b) RST
A
c) ATN
View Answer
Answer: b
Explanation: None.
10. The SCSI BUS uses ______ arbitration.

a) Distributed
b) Centralised
c) Daisy chain
d) Hybrid
View Answer
Answer: a
Explanation: The SCSI uses distributed arbitration to select the device to give the BUS control.
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SCSI BUS-2
« Prev Next »
This set of Computer Organization Questions and Answers for Freshers focuses on “SCSI BUS-2”.
1. SCSI stands for ________

a) Small Computer System Interface
b) Switch Computer system Interface
c) Small Component System Interface
View Answer
Answer: a
Explanation: The SCSI BUS is one of the expansion BUSes used in a system.
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2. ANSI stands for _________

a) American National System Interface
b) ASCII National Standard Interface
c) American Network System Interface
d) American National Standard Institute
View Answer
Answer: d
Explanation: This a standard for designing BUSes and other system components.
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3. A narrow SCSI BUS has _____ data lines.

a) 6
b) 8
c) 16
d) 4
View Answer
Answer: b
Explanation: The SCSI BUS which is narrow is capable of transferring 8 bits of data at a time.
4. Single ended transmission means _________

a) That all the signals have a similar bit pattern
b) That the signals have a common source
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c) That the signals have a common ground return
d) That the signals have a similar voltage signature
A
View Answer
Answer: c
Explanation: These type of signals are a common feature of the SCSI BUS.
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5. HVD stands for _________

a) High Voltage Differential
b) High Voltage Density
c) High Video De inition
View Answer
Answer: a
Explanation: This is a type of signaling which uses 5v of current.
6. For better transfer rates on the SCSI BUS the length of the cable is limited to ______
a) 2m
b) 4m
c) 1.3m
d) 1.6m
View Answer
Answer: d
Explanation: To increase the transmission rate in SCSI in SE mode of transfer the wire length is restricted
to 1.6m.
7. The maximum number of devices that can be connected to SCSI BUS is ______
a) 12
b) 10
c) 16
d) 8
View Answer
Answer: c
Explanation: None.
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8. The SCSI BUS is connected to the processor through _____

a) SCSI Controller
b) Bridge
c) Switch
View Answer
Answer: a
Explanation: This is used to coordinate and monitor the data transfer over the BUS.
9. The mode of data transfer used by the controller is _____

a) Interrupt
b) DMA
R
c) Asynchronous
d) Synchronous
A
View Answer
Answer: b
Explanation: None.
10. The data is stored on the disk in the form of blocks called _____
a) Pages
b) Frames
c) Sectors
d) Tables
View Answer
Answer: c
Explanation: The data is stored on the disk in the form of a collection of blocks called as sectors.
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USB – 1
« Prev Next »
focuses on “USB – 1”.
1. The transfer rate, when the USB is operating in low-speed of operation is _____
a) 5 Mb/s
b) 12 Mb/s
c) 2.5 Mb/s
d) 1.5 Mb/s
View Answer
Answer: d
Explanation: The USB has two rates of operation the low-speed and the full-speed one.
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2. The high speed mode of operation of the USB was introduced by _____
a) ISA
b) USB 3.0
c) USB 2.0
d) ANSI
View Answer
Answer: c
Explanation: The high-speed mode of operation was introduced with USB 2.0, which enabled the USB to
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operate at 480 Mb/s.
3. The sampling process in speaker output is a ________ process.

a) Asynchronous
b) Synchronous
c) Isochronous
View Answer
Answer: c
Explanation: The isochronous process means each bit of data is separated by a time interval.
4. The USB device follows _______ structure.
R
a) List
b) Huffman
A
c) Hash
d) Tree
View Answer
Answer: d
Explanation: The USB has a tree structure with the root hub at the centre.
5. The I/O devices form the _____ of the tree structure.

a) Leaves
b) Subordinate roots
c) Left subtrees
d) Right subtrees
View Answer
Answer: a
Explanation: The I/o devices form the leaves of the structure.
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6. USB is a parallel mode of transmission of data and this enables for the fast speeds of data transfers.
a) True
b) False
View Answer
Answer: b
Explanation: The USB does a serial mode of data transfer.
7. In USB the devices can communicate with each other.

a) True
b) False
View Answer
Answer: b
Explanation: It allows only the host to communicate with the devices and not between themselves.
8. The device can send a message to the host by taking part in _____ for the communication path.
a) Arbitration
b) Polling
c) Prioritizing
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View Answer
Answer: b
Explanation: None.
9. When the USB is connected to a system, its root hub is connected to the ________
a) PCI BUS
b) SCSI BUS
c) Processor BUS
d) IDE
View Answer
R
Answer: c
Explanation: The USB’s root is connected to the processor directly using the BUS.
A
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10. The devices connected to USB is assigned a ____ address.

a) 9 bit
b) 16 bit
c) 4 bit
d) 7 bit
View Answer
Answer: d
Explanation: To make it easier for recognition the devices are given 7 bit addresses.
11. The USB address space can be shared by the user’s memory space.
a) True
b) False
View Answer
Answer: b
Explanation: The USB memory space is not under any address spaces and cannot be accessed.
12. The initial address of a device just connected to the HUB is ________
a) AHFG890
b) 0000000
c) FFFFFFF
d) 0101010
View Answer
Answer: b
Explanation: By standard, the usual address of a new device is zero.
13. Locations in the device to or from which data transfers can take place is called ________
a) End points
b) Hosts
c) Source
View Answer
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Answer: a
Explanation: None.
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14. A USB pipe is a ______ channel.

a) Simplex
b) Half-Duplex
c) Full-Duplex
d) Both Simplex and Full-Duplex
View Answer
Answer: c
Explanation: This means that the pipe is bi-directional in sending messages or information.
R
15. The type/s of packets sent by the USB is/are _______
A
a) Data
b) Address
c) Control
d) Both Data and Control
View Answer
Answer: d
Explanation: This means that the USB gets both data and control signals required for the transfer
operation.

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USB – 2
« Prev Next »
This set of Computer Organization Interview Questions and Answers for freshers focuses on “USB-2”.
1. The irst ield of any packet is _____

a) PID
b) ADDR
c) ENDP
d) CRC16
View Answer
Answer: a
Explanation: The PID is the ield that is used to identify the device (the device id).
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2. The 4 bit PID’s are transmitted twice.

a) True
b) False
View Answer
Answer: a
Explanation: The ields are transmitted twice, once with the true values and the second time with the
complemented values.
3. The last ield in the packet is ______

a) PID
b) ADDR
c) ENDP
d) CRC
View Answer
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Answer: d
Explanation: The last 5 bits of the packet is used for error checking, that is cyclic redundancy check.
4. The CRC bits are computed based on the values of the _____
a) PID
b) ADDR
c) ENDP
d) Both ADDR and ENDP
View Answer
Answer: d
Explanation: The CRC bits are calculated based on the values of the address and endp.
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5. The data packets can contain data upto ______
A
a) 512 bytes
b) 256 bytes
c) 1024 bytes
d) 2 KB
View Answer
Answer: c
Explanation: None.
6. The most important objective of the USB is to provide ______

a) Isochronous transmission
b) Plug and play
c) Easy device connection
View Answer
Answer: d
Explanation: The above are all the common features of the USB.
7. The transmission over the USB is divided into ____

a) Frames
b) Pages
c) Packets
d) Tokens
View Answer
Answer: a
Explanation: To support the isochronous mode of operation the usb transmission is divided into frames.
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8. The _____ signal is used to indicate the beginning of a new frame.

a) Start
b) SOF
c) BEG
View Answer
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Answer: b
Explanation: The SOF(State Of Frame) is used to indicate the beginning of a new frame.
9. The SOF is transmitted every ______

a) 1s
b) 5s
c) 1ms
d) 1Us
View Answer
Answer: c
Explanation: None.
R
10. The power speci ication of usb is _____
a) 5v
A
b) 10v
c) 24v
d) 10v
View Answer
Answer: a
Explanation: None.
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Static Memories
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focuses on “Static Memories”.
1. The duration between the read and the mfc signal is ______
a) Access time
b) Latency
c) Delay
d) Cycle time
View Answer
Answer: a
Explanation: The time between the issue of a read signal and the completion of it is called memory
access time.
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2. The minimum time delay between two successive memory read operations is ______
a) Cycle time
b) Latency
c) Delay
View Answer
Answer: a
Explanation: The Time taken by the cpu to end one read operation and to start one more is cycle time.
3. MFC is used to _________

a) Issue a read signal
b) Signal to the device that the memory read operation is complete
c) Signal the processor the memory operation is complete
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d) Assign a device to perform the read operation

View Answer
Answer: c
Explanation: The MFC stands for memory Function Complete.
4. __________ is the bottleneck, when it comes computer performance.

b) Memory cycle time
c) Delay
d) Latency
View Answer
R
Answer: b
Explanation: The processor can execute instructions faster than they’re fetched, hence cycle time is the
A
bottleneck for performance.
5. The logical addresses generated by the cpu are mapped onto physical memory by ____________
a) Relocation register
b) TLB
c) MMU
View Answer
Answer: c
Explanation: The MMU stands for memory management unit, which is used to map logical address onto
the physical address.
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6. VLSI stands for ___________

a) Very Large Scale Integration
b) Very Large Stand-alone Integration
c) Volatile Layer System Interface
View Answer
Answer: a
Explanation: None.
7. The cells in a row are connected to a common line called ______

a) Work line
b) Word line
c) Length line
d) Principle diagonal
View Answer
Answer: b
Explanation: This means that the cell contents together form one word of instruction or data.
8. The cells in each column are connected to ______

a) Word line
b) Data line
c) Read line
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d) Sense/ Write line

View Answer
Answer: d
Explanation: The cells in each column are connected to the sense/write circuit using two bit lines and
which is in turn connected to the data lines.
9. The word line is driven by the _____

a) Chip select
b) Address decoder
c) Data line
d) Control line
View Answer
R
Answer: b
A
Explanation: None.
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10. A 16 X 8 Organisation of memory cells, can store upto _____

a) 256 bits
b) 1024 bits
c) 512 bits
d) 128 bits
View Answer
Answer: d
Explanation: It can store upto 128 bits as each cell can hold one bit of data.
11. A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be
organized into _____
a) 128 X 8
b) 256 X 4
c) 512 X 2
d) 1024 X 1
View Answer
Answer: d
Explanation: All the others require less than 10 address bits.
12. Circuits that can hold their state as long as power is applied is _______
a) Dynamic memory
b) Static memory
c) Register
d) Cache
View Answer
Answer: b
Explanation: None.
13. The number of external connections required in 16 X 8 memory organisation is _____

a) 14
b) 19
c) 15
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d) 12
View Answer
Answer: a
Explanation: In the 14, 8-data lines,4-address lines and 2 are sense/write and CS signals.
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14. The advantage of CMOS SRAM over the transistor one’s is _________
a) Low cost
b) High ef iciency
c) High durability
d) Low power consumption
View Answer
R
Answer: d
A
Explanation: This is because the cell consumes power only when it is being accessed.
15. In a 4M-bit chip organisation has a total of 19 external connections.then it has _______ address if 8
data lines are there.
a) 10
b) 8
c) 9
d) 12
View Answer
Answer: c
Explanation: To have 8 data lines and 19 external connections it has to have 9 address lines(i.e 512 x 8
organisation).

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Asynchronous DRAM
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focuses on “Asynchronous DRAM”.
1. The Reason for the disregarding of the SRAM’s is ________

a) Low Ef iciency
b) High power consumption
c) High Cost
View Answer
Answer: c
Explanation: The reason for the high cost of the SRAM is because of the usage of more number of
transistors.
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2. The disadvantage of DRAM over SRAM is/are _______

a) Lower data storage capacities
b) Higher heat dissipation
c) The cells are not static
View Answer
Answer: c
Explanation: This means that the cells won’t hold their state inde initely.
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3. The reason for the cells to lose their state over time is ________
a) The lower voltage levels
b) Usage of capacitors to store the charge
c) Use of Shift registers
View Answer
Answer: b
Explanation: Since capacitors are used the charge dissipates over time.
4. The capacitors lose the charge over time due to ________

a) The leakage resistance of the capacitor
b) The small current in the transistor after being turned on
R
c) The defect of the capacitor
A
View Answer
Answer: a
Explanation: The capacitor loses charge due to the backward current of the transistor and due to the
small resistance.
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5. _________ circuit is used to restore the capacitor value.

a) Sense amplify
b) Signal ampli ier
c) Delta modulator
View Answer
Answer: a
Explanation: The sense ampli ier detects if the value is above or below the threshold and then restores it.
6. To reduce the number of external connections required, we make use of ______

a) De-multiplexer
b) Multiplexer
c) Encoder
d) Decoder
View Answer
Answer: b
Explanation: We multiplex the various address lines onto fewer pins.
7. The processor must take into account the delay in accessing the memory location, such memories are
called ______
a) Delay integrated
b) Asynchronous memories
c) Synchronous memories
d) Isochronous memories
View Answer
Answer: b
Explanation: None.
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8. To get the row address of the required data ______ is enabled.

a) CAS
b) RAS
c) CS
d) Sense/write
View Answer
Answer: b
Explanation: This makes the contents of the row required refreshed.
9. In order to read multiple bytes of a row at the same time, we make use of ______
a) Latch
b) Shift register
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c) Cache
d) Memory extension
A
View Answer
Answer: a
Explanation: The latch makes it easy to ready multiple bytes of data of the same row simultaneously by
just giving the consecutive column address.
10. The block transfer capability of the DRAM is called ________

a) Burst mode
b) Block mode
c) Fast page mode
d) Fast frame mode
View Answer
Answer: c
Explanation: None.
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Synchronous DRAM
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focuses on “Synchronous DRAM”.
1. The difference between DRAM’s and SDRAM’s is/are ________

a) The DRAM’s will not use the master slave relationship in data transfer
b) The SDRAM’s make use of clock
c) The SDRAM’s are more power ef icient
View Answer
Answer: d
Explanation: The SDRAM’s make use of clock signals to synchronize their operation.
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2. The difference in the address and data connection between DRAM’s and SDRAM’s is _______
a) The usage of more number of pins in SDRAM’s
b) The requirement of more address lines in SDRAM’s
c) The usage of a buffer in SDRAM’s
View Answer
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Answer: c
Explanation: The SDRAM uses buffered storage of address and data.
3. A _______ is used to restore the contents of the cells.

a) Sense ampli ier
b) Refresh counter
c) Restorer
View Answer
Answer: b
Explanation: The Counter helps to restore the charge on the capacitor.
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4. The mode register is used to _______
a) Select the row or column data transfer mode
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b) Select the mode of operation
c) Select mode of storing the data
View Answer
Answer: b
Explanation: The mode register is used to choose between burst mode or bit mode of operation.
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5. In a SDRAM each row is refreshed every 64ms.

a) True
b) False
View Answer
Answer: a
Explanation: None.
6. The time taken to transfer a word of data to or from the memory is called as ______
a) Access time
b) Cycle time
c) Memory latency
View Answer
Answer: c
Explanation: The performance of the memory is measured by means of latency.
7. In SDRAM’s buffers are used to store data that is read or written.

a) True
b) False
View Answer
Answer: a
Explanation: In SDRAM’s all the bytes of data to be read or written are stored in the buffer until the
operation is complete.
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8. The SDRAM performs operation on the _______

a) Rising edge of the clock
b) Falling edge of the clock
c) Middle state of the clock
d) Transition state of the clock
View Answer
Answer: a
Explanation: The SDRAM’s are edge-triggered.
9. DDR SDRAM’s perform faster data transfer by _______

a) Integrating the hardware
b) Transferring on both edges
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c) Improving the clock speeds
d) Increasing the bandwidth
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View Answer
Answer: b
Explanation: By transferring data on both the edges the bandwidth is effectively doubled.
10. To improve the data retrieval rate ____________

a) The memory is divided into two banks
b) The hardware is changed
c) The clock frequency is increased
View Answer
Answer: a
Explanation: The division of memory into two banks makes it easy to access two different words at each
edge of the clock.
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Large Memories
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focuses on “Large Memories”.
1. The chip can be disabled or cut off from an external connection using ______
a) Chip select
b) LOCK
c) ACPT
d) RESET
View Answer
Answer: a
Explanation: The chip gets enabled if the CS is set otherwise the chip gets disabled.
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2. To organise large memory chips we make use of ______

a) Integrated chips
b) Upgraded hardware
c) Memory modules
View Answer
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Answer: c
Explanation: The cell blocks are arranged and put in a memory module.
3. The less space consideration as lead to the development of ________ (for large memories).
a) SIMM’s
b) DIMS’s
c) SRAM’s
d) Both SIMM’s and DIMS’s
View Answer
Answer: d
Explanation: The SIMM (single inline memory module) or DIMM (dual inline memory module) occupy
less space while providing greater memory space.
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4. The SRAM’s are basically used as ______
A
a) Registers
b) Caches
c) TLB
d) Buffer
View Answer
Answer: b
Explanation: The SRAM’s are used as caches as their operation speed is very high.
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5. The higher order bits of the address are used to _____

a) Specify the row address
b) Specify the column address
c) Input the CS
View Answer
Answer: a
Explanation: None.
6. The address lines multiplexing is done using ______

a) MMU
b) Memory controller unit
c) Page table
d) Overlay generator
View Answer
Answer: b
Explanation: This unit multiplexes the various address lines to lesser pins on the chip.
7. The controller multiplexes the addresses after getting the _____ signal.
a) INTR
b) ACK
c) RESET
d) Request
View Answer
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Answer: d
Explanation: The controller gets the request from the device needing the memory read or write
operation and then it multiplexes the address.
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8. The RAS and CAS signals are provided by the ______

a) Mode register
b) CS
c) Memory controller
View Answer
Answer: c
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Explanation: The multiplexed signal of the controller is split into RAS and CAS.
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9. Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read operation.
Then the refresh overhead of the chip is ______
a) 0.0021
b) 0.0038
c) 0.0064
d) 0.0128
View Answer
Answer: b
Explanation: The refresh overhead is calculated by taking into account the total time for refreshing and
the interval of each refresh.
10. When DRAM’s are used to build a complex large memory, then the controller only provides the
refresh counter.
a) True
b) False
View Answer
Answer: a
Explanation: None.
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RamBus Memory
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focuses on “RamBus Memory”.
1. RAMBUS is better than the other memory chips in terms of ________

a) Ef iciency
b) Speed of operation
c) Wider bandwidth
View Answer
Answer: b
Explanation: The RAMBUS is much advanced mode of memory storage.
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2. The key feature of the RAMBUS tech is ________

a) Greater memory utilisation
b) Ef iciency
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c) Speed of transfer
View Answer
Answer: c
Explanation: The RAMBUS was developed basically to lessen the data transfer time.
3. The increase in operation speed is done by ________________

a) Reducing the reference voltage
b) Increasing the clk frequency
c) Using enhanced hardware
View Answer
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Answer: a
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Explanation: The reference voltage is reduced from the Vsupply about 2v.
4. The data is transferred over the RAMBUS as _______

a) Packets
b) Blocks
c) Swing voltages
d) Bits
View Answer
Answer: c
Explanation: By using voltage swings to transfer data, the transfer rate along with ef iciency is improved.
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5. The type of signaling used in RAMBUS is ______

a) CLK signaling
b) Differential signaling
c) Integral signaling
View Answer
Answer: b
Explanation: The differential signaling basically means using voltage swings to transmit data.
6. The special communication used in RAMBUS are _________

a) RAMBUS channel
b) D-link
c) Dial-up
View Answer
Answer: a
Explanation: The special communication link is used to provide the necessary design and required
hardware for the transmission.
7. The original design of the RAMBUS required for ________ data lines.
a) 4
b) 6
c) 8
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d) 9
View Answer
Answer: d
Explanation: Out of the 9 data lines, 8 were used for data transmission and the one left was used for
parity checking.
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8. The RAMBUS requires specially designed memory chips similar to _____

a) SRAM
b) SDRAM
c) DRAM
d) DDRRAM
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View Answer
A
Answer: c
Explanation: The special memory chip should be able to transmit data on both the edges and is called as
RDRAM’s.
9. A RAMBUS which has 18 data lines is called as _______

a) Extended RAMBUS
b) Direct RAMBUS
c) Multiple RAMBUS
d) Indirect RAMBUS
View Answer
Answer: b
Explanation: The direct RAMBUS is used to transmit 2 bytes of data at a time.
10. The RDRAM chips assembled into larger memory modules called ______
a) RRIM
b) DIMM
c) SIMM
View Answer
Answer: a
Explanation: None.
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Read-Only Memory
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focuses on “Read-Only Memory”.
1. If the transistor gate is closed, then the ROM stores a value of 1.

a) True
b) False
View Answer
Answer: b
Explanation: If the gate of the transistor is closed then, the value of zero is stored in the ROM.
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2. PROM stands for __________

a) Programmable Read Only Memory
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b) Pre-fed Read Only Memory

c) Pre-required Read Only Memory
d) Programmed Read Only Memory
View Answer
Answer: a
Explanation: It allows the user to program the ROM.
3. The PROM is more effective than ROM chips in regard to _______

a) Cost
b) Memory management
c) Speed of operation
d) Both Cost and Speed of operation
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View Answer
A
Answer: d
Explanation: The PROM is cheaper than ROM as they can be programmed manually.
4. The difference between the EPROM and ROM circuitry is _____

a) The usage of MOSFET’s over transistors
b) The usage of JFET’s over transistors
c) The usage of an extra transistor
View Answer
Answer: c
Explanation: The EPROM uses an extra transistor where the ground connection is there in the ROM chip.
5. The ROM chips are mainly used to store _______

a) System iles
b) Root directories
c) Boot iles
d) Driver iles
View Answer
Answer: c
Explanation: The ROM chips are used to store boot iles required for the system startup.
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6. The contents of the EPROM are erased by ________

a) Overcharging the chip
b) Exposing the chip to UV rays
c) Exposing the chip to IR rays
d) Discharging the Chip
View Answer
Answer: b
Explanation: To erase the contents of the EPROM the chip is exposed to the UV rays, which dissipate the
charge on the transistor.
7. The disadvantage of the EPROM chip is _______

a) The high cost factor
b) The low ef iciency
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c) The low speed of operation

d) The need to remove the chip physically to reprogram it
View Answer
Answer: d
Explanation: None.
8. EEPROM stands for Electrically Erasable Programmable Read Only Memory.

a) True
b) False
View Answer
Answer: a
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Explanation: The disadvantages of the EPROM led to the development of the EEPROM.
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9. The disadvantage of the EEPROM is/are ________
a) The requirement of different voltages to read, write and store information
b) The Latency read operation
c) The inef icient memory mapping schemes used
View Answer
Answer: a
Explanation: None.
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10. The memory devices which are similar to EEPROM but differ in the cost effectiveness is ______
a) Memory sticks
b) Blue-ray devices
c) Flash memory
d) CMOS
View Answer
Answer: c
Explanation: The lash memory functions similar to the EEPROM but is much cheaper.
11. The only difference between the EEPROM and lash memory is that the latter doesn’t allow bulk data
to be written.
a) True
b) False
View Answer
Answer: a
Explanation: This is not permitted as the previous contents of the cells will be overwritten.
12. The lash memories ind application in ______

a) Super computers
b) Mainframe systems
c) Distributed systems
d) Portable devices
View Answer
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Answer: d
Explanation: The lash memories low power requirement enables them to be used in a wide range of
hand held devices.
13. The memory module obtained by placing a number of lash chips for higher memory storage called
as _______
a) FIMM
b) SIMM
c) Flash card
d) RIMM
View Answer
Answer: c
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Explanation: None.
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14. The lash memory modules designed to replace the functioning of a hard disk is ______
a) RIMM
b) Flash drives
c) FIMM
d) DIMM
View Answer
Answer: b
Explanation: The lash drives have been developed to provide faster operation but with lesser space.
15. The reason for the fast operating speeds of the lash drives is ____________
a) The absence of any movable parts
b) The integrated electronic hardware
c) The improved bandwidth connection
View Answer
Answer: a
Explanation: Since the lash drives have no movable parts their access and seek times are reasonably
reduced.

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Hierarchy of Memory
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focuses on “Hierarchy of Memory”.
1. The standard SRAM chips are costly as _________

a) They use highly advanced micro-electronic devices
b) They house 6 transistor per chip
c) They require specially designed PCB’s
View Answer
Answer: b
Explanation: As they require a large number of transistors, their cost per bit increases.
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2. The drawback of building a large memory with DRAM is ______________

a) The large cost factor
b) The inef icient memory organisation
c) The Slow speed of operation
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View Answer
Answer: c
Explanation: The DRAM’s were used for large memory modules for a long time until a substitute was
found.
3. To overcome the slow operating speeds of the secondary memory we make use of faster lash drives.
a) True
b) False
View Answer
Answer: a
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Explanation: To improve the speed we use lash drives at the cost of memory space.
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4. The fastest data access is provided using _______
a) Caches
b) DRAM’s
c) SRAM’s
d) Registers
View Answer
Answer: d
Explanation: The fastest data access is provided using registers as these memory locations are situated
inside the processor.
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5. The memory which is used to store the copy of data or instructions stored in larger memories, inside
the CPU is called _______
a) Level 1 cache
b) Level 2 cache
c) Registers
d) TLB
View Answer
Answer: a
Explanation: These memory devices are generally used to map onto the data stored in the larger
memories.
6. The larger memory placed between the primary cache and the memory is called ______
a) Level 1 cache
b) Level 2 cache
c) EEPROM
d) TLB
View Answer
Answer: b
Explanation: This is basically used to provide effective memory mapping.
7. The next level of memory hierarchy after the L2 cache is _______

b) TLB
c) Main memory
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d) Register
View Answer
Answer: d
Explanation: None.
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8. The last on the hierarchy scale of memory devices is ______

a) Main memory
b) Secondary memory
c) TLB
d) Flash drives
View Answer
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Answer: b
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Explanation: The secondary memory is the slowest memory device.
9. In the memory hierarchy, as the speed of operation increases the memory size also increases.
a) True
b) False
View Answer
Answer: b
Explanation: As the speed of operation increases the cost increases and the size decreases.
10. If we use the lash drives instead of the harddisks, then the secondary storage can go above primary
memory in the hierarchy.
a) True
b) False
View Answer
Answer: b
Explanation: The lash drives will increase the speed of transfer but still it won’t be faster than primary
memory.
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Caches
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focuses on “Caches”.
1. The reason for the implementation of the cache memory is ________

a) To increase the internal memory of the system
b) The difference in speeds of operation of the processor and memory
c) To reduce the memory access and cycle time
View Answer
Answer: b
Explanation: This difference in the speeds of operation of the system caused it to be inef icient.
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2. The effectiveness of the cache memory is based on the property of ________

a) Locality of reference
b) Memory localisation
c) Memory size
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View Answer
Answer: a
Explanation: This means that the cache depends on the location in the memory that is referenced often.
3. The temporal aspect of the locality of reference means ________

a) That the recently executed instruction won’t be executed soon
b) That the recently executed instruction is temporarily not referenced
c) That the recently executed instruction will be executed soon again
View Answer
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Answer: c
Explanation: None.
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4. The spatial aspect of the locality of reference means ________
a) That the recently executed instruction is executed again next
b) That the recently executed won’t be executed again
c) That the instruction executed will be executed at a later time
d) That the instruction in close proximity of the instruction executed will be executed in future
View Answer
Answer: d
Explanation: The spatial aspect of locality of reference tells that the nearby instruction is more likely to
be executed in future.
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5. The correspondence between the main memory blocks and those in the cache is given by _________
a) Hash function
b) Mapping function
c) Locale function
d) Assign function
View Answer
Answer: b
Explanation: The mapping function is used to map the contents of the memory to the cache.
6. The algorithm to remove and place new contents into the cache is called _______
a) Replacement algorithm
b) Renewal algorithm
c) Updation
View Answer
Answer: a
Explanation: As the cache gets full, older contents of the cache are swapped out with newer contents.
This decision is taken by the algorithm.
7. The write-through procedure is used ________

a) To write onto the memory directly
b) To write and read from memory simultaneously
c) To write directly on the memory and the cache simultaneously
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View Answer
Answer: c
Explanation: When write operation is issued then the corresponding operation is performed.
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8. The bit used to signify that the cache location is updated is ________
a) Dirty bit
b) Update bit
c) Reference bit
d) Flag bit
View Answer
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Answer: a
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Explanation: When the cache location is updated in order to signal to the processor this bit is used.
9. The copy-back protocol is used ________

a) To copy the contents of the memory onto the cache
b) To update the contents of the memory from the cache
c) To remove the contents of the cache and push it on to the memory
View Answer
Answer: b
Explanation: This is another way of performing the write operation, wherein the cache is updated irst
and then the memory.
10. The approach where the memory contents are transferred directly to the processor from the
memory is called ______
a) Read-later
b) Read-through
c) Early-start
View Answer
Answer: c
Explanation: None.
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Mapping Functions
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focuses on “Mapping Functions”.
1. The memory blocks are mapped on to the cache with the help of ______
a) Hash functions
b) Vectors
c) Mapping functions
View Answer
Answer: c
Explanation: The mapping functions are used to map the memory blocks on to their corresponding
cache block.
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2. During a write operation if the required block is not present in the cache then ______ occurs.
a) Write latency
b) Write hit
c) Write delay
d) Write miss
View Answer
Answer: d
Explanation: This indicates that the operation has missed and it brings the required block into the cache.
3. In ________ protocol the information is directly written into the main memory.
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a) Write through
b) Write back
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c) Write irst
View Answer
Answer: a
Explanation: In case of the miss, then the data gets written directly in main memory.
4. The only draw back of using the early start protocol is _______
a) Time delay
b) Complexity of circuit
c) Latency
d) High miss rate
View Answer
Answer: b
Explanation: In this protocol, the required block is read and directly sent to the processor.
5. The method of mapping the consecutive memory blocks to consecutive cache blocks is called ______
a) Set associative
b) Associative
c) Direct
d) Indirect
View Answer
Answer: c
Explanation: This method is most simple to implement as it involves direct mapping of memory blocks.
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6. While using the direct mapping technique, in a 16 bit system the higher order 5 bits are used for
________
a) Tag
b) Block
c) Word
d) Id
View Answer
Answer: a
Explanation: The tag is used to identify the block mapped onto one particular cache block.
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7. In direct mapping the presence of the block in memory is checked with the help of block ield.
a) True
b) False
View Answer
Answer: b
Explanation: The tag ield is used to check the presence of a mem block.
8. In associative mapping, in a 16 bit system the tag ield has ______ bits.
a) 12
b) 8
c) 9
d) 10
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View Answer
A
Answer: a
Explanation: The Tag ield is used as an id for the different memory blocks mapped to the cache.
9. The associative mapping is costlier than direct mapping.

a) True
b) False
View Answer
Answer: a
Explanation: In associative mapping, all the tags have to be searched to ind the block.
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10. The technique of searching for a block by going through all the tags is ______
a) Linear search
b) Binary search
c) Associative search
View Answer
Answer: c
Explanation: None.
11. The set-associative map technique is a combination of the direct and associative technique.
a) True
b) False
View Answer
Answer: a
Explanation: The combination of the ef iciency of the associative method and the cheapness of the direct
mapping, we get the set-associative mapping.
12. In set-associative technique, the blocks are grouped into ______ sets.
a) 4
b) 8
c) 12
d) 6
View Answer
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Answer: d
Explanation: The set-associative technique groups the blocks into different sets.
13. A control bit called _________ has to be provided to each block in set-associative.
a) Idol bit
b) Valid bit
c) Reference bit
View Answer
Answer: b
Explanation: The valid bit is used to indicate that the block holds valid information.
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14. The bit used to indicate whether the block was recently used or not is _______
A
a) Idol bit
b) Control bit
c) Reference bit
d) Dirty bit
View Answer
Answer: d
Explanation: The dirty bit is used to show that the block was recently modi ied and for a replacement
algorithm.
15. Data which is not up-to date is called as _______

a) Spoilt data
b) Stale data
c) Dirty data
View Answer
Answer: b
Explanation: None.

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Cache Miss and Hit
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focuses on “Cache Miss and Hit”.
1. The main memory is structured into modules each with its own address register called ______
a) ABR
b) TLB
c) PC
d) IR
View Answer
Answer: a
Explanation: ABR stands for Address Buffer Register.
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2. When consecutive memory locations are accessed only one module is accessed at a time.
a) True
b) False
View Answer
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Answer: a
Explanation: In a modular approach to memory structuring only one module can be accessed at a time.
3. In memory interleaving, the lower order bits of the address is used to _____________
a) Get the data
b) Get the address of the module
c) Get the address of the data within the module
View Answer
Answer: b
Explanation: To implement parallelism in data access we use interleaving.
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4. The number successful accesses to memory stated as a fraction is called as _____
a) Hit rate
A
b) Miss rate
c) Success rate
d) Access rate
View Answer
Answer: a
Explanation: The hit rate is an important factor in performance measurement.
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5. The number failed attempts to access memory, stated in the form of a fraction is called as _________
a) Hit rate
b) Miss rate
c) Failure rate
d) Delay rate
View Answer
Answer: b
Explanation: The miss rate is a key factor in deciding the type of replacement algorithm.
6. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are
incremented by one, when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
View Answer
Answer: b
Explanation: Miss usually occurs when the memory block required is not present in the cache.
7. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by
one and others remain same, in the case of ______
a) Hit
b) Miss
c) Delay
View Answer
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Answer: a
Explanation: If the referenced block is present in the memory it is called as hit.
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8. If hit rates are well below 0.9, then they’re called as speedy computers.
a) True
b) False
View Answer
Answer: b
Explanation: It has to be above 0.9 for speedy computers.
9. The extra time needed to bring the data into memory in case of a miss is called as __________
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a) Delay
b) Propagation time
A
c) Miss penalty
View Answer
Answer: c
Explanation: None.
10. The miss penalty can be reduced by improving the mechanisms for data transfer between the
different levels of hierarchy.
a) True
b) False
View Answer
Answer: a
Explanation: The extra time needed to bring the data into memory in case of a miss is called as miss
penalty.
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Single BUS Organisation – 1
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focuses on “Single BUS Organisation”.
1. The CPU is also called as ________

a) Processor hub
b) ISP
c) Controller
View Answer
Answer: b
Explanation: ISP stands for Instruction Set Processor.
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2. A common strategy for performance is making various functional units operate parallelly.
a) True
b) False
View Answer
Answer: a
Explanation: By parallelly accessing data we can have a pipelined processor.
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3. The PC gets incremented _____________

a) After the instruction decoding
b) After the IR instruction gets executed
c) After the fetch cycle
View Answer
Answer: c
Explanation: The PC always points to the next instruction to be executed.
4. Which register in the processor is single directional?

a) MAR
b) MDR
R
c) PC
d) Temp
A
View Answer
Answer: a
Explanation: The MAR is single directional as it just takes the address from the processor bus and passes
it to the external bus.
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5. The transparent register/s is/are __________

a) Y
b) Z
c) Temp
View Answer
Answer: d
Explanation: These registers are usually used to store temporary values.
6. Which register is connected to the MUX?

a) Y
b) Z
c) R0
d) Temp
View Answer
Answer: a
Explanation: The MUX can either read the operand from the Y register or increment the PC.
7. The registers, ALU and the interconnecting path together are called as ______
a) Control path
b) Flow path
c) Data path
View Answer
Answer: c
Explanation: None.
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8. The input and output of the registers are governed by __________

a) Transistors
b) Diodes
c) Gates
d) Switches
View Answer
Answer: d
Explanation: None.
9. When two or more clock cycles are used to complete data transfer it is called as ________
a) Single phase clocking
b) Multi-phase clocking
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c) Edge triggered clocking
A
View Answer
Answer: b
Explanation: This is basically used in systems without edge-triggered lip lops.
10. ________ signal is used to show complete of memory operation.

a) MFC
b) WMFC
c) CFC
View Answer
Answer: a
Explanation: MFC stands for Memory Function Complete.
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Single BUS Organisation – 2
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This set of Computer Organization Questions and Answers for Experienced people focuses on “Single
BUS Organisation-2”.
1. Is the below code segment correct, for the addition of two numbers?
R1in, Yin
R2out, Select Y, ADD, Zin
Zout, R3in
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a) True
b) False
View Answer
Answer: a
Explanation: This is the gate transfer notation, which indicates the usage of switches to control the low
of data.
2. The completion of the memory operation is indicated using ______ signal.

a) MFC
b) WMFC
c) CFC
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View Answer
Answer: a
Explanation: MFC stands for Memory Function Complete.
3. _________ signal enables the processor to wait for the memory operation to complete.
a) MFC
b) TLB
c) WMFC
d) ALB
View Answer
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Answer: c
Explanation: This signal stands for Wait For Memory Function Complete.
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4. The small extremely fast, RAM’s all called as ________
a) Cache
b) Heaps
c) Accumulators
d) Stacks
View Answer
Answer: b
Explanation: Cache’s are extremely essential in single BUS organisation to achieve fast operation.
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5. The main virtue for using single Bus structure is ________

a) Fast data transfers
b) Cost effective connectivity and speed
c) Cost effective connectivity and ease of attaching peripheral devices
View Answer
Answer: c
Explanation: None.
6. To extend the connectivity of the processor bus we use ______

a) PCI bus
b) SCSI bus
c) Controllers
d) Multiple bus
View Answer
Answer: a
Explanation: The PCI BUS basically is used to connect to memory devices.
7. The bus used to connect the monitor to the CPU is ____________

a) PCI bus
b) SCSI bus
c) Memory bus
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d) Rambus
View Answer
Answer: b
Explanation: The SCSI (Small Component System Interconnect) is used to connect to display devices.
8. The ISA standard Buses are used to connect ___________

a) RAM and processor
b) GPU and processor
c) Harddisk and Processor
d) CD/DVD drives and Processor
View Answer
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Answer: c
Explanation: None.
A
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9. ANSI stands for _____________

b) American National Standard Interface
c) American Network Standard Interfacing
d) American Network Security Interrupt
View Answer
Answer: a
Explanation: It is one of the standards of developing a BUS.
10. IBM developed a bus standard for their line of computers ‘PC AT’ called ________
a) IB bus
b) M-bus
c) ISA
View Answer
Answer: c
Explanation: None.
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Multiple BUS Organistaion
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focuses on “Multiple BUS Organistaion”.
1. The general purpose registers are combined into a block called as ______
a) Register bank
b) Register Case
c) Register ile
View Answer
Answer: c
Explanation: To make the access of the registers easier, we classify them into register iles.
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2. In ______ technology, the implementation of the register ile is by using an array of memory locations.
a) VLSI
b) ANSI
c) ISA
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d) ASCI
View Answer
Answer: a
Explanation: By doing so the access of the registers can be made faster.
3. In a three BUS architecture, how many input and output ports are there?
a) 2 output and 2 input
b) 1 output and 2 input
c) 2 output and 1 input
d) 1 output and 1 input
View Answer
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Answer: c
Explanation: That is enabling reading from two locations and writing into one.
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4. For a 3 BUS architecture, is the below code correct for adding three numbers?
PCout, R = B, Marin, READ, Inc PC
WMFC
MDRout, R = B, IRin
R4outa, R5outb, Select A, ADD, R6in, End
a) True
b) False
View Answer
Answer: a
Explanation: We have assumed the names of the three BUSes have A, B and C.
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5. The main advantage of multiple bus organisation over a single bus is __________
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
View Answer
Answer: a
Explanation: None.
6. CISC stands for _________

a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation
View Answer
Answer: c
Explanation: The CISC machines are well adept at handling multiple BUS organisation.
7. If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is
(Where S is term of the Basic performance equation).
a) 3
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b) ~2
c) ~1
d) 6
View Answer
Answer: c
Explanation: The value will be much lower in case of multiple BUS organisation.
8. In multiple BUS organisation __________ is used to select any of the BUSes for input into ALU.
a) MUX
b) DE-MUX
c) En-CDS
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View Answer
A
Answer: a
Explanation: The MUX can be used to either select the BUS or to increment the PC.
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9. There exists a separate block consisting of various units to decode an instruction.

a) True
b) False
View Answer
Answer: a
Explanation: This block is used to decode the instruction and place it in the IR.
10. There exists a separate block to increment the PC in multiple BUS organisation.
a) True
b) False
View Answer
Answer: a
Explanation: None.

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Hardwired Control
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focuses on “Hardwired Control”.
1. ________ are the different type/s of generating control signals.

a) Micro-programmed
b) Hardwired
c) Micro-instruction
d) Both Micro-programmed and Hardwired
View Answer
Answer: d
Explanation: The above is used to generate control signals in different types of system architectures.
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2. The type of control signal is generated based on ________

a) contents of the step counter
b) Contents of IR
c) Contents of condition lags
View Answer
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Answer: d
Explanation: Based on the information above the type of control signal is decided.
3. What does the hardwired control generator consist of?

a) Decoder/encoder
b) Condition codes
c) Control step counter
View Answer
Answer: d
Explanation: The CU uses the above blocks and IR to produce the necessary signal.
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4. What does the end instruction do?
a) It ends the generation of a signal
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b) It ends the complete generation process
c) It starts a new instruction fetch cycle and resets the counter
d) It is used to shift the control to the processor
View Answer
Answer: c
Explanation: It is basically used to start the generation of a new signal.
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5. The Zin signal to the processor is generated using, Zin = T1+T6 ADD + T4.BR…
a) True
b) False
View Answer
Answer: a
Explanation: The signal is generated using the logic of the formula above.
6. What does the RUN signal do?

a) It causes the termination of a signal
b) It causes a particular signal to perform its operation
c) It causes a particular signal to end
d) It increments the step counter by one
View Answer
Answer: d
Explanation: The RUN signal increments the step counter by one for each clock cycle.
7. The name hardwired came because the sequence of operations carried out is determined by the
wiring.
a) True
b) False
View Answer
Answer: a
Explanation: In other words hardwired is another name for Hardware Control signal generator.
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8. The bene it of using this approach is ________

a) It is cost effective
b) It is highly ef icient
c) It is very reliable
d) It increases the speed of operation
View Answer
Answer: d
Explanation: None.
9. The disadvantage/s of the hardwired approach is ________

a) It is less lexible
b) It cannot be used for complex instructions
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c) It is costly
d) less lexible & cannot be used for complex instructions
A
View Answer
Answer: d
Explanation: The more complex the instruction set less applicable to a hardwired approach.
10. The End signal is generated using, End = T7.ADD + T5.BR + (T5.N+ T4.-N).BRN…
a) True
b) False
View Answer
Answer: a
Explanation: None.
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Microprogrammed Control
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This set of Computer Organization Problems focuses on “Microprogrammed Control”.
1. In micro-programmed approach, the signals are generated by ______

a) Machine instructions
b) System programs
c) Utility tools
View Answer
Answer: a
Explanation: The machine instructions generate the signals.
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2. A word whose individual bits represent a control signal is ______

a) Command word
b) Control word
c) Co-ordination word
d) Generation word
View Answer
Answer: b
Explanation: The control word is used to get the different types of control signals required.
3. A sequence of control words corresponding to a control sequence is called _______

a) Micro routine
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b) Micro function
c) Micro procedure
View Answer
Answer: a
Explanation: The micro routines are used to perform a particular task.
4. Individual control words of the micro routine are called as ______

a) Micro task
b) Micro operation
c) Micro instruction
d) Micro command
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View Answer
A
Answer: c
Explanation: The each instruction which put together performs the task.
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5. The special memory used to store the micro routines of a computer is ________
a) Control table
b) Control store
c) Control mart
d) Control shop
View Answer
Answer: b
Explanation: The control store is used as a reference to get the required control routine.
6. To read the control words sequentially _________ is used.

a) PC
b) IR
c) UPC
View Answer
Answer: c
Explanation: The UPC stands for Micro program counter.
7. Every time a new instruction is loaded into IR the output of ________ is loaded into UPC.
a) Starting address generator
b) Loader
c) Linker
d) Clock
View Answer
Answer: a
Explanation: The starting address generator is used to load the address of the next micro instruction.
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8. The case/s where micro-programmed can perform well _______________

a) When it requires to check the condition codes
b) When it has to choose between the two alternatives
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c) When it is triggered by an interrupt

View Answer
Answer: d
Explanation: None.
9. The signals are grouped such that mutually exclusive signals are put together.
a) True
b) False
View Answer
Answer: a
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Explanation: This is done to improve the ef iciency of the controller.
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10. Highly encoded schemes that use compact codes to specify a small number of functions in each micro
instruction is ________
a) Horizontal organisation
b) Vertical organisation
c) Diagonal organisation
View Answer
Answer: b
Explanation: None.
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Replacement Algorithms
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focuses on “Replacement Algorithms”.
1. The directly mapped cache no replacement algorithm is required.

a) True
b) False
View Answer
Answer: a
Explanation: The position of each block is pre-determined in the direct mapped cache, hence no need for
replacement.
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2. The surroundings of the recently accessed block is called as ______

a) Neighborhood
b) Neighbour
View Answer
Answer: c
Explanation: The locality of reference is a key factor in many of the replacement algorithms.
3. In set associative and associative mapping there exists less lexibility.

a) True
b) False
View Answer
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Answer: b
Explanation: The above two methods of mapping the decision of which block to be removed rests with
the cache controller.
4. The algorithm which replaces the block which has not been referenced for a while is called _____
a) LRU
b) ORF
c) Direct
d) Both LRU and ORF
View Answer
Answer: a
Explanation: LRU stands for Least Recently Used irst.
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A
5. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are
incremented by one when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
View Answer
Answer: b
Explanation: Miss usually occurs when the memory block required is not present in the cache.
6. The LRU provides very bad performance when it comes to _________

a) Blocks being accessed is sequential
b) When the blocks are randomised
c) When the consecutive blocks accessed are in the extremes
View Answer
Answer: a
Explanation: The LRU in case of the sequential blocks as to waste its one cycle just incrementing the
counters.
7. The algorithm which removes the recently used page irst is ________
a) LRU
b) MRU
c) OFM
View Answer
Answer: b
Explanation: In MRU it is assumed that the page accessed now is less likely to be accessed again.
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8. The LRU can be improved by providing a little randomness in the access.

a) True
b) False
View Answer
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Answer: a
Explanation: None.
9. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by
one and others remain same, in the case of ______
a) Hit
b) Miss
c) Delay
View Answer
Answer: a
Explanation: If the referenced block is present in the memory it is called as a hit.
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10. The counter that keeps track of how many times a block is most likely used is _______
A
a) Count
b) Reference counter
c) Use counter
d) Probable counter
View Answer
Answer: b
Explanation: None.
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Performance of Caches
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focuses on “Performance of Caches”.
1. The key factor/s in commercial success of a computer is/are ________

a) Performance
b) Cost
c) Speed
d) Both Performance and Cost
View Answer
Answer: d
Explanation: The performance and cost of the computer system is a key decider in the commercial
success of the system.
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2. The main objective of the computer system is ________

a) To provide optimal power operation
b) To provide the best performance at low cost
c) To provide speedy operation at low power consumption
View Answer
Answer: b
Explanation: An optimal system provides the best performance at low costs.
3. A common measure of performance is ________

a) Price/performance ratio
b) Performance/price ratio
c) Operation/price ratio
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View Answer
Answer: a
Explanation: If this measure is less than one then the system is optimal.
4. The performance depends on ________

a) The speed of execution only
b) The speed of fetch and execution
c) The speed of fetch only
d) The hardware of the system only
View Answer
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Answer: b
Explanation: The performance of a system is decided by how quick an instruction is brought into the
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system and executed.
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5. The main purpose of having memory hierarchy is to ________

a) Reduce access time
b) Provide large capacity
c) Reduce propagation time
d) Reduce access time & Provide large capacity
View Answer
Answer: d
Explanation: By using the memory Hierarchy, we can increase the performance of the system.
6. The memory transfers between two variable speed devices are always done at the speed of the faster
device.
a) True
b) False
View Answer
Answer: a
Explanation: None.
7. An effective to introduce parallelism in memory access is by _______

a) Memory interleaving
b) TLB
c) Pages
d) Frames
View Answer
Answer: a
Explanation: Interleaving divides the memory into modules.
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8. The performance of the system is greatly in luenced by increasing the level 1 cache.
a) True
b) False
View Answer
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Answer: a
Explanation: This is so because the L1 cache is onboard the processor.
9. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can
execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the
execution of the same instruction which processor is faster.
a) A
b) B
c) Both take the same time
d) Insuf icient information
View Answer
Answer: a
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Explanation: None.
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10. If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is
(Where S is a term of the Basic performance equation).
a) 3
b) ~2
c) ~1
d) 6
View Answer
Answer: c
Explanation: Pipelining is a process of fetching an instruction during the execution of other instruction.
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19. Computer Organization Questions and Answers – Intel IA-32 Pentium Architecture-1
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Virtual Memory
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focuses on “Virtual Memory”.
1. The physical memory is not as large as the address space spanned by the processor.
a) True
b) False
View Answer
Answer: a
Explanation: This is one of the main reasons for the usage of virtual memories.
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2. The program is divided into operable parts called as _________

a) Frames
b) Segments
c) Pages
d) Sheets
View Answer
Answer: b
Explanation: The program is divided into parts called as segments for ease of execution.
3. The techniques which move the program blocks to or from the physical memory is called as ______
a) Paging
b) Virtual memory organisation
c) Overlays
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d) Framing
View Answer
Answer: b
Explanation: By using this technique the program execution is accomplished with a usage of less space.
4. The binary address issued to data or instructions are called as ______

a) Physical address
b) Location
c) Relocatable address
d) Logical address
View Answer
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Answer: d
Explanation: The logical address is the random address generated by the processor.
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5. __________ is used to implement virtual memory organisation.

a) Page table
b) Frame table
c) MMU
View Answer
Answer: c
Explanation: The MMU stands for Memory Management Unit.
6. ______ translates the logical address into a physical address.

a) MMU
b) Translator
c) Compiler
d) Linker
View Answer
Answer: a
Explanation: The MMU translates the logical address into a physical address by adding an offset.
7. The main aim of virtual memory organisation is ________

a) To provide effective memory access
b) To provide better memory transfer
c) To improve the execution of the program
View Answer
Answer: d
Explanation: None.
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8. The DMA doesn’t make use of the MMU for bulk data transfers.
a) True
b) False
View Answer
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Answer: b
Explanation: The DMA stands for Direct Memory Access, in which a block of data gets directly
transferred from the memory.
9. The virtual memory basically stores the next segment of data to be executed on the _________
b) Disks
c) RAM
d) ROM
View Answer
Answer: a
Explanation: None.
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10. The associatively mapped virtual memory makes use of _______
A
a) TLB
b) Page table
c) Frame table
View Answer
Answer: a
Explanation: TLB stands for Translation Look-aside Buffer.
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Secondary Storage – 1
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focuses on “Secondary Storage – 1”.
1. The main reason for the discontinuation of semi conductor based storage devices for providing large
storage space is _________
a) Lack of suf icient resources
b) High cost per bit value
c) Lack of speed of operation
View Answer
Answer: b
Explanation: In the case of semi conductor based memory technology, we get speed but the increase in
the integration of various devices the cost is high.
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2. The digital information is stored on the hard disk by ____________

a) Applying a suitable electric pulse
b) Applying a suitable magnetic ield
c) Applying a suitable nuclear ield
d) By using optic waves
View Answer
Answer: a
Explanation: The digital data is sorted on the magnetized discs by magnetizing the areas.
3. For the synchronization of the read head, we make use of a _______

a) Framing bit
b) Synchronization bit
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c) Clock
d) Dirty bit
View Answer
Answer: c
Explanation: The clock makes it easy to distinguish between different values red by a head.
4. One of the most widely used schemes of encoding used is _________

a) NRZ-polar
b) RZ-polar
c) Manchester
d) Block encoding
View Answer
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Answer: c
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Explanation: The Manchester encoding used is also called as phase encoding and it is used to encode
both clock and data.
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5. The drawback of Manchester encoding is _________

a) The cost of the encoding scheme
b) The speed of encoding the data
c) The Latency offered
d) The low bit storage density provided
View Answer
Answer: d
Explanation: The space required to represent each bit must be large enough to accommodate two
changes in magnetization.
6. The read/write heads must be near to disk surfaces for better storage.
a) True
b) False
View Answer
Answer: a
Explanation: By maintaining the heads near to the surface greater bit densities can be achieved.
7. _____ pushes the heads away from the surface as they rotate at their standard rates.
a) Magnetic tension
b) Electric force
c) Air pressure
View Answer
Answer: c
Explanation: Due to the speed of rotation of the discs air pressure develops in the hard disk.
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8. The air pressure can be countered by putting ______ in the head-disc surface arrangement.
a) Air ilter
b) Spring mechanism
c) coolant
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View Answer
Answer: b
Explanation: The spring mechanism pushes the head along the surface to reduce the air pressure effect.
9. The method of placing the heads and the discs in an air tight environment is also called as ______
a) RAID Arrays
b) ATP tech
c) Winchester technology
d) Fleming reduction
View Answer
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Answer: c
Explanation: The Disks and the heads operate faster due to the absence of the dust particles.
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10. A hard disk with 20 surfaces will have _____ heads.
a) 10
b) 5
c) 1
d) 20
View Answer
Answer: d
Explanation: Each surface will have its own head to perform read/write operation.
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Secondary Storage – 2
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This set of Computer Organization Interview Questions and Answers for Experienced people focuses on
“Secondary Storage – 2”.
1. The disk system consists of which of the following?

i. Disk
ii. Disk drive
iii. Disk controller
a) i and ii
b) i, ii and iii
c) ii and iii
d) i
View Answer
Answer: b
Explanation: None.
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2. The set of corresponding tracks on all surfaces of a stack of disks form a ______
a) Cluster
b) Cylinder
c) Group
d) Set
View Answer
Answer: b
Explanation: The data is stored in these sections called as cylinders.
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3. The data can be accessed from the disk using _________

a) Surface number
b) Sector number
c) Track number
View Answer
Answer: d
Explanation: None.
4. The read and write operations usually start at ______ of the sector.
a) Center
b) Middle
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c) From the last used point
d) Boundaries
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View Answer
Answer: d
Explanation: The heads read and write data from the ends to the center.
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5. To distinguish between two sectors we make use of ________

a) Inter sector gap
b) Splitting bit
c) Numbering bit
View Answer
Answer: a
Explanation: This means that we leave a little gap between each sector to differentiate between them.
6. The _____ process divides the disk into sectors and tracks.
a) Creation
b) Initiation
c) Formatting
d) Modi ication
View Answer
Answer: c
Explanation: The formatting process deletes the data present and does the creation of sectors and
tracks.
7. The access time is composed of __________

a) Seek time
b) Rotational delay
c) Latency
d) Both Seek time and Rotational delay
View Answer
Answer: d
Explanation: The seek time refers to the time required to move the head to the required disk.
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8. The disk drive is connected to the system by using the _____

a) PCI bus
b) SCSI bus
c) HDMI
d) ISA
View Answer
Answer: b
Explanation: None.
9. _______ is used to deal with the difference in the transfer rates between the drive and the bus.
a) Data repeaters
b) Enhancers
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c) Data buffers
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View Answer
Answer: c
Explanation: The buffers are added to store the data from the fast device and to send it to the slower
device at its rate.
10. _______ is used to detect and correct the errors that may occur during data transfers.
a) ECC
b) CRC
c) Checksum
View Answer
Answer: a
Explanation: ECC stands for Error Correcting Code.
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Fast Adders
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focuses on “Fast Adders”.
1. The logic operations are simpler to implement using logic circuits.

a) True
b) False
View Answer
Answer: a
Explanation: The logic operation includes AND, OR, XOR etc.
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2. The logic operations are implemented using _______ circuits.

a) Bridge
b) Logical
c) Combinatorial
d) Gate
View Answer
Answer: c
Explanation: The combinatorial circuits means, using the basic universal gates.
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3. The carry generation function: ci + 1 = yici + xici + xiyi, is implemented in ____________

a) Half adders
b) Full adders
c) Ripple adders
d) Fast adders
View Answer
Answer: b
Explanation: In this the carry for the next step is generated in the previous steps operation.
4. Which option is true regarding the carry in the ripple adders?

a) Are generated at the beginning only
b) Must travel through the con iguration
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c) Is generated at the end of each operation
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View Answer
Answer: b
Explanation: The carry must pass through the con iguration of the circuit till it reaches the particular
step.
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5. In full adders the sum circuit is implemented using ________

a) And & or gates
b) NAND gate
c) XOR
d) XNOR
View Answer
Answer: c
Explanation: sum = a ^ b ^ c (‘^’ indicates XOR operation).
6. The usual implementation of the carry circuit involves _________

a) And & or gates
b) XOR
c) NAND
d) XNOR
View Answer
Answer: b
Explanation: In case of full and half adders this method is used.
7. A _______ gate is used to detect the occurrence of an over low.

a) NAND
b) XOR
c) XNOR
d) AND
View Answer
Answer: b
Explanation: The over low is detected by cn^cn-1 (‘^’ indicates XOR operation).
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8. In a normal adder circuit, the delay obtained in a generation of the output is _______
a) 2n + 2
b) 2n
c) n + 2
View Answer
Answer: a
Explanation: The 2n delay cause of the carry generation and the 2 delay cause of the XOR operation.
9. The inal addition sum of the numbers, 0110 & 0110 is ____________
a) 1101
b) 1111
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c) 1001
d) 1010
A
View Answer
Answer: a
Explanation: None.
10. The delay reduced to in the carry look ahead adder is __________
a) 5
b) 8
c) 10
d) 2n
View Answer
Answer: a
Explanation: None.
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Multiplication
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focuses on “Multiplication”.
1. The product of 1101 & 1011 is ______

a) 10001111
b) 10101010
c) 11110000
d) 11001100
View Answer
Answer: a
Explanation: The above operation is performed using binary multiplication.
2. We make use of ______ circuits to implement multiplication.

a) Flip lops
b) Combinatorial
c) Fast adders
View Answer
Answer: c
Explanation: The fast adders are used to add the multiplied numbers.
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3. The multiplier is stored in ______

a) PC Register
b) Shift register
c) Cache
View Answer
Answer: b
Explanation: The value is stored in a shift register so that each bit can be accessed separately.
4. The ______ is used to coordinate the operation of the multiplier.
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a) Controller
b) Coordinator
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c) Control sequencer
View Answer
Answer: c
Explanation: This performs the required sequencing of the various parts of the circuit.
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5. The multiplicand and the control signals are passed through to the n-bit adder via _____
a) MUX
b) DEMUX
c) Encoder
d) Decoder
View Answer
Answer: a
Explanation: None.
6. The product of -13 & 11 is ______________

a) 1100110011
b) 1101110001
c) 1010101010
d) 1111111000
View Answer
Answer: b
Explanation: None.
7. The method used to reduce the maximum number of summands by half is _______
a) Fast multiplication
b) Bit-pair recording
c) Quick multiplication
View Answer
Answer: b
Explanation: It reduces the number of summands by concatenating them.
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8. The bits 1 & 1 are recorded as _______ in bit-pair recording.

a) -1
b) 0
c) +1
d) both -1 and 0
View Answer
Answer: d
Explanation: Its ‘-1’ when the previous bit is 0 and ‘0’ when the previous bit is 1.
9. The multiplier -6(11010) is recorded as _______

a) 0-1-2
b) 0-1+1-10
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c) -2-10
A
View Answer
Answer: a
Explanation: None.
10. CSA stands for?

a) Computer Speed Addition
b) Carry Save Addition
c) Computer Service Architecture
View Answer
Answer: a
Explanation: The CSA is used to speed up the addition of multiplicands.
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Representation of Floating Number
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This set of Computer Organization Question Bank focuses on “Representation of Floating Number”.
1. The decimal numbers represented in the computer are called as loating point numbers, as the decimal
point loats through the number.
a) True
b) False
View Answer
Answer: a
Explanation: By doing this the computer is capable of accommodating the large loat numbers also.
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2. The numbers written to the power of 10 in the representation of decimal numbers are called as _____
a) Height factors
b) Size factors
c) Scale factors
View Answer
Answer: c
Explanation: These are called as scale factors cause they’re responsible in determining the degree of
speci ication of a number.
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3. If the decimal point is placed to the right of the irst signi icant digit, then the number is called ________
a) Orthogonal
b) Normalized
c) Determinate
View Answer
Answer: b
Explanation: None.
4. ________ constitute the representation of the loating number.

a) Sign
b) Signi icant digits
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c) Scale factor
A
View Answer
Answer: d
Explanation: The following factors are responsible for the representation of the number.
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5. The sign followed by the string of digits is called as ______

a) Signi icant
b) Determinant
c) Mantissa
d) Exponent
View Answer
Answer: c
Explanation: The mantissa also consists of the decimal point.
6. In IEEE 32-bit representations, the mantissa of the fraction is said to occupy ______ bits.
a) 24
b) 23
c) 20
d) 16
View Answer
Answer: b
Explanation: The mantissa is made to occupy 23 bits, with 8 bit exponent.
7. The normalized representation of 0.0010110 * 2 9 is _______

a) 0 10001000 0010110
b) 0 10000101 0110
c) 0 10101010 1110
d) 0 11110100 11100
View Answer
Answer: b
Explanation: Normalized representation is done by shifting the decimal point.
8. The 32 bit representation of the decimal number is called as ___________

a) Double-precision
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b) Single-precision
c) Extended format
View Answer
Answer: b
Explanation: None.
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9. In 32 bit representation the scale factor as a range of ________

a) -128 to 127
b) -256 to 255
c) 0 to 255
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View Answer
A
Answer: a
Explanation: Since the exponent ield has only 8 bits to store the value.
10. In double precision format, the size of the mantissa is ______

a) 32 bit
b) 52 bit
c) 64 bit
d) 72 bit
View Answer
Answer: b
Explanation: The double precision format is also called as 64 bit representation.
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Pipe-lining
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focuses on “Pipe-lining”.
1. ______ have been developed speci ically for pipelined systems.

a) Utility software
b) Speed up utilities
c) Optimizing compilers
View Answer
Answer: c
Explanation: The compilers which are designed to remove redundant parts of the code are called as
optimizing compilers.
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2. The pipelining process is also called as ______

a) Superscalar operation
b) Assembly line operation
c) Von Neumann cycle
View Answer
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Answer: b
Explanation: It is called so because it performs its operation at the assembly level.
3. The fetch and execution cycles are interleaved with the help of ________
a) Modi ication in processor architecture
b) Clock
c) Special unit
d) Control unit
View Answer
Answer: b
Explanation: The time cycle of the clock is adjusted to perform the interleaving.
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4. Each stage in pipelining should be completed within ___________ cycle.
a) 1
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b) 2
c) 3
d) 4
View Answer
Answer: a
Explanation: The stages in the pipelining should get completed within one cycle to increase the speed of
performance.
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5. In pipelining the task which requires the least time is performed irst.
a) True
b) False
View Answer
Answer: b
Explanation: This is done to avoid starvation of the longer task.
6. If a unit completes its task before the allotted time period, then _______
a) It’ll perform some other task in the remaining time
b) Its time gets reallocated to a different task
c) It’ll remain idle for the remaining time
View Answer
Answer: c
Explanation: None.
7. To increase the speed of memory access in pipelining, we make use of _______

a) Special memory locations
b) Special purpose registers
c) Cache
d) Buffers
View Answer
Answer: c
Explanation: By using the cache we can reduce the speed of memory access by a factor of 10.
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8. The periods of time when the unit is idle is called as _____

a) Stalls
b) Bubbles
c) Hazards
d) Both Stalls and Bubbles
View Answer
Answer: d
Explanation: The stalls are a type of hazards that affect a pipelined system.
9. The contention for the usage of a hardware device is called ______

a) Structural hazard
b) Stalk
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c) Deadlock
A
View Answer
Answer: a
Explanation: None.
10. The situation wherein the data of operands are not available is called ______
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
View Answer
Answer: a
Explanation: Data hazards are generally caused when the data is not ready on the destination side.
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Superscalar Processors
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focuses on “Superscalar Processors”.
1. The throughput of a super scalar processor is _______

a) less than 1
b) 1
c) More than 1
d) Not Known
View Answer
Answer: c
Explanation: The throughput of a processor is measured by using the number of instructions executed
per second.
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2. When the processor executes multiple instructions at a time it is said to use _______
a) single issue
b) Multiplicity
c) Visualization
d) Multiple issues
View Answer
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Answer: d
Explanation: None.
3. The ______ plays a very vital role in case of super scalar processors.
a) Compilers
b) Motherboard
c) Memory
d) Peripherals
View Answer
Answer: a
Explanation: The compilers are programmed to arrange the instructions to get more throughput.
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4. If an exception is raised and the succeeding instructions are executed completely, then the processor is
said to have ______
A
a) Exception handling
b) Imprecise exceptions
c) Error correction
View Answer
Answer: b
Explanation: The processor since as executed the following instructions even though an exception was
raised, hence the exception is treated as imprecise.
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5. In super-scalar mode, all the similar instructions are grouped and executed together.
a) True
b) False
View Answer
Answer: a
Explanation: The instructions are grouped meaning that the instructions fetch and decode and other
cycles are overlapped.
6. In super-scalar processors, ________ mode of execution is used.

a) In-order
b) Post order
c) Out of order
View Answer
Answer: c
Explanation: It follows out of order execution to speed up the execution of instructions.
7. Since it uses the out of order mode of execution, the results are stored in ______
a) Buffers
b) Special memory locations
c) Temporary registers
d) TLB
View Answer
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Answer: c
Explanation: The results are stored in temporary locations and are arranged afterward.
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8. The step where in the results stored in the temporary register is transferred into the permanent
register is called as ______
a) Final step
b) Commitment step
c) Last step
d) Inception step
View Answer
Answer: b
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Explanation: None.
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9. A special unit used to govern the out of order execution of the instructions is called as ______
a) Commitment unit
b) Temporal unit
c) Monitor
d) Supervisory unit
View Answer
Answer: a
Explanation: This unit monitors the execution of the instructions and makes sure that the inal result is in
order.
10. The commitment unit uses a queue called ______

a) Record buffer
b) Commitment buffer
c) Storage buffer
View Answer
Answer: a
Explanation: None.
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CISC and RISC Processors
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focuses on “CISC and RISC Processors”.
1. The CISC stands for ___________

a) Computer Instruction Set Compliment
b) Complete Instruction Set Compliment
c) Computer Indexed Set Components
d) Complex Instruction set computer
View Answer
Answer: d
Explanation: CISC is a computer architecture where in the processor performs more complex operations
in one step.
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2. The computer architecture aimed at reducing the time of execution of instructions is ________
a) CISC
b) RISC
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c) ISA
d) ANNA
View Answer
Answer: b
Explanation: The RISC stands for Reduced Instruction Set Computer.
3. The Sun micro systems processors usually follow _____ architecture.

a) CISC
b) ISA
c) ULTRA SPARC
d) RISC
View Answer
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Answer: d
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Explanation: The Risc machine aims at reducing the instruction set of the computer.
4. The RISC processor has a more complicated design than CISC.

a) True
b) False
View Answer
Answer: b
Explanation: The RISC processor design is more simpler than CISC and it consists of fewer transistors.
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5. The iconic feature of the RISC machine among the following is _______
a) Reduced number of addressing modes
b) Increased memory size
c) Having a branch delay slot
View Answer
Answer: c
Explanation: A branch delay slot is an instruction space immediately following a jump or branch.
6. Both the CISC and RISC architectures have been developed to reduce the ______
a) Cost
b) Time delay
c) Semantic gap
View Answer
Answer: c
Explanation: The semantic gap is the gap between the high level language and the low level language.
7. Out of the following which is not a CISC machine.

a) IBM 370/168
b) VAX 11/780
c) Intel 80486
d) Motorola A567
View Answer
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Answer: d
Explanation: None.
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8. Pipe-lining is a unique feature of _______

a) RISC
b) CISC
c) ISA
d) IANA
View Answer
Answer: a
Explanation: The RISC machine architecture was the irst to implement pipe-lining.
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9. In CISC architecture most of the complex instructions are stored in _____
A
a) Register
b) Diodes
c) CMOS
d) Transistors
View Answer
Answer: d
Explanation: In CISC architecture more emphasis is given on the instruction set and the instructions take
over a cycle to complete.
10. Which of the architecture is power ef icient?

a) CISC
b) RISC
c) ISA
d) IANA
View Answer
Answer: b
Explanation: Hence the RISC architecture is followed in the design of mobile devices.
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Hazards of Processor Architecture
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This set of Computer Organization online quiz focuses on “Hazards of Processor Architecture”.
1. Any condition that causes a processor to stall is called as _________

a) Hazard
b) Page fault
c) System error
View Answer
Answer: a
Explanation: An hazard causes a delay in the execution process of the processor.
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2. The periods of time when the unit is idle is called as ________

a) Stalls
b) Bubbles
c) Hazards
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d) Both Stalls and Bubbles

View Answer
Answer: d
Explanation: The stalls are a type of hazards that affect a pipe-lined system.
3. The contention for the usage of a hardware device is called ______

a) Structural hazard
b) Stalk
c) Deadlock
View Answer
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Answer: a
Explanation: The processor contends for the usage of the hardware and might enter into a deadlock
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state.
4. The situation wherein the data of operands are not available is called ______
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
View Answer
Answer: a
Explanation: Data hazards are generally caused when the data is not ready on the destination side.
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5. The stalling of the processor due to the unavailability of the instructions is called as ___________
a) Control hazard
b) structural hazard
c) Input hazard
View Answer
Answer: a
Explanation: The control hazard also called as instruction hazard is usually caused by a cache miss.
6. The time lost due to the branch instruction is often referred to as ____________
a) Latency
b) Delay
c) Branch penalty
View Answer
Answer: c
Explanation: This time also retards the performance speed of the processor.
7. The pipeline bubbling is a method used to prevent data hazard and structural hazards.
a) True
b) False
View Answer
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Answer: a
Explanation: The periods of time when the unit is idle is called a Bubble.
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8. ____________ method is used in centralized systems to perform out of order execution.

a) Scorecard
b) Score boarding
c) Optimizing
d) Redundancy
View Answer
Answer: b
Explanation: In a scoreboard, the data dependencies of every instruction are logged. Instructions are
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released only when the scoreboard determines that there are no con licts with previously issued and
incomplete instructions.
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9. The algorithm followed in most of the systems to perform out of order execution is __________
a) Tomasulo algorithm
b) Score carding
c) Reader-writer algorithm
View Answer
Answer: a
Explanation: The Tomasulo algorithm is a hardware algorithm developed in 1967 by Robert Tomasulo
from IBM. It allows sequential instructions that would normally be stalled due to certain dependencies to
execute non-sequentially (out-of-order execution).
10. The problem where process concurrency becomes an issue is called as ___________
a) Philosophers problem
b) Bakery problem
c) Bankers problem
d) Reader-writer problem
View Answer
Answer: d
Explanation: None.
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Computer Organization Questions and Answers – Clusters
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Clusters
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focuses on “Clusters”.
1. The set of loosely connected computers are called as __________

a) LAN
b) WAN
c) Workstation
d) Cluster
View Answer
Answer: d
Explanation: In a computer cluster all the participating computers work together on a particular task.
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2. Each computer in a cluster is connected using __________

a) UTP
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b) Rj-45
c) STP
d) Coaxial cable
View Answer
Answer: b
Explanation: The computers are connected to each other using a LAN connector cable.
3. The computer cluster architecture emerged as a result of _________

a) ISA
b) Workstation
c) Super computers
d) Distributed systems
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View Answer
A
Answer: d
Explanation: A distributed system is a computer system spread out over a geographic area.
4. The software which governs the group of computers is __________

a) Driver Rd45
b) Interface UI
c) Clustering middleware
d) Distributor
View Answer
Answer: c
Explanation: The software helps to project a single system image to the user.
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5. The simplest form of a cluster is __________ approach.

a) Beowolf
b) Sequoia
c) Stone
View Answer
Answer: a
Explanation: None.
6. The cluster formation in which the work is divided equally among the systems is ______
a) Load-con iguration
b) Load-Division
c) Light head
d) Both Load-con iguration and Load-Division
View Answer
Answer: a
Explanation: This approach the work gets divided among the systems equally.
7. In the client server model of the cluster _________ approach is used.

a) Load con iguration
b) FIFO
c) Bankers algorithm
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d) Round robin
View Answer
Answer: d
Explanation: By using this approach the performance of the cluster can be enhanced.
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8. The beowolf structure follows the __________ approach of a relationship between the systems.
a) Master-slave
b) Asynchronous
c) Synchronous
d) Isochronous
View Answer
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Answer: a
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Explanation: None.
9. The most common modes of communication in clusters are ______

a) Message queues
b) Message passing interface
c) PVm
d) Both Message passing interface and PVm
View Answer
Answer: d
Explanation: None.
10. The method followed in case of node failure, wherein the node gets disabled is _________
a) STONITH
b) Fibre channel
c) Fencing
View Answer
Answer: a
Explanation: None.
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Computer Organization Questions and Answers – VLIW Architecture (I-64)

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VLIW Architecture (I-64)
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focuses on “VLIW Architecture (I-64)”.
1. VLIW stands for?

a) Very Long Instruction Word
b) Very Long Instruction Width
c) Very Large Instruction Word
d) Very Long Instruction Width
View Answer
Answer: a
Explanation: It is the architecture designed to perform multiple operations in parallel.
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2. The important feature of the VLIW is _______

a) ILP
b) Cost effectiveness
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c) Performance
View Answer
Answer: a
Explanation: ILP stands for Instruction Level Parallelism.
3. The main difference between the VLIW and the other approaches to improve performance is
___________
a) Cost effectiveness
b) Increase in performance
c) Lack of complex hardware design
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View Answer
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Answer: c
Explanation: The Pipe-lining and super-scalar architectures involved the usage of complex hardware
circuits for the implementation.
4. In VLIW the decision for the order of execution of the instructions depends on the program itself.
a) True
b) False
View Answer
Answer: a
Explanation: In other words, the order of execution of instructions has nothing to do with the physical
hardware implementation of the system.
5. The parallel execution of operations in VLIW is done according to the schedule determined by
__________
a) Task scheduler
b) Interpreter
c) Compiler
d) Encoder
View Answer
Answer: c
Explanation: The compiler irst checks the code for interdependencies and then determines the schedule
for its execution.
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6. The VLIW processors are much simpler as they do not require of _________
a) Computational register
b) Complex logic circuits
c) SSD slots
d) Scheduling hardware
View Answer
Answer: d
Explanation: As the compiler only decides the schedule of execution the schedule is not required here.
7. The VLIW architecture follows _____ approach to achieve parallelism.

a) MISD
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b) SISD
c) SIMD
d) MIMD
View Answer
Answer: d
Explanation: The MIMD stands for Multiple Instructions Multiple Data.
8. The following instruction is allowed in VLIW:

f12 = f0 * f4, f8 = f8 + f12, f0 = dm(i0, m3), f4 = pm(i8, m9);
a) True
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b) False
View Answer
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Answer: a
Explanation: The above mentioned instruction is a complex 48 bit instruction used to perform
operations on loating numbers.
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9. To compute the direction of the branch the VLIW uses _____________

a) Seekers
b) Heuristics
c) Direction counter
d) Compass
View Answer
Answer: b
Explanation: None.
10. EPIC stands for?

a) Explicitly Parallel Instruction Computing
b) External Peripheral Integrating Component
c) External Parallel Instruction Computing
View Answer
Answer: a
Explanation: None.

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Address Translation – 1
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focuses on “Address Translation – 1”.
1. For converting a virtual address into the physical address, the programs are divided into __________
a) Pages
b) Frames
c) Segments
d) Blocks
View Answer
Answer: a
Explanation: On the physical memory side the memory is divided into pages.
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2. The memory allocated to each page is contiguous.

a) True
b) False
View Answer
Answer: a
Explanation: Each page might be allocated memory deferentially but the memory for one page will be
continuous.
3. The pages size shouldn’t be too small, as this would lead to __________
a) Transfer errors
b) Increase in operation time
c) Increase in access time
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d) Decrease in performance
View Answer
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Answer: c
Explanation: The access time of the magnetic disk is much longer than the access time of the memory.
4. The cache bridges the speed gap between ______ and __________
a) RAM and ROM
b) RAM and Secondary memory
c) Processor and RAM
View Answer
Answer: c
Explanation: The Cache is a hardware implementation to reduce the access time for processor
operations.
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5. The virtual memory bridges the size and speed gap between __________ and __________
a) RAM and ROM
b) RAM and Secondary memory
c) Processor and RAM
View Answer
Answer: b
Explanation: The virtual memory basically works as an extension of the RAM.
6. The higher order bits of the virtual address generated by the processor forms the _______
a) Table number
b) Frame number
c) List number
d) Page number
View Answer
Answer: d
Explanation: The higher order bits indicate the page number which points to one particular entry in the
page table.
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7. The page length shouldn’t be too long because ___________

a) It reduces the program ef iciency
b) It increases the access time
c) It leads to wastage of memory
View Answer
Answer: c
Explanation: If the size is more than the required size then the extra space gets wasted.
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8. The lower order bits of the virtual address forms the __________
a) Page number
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b) Frame number
c) Block number
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d) Offset
View Answer
Answer: d
Explanation: This gives the offset within the page table.
9. The area in the main memory that can hold one page is called as ___________
a) Page entry
b) Page frame
c) Frame
d) Block
View Answer
Answer: b
Explanation: None.
10. The starting address of the page table is stored in __________

a) TLB
b) R0
c) Page table base register
View Answer
Answer: c
Explanation: The register is used to hold the address which is used to access the table.
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Address Translation – 2
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This set of Computer Organization test focuses on “Address Translation-2”.
1. The bits used to indicate the status of the page in the memory is called ______
a) Control bits
b) Status bits
c) Progress bit
View Answer
Answer: a
Explanation: These bits are used to store the status information of the program.
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2. The _______ bit is used to indicate the validity of the page.

a) Valid bit
b) Invalid bit
c) Correct bit
View Answer
Answer: a
Explanation: The os irst validates the page and then only moves from the page table.
3. The bit used to store whether the page has been modi ied or not is called as _______
a) Dirty bit
b) Modify bit
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c) Relocation bit
A
View Answer
Answer: a
Explanation: This bit is set after the page in the table gets modi ied.
4. The page table should be ideally situated within ____________

a) Processor
b) TLB
c) MMU
d) Cache
View Answer
Answer: c
Explanation: The page table information is used for every read and access operation.
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5. If the page table is large then it is stored in __________

a) Processor
b) Main memory
c) Disk
d) Secondary storage
View Answer
Answer: b
Explanation: By storing the table on the RAM the required operation’s speed is increased.
6. When the page table is placed in the main memory, the ___________ is used to store the recently accessed
pages.
a) MMU
b) TLB
c) R0
d) Table
View Answer
Answer: b
Explanation: The TLB is used to store the page numbers of the recently accessed pages.
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7. The TLB is incorporated as part of the _________

a) Processor
b) MMU
c) Disk
d) RAM
View Answer
Answer: b
Explanation: None.
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8. Whenever a request to the page that is not present in the main memory is accessed ______ is triggered.
a) Interrupt
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b) Request
c) Page fault
A
View Answer
Answer: c
Explanation: When a page fault is triggered, the os brings the required page into memory.
9. The general purpose registers are combined into a block called as ______
a) Register bank
b) Register Case
c) Register ile
View Answer
Answer: c
Explanation: To make the access of the registers easier, we classify them into register iles.
10. What does the RUN signal do?

a) It causes the termination of a signal
b) It causes a particular signal to perform its operation
c) It causes a particular signal to end
d) It increments the step counter by one
View Answer
Answer: d
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Motorola 680X0 Processor Architecture – 1
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focuses on “Motorola 680X0 Processor Architecture – 1”.
1. _____ register is designated to point to the 68000 processor stack.

a) A7 register
b) B2 register
c) There is no such designation
d) Any general purpose register is selected at random
View Answer
Answer: a
Explanation: The processor stack is the place used to store the ongoing and upcoming process
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information
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2. The word length in the 68000 computer is _______

a) 32 bit
b) 64 bit
c) 16 bit
d) 8 bit
View Answer
Answer: c
Explanation: The length of an instruction that can be read or accessed at a time is referred to as word
length.
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3. Is 68000 computer Byte addressable?
A
a) True
b) False
View Answer
Answer: a
Explanation: The ability of a system to access the entire data of a process by reading consecutive bytes is
called as Byte addressability
4. The register in 68000 can contain up to _____ bits.

a) 24
b) 32
c) 16
d) 64
View Answer
Answer: b
Explanation: None.
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5. The 68000 has a max of how many data registers?

a) 16
b) 20
c) 10
d) 8
View Answer
Answer: d
Explanation: The data registers are solely used for the purpose of storing data items of the process.
6. When an operand is stored in a register it is _______

a) Stored in the lower order bits of the register
b) Stored in the higher order bits of the register
c) Stored in any of the bits at random
View Answer
Answer: a
Explanation: The data always gets stored from the lower order to the higher order bits, except in the
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case of Little Endian architecture.
7. The status register of the 68000 has ____ condition codes.

a) 7
b) 4
c) 5
d) 8
View Answer
Answer: c
Explanation: The register which is used to basically store the condition lags is called as a status register.
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8. The 68000 uses _____ address assignment.
a) Big Endian
A
b) Little Endian
c) X-Little Endian
d) X-Big Endian
View Answer
Answer: a
Explanation: The way the data gets stored in a memory is called an address assignment.
9. The addresses generated by the 68000 is _____ bit.

a) 32
b) 16
c) 24
d) 42
View Answer
Answer: c
Explanation: The size of the address is directly related to the address space of the system.
10. Instructions which can handle any type of addressing mode are said to be ___________
a) Omniscient
b) Orthogonal
c) Versatile
View Answer
Answer: b
Explanation: These instructions do not require the mentioning of any one type of addressing mode.
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Motarola 680X0 Processor Architecture – 2
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This set of Computer Organization Quiz focuses on “Motarola 680X0 Processor Architecture – 2”.
1. The instructions in 68000 can deal with operands of three different sizes.
a) True
b) False
View Answer
Answer: a
Explanation: The operands are of different sizes because of the difference in the values.
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2. As the instructions can deal with variable size operands we use ____________ to resolve this.
a) Delimiter
b) Size indicator mnemonic
c) Special assemblers
View Answer
Answer: b
Explanation: To indicate the size of the operand we use a separate variable mnemonic to indicate it.
3. The starting address is denoted using _________ directive.

a) EQU
b) ORIGIN
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c) ORG
d) PLACE
A
View Answer
Answer: c
Explanation: The starting address is the location where the program is stored.
4. The constant can be declared using ___________ directive.

a) DATAWORD
b) PLACE
c) CONS
d) DC
View Answer
Answer: d
Explanation: To declare Global constants we use this directive.
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5. To allocate a block of memory we use ___________ directive.

a) RESERVE
b) DS
c) DATAWORD
d) PLACE
View Answer
Answer: b
Explanation: None.
6. The Branch instruction in 68000 provides how many types of offsets?

a) 3
b) 1
c) 0
d) 2
View Answer
Answer: d
Explanation: The Branch instruction basically just adds a constant value to the address present in the PC,
to change the instruction to be executed.
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7. The purpose of using DBcc as a branch instruction is __________

a) It provides two conditions to be satis ied for a branch to occur
b) It provides a counter to check the number of times the branch as taken place
c) It is used to check the condition along with the branch condition
View Answer
Answer: d
Explanation: None.
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8. The 68000 uses ____________ method to access I/O devices buffers.

a) Memory mapped
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b) I/O mapped
c) Buffer mapped
A
View Answer
Answer: a
Explanation: In this method, both the I/O device and the memory share a common address space.
9. ____________ instruction is used to set up a frame pointer for the subroutines in 68000.
a) CREATE
b) LINK
c) UNLK
d) FRAME
View Answer
Answer: b
Explanation: This pointer is used to monitor the stack.
10. The LINK instruction is always followed by ____________ instruction.

a) MOV
b) UNLK
c) ORG
d) MOVEM
View Answer
Answer: d
Explanation: None.
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ARM Architecture – 1
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focuses on “ARM Architecture – 1”.
1. ARM stands for _____________

a) Advanced Rate Machines
b) Advanced RISC Machines
c) Arti icial Running Machines
d) Aviary Running Machines
View Answer
Answer: b
Explanation: ARM is a type of system architecture.
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2. The main importance of ARM micro-processors is providing operation with ______

a) Low cost and low power consumption
b) Higher degree of multi-tasking
c) Lower error or glitches
d) Ef icient memory management
View Answer
Answer: a
Explanation: The Stand alone feature of the ARM processors is that they’re economically viable.
3. ARM processors where basically designed for _______
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a) Main frame systems
b) Distributed systems
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c) Mobile systems
d) Super computers
View Answer
Answer: c
Explanation: These ARM processors are designed for handheld devices.
4. The ARM processors don’t support Byte addressability.

a) True
b) False
View Answer
Answer: b
Explanation: The ability to store data in the form of consecutive bytes.
5. The address space in ARM is ___________

a) 224
b) 264
c) 216
d) 232
View Answer
Answer: d
Explanation: None.
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6. The address system supported by ARM systems is/are ___________

a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both Little & Big Endian
View Answer
Answer: d
Explanation: The way in which, the data gets stored in the system or the way of address allocation is
called as address system.
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7. Memory can be accessed in ARM systems by __________ instructions.

i) Store
ii) MOVE
iii) Load
iv) arithmetic
v) logical
a) i, ii, iii
b) i, ii
c) i, iv, v
d) iii, iv, v
View Answer
Answer: b
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Explanation: None.
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8. RISC stands for _________
a) Restricted Instruction Sequencing Computer
b) Restricted Instruction Sequential Compiler
c) Reduced Instruction Set Computer
d) Reduced Induction Set Computer
View Answer
Answer: c
Explanation: This is a system architecture, in which the performance of the system is improved by
reducing the size of the instruction set.
9. In the ARM, PC is implemented using ___________

a) Caches
b) Heaps
c) General purpose register
d) Stack
View Answer
Answer: c
Explanation: PC is the place where the next instruction about to be executed is stored.
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10. The additional duplicate register used in ARM machines are called as _______
a) Copied-registers
b) Banked registers
c) EXtra registers
d) Extential registers
View Answer
Answer: b
Explanation: The duplicate registers are used in situations of context switching.
11. The banked registers are used for ______

a) Switching between supervisor and interrupt mode
b) Extended storing
c) Same as other general purpose registers
View Answer
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Answer: a
Explanation: When switching from one mode to another, instead of storing the register contents
somewhere else it’ll be kept in the duplicate registers and the new values are stored in the actual
registers.
12. Each instruction in ARM machines is encoded into __________ Word.

a) 2 byte
b) 3 byte
c) 4 byte
d) 8 byte
View Answer
Answer: c
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Explanation: The data is encrypted to make them secure.
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13. All instructions in ARM are conditionally executed.
a) True
b) False
View Answer
Answer: a
Explanation: None.
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14. The addressing mode where the EA of the operand is the contents of Rn is ______
a) Pre-indexed mode
b) Pre-indexed with write back mode
c) Post-indexed mode
View Answer
Answer: c
Explanation: None.
15. The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is _______
a) EA = [Rn]
b) EA = [Rn + Rm]
c) EA = [Rn] + Rm
d) EA = [Rm] + Rn
View Answer
Answer: a
Explanation: Effective address is the address that the computer acquires from the current instruction
being executed.
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ARM Architecture – 2
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This set of Computer Organization MCQs focuses on “ARM Architecture – 2”.
1. ___________ symbol is used to signify write back mode.

a) #
b) ^
c) &
d) !
View Answer
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Answer: d
Explanation: None.
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2. The instructions which are used to load or store multiple operands are called as __________
a) Banked instructions
b) Lump transfer instructions
c) Block transfer instructions
d) DMA instructions
View Answer
Answer: c
Explanation: These instructions are generally used to perform memory transfer operations.
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3. The Instruction, LDM R10!, {R0,R1,R6,R7} ______
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a) Loads the contents of R10 into R1, R0, R6 and R7
b) Creates a copy of the contents of R10 in the other registers except for the above mentioned ones
c) Loads the contents of the registers R1, R0, R6 and R7 to R10
d) Writes the contents of R10 into the above mentioned registers and clears R10
View Answer
Answer: a
Explanation: The LDM instruction is used to load data into multiple locations.
4. The instruction, MLA R0,R1,R2,R3 performs _________

a) R0<-[R1]+[R2]+[R3]
b) R3<-[R0]+[R1]+[R2]
c) R0<-[R1]*[R2]+[R3]
d) R3<-[R0]*[R1]+[R2]
View Answer
Answer: c
Explanation: The MLA instruction is used perform addition and multiplication together.
5. The ability to shift or rotate in the same instruction along with other operation is performed with the
help of _________
a) Switching circuit
b) Barrel switcher circuit
c) Integrated Switching circuit
d) Multiplexer circuit
View Answer
Answer: b
Explanation: These switching circuits are used to basically switch fast and to perform better.
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6. _________ instruction is used to get the 1’s complement of the operand.

a) COMP
b) BIC
c) ~CMP
d) MVN
View Answer
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Answer: d
Explanation: The complement of all the bits of a data is its 1’s compliment.
7. The offset used in the conditional branching is __________ bit.

a) 24
b) 32
c) 16
d) 8
View Answer
Answer: a
Explanation: The offset is used to get the new branching address of the process.
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8. The BEQ instructions is used ____________
a) To check the equality condition between the operands and then branch
A
b) To check if the Operand is greater than the condition value and then branch
c) To check if the lag Z is set to 1 and then causes branch
View Answer
Answer: c
Explanation: This instruction is basically used to check the branch enable bit.
9. The condition to check whether the branch should happen or not is given by ____________
a) The lower order 8 bits of the instruction
b) The higher order 4 bits of the instruction
c) The lower order 4 bits of the instruction
d) The higher order 8 bits of the instruction
View Answer
Answer: b
Explanation: None.
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10. Which of the two instructions sets the condition lag upon execution?
i) ADDS R0,R1,R2
ii) ADD R0,R1,R2
a) i
b) ii
c) Both i and ii
d) Insuf icient data
View Answer
Answer: a
Explanation: This instruction sets the condition lag without considering whether a carry or over low has
happened or not.
11. __________ directive is used to indicate the beginning of the program instruction or data.
a) EQU
b) START
c) AREA
d) SPACE
View Answer
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Answer: c
Explanation: None.
12. ___________ directive speci ies the start of the execution.

a) START
b) ENTRY
c) MAIN
d) ORIGIN
View Answer
Answer: b
Explanation: This directive indicates the beginning of the executable part of the program.
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13. ___________ directives are used to initialize operands.
a) INT
A
b) DATAWORD
c) RESERVE
d) DCD
View Answer
Answer: d
Explanation: These directives are used to initialize the operands to a user de ined value or a default
value.
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14. ___________ directive is used to name the register used for execution of an instruction.
a) ASSIGN
b) RN
c) NAME
d) DECLARE
View Answer
Answer: b
Explanation: This instruction is used to list the registers used for execution.
15. The pseudo instruction used to load an address into the register is _________
a) LOAD
b) ADR
c) ASSIGN
d) PSLOAD
View Answer
Answer: b
Explanation: None.
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Intel IA-32 Pentium Architecture-1
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focuses on “Intel IA-32 Pentium Architecture-1”.
1. The address space of the IA-32 is __________

a) 216
b) 232
c) 264
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d) 28
View Answer
Answer: b
Explanation: The number of addressable locations in the memory is called as address space.
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2. The addressing method used in IA-32 is ____________

a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both Little and Big Endian
View Answer
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Answer: a
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Explanation: The method of addressing the data in the system.
3. The loating point numbers are stored in general purpose register in IA-32.
a) True
b) False
View Answer
Answer: b
Explanation: The loating registers are not stored in general purpose registers as they have a real part
and a decimal part.
4. The Floating point registers of IA-32 can operate on operands up to ___________

a) 128 bit
b) 256 bit
c) 80 bit
d) 64 bit
View Answer
Answer: d
Explanation: The size of the loating numbers that can be stored in the loating register.
5. The size of the loating registers can be extended upto _________

a) 128 bit
b) 256 bit
c) 80 bit
d) 64 bit
View Answer
Answer: c
Explanation: None.
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6. The IA-32 architecture associates different parts of memory called __________ with different usages.
a) Frames
b) Pages
c) Tables
d) Segments
View Answer
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Answer: d
Explanation: The memory is divided into parts called as segments.
7. The PC is incorporated with the help of general purpose registers.

a) True
b) False
View Answer
Answer: b
Explanation: Registers are not used to incorporate PC as in other architectures, but a separate space is
allocated to it.
8. IOPL stands for ________
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a) Input/Output Privilege level
b) Input Output Process Link
A
c) Internal Output Process Link
d) Internal Offset Privilege Level
View Answer
Answer: a
Explanation: This indicates the security between the transfers between the I/O devices and memory.
9. In IA-32 architecture along with the general lags, the other conditional lags provided are ___________
a) IOPL
b) IF
c) TF
View Answer
Answer: d
Explanation: These lags are basically used to check the system for exceptions.
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10. The register used to serve as PC is called as ___________

a) Indirection register
b) Instruction pointer
c) R-32
View Answer
Answer: b
Explanation: The PC is used to store the next instruction that is going to be executed.
11. The IA-32 processor can switch between 16 bit operation and 32 bit operation with the help of
instruction pre ix bit.
a) True
b) False
View Answer
Answer: a
Explanation: This switching enables a wide range of operations to be performed.
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12. The Bit extension of the register is denoted with the help of __________ symbol.
a) $
b) `
c) E
d) ~
View Answer
Answer: c
Explanation: This is used to extend the size of the register.
13. The instruction, ADD R1, R2, R3 is decoded as ___________

a) R1<-[R1]+[R2]+[R3]
b) R3<-[R1]+[R2]
R
c) R3<-[R1]+[R2]+[R3]
d) R1<-[R2]+[R3]
A
View Answer
Answer: d
Explanation: None.
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14. The instruction JG loop does ______

a) jumps to the memory location loop if the result of the most recent arithmetic op is even
b) jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0
c) jumps to the memory location loop if the test condition is satis ied with the value of loop
View Answer
Answer: b
Explanation: This instruction is used to cause a branch based on the outcome of the arithmetic
operation.
15. The LEA mnemonic is used to __________

a) Load the effective address of an instruction
b) Load the values of operands onto an accumulator
c) Declare the values as global constants
d) Store the outcome of the operation at a memory location
View Answer
Answer: a
Explanation: The effective address is the address of the memory location required for the execution of
the instruction.

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Intel IA-32 Pentium Architecture-2
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This set of Computer Organization Multiple Choice Questions & Answers focuses on “Intel IA-32 Pentium
Architecture – 2”.
1. The instructions of IA-32 machines are of length up to ______

a) 4 bytes
b) 8 bytes
c) 16 bytes
d) 12 bytes
View Answer
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Answer: d
Explanation: The size of instruction that can be executed at once.
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2. The bit present in the op code, indicating which of the operands is the source is called as ________
a) SRC bit
b) Indirection bit
c) Direction bit
d) FRM bit
View Answer
Answer: c
Explanation: None.
R
3. The __________ directive is used to allocate 4 bytes of memory.
A
a) DD
b) ALLOC
c) RESERVE
d) SPACE
View Answer
Answer: a
Explanation: None.
4. .data directive is used _________

a) To indicate the ending of the data section
b) To indicate the beginning of the data section
c) To declare all the source operands
d) To Initialize the operands
View Answer
Answer: b
Explanation: This is used to indicate the starting of the section of data.
5. The instruction used to cause unconditional jump is ________

a) UJG
b) JG
c) JMP
d) GOTO
View Answer
Answer: c
Explanation: This statement causes a jump from one instruction to another without the condition.
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6. __________ instruction is used to check the bit of the condition lags.

a) TEST
b) TB
c) CHECK
d) BT
View Answer
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Answer: d
Explanation: This is used to check the condition lags for exceptions.
7. REPINS instruction is used to __________

a) Transfer a block of data serially from an Input device to the processor
b) Transfer a block of data parallelly from Input device to the processor
c) Transfer a block of data serially from an Input device to the output device
d) Transfer a block of data parallelly from Input device to the output device
View Answer
Answer: b
Explanation: None.
R
8. Which of the following statements regarding Stacks is/are True?
i) The stack always grows towards higher addresses
A
ii) The stack always grows towards lower addresses
iii) The stack has a ixed size
iv) The width of the stack is 32 bits
a) i and iii
b) i and iv
c) ii and iv
d) iii and iv
View Answer
Answer: c
Explanation: The stack is a data structure which is ixed at one end and grows at the other.
9. The instruction used to multiply operands yielding a double integer outcome is _________
a) MUL
b) IMUL
c) DMUL
d) EMUL
View Answer
Answer: b
Explanation: This instruction is used to carry out multiplication on large integral values.
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10. SIMD stands for __________

a) Single Instruction Multiple Data
b) Simple Instruction Multiple Decoding
c) Sequential Instruction Multiple Decoding
d) System Information Mutable Data
View Answer
Answer: a
Explanation: This is the instruction used to perform an operation on multiple types of data.
11. The IA-32 system follows _________ design.

a) RISC
b) CISC
c) SIMD
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View Answer
Answer: b
Explanation: This system architecture is used to reduce the steps involved in execution by performing
complex operations in one step.
12. Which architecture is suitable for a wide range of data types?

a) ARM
b) 68000
c) IA-32
d) ASUS irebird
View Answer
R
Answer: c
A
Explanation: None.
13. In case of multimedia extension instructions, the pixels are encoded into a data item of _________
a) 16 bit
b) 32 bit
c) 24 bit
d) 8 bit
View Answer
Answer: d
Explanation: None.
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14. The MMX (Multimedia Extension) operands are stored in __________

a) General purpose registers
b) Banked registers
c) Float point registers
d) Graphic registers
View Answer
Answer: c
Explanation: These operands are used for graphic related operations.
15. The division operation in IA-32 is a single operand instruction so it is assumed that ___________
a) The divisor is stored in the EAX register
b) The dividend is stored in the EAC register
c) The divisor is stored in the accumulator
d) The dividend is stored in the accumulator
View Answer
Answer: a
Explanation: In the case of a division the divisor is pre-loaded onto the ALU.
To practice all areas of Computer Organization, here is complete set on 1000+ Multiple Choice Questions
and Answers on Computer Organization and Architecture.
1. Which of the following is true about Computer Architecture?
A. It acts as the interface between hardware and software.
B. Computer Architecture tells us how exactly all the units in the system are
arranged and interconnected.
C. Computer Architecture is concerned with the structure and behaviour of a
computer system as seen by the user.
D. It involves Physical Components
View Answer
Ans : A
Explanation: It acts as the interface between hardware and software is true statement
and all other statement are related to Computer Organization.
2. Which of the following is true about Computer Organization?

A. It deals with high-level design issues.
B. It involves Logic (Instruction sets, Addressing modes, Data types, Cache
optimization).
C. Computer Organization tells us how exactly all the units in the system are
arranged and interconnected.
D. None of the Above
View Answer
Ans : C
Explanation: Computer Organization tells us how exactly all the units in the system are
arranged and interconnected is true about Computer Organization and all other
statement are related to Computer Architecture.
3. Which format is used to store data?

A. BCH
B. BCD
C. Binary
D. Decimal
View Answer
Ans : B
Explanation: BCD format is used to store data.
4. The program written and before being compiled or assembled is

called ____________.
A. Start Program
B. Intermediate program
C. Source Program
D. Natural Program
View Answer
Ans : C
Explanation: The program written and before being compiled or assembled is called
Source Program.
1. How many types of Pipelining exist?

A. 2
B. 3
C. 4
D. 5
View Answer
Ans : A
Explanation: It is divided into 2 categories: Arithmetic Pipeline and Instruction Pipeline
2. Arithmetic Pipeline is used for?

A. floating point operations
B. interger operations
C. character operations
D. None of the above
View Answer
Ans : A
Explanation: Arithmetic pipelines are usually found in most of the computers. They are
used for floating point operations, multiplication of fixed point numbers etc.
3. Which of the following is not a Pipeline Conflicts?

A. Timing Variations
B. Branching
C. Load Balancing
D. Data Dependency
View Answer
Ans : C
Explanation: Load Balancing is not a Pipeline Conflicts.

4. Which of the following is disadvantage of Pipelining?
A. cycle time of the processor is reduced.
B. The design of pipelined processor is complex and costly to manufacture.
C. The instruction latency is more.
D. Both B and C
View Answer
Ans : D
Explanation: Both B and C are Disadvantages of Pipelining.
5. Which of the following is an advantage of pipelining?

A. Instruction throughput increases.
B. Faster ALU can be designed when pipelining is used.
C. Pipelining increases the overall performance of the CPU.
D. All of the above
View Answer
Ans : D
Explanation: All of the above are advantage of pipelining.
6. The processor contends for the usage of the hardware and might
enter into a ____________.
A. hazard state
B. Stalk State
C. Deadlock State
View Answer
Ans : C
Explanation: The processor contends for the usage of the hardware and might enter into
a deadlock state.
7. The Tomasulo algorithm is a hardware algorithm developed

___________.
A. 1966
B. 1967
C. 1968
D. 1969
View Answer
Ans : B
Explanation: The Tomasulo algorithm is a hardware algorithm developed in 1967 by

Robert Tomasulo from IBM. It allows sequential instructions that would normally be
stalled due to certain dependencies to execute non-sequentially
8. In Arithmetic Pipeline, the floating point addition and subtraction is

done in ____________ parts.
A. 2
B. 3
C. 4
D. 5
View Answer
Ans : C
Explanation: The floating point addition and subtraction is done in 4 parts: Compare the
exponents, Align the mantissas, Add or subtract mantissas, Produce the result.
9. ______ have been developed specifically for pipelined systems.

A. Utility software
B. Speed up utilities
C. Optimizing compilers
View Answer
Ans : C
Explanation: The compilers which are designed to remove redundant parts of the code
are called as optimizing compilers.
10. The pipelining process is also called as ______

A. Assembly line operation
B. Von Neumann cycle
C. Superscalar operation
View Answer
Ans : A
Explanation: It is called so because it performs its operation at the assembly level.

1. The main job of the interrupt system is to identify the ______ of the
interrupt.
A. signal
B. device
C. source
D. peripherals
View Answer
Ans : C
Explanation: The main job of the interrupt system is to identify the source of the interrupt.
2. The hardware interrupts which can be delayed when a much high

priority interrupt has occurred at the same time are known as
___________.
A. Non Maskable Interrupt
B. Maskable Interrupt
C. Normal Interrupt
View Answer
Ans : B
Explanation: Maskable Interrupt : The hardware interrupts which can be delayed when a
much high priority interrupt has occurred at the same time.
3. The interrupts that are caused by software instructions are called

______________.
A. Exception interrupts
B. Normal Interrupt
C. hardware interrupt.
View Answer
Ans : B
Explanation: Normal Interrupt : The interrupts that are caused by software instructions
are called normal software interrupts.
4. In Daisy Chaining Priority, the device with the highest priority is

placed at the ______.
A. First Position
B. Last Position
C. Can be placed anywhere
D. Depend on device
View Answer
Ans : A
Explanation: The device with the highest priority is placed at the first position followed by
lower priority devices and the device which has lowest priority among all is placed at the
last in the chain.
5. Which interrupt is unmaskable?

A. RST 5.5
B. RST 6.5
C. RST 7.5
D. Trap
View Answer
Ans : D
Explanation: The trap is a non-maskable interrupt as it deals with the ongoing process in
the processor.
6. Which microprocessor are designed to complete the execution of

the current instruction and then to service the interrupts?
A. 8081
B. 8082
C. 8084
D. 8085
View Answer
Ans : D
Explanation: The 8085 microprocessor are designed to complete the execution of the
current instruction and then to service the interrupts.
7. open-collector type circuits are generally used for ___________.

A. open-drain
B. Batch processing
C. interrupt service lines.
View Answer
Ans : C
Explanation: open-collector type circuits are generally used for interrupt service lines
8. The Interrupt-request line is a _________ along which the device is

allowed to send the interrupt signal.
A. Data line
B. control line
C. Address line
View Answer
Ans : B
Explanation: The Interrupt-request line is a control line along which the device is allowed
to send the interrupt signal.
9. Which table handle stores the addresses of the interrupt handling

sub-routines?
A. Interrupt-vector table
B. Vector table
C. Symbol link table
D. All of the above
View Answer
Ans : A
Explanation: Interrupt-vector table handle stores the addresses of the interrupt handling
sub-routines.
10. Interrupts initiated by an instruction is called as ____________.

A. Internal
B. External
C. hardware
D. Software
View Answer
Ans : B
Explanation: Interrupts initiated by an instruction is called as External
1. What is true about memory unit?

A. A memory unit is the collection of storage units or devices together.
B. The memory unit stores the binary information in the form of bits.
C. Both A and B
View Answer
Ans : C
Explanation: A memory unit is the collection of storage units or devices together. The
memory unit stores the binary information in the form of bits.
2. In how many categories memory/storage is classified?

A. 2
B. 3
C. 4
D. 5
View Answer
Ans : A
Explanation: Generally, memory/storage is classified into 2 categories: Volatile Memory

and Non-Volatile Memory.
3. When when power is switched off which memory loses its data?
A. Non-Volatile Memory
B. Volatile Memory
C. Both A and B
View Answer
Ans : B
Explanation: Volatile Memory: This loses its data, when power is switched off.
4. Auxillary memory access time is generally ________ times that of the

main memory
A. 10
B. 100
C. 1000
D. 10000
View Answer
Ans : C
Explanation: Auxillary memory access time is generally 1000 times that of the main
memory, hence it is at the bottom of the hierarchy.
1. Input or output devices that are connected to computer are called

______________.
A. Input/Output Subsystem
B. Peripheral Devices
C. Interfaces
D. Interrupt
View Answer
Ans : B
Explanation: Input or output devices that are connected to computer are called
peripheral devices.
2. How many types of modes of I/O Data Transfer?

A. 2
B. 3
C. 4
D. 5
View Answer
Ans : B
Explanation: Generally three types of modes which are : Programmed I/O, Interrupt
Initiated I/O, Direct Memory Access
3. Keyboard and Mouse Comes under?

A. Input peripherals
B. Output peripherals
C. Input-Output peripherals
View Answer
Ans : A
Explanation: Allows user input, from the outside world to the computer. Example:
Keyboard, Mouse etc.
4. The method which offers higher speeds of I/O transfers is ___________

A. Interrupts
B. Memory mapping
C. Program-controlled I/O
D. DMA
View Answer
Ans : D
Explanation: In DMA the I/O devices are directly allowed to interact with the memory
without the intervention of the processor and the transfers take place in the form of
blocks increasing the speed of operation.
1. What is the full form of RISC?

A. Read Instruction Set Architecture
B. Reduced Instruction Set Computer.
C. Register Instruction Set Computer.
View Answer
Ans : B
Explanation: RISC Processor : It is known as Reduced Instruction Set Computer.
2. What is the full form of CISC?

A. Complex Instruction Set Computer.
B. Completed Instruction Set Computer.
C. Control Instruction Set Computer.
View Answer
Ans : A
Explanation: CISC Processor : It is known as Complex Instruction Set Computer.
3. Which Processors includes multi-clocks?

A. Complex Instruction Set Computer
B. Reduced Instruction Set Computer
C. ISA
D. ANNA
View Answer
Ans : A
Explanation: CISC includes multi-clocks.

4. Which Processors Data transfer Register to register?
A. Complex Instruction Set Computer
B. Reduced Instruction Set Computer
C. ISA
D. ANNA
View Answer
Ans : B
Explanation: RISC Processors Data transfer Register to register.
6. Which of the following is true?

A. The RISC processor has a more complicated design than CISC.
B. Risc Focus on software
C. Cisc Focus on software
D. Risc has Variable sized instructions
View Answer
Ans : B
Explanation: RISC Focus on software is true.
7. Which processor requires more number of registers?

A. CISC
B. ISA
C. RISC
D. ANNA
View Answer
Ans : C
Explanation: RISC Requires more number of registers.
8. Both the CISC and RISC architectures have been developed to

reduce the ______
A. Semantic gap
B. Time Delay
C. Cost
D. Reduced Code
View Answer
Ans : A
Explanation: The semantic gap is the gap between the high level language and the low
level language.
9. Which of the following is true about CISC processor?

A. Micro programmed control unit is found in CISC.
B. Data transfer is from memory to memory.
C. In this instructions are not register based.
D. All of the above
View Answer
Ans : D
Explanation: All options are true.
10. Out of the following which is not a CISC machine.

A. IBM 370/168
B. Motorola A567
C. Intel 80486
D. VAX 11/780
View Answer
Ans : B
Explanation: Motorola A567 is not a CISC machine.
1. The register is used to hold the ________ which is used to access the
table.
A. Table
B. Pages
C. Address
View Answer
Ans : C
Explanation: The register is used to hold the address which is used to access the table.
2. The _____ is a hardware implementation to reduce the access time

for processor operations.
A. RAM
B. ROM
C. Cache
D. All of the above
View Answer
Ans : C
Explanation: The Cache is a hardware implementation to reduce the access time for
processor operations.
3. The access time of the magnetic disk is?

A. High
B. Low
C. Depend of disk
View Answer
Ans : A
Explanation: The access time of the magnetic disk is High.
4. Physical memory side the memory is divided into?

A. Blocks
B. Pages
C. Address
D. Pointers
View Answer
Ans : B
Explanation: On the physical memory side the memory is divided into pages.
5. Which of the following is false?

A. The virtual memory basically works as an extension of the RAM.
B. Each page might be allocated memory deferentially but the memory for
one page will be continuous.
C. The access time of the magnetic disk is much longer than the access
time of the memory.
D. The memory allocated to each page is contiguous.
View Answer
Ans : D
Explanation: The memory allocated to each page is contiguous is false statement.

6. The RUN signal increments the step counter by _____ for each clock
cycle.
A. One
B. Two
C. Three
D. No Limit
View Answer
Ans : A
7. The _________ is used to store the page numbers of the recently

accessed pages
A. Table
B. MMU
C. TLB
D. R1
View Answer
Ans : C
Explanation: The TLB is used to store the page numbers of the recently accessed
pages.
1. ARM stands for _____________.

A. Advanced RISC Microprocessors
B. Advanced RISC Management
C. Advanced RISC Machines
D. Advanced RISC Main frame
View Answer
Ans : C
Explanation: ARM stands for Advanced RISC Machines.
2. Instruction in ARM machines is encoded into __________ Word.

A. Two byte
B. Four Byte
C. Eight Byte
D. Six Byte
View Answer
Ans : B
Explanation: Instruction in ARM machines is encoded into Four Byte Word.
3. The address space in ARM is ___________

A. 2^8
B. 2^16
C. 2^32
D. 2^64
View Answer
Ans : C
Explanation: The address space in ARM is 2^32.
4. Which of the following is False?

A. The ability to store data in the form of consecutive bytes.
B. These ARM processors are designed for handheld devices.
C. ARM is a type of system architecture.
D. Both A and B
View Answer
Ans : A
Explanation: Option A is false.

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Bharati Vidyapeeth’s College of Engineering for Women, Pune

Department of Information Technology

Q.1) The smallest entity of memory is called as _______ .

Q.45) The reason for the implementation of the cache memory is

Q.1) …...Holds the last instruction fetched.

Which one of the following signed number

Question Question In which generation of computers history, the

Question Question which of the following is NOT a computer

Question Question The Von Neumann Bottleneck is due to which

A A Mismatch in speed between secondary

B B Mismatch in speed between CPU &Primary

Question The instruction register IR stores what?

Question Question The communication line between CPU

Question Question Execution of two or more programs by a

Question The term 'baud' is a measure of Question A bootstrap is

Question Question which of the following register holds address

Question Which of following is the prototype of all general purpose Question

Question Question The memory of IAS computer consist of how

Question What is Harvard architecture? Question What is Harvard architecture?

C physically separate storage &signal path ways for C

Question Control signals transmit which information between system Question

C C Greater range of memory location

Question Question What is the impact of increasing address bus

Which architecture allows simultaneous

Question Question Bit pair recording technique speeds up the

Electronic Numerical Integrator and

Which kind of architecture is used in

Question Which basic components are used in ENIAC?

Which kind of number system is used by

In n-bit Booth's multiplication algorithm,

Performance of a pipelined processor suffers

Consecutive instructions are dependent on

C Both A and B C The pipeline stages share hardware resources

D None of the above D All of these

The concept of pipelining is most effective in improving

A Require different amount of time A MIPS = Instruction count/(Execution time)10^

Valid and unimpeachable measurement of performance

For a given FINITE number of instructions to be

MFLOPS Rate = ( Number of executed

Operation performed by a processor, such as fetching an

Operation performed by a processor, such as fetching an

_____________________ becomes an important parameter

Question Question Machine capability can be enhanced

Performance of a program is affected by the way in which

Question Which of the following is/are characteristics of a benchmark Question

Which of the following instructions move

The law stating that the maximum speedup of a parallel

Who is regarded as the founder of Computer

As of 2000, the reference system to find

During the execution of the instructions, a

In Non-Restoring algorithms for division,

In Non-Restoring algorithms for division,

In Non-Restoring algorithms for division,

In Non-Restoring algorithms for division,

In Non-Restoring algorithms for division,

C Both A and B C In the form 3n

D None of these D In the form n/2

After performing Non-Restoring

In Restoring algorithms for division, if

In Booths algorithms for multiplication, if

In Booths algorithms for multiplication, if

In Booths algorithms for multiplication, if number of In Booths algorithms for multiplication,

In Booths algorithms for multiplication, if least In Booths algorithms for multiplication,

_ receives & sends data through ___ What is Pipelining ?

____ branch to location X if result is positive. _ operation stop program

______ operation place current program _ operation replace contents of

_ branch to location X if overflow _ branch to location X if

allow large programming tasks to be _ instruction that returns

A simple instruction format consists of _bit _________________ register: Used

contains the address of an instruction to _ contains the address of

Calculate Operands calculate _ address of ________ instruction perform

_: An instruction modifies a register or _ An instruction reads a

__ Approach is Dynamic: they depend on strategies attempt to improve

If a _ is to be taken, the hardware first In ______ it is possible to

when Set, causes an interrupt after the A ________________ is