ARM ADDRESSING FOR 32-BIT IMMEDIATE

AND MORE COMPLEX ADDRESSING MODES

32-BIT IMMEDIATE OPERANDS
Constants are frequently short and fit into a narrow field

Sometimes they are bigger

32-bit constants were more popular than others so included in ARM

12-bit operand2 field in the DP format is subdivided into two fields:

⚫ 8-bit constant field on the right
⚫ 4-bit rotate right field (rotates the 8-bit constant to the right by twice the
value in the rotate field

Number is represented as X * 22i

0 < X < 255 & 0 < i < 15

LOADING A 32-BIT CONSTANT
ARM machine code to load 32-bit constant into register r4
0000 0000 1101 1001 0000 0000 0000 0000 = 1422131210
8-bit constant field = 1101 1001 = D916 = 21710
4- bit rotate field = 8 (rotated right by 16 bits)
X * 22i = 217 * 22*8 = 217 * 216 = 217 * 65536 = 1422131210
MOV r0, D9 ROR 16

Cond F I Opcode S Rn Rd Rotate_imm mm_8

14 0 1 13 0 0 4 8 217
ADDRESSING MODES
There are different ways to specify the address of the operands
for any given operations (load, add or branch)

Addressing modes - The different ways of determining the

address of the operands

Information contained in the instruction code is the value of

the operand or the address of the result/operand
 ADDRESSING MODES (1)
1. Immediate Addressing
The operand is a constant within the instruction itself
ADD r2, r0, #5 ; r2 = r0+5
CMP r0, #1 ; r0 – 1
MOV r1, #1 ; r1 = 1

2. Register Addressing
Operand is a register
ADD r2, r0, r1

3. Scaled Register Addressing

Register operand is shifted prior to operation
ADD r2, r0, r1, LSL #2
IMMEDIATE ADDRESSING , REGISTER ADDRESSING
 ADDRESSING MODES (2)
4. PC Relative Addressing
Branch address is the sum of the PC and a constant in the
instruction
BEQ 1000

5. Immediate offset
Constant address is added to a base register
LDR r2, [r0, #8]

6. Register Offset
Another register is added to the base register
Array index is in one register and base of the array is in another
LDR r2, [r0, r1]
 ADDRESSING MODES (3)
7. Scaled Register Offset
Allows the register to be shifted before it is added to the base register
Useful to turn array index in to a byte address by shifting it left by 2
bits
LDR r2, [r0, r1, LSL #2]

8. Immediate offset Pre-Indexed

Facilitate the reading of sequential data in structures such as
arrays, tables, and vectors
A pointer register is used to hold the base address (r0)
An offset can be added to achieve the effective address
LDR r2, [r0, #4]! ; Effective Address r0+4
Loads r2 with the word pointed at by r0+4 ; then update the pointer
by adding 4 to r0
ADDRESSING MODES (4)

9. Immediate offset Post-indexed

Address in the base register is used to access memory first
Then constant is added or subtracted
LDR r2, [r0], #4

10. Register offset Pre-indexed

Same as immediate pre indexed except add or subtract a register
instead of a constant
LDR r2, [r0, r1] !
 ADDRESSING MODES (5)

11. Scaled Register offset Pre indexed

Same as register pre indexed except shift the register before
adding or subtracting it
LDR r2, [r0, r1, LSL #2]!

12. Register offset Post indexed

Same as immediate post indexed except add or subtract a register
instead of a constant
LDR r2, [r0], r1