SR FLIP FLOP si Q Cike———___} R —— a D FLIP FLOP D Da au cK a I [Ena | =o UW 7400 Quad 2 input 7404 Hex NOT Gates NAND GatesSTUDY OF FLIP FLOPS AIM: To study the logic of different flip flops and to verify the truth table of flip flops. APPARATUS REQUIRED: 1, Digital trainer kit 2. IC's 7474,7476,7400 THEORY: SR FLIP FLOP: The clocked SR flip-flop which consists basic NAND gates and two other NAND gates. The $ and R input control the gates of the flip flop on the same manner. As for the basic SR flip flop. Whenever as flip-flop does not respond to this input until the rising edge of the clock signal the clock pulse input as an enable signal for the other input. D FLIP FLOP The D (Delay) flip flop has only one input called the delay (D) input and ‘vo output Q and Q inserting between S and R assigning the symbol D to the S input. JK FLIP FLOP: A IK flip-flop has a character similar to that of an SR flip flop. In addition to the determinant condition of the SR flip-flop is permitted it. Input J and K to have take respectively. When § = » the flip-flop output toggle AT flip-flop is like a JK flip-flop. These are basically a single input versioh of JK flip-flops. This modified form of JK flip-flop is obtained by Connecting both inputs J and K together. It has only one input along with the lock input. These flip-flops are called T flip-flops because of the: ability to Somplerient its state (ie.) Toggle, hence the name Toggle flip-flop,T-FLIP FLOPPROCEDURE: 1. Connections are made on the digital trainer kit as per the circuit diagram. 2. Switch on the supply. 3. Note down the outputs from LED. TRUTH TABLE: S-R FLIP FLOP Clock | S Qui ‘Action pulse Practical _| Theoretical T Qn Qn. NO change. ° 9 Yeoek __| 1 L Vo Vo | forbidden. D-FLIP FLOP Clock pulse | Input Output Practical | Theoretical 1 0 ° ° C t 0 1 [nochange [ne chooge | | | molar =|o}—|0] 1 i 1 JK FLIP FLOP Clock pulse | J] K Quel Action Practical | Theoretical 0 | Gn in vy 1 oO 2 Roel 0 1 i 1 \ [aaa Set io | Ga __I Toaglo. T-FLIP FLOP ~|~l oles] {Clock pulse | Input | Output | (1) | Practical | Theoretical ( 0 [ras Tremors | | aoa yaa ae | EC) Ross {Son comm | logic gates IC's and specific IC's Thus, the truth table of flip-flop usi are studied and the truth table was verified.CIRCUIT DIAGRAM: Tetaog AB TABULAR COLUMN: i A B A’ By AB 0 0 1 L 5 ORGR emer 1 70 o 1 EO 0 7 - a | eet o~ o Tos X.No: A __| si pLIrIcaTION OF BOOLEAN FUNCTIONS AND ITS ate: 6(5(22. IMPLEMENTATION USING LOGIC GATES AIM: To simplify and to implement the given Boolean function using suitable gates. APPARATUS REQUIRED: 1. Digital trainer kit 2, IC’s 7404,7432,7408 IMPLEMENTATION OF BOOLEAN FUNCTION: 1. ¥=Em (0,1,2,3,12,13,14,15) 2. Y=nm (1,2,6,7) / SIMPLIFICATION: 1. Y=Em (0,1,2,3,12,13,14,15) CD] 00] O1 | 1] 10 00 (Asa or j{ofofo|fo boo ee io {o[o]0|]0 Y-AB+AB 2. Y=nm (1,2,6,7) [Ngc [oo] o1 [11] 10 AS : of afO, | 5 f/0} a | Fol o Y=(A+B+C’) (A’B’) (B'C)CA*BIC) ABR c a —| elo T ( 3 [| 9 FIL -|-|e|- a fa A alathl14 Ae eles R ra < L Ble Kol -]2° wo le l= he |o a [a/S| aa > z “ B lel ela joo & j E lole Sess 1 2 & a ° olo|- CIRCUIT DIAGRAM: B ATHEORY: A Boolean function is an algebraic expression formed using binary constants, binary variable and basic logic operating symbols. Basic logical operations include the AND function (multiplication). The OR function condition and NOT function complementation function condition and NOT function can be converted into a logical diagram compared of the AND, OR and NOT (input for) gates. The logical AND operation of two binary variables A and B given The logical OR operation between two Boolean variable A and B is given as Y= A+B. The logical complementation (input) operation the logical 1 to 0 and vice versa, this method is also called NOT operations. It is denoted by bar over the function. ba Thus, the given function is simplified and implemented by using suitable logic gates.PIN CONFIGURATION: , 1 2 3 4 s 6 7 3 « CIRCUIT DIAGRAM: Las bas | es L vee L sz ee ara e 82 + az Ba +16 sis ca 1 co 413 GND 12. adn at 40 s1 49 AT TS] XOR Gates ea 7486 Quad 2 inputDate: | - 4-22 DESIGN OF 4 BIT ADDER AND SUBTRACTOR CIRCUITS > AIM: To design and verify 4-bit adder and subtractor circuit. APPARATUS REQUIRED: 1. Digital trainer kit | 2. IC’s 7483,7486 THEORY: The 4 bit adder and subtractor circuit using 1C7483 and EX-OR is displayed. It can add two 4-bit numbers, say A (= Aa As Az Ai) and B (= By Bs By By) and produce sum output S (= Ss S; S2 Si). Co is the initial carry input and Cy is the final carry output. The 7483 IC can be used as a 4-bit binary adder-subtractor with some modifications. The 7483 IC receives the first operand (A) directly and other operand (B) through EX-OR gates. Each EX- OR gate receives the mode input (M) and one of the inputs of (B). When M=0 the circuit is an adder and when M=I it becomes a subtractor. When M = 0, the initial carry Cy = 0, one of the inputs of each EX-OR gates is 0 and each EX-OR gate passes the other input to its output (because X © 0=X). Thus, the second input to the 7483 IC is B and the circuit performs normal addition as follows: Initial carry Cy CC 0 + First operand A= AgA3 Ar Ate Second operand B= B, B; B, By Sum output S= Cr Si 3S Si When M = 1, the initial carry Co = 1, one of the inputs of each EX-OR. gate is 1 and each EX-OR gate produces the complement of its other input (because X@1 =X’). Thus the second input to the 7483 IC is the I's complement of B. This 1’s complement plus Co (which is actually 1) becomes the 2’s complement of B. Thus circuit adds the 2’s complement of BoA (ie. subtracts B from A), as shown below, Initial carry Cy Cy @ Cr Di First operand A= Ay Ay Ar Ars Second operand 1's complement of B B’, BBB Sum output Cy Ss $3 Sz SiSUBTRACTOR: \lith Carry vaithouk Corry (ol S=> o1ol oe qs tool Bo oW0 5 Carxvy lool 34 O10\ 5 © (00 SA ASodd > wit {Vib a wah ewouk CONS SabroukorPROCEDURE: 1. Connect Aj, Az, As, Ay and By, Bz, Bs, Ba given in the circuit also connect Cin in input side. 2, Connect $1, S2, Ss, Ss to the output side of the kit and also connect the C- out in output side. 3. Connect Ver to +5V and ground to ground terminal of kit. 4. For the adder set Ci-0 and set two different input values in A and B as four different digits. 5. The truth table and theoretical to the input side of the kit is table are filled and verified. ow ‘110 RESULT: > verified fmplementatioh of 4-bit adder and subtractor circuit has ‘Thus, t! successfully:Cireey Bindey BENARY CODE TO GRAY CODE CONVERSION: Tetath% vv 6lsi2 CODE CONVERTERS AIM: To construct a 4-bit binary to gray code and binary to excess 3 code convertors and to verify the truth table. APPARATUS REQUIRED: 1. Digital trainer kit 2. IC 7486 feor = Ab+RA DESIGN: . ‘ pO BINARY TO GRAY CONVERSION For G3 Bo] 00] 01 [11 [10 BB 00] 01 [11 | 10 o l[olololo ate or foo toto! a i 1 [ot ye TL 0 10 eas 10 1010 fa Gs=Bs Gi=By’B2+B2’Bi =O For G2 For Go 1Bo [00] O1 [11 [10 Bo | 00 | 01] 11] 10 BB? : B3B> oo [ololo|o oo | 0 (ao fa oO (eas | or | o [ajo {i u_lolololo nfo fifo |i 10 fafa io |o}ajfo{i ‘ \ 2 Bi Bot Bo B G:=By’B,+By’Bs 22 &o = ®2® 63 zhOREle -[-[°{o]-] 4ofof_|-]ole]_l-lo Re aol | 8 E[S}o] of-|-]- |-lolololo|_} |b lele 28 Be lolele|4-|-{4-[4-| 9} 0] oo Go} ofofo | ofofo]of-|_-}_|_|_|_]. 8] o-|4] -]-]e}o]-1- JoJo} fo 2 8 Sle 44-0 eo} Of o|-} -] -|-]o ]© =o & 3/5/2} 4 ©] of 4-|-|- -|-|-|]-| 9] o} ojo Om SO} clo} Of ofofofo}—|—)-] si f-} | at-l{-f4-/2}-2/--15|e)- taele-Clelat-tlelebdele < g 8]O]O]O}O]-|4]—|Hlolololo}a}ajalak) a [ABINARY TO EXCESS 3 por W for Y B] 00] 01 | 11 | 10 oD 0 [O10 1 or | OND tt | 0 Diy 10 | © LIN [y W=A+BC+BD For X po ty u © DI 10 OF TS c y-(c@py @CIRCUIT DIAGRAM: TRUTH TABLE:proCcEDURE: 1 Connections ai i re madi ; A ¢ down the output Fane H _ Disconnect the circuit rom LED's, igital trainer kit as per rcuit diagram. kit as per the cit it di , Kgl? RESULT: to gray conversion # Yhus, the binaly yand vert and binary to excess 3 conversion ied. circuits are desiBne®INVERTING MODE: model graph Vv INPUT VOLTAGE OUTPUT VOLTAGE AMPLITUDE AMPLITUDE TIME No. of. Div* No. of. Div* volt/div= time/div= \v LOOMS No. of. Div* No. of. Div* volt/div= 2x5 time/div= 2.90 (¢ ZwOV 260s NON-INVERTING MODE: “2 model graph INPUT VOLYAGE “OUTPUT VOLTAGE AMPLITUDE | TIME, AMPLITUDE TIME No. of. Div* time/div= 20M No. of. Div* volt/di No. of. Div™ No. of. Div voltidiv=22%S | time/div=24= No: 2 x. No: - _| STUDY OF OP-AMP OPERATING MODES AND ate: 25 03.22 COMPARATOR To study the op-amp under different operating modes like inverting and non-inverting modes and to design the comparator. APPARATUS REQUIRED: 1. Bread Board 2. Op-amp IC 741 3. Resistors ye 4. DCRPS(0-30V) 5. CRO THEORY: COMPARATOR: It is a circuit which compares the signal voltage at the input with a known self voltage at another input it basically an op-amp with output Vset. The output voltage at Vse for the Vin and Vier. Vo g08S to Vser from Vine Veet: INVERTING MODE: A Typically inverting resistance R and feedback resist across R and Comparator and voltage but code is 2 terminal is grounded. amplifier with input voltage V, and output ance Ry in the figure. There is no voltage drop ero as non-inverting input5 Yer sn Hz vt model graph INPUT VOLTAGE. TIME IN SEC [OUTPUT Vin Vref ON OFF | VOLTAGE Nook Div [No of Di* |No. of. Div* |No. of. Div* | No. of. Div® voldiv= | voltidiv= _| time/div=Uxs | time/divs 3's | volt/div= Av Ww Sy ise | ley PIN DIAGRAM: a — Offsetnull fine Inverting 7 e¥ee ‘aout ‘Non Inverting| [_JOutput ‘pout Ve {7 +0 ftetnull:Savertins HopROCEDURE: 1. Connections are made as ber the circuit diagram. 2. For an inverting amplifier the input was given to the negative terminal, therefore the given input Signal gives -180 phase shift by CRO. 3. For an non-inverting amplifier the input was given to the input gives without change in output, 4, For a comparator it compares the input measured signal at the given reference voltage measured by CRO. —) (0) fF OP-AMP has been studied by different modes using q “ristics of OP- Thus, the chargeteristics WANe oat No Rg Venu Mo! -§ Vie® Vint OUTPUT VOLTAGE PRACTICAL _| THEORETICAL OSV Opty ~Fav —B2N. =v ae Olay DIFFRENTIATOR: an ~An8M model graph Pec wl Vp = BS A INPUT VOLTAGE OUTPUT VOLTAGE pan FREQUENCY TIME PERIOD No. of. Div* volt/div= No. of. Div™ _ time/di bask Oar 22 oemAPPLICATION OF OP-AMP (gx. No: & __| pate: 22-04 22) AIM: To determine the adder, integrator, differentiator and verify the result using oP- amp. APPARATUS REQUIRED: 1. IC741 2. RESISTOR 1KQ,100 3. CAPACITOR 0.01 uF DESIGNING: \ ——— FEURTIRC=H60R= = gy Korte x0 ov ee = SAlaz THEORY: Beato ADDER OP-AMP may be used to design a circuit where output is the sum of several input signals. Such a circuit is called summing amplifier. Vou = RAR: (VitV2) SUBTRACTOR ‘A basic differential amplifier can be used as a subtractor. If all resistors are equal in value then the output voltage can be derived by using Vou = RAR; (Vi-V2) DIFFERENTIATOR One of the simplest circuits of OP-AMP that contains capacitor is the differentiating amplifier. As the name suggests the circuit performs the mathematical operation of differentiator, it conneets an input square wave form to spikes. Vou = Rr. Ci(Avidt) INTEGRATOR , This is a circuit that performs the operation of integration because it produces portional to integral of input voltage. the i ae Naa = (URIC LEV) at + VD) ] Forenalon : psdor, Vo =~ aL Mel 4 Viale} Tie centiates / Vo WE, ~RgdVinlde K Titlagyatior No =INTEGRATOR: INPUT VOLTAGE FREQUENCY TIME PERIOD VOLTAGE No. of. Div* No. of. Div* No. of. Div* Laskuz Squove_| wba sto basuttz — loax2 0-2 [Trtargle | We [tart 202] Sine WIS KHZ oar a = ORM PIN DIAGRAM:Agglicodtona 85 OF ACP S| TigderentiaborCaleulalion Vo <= - Rae Sul at — -RAe ANen Simi = - RA Cw Vm los ot = tow *2*T eg OS ie COSWE 0-01 mtg 6 No i- OATS COSACo tortalion b Vo = tL \ Vidb Rcd & 7 ( t ace \ Vorsin ext Ak -- |. Nm toosat } ag EL? - Vim Loscat eg oO Yo = O-Soors CostPROCEDURE: He Connections are Siven as per the circuit diagram. 2, For adder circuit, d.c input signals are given to the inverting terminal and the _s inverting terminal is grounded, the corresponding output are nol 3, For differentiator circuit, a.c, input signal is given to the inverting terminal and the non inverting terminal is grounded, the corresponding output are noted from the CRO. 4, For inverting circuit, a.c. input signal is given to the inverting terminal and the non inverting terminal is grounded, the corresponding output are noted from the CRO. Modah Sraeh Oukeuk Wlave dorm [ Didderentiator a fA | NV Tiwalid 6 Tapukt klavegoros, RESULT: Thus, the adder, op-amp IC 741. integrator, differentiator has been done by using thePIN CONFIGURATION ¢ Ic 5S5 Timer +Vee diechaage Thieshold Gp - Tatlg ger Output Reset COntaal Vol cageNe eit APPLICATION OF 555 TIMER MONOSTABLE aes MULTIVIBRATOR AIM: To design a monostable multivibrator circuits and to ge! i i ibrator d to get an desire waveform using IC 555, ; " APPARATUS REQUIRED: 1. IC'555 timer 2. Resistor- 6k, 12k,8.2kQ each one 3. DCRPS(0-30V) 4. Capacitor-0.01F 5. CRO. FORMULAE USED: TeLIR.C DESIGN: THEORY: LA monostable multivibrator often called a one-shot. sultan is a fhich the duration OF the pulse is determined pulse generating circuit in WI by the RC network connected externally to the 555 timer. 2, Ina stable or stand-by state the output of the circuit is approximately zero or at logic low level. When an ‘external trigger pulse is applied, the output ig forced to go high(approx. Vee) The time during which the output femains high is given by , f= 1.1 Rl G 1, the output automatically revsres‘back' to 3, At the end of the timing interval igs lage. nw sade. The tpt S187 low until a trigger pulSe is applied again. 4, Then the cycle repeats. 5, Thus the monostable state has only one stable state hence the name monostable.satis MULTVISRATOR ones Rabe, EL QeAPh : 3 Mobisemna) Ke uLTia! RATORPROCEDURE: + Circuit connection are given as per the circuit diagram, - Power supply is given. . For monostable multivibrator, trigger input is given from AFO . ‘The magnitude and time periods are noted from CRO, across the capacitor and output torminal, Bene TABULATION: Charging time | Discharging time | Frequency | Tot) Tove(us) on ete Across capacitor fete ‘ © Say ee] rae output OF NXDS = O-SM/IXOS © OSMlaggaz] (LZ Across output terminal (xO SMB] Le OS = OS Amel Judo LAN | 2IN Ve Non Ai toga oS AOS mS OS = \WAZ Thus, the monostable ntivigator ing 1CS5S timer has been done and output graph was drawn. wy (Xo ‘ ANPin ConPiouenTion + ess Tine Gly i Oupe fs 5 e 5 a CikCUIT Droseort + COntaot vortoge ASTARLS NuLTIVIBEATOR Ourpue 10 CRO oor RF | |APPLICATION OF 555 TIMER ASTABLE MULTIVIBRATOR se Hee **si8n an astable multivibrator circuit to get the desired waveform using timer IC 555, COMPONENTS REQUIRED: LIC 555 2. Resistor (6k, 12k) 3. RPS(0-5V) 4. Capacitor (0.01 F) 5.CRO Fe D: : ‘ORMULA USE) [AA = ome : ‘ by olsen eg i. Frequency, Sees Ta = (bacg snot NE ii, Dutyeycle, D=_RytRy _* 100 8% 33 gg coe tsS Tet "RR 684289) etsy, DESIGN: Frequency = 5kHz C= 0.01pF THEORY: 1. An astable multi-vibrator, often called a free-running multi-vibrator, is a rectangular-wave generating circuit. This circuit do not require an Scternal trigger f0 change the state of the output v— The time during which the output is either hjgl or low is determined eae as and a capacitor, which gréconnected externally to the pa eae time during which thé Capacitor charges from 1/3 Vc sao ae vrce is equal to the time the output is high and is given by, (2 cma te = 0,69 (Ry + Ry) CMone, Geapit ASTABLE MULTIVIGRATOR Lene. re) diene bres)5. The term duty cycle is often used in The duty cycle is the € total time p multivibrator. the output is high to th in percentage. In equation form, % duty cycle=[Ry/(R, or PROCEDURE: 1. Circuit connections are ta/ te x 100% 2. Power supply is given. 3. The magnitude and time periods are noted from CRO, across the Capacitor and output terminal. TABULATION: +2R))} x 100% conjunction with the astable ratio of the time t, during which riod T. It is generally expressed given as per the circuit diagram. charging time | Discharging time | Frequency Ton(#S) Torr(#S) f1/T(Hz) itor output | @. Om [ilevedid Practica) 9.9. Across capacitor outpi OA MS : ae | rei Across output terminal ! 6 ‘AT om wor | [66] Ww VT=f= 1.45 (Rat2Rp) C Rat2Rp = 28.8 Duty cycle= RytRo Rat2Rp (Rat2Rp) D=RatRe ; RatRp =28.8%0.6= 17.28 9 ———- ~ (2) Solving (1) and (2), Ra = §.87kQ = 6kQ. Ry = 11.52kQ= 12kQRESULT: Thus an Astable liv output graph was drawn, . ible ir @ ICSSS timer v has been done and thePIN DIAGRAM:DI Date: 290.52 EN OF 4-BIT MODULO SYNCHRONOUS COUNTER SING FLIP FLOP AND SPECIAL COUNTER IC AIM: To perform the 4-bit s ynchron¢ is i flop by using CTATS ous counter by IC74163 and using JK flip APPARATUS REQUIRED: 1. 174163 2. 1C7473, 3.. Trainer kit 4. Connecting wires THEORY: SYNCHRONOUS COUNTER: 'A synchronous counter is simplest type of binary counter as its requires Jess hard drive but its speed of operption is low because the cumulative and total time, setting time is producéd by {otal ‘number of Slip flop in the propagation delay of single flip flop: : problem encounte coding géte output. These problems can be “<{o all the flip flop simultaneously which is eration in the synchronous counter is a limited by the nd a flip flop. The design of the with ripple counter is glitches at the eliminated by applying clock “0° in this counter. The speed of op propagation delay of control gravity a synchronous counter,PIN DIAGRAM OPERATING MODE (Ount RESETDexign qf Synthroreus (ing AUellop CH od:) State Diasyom uOUy 90} Excitabion Tas (3) Rs “7 NS ae A ee we | Oo © Oo \V oO | xX j el , io ft | * i; 6 | \ | 0 6 | ° \ \ | ° \ | Ss || ge |e? x ee eei Demign | Sk AtedlogCl lock pulse Count 0 QT Q & 1 © 9 oO fo) 2 9 ° ° ( } 3 5 ! 0 q _O 0 \ 1 5 © \ } O 6 | 1 }° ' 7 a 1 : o 8 e \ . \ 9 6 } } 10 1 2 O ( ‘ ° \ } 12 4 o \ 1 13 1 5 ; o } oO \ 4 Tt : : a \ ' \ 1 f { { RESULT: Thus, the truth table using 1C74163 and 4-bit synchronous coun ous counter is verified experimentally of synchront nter is also designed and verified.PIN DIAGRAM: DECADE COUNTERDESIGN OF 4-] USING Hat MODULO ASYNCHRONOUS COUNTER OP AND SPECIAL COUNTER IC To perform the experiment JK flipflop by using 17476, APPARATUS REQUIRED: 1. 1C7476, 17493 2. Digital trainer kit 3. Connecting wires. THEORY: RIPPLE FACTOR: ton asynchronous counter using, 1C7493 & using, __ A asynchronous counter is the simplest in the terms of logical operations and is therefore their exists to design . In this counter , all the flip-flops are also not under the control of the single clock. Here the clock pulse is applied to the first flip-flop ie) the least significant bit single stage of the counter and the successive flip-flop is triggered by the output of the previous flip-flop Thus the count: has commulative setting fi Speed of operations is a limit . Thus 1* stage of counter thus the és first time on the application of a clock pulse to the first flip-flop faccessive states change . Thus the state is tum causing a flip through effect of the clock pulse as the ripple factor.DECADE COUNTER: high “Tortutaluon Roxer dled] outeuk | He | ea) Os | O | Qs! Os | ae Lyu | | wu | — lurk — | tL — Cunk — L |— CooPROCEDURE; 1. Connections are made as per the circuit diagram. 2. Switches on the supply and input. 3. operation at a noted down the output using LED’S. TRUTH TABLE: aE ES & a @ ieee 8 ° J } See 6 ai 5 T ae © } \ © ac. 2 9 \ l a \ 8 a ec © t 9 \ = } { \ 3 (nse eee ! \ t | ——>— \ } ° é = _._| 1 0 ° 1 Ly 1 o \ ° UW ) D \ 1 [io \ 1 } ° 13 pad 1 ° 1 Lg ‘ ( \ 9 | ! \ v T {| RESULT: Thus the truth table of asynchronous counter are also. verified experimentally. absEX No ae ic at SHIFT REGISTER AIM: ; hift register To design a 4 bit serial/parallel in and serial/parallel out sl and to verify the results, APPARATUS REQUIRED: 1. Digital trainer kit, 2. IC's 7474, TRUTH TABLE: SERIAL IN SERIAL OUT . ical Output Input | Clock | Theoretical output oe Q | Q | Pulse | Qs | Qs | Or Pree eee tee | | LO [re 2 ? a \ o d i iia || | TOM | 1 1 Saas see t t 0 eee ee ( i 0 1 jo} oft} i jojo} _+ fo }rfopotetit,te fot o a a a ew, our. SEEN AN PARNULEL 8PARALLEL IN PARALLEL OUT ‘Clock Iny Theoretical Output | Qc | Qo | Oulny 1 0 0 1 1 1 0 1 ir a 2 oe op lol |e / lolol | — } rlolo}-|H}H]-|Hlo, = Hlolo|=|-)-|—)- n|H|Hlof-lol-lolol? nla} |aplolo - |-|—o|-]0|-|a/elp| SERIAL IN PARALLEL OUT Clock | Input Theoretical output Practical output Pulse Q | @& Q 1 a O 1 ). d oO t plereepe LLEL IN SERIAL OUT . Theoretical _-~ Practical Output Outputs De Shift/Load=0 ‘Shift/Load=1 | Shift/Load=0 Shift/Load=1 0 Input [ms [Ta la, | [etTHEORY: D-Flip Flop: : This devices consist two implement positive edge triggered D flipflops with complementary output .The information on D input is accepted by the flipflop on the positive going edge. The clock pulse, the triggers occur set a voltage level and B required the D input may be changed while .The clock low or high without effecting are also not present or clear input will set or reset the input regardless of the logic levels of the clear input . SERIAL IN SERIAL OUT SHIFT REGISTER: It is the simplest blind of ‘shift register the data spring is presented at data and is shifter right one stage each timing data advance is brought high. At each advance the bit on the left the bit on the right shifted out and left. SERIAL IN PARALLEL OUT: ‘om serial to parallel format data The configuration allows conservation fr is input serially once the data been input it may be either read of at each output simultaneously or it can be shifted out and replaced. PARALLEL IN SERIAL OUT: The configuration has the shi -Dp) and shifts to comp case ft register takes the data from the parallel input(Da- ementary corresponding output(Qu-Qo) register are clocked. It can bi d has a final of history remaining old information has the input in another part of the system until ready for new jnformation were output upon the register and also clocked and the new details is not through are opened . PROCEDURE: 1. Switch on the supply. 2. Giye input the compounding input pins. 3. down the output using LED's. RESULT: Thus the 4 bit sh i designed and implemented using sul ift register In (SISO, PISO,SIPO,PIPO) modes is a itable IC's. yan”ein ora Geert Le W180 Lo@ic §=STMBOL: 2 Feo Wi. 204PARITY GENERATOR AND CHECKER pate: 27-05-22 USING IC74180 AIM: To study the odd/even parity generator/checker using IC 74180 and to verify the truth table. APPARATUS REQUIRED 1. 1C 74180. 2. Digital trainer kit. 3. Wires. TRUTH TABLE: ae | eee Even H it, H iy " Oda Po H u a Even L H L H u L Odd iL H | Hy UT pel x H H wi L Ll L x L L H cai| 63 THEORY: veces a cia rensmistion of data from one place to another it is . l€ Correctness of data is recei detection many methods are be poplar ete ‘ y available one of the Popular method is parity checking. In this method along the data one extra bit called Parity bit is added there are two types of parity bit available namely, 1, Even parity 2. Odd parity In an even parity system, the parity bit is added to the word to be transmitted is chosen so that number of is the modified is even. In an odd parity system the parity bit has added to the word to be transmitted to be chosen so that the number of is in the modified data is odd . PROCEDURE: 1. Connections are made as per the circuit diagram. 2. Switch on the supply and then the inputs. 3. Note down the output using multi-meters. RESULT: Thus using I S180, pari its truth table for various combinations 0 C 74LS180 , parity checked, generator Is signed and lata and parity is verified .Pin Diagram for 8:1 MUX MULTIPLEXER: Logic Circuit: D ale |Z al2 [es]lea BLE [:2}l> SE] ay [io] ea oF =] 8 & 8E a ae [8 se 8 Lf,pate 24-0429) MULTIPLEXER AND DEMULTIPLEXER I AIM: | table. To construct 8:1multiplexer and 1:8 de-multiplexer and verify the truth Apparatus required: He a 3. 4, IC 74151 IC 74155 Digital trainer kit Connecting wires THEORY: Multiplexer: be rot and a single output line. The selection of a particul It is a digital switch. It allows digital information from several sources to uted into a single output lone. The base multiplier has several data input Jar input line is controlled by a set of select lines. TRUTH TABLE: MULTIPLEXER (8:1) Enable | Address Selection Tnput ‘Output a TAL AL] Ae} De | Dr [Bs [Bs [De Ts PDs | ¥ ab x px px px px x tx [x | x) L oot stele ti a ate Se L tooo pa px pe x x {x [xs x L ie po px |x pe x txt x ia L raat a el x [x L Li 1 |0 [| 0 xX x |x |e [x [x |x L iq 1 0 ae x Tx Lx Lx [oe Tx] x L L 1 1 0 x | x x x x x |Lt{|x L L cia pf x x [x xx [x [x Te cs polo po | eT x Tx [x |x |x {x H | htporpe pf et x Lx | x [x |x H | pete oe woLx px |b Txt x H tox [x fx fate H[x{x| LPO px pe x of x tt x LX LX ax pL {i | | x [HL +t x Lx [#voc Fs % mM Om Sm Ow Oe wo) [3] TEE EEE ae Fa Ea M1 Oxy O22 O12 Og GND ‘Connection diagram for cascaded Two 1:4 into 1:8 DEMUX —> Yo (0) —» Y3 (1b) }—> Y2 (2) [> ¥2 a) I> Ya (0'a) I> ¥5 (1a) > Y6 (2) * Y7 (29)DEMy,, It TPLEXER, lines. The : Circuit that selection lings to? of Teceives information in one of the 2" possible output Specific output line is controlled by values of the n le] number of oi Ine application i in: . F ae In case if more tye ie pea We cannot implement by a single integrated circuit. ICs are cago, d to tput Tequires a higher order de-multiplexer with more fuifi, Pins are needed, then two or more de-multiplexer cascaded to pet single 1:4 the requirement. Here we can do two 1:4 DEMUX *8 DEMUX. TRUTH TABLE: DEMULTIPLEXER (1:8) Input | Adare: i ss Slecion ] oa Da _|_s: = 7 & Yi ¥ Lys ba | es Lye |v, 7 De oO [ayy 1 1 1 1 iat | ae . (OR ao [anes 1S Lan || [mT | H nmi EO [tes pete tera [otal TL L 1 | (aes oa co] H OM} 6 [OR is) asta rel vt [eto | ae TT | ws 0 | eae | a [i H 0 1 env eae 1 | i a ea [aa i Te a + [aan | a a | | | AT H a ea | | A Ta as | | L 0 1 ie st a 1 1 sa ET Sa 2H [RE | || | || | | Ea | La || | Hi es | RA | | TM A A | [ee | 1] [| 1 a | | [TT H ca | a | | | a a | | | | PROCEDURE: 1. Connections are made as per the IC pin diagram. 2. Switch on the power supply and then give the input. 3. Note down the outputs using LEDS. hy © ‘Thus the 8:1 multiplexer and 1:8 demultiplexers is studied and done successfully.10:4 ENCODER Logic circuit: Yor Ye Ys ¥y Ys Ye Ya 9 2:4 DECODER Logie circuit:ENCODER AND DECODER u e iM i Ml output, M HL ut Lit [ala a ee Tahoe Ee H H ale lh H E i Input 4 H Digital trainer kit IC 74LS147 IC74LS155 connecting wires To study the 10:4 encoder and 2:4 decoder. mH Ts 3. 4. He TRUTH TABLE: 10:4 Encoder & APPARATUS REQUIRED:Voc Eb Dx Om Oty dp GeO fo} [2] ») 1c 74155 SUG Tw M Om Cra Om Oy GHD Enable . Input | out = *e A 0; L Oy x L H _ A : x H - 4 : i H L if, L L 4 : Pe ee H L L \ f i ' : : Bee V H Hu nl lea | gHRORY: ‘The pin diagram of IC 74147 decimal to BCD priority encoders. It has | v input representing inverted BCD code corresponding to the highest onder activated input . When the input (Ip—I,) are high. All output are high when pis low, the ABC output is 0110 which is the inverse of 1001. The BCD code | for 9 when Is is low , the ABCD output is 0111. The BCD code for 8.hence the output of IC 74147 will normally high. When one at input is activated,this is corresponding the decimal 0 input condition since there is no Io input state when all the inputs were high. | active low logic circuit which convert coder put are different. The input code ce a different A decoder is a multiple input or output input to coder output, where the input and out generally 4 bits then output code back input code words produ output code word. There is one to one mapping from input code words into output code words. PROCEDURE: 1. Connections are given as per the circuit diagram. +2, Switch on the supply and the inputs. 3. The output are obtained from the LEDS. ie al SULT: n of encoder and decoder are studied and the truth table Thus, the operatior | | is verified. | |CMOS NAND au ae J] ee | [A] lar I ia Ce & CMOS NOR wes, ee er | aus >4 | (No:12 | SIMULATION OF TTL AND CMOS LOGIC pate: 2b 0-29} GATES FAMILIES | (NAND &NOR GATES) L - | |AIM: | To simulate the TTL and CMOS logic gates families. | APPARATUS REQUIRED: | PC, multism | THEORY: Input CMOS NAND gate: | ‘Two input gates which consists of two p-type units in parallel and two n- | type units in series QI and QO from the complementary connection. Q3 and Q4 from another complimentary connection. If the both the inputs are high both p channel transistor tun off and both n-channel transistors turn ON. The output has a low impedance to ground and produce a low state. | If any input low, the associated n-channel transistor is turned off and on the associated n-channel is tumed off and the associated p-channel transistor is turned on. ‘The output is coupled to Vjp and goes to the high state. ‘This function as a lo} ID gate the 74100 is Quad -2 input NAND gates. To produce the positive and function the output of the CMOS NAND gates can be connected to a CMOS counter. INPUT CMOS NOR GATE: Two inputs CMOS NOR gates using a pin of PMOS [QI & Q2] and NMOS transistor [Q3 & Q4] of the two inputs A & B either of the input ean tum on PMOS or MNOS device connected to it. When both the inputs are also low PMOS device on both the NMOS off. The output is coupled to Vpp and goes to the high state. 1f the input is high the associated p-channel transistor is tuned off and the associated n-channel transistor is turned on. 88 Sl ce seTTLNANDThis connects to the ground causing the low output, thus the circuit functions as a NOR gates.An CMOS OR gate can be formed by combining the output of the CMOS NOR gates with CMOS invertor. UT TTL NOR GATES: The circuit diagram of TTL NOR gates put transistor Q3 & Q4 that one connected in parallel to Q5 & Q6 from a pole output in the circuit. OPERATION: When the inputs are low the BE junction of QI and Q2 are forward biased to pull current away from the transistor Q3 and Q4 keeping them off as a result Q5 is on Q6 and tum off QS producing low output. ‘When aninput A is low and B is high Q3 is off and Q4 is off, on the transistor Q4 turns on Q6 and turns of Q5 producing, the low output, When both the inputs A and B are high transistor Q3 and Q4 are ON this has the same effect as either one being on turning Q6 and Q5 off, this result is low output, thus this function as NOR gates. TWO INPUTS TTL NAND GATES: There are two transistor stages in the circuit, A multivibrator input transistor and output transistor, function of multivibrator transistor is same as that of the two-parallel transistor with common base two collectors” terminals. OPERATION: When the two emitters of the circuit transistors are also connected to a high voltage. When emitter base junction of the transistor is reverse biased that means the transistor is in reverse active mode. In this mode in magnitude current flow in opposite direction. A current reaches base of the output transistor, always it is to conduct and pulling systems show the output voltage to 0. When only one of the input terminals is low, The current through the other branch flow through this terminal. However, no current reaches the basic terminals of the output transistor output remains as static, RESULT: TTL NAND, NOR 90on? 7 Logic ie wa® gyovr0e? gate. wo! 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