Multilevel Gate Networks

Reouven Elbaz
reouven@uwaterloo.ca
Office room: DC3576
 Outline

y Wh
Whatt is
i a Multilevel
M ltil l Gate
G t N
Network?
t k?
{ Example

y New gates: Universal gates

{ NAND

{ NOR

y Functionally complete set of gates

y Multilevel NAND circuits
y Multilevel NOR circuits
 What is a Multilevel Gate Network?

y # of levels of gates:
maximum # of gates cascaded
in series between an input and
output (inverters excluded).
y # levels of gates is
proportional to total
propagation i delay
d l through
h h
logic.
y Decreasing the # of levels can
decrease / increase the # of
gates and inputs
 Example – AND-OR Network
cd
y f(a,b,c,d)=∑(1,5,6,10,13,14)
00 01 11 10
00 m0 1 m1 m3 m2

ab 01 m4 1 m5 m7 1 m6

11 m8 1 m9 m11 1 m10
10 m12 m13 m15 1 m14

y f =a
=a’c’d
c d + bcd
bcd’ + b
b’c’d
c d + acd
acd’

Network #level #gates #inputs

AND-OR 2 5 16
 OR-AND-OR Network

y f = a’c’d + bcd’ + b’c’d + acd’

=(a’ + b’) c’d + (a + b)cd’

Network #level #gates #inputs

AND-OR 2 5 16
OR-AND-OR 3 5 12
 OR-AND Network
cd
y The product of sums 00 01 11 10
expression of f is obtained 00 0 1 0 0
m0 m1 m3 m2
using the 0’s in the 01 0 1 0 1
ab m4 m5 m7 m6
karnaugh map:
11 0 m8 1 m9 0 m11 1 m10
10 0 m12 0 m13 0 m15 1 m14

y ff’ = c
c’d’
d + cd + ab
ab’d
d+a
a’b’
b dd’
f = (c’d’ + cd + ab’d + a’b’ d’)’
DeMorgan’s
f ( d)( ’ d’)( ’ b d’)( b d)
f=(c+d)(c’+d’)(a’+b+d’)(a+b+d)
Network #level #gates #inputs
AND-OR 2 5 16
OR-AND-OR 3 5 12
OR-AND 2 5 14
 AND-OR-AND Network

y f=(c+d)(c’+d’)(a+b+d)(a’+b+d’)
= (cd’+c’d)(ab+ad’+a’b+b+bd’+a’d+bd)
=(cd’+c’d)(b+ad’+a’d)

Network #level #gates #inputs

AND-OR 2 5 16
OR-AND-OR 3 5 12
OR-AND 2 5 14
AND-OR-AND
AND OR AND 3 7 15
 Outline

y Wh
Whatt is
i a Multilevel
M ltil l Gate
G t N
Network?
t k?
{ Example

y New gates: Universal gates

{ NAND

{ NOR

y Functionally complete set of gates

y Multilevel NAND circuits
y Multilevel NOR circuits
 Universal gate NAND

y Truth table ((O= ((ab)’)

)) a b AND NAND
(O)
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0

y Gate Symbol:
 Universal gate NOR

y Truth table: : O= (a+b)’

( )
a b OR NOR
(O)
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0

y Gate Symbol:
y
 Functionally Complete set of gates

y A set of logic operations is said functionally complete if

any B
Boolean
l ffunction
i can b
be expressed
d iin terms off this
hi set
of operations.
Example
a p e of
o Functionally
u ct o a y Complete
Co p ete Set
AND, OR, NOT
AND, NOT
NAND

y Show why AND and NOT gates can realize an OR gate:

X+Y=(X+Y)’’=(X’.Y’)’
 Multilevel NAND circuits

y How to implement NOT and AND, OR operations with NAND gates:

y NOT:

y AND:
a.b=(a.b)’’

y OR:
a + b = (a+b)’’=(a’.b’)’

y Equivalent Symbol: (ab)’ = (a’+b’)

 From AND-OR to NAND-NAND

y 1st Method: DeMorgan’s

g and Boolean expression
p
{ f = a+bc'+b'cd

{ f = (a+bc’+b’cd)’’ = (a’.(bc’)’.(b’cd)’)’
 From AND-OR to NAND network

y 2nd Method: Graphically

p y
y f = a+bc'+b'cd

{ f = (a
(a’.(bc’)’.(b’cd)’)’
.(bc ) .(b cd) )
 From AND-OR to NAND-NAND
Example 2 (1/2): 1st Method

y f =a’c’d + bcd’ + b’c’d + acd’

y f= (a’c’d + bcd’ + b’c’d + acd’)’’

=((a’c’d)’(bcd’)’(b’c’d)’(acd’)’)’
((a c d) (bcd ) (b c d) (acd ) )
From AND-OR to NAND-NAND
Example 2: 2nd Method
 Multilevel NOR circuits

y How to implement NOT and AND, OR operations with NOR gates:

y NOT:

y OR:
a+b=(a+b)’’

y AND:
ab =(ab)’’= (a’+b’)’

y Equivalent Symbol: (a+b)’= a’b’

 From OR-AND to NOR-NOR
Example

y f=(c+d)(c’+d’)(a+b+d)(a’+b+d’)

y f=((c+d)(c’+d’)(a+b+d)(a’+b+d’))’’=
=((c+d)’+(c’+d’)’+(a+b+d)’+(a’+b+d’)’)’
From OR-AND to NOR-NOR
Example
p