Reduction 

of States and Flow Tables
• How to reduce the number of internal states in an asynchronous
sequential circuit ????

• The algorithm, that was used in chapter 5 for state reduction of a

complete state table in synchronous sequential circuits, will be modified
to cover the state reduction of asynchronous sequential circuits.

¾ Implication Table

¾ Merging of the Flow Table

¾ Compatible Pairs

¾ Maximal Compatibles

¾ Closed Covering Condition

©  2010  Dr. Ashraf Armoush , An‐Najah National University  40

Implication Table
• Two states in a state table can be combined into one, as long as 
they can be shown to be equivalent
• Equivalent States: Two states are equivalent if, for each possible 
Equivalent States: Two states are equivalent if, for each possible
input, they give exactly the same output and go to the same next 
states or to equivalent next states.  

– a and b have the same output for the same input, their next states are 
c and d for x=0 and b and a for x = 1
– If we can show that (c and d) are equivalent, then (a and b) are 
( ) ( )
equivalent.  Î [(a,b) imply (c,d)]
©  2010  Dr. Ashraf Armoush , An‐Najah National University  41
 Implication Table (cont.)
• The checking of each pair of states for possible equivalence in a
table with a large number of states can be done systematically by
means of an implication table.

• It is a chart that consists of squares, one for every possible pair of

states.
– On the left side along the vertical are listed all the states defined in the
state table except the last.
– Across the bottom horizontally are listed all the states except the last.
– The states that are not equivalent are marked with (X) in the
corresponding squares.
– The states that are equivalent are marked with (9) in the
corresponding squares.
– Some of the squares
q have entries of implied
p states that must be
further investigated to determine whether they are equivalent or not.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  42

Implication Table (cont.)

1. Place a cross in any square corresponding to a pair whose outputs are not equal
2. Enter in the remainingg squares
q the p
pairs of states that are implied
p byy the p
pair of
states representing the squares. (Start form the top square in the left column
and going down and then proceeding with the next column to the right).
3. Make successive passes through the table to determine whether any additional
squares should be marked with a ‘x’ x.
4. Finally, all the squares that have no crosses are recorded with check marks.
©  2010  Dr. Ashraf Armoush , An‐Najah National University  43
 Implication Table (cont.)
¾ The equivalent states are:
(a, b), (d, e), (d, g), (e, g).
¾ Combine pairs of states into larger groups of
equivalent states.
(a, b), (d, e, g)
¾ The final partition consists of:
ƒ The equivalent states found from the
implication table [(a, b) (d, e, g)]
ƒ All the remaining states in the state table
that are not equivalent to any other state.
[(c) , (f)]
Present  Next State Output
State
Î(a b) (c) (d,
Î(a, (d e,
e g) (f) {4 states} x=0
0 x =1 1 x=0
0 x=1
1
a d a 0 0
™ The original flow table can be reduced from c d f 0 1
7 states into 4 states: d a d 1 0
f c a 0 0
©  2010  Dr. Ashraf Armoush , An‐Najah National University  44

Merging of the Flow Table

• When certain combinations of inputs or input sequences may never
occur because of external and internal constrains Î The state table
is incompletely
p y specified.
p
• Incompletely specified states can be combined to reduce the
number of states in the flow table.
• Such states cannot be called equivalent, but, instead they are said
to be compatible.
• In order to find a suitable group of compatibles for the purpose of
merging a flow table, the following steps must be applied:
1. Determine all compatible pairs by using the implication table.
2. Find the maximal compatibles using a merger diagram.
3. Find a minimal collection of compatibles that covers all the states
and is closed.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  45
Compatible Pairs

• Compatible States: Two states are compatible if in every column of

the corresponding rows in the flow table, they are identical or
compatible states and if there is no conflict in the output values.
values

The compatible 
pairs are :
i
(a , b)
(a , c)
( d)
(a , d)
(b , e)
(b , f)
(c ,d)
(e , f)

©  2010  Dr. Ashraf Armoush , An‐Najah National University  46

Maximal Compatibles

• Maximal compatible: is a group of compatibles that contains all 
the possible combinations of compatible states.
• A merger diagram can be used to obtain the maximal compatible.
A merger diagram can be used to obtain the maximal compatible

¾ All possible compatibles can be found from the geometrical

patterns in which states are connected to each other.
©  2010  Dr. Ashraf Armoush , An‐Najah National University  47
 Closed Covering Condition

• The condition that must be satisfied for row merging is that the set 
of chosen compatibles must: 
1.
1 Cover all states.
Cover all states
2. Be closed:  ( the closure condition is satisfied if there are no implied states or 
if the implied states are included within the set)

Î In the last example, the  maximal compatibles are (a , b) (a , c , d) (b , e , f)
• if we remove (a , b), we get a set of two compatibles: (a , c , d) (b , e , f)

™ All the six states are included in this set. 9
™ There are  no impiled states for (a,c); (a,d);(c,d);(b,e);(b,f) and (e,f) [you 
can check the implication table] . Î the closer condition is satisfied 9

Î The original primitive flow table can be merged into two rows, one for 
g p f g , f
each of the compatibles.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  48

Ex: (Closed Covering Condition)

• From the given implication table, we have the following
compatible pairs:
(a,b)(a,d)(b,c)(c,d)(c,e)(d,e)
• From the merger diagram,
diagram we determine the maximal
compatibles:
(a,b) (a,d)(b,c)(c,d,e)
• If we choose the two compatibles
(a,b) (c,d,e)

™ All the 5 states are included in this set. (9)

™ The implied states for (a,b) are (b,c). But (b,c) are not
include in the chosen set Î This set is not closed. (X)
™ A set of compatibles that will satisfy the closed
covering condition is ( a , d ) ( b , c ) ( c , d , e )
©  2010  Dr. Ashraf Armoush , An‐Najah National University  49
Notes

• The same state can be repeated more than once.

• There may be more than one possible way of merging rows

when reducing a primitive flow table.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  50

Race‐Free State Assignment
• Once a reduced flow table has been derived, the next step in the
design is to assign binary variables to each stable state.

• The main objective in choosing a proper binary state assignment is

the prevention of critical races.

¾ Adjacent Binary Values: 2 binary values are said to be adjacent if

they differ in only one variable ( e.g.
e g 010 and 011 are adjacent)

‰ 2‐Row Flow‐Table:
The assignment of a single variable to a flow table with two rows
does not impose critical race problems.
[two adjacent values 0 and 1]

©  2010  Dr. Ashraf Armoush , An‐Najah National University  51
 3‐Row Flow‐Table Example

• A flow table with 3 states requires an assignment of 2

variables.
• We have the following transitions:
aÆb , aÆc, bÆa , bÆc&cÆa
(see the transition diagram)
• If we take the following assignment:

State Value
a 00
b 01
c 11

• Î This assignment will cause a critical race during the

transition from a to c (2 changes in the binary state ),
and also from c to a

©  2010  Dr. Ashraf Armoush , An‐Najah National University  52

3‐Row Flow‐Table Example (cont.)

• A race‐free assignment can be obtained by adding an extra row to the original 
flow table : 
¾ The
Th use off an extra
t row will
ill nott increase
i
the number of binary state variables (2
variables), but it allows the formation of
cycles
y between two stable states.

¾The added row (d) is assigned the binary

value (10), which is adjacent to both a & c.

¾The transition from a to c must go

through d, thus avoiding a critical race.

¾The two squares with dashes in row d

X
represent unspecified states (don’t care).
These squares must not be assigned to 01
in order to avoid the possibility of stable
state being established in the 4th row.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  53

 3‐Row Flow‐Table Example (cont.)

• The new flow table is converted to a transition table to complete the design 
process. 

©  2010  Dr. Ashraf Armoush , An‐Najah National University  54

4‐Row Flow‐Table Example

• A flow table with 4 states requires an assignment

of two state variables.

• If there were no transitions in the diagonal

direction (from a to c or from b to d), it would be
possible to find adjacent assignment for the
remaining 4 transitions.

• Î In order to satisfy the adjacency requirement,

requirement
at least 3 binary variables are needed.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  55
 4‐Row Flow‐Table Example (cont.)

• The following state assignment map is suitable for any 4‐row flow table.
– a, b, c, and d are the original states.
– e,
e ff, and g are extra states.
states
– States placed in adjacent squares in the map will have adjacent assignments

©  2010  Dr. Ashraf Armoush , An‐Najah National University  56

4‐Row Flow‐Table Example (cont.)
• To produce cycles:
– The transition from a to d must be directed through the extra state e
– The transition from c to a must be directed through the extra state g
– The transition from d to c must be directed through the extra state f

Although the flow

table has 7 rows,
there are only 4
stable states.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  57
Multiple Row Method for race‐free assignment  
• It is less efficient than the previous method (shared row method).

• Each state in the original flow table is replaced by two or more

combinations of state variables.
e.g.:
g
a is replaced with a1 and a2, where a1 is the logical complement of a2

• Î Each
E h stable
bl state has
h two binary
bi assignments
i with
i h exactly
l the
h
same output
e.g.:
The output values must be the same in a1 and a2

• At any given
i ti
time, only
l one off the
th assignments
i t is
i in
i use.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  58

Multiple Row Method (cont.)

• e.g. a1 is adjacent to b1, c2, and d1 where a2 is adjacent to c1, b2, d1

• When choosing the next state for a given present state, a state that is
adjacent to the present state is selected from the map.
©  2010  Dr. Ashraf Armoush , An‐Najah National University  59
 Hazards
• In order to ensure the proper operation in asynchronous circuits , the
circuits must be:
1. Operated in fundamental mode with only one input changing at any time.
1 time
2. Free of critical races.
3. Checked for hazards .

• Hazards are unwanted switching transients that may appear at the

output of a circuit because different paths exhibit different
propagation delay.

• Hazards occur in in combinational and asynchronous circuits:

– In combination circuits, they may cause a temporarily false output value.
– In asynchronous circuits, they may result in a transition to a wrong stable state.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  60

Hazards in Combinational Circuits

x1 x2 x3 AND 1 AND 2 Y
1 1 1 1 0 1
1 0 1 0 1 1

• The delay in the inverter may cause the output of gate 1 to change to 0 
The delay in the inverter may cause the output of gate 1 to change to 0
before the output of gate 2 changes to 1.
• In that case, the output goes to 0 for short interval of time. 

Y = x1 x2 + x2 ' x3 or Y = ( x1 + x2 ' )( x2 + x3 )
(sum of products) (product of sums)

• The first implementation may cause the output to go to 0 when it should 
remain at 1 (Static 1
remain at 1 (Static 1‐hazard),
hazard), while the second implementation may cause 
while the second implementation may cause
the output to go to  1 when it should remain at 0 (Static 0‐hazard) .

©  2010  Dr. Ashraf Armoush , An‐Najah National University  61
 Hazards in Combinational Circuits (cont.)

• The dynamic hazard causes the output to change three or four

times when it should change from 1 to 0 or from 0 to 1.
1

• The occurrence of the hazard can be detected by inspecting the

map of a particular circuit.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  62

Hazard Free Circuit
• The change in x2 from 1 to 0 moves the circuit
from minterm 111 to minterm 101.

• The hazard exists because the change of input

results in a different product term covering the
two minterms.
minterms

• Whenever the circuit must move from one

product term to another, there is a possibility
of a momentary interval when neither term is
equal to 1, giving rise to undesirable 0 output.

• The solution is to enclose the minterms with

another product term that overlaps both
groupings. ÎÎÎÎ
©  2010  Dr. Ashraf Armoush , An‐Najah National University  63
 Hazard Free Circuit (cont.)

™ The removal of hazards requires the addition of

redundant gates to the circuit.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  64

Hazards in Sequential Circuits
• Momentary erroneous signals are not generally troublesome in normal
combinational‐circuits associated with synchronous sequential circuit. Thus,
hazard are not of concern in these circuits.
• Conversely, if a momentary incorrect signal is fed back in an asynchronous
sequential circuit, it may cause the circuit to go to a wrong stable state.

o If the circuit is in total state yx1x2 = 111 and input x2 changes from 1 to 0, the
next total state should be 110. However, because of the hazard, output Y
may go 0 momentarily.
o If this false signal feeds back into gate 2, the output of gate 2 will remain at
0 and the circuit will switch to the incorrect total state 010.
¾ This problem can be eliminated by adding an extra gate.
©  2010  Dr. Ashraf Armoush , An‐Najah National University  65
 Hazards in Sequential Circuits
‐ Implementation with SR Latches
• Another way to avoid static hazards in asynchronous sequential circuits is
to implement the circuit with SR latches.
• A momentary 0 signal applied to the S or R inputs of a NOR latch will have no
effect on the state of the latch.
• Similarly, a momentary 1 signal applied to the S or R inputs of a NAND latch
will also have no effect on the state of the latch.
Ex:

• This implementation
Thi i l t ti may have
h a static
t ti 1‐hazard
1h d if both
b th inputs
i t off gate#3
t #3 go
to 1, changing the output from 1 to 0 momentarily.
• But if gate 3 is part of a NAND‐latch, the momentarily 1 signal will have no
effect
ff t because
b another
th input
i t will
ill come from
f Q’ that
th t will
ill be
b equall to
t 0 andd
thus maintain the output at 1
©  2010  Dr. Ashraf Armoush , An‐Najah National University  66

Ex:
• Consider a NAND SR‐latch with the following Boolean functions for S and R
S = AB + CD 
R A’C
R = A’C
• Since this is a NAND latch we must use the complement value for S and R
S = (AB + CD)’ =(AB)’(CD)’
R = (A’C)’

©  2010  Dr. Ashraf Armoush , An‐Najah National University  67
 Ex (cont.):
• The Boolean function for output  is 
Q = (Q’S)’ = [Q’ (AB)’(CD)’]’
• The output is generated with two levels of NAND gates:

• If output Q is equal to 1, then Q′ is equal to 0. If two of the three inputs

go momentarily to 1, the NAND gate associated with output Q will
remain at 1 because Q′′ is maintained at 0.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  68

Essential Hazards
• An Essential Hazard: is caused by unequal delays along two or 
more paths that originate from the same input. 

• Essential hazards cannot be corrected by adding redundant 
gates as in static hazards
gates as in static hazards.

• The problem can be corrected by adjusting the amount of 
p y j g
delay in the affected paths.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  69
 DESIGN EXAMPLE 
¾ The recommended procedural steps for the design of a complete
asynchronous sequential circuit are:
1 State the design specifications.
1. specifications
2. Derive a Primitive Flow Table.
3. Reduce the Flow Table by merging rows.
4. Makek a race‐free
f bi
binary state assignment.
i
5. Obtain the transition table and output map.
6. Obtain the logic diagram using SR latches.

1) Design Specification:
It is necessary to design a negative‐edge‐triggered T flip‐flop.
flip‐flop The
circuit has two inputs T (toggle) and C (clock) and one output Q.
The output state is complemented if T=1 and the clock changes
from 1 to 0 ((negative‐edge‐triggering).
g g gg g) Otherwise,, under all input
p
condition, the output remains unchanged.
©  2010  Dr. Ashraf Armoush , An‐Najah National University  70

Design example (cont)
2) Primitive flow table.

Inputs Output
State  T C Q Comments
a 1 1 0 I iti l t t i 0
Initial output is 0
b 1 0 1 After state a
c 1 1 1 Initial output is 1
d 1 0 0 After state
f c
e 0 0 0 After state d or f
f 0 1 0 After state e or a
g 0 0 1 After state b or h
h 0 1 1 After State g or c

©  2010  Dr. Ashraf Armoush , An‐Najah National University  71

Design example (cont)
3) Merging of the Flow Table

Th maximal
The i l compatibles
tibl pairs i are:
(a , f) (b , g , h)  (c , h)  (d , e , f)
©  2010  Dr. Ashraf Armoush , An‐Najah National University  72

Design example (cont)
In this particular example, the minimal collection of compatibles
is also the maximal compatibles set:
( f) (b
(a , f) (b , g , h)  (c , h)  (d , e , f)
h) ( h) (d f)

©  2010  Dr. Ashraf Armoush , An‐Najah National University  73

Design example (cont)
4) State Assignment and Transition Table
From the transition diagram, it is clear that there are no diagonal lines.
Therefore,, it is p
possible to find a suitable adjacent
j assignment
g without
the need of extra states.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  74

Design example (cont)
5) Logic Diagram
There are two state variables Y1 and Y2, and one output Q. The
previous output map shows that Q is equal to y2.

©  2010  Dr. Ashraf Armoush , An‐Najah National University  75

Design example (cont)

©  2010  Dr. Ashraf Armoush , An‐Najah National University  76