— EAIRCHILD — FSBB20CH60 Smart Power Module Features + UL Cortied No.£200204(SPI27-CA package) + Very low thermal resistance due to using DBC. + 600V-20A 3-pnase IGBT invertor bricge inhiding contol IOs for gate crving and protection + Divided negative de-nk terminals for inverter current sensing -pplicalons + Single-grounded nower supply de to bultin HVIC + Isolation rating of 2500 vIn Applications + ACAOIV= 253V three-phase inverter civ for small power fe motor aves + Home appliances application lke air condtioner and wash ing machine ‘April 2005 SPM" General Description Its an advanced smart power module (SPM) that Fata hes newly developed and designed to provide very compact land high parformanes ae motor dives manly targeting iow power invertr-drven application Ike ar condttonor and wash- ing machine. I combines optimized circuit protection and drive matched 0 lowloss IGBTS. System relbiity Is. further ‘enhanced by tne ifegrated under-votage lockout and short- Ceut protection. The high speed buttin HVIC provides opto- couplerless single-supply IGBT gate driving capabilty that fu thet reduce the overall se ofthe inverter system design. Each hase current of inverter can be monitored separately due to the divided negative de terminals, Figure 1. $2005 Fach Ser FSBB20CHEO Rev. C utr Corpraton Sache com aINPOW JaMod WeUS OSHOOZASSSIntegrated Power Functions + 600.204 GBT inverter or tree pase DIAG power eonversion Pease refer Fire 3) Integrated Drive, Protection and System Control Functions + For invertor high sido IGBTs: Gate drive ciel, High voltage isolated high-speed level shiing Control circuit under-votage (UY) protection Note) Available bootstrap circuit example is given in Figures 10 end 11, + For inverter ou-sde IGBTS: Gate drve circu, Short circuit protection (SC) (Contr supply cireut Under-votage (UY) protection + Fauitsinalin: Corresponding to @ UV faut (Lowside supply) + Input interface: 33/6V CMOSILSTTL compatible, Schmit tigger input Pin Configuration Top View 437 freon, fem [2123 on err Pica caer | es Figure 2. FSBB20CH50 Rev. C i Sahar om aINPOW JaMod WeUS OSHOOZASSSPin Descriptions Pin Number | Pin Name Pin Description 1 Vea; __ | Lowside Common Bias Votage forIC and IGBTs Drving 2 COM | Common Supply Ground 3 Tuy | Sana aput or Lowside U Phase 4 TN | Signal nput or Low-side V Phase 5 TN) | Sonal Input for Low-side W Phase 6 Veo | Fault Outout 7 Groa | Capacitor or Fault Outout Duraton Timo Selection @ Taq | Capacitor (Low-pess Fite for Shor-Curent Detection Input e Tig | Sonal Input for Highs U Phase 70 Vecuny | Hihrside Bias Vatage for U Phase IG 1 aw) | Highsdo Bias Votage Tor U Phase IGBT Driving 2 Vewu) | Hiahside Bias Votage Ground for U Phase IGBT Driving 8 TNsag__| Sonal Input for Hih-side V Phase 4 Vecun) [Fairs Bias Votage for Phase IC 5 Vax. | Fits Bios Vatage for Phase IGBT Onvng 6 Vax itSie Bias Votage Ground forv Phase ISBT Diving 7 Nw | Stona Input or Highside W Phase 78 Vecowny | Hah side Bias Votage for W Phase IC 70 Venu) | ah-side Bias Vatags for W/ Phase 1GBT Daving 20 Vayu | ihe Bios Voltage Ground for W Phase IGBT Diving a Nu | Negative DG-Link input for U Phase 2 Ny___| Negative D-Link input forv Phase 2 Ny. [Negative DG-Link Input Tor W Phase 24 U__[Ovtout or U Phase a V___[OuiputfocV Phase 26 W___ [Output for W Phase 2 P___[Pestve 00-Link input FSBB20CH50 Rev. C i Sahar om aINPOW JaMod WeUS OSHOOZASSSInternal Equivalent Circuit and Input/Output Pins (sh "tener ewe conpeast mee GST, Peewee dee cacIGET ard one crt Rha gue rv and pretest, 2 iver putea cages tourna npn ances ne epemans 2 Ivete gratin compen cf res evel reacted a ech GET Figure 3. FSBB20CH50 Rev. C i Sahar om aINPOW JaMod WeUS OSHOOZASSS25°C, Unless Otherwise Specified) Inverter Part ‘Symbol Parameter Conditions Rating | Units Veu__| Supply WoRege [Applied between P-Ny, Ny Ny 0 Vv Vensuge)_| Supply Votage (Surge) ‘Applied between P- Ny, Ny Ny 500 Vv ‘Ves __| Callstoremtar vonage 00 Vv Each IGBT Collector Curent Te=25C 2 A Each IGBT Collctor Curent (Peak) | Te = 25°C, Under fms Pulse Wath a A Callactor Dissipation °C per One Chip et w ‘Operating Junction Temperate cia) 2-18 | os Rasonsnpasuresousesingeen iso teeaesec eS Control Part ‘Symbol Parameter Conditions Rating | Units Vez | GoritelSupiy Vaiegs | Anpfed Betwaen Vosiun. Veena, Vez Veoa 0 v ‘con Ves [Hatvside GontalBies | Aopfed betwaen Vow Vau, Veen - Vann Ve 20 v vota92 Vea Yin [Inout Sana Voone oped batweon Num. Nyy Nuts INuy Nye.) 0317 fv IN) COM Ful Output Suppl Vologe | Aopted between Veg COM oaVer03] Vv Fault Qutpat Curent Sik Cunt at Vag Pin 3 ma Current Sensing input Votago | Appted between Cs -COM osVecr03] Vv Total System ‘Symbol Parameter Conditions Rating | Units Veupaon | SelfProtection Supply Vollage Limit | Voc = Vag = 185~ 105V 400 Vv (Short Circuit Protection Capability) (25°C, Non-repettve, less than 2us Tz___ | Module Case Operation Tomporatue | 20°0s T,= 125°C, See Figure 2 m= 10 |e Tere | Sorage Tomperaiute = 125 | c Viso | soltion Vote ie, Siusaidal, AC 4 minute, Connection | 2600 Vine Pins to ceramic substrate Thermal Resistance ‘Symbol Parameter Condition Min. [ Typ. [Max. | Units Raja _ | dunetion to ase Thema! [Inverter IGBT par (per V6 module) zi 163 | "ow Rance [Restore Inverter FYD pat (per1/8 modula) zi 2a5 | “cw oe 2. Forte measurement pit fae temperate plas eto Fee? FSBB20CH50 Rev. C i Sahar om aINPOW JaMod WeUS OSHOOZASSSElectrical Characteristics (7, = 25°C, Unless Otherwise Specified) Inverter Part Symbol Parameter Conditions Min. | Typ. | Max. | Units Vesa) | calestorEmter maT =e] - | - | 2a] v ‘Saturation Vologe Ve__ [WO Forward votage ema =we] — | - [2] v FS] ton | Stoning Times fea 1 ~ [oe [= [as "oon OV +, Inductive Loed __j ox {| =} as torr =| oe [| us Teiorr) = [esa [Ts We = [ow [= [as 1S] ton es 1 foe [os ‘jon OV «> 8, Indvebve Load —f 0% {| =| os lore Wote3) ~— [tor [as rf) ~ [os [ - | us te [oto [= [as Toes | CalectorEmitier Woe = Voes >| >) | aw Loakage Current we tr ee ropspten ete ei IC ta er eg ti GT tld gen ati conden tay 100%, 100% toe ‘ore ‘on bom 10%, SOL 0% Y%e Yer Oe OL (a) turn-on (o) turn-off Figure 4. Switching Time Defini FSBB20CH50 Rev. C i Sahar om aINPOW JaMod WeUS OSHOOZASSSElectrical Characteristics (7, = 25°C, Unless Otherwise Specified) Control Part Symbol Parameter Conditions Min. | Typ. | Max. | Units Taoer | OMescentVoo SupBIy _|Vog= 15 Voea) = CON - | ma Curent, IN ey = loccH Voc = 19 Vociuy Veowsy Yooiwry| ~ 100 wa Nua van) = OV_|- COM Toes | Guesent Ves Supp |Ves=15¥ Yaw) - Vann Venn Vann, |= m0 | WA Current Nua va. wy) = OV_| Veg) = Vein Vou | Faun Opa Vorage [Vag = 0, Veo Grout 4 Tet SV Para a Vv Vou sc = 1V, Veo Grout 4 Teht0 SY Pup i we fv Yeon [Shor Grout Tep Lovel [Voc = 15V Nate oas [os [oss | Vv Uveco | Suppl Grout Under | Detecon Level wor | 9 | 90 | Vv Ween _| Voltage Protection Reset Level a2 | 124 | 132 Vv Was Detection Level wor [na 2s| iv Wes Reset Level ws [a7 | 28 |v ‘bon | Fauttout Pus Wath | pap = Sank (Nate 5) 10 | 18 me Vion [ON Tivesno vatage | Appiod netweon INuay Na, INoway ‘Muy | 30 v Vinorr) [OFF Threshold Votage [Nowy Newt)“ COM ~ os |v owe 1 Stoica ponchos 5. Thtavtutde wa gg pina apace a Cn arg elon xn equi Recommended Operating Conditions Value Symbol) Parameter Conditions Units Min. | Typ. | Max. Ven | Supa Votooe ‘oped belwoon P- Ny, Nv Na — | 300 | 400 |v oo | Conte Supply Vatlage | Applied between Veouny, Vecnmy Voowmmn| 15 | 18 | 105 | Vv Vee COMt Vag [Hal-side Bias Volage | Appind between Vaqy -Vauy Vey -Vams| 30 | 1 | es |v Vay =Vsq0 vag, | Contra supply varaton = ppt] we DVasiDt Tent | Banking Te for Pravening |For Each Input Sal m=]. | ps Amst ‘Ea [PO input Signal BPC Tye OME APOE TEES [= We Vsen | Voltage for Current Sensing | Applied between Ny, Ny, Nyy - COM 7 4 Vv {Including surge voltage) FSBB20CH50 Rev. C i Sahar om aINPOW JaMod WeUS OSHOOZASSSMechanical Characteristics and Ratings Parameter Conditions tims Units Min. [ Typ. [ Max. Tsang Trae Tuning Seer -Nib[Reconmenceaoeanm | 051 | 062 | 072 | wan Doves Flaness Noto Feguos 0 [p20 | um wont ~ [wep fe Figure 5. Flatness Measurement Position FSBB20CH50 Rev. C i Sahar om aINPOW JaMod WeUS OSHOOZASSSTime Charts of SPMs Protective Fun vows LSP LL LS] Protection RESET _SET/—_=RESET, Circuit State —— Control * Supply Voltage # ” |) Vv “| Output Current | | Fault Output Signal PL at Control supply volage rises: After the voltage rises Ucop, the crcuis star to operate when nex! input apple. 2: Normal operation: GBT ON and carving current 83: Under votage detection (U 24: IGBT OFF in spite of control nput condition. 25 : Fault output operation stars 26 : Under votlage reset (UV eR) 47 : Normal operation: GBT ON and carving current Figure 6. Under-Voltage Protection (Low-side) wases [| | LI | I] PLA Protection RESET SET RESET, Circuit State Woe, Control ‘Supply Voltage Output Current High ove (na faut xu) « Fault Output Signal bt Control supply votage nses: After the votage reaches UVa, the cuts start to operate when next inputs applied. 2: Normal operation. GBT ON and carying current. 3: Under votage detection (Uvasq). 1b: IGBT OFF in spite of contro! nput condition, bul thre is no fault ouput signal. 5 : Under vottage reset (Usa) 1: Normal operation: IGET ON and carying current Figure 7. Under-Voltage Protection (High-side) ° i Sahar om FSBB20CH50 Rev. C aINPOW JaMod WeUS OSHOOZASSSg Lower arms [a cs control input = —! L Protection ° circuit state SET RESET, Internal IGBT Gate-Emitter Voltage _| ‘ L Output Current I ence Vo Sensing Voltage iden a of the shunt Li¢ pe \ resistance +— S cxcout ne Fault Output Signal 8 | consartoeey (withthe external shunt resistance and GR eannestion) fe Noxmal operation Hard IGBT ote GBT turns OFF. Input“L" = 1GBT IGBT OFF state IGT ON and carrying curent Short citeut current detection (SC trigger interrupt, Fault autput timer operation stats: The pulse with ofthe faut autput signals set by the extemal eapactior Cro, OFF state Inout"H" IGBT ON state, but during the active perio of fault output the IGBT doesnt tun ON, Figure 8. Short-Circuit Current Protection (Low-side Operation only) FSBB20CH50 Rev. C 10 i Sahar om aINPOW JaMod WeUS OSHOOZASSSsv-Line SPM Ne IN tN IN, CPU as IN Ng Ves [> com 1 Roping a ah ia town tad) nigh car epadng ne PHM cl care atin aan adh wig parce fe spleains Prrederegtcnd The fms apes star eyes 3 Sirus Tea wes ang one ae esa pao stein ea Fatctage dep aera 2. Thelage nats empath ands CMOS or LSTTL ots Figure 9. Recommended CPU I/O Interface Circuit, These Values depend on PWM Control Algorithm 16V-Line 4 — DreLeg Diagram of SPH Inverter “| > Output AM Noe | vou be eeormente atte tats ode Osha ot aris ener eters 2 Tegan) en ese ny, Tesora fey SE canbe men ip 08 mer rane et 2. The carr capt lced eee Ven-COM tei ve Fan ts cl th ns fhe SPM pla Figure 10. Recommended Bootstrap Operation Circuit and Parameters 1" i Sahar om FSBB20CH50 Rev. C aINPOW JaMod WeUS OSHOOZASSSTreat Signal or Shor Ciout Proteoton WePhase Curent Vases Curent UPnase Curent 4 1 To aed ratanten he weg ceeh wp rob a2 tr spose (es Ban? 300) 2 By wruect resengan aoieatn cose ype HVC nade te SPM et couning 2 CPU rans weet any opal er Yanome aon pas 3 Vegeta sqpecatecterpe: The agralinestedatepuleduptothe patie se the 5V potest apron 4h aoe Plane eer oF 4 Cog cus ne ge an bots capa Cae ecoreied 5 Va aut pe with rode deen) cnretg an esta pain) been Cf) and COMP, ExaNpe Cra * 33. te = Ls Ui) Betercero tenets ication nebo 6 Inu sia Hgh Acinic esoinst fe IC pul dom xhina sia ine GAD When elon RC caging cc et up suche IBalnpz son Spee wn kr-cbhiean resa veoge 1 Tepreetaras tte ete ton, wig sed ean shad bea shot a oecle inne stotereutgeeton cut pease det he Recs: tre cma ne ange 12 9 Ean caps sou be mounts as cee te he pri athe SPM a5 oss. EES USE SESE pPotnadn vs hacnb esse osens a se shat sepa Te ae ish eure 1 Reloyam anal aeaterny aplomb eumetscihoe pares infects fresh cn ec een CPU ey, 12. Casey 1 1 and mora cose toe tthe SP 2 poss Figure 11. Typical Application Circuit 2 i Sahar om FSBB20CH50 Rev. C aINPOW JaMod WeUS OSHOOZASSSDetailed Package Outline Drawings AcAcmcacac anmananan Lees Pitch + 4030 AG 1778 x B : 2.050 2 2531 i a4 Tt Lisao woos |, soto df) 10 ses Sel2.09 % i Sahar om FSBB20CH50 Rev. C aINPOW JaMod WeUS OSHOOZASSSDetailed Package Outline Drawings canine 11901030 geo 4eus (Clead Forming Dimension) (276) (278) sagotiow|. 204470 ta.ptsns0 |. 19.242050 eso | (553) (PKG Center fo Leod Oistonce ) a FSBB20CH50 Rev. C “ i Sahar om aINPOW JaMod WeUS OSHOOZASSSDetailed Package Outline Drawings canine OER TED) SCALE 2:1 A & ) LEAD TYPE 1 LEAD TYPE 2 LEAD TYPE 5 Sow 5+! Car SECTION) 6 FSBB20CH50 Rev. C i Sahar om aINPOW JaMod WeUS OSHOOZASSSTRADEMARKS “Te folowng are registred and unregistered trademarks Faicild Semiconductor owns os authorized to use and is not intended to be an exhaustive list ofall such trademarks ACEx™ FAST? IntelliMAX™® Pon sPM™ SSrearay= Fast IROBUNAR™ Boner Seam Someones tere Fowertoge™ Soperer™ Scares raeer MigRocouPLeR™ — Poversarer™ susesoT™ 3 ‘CROSSVOLT™ GlobalOptoisolator™ MicroFET™ PowerTrench® ‘SuperSOT™-5 DOME™ geTo™ ‘MicroPak™ QFeT® ‘SuperSOT™-3 een geo Merowme™ = Ge Speer E’cMos™ rom msx™ QT Opteelectronies™ ——TinyLogie® Enso tom nexPro™ Guat eros TReton ey InpledDeeornacr™ — Bexm Ropecortgue™® ——Trutreroon™ FAST Gut seres™ Soxro™ occomes™ ge ™ OPTOLOGIC? wSerDes™ UltraFET fron bow, cud he wo Gerona —Sueetswmronen®— UneT™ Programmabie Active Oroop™ PACMAN” ‘SMART START™ vex™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING QUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN, NEITHER DOES IT ‘CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR ‘SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION ‘As used herein 1-Lite support dewces or systems are devices or systems which, (@) are intended for surgical impiant ito the body, or (0) supper {or sustain fe, oF () whose failure to perform wien properiy used in accordance with instructions for use provided inthe labeling, ‘can be reasonably expectod fo fesull insignificant injury tothe 2 Antal components any componant of fe support device for system whose faiuro to perform can be reasonably expectod to cause the far of the He sunpart device or system, of to alec is safety oreflectiveness, PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet identification Product Status Detnition ‘Advance Information Formative or In ‘This datasheet contains the design specications for Design product development. Speciicatens may change in ‘any manner without notice Preliminary First Production ‘This datasheet contains preliminary data, and Ssupplomentary data wi be pubished ata ator dato, Farrchig Semiconductor reserves the ngnt to make Changes a any time without notice in order to improve design, No Identification Needed Full Production “This datasheet contains nel specifeations, Fairnid ‘Semiconductor reserves the right to make changes at any time without note in order to improve desig. Obsointe Not n Production ‘This datashest contains specications on product that has boon discontinued by Fairchild semiconductor. ‘The datasheet is printed for reference information only. FSB820CHED Rev. C 6 i Sahar om aINPOW JaMod WeUS OSHOOZASSS