PCS-978S - X - Technical Manual - EN - Overseas General - X - R1.00

Copyright © 2019 NR. All rights reserved.
NR, the NR logo are either registered trademarks or trademarks of NR Electric Co., Ltd. No NR
trademarks may be used without written permission. NR products appearing in this document may
be covered by P.R. China and foreign patents. NR Electric Co., Ltd. reserves all rights and
benefits afforded under P.R. China and international copyright and patent laws in its products,
including but not limited to software, firmware and documentation. NR Engineering Co., Ltd. is
licensed to use this document as well as all intellectual property rights owned or held by NR
Electric Co., Ltd, including but not limited to copyright, rights in inventions, patents, know-how,
trade secrets, trademarks and trade names, service marks, design rights, database rights and
rights in data, utility models, domain names and all similar rights.
The information in this document is provided for informational use only and does not constitute a
legal contract between NR and any person or entity unless otherwise specified. Information in this
document is subject to change without prior notice.
To the extent required the products described herein meet applicable IEC and IEEE standards,
but no such assurance is given with respect to local codes and ordinances because they vary
greatly.
Although every reasonable effort is made to present current and accurate information, this
document does not purport to cover all details or variations in equipment nor provide for every
possible contingency to be met in connection with installation, operation, or maintenance. Should
further information be desired or should particular problems arise which are not covered
sufficiently for your purposes, please do not hesitate to contact us.
Preface
Preface
About This Manual

The technical manual describes the protection, automation, control, and supervision functions of
PCS S series device for line differential protection, and contains operation principle descriptions,
and lists function blocks, logic diagrams, input and output signals, setting parameters and
technical data, sorted per function, as well as the hardware of the device. The manual can be
used as a technical reference during the engineering phase and during normal service. In addition,
the manual also includes a glossary that lists and defines technical terms used throughout the
manual.
Safety Information
This manual is not a complete index of all safety measures required for operation of the
equipment (module or device). However, it comprises important information that must be followed
for personal safety, as well as to avoid material damage. Information is highlighted and illustrated
as follows according to the degree of danger:
Indicates an imminently hazardous situation that, if not avoided, will
result in death or serious injury.
Indicates a potentially hazardous situation that, if not avoided, could
result in death or serious injury.
Indicates a potentially hazardous situation that, if not avoided, may result
in minor or moderate injury or equipment damage.
Indicates that property damage can result if the measures specified are
not taken.
Important information about the device, product handling or a certain

section of the documentation which must be given particular attention.
Instructions and Warnings

The following hazard statements apply to this device.
Disconnect or de-energize all external connections BEFORE opening this
PCS-978S Transformer Relay I

Date: January 31, 2019
Preface
device. Contact with hazardous voltages and currents inside this device
can cause electrical shock resulting in injury or death.
Contact with instrument terminals can cause electrical shock that can
result in injury or death.
Use of this equipment in a manner other than specified in this manual can
impair operator safety safeguards provided by this equipment.
Have only qualified personnel service this equipment. If you are not
qualified to service this equipment, you can injure yourself or others, or
cause equipment damage.
This device is shipped with default passwords. Default passwords should

be changed to private passwords at installation. Failure to change each
default password to a private password may allow unauthorized access.
NR shall not be responsible for any damage resulting from unauthorized
access.
DO NOT look into the fiber (laser) ports/connectors.
DO NOT look into the end of an optical cable connected to an optical

output.
DO NOT perform any procedures or adjustments that this instruction

manual does not describe.
During installation, maintenance, or testing of the optical ports, ONLY use
II PCS-978S Transformer Relay

Preface
the test equipment qualified for Class 1 laser products!
Incorporated components, such as LEDs, transceivers, and laser emitters,

are NOT user serviceable. Return units to NR for repair or replacement.
Equipment components are SENSITIVE to electrostatic discharge (ESD).

Undetectable permanent damage can result if you do not use proper ESD
procedures. Ground yourself, your work surface, and this equipment
BEFORE removing any cover from this equipment. If your facility is not
equipped to work with these components, contact NR about returning this
device and related NR equipment for service.
Insufficiently rated insulation can deteriorate under abnormal operating

conditions and cause equipment damage. For external circuits, use wiring
of SUFFICIENTLY RATED insulation that will not break down under
abnormal operating conditions.
SEVERE power and ground problems can occur on the communications

ports of this equipment as a result of using non-standard cables. Please
use the wiring method recommended in the manual for communication
terminals.
DO NOT connect power to the relay until you have completed these
procedures and receive instruction to apply power. Equipment damage
can result otherwise.
Use of controls or adjustments, or performance of procedures other than

those specified herein, may RESULT IN hazardous radiation exposure.
The firmware may be upgraded to add new features or enhance/modify
PCS-978S Transformer Relay III

Preface
existing features, please MAKE SURE that the version of this manual is
compatible with the product in your hand.
Document Conventions
 The abbreviations and acronyms in this manual are explained in “Appendix A Glossary”. The
Glossary also contains definitions of important terms.
 Menu path is connected with the arrow "→" and bold.
For example: the access path of protection settings is: MainMenu→Settings→Protection

Settings
 Settings not in the table should be placed in brackets.
For example: the system setting [Opt_SysFreq]
 Cross-references are presented in italics.
For example: refer to Figure 1.1-1, refer to Table 1.1-1, reference to Section 1.1
 Binary input signals, binary output signals, analogs, LED lights, buttons, and other fixed
meanings, should be written in double quotes and bold.
For example: press the button "ENT".
Symbols
 AND Gate
& & &
 OR Gate
>=1 >=1 >=1
 Comparator
 Binary signal Input
BI xxx
IV PCS-978S Transformer Relay

Preface
 Signal input
SIG xxx
 Setting input
SET xxx
 Enable input
EN xxx
 Timer
Optional definite-time or inverse-time characteristic
Timer
t
t
 Timer
Fixed delay pickup (10ms), fixed delay dropout (2ms)
10ms 2ms
 Timer
Settable delay pickup, fixed delay dropout
[Tset1] 0ms
 Timer
Fixed delay pickup, settable delay dropout
0ms [Tset2]
 Timer
Settable delay pickup, settable delay dropout
[Tset1] [Tset2]
 Generator
PCS-978S Transformer Relay V

Preface
 Transformer
 Reactor
 Motor
 Capacitor
 Busbar
 Circuit breaker
52
 Current transformer
3CT
*
 Voltage transformer
3VT
 Disconnector
VI PCS-978S Transformer Relay

Preface
 Earth
Three-phase Corresponding Relationship

Basic
A, B, C L1, L2, L3 R, Y, B
AN, BN, CN L1N, L2N, L3N RN,YN, BN
ABC L123 RYB
U (voltage) V U
Example
Ia, Ib, Ic, I0 IL1, IL2, IL3, IN IR, IY, IB, IN
Ua, Ub, Uc VL1, VL2, VL3 UR, UY, UB
Uab, Ubc, Uca VL12, VL23, VL31 URY, UYB, UBR
U0, U1, U2 VN, V1, V2 UN, U1, U2
Warranty
This product is covered by the standard NR 10-year warranty. For warranty details, please consult
the manufacturer or agent for warranty information.
Document Structure
This manual is a comprehensive work covering the theories of protection, control, supervision,
measurement, etc. and the structure & technical data of relevant hardware. Read the sections that
pertain to your application to gain valuable information about using the PCS-978S. To concentrate
on the target sections of this manual as your job needs and responsibilities dictate. An overview of
each manual section and section topics follows.
1 Introduction
Introduces PCS-978S features, summarizes functions and applications of the device.
2 Technical Data
Lists device specifications, type tests, and ratings.
3 Protection Functions
Describes the function of various protection elements, gives detailed specifics on protection
scheme logic, provides the relevant logic diagrams.
PCS-978S Transformer Relay VII

Preface
4 Control Functions
Describes the logic for the control of disconnectors and circuit breakers.
5 Measurement
Provides information on viewing fundamental and rms metering quantities for voltages and
currents, as well as power and energy metering data.
6 Supervision
Describes self-supervision technique to help diagnose potential difficulties should these occur and
includes the list of status notification messages. Provides a troubleshooting chart for common
device operation problems.
7 System Functions
Describes how to perform fundamental operations such as clock synchronization, communicating
with the device, switching active setting group, checking relay status, reading event reports and
SER (Sequential Events Recorder) records.
8 Hardware
Describes the hardware of the PCS series device family and provides general information on the
product structure and the modules technical data.
9 Settings
Provides a list of all settings and their ranges, unit, steps, defaults. The organization of the
settings is similar to the settings organization in the device and in the PCS-Studio software.
Appendix A Glossary
Describes the abbreviations adopted in this manual.
Document Revision History

PN: ZL_PCS-978S_X_Technical Manual_EN_Overseas General_X
Current version: R1.00
Corresponding Version
Date Description of change
Document Software
R1.00 B1.00 2019-01-31  Form the original manual.
VIII PCS-978S Transformer Relay

1 Introduction
1 Introduction
1
Table of Contents
1.1 Application ....................................................................................................... 1-1

1.2 Functions ......................................................................................................... 1-3
1.3 Features ............................................................................................................ 1-7
List of Figures
Figure 1.1-1 2-windings transformer ....................................................................................... 1-1
Figure 1.1-2 3-windings transformer ....................................................................................... 1-1
Figure 1.1-3 Auto-transformer with two sides ........................................................................ 1-2
Figure 1.1-4 Auto-transformer with three sides ..................................................................... 1-2
Figure 1.1-5 Typical application of a 3-windings transformer .............................................. 1-3
PCS-978S Transformer Relay 1-a

1 Introduction
1-b PCS-978S Transformer Relay

1 Introduction
1.1 Application
PCS-978S can be applied for a two-winding transformer, three-winding transformer or
auto-transformer in any voltage level. PCS-978S provides full transformer protections which are
1
configurable by user. Ancillary functions of fault diagnostic, disturbance records, event records
and communication function are integrated in the device.
PCS-978S is adaptive to the following 2/3-windings transformers or autotransformer.
Figure 1.1-1 2-windings transformer
Figure 1.1-2 3-windings transformer
PCS-978S Transformer Relay 1-1

1 Introduction
Figure 1.1-3 Auto-transformer with two sides
Figure 1.1-4 Auto-transformer with three sides
The function diagrams for protecting a 3-windings transformer is shown below.
1-2 PCS-978S Transformer Relay

1 Introduction
HVS
3 VT
52
*
1
3 CT
51P 64
87T 49 87W 50BF 67G 67P
Alm REF
MVS * 50/
51P
* 1 CT * *
52 50/
67Q
51G
3 CT 1 CT
1 CT *
50/
51Q
1 CT
3 VT
59P 59G 27P 24 81O 81U
3 CT
*
52
3 VT
LVS
Figure 1.1-5 Typical application of a 3-windings transformer
1.2 Functions
1. Protection Functions
ANSI Protection Functions Remark

 Biased differential protection with three slopes
 Biased DPFC differential protection
 Unrestrained instantaneous differential protection
 Optional inrush current distinguished principles:
harmonic criterion or waveform distortion
 Optional harmonic blocking modes: self-adaptive
87T Transformer differential protection
1Pblk1P mode, 2PBlk3P mode, 1Pblk3P mode
 Overexcitation detection: fifth harmonic or third
harmonic criterion
 Optional transfer methods: △→Y or Y→△
 Independent CT saturation criterion
 Differential CT circuit failure supervision

1 Introduction
 Optional direction element

 CT transient detection
64REF Restricted earth-fault protection

1 CT saturation detection based on 2nd and 3rd
harmonics
 CT transient detection
87W Winding differential protection  CT saturation detection based on 2nd and 3rd
harmonics
 Two stages definite-time overexcitation protection
 Stage 1 of definite-time overexcitation protection for
trip purpose
24 Overexcitation protection  Stage 2 of definite-time overexcitation protection for
alarm purpose
 One stage inverse-time overexcitation protection for
both alarm purpose and trip purpose
 6 stages with independent logic by default
 Voltage control element for each stage
 Optional direction element for each stage
67P
Phase overcurrent protection  Optional definite-time characteristic and inverse-time
50/51P
characteristic for each stage
 Trip purpose or alarm purpose for each stage
 Harmonic control element for each stage
 4 stages with independent logic by default
 Optional direction element for each stage
 Optional measured zero-sequence current or
calculated zero-sequence current
67G
Earth fault protection  Optional definite-time characteristic and inverse-time
50/51G
 Selectable trip purpose or alarm purpose for each
stage
 Harmonic control element for each stage
 Up to 2 stages with independent logic
67Q Negative-sequence overcurrent  Optional direction element for each stage
50/51Q protection  Optional definite-time characteristic and inverse-time
 Two stages thermal overload protection, and one
49 Thermal overload protection stage for alarm purpose and the other stage for trip
purpose
 Up to 6 circuit breakers are supported
 Phase-segregated re-trip and three-phases re-trip
 Optional current criterion (phase overcurrent element,
50BF Breaker failure protection zero-sequence overcurrent element,
negative-sequence overcurrent element)
 Optional circuit breaker position check
 Two time delays

1 Introduction

 Optional definite-time characteristic and inverse-time
59P Overvoltage protection 

Optional phase voltage or phase-to-phase voltage
1
 Optional “1-out-of-3” logic or “3-out-of-3” logic
stage
 Optional definite-time characteristic and inverse-time
 Optional phase voltage or phase-to-phase voltage
27P Undervoltage protection
 Optional “1-out-of-3” logic or “3-out-of-3” logic
 Blocked by instantaneous VT circuit failure
stage
 Optional measured zero-sequence voltage or
calculated zero-sequence voltage
59G Residual overvoltage protection  Optional definite-time characteristic and inverse-time
stage
81O Overfrequency protection
 Voltage control element
81U Underfrequency protection
 Voltage control element
2. Control Functions
 Switchgear control
 Double point status synthesis
 Remote/Local control mode switch
 Interlocking logic for control
 Direct control
 Closing synchronism check with voltage switching
 Trip statistics
 Tap changer indicator and control
3. Measurement and Metering Functions
 U, I, P, Q, Cos, f
 Positive, negative and zero sequences

1 Introduction
 Max.15th harmonics
 DC analog inputs for transducers (0~±20mA or 0~±10Vdc optional)

1 4. Supervision Functions
 CT circuit failure supervision (CTS)
 VT circuit failure supervision (VTS)
 Self diagnostic
 Powerful faults recording (max. buffer for 10,000 sampled points at 4.8 or 9.6 kHz)
 Event Recorder including 1024 disturbance records, 1024 binary events, 1024
supervision events, 256 control logs and 1024 device logs.
 Disturbance recorder including 64 disturbance records with waveforms (The file format of
disturbance recorder is compatible with international COMTRADE file.)
 Single line diagram representation in display
5. Communication Functions
 Support of various protocols
Modbus, DNP3.0, IEC 60870-5-103, IEC 61850 ed1 & ed2, IEC 61850-8-1 (MMS
GOOSE), IEC 62439 Parallel Redundancy Protocol, IEC 62439 HSR Ring Redundancy
Protocol
 Up to four 10Base-T/100Base-TX copper Ethernet ports
 Up to two 100Base-FX optical Ethernet ports
 Two RS-485 serial ports for communication or printer
 One RS-485/TTL serial port for clock synchronization
 RJ45 debugging ports for both front and rear sides
6. User Interfaces
 Friendly HMI interface with LCD, easy-to-use keypad aids simple navigation and
set-point adjustment
 Push buttons for open/close, switch for selection between local and remote control, and
user's login and logout authority management
 4 Programmable operator pushbuttons with user-configurable labels
 Up to 18 programmable target LEDs with user-configurable labels
 1 RS-232 or RS-485 rear ports for printer
 Language switchover—English+ selected language
 Configuration tool—PCS-Studio

1 Introduction
7. Additional Functions
 User programmable logic
 Switching system phase sequences function (ABC or ACB)

1
 Clock synchronization
 IRIG-B: IRIG-B via RS-485 differential level, TTL level or optical fibre interface
 PPS: Pulse per second (PPS) via RS-485 differential level or binary input
 PPM: Pulse per minute (PPM) via RS-485 differential level or binary input
 IEEE1588: Clock message based on IEEE1588 via optical fibre interface
 SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network
 SNTP (BC): Broadcast SNTP mode via Ethernet network
 Message (IEC103/Modbus/DNP3.0): Clock messages through IEC103 protocol,

Modbus protocol and DNP3.0 protocol
 Cyber security
 NERC CIP
 IEC 62351
 IEC 62443
 IEEE 1686
1.3 Features
 High degree of functional integration and flexible configuration modes, transformer main
protection and back-up protection can be integrated in one device, or be separated in two
devices.
 Up to 36 analog inputs can be provided and configured flexibly.
 The tripping output contacts can be configured by tripping matrix, which is flexible, convenient
and suitable to any mode of tripping.
 The relay supports at most 6 branches differential protection. The transformer angle can be
adjusted flexibly, and any transformer angle compensation mode is supported and any side
can be chosen as the reference side of differential protection.
 Reliable differential CT circuit failure supervision. The relay can detect multi-phase CT
wire-break, multi-side CT wire-break, short-circuit, and other complex situation. The
corresponding logic setting can be used to select blocking differential protection or not, in case
of CT circuit failure.
 Multiple inrush current blocking options are provided. Self-adaptive inrush current blocking
criterion can ensure the relay fast operation for transformer energized on to a slight fault,

1 Introduction
meanwhile it will avoid the unwanted operation in the case of the energization inrush current
caused by energizing transformer with no load, the recovery inrush current caused by cutting
1 off the transformer external fault, and the sympathetic inrush current.
 Biased DPFC differential protection is regardless of load current and is sensitive to small
internal fault current within the transformer. Its anti CT saturation performance is also strong.

2 Technical Data
2 Technical Data
Table of Contents
2.1 Electrical Specifications ................................................................................. 2-1 2

2.1.1 AC Current Input ................................................................................................................... 2-1
2.1.2 AC Voltage Input ................................................................................................................... 2-1
2.1.3 Power Supply ....................................................................................................................... 2-2
2.1.4 Transducer Input .................................................................................................................. 2-2
2.1.5 Binary Input .......................................................................................................................... 2-2
2.1.6 Binary Output........................................................................................................................ 2-3
2.2 Mechanical Specifications .............................................................................. 2-4

2.3 Ambient Temperature and Humidity Range .................................................. 2-5
2.4 Communication Port ....................................................................................... 2-5
2.4.1 EIA-485 Port ......................................................................................................................... 2-5
2.4.2 Ethernet Port ........................................................................................................................ 2-6
2.4.3 Optical Fibre Port ................................................................................................................. 2-6
2.4.4 Print Port ............................................................................................................................... 2-6
2.4.5 Clock Synchronization Port .................................................................................................. 2-6
2.5 Type Tests ........................................................................................................ 2-7

2.5.1 Environmental Tests ............................................................................................................. 2-7
2.5.2 Mechanical Tests .................................................................................................................. 2-7
2.5.3 Electrical Tests ...................................................................................................................... 2-7
2.5.4 Electromagnetic Compatibility .............................................................................................. 2-7
2.6 Certifications .................................................................................................... 2-9

2.7 Liquid Crystal Display (LCD) .......................................................................... 2-9
2.8 Terminals .......................................................................................................... 2-9
2.8.1 Ring Ferrule .......................................................................................................................... 2-9
2.8.2 Pin Ferrule .......................................................................................................................... 2-10

2 Technical Data
2.9 Measurement Scope and Accuracy ............................................................. 2-10

2.10 Management Function................................................................................. 2-10
2.10.1 Control Performance ........................................................................................................ 2-10
2.10.2 Clock Performance ........................................................................................................... 2-11
2 2.10.3 Fault and Disturbance Recording..................................................................................... 2-11
2.10.4 Binary Input Signal ........................................................................................................... 2-11
2.11 Protective Functions ....................................................................................2-11

2.11.1 Transformer Current Differential Protection (87T) ............................................................ 2-11
2.11.2 Restricted Earth Fault Protection (64REF) ....................................................................... 2-12
2.11.3 Winding Differential Protection (87W) .............................................................................. 2-13
2.11.4 Overexcitation Protection (24) .......................................................................................... 2-13
2.11.5 Phase Overcurrent Protection (50/51P, 67P) ................................................................... 2-13
2.11.6 Earth Fault Overcurrent Protection (50/51G, 67G) .......................................................... 2-14
2.11.7 Negative-sequence Overcurrent Protection (50/51Q, 67Q) ............................................. 2-15
2.11.8 Thermal Overload Protection (49) .................................................................................... 2-15
2.11.9 Breaker Failure Protection (50BF) .................................................................................... 2-15
2.11.10 Overvoltage Protection (59P) ......................................................................................... 2-16
2.11.11 Residual Overvoltage Protection (59G) .......................................................................... 2-16
2.11.12 Undervoltage Protection (27P) ....................................................................................... 2-16
2.11.13 Overfrequency Protection (81O) .................................................................................... 2-16
2.11.14 Underfrequency Protection (81U)................................................................................... 2-17

2 Technical Data
2.1 Electrical Specifications
“System phase sequence”, which can be set by PCS-Studio, this setting

informs the device of the actual system phase sequence, either ABC or
ACB. CT and VT inputs on the device, labeled as A, B and C, must be 2
connected to system phase A, B and C for correct operation.
2.1.1 AC Current Input
Phase rotation ABC or ACB
Nominal frequency (fn) 50Hz, 60Hz
Rated current (In) 1A/5A (settable)
Linear to 0.05In~40In
Thermal withstand
-continuously 4In
-for 10s 30In
-for 1s 100In
-for half a cycle 250In
Burden <0.05VA/phase @1A, <0.25VA/phase @5A
2.1.2 AC Voltage Input
Phase rotation ABC or ACB
Nominal frequency (fn) 50Hz, 60Hz
Rated voltage (Un) 100V~130V
Linear to 1V~300V
Thermal withstand Phase-to-ground Phase-to-phase
-continuously 300V 519V
-10s 600V 1038V
-1s 660V 1141V
Burden at rated <0.10VA/phase @100V

2 Technical Data
2.1.3 Power Supply
Standard IEC 61000-4-29:2000
100Vac/110Vac/115Vac/120Vac
Rated voltage 110Vdc/125Vdc/220Vdc/250Vdc 127Vac/220Vac/230Vac/240Vac
2 250Vac
Permissible voltage range 88~300Vdc 88~275Vac
Permissible AC ripple voltage ≤15% of the nominal auxiliary voltage
Burden
Quiescent condition <30W
Operating condition <35W
2.1.4 Transducer Input
Standard IEC 60255-1: 2009
Input range 0~±20mA 0~±10V
Input resistance 230Ω >1MΩ
Accuracy 0.1% 0.1%
RTD PT10, PT100, PT1000, CU50, CU100
Types 3-wire, 2-wire
PT10, PT100, PT1000: -200°C ~ 850°C

Range
CU50, CU100: -50°C ~ 150°C
Accuracy 0.5°C (3-wire, environment temperature: 25°C)
2.1.5 Binary Input
Settable pickup voltage and dropout voltage
Rated voltage 110Vdc 125Vdc 220Vdc 250Vdc
Rated current drain 0.73mA 0.83mA 1.47mA 1.67mA
On value (default set) 69.3~132Vdc 78.75~160Vdc 138.6~264Vdc 157.5~300Vdc
Off value (default set) <55Vdc <62.5Vdc <110Vdc <125Vdc
Maximum permissible voltage 300Vdc

2 Technical Data
Withstand voltage 2000Vac, 2800Vdc (continuously)
Rated voltage 110Vac 220Vac
Rated current drain 0.73mA 1.47mA

2
On value (default set) 69.3~132Vac 138.6~264Vac
Off value (default set) <55Vac <110Vac
Maximum permissible voltage 300Vac
Rated voltage 24Vdc 48Vdc
Rated current drain 0.16mA 0.32mA
On value (default set) 15.12~28.8Vdc 30.24~57.6Vdc
Off value (default set) <12Vdc <24Vdc
Maximum permissible voltage 350Vdc
2.1.6 Binary Output
Tripping/signaling contact
Output mode Potential free contact
Max. system voltage 250Vac, 300Vdc
Continuous carry 10A
Pickup time (Typical value) <5ms
Dropout time (Resistive load) <6ms
0.5A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=40ms) 0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc

2 Technical Data
0.5A@48Vdc
0.35A@110Vdc
Cyclic Capacity (2.5 cycle/second,
0.30A@125Vdc
L/R=40ms)
0.20A@220Vdc
2 0.15A@250Vdc
30A@3s
Short duration current
50A@1s
Durability (Loaded contact) 10000 operations
Heavy-capacity tripping contact
Output mode Potential free contact
MOV Protection (maximum voltage ) 350Vdc, 275Vac
Continuous carry 10A
Pickup time (Typical value) <1ms
Dropout time (Resistive load) <10ms
10A@48V
10A@110V
Breaking capacity (L/R=40ms)
10A@125V
10A@250V
10A@48V L/R=40ms
Cyclic Capacity (4 cycles in 1 second,
10A@110V L/R=40ms
followed by 2 minutes idle for thermal
10A@125V L/R=40ms
dissipation)
10A@250V L/R=20ms
30A@3s
Short duration current
50A@1s
Durability (Loaded contact) 10000 operations
2.2 Mechanical Specifications
Chassis color Silver grey
Weight per device Approx. 8.66kg (6U, 1/2)

2 Technical Data
Approx. 15.27kg (6U, 1/1)
Chassis material Aluminum alloy
Location of terminal Rear panel of the device
Device structure Plug-in modular type @ rear side, integrated front plate
Protection Class 2
Standard IEC 60529-2013
Front side IP52
Other sides IP50
Rear side, connection terminals IP20
2.3 Ambient Temperature and Humidity Range
Standard IEC 60255-1:2009
-40°C to +80°C (Readability of display may be impaired below -20°C

Operating temperature
and above 70℃ )
Transport and storage temperature

-40°C to +80°C
range
Permissible humidity 5%-95%, without condensation
Pollution degree Ⅱ
Altitude <3000m
2.4 Communication Port

2.4.1 EIA-485 Port
Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Protocol IEC 60870-5-103:1997 or Modbus
Max. capacity 32
Max. transmission distance 500m
Safety level Isolation to ELV level
Twisted pair Screened twisted pair cable

2 Technical Data
2.4.2 Ethernet Port
Connector type RJ-45
Transmission rate 100Mbits/s
Transmission standard 100Base-TX
2 Max. transmission distance 100m
Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850
2.4.3 Optical Fibre Port
For Station Level
Characteristic Glass optical fiber
Connector type LC
Fibre type Multi-mode
Max. transmission distance 2km
Wave length 1310nm
Transmission power 50μm: -24dBm 62.5μm: -20dBm
Minimum receiving power Min -31dBm
Margin 50μm: -7dBm 62.5μm: -9dBm
2.4.4 Print Port
Type RS-232
Baud Rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Printer type EPSON® 300K printer
2.4.5 Clock Synchronization Port
Type Serial port
Input Demodulated IRIG-B or PPS
Nominal Voltage 5Vdc+10%
Maximum Voltage 8Vdc

2 Technical Data
Input Impedance 2.5kΩ
Isolation 500Vdc
2.5 Type Tests

2.5.1 Environmental Tests
2
Dry cold test IEC60068-2-1:2007
Dry heat test IEC60068-2-2:2007
Damp heat test, cyclic IEC60068-2-30:2005
2.5.2 Mechanical Tests
Vibration IEC 60255-21-1:1988 Class Ⅰ
Shock and bump IEC 60255-21-2:1988 Class Ⅰ
2.5.3 Electrical Tests
Standard IEC 60255-27:2013
Dielectric tests Test voltage 2kV, 50Hz, 1min
Impulse voltage tests Test voltage 5kV
Overvoltage category Ⅲ
Insulation resistance measurements Isolation resistance >100MΩ@500VDC
2.5.4 Electromagnetic Compatibility
IEC 60255-26:2013
1MHz burst disturbance test Common mode: class Ⅲ 2.5kV
Differential mode: class Ⅲ 1.0kV
IEC 61000-4-2-2008 class Ⅳ
Electrostatic discharge test For contact discharge: 8kV
For air discharge: 15kV
IEC 60255-26:2013 class Ⅲ
Frequency sweep
Radio frequency interference tests
Radiated amplitude-modulated
10V/m (rms), f=80~1000MHz, 14000~2700MHz

2 Technical Data
Spot frequency
Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz
IEC 60255-26:2013
2 Fast transient disturbance tests Power supply, I/O, Earth: class Ⅳ, 4kV, 5kHz, 5/50ns
Communication terminals: class Ⅳ, 2kV, 5kHz, 5/50ns
IEC 60255-26:2013
Power supply, AC input, I/O port: class Ⅳ, 1.2/50us

Surge immunity test
Common mode: 4kV
Differential mode: 2kV
IEC 60255-26:2013
Power supply, AC, I/O, Comm. Terminal: Class Ⅲ , 10Vrms, 150

Conducted RF Electromagnetic
kHz~80MHz
Disturbance
Spot frequency
10V/m (rms), f=27MHz/68MHz
Power Frequency Magnetic Field IEC 61000-4-8: 2009
Immunity class Ⅴ, 100A/m for 1min, 1000A/m for 3s
IEC 61000-4-9:2016
Pulse Magnetic Field Immunity
class Ⅴ, 6.4/16μs, 1000A/m for 3s
Damped oscillatory magnetic field IEC 61000-4-10:2016
immunity class Ⅴ, 100kHz & 1MHz–100A/m
IEC 60255-26:2013
Conducted emission 0.15MHz~0.50MHz: 79dB (μV) quasi peak, 66dB (μV) average
0.50MHz~30MHz: 73dB (μV) quasi peak, 60dB (μV) average
IEC 60255-26:2013
30MHz~230MHz: 40dB (μV/m) quasi peak @10m,
Radiated emission 50dB (μV/m) quasi peak @3m

Below 1GHz
230MHz~1000MHz: 47dB (μV/m) quasi peak @10m,
57dB (μV/m) quasi peak @3m

2 Technical Data
1GHz~3GHz: 56dB (μV/m) average, 76dB (μV/m)
peak @3m
Above 1GHz
3GHz~6GHz: 60dB (μV/m) average, 80dB (μV/m)
peak @3m
IEC 60255-26:2013
2
Up to 200ms for dips to 40% of rated voltage without
Voltage dips
reset
Auxiliary power supply performance
50ms for interruption without rebooting without
Voltage short energy storage board (Typical configuration)
interruptions 500ms for interruption without rebooting with energy
storage board (Typical configuration)
2.6 Certifications
 ISO9001:2008
 ISO14001:2004
 OHSAS18001:2007
 ISO10012:2003
 CMMI L5
 EMC: 2014/30/EU, EN60255-26:2013
 Products safety (LVD): 2014/35/EU, EN60255-27:2014
2.7 Liquid Crystal Display (LCD)
Type Resolution
Large size 320x240 pixels
2.8 Terminals
2.8.1 Ring Ferrule
Connection Type Wire Size Screw Type Torque
2
AC current Screw terminals, 1.5~4mm lead M4 1.6~1.8 N·m

2 Technical Data
2
AC voltage Screw terminals, 0.8~4mm lead M4 1.6~1.8 N·m
Power supply Screw terminals, 0.8~4mm2 lead M4 0.8~1.4 N·m
2
Contact I/O Screw terminals, 0.8~4mm lead M4 0.8~1.4 N·m
Grounding (Earthing) Connection BVR type, 0.8~4mm2 lead M3 0.6~0.8 N·m
2 2.8.2 Pin Ferrule
Connection Type Wire Size Screw Type Torque
Power supply Screw terminals, 0.3~3.3mm2 lead M2.5 0.4~0.6 N·m
Contact I/O Screw terminals, 0.3~3.3mm2 lead M2.5 0.4~0.6 N·m
2.9 Measurement Scope and Accuracy
Item Range Accuracy
Phase range 0°~ 360° ≤±1°
Frequency fn±3 Hz ≤ 0.01Hz
Currents from protection measurement current transformers
≤ 1.0% of rating (0.05~1.00In)

Current 0.05~4.00In
≤ 0.5% of applied quantities (1.00~4.00In)
≤ 1.0% of rating (0.05~1.00Un)

Voltage 0.05~1.50Un
≤ 0.5% of applied quantities (1.00~1.50Un)
0.05~1.50Un ≤ 2.0% of rating (0.05~1.00In, 0.05~1.00Un)

Active power (W)
0.05~4.00In ≤ 1.0% of applied quantities (1.00~4.00In, 1.00~1.50Un)
0.05~1.50Un ≤ 2.0% of rating (0.05~1.00In, 0.05~1.00Un)

Reactive power (VAr)
0.05~1.50Un ≤ 2.0% of rating (0.05~1.00In, 0.05~1.00Un)

Apparent power (VA)
2.10 Management Function

2.10.1 Control Performance
Control mode Local or remote
Response time of local control ≤1s

2 Technical Data
Response time of remote control ≤3s
2.10.2 Clock Performance
Real time clock accuracy ≤1s/day
Accuracy of GPS synchronization ≤1ms
External time synchronization IRIG-B (200-98), PPS, IEEE1588 or SNTP protocol

2
2.10.3 Fault and Disturbance Recording
Settable pre-disturbance, post-disturbance and maximum recorded

Duration & Recording position
duration
Sampling rate Up to 9.6kHz
2.10.4 Binary Input Signal
Resolution of binary input signal ≤1ms
Binary input mode Potential-free contact
2.11 Protective Functions

There are some symbols mentioned in the following sections and the meaning of them is given
here.
Un——VT rated secondary voltage
In——CT rated secondary current
p.u.——per unit value of settings and currents for current differential protection
Id——differential current
3I0d——residual differential current
Iwd——winding differential current
ΔId——DPFC differential current
U*/f*——the overexcitation multiple
2.11.1 Transformer Current Differential Protection (87T)

2.11.1.1 Biased Differential Protection
Tolerance of 2nd and 3rd harmonic settings 0.01
Tolerance of 5th harmonic settings 0.02

2 Technical Data
Tolerance of operating current ≤5% of operating current or 0.02p.u., whichever is greater
Reset ratio ≥95%
50Hz: ≤ 30ms (Id>2 times current setting)

Operating time (without blocking criteria)
2 Reset time ≤30ms
2.11.1.2 Instantaneous Differential Protection
Tolerance of current setting ≤2.5% of setting or 0.02p.u., whichever is greater
Reset ratio ≥95%

Operating time
Reset time ≤30ms
2.11.1.3 DPFC Current Differential Protection
Tolerance of operating current ≤10%
Reset ratio ≥95%
50Hz: ≤30ms (ΔId >3x0.2p.u.)

Operating time
60Hz: ≤30ms (ΔId >3x0.2p.u.)
Reset time ≤30ms
2.11.2 Restricted Earth Fault Protection (64REF)
Tolerance of operating current ≤5% of operating current or 0.02×In, whichever is greater
Reset ratio ≥95%
Operating time (without time delay, without 50Hz: ≤30ms (3I0d>2 times current setting)
blocking criterion) 60Hz: ≤25ms (3I0d>2 times current setting)
Tolerance of time setting ≤1% of setting +30ms (3I0d>2 times current setting)
Reset time ≤30ms

2 Technical Data
2.11.3 Winding Differential Protection (87W)
Tolerance of operating current ≤5% or 0.02×In, whichever is greater
Reset ratio ≥95%
50Hz: ≤30ms (Iwd>2 times current setting)

Operating time (without blocking criterion)
60Hz: ≤25ms (Iwd>2 times current setting)
2
Reset time ≤30ms
2.11.4 Overexcitation Protection (24)
Reset ratio of definite-time overexcitation

≥97%
protection
Tolerance of operating time of definite-time

≤1% of setting +100ms (at 1.5 times U*/f* setting)
overexcitation protection
Tolerance of operating time of inverse-time

≤2.5% of setting +100ms
Reset time of definite-time overexcitation

≤30ms
protection
2.11.5 Phase Overcurrent Protection (50/51P, 67P)

2.11.5.1 Without Direction Control Element
Pickup current setting 1.0×setting
Tolerance of current setting ≤1%×setting or 0.01×In, whichever is greater
Tolerance of voltage setting ≤1%×setting or 0.1V, whichever is greater
Tolerance of pickup time ≤25ms (at 2 times current setting)
Definite-time: ≤1%×setting or 25ms (at 2 times current

setting)
Tolerance of operating time
Inverse-time: ≤ 5 ％ of the calculated value + 1 ％ of
current tolerance, or 35ms (1.2≤I/Ip≤30)
Definite-time: ≤1%×setting or 30ms

Reset time
Inverse-time: ≤5% of the calculated value or 30ms
Reset ratio 0.95
2.11.5.2 With Direction Control Element

2 Technical Data
Definite-time: ≤ 1%×setting or 40ms (at 2 times current

setting)

Reset time
2 Reset ratio 0.95
Tolerance of angle ≤3°
2.11.6 Earth Fault Overcurrent Protection (50/51G, 67G)


setting)
current tolerance, or 35ms（1.2≤I/Ip≤30）

Reset time
Reset ratio 0.95

setting)

Reset time
Inverse-time: ≤5%× the calculated value or 30ms
Reset ratio 0.95

2 Technical Data
2.11.7 Negative-sequence Overcurrent Protection (50/51Q, 67Q)

Definite-time:≤ 1%×setting or 25ms (at 2 times current

2
setting)
current tolerance, or 35ms（1.2≤I/Ip≤30）

Reset time
Reset ratio 0.95

setting)

Reset time
Reset ratio 0.95
2.11.8 Thermal Overload Protection (49)
≤2.5% of operating time or 30ms, whichever is greater (for

Operating time
current between 1.2 and 20 multiples of pickup)
Reset time ≤30ms
2.11.9 Breaker Failure Protection (50BF)
Pickup current 1.0×Setting
Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater
Pickup time ≤20ms (at 2 times current setting)

2 Technical Data
Reset time <20ms (at 2 times current setting)
Reset ratio 1
2.11.10 Overvoltage Protection (59P)
Pickup voltage setting 1.0×setting

2 Tolerance of voltage setting ≤1%×setting or 0.1V, whichever is greater
Tolerance of pickup time ≤35ms (at 1.1 times voltage setting)
Definite-time: ≤1%×setting or 35ms (at 1.1 times voltage

setting)
current tolerance, or 40ms (1.1≤U/Up≤2)
Reset time ≤1%×setting or 30ms, definite-time
Reset ratio 0.93~1.00 (settable), 0.98 by default
2.11.11 Residual Overvoltage Protection (59G)
Tolerance of pickup time ≤35ms (at 1.1 times voltage setting)
Tolerance of operating time ≤1%×setting or 35ms (at 1.1 times voltage setting)
Reset time ≤30ms
2.11.12 Undervoltage Protection (27P)
Tolerance of pickup time ≤35m (at 0.9 times voltage setting)
Definite-time: ≤1%×setting or 35ms (at 0.9 times voltage

setting)
current tolerance, or 50ms (U/Up≤0.9)
Reset time ≤1%×setting or 30ms, definite-time
2.11.13 Overfrequency Protection (81O)
Pickup frequency setting 1.0×setting
Tolerance of frequency setting ≤0.01Hz
Tolerance of pickup time ≤70ms

2 Technical Data
Tolerance of operating time ≤1%×setting or 70ms
Reset time ≤30ms
Reset setting 1.0×Setting
2.11.14 Underfrequency Protection (81U)
Pickup frequency setting
Tolerance of frequency setting

1.0×setting
≤0.01Hz
2
Tolerance of pickup time ≤70ms
Tolerance of operating time ≤1%×setting or 70ms
Reset time ≤30ms
Reset setting 1.0×Setting

Table of Contents
3.1 Three-phase Current Element (TCUR3P) ....................................................... 3-1

3.1.1 Function Description............................................................................................................. 3-1
3.1.2 Function Block Diagram ....................................................................................................... 3-2
3.1.3 I/O Signals ............................................................................................................................ 3-2 3

3.1.4 Settings ................................................................................................................................. 3-3
3.2 Three-phase Voltage Element (TVOL3P)........................................................ 3-3

3.2.3 I/O Signals ............................................................................................................................ 3-4
3.2.4 Settings ................................................................................................................................. 3-5
3.3 Single-phase Current Element (TCUR1P) ...................................................... 3-5

3.3.3 I/O Signals ............................................................................................................................ 3-6
3.3.4 Settings ................................................................................................................................. 3-6
3.4 Single-phase Voltage Element (TVOL1P) ...................................................... 3-7

3.4.3 I/O Signals ............................................................................................................................ 3-7
3.4.4 Settings ................................................................................................................................. 3-7
3.5 Three-phase Current Summation Element (TCUR3P_3SD).......................... 3-8

3.5.3 I/O Signals ............................................................................................................................ 3-9
3.6 Transformer Current Differential Protection (87T) ...................................... 3-10

3.6.1 Function Description........................................................................................................... 3-10

3.6.2 Function Block Diagram ..................................................................................................... 3-33
3.6.3 I/O Signals .......................................................................................................................... 3-33
3.6.4 Logic ................................................................................................................................... 3-35
3.6.5 Settings ............................................................................................................................... 3-37
3.7 Restricted Earth Fault Protection (64REF) .................................................. 3-39

3 3.7.3 I/O Signals .......................................................................................................................... 3-47
3.7.4 Logic ................................................................................................................................... 3-48
3.7.5 Settings ............................................................................................................................... 3-49
3.8 Winding Differential Protection (87W) ......................................................... 3-49

3.8.3 I/O Signals .......................................................................................................................... 3-55
3.8.4 Logic ................................................................................................................................... 3-57
3.8.5 Settings ............................................................................................................................... 3-58
3.9 Overexcitation Protection (24) ...................................................................... 3-59

3.9.3 I/O Signals .......................................................................................................................... 3-61
3.9.4 Logic ................................................................................................................................... 3-62
3.9.5 Settings ............................................................................................................................... 3-64
3.10 Phase Overcurrent Protection (50/51P, 67P) ............................................. 3-66

3.10.1 Function Description......................................................................................................... 3-66
3.10.2 Function Block Diagram ................................................................................................... 3-77
3.10.3 I/O Signal .......................................................................................................................... 3-77
3.10.4 Logic ................................................................................................................................. 3-79
3.10.5 Settings ............................................................................................................................. 3-79
3.11 Earth Fault Overcurrent Protection (50/51G, 67G) .................................... 3-83

3.11.1 Function Description ......................................................................................................... 3-83

3.11.2 Function Block Diagram ................................................................................................... 3-92
3.11.3 I/O Signal .......................................................................................................................... 3-92
3.11.4 Logic ................................................................................................................................. 3-93
3.11.5 Settings ............................................................................................................................. 3-93
3.12 Negative-sequence Overcurrent Protection (50/51Q, 67Q) ...................... 3-97

3.12.1 Function Description......................................................................................................... 3-97
3.12.2 Function Block Diagram ................................................................................................. 3-105
3.12.3 I/O Signal ........................................................................................................................ 3-105 3

3.12.4 Logic ............................................................................................................................... 3-106
3.12.5 Settings ........................................................................................................................... 3-106
3.13 Thermal Overload Protection (49) .............................................................3-110

3.13.1 Application ...................................................................................................................... 3-110
3.13.2 Function Description....................................................................................................... 3-110
3.13.4 I/O Signals ...................................................................................................................... 3-113
3.13.5 Logic ............................................................................................................................... 3-114
3.13.6 Settings ........................................................................................................................... 3-115
3.14 Breaker Failure Protection (50BF) .............................................................3-115

3.14.3 I/O Signals ...................................................................................................................... 3-117
3.14.4 Logic ............................................................................................................................... 3-118
3.14.5 Settings ........................................................................................................................... 3-120
3.15 Phase Overvoltage Protection (59P) ........................................................ 3-121

3.15.3 I/O Signal ........................................................................................................................ 3-127
3.15.4 Logic ............................................................................................................................... 3-128
3.15.5 Settings ........................................................................................................................... 3-128
3.16 Residual Overvoltage Protection (59G) ................................................... 3-130
PCS-978S Transformer Relay 3-c

3.16.3 I/O Signal ........................................................................................................................ 3-133
3.16.4 Logic ............................................................................................................................... 3-134
3.16.5 Settings ........................................................................................................................... 3-134
3.17 Phase Undervoltage Protection (27P) ...................................................... 3-135

3 3.17.2 Function Block Diagram ................................................................................................. 3-141
3.17.3 I/O Signal ........................................................................................................................ 3-141
3.17.4 Logic ............................................................................................................................... 3-142
3.17.5 Settings ........................................................................................................................... 3-142
3.18 Overfrequency Protection (81O)............................................................... 3-145

3.18.3 I/O Signals ...................................................................................................................... 3-146
3.18.4 Logic ............................................................................................................................... 3-147
3.18.5 Settings ........................................................................................................................... 3-147
3.19 Underfrequency Protection (81U)............................................................. 3-147

3.19.3 I/O Signals ...................................................................................................................... 3-149
3.19.4 Logic ............................................................................................................................... 3-150
3.19.5 Settings ........................................................................................................................... 3-150
3.20 VT Circuit Supervision (VTS) .................................................................... 3-150

3.20.2 Function Block ................................................................................................................ 3-152
3.20.3 I/O Signals ...................................................................................................................... 3-152
3.20.4 Logic ............................................................................................................................... 3-153
3.20.5 Settings ........................................................................................................................... 3-153
3.21 Output Map (OutMap) ................................................................................ 3-154
3-d PCS-978S Transformer Relay

3.21.2 I/O Signals ...................................................................................................................... 3-156
3.21.3 Settings ........................................................................................................................... 3-156
List of Figures
Figure 3.6-1 Current compensation calculation process.................................................... 3-16
Figure 3.6-2 Operation characteristic of sensitive biased differential element ............... 3-19
Figure 3.6-3 Operation characteristic of conventional biased differential element ......... 3-20 3
Figure 3.6-4 Operation characteristic of biased/instantaneous differential elements .... 3-21
Figure 3.6-5 Operation characteristic of DPFC biased differential protection ................. 3-24
Figure 3.6-6 Schematic of waveform symmetry principle .................................................. 3-26
Figure 3.6-7 Logic of inrush current blocking current differential protection.................. 3-29
Figure 3.6-8 Logic of enabling transformer differential protection ................................... 3-35
Figure 3.6-9 Pickup logic of transformer differential protection........................................ 3-36
Figure 3.6-10 Logic diagram of instantaneous differential element .................................. 3-36
Figure 3.6-11 Logic diagram of biased differential element ............................................... 3-36
Figure 3.6-12 Logic diagram of DPFC biased differential element .................................... 3-37
Figure 3.6-13 Logic diagram of CT circuit failure alarm...................................................... 3-37
Figure 3.7-1 Application for two-windings transformer with one CB at one side ............ 3-40
Figure 3.7-2 Application for two-windings transformer with two CBs at one side .......... 3-40
Figure 3.7-3 Application for auto-transformer...................................................................... 3-41
Figure 3.7-4 REF principle ...................................................................................................... 3-43
Figure 3.7-5 Operation characteristic of REF ....................................................................... 3-44
Figure 3.7-6 Currents at an external earth fault ................................................................... 3-45
Figure 3.7-7 Currents at an internal earth fault .................................................................... 3-45
Figure 3.7-8 Logic of enabling restricted earth fault protection ........................................ 3-48
Figure 3.7-9 Pickup logic of restricted earth fault protection ............................................ 3-48
Figure 3.7-10 Logic diagram of restricted earth fault protection ....................................... 3-48
Figure 3.8-1 Winding differential protection applied to auto-transformer ........................ 3-50
Figure 3.8-2 Winding differential protection applied to stub differential protection ....... 3-50
PCS-978S Transformer Relay 3-e

Figure 3.8-3 Operating characteristic of winding differential protection .......................... 3-54
Figure 3.8-4 Logic of enabling winding differential protection .......................................... 3-57
Figure 3.8-5 Pickup logic of transformer differential protection........................................ 3-57
Figure 3.8-6 Logic diagram of winding differential protection ........................................... 3-58
Figure 3.9-1 Inverse-time characteristic of overexcitation protection .............................. 3-60
Figure 3.9-2 Logic of enabling overexcitation protection ................................................... 3-63
Figure 3.9-3 Pickup logic of overexcitation protection ....................................................... 3-63
3 Figure 3.9-4 Logic diagram of definite-time overexcitation protection ............................. 3-63
Figure 3.9-5 Logic diagram of inverse-time overexcitation protection ............................. 3-64
Figure 3.10-1 Logic of enabling phase overcurrent protection.......................................... 3-67
Figure 3.10-2 Pickup logic of phase overcurrent protection .............................................. 3-67
Figure 3.10-3 Logic of voltage control element ................................................................... 3-68
Figure 3.10-4 Operating characteristics of the direction element ..................................... 3-68
Figure 3.10-5 Logic of forward and reverse direction element .......................................... 3-70
Figure 3.10-6 Logic of harmonic control element ................................................................ 3-71
Figure 3.10-7 Definite-time operating curve of phase overcurrent protection ................. 3-73
Figure 3.10-8 Inverse-time operating curve of phase overcurrent protection.................. 3-74
Figure 3.10-9 Definite-time dropout characteristics of phase overcurrent protection .... 3-75
Figure 3.10-10 Inverse-time dropout curve of phase overcurrent protection .................. 3-76
Figure 3.10-11 Inverse-time dropout characteristics of phase overcurrent protection... 3-77
Figure 3.10-12 Logic of phase overcurrent protection........................................................ 3-79
Figure 3.11-1 Logic of enabling earth fault protection ........................................................ 3-83
Figure 3.11-2 Pickup logic of earth fault protection ............................................................ 3-84
Figure 3.11-3 Operating characteristics of direction control element ............................... 3-84
Figure 3.11-5 Logic of harmonic control element ................................................................ 3-87
Figure 3.11-6 Definite-time operating curve of earth fault protection ............................... 3-88
Figure 3.11-7 Inverse-time operating curve of earth fault protection ................................ 3-89
Figure 3.11-8 Definite-time dropout characteristics of earth fault protection .................. 3-90
Figure 3.11-9 Inverse-time dropout curve of earth fault protection ................................... 3-91
3-f PCS-978S Transformer Relay

Figure 3.11-10 Inverse-time dropout characteristics of earth fault protection ................. 3-92
Figure 3.11-11 Logic diagram of earth fault overcurrent protection .................................. 3-93
Figure 3.12-1 Logic of enabling negative-sequence overcurrent protection ................... 3-97
Figure 3.12-2 Pickup logic of negative-sequence protection ............................................. 3-98
Figure 3.12-3 Operating characteristics of direction control element............................... 3-98
Figure 3.12-5 Definite-time operating curve of negative-sequence overcurrent protection

................................................................................................................................................. 3-101
3
Figure 3.12-6 Inverse-time operating curve of negative-sequence overcurrent protection
................................................................................................................................................. 3-102
Figure 3.12-7 Definite-time dropout characteristics of negative-sequence overcurrent

protection ............................................................................................................................... 3-103
Figure 3.12-8 Inverse-time dropout curve of negative-sequence overcurrent protection

................................................................................................................................................. 3-104
Figure 3.12-9 Inverse-time dropout characteristics of negative-sequence overcurrent

protection ............................................................................................................................... 3-105
Figure 3.12-10 Logic of negative-sequence overcurrent protection ............................... 3-106
Figure 3.13-1 Characteristic curve of thermal overload protection ................................. 3-111
Figure 3.13-2 Logic diagram of enabling thermal overload protection (method 1) ....... 3-114
Figure 3.13-3 Pickup logic of thermal overload protection (method 1) ........................... 3-114
Figure 3.13-4 Logic diagram of thermal overload protection (method 1) ....................... 3-114
Figure 3.14-1 Logic of enabling reverse power protection ............................................... 3-118
Figure 3.14-2 Logic of breaker failure initiating signal abnormality ................................ 3-119
Figure 3.14-3 Logic of breaker failure protection .............................................................. 3-120
Figure 3.15-1 Logic of enabling phase overvoltage protection ....................................... 3-122
Figure 3.15-2 Pickup logic of phase overvoltage protection............................................ 3-123
Figure 3.15-3 Definite-time operating curve of phase overvoltage protection ............... 3-124
Figure 3.15-4 Inverse-time operating curve of phase overvoltage protection ............... 3-125
Figure 3.15-5 Definite-time dropout characteristics of phase overvoltage protection.. 3-126
Figure 3.15-6 Logic of phase overvoltage protection ....................................................... 3-128
Figure 3.16-1 Logic of enabling residual overvoltage protection .................................... 3-131
PCS-978S Transformer Relay 3-g

Figure 3.16-2 Pickup logic of residual overvoltage protection ........................................ 3-131
Figure 3.16-3 Definite-time operating curve of residual overvoltage protection ........... 3-132
Figure 3.16-4 Definite-time dropout characteristics of residual overvoltage protection3-133
Figure 3.16-5 Logic of residual overvoltage protection .................................................... 3-134
Figure 3.17-1 Logic of enabling phase undervoltage protection ..................................... 3-136
Figure 3.17-2 Pickup logic of phase undervoltage protection ......................................... 3-137
Figure 3.17-3 Definite-time operating curve of phase undervoltage protection ............ 3-138
3 Figure 3.17-4 Inverse-time operating curve of phase undervoltage protection ............. 3-139
Figure 3.17-5 Definite-time dropout characteristics of phase undervoltage protection3-140
Figure 3.17-6 Logic of phase undervoltage protection ..................................................... 3-142
Figure 3.18-1 Logic of enabling overfrequency protection .............................................. 3-145
Figure 3.18-2 Pickup logic of overfrequency protection................................................... 3-145
Figure 3.18-3 Definite-time operating curve of overfrequency protection...................... 3-146
Figure 3.18-4 Function block diagram of overfrequency protection ............................... 3-146
Figure 3.18-5 Logic of overfrequency protection .............................................................. 3-147
Figure 3.19-1 Logic of enabling underfrequency protection ............................................ 3-148
Figure 3.19-2 Pickup logic of underfrequency protection ................................................ 3-148
Figure 3.19-3 Definite-time operating curve of underfrequency protection ................... 3-149
Figure 3.19-4 Function block diagram of underfrequency protection............................. 3-149
Figure 3.19-5 Logic of underfrequency protection ............................................................ 3-150
Figure 3.20-1 VT circuit supervision logic diagram ........................................................... 3-153
Figure 3.20-2 Neutral VT supervision logic diagram ......................................................... 3-153
List of Tables
Table 3.1-1 Input signals of three-phase current element .................................................... 3-2
Table 3.1-2 Output signals of three-phase current element ................................................. 3-2
Table 3.1-3 Settings of three-phase current element............................................................. 3-3
Table 3.2-1 Input signals of three-phase voltage element .................................................... 3-4
Table 3.2-2 Output signals of three-phase voltage element ................................................. 3-4
Table 3.2-3 Settings of three-phase voltage element ............................................................ 3-5
3-h PCS-978S Transformer Relay

Table 3.3-1 Input signals of single-phase current element ................................................... 3-6
Table 3.3-2 Output signals of single-phase current element ................................................ 3-6
Table 3.3-3 Settings of single-phase current element ........................................................... 3-6
Table 3.4-1 Input signals of single-phase voltage element................................................... 3-7
Table 3.4-2 Output signals of single-phase voltage element................................................ 3-7
Table 3.4-3 Settings of single-phase voltage element ........................................................... 3-7
Table 3.5-1 I/O signals of three-phase current summation element .................................... 3-9
Table 3.5-2 I/O signals of three-phase current summation element .................................... 3-9 3
Table 3.6-1 Matrix of phase compensation ........................................................................... 3-14
Table 3.6-2 Comparison of different blocking modes ......................................................... 3-28
Table 3.6-3 Input signals of transformer differential protection......................................... 3-33
Table 3.6-4 Output signals of transformer differential protection ..................................... 3-33
Table 3.6-5 Settings of transformer differential protection ................................................ 3-37
Table 3.7-1 Input signals of restricted earth-fault protection ............................................. 3-47
Table 3.7-2 Output signals of restricted earth-fault protection .......................................... 3-47
Table 3.7-3 Settings of restricted earth fault protection ..................................................... 3-49
Table 3.8-1 Input signals of winding differential protection ............................................... 3-55
Table 3.8-2 Output signals of winding differential protection ............................................ 3-56
Table 3.8-3 Settings of winding differential protection ....................................................... 3-58
Table 3.9-1 Input signals of overexcitation protection ........................................................ 3-61
Table 3.9-2 Output signals of overexcitation protection ..................................................... 3-62
Table 3.9-3 Settings of overexcitation protection ................................................................ 3-64
Table 3.10-1 Input signals of phase overcurrent protection ............................................... 3-77
Table 3.10-2 Output signals of phase overcurrent protection ............................................ 3-78
Table 3.10-3 Settings of phase overcurrent protection ....................................................... 3-79
Table 3.11-1 Input signals of earth fault protection ............................................................. 3-92
Table 3.11-2 Output signals of earth fault protection .......................................................... 3-93
Table 3.11-3 Settings of earth fault overcurrent protection ................................................ 3-94
Table 3.12-1 Input signals of negative-sequence overcurrent protection ...................... 3-105
Table 3.12-2 Output signals of negative-sequence overcurrent protection ................... 3-106
PCS-978S Transformer Relay 3-i

Table 3.12-3 Settings of negative-sequence overcurrent protection............................... 3-106
Table 3.13-1 Input signals of thermal overload protection ............................................... 3-113
Table 3.13-2 Output signals of thermal overload protection ............................................ 3-113
Table 3.13-3 Settings of thermal overload protection ....................................................... 3-115
Table 3.14-1 Input signals of breaker failure protection ................................................... 3-117
Table 3.14-2 Output signals of breaker failure protection ................................................ 3-118
Table 3.14-3 Settings of breaker failure protection............................................................ 3-120
3 Table 3.15-1 Input signals of phase overvoltage protection............................................. 3-127
Table 3.15-2 Output signals of phase overvoltage protection.......................................... 3-127
Table 3.15-3 Settings of phase overvoltage protection ..................................................... 3-128
Table 3.16-1 Input signals of residual overvoltage protection ......................................... 3-133
Table 3.16-2 Output signals of residual overvoltage protection ...................................... 3-134
Table 3.16-3 Settings of residual overvoltage protection ................................................. 3-134
Table 3.17-1 Input signals of phase undervoltage protection .......................................... 3-141
Table 3.17-2 Output signals of phase undervoltage protection ....................................... 3-141
Table 3.17-3 Settings of phase undervoltage protection .................................................. 3-142
Table 3.18-1 Input signals of overfrequency protection ................................................... 3-146
Table 3.18-2 Output signals of overfrequency protection ................................................ 3-146
Table 3.18-3 Settings of overfrequency protection............................................................ 3-147
Table 3.19-1 Input signals of underfrequency protection ................................................. 3-149
Table 3.19-2 Output signals of underfrequency protection .............................................. 3-149
Table 3.19-3 Settings of underfrequency protection ......................................................... 3-150
Table 3.20-1 Input signals of VT circuit supervision ......................................................... 3-152
Table 3.20-2 Settings of VT circuit supervision ................................................................. 3-154
Table 3.21-1 I/O signals of programmable trip output ....................................................... 3-156
Table 3.21-2 Settings of programmable trip output ........................................................... 3-156
3-j PCS-978S Transformer Relay

3.1 Three-phase Current Element (TCUR3P)
Three-phase current element is responsible for pre-processing three phase currents and
calculating sequence components, amplitudes and phases of three phase currents, etc. All
calculated information of three-phase current element is used for protection logic calculation.
The symbol “x” represents some side of transformer defined by user

through PCS-Studio software, which may be “HVS”, “MVS”, “LVS”, “CWS”
by default.
3
3.1.1 Function Description
Three-phase current element has following functions:
1. Pre-process three phase currents
2. Calculate information related to three-phase current
3.1.1.1 CT Circuit Failure Supervision
When three phase currents are engaged in the calculation of transformer differential protection,
restricted earth fault protection or winding differential protection, CT circuit failure supervision of
each protection is carried out in the corresponding protection element, which can refer to
corresponding sections for details.
3.1.1.2 Current Detection
When any phase current is greater than 0.04In, inputted current signals are decided valid and the
valid signal is outputted for programmable logic application.

3.1.2 Function Block Diagram
TCUR3P
x.in_ia x.I3P
x.in_ib x.Ia_Sec
x.in_ic x.Ib_Sec
x.in_ia_smv x.Ic_Sec
x.in_ib_smv x.I1_Sec
3 x.in_ic_smv x.I2_Sec
x.3I0_Cal_Sec
x.Ang(Ia-Ib)
x.Ang(Ib-Ic)
x.Ang(Ic-Ia)
x.Ang(Ia)
x.Ang(Ib)
x.Ang(Ic)
x.Ang(3I0_Cal)
x.Alm_CTS
x.Flg_OnLoad
3.1.3 I/O Signals

Table 3.1-1 Input signals of three-phase current element
No. Input Signal Description

1 x.in_ia Sampled value of phase-A current at x side of transformer
2 x.in_ib Sampled value of phase-B current at x side of transformer
3 x.in_ic Sampled value of phase-C current at x side of transformer
4 x.in_ia_smv SMV value of phase-A current at x side of transformer
5 x.in_ib_smv SMV value of phase-B current at x side of transformer
6 x.in_ic_smv SMV value of phase-C current at x side of transformer
Table 3.1-2 Output signals of three-phase current element
No. Output Signal Description

1 x.I3P A current data set at x side of transformer
2 x.Ia_Sec Amplitude of phase-A secondary current at x side of transformer
3 x.Ib_Sec Amplitude of phase-B secondary current at x side of transformer
4 x.Ic_Sec Amplitude of phase-C secondary current at x side of transformer


5 x.I1_Sec Amplitude of positive sequence secondary current at x side of transformer
6 x.I2_Sec Amplitude of negative sequence secondary current at x side of transformer
7 x.3I0_Cal_Sec Amplitude of calculated residual secondary current at x side of transformer
8 x.Ang(Ia-Ib) Phase angle between phase A and phase B currents at x side of transformer
9 x.Ang(Ib-Ic) Phase angle between phase B and phase C currents at x side of transformer
10 x.Ang(Ic-Ia) Phase angle between phase C and phase A currents at x side of transformer
11 x.Ang(Ia) Phase angle of phase-A current at x side of transformer
12 x.Ang(Ib) Phase angle of phase-B current at x side of transformer
13 x.Ang(Ic) Phase angle of phase-C current at x side of transformer
14 x.Ang(3I0_Cal) Phase angle of calculated residual current at x side of transformer 3
15 x.Alm_CTS CT secondary circuit failure at x side of transformer
16 x.Flg_OnLoad A flag indicating there is load current detected at x side of transformer
3.1.4 Settings
Table 3.1-3 Settings of three-phase current element
No. Item Range Unit Default Description

1 x.I1n 0~9999 A 1000 Primary current value at x side of transformer
2 x.I2n 1 or 5 A 1 Secondary current value at x side of transformer
Enabled, Logic setting of enabling/disabling the current polarity of
3 x.En_RevCT - Disabled
Disabled CT reversed at x side of transformer
3.2 Three-phase Voltage Element (TVOL3P)
Three-phase voltage element is responsible for pre-processing three phase voltages and
calculating sequence components, amplitudes and phases of three phase voltages, etc. All
calculated information of three-phase voltage element is used for the protection logic calculation.

by default.

Three-phase voltage element has following functions:
1. Pre-process three phase voltages
2. Calculate information related to three phase voltages
3.2.1.1 VT Circuit Failure Supervision
VT circuit failure supervision of three-phase voltage is carried out by the special VTS element,

which can refer to Section 3.20 for details.
TVOL3P
x.in_ua x.U3P
x.in_ub x.Ua_Sec
x.in_uc x.Ub_Sec
x.in_ua_smv x.Uc_Sec
3 x.in_ub_smv x.Uab_Sec
x.in_uc_smv x.Ubc_Sec
x.BI_En_VT x.Uca_Sec
x.U1_Sec
x.U2_Sec
x.3U0_Cal_Sec
x.Ang(Ua-Ub)
x.Ang(Ub-Uc)
x.Ang(Uc-Ua)
x.Ang(Ua)
x.Ang(Ub)
x.Ang(Uc)
x.Ang(3U0_Cal)
X.VTS.Alm
3.2.3 I/O Signals

Table 3.2-1 Input signals of three-phase voltage element
No. Input signal Description

1 x.in_ua Sampled value of phase-A voltage at x side of transformer
2 x.in_ub Sampled value of phase-B voltage at x side of transformer
3 x.in_uc Sampled value of phase-C voltage at x side of transformer
4 x.in_ua_smv SMV value of phase-A voltage at x side of transformer
5 x.in_ub_smv SMV value of phase-B voltage at x side of transformer
6 x.in_uc_smv SMV value of phase-C voltage at x side of transformer
7 x.BI_En_VT Input signal of indicating VT in service at x side of transformer
Table 3.2-2 Output signals of three-phase voltage element

No. Output signal Description

1 x.U3P A voltage data set at x side of transformer
2 x.Ua_Sec Amplitude of phase-A secondary voltage at x side of transformer
3 x.Ub_Sec Amplitude of phase-B secondary voltage at x side of transformer
4 x.Uc_Sec Amplitude of phase-C secondary voltage at x side of transformer
5 x.Uab_Sec Amplitude of phase-AB secondary voltage at x side of transformer
6 x.Ubc_Sec Amplitude of phase-BC secondary voltage at x side of transformer
7 x.Uca_Sec Amplitude of phase-CA secondary voltage at x side of transformer
8 x.U1_Sec Amplitude of positive sequence secondary voltage at x side of transformer
9 x.U2_Sec Amplitude of negative sequence secondary voltage at x side of transformer
10 x.3U0_Cal_Sec Amplitude of calculated residual secondary voltage at x side of transformer 3
11 x.Ang(Ua-Ub) Phase angle between phase A and phase B voltages at x side of transformer
12 x.Ang(Ub-Uc) Phase angle between phase B and phase C voltages at x side of transformer
13 x.Ang(Uc-Ua) Phase angle between phase C and phase A voltages at x side of transformer
14 x.Ang(Ua) Phase angle of phase-A voltage at x side of transformer
15 x.Ang(Ub) Phase angle of phase-B voltage at x side of transformer
16 x.Ang(Uc) Phase angle of phase-C voltage at x side of transformer
17 x.Ang(3U0_Cal) Phase angle of calculated residual voltage at x side of transformer
18 x.VTS.Alm VT secondary circuit abnormality at x side of transformer
3.2.4 Settings
Table 3.2-3 Settings of three-phase voltage element

1 x.U1n 1.000~1100.000 kV - Rated value of primary voltage at x side of transformer
Rated value of secondary voltage at x side of
2 x.U2n 1.000~120.000 V -
transformer
Enabled,
3 x.En_VT - Enabled Logic setting to put VT into service
Disabled
3.3 Single-phase Current Element (TCUR1P)
Single-phase current element is responsible for pre-processing measured single-phase current

and calculating the magnitude and the phase angle of the single-phase current, etc. All calculated
information of single-phase current element is used for the protection logic calculation.

by default.


Single-phase current element has following functions:
1. Pre-process measured single-phase current
2. Calculate information related to the single-phase current
TCUR1P
3 x.in_ip x.I1P
x.in_ip_smv x.3I0_Ext_Sec
x.Ang(3I0_Ext)
x.Flg_OnLoad
3.3.3 I/O Signals

Table 3.3-1 Input signals of single-phase current element

1 x.in_ip Sampled single-phase current at x side of transformer
2 x.in_ip_smv SMV single-phase current at x side of transformer
Table 3.3-2 Output signals of single-phase current element

2 x.3I0_Ext_Sec Amplitude of external residual secondary current at x side of transformer
3 x.Ang(3I0_Ext) Phase angle of external residual current at x side of transformer
3.3.4 Settings
Table 3.3-3 Settings of single-phase current element

Primary rated current of neutral CT at x side of
1 x.Neu.I1n 0~9999 A 1000
transformer
Secondary rated current of neutral CT at x side
2 x.Neu.I2n 1 or 5 A 1
of transformer
Logic setting of enabling/disabling the current
Enabled,
3 x.Neu.En_RevCT - Disabled polarity of neutral CT CT reversed at x side of
Disabled
transformer

3.4 Single-phase Voltage Element (TVOL1P)
Single-phase voltage element is responsible for pre-processing single-phase voltage and

calculating the magnitude and the phase angle of the single-phase voltage, etc. All calculated
information of single-phase voltage element is used for the protection logic calculation.

by default.
3
Single-phase voltage element has following functions:
1. Pre-process measured single-phase voltage
2. Calculate information related to single-phase voltage
TVOL1P
x.in_up x.U1P
x.in_up_smv x.U_Sec
X.BI_En_VT x.Ang(U)
3.4.3 I/O Signals

Table 3.4-1 Input signals of single-phase voltage element

1 x.in_up Sampled single-phase voltage at x side of transformer
2 x.in_up_smv SMV single-phase voltage at x side of transformer
3 x.BI_En_VT Input signal of indicating VT in service at x side of transformer
Table 3.4-2 Output signals of single-phase voltage element

1 x.U1P A voltage data set at x side of transformer
2 x.U_Sec Amplitude of single-phase secondary voltage at x side of transformer
3 x.Ang(U) Phase angle of single-phase voltage at x side of transformer
3.4.4 Settings
Table 3.4-3 Settings of single-phase voltage element


Primary rated voltage of broken-delta VT at x side of
1 x.Neu.U1n 0.000~1100.000 kV -
transformer
Secondary rated voltage of broken-delta VT at x side
2 x.Neu.U2n 1.000~200.000 V -
of transformer
3.5 Three-phase Current Summation Element (TCUR3P_3SD)
Three-phase current summation element is responsible for calculating the sum of multiple current
inputs in one side of transformer. All calculated information of three-phase current summation
3 element is used for the protection logic calculation.

by default.

Three-phase current summation element has following functions:
1. Calculate the sum of several groups of currents
3.5.1.1 Current Detection
When any phase current is greater than 0.04In, inputted current signals are decided valid and the
valid signal is outputted for programmable logic application.

TCUR3P_3SD
x.in_i3p1 x.I3P
x.in_i3p2 x.Ia_Sec
x.in_i3p3 x.Ib_Sec
x.Ic_Sec
x.I1_Sec
x.I2_Sec 3
x.3I0_Cal_Sec
x.Ang(Ia-Ib)
x.Ang(Ib-Ic)
x.Ang(Ic-Ia)
x.Ang(Ia)
x.Ang(Ib)
x.Ang(Ic)
x.Ang(3I0_Cal)
x.Flg_OnLoad
3.5.3 I/O Signals

Table 3.5-1 I/O signals of three-phase current summation element

st
1 x.in_i3p1 Sampled value of the 1 group of three-phase current at x side of transformer
nd
rd
Table 3.5-2 I/O signals of three-phase current summation element

2 x.Ia_Sec Amplitude of phase-A secondary current at x side of transformer
3 x.Ib_Sec Amplitude of phase-B secondary current at x side of transformer
4 x.Ic_Sec Amplitude of phase-C secondary current at x side of transformer
5 x.I1_Sec Amplitude of positive sequence secondary current at x side of transformer
6 x.I2_Sec Amplitude of negative sequence secondary current at x side of transformer
7 x.3I0_Cal_Sec Amplitude of calculated residual secondary current at x side of transformer
8 x.Ang(Ia-Ib) Phase angle between phase A and phase B currents at x side of transformer


9 x.Ang(Ib-Ic) Phase angle between phase B and phase C currents at x side of transformer
10 x.Ang(Ic-Ia) Phase angle between phase C and phase A currents at x side of transformer
11 x.Ang(Ia) Phase angle of phase-A current at x side of transformer
12 x.Ang(Ib) Phase angle of phase-B current at x side of transformer
13 x.Ang(Ic) Phase angle of phase-C current at x side of transformer
14 x.Ang(3I0_Cal) Phase angle of calculated residual current at x side of transformer
3.6 Transformer Current Differential Protection (87T)

3 In power system, the power transformer is one of most valuable and expensive equipment. If a
fault occurs in the protection zone of a transformer, current differential protection operates quickly
to clear the fault to avoid the transformer from damages or reduce the maintenance cost as low as
possible.

Transformer differential protection supports up to 6 group CT inputs, and can be used for
2-windings, 3-windings transformer and auto-transformer. There are 24 vector groups available
for two-winding transformer and 288 vector groups available for 3-winding transformer.
Transformer differential protection includes biased differential element, instantaneous differential

element, DPFC biased differential element. Biased differential element is biased characteristic
with three slopes Instantaneous differential element is without biased characteristic and blocking
logic and can accelerate to operate for transformer's severe internal faults. DPFC biased
differential element calculated by current variation has high sensitivity to inter-turn faults and
high-impedance fault under heavy load. Three differential elements mentioned above work
coordinately to form the high-speed current differential protection with high sensitivity.
3.6.1.1 Fault Detector
 Fault detector based on biased differential current
The fault detector can initiate biased differential element, and its operation equation is as follows.
Id>[87T.I_Biased] Equation 3.6-1
Where:
Id is the differential current of any phase.
 Fault detector based on instantaneous differential current
The fault detector can initiate instantaneous differential element, and its operation equation is as
follows.
Id>0.5x[87T.I_Inst] Equation 3.6-2

Where:
Id is the differential current of any phase.
 Fault Detector based on DPFC differential current
The fault detector can initiate DPFC biased differential element, and its operation equation is as
follows.
I d  1.25  I dt  I dth
Equation 3.6-3
  
I d   I 1   I 2  ...   I m
3
Where:
I dt is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold ( I dt ) is higher than the change of current under these conditions and hence the
element maintains stability.
I dth is fixed threshold internally.
I d is DPFC differential current.
  
 I 1 ,  I 2 , …,  I m are DPFC current of each side of transformer representatively.
Regardless of direction of power flow and very sensitive, this fault detector is used to guard DPFC
biased differential protection. The setting is fixed in factory and thus site setting is not required.
3.6.1.2 Amplitude Compensation
During the normal operation, the magnitudes of secondary current of each side of transformer are
different due to the mismatch between the CT ratios and the power transformer ratio. The current
value difference between each side shall be eliminated before calculation for current differential
protection by amplitude compensation.
 Calculate rated primary current at each side
Sn
I 1bBrm  Equation 3.6-4
3U 1nBrm
Where:
Sn is the maximum rated capacity (i.e., the setting [Sn]).
U1n is rated primary voltage.

U1nBrm is rated primary voltage of side m (i.e., the settings [HVS.U1n_Tr], [MVS.U1n_Tr] or
[LVS.U1n_Tr]).
I1bBrm is rated primary current of side m.
 Calculate rated secondary current at each side
I 1bBrm
I 2bBrm  Equation 3.6-5
CTBrm
Where:
3 I2bBrm is rated secondary current of side m.
CTBrm is the CT ratio of side m.
 Limitation of secondary current
For all differential protections, the secondary currents of each side must follow below criterion.
I 2bBr1 I 2bBr2 I
Max( , ,..., 2bBrm )
I 2nBr1 I 2nBr2 I 2nBrm
 128 Equation 3.6-6
I 2bBr1 I 2bBr2 I 2bBrm
Min( , ,..., )
When selecting CT, the ratio between maximum value and minimum value
should be considered. It is recommended that the ratio is smaller than 16.
Theoretically, the ratio is preferred to be as small as it can be.
For DPFC biased differential element, the secondary currents of each side must follow Equation
3.6-7 in addition to Equation 3.6-6. Otherwise, alarm signals [ProtBrd.Fail_Settings] and
[FDBrd.Fail_Settings] are issued and the device will be blocked at the same time unless DPFC
biased differential element is disabled.
I 2bBr1 I 2bBr2 I
Max( , ,..., 2bBrm )  0.4
Equation 3.6-7
I I I
Min( 2bBr1 , 2bBr2 ,..., 2bBrm )  0.1
Where:
I2bBr1, I2bBr2… I2bBrm are rated secondary current of branch 1, 2 … m of transformer.
I2nBr1, I2nBr2…I2nBrm are CT rated secondary current of branch 1, 2 … m of transformer.

If Equation 3.6-6 is not met, alarm signals [ProtBrd.Fail_Settings] and

[FDBrd.Fail_Settings] are issued and the device will be blocked at the
same time.
When viewing settings and values of conventional current differential

protection in the device, p.u. (per unit value) is provided. The current in
differential protection calculation is not actual secondary value but per unit
value which is got by actual secondary value of each branch of transformer
divided by transformer secondary rated current of each side (i.e., I2bBrm).
3
3.6.1.3 Phase Compensation
 Phase compensation principle
False differential current is caused by phase shift between the power transformer primary current
and secondary current for delta/wye, so phases of each side secondary current must be
compensated by this phase compensation. Δ→Y and Y→Δ transfer methods by settings can be
selected to adjust phase angle of secondary current on each side of the transformer, and Δ→Y
transfer method is recommended. Zero-sequence current is always eliminated both at Y and Δ
windings by adopting Δ→Y method.
The following transforming method is based on the assumptions listed here:
1. Each side three-phase CT of transformer shall be connected in star type.
2. The positive polarity of each side three-phase CT shall be at busbar side.
The wiring connection of HV, MV and LV sides may be different, so it is needed to compensate
phase of each side current of transformer for calculation of current differential protection. There
are two transforming methods for phase compensation: Δ→Y and Y→Δ, and different
transforming methods will result in the difference.
Phase compensation is controlled by the following settings:
1. [Clk_MVS_WRT_HVS], [Clk_LVS_WRT_HVS]: the wiring o’clock of MV/LV side with respect

to HV side, is the parameter shown on transformer nameplate with the range of 0~11, and
need no further calculation.
2. [Clk_PhComp]: the target o'clock each side current will be shifted to for phase compensation.
3. [HVS.En_I0Elim], [MVS.En_I0Elim] and [LVS.En_I0Elim]: logic settings to enable

zero-sequence current elimination for phase compensation of each side of transformer. The
setting is recommended to be set to “1” in general condition, and only if one side of
transformer, without earthing transformer being connected to, is not grounded, the setting of
corresponding side is recommended to be set to “0”.
For example:
The vector group of a transformer is Y0/Δ11 and the target o'clock ([Clk_PhComp]) is set to LV

side. Therefore, the setting [Clk_LVS_WRT_HVS] should be set to “11”.
1. For HV side, with reference to the set target o'clock, the o'clock of HV side is 1 (i.e. wiring
o'clock 12-target o'clock 11) clock, so the matrix of relative o'clock 1 is adopted to
compensate HV side current.
2. For LV side, with reference to the set target o'clock, the o'clock of LV side is 0 (i.e. wiring
o'clock 11- target o'clock 11), so the matrix of relative o'clock 0 is adopted to compensate LV
side current.
If an earthing transformer is connected outside the protection zone of differential protection, the
setting [HVS.En_I0Elim] (or [LVS.En_I0Elim]) could be disabled, i.e. set to 0.
3 If an earthing transformer is connected within the protection zone of differential protection, then
zero-sequence current must be eliminated and otherwise differential protection may operate
unexpectedly during an external fault. Therefore the setting [HVS.En_I0Elim] (or [LVS.En_I0Elim])
must be enabled, i.e., set to 1.
Table 3.6-1 Matrix of phase compensation
Matrix without zero-sequence current Matrix with zero-sequence current

Relative o'clock
elimination elimination
1 0 0   2 - 1 - 1
0 0 1 0  1
- 1 2 - 1
(No phase shit)   3 
0 0 1 - 1 - 1 2 
 1 -1 0   1 -1 0 
1 
0 1 - 1
1 
0 1 - 1
1
(Shift 30°leading) 3  3 
- 1 0 1  - 1 0 1 
 0 -1 0   1 -2 1 
2  0 0 - 1 1
1 1 - 2 
(shift 60°leading)   3 
- 1 0 0  - 2 1 1 
 0 -1 1   0 -1 1 
1 
1 0 - 1
1 
1 0 - 1
3
(Shit 90°leading) 3  3 
- 1 1 0  - 1 1 0 
0 0 1 - 1 - 1 2 
4 1 0 0  1
2 - 1 - 1
(Shit 120°leading)   3 
0 1 0  - 1 2 - 1
- 1 0 1  - 1 0 1 
1 
1 - 1 0 
1 
1 - 1 0 
5
(Shift 150°leading) 3  3 
 0 1 - 1  0 1 - 1

- 1 0 0  - 2 1 1 
6  0 -1 0  1
1 - 2 1 
(Shift 180°leading)   3 
 0 0 - 1  1 1 - 2 
- 1 1 0  - 1 1 0 
1 
0 - 1 1 
1 
0 - 1 1 
7
(Shift 150°lagging) 3 3
 1 0 - 1  1 0 - 1
0 1 0  - 1 2 - 1
8 0 0 1 1
- 1 - 1 2 
  
(Shift 120°lagging)
1 0 0 
3
 2 - 1 - 1 3
 0 1 - 1  0 1 - 1
1 
- 1 0 1 
1 
- 1 0 1 
S9
(Shift 90°lagging) 3  3 
 1 - 1 0   1 - 1 0 
 0 0 - 1  1 1 - 2
10 - 1 0 0  1
- 2 1 1 
(Shift 60°lagging)   3
 0 - 1 0   1 - 2 1 
 1 0 - 1  1 0 - 1
1 
- 1 1 0 
1 
- 1 1 0 
11
(Shift 30°lagging) 3  3 
 0 - 1 1   0 - 1 1 
3.6.1.4 Calculate Differential and Restraint Currents
The equation of calculating differential current is:

 I dA   I A1  I A2   I A3  I A4 
         
I
 dB   M  /
1  B1 2bBr1
I I  M  I / I
2  B 2  2bBr 2  M  I / I
3  B3  2bBr 3  M 4  I B 4  / I 2bBr 4 

 I dC   I C1  I C 2  I C 3 I C 4 
          
1 2 3 4
Equation 3.6-8
 I A5   I A6 
   
M 5   I B5  / I 2bBr 5  M 6   I B 6  / I 2bBr 6
I C5  I C6 
     
5 6
The above equation can be simplified to the following:
 I dA  I  A1  I  A2  I  A3  I A4  I A5  I A6


 I dB  I  B1  I  B 2  I  B3  I B 4  I B 5  I B 6 Equation 3.6-9

 I dC  I C1  I C 2  I C 3  I C 4  I C 5  I C 6
The equation of calculating restraint current is:

 1
 
 I rA  2 I  A1  I  A2  I  A3  I  A4  I  A5  I  A6


 I rB 
1
2

I B1  I B 2  I B 3  I B 4  I B 5  I B 6 Equation 3.6-10

 1

 I rC  2 I C1  I C 2  I C 3  I C 4  I C 5  I C 6 

Where:
IAm, IBm, ICm are the secondary current of branch m (m=1, 2, 3, 4, 5, 6).
I'Am, I'Bm, I'Cm are corrected secondary current of branch m (m=1, 2, 3, 4, 5, 6).
3 IdA, IdB, IdC are differential currents.
IrA, IrB, IrC are restraint currents.
M1, M2, M3, M4, M5, M6 are matrixes of phase shifting of each branch of transformer respectively.
Its value is decided according to the vector group of transformer and please refers to “section
3.6.1.2” for details.
I2bBr1, I2bBr2, I2bBr3, I2bBr4, I2bBr5, I2bBr6 are rated secondary values of each branch of transformer
respectively.
Current compensation process is shown in the flowing figure by taken 2-winding transformer with
three-phase CT inputs for an example. In an ideal situation, the differential current (i.e.,
Id=I'_H+I'_L) should be zero during the normal operation of the transformer or an external fault
occurring.
*
HV side I_H I_L LV side

*
*
*
I'_H I'_L
PCS-978S
Phase shift/zero sequence Phase shift/zero sequence
current elimination (*M1) current elimination (*M2)
Magnitude compensation Magnitude compensation

(/I2bBr1) (/I2bBr2)
I''_H I''_L
Calculate differential current and restraint current
Figure 3.6-1 Current compensation calculation process
Where:
“I_H” and “I_L” are primary currents of HV and LV sides respectively.
“I'_H” and “I'_L” are secondary currents of HV and LV sides respectively.

“I''_H” and “I''_L” are secondary corrected currents of HV and LV sides respectively.
M1 and M2 are matrixes of phase shifting and zero-sequence current elimination of HV and LV
sides respectively.
I2bBr1 and I2bBr2 are rated secondary currents at HV and LV sides respectively.
The symbol “*” represents the polarity of CT. If current flowing into the
polarity of CT, the current direction is defined as forward direction.
To clarify the situation, three important operation conditions with ideal and matched measurement 3
quantities are considered.
1. Through-flowing current under undisturbed conditions or external fault:
I'_H flows into the protected zone, I'_L leaves the protected zone, according to the definition of
signs in above figure, therefore I'_H=–I'_L.
Moreover |I'_H|=|I'_L|
Id=|I'_H+I'_L|=|I'_H-I'_H|=0
Ir=(|I'_H|+|I'_L|)/2=(|I'_H|+|I'_H|)/2=|I'_H|
Differential current (Id) is far less than restraint current (Ir), and current differential protection does
not operate.
2. Internal short-circuit fault, infeed with equal currents each side:
The following applies I'_L=I'_H, moreover |I'_L|=|I'_H|
Id=|I'_H+I'_L|=|I'_H+I'_H|=2|I'_H|
Ir=(|I'_H|+|I'_L|)/2=(|I'_H|+|I'_H|)/2=|I'_H|
Differential current (Id) is two times of restraint current (Ir), and current differential protection
operates.
3. Internal short-circuit fault, infeed from one side only:
The following applies I'_L=0
Id=|I'_H+I'_L|=|I'_H+0|=|I'_H|
Ir=(|I'_H |+|I'_L|)/2=(|I'_H|+|0|)/2=|I'_H|/2
Differential current (Id) are two times of restraint current (Ir), and current differential protection
operates.
3.6.1.5 Biased Differential Element
1. Sensitive biased differential element

The currents for following calculation are the products of the actual secondary current of each side
multiplying its own correction coefficient. The sensitive biased differential element with low pickup
setting and restraint slope is much more sensitive for a slight internal fault. Four blocking elements,
CT saturation, inrush current, overexcitation and CT circuit failure (optional) have also been
included for the protection in order to prevent it from the unwanted operation during an external
fault.
I d  K 1  I r  I Pkp（I r  Knee1）
I d  K 2 （I r - Knee1） K 1  Knee1 I Pkp（Knee1  I r  Knee2）

3 I d  K 3 （I r - Knee2） K 2  ( Knee2  Knee1 )  K 1  Knee1  I Pkp（I r  Knee2）
Equation 3.6-11
m 
Id  I
i 1
i
1 m 
Ir   Ii
2 i 1
Where:
I d and I r are respectively the differential current and the restraint current.
I Pkp is the pickup setting of biased differential protection (i.e., [87T.I_Biased]).

“Knee1” and “Knee2” are respectively current settings of knee point 1 and knee point 2 (i.e.,
[87T.I_Knee1] and [87T.I_Knee2]). “K1”, “K2” and “K3” are three slopes of biased differential
protection. (i.e., [87T.Slope1], [87T.Slope2], [87T.Slope3], recommended values: [87T.Slope1]=0.2,
[87T.Slope2]=0.5 and [87T.Slope3]=0.75.)
Operation characteristic of sensitive biased differential element is shown below.

Differential current
K=2
[87T.I_Inst]
t
en
em
l el
6 tia
0. r en
K= ffe
di
ed
as
bi
[87T.Slope1] ve [87T.Slope3]
iti
ns
se
of
ea
ar
n
io
at
er
op
1.2 3
[87T.Slope2]
[87T.I_Biased] Restraint current

0.8
[87T.I_Knee1] [87T.I_Knee2]
Figure 3.6-2 Operation characteristic of sensitive biased differential element
2. Conventional biased differential element
Conventional biased differential element with higher setting and restraint coefficient comparing
with sensitive biased differential element is blocked only by an inrush current detection.
Conventional biased differential element provides faster operation for severe internal faults. Its
operation criterion is:
I d  1.2 p.u（
. I r  0.8 p.u）
.
I d  max(0.6,87T .Slopt 3  0.15) （I r -0.8 p.u.）（I r  0.8 p.u.） Equation 3.6-12
Conventional biased differential element can eliminate the influence of CT saturation during an
external fault and ensures reliable operation even if CT is saturated during an internal fault by
means of its biased characteristic.
The slop of conventional biased differential element takes the higher one
between “0.6” and “87T.Slope3-0.15”, and the knee point is fixed in
program.
Operation characteristic of conventional biased differential element is shown below.

K=2
[87T.I_Inst]
en al
lem on
t
l e nti
tia ve
ren con
iffe of
d d area
bia ation
K=max(0.6, 87T.Slope3-0.15)
se
er
op
3
1.2
Restraint current
0.8
Figure 3.6-3 Operation characteristic of conventional biased differential element
3.6.1.6 Instantaneous Differential Element
Instantaneous differential element for transformer is to accelerate the operation speed for
transformer's internal fault. The element has no blocking element but to guard that the setting
must be greater than the maximum inrush current. Instantaneous differential element shall
operate to clear the fault when any phase differential current is higher than its setting. Its
operation criterion is:
Id>[87T.I_Inst] Equation 3.6-13
Where:
Id is the maximum value of three phase differential currents.

F operation area of instantaneous
K=2 differential element
[87T.I_Inst]
of d
ea se
ar bia ent K=0.6
[87T.Slope1] n l
tio na elem
a
e r ti a lo ve
iti t
op ven nti e ns en
n r e s e m
co iffe of l el
d
at
n
ea ia
ar ent
io iffe
er ed d
r
[87T.Slope3]
3
E C p
o as
bi
D
1.2
[87T.Slope2]
[87T.I_Biased]
0.8 B Restraint current
A [87T.I_Knee2]
[87T.I_Knee1]
Figure 3.6-4 Operation characteristic of biased/instantaneous differential elements
The characteristic of internal faults is a straight line with the slope 2 (63.4°) in the operation
diagram (dash-dotted line K=2)
Point A shows normal operation of transformer.
Point B shows CT saturation.
Point C, D, E, and F indicate internal faults or external fault of transformer.
1. Sensitive biased differential element will send tripping signal monitored by CT saturation,
overexcitation, inrush current and CT circuit failure (optional). It can ensure sensitivity and
avoid the unwanted operation when CT is saturated during an external fault. Its operation
area is the tint shadow area in the figure above.
When a slight intern fault occurs, differential current rises not greatly and the operating point
moves from A to D into the tripping area of sensitive biased differential protection.
When an external fault occurs, the short-circuit current rise strongly, causing a correspondingly
high restraint current (2 times through-flowing current) with little differential current. After CT
reaches saturation (point B), a differential quantity is produced and the restraint quantity is
reduced. In consequence, the operating point may moves into the tripping area of sensitive biased
differential protection. Because CT saturation criterion is equipped, sensitive biased differential
protection will not maloperate even the fault point moves into the operation area.
2. Conventional biased differential element will send tripping signal monitored by inrush current
only. It eliminates the influence of transient and steady saturations of CT during an external
fault and ensures reliable operation even if CT is in saturation condition during an internal

fault by means of its biased characteristic. Its operation area is the deeper shadow area in the
figure above.
When an internal fault occurs, differential current rises greatly and the operating point moves to E
in the tripping area of conventional biased differential protection. (Only the second harmonic
criterion is adapted to distinguishing inrush current for blocking conventional biased differential
protection.)
3. Unrestrained instantaneous differential protection element will send tripping signal without
any blocking if differential current of any phase reaches its setting. Its operation area is over
the above two areas with the deepest dark shadow.
3 When a severe internal fault occurs, differential current rises sharply and the operating point
moves to F in the operation area of instantaneous differential element.
3.6.1.7 DPFC Biased Differential Element
DPFC biased differential protection is regardless of the load current and is sensitive to small
internal fault current within the transformer. Its performance against current transformer saturation
is also good. DPFC (Deviation of Power Frequency Component) is the power frequency
component of fault component, which is the differential value between the sampling value at this
time point and that at a cycle before.
DPFC biased differential element has the higher anti-CT saturation characteristic, the sensitivity of
which to slight inter-turn fault is maintained during normal operation of transformer. The sensitivity
of transformer differential protection is improved greatly when DPFC biased differential element is
enabled, especially in the situation inter-turn fault during heavy load operation.
200
100
-100
-200
0 20 40 60 80 100 120
Original Current
100
50
-50
-100
0 20 40 60 80 100 120
DPFC current
ΔI=I(K)-I(K-24)
I(k) is the sampling value at a point.
I(k-24) is the value of a sampling point before a cycle, 24 is the sampling points in one cycle.
From above figures, it is concluded that DPFC can reflect the sudden change of fault current at
the initial stage of a fault and has a perfect performance of fault detection. DPFC biased

differential protection reflects variation of load condition to perform a sensitive protection for the
transformer. Lab tests show that it is more sensitive than the biased differential element under the
heavy load condition. DPFC restraint current and differential current are phase-segregated. DPFC
biased differential element can be blocked by inrush current, overexcitation and CT circuit failure.
The operation criterion is as follows:
I d  0.2 p.u.
I d  1.25  I dt  I dth
I d  0.6  I r ( I r  2 p.u.) 3
Equation 3.6-14
I d  0.75  I r - 0.3 p.u.( I r  2 p.u.)
  
I d   I 1   I 2  ...   I m
m  m  m  
I r  Max  I ak ,   I bk ,   I ck 
 k 1 k 1 k 1 
Where:
  
 I ak ,  I bk ,  I ck are DPFC current of branch k of the transformer.
I dt is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold ( I dt ) is higher than the change of current under these conditions and hence the
element maintains stability.
I dth is fixed threshold internally.
I d and I r are DPFC differential current and DPFC restraint current respectively.
Because the calculation of restraint current is different between DPFC

biased differential element and biased differential protection, it is difficult to
test the characteristic at site, so we recommend qualitative function test
only at site.
Operation characteristic of DPFC biased differential element is shown below.

K=m
K=0.75
1.2p.u.
3 0.2p.u.
K=0.6
Restraint current
0.333p.u. 2p.u.
Figure 3.6-5 Operation characteristic of DPFC biased differential protection
The value of m is not greater than 1. For the phase with maximum restraint current, m is equal to 1,
and for other phases, m is less than 1.
DPFC biased differential element can detect a slight inter-turn fault of transformer more
sensitively than biased current differential element. During a slight inter-turn fault, fault current will
flow through transformer whether transformer is fed from one side or from both sides. Therefore,
following two typical situations (an external fault and a slight inter-turn fault) are given to show
differential and restraint current calculation.
During normal operation, Ia_HVS=1A∠0°, Ib_LVS=1A∠180°
1. A slight inter-turn fault: I'a_HVS=1.3A∠0°, I'b_LVS=1.1A∠180°, other phase are supposed

as zero
 Biased differential element:
Id=|I'a_HVS+I'b_LVS|
=|1.3A∠0°+1.1A∠180°|=0.2A
Ir=0.5x(|I'a_HVS|+|I'b_LVS|)
=0.5x(|1.3A∠0°|+|1.1A∠180°|)=1.2A
 DPFC biased differential element:
ΔId=|(I'a_HVS-Ia_HVS)+(I'b_LVS-Ib_LVS)|
=|(1.3A∠0°-1A∠0°)+(1.1A∠180°-1A∠180°)|=0.2A
ΔIr=max(|I'a_HVS-Ia_HVS|,|I'b_LVS-Ib_LVS|)
=max(|1.3A∠0°-1A∠0°|,|1.1A∠180°-1A∠180°|)=0.3A
Conclusion: DPFC biased differential element is more sensitive than biased differential element
during an internal fault.

2. An external fault: I'a_HVS=2A∠0°, I'b_LVS=2A∠180°, other phase are supposed as zero
 Biased differential element:
Id=|I'a_HVS+I'b_LVS|
=|2A∠0°+2A∠180°|=0A
Ir=0.5x(|I'a_HVS|+|I'b_LVS|)
=0.5x(|2A∠0°|+|2A∠180°|)=2A
 DPFC biased differential element:
ΔId=|(I'a_HVS-Ia_HVS)+(I'b_LVS-Ib_LVS)| 3
=|(2A∠0°-1A∠0°)+(2A∠180°-1A∠180°)|=0A
ΔIr=max(|I'a_HVS-Ia_HVS|, |I'b-_LVS-Ib_LVS|)
=max(|2A∠0°-1A∠0°|,|2A∠180°-1A∠180°|)=1A
Conclusion: DPFC biased differential element does not operate during an external fault.
3.6.1.8 Inrush Current Discrimination
The device provides optional inrush current distinguished principles: harmonic principle (second
harmonic and third harmonic) and waveform symmetry principle. The logic setting
[87T.Opt_Inrush_Ident] is used to select distinguished principle, second harmonic principle or
waveform symmetry principle. The discrimination of inrush current by third harmonics is
independent criterion, and is not controlled by the setting [87T.Opt_Inrush_Ident]. When an
internal fault occurs and CT goes to stable saturation, there are great third harmonic component in
CT secondary current. Because sensitive biased differential element has too high sensitivity, the
third harmonic criterion is only used to block sensitive biased differential element to prevent it from
maloperation when both [87T.Opt_Inrush_Indent] and [En_Hm3_Inrush] are set as “1”.
1. Inrush current discrimination based on harmonics
The second and third harmonics of differential current can be used to distinguish inrush current.
Its criteria are:
I d _ 2 nd  [ 87T .K _ Hm2 _ Inrus ]  I d_ist

Equation 3.6-15
I d _ 3 rd  [ 87T .K _ Hm3 _ Inrush ]  I d_1st
Where:
I d _ 2 nd and I d _ 3rd are the second and third harmonics of phase differential current respectively.
I d_ist is the fundamental component of corresponding phase differential current.

It is recommended to set [87T.K_Hm2_Inrush] as 0.15 and [87T.K_Hm3_Inrush] as 0.2.
2. Inrush current discrimination based on waveform symmetry principle
The differential current is basically the fundamental sinusoidal wave during a fault. When the
transformer is energized, plentiful harmonics will appear, and the waveform will be distorted,
interrupted and unsymmetrical. Wave symmetry principle is used to distinguish inrush current.
CT saturation characteristics make waveform unsymmetrical between the first half cycle and the
second half cycle. During internal faults, current waveform is sinusoidal wave, so two half cycles
of wave are almost symmetrical after a periodic component is eliminated (calculate the differential
of differential current in fact).
3 As shown in Figure 3.6-6, arc ABC is a cycle of typical waveform of differential current with a
periodic component. Flip the arc BC of second half cycle vertically to get the arc B'C', and then
move it forward half cycle to get the arc B''C''. The degree of symmetry of current wave is shown
as
S
K sym  Equation 3.6-16
S
Where:
X: arc AB
Y: arc B''C''
S+: are of X-Y
S-: are of X+Y
Figure 3.6-6 Schematic of waveform symmetry principle
For a differential current waveform, the area of X is almost equal to that of Y and the value of K sym
is almost 0. For an unsymmetrical waveform, the area of X is not equal to that of Y, so the value of
Ksym is a great value. Therefore, waveform of inrush current can be distinguished from the
waveform of internal fault according to the value of K sym.
Both waveform symmetry principle and second harmonic principle are based on current distortion

due to inrush current, and the only difference is the mathematical method. The second harmonic
principle is to calculate the percentage of second harmonic in differential current, but the
waveform symmetry principle is to calculate the percentage of even harmonic to total differential
current.
3.6.1.9 Inrush Blocking Mode
There are three optional blocking modes for inrush current, self-adaptive one-phase inrush
blocking one-phase differential element mode (self-adaptive 1Pblk1P mode), two-phase inrush
blocking three-phase differential element mode (2PBlk3P mode) and one-phase inrush blocking
three-phase differential element mode (1Pblk3P mode), by the logic setting
[87T.Opt_BlkMode_Inrush]. Self-adaptive blocking mode can enhance ability of differential
protection to avoid maloperation during transformer energization effectively and ensure high
3
speed of differential protection for faults under normal operation. The self-adaptive blocking mode
is recommended to be selected in the actual application.
1. Self-adaptive one-phase inrush blocking one-phase differential element mode (self-adaptive

1Pblk1P mode)
The device has an energizing detection element by current criterion (without additional breaker
position signal) to check whether the transformer is in the process of energization. Once the
transformer in the process of energization is detected, the following criterions are adopted to
improve the stability to avoid mal-operation caused by inrush current.
 Criterion 1
The device automatically decreases the restraint coefficient values of second harmonics and
wave distortion during the initial stage of transformer energization and with the passage of time
automatically increases those values which shall be not greater than corresponding values of
settings. This feature ensures biased differential element fast operation for transformer energized
on to a fault in addition to the inrush current blocking.
 Criterion 2
The device can be self-adaptive to enable “2PBlk3P” mode according to the comprehensive
characteristics of three-phase differential current. If inrush current is distinguished, then enables
“2PBlk3P” mode for short time, and then switches to phase-segregated blocking mode after a
period.
 Criterion 3
If the second harmonic percent of differential current used as auxiliary criteria continues to rise,
then biased differential element is kept being blocked.
2. Two-phase inrush blocking three-phase differential element mode (2PBlk3P mode)
When the inrush current is detected in any two-phase current, three-phase current differential
protection will be blocked.
3. One-phase inrush blocking three-phase differential element mode (1Pblk3P mode)

When the inrush current is detected in any phase current, three-phase current differential
protection will be blocked.
A list is given below to compare operation of differential protection in following situations.
It is supposed that three differential currents are Ida, Idb, and Idc.
Table 3.6-2 Comparison of different blocking modes
Case Harmonic current Mode 1 Mode 2 Mode 3

High harmonic component in Ida
1 High harmonic component in Idb Not operate Not operate Not operate
3 High harmonic component in Idc

Normal harmonic component in Ida
2 Normal harmonic component in Idb Operate Operate Operate
Normal harmonic component in Idc
High harmonic component in Ida Operate or not operate
3 High harmonic component in Idb according to differential Not operate Not operate
Normal harmonic component in Idc current waveform
High harmonic component in Ida
4 Normal harmonic component in Idb Operate Operate Not operate
Normal harmonic component in Idc
Mode 1: self-adaptive one-phase inrush blocking one-phase differential element mode
Mode 2: Two-phase inrush blocking three-phase differential element mode
Mode 3: One-phase inrush blocking three-phase differential element mode
For mode 1 in case 3, when blocking criterion 1, 2 and 3 of inrush current discrimination are all
released to differential element, differential element can operate. Otherwise, differential element
will be blocked if any of three blocking criterions blocks.
Case 4 is usually an internal fault, and blocking mode 2 can ensure differential protection operate
correctly if there is an internal fault in case 4. Case 3 may be an internal fault or inrush current,
and blocking mode 1 can distinguish through its perfect criteria, hence, it is recommended to use
blocking mode 1.
The following figure shows the logic of inrush current blocking differential protection.

SET [87T.Opt_BlkMode_Inrush=0]
SIG Transformer energization >=1

SIG Blocking criterion 1
&
&
SIG Flag_NoInrush_Harm &

>=1
SET [87T.Opt_Inrush_Ident]
& No Inrush (Phase A)
SIG Flag_NoInrush_Wave
&
No Inrush (Phase B)
3
SIG 87T.TrigDFR No Inrush (Phase C)
SIG Flag_NoInrush_Hm3 >=1

Only valid for sensitive biased
EN [87T.En_Hm3_Blk]
differential element
SIG No Inrush (Phase A) &

& >=1
SIG No Inrush (Phase B)

& >=1
Not block 87T
&
&
SIG No Inrush (Phase C)
&
>=1
&
>=1
>=1
SIG Transformer energization 100ms 0ms &
Figure 3.6-7 Logic of inrush current blocking current differential protection
Where:

“Flag_NoInrush_Harm” is the internal signal that means no inrush current is detected by the
harmonic principle.
“Flag_NoInrush_Wave” is the internal signal that means no inrush current is detected by the
waveform symmetry principle.
“Flg_NoInrush_Hm3” is the internal signal that means no inrush current is detected by the third
harmonic principle.
3.6.1.10 CT Saturation Detection
There are two kinds of CT saturation, i.e. transient CT saturation and stable CT saturation. If an
3 external fault or an internal fault occurs, CT primary current increases greatly and CT secondary
current consists of fundamental component, DC component and harmonic component. The
decaying DC component results in remanent magnetism in magnetic core, and with the
accumulation of remnant magnetism, CT goes into saturation state which is called transient CT
saturation. With the time passed, the DC component decays to zero almost and CT is still
saturated caused by AC excitation, which is called stable CT saturation.
According to tests in lab, it is found that the second harmonic component is greater than the third
harmonic component at the stage of CT transient saturation and the third harmonic is greater than
the secondary harmonic at the stage of CT stable saturation. Therefore, the second and third
harmonics both can be used to detect CT saturation.
In order to prevent an unwanted operation of biased differential element caused by transient or

steady state saturation of CT during an external fault, the second and third harmonics of
secondary current of individual CTs are used for the device to discriminate saturation of
three-phase CT. If CT saturation is detected, biased differential element will be blocked.
I  _ 2 nd  K_2nd  I _1st
or Equation 3.6-17
I  _ 3 rd  K _3rd  I _1st
Where:
I _1st is the fundamental component of one phase current, it won’t do CT saturation detection
unless the fundamental component is higher than the corresponding internal setting.
I  _ 2 nd is the secondary harmonic of the same phase current.
I  _ 3rd is the third harmonic of the same phase current.
K _2nd and K _3rd are fixed coefficients of secondary and third harmonics respectively.
If any harmonic of one phase current meets the above equation, it will be considered that it is CT
saturation to cause this phase differential current and biased differential element will be blocked.

Internal faults can be distinguished from external faults by differential protection through the
asynchronous method of differential and restraint, and it is needed that the saturation free time of
CT is no less than 4ms for internal faults to ensure differential protection operate correctly with the
added CT saturation criterion.
3.6.1.11 Overexcitation Detection
When a transformer is overexcited, the exciting current will increase sharply which may result in
an unwanted operation of differential protection. Therefore the overexcitation shall be
discriminated to block differential protection. The third or fifth harmonic of differential current can
be selected to determinate overexcitation.
Id_3rd/5th>[87T.K_Hm3/Hm5_OvExc]×Id_1st Equation 3.6-18

3
Where:
Id_1st is the fundamental component of differential current.
Id_3rd/5th is the third or fifth harmonic of differential current.
The fifth harmonic is recommended to be selected for overexcitation calculation.
The degree of overexcitation (overexcitation factor n) can is evaluated as follows:
U
n Equation 3.6-19
f
Where:
U and f are per unit value of voltage and frequency respectively.
The base value for calculating per unit value of voltage is rated secondary voltage value (phase
voltage) of the voltage transformer, and the base value for calculating per unit value of frequency
is rated frequency. During normal operation, n = 1.
If overexcitation factor is less than 1.4, biased differential element is blocked when the constant of
fifth or third harmonics is greater than [87T.K_Hm3/Hm5_OvExc] and this condition is judged as
overexcitation condition without damages to transformer. If overexcitation factor is greater than
1.4, biased differential element is no longer being blocked by overexcitation because transformer
is damaged in this situation.
3.6.1.12 Differential CT Circuit Supervision
1. Differential CT circuit abnormality
If the differential current in any phase is continually greater than the alarm setting [87T.I_Alm] over
10s, the differential current abnormality alarm [87T.Alm_Diff] will be issued, but this alarm will not
block differential protection.
2. Differential CT circuit failure

The following two cases are considered as CT circuit failure, and the device can discriminate at
which side CT circuit is failure by unbalanced currents. Differential CT secondary circuit failure
can be judged more accurately and reliably by adopting combined method of voltage and current.
 First case, if none of following four conditions is satisfied after the fault detector of biased
differential current, or biased residual differential current, or biased winding differential current
picks up, it will be judged as CT circuit failure and the alarm will be issued.
1) Negative-sequence voltage at any side is greater than 2%Upp (Upp is the secondary
phase-to-phase rated voltage).
2) Any phase current at any side increases after fault detector picks up.
3 3) The maximum phase current is greater than 1.1p.u. after the fault detector picks up.
4) DPFC element of any phase-to-phase voltage at any side picks up.
 If the alarm of differential CT circuit abnormality (i.e. [87T.Alm_Diff]) is issued and

negative-sequence current at one side is greater than 0.04 times maximum phase current at
the same side or greater than 0.1In, and then CT circuit failure will be judged.
3. Influence of CT circuit failure on differential protection
The alarm of CT circuit failure can be settable to block transformer differential protection, reactor
differential protection, restricted earth-fault protection and winding differential protection. The
alarm of CT circuit failure is latched once issued, it can be reset aumatically after the failure is
cleared (under the condition that the setting [En_AutoRecov_Alm_CTS] is set to be “1”), or it can
be reset manually when the setting [En_AutoRecov_Alm_CTS] is set to be “0”.
 Transformer's conventional biased differential element and instantaneous differential element

are always not blocked during CT circuit failure.
 Transformer's DPFC biased differential element is always blocked during CT circuit failure.
 Transformer's sensitive biased differential element will be blocked during CT circuit failure
when the logic setting [87T.En_CTS_Blk] set as “1”.
 Biased restricted earth-fault element will be blocked during CT circuit failure when the logic
setting [64REF.En_CTS_Blk] is set as “1”.
 Biased winding differential protection will be blocked during CT circuit failure when the logic
setting [87W.En_CTS_Blk] is set as “1”.
The operation time of biased differential element controlled by CT circuit

failure has additional 50ms delay than that of biased differential protection
not controlled by CT circuit failure.

87T
87T.in_I3P1 87T.On_Inst
87T.in_I3P2 87T.On_Biased
87T.in_I3P3 87T.On_DPFC
87T.in_I3P4 .
87T.in_I3P5 .
87T.in_I3P6 . 3
87T.Enable 87T.Ib_Th
87T.Block 87T.Ic_Th
3.6.3 I/O Signals

Table 3.6-3 Input signals of transformer differential protection

1 87T.in_I3P1 Three-phase current data input 1 for transformer current differential protection.
Input signal of enabling transformer current differential protection. It is triggered
7 87T.Enable
from binary input or programmable logic etc.
Input signal of blocking transformer current differential protection. It is triggered
8 87T.Block
from binary input or programmable logic etc.
Table 3.6-4 Output signals of transformer differential protection

1 87T.On_Inst Instantaneous differential element of transformer differential protection is enabled.
2 87T.On_Biased Biased differential element of transformer differential protection is enabled.
3 87T.On_DPFC DPFC differential element of transformer differential protection is enabled.
4 87T.Blocked_Inst Instantaneous differential element of transformer differential protection is blocked.
5 87T.Blocked_Biased Biased differential element of transformer differential protection is blocked.
6 87T.Blocked_DPFC DPFC differential element of transformer differential protection is blocked.
7 87T.Valid_Inst Instantaneous differential element of transformer differential protection is valid.
8 87T.Valid_Biased Biased differential element of transformer differential protection is valid.
9 87T.Valid_DPFC DPFC differential element of transformer differential protection is valid.
10 87T.St Transformer differential protection starts.


11 87T.St_Inst Instantaneous differential element of transformer differential protection starts.
12 87T.St_Biased Biased differential element of transformer differential protection starts.
13 87T.St_DPFC DPFC differential element of transformer differential protection starts.
14 87T.Op Transformer differential protection operates.
15 87T.Op.PhA Phase-A transformer differential protection operates.
16 87T.Op.Ph B Phase-B transformer differential protection operates.
17 87T.Op.Ph C Phase-C transformer differential protection operates.
18 87T.Op_Inst Instantaneous differential element of transformer differential protection operates.
Phase-A instantaneous differential element of transformer differential protection
19 87T.Op_Inst_A
3 operates.
Phase-B instantaneous differential element of transformer differential protection
20 87T.Op_Inst_B
operates.
Phase-C instantaneous differential element of transformer differential protection
21 87T.Op_Inst_C
operates.
22 87T.Op_Biased Biased differential element of transformer differential protection operates.
23 87T.Op_Biased_A Phase-A biased differential element of transformer differential protection operates.
24 87T.Op_Biased_B Phase-B biased differential element of transformer differential protection operates.
25 87T.Op_Biased_C Phase-C biased differential element of transformer differential protection operates.
26 87T.Op_DPFC DPFC differential element of transformer differential protection operates.
27 87T.Op_DPFC_A Phase-A DPFC differential element of transformer differential protection operates.
28 87T.Op_DPFC_B Phase-B DPFC differential element of transformer differential protection operates.
29 87T.Op_DPFC_C Phase-C DPFC differential element of transformer differential protection operates.
30 87T.Alm_Diff Differential current of transformer differential protection is abnormal.
31 87T.Alm_CTS CT secondary circuit of transformer differential protection is abnormal.
32 87T.Ida Phase-A differential current of transformer differential protection.
33 87T.Idb Phase-B differential current of transformer differential protection.
34 87T.Idc Phase-C differential current of transformer differential protection.
35 87T.Ira Phase-A restraint current of transformer differential protection.
36 87T.Irb Phase-B restraint current of transformer differential protection.
37 87T.Irc Phase-C restraint current of transformer differential protection.
38 87T.Ia_Th Threshold value of phase-A restraint current of transformer differential protection.
39 87T.Ib_Th Threshold value of phase-B restraint current of transformer differential protection.
40 87T.Ic_Th Threshold value of phase-C restraint current of transformer differential protection.

3.6.4 Logic
EN [87T.En_Inst] &
87T.On_Inst
SIG 87T.Enable
&
SIG 87T.Block >=1 87T.Blocked_Inst
SIG Fail_Device
&
87T.Valid_Inst
3
EN [87T.En_Biased] &
87T.On_Biased
SIG 87T.Enable
&
SIG 87T.Block >=1 87T.Blocked_Biased
SIG Fail_Device
&
87T.Valid_Biased
EN [87T.En_DPFC] &
87T.On_DPFC
SIG 87T.Enable
&
SIG 87T.Block >=1 87T.Blocked_DPFC
SIG Fail_Device
&
87T.Valid_DPFC
Figure 3.6-8 Logic of enabling transformer differential protection

SET Idmax>[87T.I_Inst] &

0 500ms 87T.Pkp_Inst
FD.Pkp
SIG 87T.Valid_Inst
SET Idmax>[87T.I_Biased] &

0 500ms 87T.Pkp_Biased
FD.Pkp
SIG 87T.Valid_Biased
SET ΔId>1.25ΔIdt+Idth &

0 500ms 87T.Pkp_DPFC
FD.Pkp
SIG 87T.Valid_DPFC
3
Figure 3.6-9 Pickup logic of transformer differential protection
SET Idmax>[87T.I_Inst] &

87T.Op_Inst
SIG 87T.Pkp_Inst
Figure 3.6-10 Logic diagram of instantaneous differential element
SIG Conventional 87T &

&
SIG Inrush current
SIG 87T.Pkp_Biased
>=1
SIG Sensitive 87T & 87T.Op_Biased
SIG CT saturation >=1
SIG Inrush current
SIG CT circuit failure & &

&
EN [87T.En_CTS_Blk]
SIG Overexcitation >=1
SIG U*/f*>1.4
SIG 87T.Pkp_Biased
Figure 3.6-11 Logic diagram of biased differential element

SIG DPFC 87T
SIG Inrush current

& &
SIG CT circuit failure 87T.Op_DPFC
SIG Overexcitation >=1
SIG U*/f*>1.4
SIG 87T.Pkp_DPFC
Figure 3.6-12 Logic diagram of DPFC biased differential element

3
SIG U2>2%Upp >=1
SIG DPFC line voltage pickup

>=1
>=1 &
SIG Any phase current increase >=1 &
CT circuit failure
SIG Ipmax>1.1p.u.
SIG 87T.Pkp_Inst
>=1
SIG 87T.Pkp_Biased
SIG 87T.Pkp_DPFC
SIG CT circuit failure &

T 0ms x.AlmH_CTS
SIG I2>0.04Ipmax or I2>0.1In
&
T 0ms 87T.Alm_CTS
Figure 3.6-13 Logic diagram of CT circuit failure alarm
Where:
Idmax is the maximum value of three phase differential currents.
“Upp” is phase-to-phase secondary rated voltage.
“T” is an internal time delay parameter, and it is floating and not open for user’s configuration.
3.6.5 Settings
Table 3.6-5 Settings of transformer differential protection
No. Name Range Unit Default Description

Pickup setting of biased differential
1 87T.I_Biased 0.050~5.000 p.u. 0.5
element
2 87T.I_Inst 0.050~20.000 p.u. 4 Current setting of instantaneous


Current setting of differential circuit
3 87T.I_Alm 0.050~1.500 p.u. 0.2
abnormality alarm
Current setting of knee point 1 for
4 87T.I_Knee1 0.100~3.500 p.u. 0.5
transformer differential protection
5 87T.I_Knee2 4.000~8.000 p.u. 6
6 87T.Slope1 0.000~0.900 - 0.2 Slope 1 of biased differential element
3 8 87T.Slope3 0.100~1.900 - 0.75 Slope 3 of biased differential element

Coefficient of second harmonics
9 87T.K_Hm2_Inrush 0.050~0.800 - 0.15
for inrush current detection
Coefficient of third harmonics for
10 87T.K_Hm3_Inrush 0.050~0.800 - 0.2
inrush current detection
Coefficient of third or fifth harmonic
11 87T.K_Hm3/Hm5_OvExc 0.050~0.800 - 0.25 for overexcitation detection
The recommended value is 0.25.
Enabled, Logic setting for enabling/disabling
12 87T.En_Inst - Disabled
Disabled instantaneous differential element
Logic setting for enabling/disabling
Enabled,
13 87T.En_Biased - Disabled conventional biased differential
Disabled
element
14 87T.En_DPFC - Disabled
Disabled DPFC biased differential element
Option of inrush current
WaveSym discrimination principle:
15 87T.Opt_Inrush_Ident - Hm2
Hm2 WaveSym: waveform symmetry
Hm2: Harmonic principle
Option of inrush blocking mode
Adaptive: self-adaptive one-phase
inrush blocking one-phase
Adaptive,
2PBlk3P: two-phase inrush
16 87T.Opt_BlkMode_Inrush 2PBlk3P, - Adaptive
blocking three-phase differential
1PBlk3P
element
1PBlk3P: one-phase inrush
element
Enabled,
17 87T.En_Hm3_Blk - Enabled the third harmonic blocking for
Disabled
inrush current
Option of third or fifth harmonic for
18 87T.Opt_Hm3/Hm5_OvExc Hm3, Hm5 - Hm5
overexcitation criterion


Hm3: third harmonic
Hm5: fifth harmonic
Enabled,
19 87T.En_CTS_Blk - Enabled blocking biased differential element
Disabled
during CT circuit failure
3.7 Restricted Earth Fault Protection (64REF)

Restricted earth fault protection (REF) is meant to protect a single winding of a power transformer,
and the protected winding must be earthed. In the case of delta windings, the winding must be
earthed by an earthing transformer, which must be electrically placed between the winding and 3
the current transformers. REF can be applied to protection of two-winding transformer,
three-winding transformer or auto-transformer.
REF is a kind of differential protection, so it calculates differential current and restrained current.
The differential current is a vector difference of the neutral current (i.e., current flowing in the
neutral conductor) and the residual current from the lines. For internal faults, this difference is
equal to the total earth fault current. REF operates on the fault current only, and is not dependent
on eventual load currents. This makes REF a very sensitive protection.
The symbol ”x” represents some side of transformer defined by user

through PCS-Studio software, which may be “HVS”, “MVS”, “LVS” by
default.

3.7.1.1 Overview
The difference between current differential protection and REF is that the first one is based on
adjusted phase current balance and the latter is based on balance of calculated residual current
and residual current from neutral CT.
Three groups of REF are for each side of a three-winding transformer at most. REF is not affected
by inrush current and the tap of transformer. CT Transient detection function based on the ratio of
residual current to positive current is adopted to eliminate the influence of difference of transient
characteristic to REF.

*
HV side I_H LV side
* *
3I0Cal'_H
Magnitude compensation
I'_HNP
REF at HV side I_HNP
*
3
Figure 3.7-1 Application for two-windings transformer with one CB at one side
HV side 1
* * *
I_H1
LV side
I_H2
3I0Cal'_H1 3I0Cal'_H2 * * *
HV side 2
Magnitude
compensation
REF at HV side I_HNP
Magnitude
compensation *
Magnitude
compensation
I'_HNP
Figure 3.7-2 Application for two-windings transformer with two CBs at one side

HV side
* * *
I_H
3I0Cal'_H I_M
*
MV side CW side
*
*
3I0Cal'_M
Magnitude
I_CW 3
LV side
compensation *
REF at HV side
Magnitude
compensation
I'_CW
Magnitude
compensation
Figure 3.7-3 Application for auto-transformer
Maximum 4 group of CTs and 1 neutral point CT inputs for REF, and the maximum current inputs
applied for an auto-transformer with two circuit breakers at HV and MV sides respectively.
Before REF of a side is put into service on site, polarity of neutral point CT
must have been checked by a primary injection test. Otherwise an
undesired operation may occur during an external earth fault.
REF's pickup criterion is:
I0d>[x.64REF.I_Biased] Equation 3.7-1
Where:
I0d is the residual differential current of some side.
If CTs used for REF have different primary rated values, the device will automatically adjust the
currents with respective correction ratio shown as below.
I1n
Klph   Klb / I 2 n and K lb  min(
I1n _ max
,4) Equation 3.7-2
I1n _ max I1n _ min

Where:
K1ph is the correction coefficient of the calculated side.
I1n is CT primary rated value at calculated side.
I2n is CT second rated value at calculated side.
I1n_min is minimum primary rated value among all CTs for REF.
I1n_max is maximum primary rated value among all CTs for REF.
This calculation method is to take the minimum CT primary rated value of all calculated sides as
3 the reference side. If the multiple of maximum CT primary rated value to minimum CT primary
rated value is greater than 4, then reference side shall be taken as 4 and other sides shall be
calculated proportionally. Otherwise, the reference side shall be taken as 1, and other sides will be
calculated proportionally.
The currents used in the following analysis have been corrected, that means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient (K1ph).
When selecting CT, the primary currents for each side muse follow the
I1n _ max
criterion:  128 , it is recommended that the ratio is smaller than 16.
I1n _ min
3.7.1.4 Calculate Differential and Restraint Current
The equation of calculating residual differential current is:
I 0d  K lph1  I 01  K lph 2  I 02  K lph3  I 03  K lph 4  I 04  K lphNP  I NP

1 2 3 4 5
  I 02
I 0 d  I 01   I 03
  I 04
  I NP
 Equation 3.7-3
Where:
I0d is the residual differential current.
I01, I02, I03, I04 are secondary values of calculated residual current at each side.
INP is secondary current at neutral point.
I'01, I'02, I'03, I'04 are secondary values of corrected calculated residual current at each side.

I'NP is the secondary corrected current at neutral point.
K1ph1, K1ph2, K1ph3, K1ph4 are corrected coefficients of amplitude compensation at each side.
K1phNP is corrected coefficient of amplitude compensation at neutral point.
The equation of calculating residual restraint current is:
I 0 r  Max（I 01 , I 02 , I 03 , I 04 , I 0 NP ） Equation 3.7-4
Where:
I0r is the residual restraint current.

3
Ia
*
A
Ib
*
B
Ic
* C
I_NP
*
3I0Cal' =I'c+I'b+I'a
I'_NP REF
Figure 3.7-4 REF principle
1. Through-flowing current under undisturbed conditions or external fault:
I_NP' flows into the protected zone from ground, 3I0Cal' leaves the protected zone, i.e. I_NP'
is negative according to the definition of signs in above figure, therefore I_NP'=-3I0Cal'.
3I0d=|3I0Cal'+I_NP'|=|3I0Cal'–3I0Cal'|=0
3I0r=Max(|3I0Cal'|, |I_NP'|)=|3I0Cal'|
No differential current, but restraint current corresponds to the through-flowing current, hence,
REF does not operate.
2. Internal short-circuit:
Assume that I_NP'=3I0Cal'
3I0d=|3I0Cal'+I_NP'|=2x|3I0Cal'|
3I0r=Max(|3I0Cal'|, |I_HNP) =|3I0Cal'|
Differential current are two times of restraint current and corresponding to the total fault, hence,
REF operates.

3.7.1.5 Operation Criterion
The operation criteria of REF protection are as follows:
3 I 0 d  [ x.64 REF .I _ Biased ]( 3 I 0 r  [ x.64 REF .I _ Knee ])
3 I 0 d  [ x.64 REF .Slope] （I 0 r - [ x.64 RF .I _ Knee ]） [ x.64 REF .I _ Biased ]
     Equation 3.7-5
3I 0d  I01  I 02  I 03  I 04  I 0 NP
3   
3 I 0 r  Max( I 01 , I 02 , I 03 , I 04 , I 0 NP )
 
Where:
3 I 0 d and 3 I 0 r are respectively the differential current and the restraint current at side x of
transformer.
   
I 01 , I 02 , I 03 and I 04 are the calculated residual currents at side x of transformer.

I 0 NP is the residual current from neutral point CT at side x of transformer.
3.7.1.6 Operation Characteristic

K=m
[x.64REF.Slope]
[x.64REF.I_Biased]
Restraint current
[x.64REF.I_Knee]
Figure 3.7-5 Operation characteristic of REF
The value of m is defined by the branch number for REF calculation. For example, there are two
branches at HV side (wye winding with neutral point earthed), so there are three branches

constitute REF of HV side and m is equal to 3.
3.7.1.7 Direction Criterion
In order to ensure the selectivity of restricted earth fault protection, direction criterion is also
available. The setting [x.64REF.En_Dir_Blk] is used to enable/disable the function of direction
criterion blocking REF. The direction criterion is based on the different direction characteristic of
neutral-point current 3I0_Neu and calculated residual current 3I0_Cal at an external earth fault
and an internal earth fault.
For an external earth fault, the neutral-point current 3I0_Neu and the calculated residual current
3I0_Cal have equal magnitude, but they are of approximately opposite directions.
3
For external fault
3I0_Cal
ROA (Relay Operate Angle)
3I0_Neu
ROA
Figure 3.7-6 Currents at an external earth fault
For an internal earth fault, the magnitudes of the two currents 3I0_Neu and 3I0_Cal may be
different, but their relative directions are within a certain angle range. The operation angle setting
[x.64REF.ROA] is equipped in the device, it will be judged as an internal earth fault and the
direction criterion will be released when the relative angle of the two currents is lower than the
setting.
For internal fault
ROA
3I0_Cal
3I0_Neu
ROA
Figure 3.7-7 Currents at an internal earth fault
3.7.1.8 CT Transient Characteristic Difference Detection
Non-identical CT characteristics can cause unbalance current. During phase-to-phase faults and

three-phase faults, the unbalance of three-phase CTs results in residual current which may lead to
maloperation of RFE. Therefore, positive-sequence current restraint blocking criterion is adopted
to prevent REF from maloperation in above mentioned conditions.
When the residual current of REF at each side is greater than 0 times positive-sequence current,
it is decided that zero-sequence current is caused by a fault and release REF. Positive-sequence
current restraint blocking criterion is showed below. This blocking criterion is ignored when neutral
point current is greater than the internal setting, whichever is greater.
I0>β0×I1 Equation 3.7-6
3 Where:
I0 is the zero-sequence current at a side.
I1 is its corresponding positive-sequence current.
β0 is a proportional constant and the value is 0.6
CT saturation detection function based on 2nd and 3rd harmonics is adopted to avoid
maloperation of REF during an external fault. Please refer to Section 3.6.1.10 for details.
3.7.1.10 CT Circuit Supervision
CT circuit supervision for REF is divided into two kinds: differential CT circuit abnormality without
the pickup of the fault detector and differential CT circuit failure with the pickup of the fault
detector.
 CT Circuit Abnormality
If the following operation formula is met for 10s, CT circuit abnormality alarm of REF will be issued
without blocking the protection.
The operation formula is as follows:
I0d>Max(0.2×[x.64REF.I_Biased], 0.1In) Equation 3.7-7
 CT Circuit Failure
Please refer to Section 3.6.1.12 for details.

64REF
x.64REF.in_I3P1 x.64REF.On
x.64REF.in_I3P2 x.64REF.Blocked
x.64REF.in_I3P3 x.64REF.Valid
x.64REF.in_I3P4 x.64REF.St
x.64REF.in_I1P x.64REF.Op
x.64REF.Enable x.64REF.Alm_Diff 3
x.64REF.Block x.64REF.Alm_CTS
x.64REF.3I0d
x.64REF.3I0r
x.64REF.I0_Th
3.7.3 I/O Signals

Table 3.7-1 Input signals of restricted earth-fault protection

1 x.64REF.in_I3P1 Three-phase current data input 1 for REF protection at x side of transformer.
5 x.64REF.in_I1P Residual current data input for REF protection at x side of transformer.
Input signal of enabling REF protection at x side of transformer. It is triggered from
6 x.64REF.Enable
binary input or programmable logic etc.
Input signal of blocking REF protection at x side of transformer. It is triggered from
7 x.64REF.Block
Table 3.7-2 Output signals of restricted earth-fault protection

1 x.64REF.On REF protection at x side of transformer is enabled.
2 x.64REF.Blocked REF protection at x side of transformer is blocked.
3 x.64REF.Valid REF protection at x side of transformer is valid.
4 x.64REF.St REF protection at x side of transformer starts.
5 x.64REF.Op REF protection at x side of transformer operates.
6 x.64REF.Alm_Diff Differential current of REF protection at x side of transformer is abnormal.
7 x.64REF.Alm_CTS CT secondary circuit of REF at x side of transformer is abnormal.
8 x.64REF.3I0d Residual differential current of REF protection at x side of transformer.
9 x.64REF.3I0r Residual restraint current of REF protection at x side of transformer.


10 x.64REF.3I0_Th Threshold of residual restraint current of REF protection at x side of transformer.
3.7.4 Logic
EN [x.64REF.En] &
x.64REF.On
SIG x.64REF.Enable
&
SIG x.64REF.Block >=1 x.64REF.Blocked
3 SIG Fail_Device
&
x.64REF.Valid
Figure 3.7-8 Logic of enabling restricted earth fault protection
SET I0d>[x.64REF.I_Biased] &

0 500ms &
x.64REF.Pkp
SIG x.64REF.On
FD.Pkp
SIG x.64REF.Valid
Figure 3.7-9 Pickup logic of restricted earth fault protection
SIG Flag_x.64REF &
SIG I0>β0×I1
&
SIG CT saturation
EN [x.64REF.En_CTS_Blk] x.64REF.St
SIG x.3I0Ext>0.04In >=1 &

[x.64REF.t_Op] 0ms x.64REF.Op
EN [x.64REF.En_NPCurr]
SIG x.64REF.Dir_op >=1
EN x.64REF.En_Dir_Blk
SIG x.64REF.Pkp
Figure 3.7-10 Logic diagram of restricted earth fault protection
Where:
“Flag_x.64REF” means that operation criterion of REF at side x is satisfied.

x.3I0Ext is the measured residual current at side x.
3.7.5 Settings
Table 3.7-3 Settings of restricted earth fault protection

1 x.64REF.I_Biased 0.050~5.000 In 0.5 Pickup setting of REF
2 x.64REF.I_Alm 0.050~1.500 In 0.2 Current setting of REF abnormality alarm
Knee point setting of REF
3 x.64REF.I_Knee 0.100~4.000 In 0.5
0.5In is recommended.
Percentage restraint coefficient of REF
4 x.64REF.Slope 0.200~0.750 - 0.5
0.5 is recommended.
3
5 x.64REF.ROA 45.000~90.000 deg 60 Operation angle setting
Time delay for REF
6 x.64REF.t_Op 0.000~20.000 s 0
Recommended value is zero.
7 x.64REF.En - Disabled
Disabled REF
8 x.64REF.En_NPCurr - Disabled
Disabled neutral current criterion
9 x.64REF.En_CTS_Blk - Enabled
Disabled blocking REF during CT circuit failure
Logic setting for enabling/disabling the
Enabled,
10 x.64REF.En_Dir_Blk - Disabled function of direction criterion blocking
Disabled
REF
3.8 Winding Differential Protection (87W)

When each side and common winding of auto-transformer are installed with three phase CTs,
winding differential protection can be equipped. Winding differential protection is based on
Kirchhoff's law, so inrush current has no effect on it. Winding differential protection consists of
phase winding differential protection and residual winding differential protection. Residual winding
differential protection adopts the calculated residual current of each side and common winding for
the protection calculation and three-phase CT polarity is easy to be checked. The operation
principle of which is similar to that of REF, but compared to REF, winding differential protection
can operate not only during internal earth faults but also during phase-to-phase faults.

3.8.1.1 Overview
Winding differential protection is based on Kirchhoff's first law and calculates differential currents
of electrical connection circuits including phase A, phase B phase C and residual differential
currents. Inrush current and tap change of the transformer have no effect on winding differential
protection. Winding differential protection has high sensitivity to internal earth faults because there
is no load current in the restraint current. Normally, winding differential protection is applied in
following two situations.

HV side
* * *
I_H
I_M
I'_H
*
MV side
*
CW side
*
I'_M
I_CW
3 Magnitude
LV side
compensation Winding
* * *
differential
Magnitude protection
compensation
Magnitude I'_CW
compensation
Figure 3.8-1 Winding differential protection applied to auto-transformer
HV side 1
* * * I_Bush
*
I_H1
LV side
*
HV side
*
I_H2
* * *
I'_H1
I'_H2 HV side 2
Magnitude
compensation Winding differential
protection
Magnitude
compensation
Magnitude
compensation
I'_HBush
Figure 3.8-2 Winding differential protection applied to stub differential protection
Where:
I_HBush is primary current value of bushing CT at HV side
I'_HBush is secondary current value of bushing CT at HV side
When winding differential protection is used as stub differential protection,

CT polarity must be checked. If CT polarity at CB side and bushing CT
polarity at some side of a transformer are both at busbar side, either of

them must be reversed by PCS-Studio.
The criterion of fault detector of winding differential protection is as follows.
Iwd>[87W.I_Biased] Equation 3.8-1
Where:
Iwd is winding differential current.

3
If CTs used by winding differential protection have differential primary rated value, then the current
compensation is carried out in the program automatically with parameters input. Following gives
the criteria of calculating correction coefficient.
I1n
K wph   K wb / I 2 n
I1n _ max
Equation 3.8-2
I1n _ max
K wb  min( ,4)
I1n _ min
Where:
Kwph is the correction coefficient of the calculated CT input.
I1n is the primary value of CT at calculated CT input.
I2n is the second value of CT at calculated CT input.
I1n_min is the minimum value among primary values of all CTs for winding differential protection.
I1n_max is the maximum value among primary values of all CTs for winding differential protection.
This calculation method is to take the minimum CT primary rating of all calculated CT inputs as
the reference. If the multiple of the maximum CT primary ratio to the minimum CT primary rating is
greater than 4, then reference shall be taken as 4 and others shall be calculated proportionally.
Otherwise, the reference shall be taken as 1, and others will be calculated proportionally.
The currents used in the following analysis have been corrected, which means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient (Kwph).
When selecting CT, the primary currents for each side muse follow the

I1n _ max
criterion:  128 , it is recommended that the ratio is smaller than 16.
I1n _ min
3.8.1.4 Calculate Differential and Restraint Current
The differential current is as follows.
 I wdA   I A1   I A2   I A3 
I  I  I  I 
3  wdB   K wph1     K wph 2     K wph 3   B 3  
B1 B 2
 I wdC   I C1   IC 2   IC 3 
       
 I wd 0   I 01   I 02   I 03 
1 2 3
Equation 3.8-3
 I A4   I A5 
I  I 
K wph 4     K wph 5   
B 4 B5
 IC 4   IC 5 
   
 I 04   I 05 
4 5
I wdA  I A1  I A2  I A3  I A4  I A5

I wdB  I B 1  I B 2  I B 3  I B 4  I B 5
Equation 3.8-4
I wdC  I C 1  I C 2  I C 3  I C 4  I C 5
  I 02
I wd0  I 01   I 03   I 04  I 05 
The restraint current is:
I wrA  Max( I A1 , I A2 , I A3 , I A4 , I A5 )

I wrB  Max( I B 1 , I B 2 , I B 3 , I B 4 , I B 5 )
Equation 3.8-5
I wrC  Max( I C 1 , I C 2 , I C 3 , I C 4 , I C 5 )
 , I 02
I wr 0  Max( I 01  , I 03 , I 04 , I 05 )
Where:
I wdA , I wdB , I wdC , I wd0 are respectively three phase and residual winding differential currents.
I wrA , I wrB , I wrC , I wr0 are secondary values of three phase restraint currents and neutral
restraint current respectively.

I Am , I Bm , I Cm and I 0 m are respectively secondary values of three phase currents and

calculated neutral current of branch m (m=1, 2, 3, 4, 5).
I Am , I B m , I C m and I 0 m are respectively secondary values of corrected three phase currents
and calculated residual current of branch m (m=1, 2, 3, 4, 5).
Kwph1, Kwph2, Kwph3, Kwph4, Kwph5 are corrected coefficients of each side for magnitude
compensation respectively.
3.8.1.5 Operation Criterion
The operation criteria of winding differential protection are as follows, and maximum 5 branches
3
are supported for the calculation.
I wd  [ 87W .I _ Biased ]( I wr  [ 87W .I _ Knee ])
I wd  [ 87W .Slope]  ( I wr  [ 87W .I _ Knee ])  [ 87W .I _ Biased ]( I wr  [ 87W .I _ Knee ])

Equation 3.8-6
    
I wd  I W 1  I W 2  I W 3  I W 4  I W 5
    
I wr  Max( I W 1 , I W 2 , I W 3 , I W 4 , I W 5 )
Where:
    
I W 1 , I W 2 , I W 3 , I W 4 and I W 5 are currents of five branches respectively.
I wd is winding differential current.
I wr is winding restraint current.
For protecting an autotransformer, a winding differential protection is

composed of three-phase currents of HV side, LV side and common
winding. When calculated residual currents of each branch are used for the
calculation, the winding differential protection (87W) becomes neutral
differential protection (87N) also called residual differential protection in the
following description.

3.8.1.6 Operation Characteristic
K=m
3 [87W.Slope]
[87W.I_Biased]
Restraint current
[87W.I_Knee]
Figure 3.8-3 Operating characteristic of winding differential protection
The value of m is defined by the branch number for winding differential protection. For example,
winding differential protection is applied for protecting an autotransformer including HV side, MV
side and common winding and m is equal to 3.
In order to prevent winding differential protection from undesired operation caused by transient or
steady state saturation of CT during an external fault, the second and third harmonics of
secondary current of individual CTs are used for the device to discriminate saturation of
three-phase CT. If CT saturation is detected, winding differential protection will be blocked.
1
I  _ 2 nd  K_2nd  I _1st & I  _ wd  [ 87W.I_Biased ]
2
or Equation 3.8-7
1
I  _ 3 rd  K _3rd  I _1st & I  _ wd  [ 87W.I_Biased ]
2
Where:
I _1st is the fundamental component of one phase current.
I  _ 2 nd is the secondary harmonic of the same phase current.
I  _ 3rd is the third harmonic of the same phase current.

K _2nd and K _3rd are fixed coefficients of secondary and third harmonics respectively.
If any harmonic of one phase current meets the above equation, it will be considered that it is CT
saturation to cause this phase differential current and winding differential protection will be
blocked.
3.8.1.8 CT Circuit Supervision
 CT Circuit Abnormality
If the following operation formula is met for 10s, CT circuit abnormality alarm of winding differential
protection will be issued without blocking the protection.
3
The operation criterion is as follows:
Iwd>max(0.2×[87W.I_Biased], 0.1In) Equation 3.8-8
Where:
In is CT rated secondary voltage.
 CT Circuit Failure
Please refer to Section 3.6.1.12 for details.
87W
87W.in_I3P1 87W.On_PhSeg
87W.in_I3P2 87W.On_REF
87W.in_I3P3 87W.Blocked_PhSeg
87W.in_I3P4 .
87W.in_I3P5 .
87W.Enable .
87W.Block 87W.Ic_Th
87W.3I0_Th
3.8.3 I/O Signals

Table 3.8-1 Input signals of winding differential protection

1 87W.in_I3P1 Three-phase current data input 1 for winding differential protection.


Input signal of enabling winding differential protection. It is triggered from binary input
6 87W.Enable
or programmable logic etc.
Input signal of blocking winding differential protection. It is triggered from binary input
7 87W.Block
or programmable logic etc.
Table 3.8-2 Output signals of winding differential protection
3 No. Output signal Description

1 87W.On_PhSeg Phase-segregated winding differential protection is enabled.
2 87W.On_REF Restricted earth-fault element of winding differential protection is enabled.
3 87W.Blocked_PhSeg Phase-segregated winding differential protection is blocked.
4 87W.Blocked_REF Restricted earth-fault element of winding differential protection is blocked.
5 87W.Valid_PhSeg Phase-segregated winding differential protection is valid.
6 87W.Valid_REF Restricted earth-fault element of winding differential protection is valid.
7 87W.St Winding differential protection starts.
8 87W.St_PhSeg Phase-segregated winding differential protection starts.
9 87W.St_REF Restricted earth-fault element of winding differential protection starts.
10 87W.Op Winding differential protection operates.
11 87W.Op_PhSeg Phase-segregated winding differential protection operates.
12 87W.Op_PhSeg_A Phase-A winding differential protection operates.
13 87W.Op_PhSeg_B Phase-B winding differential protection operates.
14 87W.Op_PhSeg_C Phase-C winding differential protection operates.
15 87W.Op_REF Restricted earth-fault element of winding differential protection operates.
16 87W.Alm_Diff Differential current of winding differential protection is abnormal.
17 87W.Alm_CTS CT secondary circuit of winding differential protection is abnormal.
18 87W.Ida Phase-A differential current of winding differential protection.
19 87W.Idb Phase-B differential current of winding differential protection.
20 87W.Idc Phase-C differential current of winding differential protection.
21 87W.3I0d Residual differential current of winding differential protection.
22 87W.Ira Phase-A restraint current of winding differential protection.
23 87W.Irb Phase-B restraint current of winding differential protection.
24 87W.Irc Phase-C restraint current of winding differential protection.
25 87W.3I0r Residual restraint current of winding differential protection.
26 87W.Ia_Th Threshold of phase-A restraint current of winding differential protection.
27 87W.Ib_Th Threshold of phase-B restraint current of winding differential protection.
28 87W.Ic_Th Threshold of phase-C restraint current of winding differential protection.
29 87W.3I0_Th Threshold of residual restraint current of winding differential protection.

3.8.4 Logic
EN [87W.En_PhSeg] &
87W.On_PhSeg
SIG 87W.Enable
&
SIG 87W.Block >=1 87W.Blocked_PhSeg
SIG Fail_Device
&
87W.Valid_PhSeg
3
EN [87T.En_REF] &
87W.On_REF
SIG 87W.Enable
&
SIG 87W.Block >=1 87W.Blocked_REF
SIG Fail_Device
&
87W.Valid_REF
Figure 3.8-4 Logic of enabling winding differential protection
SET Iwd>[87W.I_Biased] &

0 500ms 87W.Pkp_PhSeg
FD.Pkp
SIG 87W.Valid_PhSeg
SET I0d>[87W.I_Biased] &

0 500ms 87W.Pkp_REF
FD.Pkp
SIG 87W.Valid_REF
Figure 3.8-5 Pickup logic of transformer differential protection

SIG 87W.Flag_DIFF
& &
SIG CT Staturation [87W.t_Op] 0ms 87W.Op_PhSeg
EN [87W.En_CTS_Blk]
SIG 87W.Pkp_PhSeg
SIG I0>β0×I1 &
3 SIG 87W.Flag_DIFF
& &
[87W.t_Op] 0ms
SIG CT Staturation 87W.Op_REF
EN [87W.En_CTS_Blk]
SIG 87W.Pkp_REF
Figure 3.8-6 Logic diagram of winding differential protection
Where:
“87W.Flag_DIFF” means that the operation criterion of winding differential protection is satisfied.
3.8.5 Settings
Table 3.8-3 Settings of winding differential protection

Pickup setting of biased winding differential
1 87W.I_Biased 0.100~5.000 In 0.5
protection
Current setting of winding differential protection
2 87W.I_Alm 0.050~1.500 In 0.2
abnormality alarm
Knee point setting of biased winding
3 87W.I_Knee 0.100~4.000 In 0.5
differential protection.
Percentage restraint coefficient of biased
4 87W.Slope 0.100~0.900 - 0.5
winding differential protection
5 87W.t_Op 0.000~20.000 s 0 Time delay for winding differential protection
Enabled,
6 87W.En_PhSeg - Disabled phase-segregated winding differential
Disabled
protection
Enabled, Logic setting for enabling/disabling residual
7 87W.En_REF - Disabled
Disabled winding differential protection
Logic setting for enabling/disabling blocking
Enabled,
8 87W.En_CTS_Blk - Enabled winding differential protection during CT circuit
Disabled
failure

3.9 Overexcitation Protection (24)

Overexcitation results from excessive applied voltage, possibly in combination with below-normal
frequency. Such condition may occur when a unit is on load, but are more likely to arise when it is
on open circuit, or at a loss of load occurrence. Transformers directly connected to generators are
in particular danger to experience overexcitation condition.
During overexcitation, field current of transformer rises greatly to cause excessive heating and
severe damage. The transformer, working magnetic flux density near the knee point, is subject to
overexcitation. Frequency range for normal operation is 45~55Hz for 50Hz working frequency of
power system and 55~65Hz for 60Hz working frequency of power system.
Overexcitation protection can be configured at any side of transformer through PCS-Studio, and it
3
is recommended to be equipped at the side without OLTC.

Overexcitation protection consists of two stages definite-time overexcitation protection and one
stage inverse-time overexcitation protection for trip purpose or alarm purpose. The voltage for
protection calculation is RMS of three phase voltages and not affected by frequency fluctuation.
Overexcitation inverse-time curve is sectional linear curve, which has high adaptability.
The overexcitation degree can be reflected by overexcitation multiple which is calculated by

voltage and frequency, according to the following equation.
n=U*/f* Equation 3.9-1
Where:
U* and f* are per unit value of voltage and frequency respectively.
The base value for calculating per unit value of voltage is secondary voltage corresponding to
primary voltage of one side of transformer, and the base value for calculating per unit value of
frequency is rated frequency. Hence, under normal operation, n should be equal to 1.
For example, overexcitation protection is equipped at HV side, primary voltage of HV side is

525kV (i.e., [HVS.U1n_Tr]=525kV) and voltage transformer ratio is 500kV/100V. The base value
for calculating per unit value of voltage is equal to:
525
 62.62V
500
3
100
This base voltage calculation is carried out in the device and users need not calculate VT ratio
when configure settings.
1. Definite-time operation criterion:
U*/f*>[24DTn.K_Set] Equation 3.9-2

Inverse-time overexcitation protection realizes inverse-time characteristic by linear processing on

given inverse-time operation characteristic, obtaining overexcitation multiple by calculation, and
getting the corresponding time delay by sectional linear insertion. It reflects the heat accumulation
and radiation.
Several groups of setting point with independent settings can be configured for simulating the
inverse-time operation characteristics curve and this protection can satisfy overexcitation
requirements of various transformers.
Following figure shows inverse-time characteristic of overexcitation protection.
3 U*/f*
n0
n1
n2
n3
n4
n5
n6
n7
n8
n9
t (s)
0 t0 t1t2 t3 t4 t5 t6 t7 t8 t9
Figure 3.9-1 Inverse-time characteristic of overexcitation protection
The main harm of overexcitation to transformer is overheat, so accumulation method is adopted

and accumulate the time delay according to curve time corresponding to calculated overexcitation
multiple. When accumulated time delay is greater than the operating time delay, inverse-time
overexcitation protection operates. Dissipating process is also simulated, when overexcitation
multiple is less than the minimum overexcitation multiple setting, the accumulated value
decreases to 0 gradually. If overexcitation protection operates and overexcitation condition
disappears, thermal accumulation value decreases to 0 in 10s.
Overexcitation multiple comprises overexcitation information at current instant and also

overexcitation information integrated over various time intervals from its beginning.
Inverse-time characteristic curve can be specified by several overexcitation multiple settings, and
the relation among various settings of n and t are:
n0 > n1 > n2 >n3 > n4 > n5 > n6 > n7 > n8 > n9
t0 < t1 < t2 < t3 < t4 < t5 < t6 < t7 < t8 < t9

24DT1
24DT1.OvExc 24DT1.On
24DT1.Enable 24DT1.Blocked
24DT1.Block 24DT1.Valid
24DT1.St
24DT1.Op
3
24DT2
24DT2.OvExc 24DT2.On
24DT2.Enable 24DT2.Blocked
24DT2.Block 24DT2.Valid
24DT2.St
24DT2.Alm
24IDMT
24IDMT.OvExc 24IDMT.On
24IDMT.Enable 24IDMT.Blocked
24IDMT.Block 24IDMT.Valid
24IDMT.St
24IDMT.Op
24IDMT.Alm
24IDMT.ThermAccu
3.9.3 I/O Signals

Table 3.9-1 Input signals of overexcitation protection

Measurement data (including frequency and voltage) required by stage i of
1 24DTi.OvExc
definite-time overexcitation protection. (i=1, 2)
Input signal of enabling stage i of definite-time overexcitation protection. It is
2 24DTi.Enable
triggered from binary input or programmable logic etc. (i=1, 2)
Input signal of blocking stage i of definite-time overexcitation protection. It is
3 24DTi.Block
triggered from binary input or programmable logic etc. (i=1, 2)
Measurement data (including frequency and voltage) required by inverse-time
4 24IDMT.OvExc
overexcitation protection.


Input signal of enabling inverse-time overexcitation protection. It is triggered from
5 24IDMT.Enable
Input signal of blocking inverse-time overexcitation protection. It is triggered from
6 24IDMT.Block
Table 3.9-2 Output signals of overexcitation protection

1 24DTi.On Stage i of definite-time overexcitation protection is enabled. (i=1, 2)
2 24DTi.Blocked Stage i of definite-time overexcitation protection is blocked. (i=1, 2)
3 3 24DTi.Valid Stage i of definite-time overexcitation protection is valid. (i=1, 2)

4 24DTi.St Stage i of definite-time overexcitation protection starts. (i=1, 2)
5 24DT1.Op Stage 1 of definite-time overexcitation protection operates to trip.
6 24DT2.Alm Stage 2 of definite-time overexcitation protection operates to alarm.
7 24IDMT.On Inverse-time overexcitation protection is enabled.
8 24IDMT.Blocked Inverse-time overexcitation protection is blocked.
9 24IDMT.Valid Inverse-time overexcitation protection is valid.
10 24IDMT.St Inverse-time overexcitation protection starts
11 24IDMT.Op Inverse-time overexcitation protection operates to trip.
12 24IDMT.Alm Inverse-time overexcitation protection operates to alarm.
Thermal state of inverse-time overexcitation protection. When the value is “100%”,
13 24IDMT.ThermAccu
inverse-time overexcitation protection operates.
3.9.4 Logic
EN [24DT1.En] &
24DT1.On
SIG 24DT1.Enable
&
SIG 24DT1.Block >=1 24DT1.Blocked
SIG Fail_Device
&
24DT1.Valid
EN [24DT2.En] &
24DT2.On
SIG 24DT2.Enable
&
SIG 24DT2.Block >=1 24DT2.Blocked
SIG Fail_Device
&
24DT2.Valid

EN [24IDMT.En] &
24IDMT.On
SIG 24IDMT.Enable
&
SIG 24IDMT.Block >=1 24IDMT.Blocked
SIG Fail_Device
&
24IDMT.Valid
Figure 3.9-2 Logic of enabling overexcitation protection

3
SET U*/f*>[24DT1.K_Set]
SIG 24DT1.Valid &

0 500ms 24DT1.Pkp
FD.Pkp
EN x.En_VT
BI x.BI_En_VT
SIG 24DT2.Valid &

0 500ms 24DT2.Pkp
EN x.En_VT
BI x.BI_En_VT
SET U*/f*>[24IDMT.Kn_Set]
SIG 24IDMT.Valid &

0 500ms 24IDMT.Pkp
FD.Pkp
EN x.En_VT
BI x.BI_En_VT
Figure 3.9-3 Pickup logic of overexcitation protection
SIG 24DT1.Pkp &

[24DT1.t_Op] 0ms 24DT1.Op
24DT1.St
SIG 24DT2.Pkp &

[24DT2.t_Alm] 0ms 24DT2.Alm
24DT2.St
Figure 3.9-4 Logic diagram of definite-time overexcitation protection

24IDMT.St
SIG 24IDMT.Pkp
&
SIG U*/f*>[24IDMT.Kn_Set] & IDMT 24IDMT.Op
24IDMT.St
EN [24IDMT.En_Trp]
&
SIG U*/f*>[24IDMT.Kn_Set] & IDMT* 24IDMT.Alm
EN [24IDMT.En_Alm]
Figure 3.9-5 Logic diagram of inverse-time overexcitation protection
3 Where, IDMT* means that the time delay of inverse-time overexcitation protection for alarm
purpose equals to [24IDMT.K_Alm] of the time delay of inverse-time overexcitation protection for
trip purpose.
3.9.5 Settings
Table 3.9-3 Settings of overexcitation protection

It is used to set reference voltage of
overexcitation calculation, and it is usually
1 24Cal.U1n 0.000~2000.000 kV 220
set as primary rated voltage at calculated
side of transformer
Voltage option between phase voltage
and phase-to-phase voltage for
2 24Cal.Opt_Up/Upp Up, Upp - Up calculation of overexcitation protection
Up: phase voltage
Upp: phase-to-phase voltage
Multiple setting of stage 1 of definite-time
3 24DT1.K_Set 1.000~1.600 - 1.3
overexcitation protection for trip purpose
Time delay setting of stage 1 of
4 24DT1.t_Op 0.100~9999.000 s 1 definite-time overexcitation protection for
trip purpose
Logic setting for enabling/disabling stage
Enabled,
5 24DT1.En - Disabled 1 of definite-time overexcitation protection
Disabled
for trip purpose
6 24DT2.K_Set 1.000~1.600 - 1.3 overexcitation protection for alarm
purpose
7 24DT2.t_Alm 0.100~9999.000 s 1 definite-time overexcitation protection for
alarm purpose
Logic setting of enabling/disabling stage 2
Enabled,
8 24DT2.En - Disabled of definite-time overexcitation protection
Disabled
for alarm purpose


Highest-limit multiple setting of
9 24IDMT.K0_Set 1.000~1.700 - 1.7
inverse-time overexcitation protection: n0
Time delay setting corresponding to
10 24IDMT.t0_Op 0.100~9999.000 s 1
highest-limit setting: t0
Multiple setting 1 of inverse-time
11 24IDMT.K1_Set 1.000~1.700 - 1.65
overexcitation protection: n1
12 24IDMT.t1_Op 0.100~9999.000 s 2
multiple setting 1: t1
13 24IDMT.K2_Set 1.000~1.700 - 1.6
overexcitation protection: n2 3
14 24IDMT.t2_Op 0.100~9999.000 s 5
15 24IDMT.K3_Set 1.000~1.700 - 1.5
16 24IDMT.t3_Op 0.100~9999.000 s 10
17 24IDMT.K4_Set 1.000~1.700 - 1.4
18 24IDMT.t4_Op 0.100~9999.000 s 20
19 24IDMT.K5_Set 1.000~1.700 - 1.3
20 24IDMT.t5_Op 0.100~9999.000 s 50
21 24IDMT.K6_Set 1.000~1.700 - 1.25
22 24IDMT.t6_Op 0.100~9999.000 s 100
23 24IDMT.K7_Set 1.000~1.700 - 1.2
24 24IDMT.t7_Op 0.100~9999.000 s 300
25 24IDMT.K8_Set 1.000~1.700 - 1.15
26 24IDMT.t8_Op 0.100~9999.000 s 600
Lowest-limit multiple setting of
27 24IDMT.K9_Set 1.000~1.700 - 1.13
inverse-time overexcitation: n9
28 24IDMT.t9_Op 0.100~9999.000 s 1000
lowest-limit multiple setting: t9
Coefficient of time delay of inverse-time
29 24IDMT.K_Alm 0.500~1.000 - 0.7 overexcitation protection for alarm
purpose


Cooling time of inverse-time
30 24IDMT.t_Cooling 0.100~9999.000 s 10
Enabled,
31 24IDMT.En_Trp - Disabled inverse-time overexcitation protection for
Disabled
trip purpose
Enabled,
32 24IDMT.En_Alm - Disabled inverse-time overexcitation protection for
Disabled
alarm purpose
3
Please input the corresponding values of selected 10 points of
overexcitation curve of transformer to the device and the values of 10
points are distributed averagely.
Inverse-time overexcitation protection is set with reference to the curve

given by the transformer manufactory. The relation among all settings of
inverse-time overexcitation protection is:
[24IDMT.K9_Set]<[24IDMT.K8_ Set]<…<[24IDMT.K1_Set]<[24IDMT.K0_
Set]
[24IDMT.t0_Op]<[ 24IDMT.t1_ Op]<…<[24IDMT.k8_ Op] <[24IDMT.t9_ Op]
3.10 Phase Overcurrent Protection (50/51P, 67P)

Phase overcurrent protection is widely used in power systems. It can be used as main protection
of the feeder, and can also be used as backup protection for power equipment such as
transformers, reactors, and motors. When a fault occurs in the system, a fault current will be
generated and phase overcurrent protection can reflect the increase of the fault current.

through PCS-Studio software, which may be “HVS”, “MVS”, “LVS”, “LVS2”,
“CWS” by default.
The device can provide 6 stages of phase overcurrent protection with independent logic by default.
Each stage can be independently set as definite-time characteristics or inverse-time
characteristics. The dropout characteristics can be set as instantaneous dropout, definite-time
dropout or inverse-time dropout. It can be chosen whether it is blocked by voltage control element
or harmonic control element. The direction control element can be set as no direction, forward
direction and reverse direction. Phase overcurrent protection picks up when the current exceeds
the setting, and operates after a certain time delay. Once the fault disappears, phase overcurrent

protection will dropout.
Phase overcurrent protection can operate to trip or alarm and can be enabled or disabled via the
settings or the signals, for some specific applications, phase overcurrent protection needs to be
blocked by the external signal, so the device provides an input signal to be used to block phase
overcurrent protection.
EN [x.50/51Pi.En] &
x.50/51Pi.On
SIG x.50/51Pi.Enable
&
SIG x.50/51Pi.Block >=1 x.50/51Pi.Blocked 3
SIG Fail_Device
&
x.50/51Pi.Valid
Figure 3.10-1 Logic of enabling phase overcurrent protection
The pickup logic of phase overcurrent protection is shown in Figure 3.10-2:
SET x.Ia>0.95×[x.50/51Pi.I_Set]
>=1
SET x.Ib>0.95×[x.50/51Pi.I_Set] &
0 500ms &
SET x.Ic>0.95×[x.50/51Pi.I_Set]
x.50/51Pi.Pkp
SIG x.50/51Pi.On
SIG x.50/51Pi.Valid
&
FD.Pkp
SET [x.50/51Pi.Opt_Trp/Alm]=Alm
Figure 3.10-2 Pickup logic of phase overcurrent protection
3.10.1.1 Voltage Control Element
When a fault occurs at the remote end of a feeder, the fault current is relatively small, so the
voltage control element can be adopted to increase the sensitivity for this kind of fault. It can be
enabled or disabled via the setting [x.50/51Pi.En_Volt_Blk] (i=1~6). If VT circuit supervision is
enabled and the setting [x.50/51P.En_VTS_Blk] is set as “Enabled”, the device will issue an alarm
signal "VTS.Alm" when VT circuit fails, and voltage control element will be blocked. If voltage
control element is not enabled, phase overcurrent protection will not effected by VT circuit failure.
The corresponding relationship between each phase and voltage control element is as follows.
Voltage criterion Phase A Phase B Phase C

x.Uab<[x.50/51P.VCE.Upp] x.Uab<[x.50/51P.VCE.Upp] x.Ubc<[ x.50/51P.VCE.Upp]
Phase-to-phase
x.Uca<[x.50/51P.VCE.Upp] x.Ubc<[x.50/51P.VCE.Upp] x.Uca<[ x.50/51P.VCE.Upp]
Negative-sequence x.U2>[x.50/51P.VCE.U2] x.U2>[x.50/51P.VCE.U2] x.U2>[x.50/51P.VCE.U2]

x.U0_Cal>[x.50/51P.VCE.3 x.U0_Cal>[x.50/51P.VCE.3 x.U0_Cal>[x.50/51P.VCE.3

Zero-sequence
U0] U0] U0]
The relationship among phase-to-phase criterion, negative-sequence criterion and zero-sequence

criterion is "OR". The logic of voltage control element is shown in Figure 3.10-3.
EN [x.50/51P.En_VTS_Blk] &
>=1
3 SIG x.VTS.Alm
>=1
SIG x.Uab, x.Ubc, x.Uca criterion
Voltage
& x.50/51P.VCE.Op
SIG x.U2, x.U0_Cal
BI x.BI_En_VT
EN [x.En_VT]
Figure 3.10-3 Logic of voltage control element
3.10.1.2 Direction Control Element
Ua
[x.50/51P.DIR.phi_Min_Fwd]
Non-operating Ia
area
[x.50/51P.DIR.phi_Max_Rev] Operating area in

forward direction
[x.50/51P.DIR.RCA]
Operating area in
reverse direction
[x.50/51P.DIR.phi_Max_Fwd]
[x.50/51P.DIR.phi_Min_Rev] Non-operating
area
Figure 3.10-4 Operating characteristics of the direction element

In order to ensure the selectivity of phase overcurrent protection, direction control element is also
available. The setting [x.50/51Pi.Opt_Dir] (i=1~6) is used to select the direction characteristics for
each stage of phase overcurrent protection: no direction, forward direction and reverse direction
are selectable. Takes the phase A fault as an example, the setting
[x.50/51P.DIR.Opt_PolarizedVolt] is set as "Up", its operating characteristics is shown in Figure
3.10-4. The principle of phase B and phase C is the same. If positive-sequence voltage or
phase-to-phase voltage is used as polarized voltage, the operating characteristics are the same.
The operation boundary of the forward direction element can be set by

[x.50/51P.DIR.phi_Min_Fwd] and [x.50/51P.DIR.phi_Max_Fwd]. The operation boundary of the
reverse direction element can be set by [x.50/51P.DIR.phi_Min_Rev] and
[x.50/51P.DIR.phi_Max_Rev]. 3
The polarized voltage is selectable by the setting [x.50/51P.DIR.Opt_PolarizedVolt]. The following
table shows the relationship among the operating current, the polarized voltage and the
polarization mode.
Direction criterion
Polarization Faulty Operating
Polarized voltage Angle difference
mode phase current
Phase-A Positive-sequence
Phase A Angle_A=Angle(U1)-Angle(Ia)-RCA
current Ia voltage
Positive-sequence Phase-B Positive-sequence
Phase B Angle_B=Angle(U1)-Angle(Ib)-RCA-120º
voltage polarized current Ib voltage
Phase-C Positive-sequence
Phase C Angle_C=Angle(U1)-Angle(Ic)-RCA+120º
current Ic voltage
Phase-A Phase-to-phase
Phase A Angle_A=Angle(Ubc)-Angle(Ia)-RCA+90º
current Ia voltage Ubc
Phase-to-phase Phase-B Phase-to-phase
Phase B Angle_B=Angle(Uca)-Angle(Ib)-RCA+90º
voltage polarized current Ib voltage Uca
Phase-C Phase-to-phase
Phase C Angle_C=Angle(Uab)-Angle(Ic)-RCA+90º
current Ic voltage Uab
Phase-A Phase-to-ground
Phase A Angle_A=Angle(Ua)-Angle(Ia)-RCA
current Ia voltage Ua
Phase-to-ground Phase-B Phase-to-ground
Phase B Angle_B=Angle(Ub)-Angle(Ib)-RCA
voltage polarized current Ib voltage Ub
Phase-C Phase-to-ground
Phase C Angle_C=Angle(Uc)-Angle(Ic)-RCA
current Ic voltage Uc
The calculation of direction control element needs to judge the voltage threshold and the current
threshold. The direction judgement can be executed only when both the voltage and the current
are greater than the threshold value. For different polarization mode, the selected voltage and
current, and their threshold value are also different, the specific principles are:
Polarized voltage Minimum operating current Minimum operating voltage

Phase-to-phase voltage Phase current Phase-to-phase voltage

Phase-to-ground voltage Phase current Phase-to-ground voltage

Positive-sequence voltage Phase current Positive-sequence voltage
The memorized characteristics of direction control element can eliminate the dead zone for close
up three-phase short-circuit fault. When the polarized voltage is less than the minimum operating
voltage setting [x.50/51P.DIR.U_Min], the positive-sequence voltage before two cycles is used to
judge the direction. The polarized voltage will not be used to judge the direction until it is greater
than [x.50/51P.DIR.U_Min].The logic of forward direction element and reverse direction element
are shown in Figure 3.10-5.
EN [x.50/51P.DIR.En_VTS_Blk] &
3
>=1
SIG x.VTS.Alm
SIG Three-phase currents & >=1

Forward direction
x.50/51P.DIR.FwdDir.Op
SIG Three-phase voltages
criterion
SIG Memorized U1
SET [x.50/51P.DIR.Opt_PolarizedVolt]
BI x.BI_En_VT &
EN x.En_VT
EN [x.50/51P.DIR.En_VTS_Blk] &
>=1
SIG x.VTS.Alm
SIG Three-phase currents & >=1

Reverse direction
x.50/51P.DIR.RevDir.Op
SIG Three-phase voltages
criterion
SIG Memorized U1
SET [x.50/51P.DIR.Opt_PolarizedVolt]
BI x.BI_En_VT &
EN x.En_VT
Figure 3.10-5 Logic of forward and reverse direction element
Where:
Memorized U1: the positive-sequence memory voltage, it refers to the positive-sequence voltage

of two cycles before the polarized voltage is less than the minimum operating voltage setting
[50/51P.DIR.U_Min], and it is calculated from the three-phase voltage.
3.10.1.3 Harmonic Control Element
When the transformer is energized with no-load, the inrush current may be generated, which may
cause the maloperation of phase overcurrent protection. Because secondary harmonic
component is high in the inrush current but secondary harmonic component is low in the fault
current, harmonic control element based on secondary harmonic component is added to prevent
phase overcurrent protection from maloperation due to inrush current. For harmonic control
element, the harmonic blocking mode can be selected through the setting [50/51P.HMB.Opt_Blk],
it can support phase blocking, cross blocking, and maximum phase blocking. The corresponding
relationship is shown in the following table.
3
Harmonic blocking criterion
Harmonic blocking mode
Phase A Phase B Phase C
PhaseBlk (phase Ia2/Ia1> Ib2/Ib1> Ic2/Ic1>
1
blocking) x.50/51P.HMB.K_Hm2 x.50/51P.HMB.K_Hm2 x.50/51P.HMB.K_Hm2
2 CrossBlk (cross blocking) (Ia2/Ia1) or (Ib2/Ib1) or (Ic2/Ic1)> x.50/51P.HMB.K_Hm2
MaxPhaseBlk (maximum Max(Ia2, Ib2, Ic2)/Ia1> Max(Ia2, Ib2, Ic2)/Ib1> Max(Ia2, Ib2, Ic2)/Ic1>
3
phase blocking) x.50/51P.HMB.K_Hm2 x.50/51P.HMB.K_Hm2 x.50/51P.HMB.K_Hm2
When the fundamental current is greater than the setting [x.50/51P.HMB.I_Rls], the corresponding
phase will be unblocked by harmonic control element. The logic of harmonic control element is
shown in Figure 3.10-6.
SET Imax>[x.50/51P.HMB.I_Rls]
SIG x.Ia1, x.Ib1, x.Ic1

&
x.50/51P.HMB.Op
Harmonic
criterion
SIG x.Ia2, x.Ib2, x.Ic2
SET [x.50/51P.HMB.Opt_Blk]
Figure 3.10-6 Logic of harmonic control element
Where:
x.Ia1, x.Ib1, x.Ic1 are the fundamental current.
x.Ia2, x.Ib2, x.Ic2 are the secondary harmonic current.
x.Imax is the maximum phase current.
3.10.1.4 Operating Characteristics
Phase overcurrent protection can operate instantaneously or with a fixed time delay. It can also
operate with inverse-time characteristics, and its characteristics curve complies with the
standards IEC 60255-3 and ANSI C37.112. Phase overcurrent protection can support
definite-time characteristics, IEC & ANSI standard inverse-time characteristics and user-defined
inverse-time characteristics, which are determined by the setting [x.50/51Pi.Opt_Curve] (i=1~6).

The relationship between the setting and the characteristics curve is shown in the table below.
50/51Pi.Opt_Curve Time Characteristics k α c tr

ANSIE ANSI Extremely inverse 28.2 2.0 0.1217 29.1
ANSIV ANSI Very inverse 19.61 2.0 0.491 21.6
ANSIN ANSI Normal inverse 0.0086 0.02 0.0185 0.46
ANSIM ANSI Moderately inverse 0.0515 0.02 0.114 4.85
ANSIDefTime ANSI Definite time - - - -
ANSILTE ANSI Long time extremely inverse 64.07 2.0 0.25 30
ANSILTV ANSI Long time very inverse 28.55 2.0 0.712 13.46
ANSILT ANSI Long time inverse 0.086 0.02 0.185 4.6
3 IECN IEC Normal inverse 0.14 0.02 0 -
IECV IEC Very inverse 13.5 1.0 0 -
IEC IEC Inverse 0.14 0.02 0 -
IECE IEC Extremely inverse 80.0 2.0 0 -
IECST IEC Short time inverse 0.05 0.04 0 -
IECLT IEC Long time inverse 120.0 1.0 0 -
IECDefTime IEC Definite time - - - -
UserDefine Programmable
When the setting [x.50/51Pi.Opt_Curve] is set as "UserDefine", it means that user-defined

inverse-time characteristics is selected. These settings [x.50/51Pi.K], [x.50/51Pi.C] and
[x.50/51Pi.Alpha] are valid, and the inverse-time operating curve is determined by the three
settings.
 Instantaneous characteristics
When I>[x.50/51Pi.I_Set], phase overcurrent protection operates instantaneously.
 Definite-time characteristics
When I>[x.50/51Pi.I_Set], phase overcurrent protection operates with a time delay

[x.50/51Pi.t_Op], and the operating characteristics curve is as shown in Figure 3.10-7.

[x.50/51Pi.t_Op]
I
[x.50/51Pi.I_Set]
Figure 3.10-7 Definite-time operating curve of phase overcurrent protection
 Inverse-time characteristics
When I>[x.50/51Pi.I_Set], phase overcurrent protection begins to accumulate, and the operating
time is affected by the applied current I. The operating time will decrease with the current
increasing, but the operating time shall not less than the setting [x.50/51Pi.tmin] (i=1~6). The
inverse-time operating characteristics equation is:
Where:
IP is the current setting [x.50/51Pi.I_Set].
TMS is the inverse-time time multiplier, i.e. the setting [x.50/51Pi.TMS].
K is the inverse-time coefficient, i.e. the setting [x.50/51Pi.K].
C is the inverse-time coefficient, i.e. the setting [x.50/51Pi.C].
α is the inverse-time coefficient, i.e. the setting [x.50/51Pi.Alpha].
I is the measured current.
The inverse-time operating characteristics curve is shown Figure 3.10-8.

3 [x.50/51Pi.tmin]
I
[x.50/51Pi.I_Set] ID
Figure 3.10-8 Inverse-time operating curve of phase overcurrent protection
When the applied current is not a fixed value, but changes with the time, the operating behavior of
inverse-time phase overcurrent protection is shown in the following equation.
Where:
T0 is the operating time of the protection element.
t(I) is the theoretical operating time when the current is I.
3.10.1.5 Dropout Characteristics
The supported dropout characteristics of phase overcurrent protection include instantaneous,

definite-time and ANSI inverse-time characteristics. When the operating characteristics curve is
selected as definite-time, IEC inverse-time or user-defined inverse-time characteristics, the
dropout characteristic curve can only be selected as instantaneous or definite-time characteristics,
and the alarm signal "Fail_Settings" will be issued and the device will be blocked if ANSI
inverse-time characteristics is selected. When the operating characteristics curve is selected as
ANSI inverse-time characteristics, the dropout characteristic curve can be selected as
instantaneous, definite-time and ANSI inverse-time characteristics.
When I<0.95×[x.50/51Pi.I_Set], phase overcurrent protection drops out instantaneously.
When I<0.95×[x.50/51Pi.I_Set], phase overcurrent protection drops out with a time delay
[x.50/51Pi.t_DropOut], and the sequence diagram of definite-time dropout characteristic among

start signal, operating signal and the counter is as shown in Figure 3.10-9.
Start time
I>[x.50/51Pi.I_Set]
x.50/51Pi.St
3
x.50/51Pi.Op
[x.50/51Pi.t_Op] Phase overcurrent

protection operating
Operating counter
[x.50/51Pi.t_DropOut]
[x.50/51Pi.t_DropOut] [x.50/51Pi.t_DropOut]
Dropout time
Dropout time
Figure 3.10-9 Definite-time dropout characteristics of phase overcurrent protection
When I>[x.50/51Pi.I_Set], phase overcurrent protection begins to accumulate, the accumulated

value after tP (Assuming tP is less than the theoretical operating time) is calculated according to
the following equation.
If I<0.95×[x.50/51Pi.I_Set], phase overcurrent protection begins to drop out, and the dropout
characteristics meets the following equations.
Where:

tR is the dropout time.
IP is the current setting [x.50/51Pi.I_Set].
TMS is the inverse-time time multiplier, i.e., the setting [x.50/51Pi.TMS].
tr is the dropout time coefficient, it is the dropout time required when the current drops to 0 after
phase overcurrent protection operates.
I is the measured current.
If 0.95×[x.50/51Pi.I_Set]<I<[x.50/51Pi.I_Set], the counter will neither accumulate nor drop out.
3 The inverse-time dropout characteristics curve is shown in Figure 3.10-10.
tr
I
[x.50/51Pi.I_Set]
Figure 3.10-10 Inverse-time dropout curve of phase overcurrent protection
The sequence diagram of inverse-time dropout characteristics among start signal, operating
signal and the counter is shown in Figure 3.10-11.

Start time
I>[x.50/51Pi.I_Set]
x.50/51Pi.St
x.50/51Pi.Op
[x.50/51Pi.t_Op]
Phase overcurrent protection operating
3
Operating counter
Dropout time Coefficient (tr)
Dropout time
Dropout time
Figure 3.10-11 Inverse-time dropout characteristics of phase overcurrent protection
50/51P
x.50/51Pi.in_I3P x.50/51Pi.On
x.50/51Pi.Enable x.50/51Pi.Blocked
x.50/51Pi.Block x.50/51Pi.Valid
x.50/51P.VCE.in_U3P .
x.50/51P.DIR.in_U3P .
x.50/51P.DIR.in_I3P .
x.50/51P.HMB.in_I3P x.50/51P.DIR.FwdDir.Op
x.50/51P.DIR.RevDir.Op
x.50/51P.HMB.Op
3.10.3 I/O Signal

Table 3.10-1 Input signals of phase overcurrent protection

1 x.50/51Pi.in_I3P Three-phase current data input for phase overcurrent protection (i=1~6)


2 x.50/51Pi.Enable Input signal of enabling stage i of phase overcurrent protection (i=1~6)
3 x.50/51Pi.Block Input signal of blocking stage i of phase overcurrent protection (i=1~6)
Three-phase voltage data input for voltage control element of phase
4 x.50/51P.VCE.in_U3P
overcurrent protection
Three-phase voltage data input for direction control element of phase

5 x.50/51P.DIR.in_U3P
Three-phase current data input for direction control element of phase

6 x.50/51P.DIR.in_I3P
3 7 x.50/51P.HMB.in_I3P
Three-phase current data input for harmonic control element of phase
Table 3.10-2 Output signals of phase overcurrent protection

1 x.50/51Pi.On Stage i of phase overcurrent protection is enabled. (i=1~6)
2 x.50/51Pi.Blocked Stage i of phase overcurrent protection is blocked. (i=1~6)
3 x.50/51Pi.Valid Stage i of phase overcurrent protection is valid. (i=1~6)
4 x.50/51Pi.St Stage i of phase overcurrent protection starts. (i=1~6)
5 x.50/51Pi.StA Stage i of phase-A overcurrent protection starts. (i=1~6)
6 x.50/51Pi.StB Stage i of phase-B overcurrent protection starts. (i=1~6)
7 x.50/51Pi.StC Stage i of phase-C overcurrent protection starts. (i=1~6)
8 x.50/51Pi.Op Stage i of phase overcurrent protection operates. (i=1~6)
9 x.50/51Pi.Op.PhA Stage i of phase-A overcurrent protection operates. (i=1~6)
10 x.50/51Pi.Op.PhB Stage i of phase-B overcurrent protection operates. (i=1~6)
11 x.50/51Pi.Op.PhC Stage i of phase-C overcurrent protection operates. (i=1~6)
12 x.50/51Pi.Alm Stage i of phase overcurrent protection alarms. (i=1~6)
13 x.50/51P.VCE.Op The voltage control element of phase overcurrent protection operates.
14 x.50/51P.DIR.FwdDir.Op The forward direction element of phase overcurrent protection operates.
15 x.50/51P.DIR.RevDir.Op The reverse direction element of phase overcurrent protection operates.
16 x.50/51P.HMB.Op The harmonic control element of phase overcurrent protection operates.

3.10.4 Logic
SET Ia>[x.50/51Pi.I_Set]
SIG X.50/51P.VCE.Op_A >=1 &
EN [x.50/51Pi.En_Volt_Blk]
SIG X.50/51P.DIR.FwdDir.Op_A
selection
Direction
SIG x.50/51P.DIR.RevDir.Op_A
SIG [x.50/51Pi.Opt_Dir] x.50/51Pi.StA

&
SIG x.50/51P.HMB.Op_A & & Timer
EN [x.50/51Pi.En_Hm_Blk]
t
t 3
SIG x.50/51Pi.Pkp &
x.50/51Pi.Op.PhA
SET [x.50/51Pi.Opt_Trp/Alm]=Trp
&
x.50/51Pi.Alm_A
SET [x.50/51Pi.Opt_Trp/Alm]=Alm
SIG x.50/51Pi.StA
>=1
SIG x.50/51Pi.StB x.50/51Pi.St
SIG x.50/51Pi.StC
SIG x.50/51Pi.Op.PhA
>=1
SIG x.50/51Pi.Op.PhB x.50/51Pi.Op
SIG x.50/51Pi.Op.PhC
SIG x.50/51Pi.Alm_A
>=1
SIG x.50/51Pi.Alm_B x.50/51Pi.Alm
SIG x.50/51Pi.Alm_C
Figure 3.10-12 Logic of phase overcurrent protection
3.10.5 Settings
Table 3.10-3 Settings of phase overcurrent protection

10.000~100.0 Low voltage setting of
1 x.50/51P.VCE.Upp V 70
00 voltage control element
Negative-sequence voltage
2 x.50/51P.VCE.U2 2.000~57.000 V 8 setting of voltage control
element
Zero-sequence voltage
3 x.50/51P.VCE.3U0 2.000~57.000 V 8 setting of voltage control
element


Enabling/Disabling phase
overcurrent protection with
voltage control element is
Disabled
4 x.50/51P.VCE.En_VTS_Blk - Disabled blocked by VT circuit failure
Enabled
when VT circuit supervision
is enabled and VT circuit
fails
The characteristic angle of
5 x.50/51P.DIR.RCA -180~179 ° 45
direction control element
3 6 x.50/51P.DIR.phi_Min_Fwd 10~90 ° 90
The minimum boundary in
forward direction of phase
The maximum boundary in
7 x.50/51P.DIR.phi_Max_Fwd 10~90 ° 90 forward direction of phase
8 x.50/51P.DIR.phi_Min_Rev 10~90 ° 90 reverse direction of phase
9 x.50/51P.DIR.phi_Max_Rev 10~90 ° 90 reverse direction of phase
The voltage polarization
mode of direction control
element
Upp: phase-to-phase
Upp voltage is used as polarized
10 x.50/51P.DIR.Opt_PolarizedVolt Up - Upp voltage
U1 Up: phase-to-ground voltage
is used as polarized
voltage
U1: positive-sequence
voltage is used as polarized
The minimum operating
11 x.50/51P.DIR.I_Min 0.050~1.000 In 0.05 current setting of direction
control element
12 x.50/51P.DIR.U_Min 1.000~10.000 V 4 voltage setting of direction
control element
Enabling/Disabling phase
Disabled
13 x.50/51P.DIR.En_VTS_Blk - Disabled direction control element is
Enabled
blocked by VT circuit failure


fails
The coefficient of second
14 x.50/51P.HMB.K_Hm2 0.100~1.000 - 0.2 harmonics of harmonic
control element
The current setting of
2.000~150.00
15 x.50/51P.HMB.I_Rls A 20 releasing harmonic control
0
element
The option of harmonic
PhaseBlk,
blocking mode 3
PhaseBlk: phase blocking
16 x.50/51P.HMB.Opt_Blk CrossBlk, - PhaseBlk
CrossBlk: cross blocking
MaxPhaseBlk
MaxPhaseBlk: maximum
phase blocking
The current setting for stage
0.050~200.00
17 x.50/51Pi.I_Set A 15 i of phase overcurrent
0
protection (i=1~6)
The operating time delay for
0.000~100.00
18 x.50/51Pi.t_Op s 0.1 stage i of phase overcurrent
0
protection (i=1~6)
The dropout time delay for
0.000~100.00
19 x.50/51Pi.t_DropOut s 0 stage i of phase overcurrent
0
protection (i=1~6)
Enabling/Disabling stage i of
Disabled phase overcurrent protection
20 x.50/51Pi.En_Volt_Blk - Disabled
Enabled controlled by voltage control
element (i=1~6)
The option direction
NonDirectional
characteristic for stage i of
21 x.50/51Pi.Opt_Dir Forward - NonDirectional
phase overcurrent protection
Reverse
(i=1~6)
Disabled phase overcurrent protection
22 x.50/51Pi.En_Hm_Blk - Disabled
Enabled controlled by harmonic
control element (i=1~6)
Enabling/disabling stage i of
Disabled
23 x.50/51Pi.En - Enabled phase overcurrent protection
Enabled
(i=1~6)
Trp
24 x.50/51Pi.Opt_Trp/Alm - Trp operate to trip or alarm
Alm
(i=1~6)
Trp: for tripping purpose


Alm: for alarm purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE
ANSILTV The option of operating
ANSILT characteristics curve for
25 x.50/51Pi.Opt_Curve - IECDefTime
3 IECN
IECV
stage i of phase overcurrent
protection (i=1~6)
IEC
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of dropout
characteristics curve for
stage i of phase overcurrent
protection (i=1~6)
Inst
Inst: instantaneous dropout
26 x.50/51Pi.Opt_Curve_DropOut DefTime - Inst
characteristics
IDMT
DefTime: definite-time
dropout characteristics
IDMT: inverse-time dropout
characteristics
Time multiplier setting for
stage i of inverse-time phase
27 x.50/51Pi.TMS 0.040~20.000 - 1
(i=1~6)
The minimum operating time
for stage i of inverse-time
28 x.50/51Pi.tmin 0.000~10.000 s 0.02
(i=1~6)
The constant “K” for stage i
0.0010~120.0 of customized inverse-time
29 x.50/51Pi.K - 0.14
000 phase overcurrent protection
(i=1~6)
The constant “α” for stage i
30 x.50/51Pi.Alpha - 0.02
(i=1~6)


The constant “C” for stage i
31 x.50/51Pi.C - 0
(i=1~6)
3.11 Earth Fault Overcurrent Protection (50/51G, 67G)

Under normal conditions, three phases of the power system is symmetrical, its zero-sequence
current and voltage are zero theoretically. Most of the faults are asymmetrical, so various
protections reflect sequence component principle can be fulfilled based on the fault's
asymmetrical characteristics. Earth fault protection has been widely used in power systems, it can 3
be applied for the fault as long as there is zero-sequence current, including single-phase earth
fault and phase-to-phase short-circuit earth fault etc.

“CWS” by default.

The device can provide 4 stages of earth fault protection with independent logic by default. Each
stage can be independently set as definite-time characteristics or inverse-time characteristics. It
can be chosen whether it is blocked by harmonic control element. The direction control element
can be set as no direction, forward direction and reverse direction. The zero-sequence current
used by earth fault protection can derived from calculated zero-sequence current or measured
zero-sequence current.
Earth fault protection can operate to trip or alarm and can be enabled or disabled via the settings
or the signals, for some specific applications, earth fault protection needs to be blocked by the
external signal, so the device provides an input signal to be used to block earth fault protection.
EN [x.50/51Gi.En] &
x.50/51Gi.On
SIG x.50/51Gi.Enable
&
SIG x.50/51Gi.Block >=1 x.50/51Gi.Blocked
SIG Fail_Device
&
x.50/51Gi.Valid
Figure 3.11-1 Logic of enabling earth fault protection

The pickup logic of earth fault protection is shown in Figure 3.11-2.
SET x.3I0>0.95×[x.50/51Gi.3I0_Set] & x.50/51Gi.Pkp

0 500ms &
SIG x.50/51Gi.On &
FD.Pkp
SIG x.50/51Gi.Valid
SET [x.50/51Gi.Opt_Trp/Alm]=Alm
Figure 3.11-2 Pickup logic of earth fault protection

3
In order to ensure the selectivity of earth fault protection, direction control element can be
available. The setting [x.50/51Gi.Opt_Dir] (i=1~6) is used to select the direction characteristics for
each stage of earth fault protection: no direction, forward direction and reverse direction are
selectable. The operation boundary of the forward direction element can be set by
[x.50/51G.DIR.phi_Min_Fwd] and [x.50/51G.DIR.phi_Max_Fwd]. The operation boundary of the
reverse direction element can be set by [x.50/51G.DIR.phi_Min_Rev] and
[x.50/51G.DIR.phi_Max_Rev].
-U0
[x.50/51G.DIR.phi_Min_Fwd]
Non-operating I0
area
Operating area in
[x.50/51G.DIR.phi_Max_Rev] forward direction
[x.50/51G.DIRRCA]
Operating area in
reverse direction
[x.50/51G.DIR.phi_Max_Fwd]
Non-operating
area
[x.50/51G.DIR.phi_Min_Rev]
Figure 3.11-3 Operating characteristics of direction control element
The following table shows the relationship among the operating current, the polarized voltage and
the polarization mode.

Polarization Polarized
Operating current Angle difference
mode voltage
Calculated residual current:
- 3U0 Angle=Angle(-3U0)-Angle(3I0_Cal)-RCA
Zero-sequence 3I0_Cal
voltage polarized Measured residual current:
- 3U0 Angle=Angle(-3U0)-Angle(3I0_Ext)-RCA
3I0_Ext
The logic of forward direction element and reverse direction element are shown in Figure 3.11-4.
For transformers, the polarity of neutral-point CT is at grounding side by 3

default. So, in case of an out-of-zone fault, the directions of calculated
residual current and external residual current are reversed, and the
method of calculating angle difference is the same, which should be noted
when setting the characteristic angle.

EN [x.50/51G.En_VTS_Blk] &
>=1
SIG x.VTS.Alm
SIG x.3I0_Ext, x.3I0_Cal
Forward direction
& >=1
x.50/51G.DIR.FwdDir.Op
criterion
3 SIG x.3U0_Cal
BI x.BI_En_VT &
EN x.En_VT
EN [x.50/51G.En_VTS_Blk] &
>=1
SIG x.VTS.Alm
SIG x.3I0_Ext, x.3I0_Cal

Reverse direction
& >=1
x.50/51G.DIR.RevDir.Op
criterion
SIG x.3U0_Cal
BI x.BI_En_VT &
EN x.En_VT
Where:
x.3I0_Ext is the measured residual current.
x.3I0_Cal is the calculated residual current.
x.3U0_Cal is the calculated residual voltage.
3.11.1.2 Harmonic Control Element
Harmonic control element based on zero-sequence current can be used to prevent earth fault
protection from maloperation due to inrush current. Zero-sequence current can be calculated or
measured. When the percentage of second harmonic component to fundamental component in

residual current is greater than the setting [x.50/51G.HMB.K_Hm2], harmonic control element
operates to block earth fault protection if the corresponding setting [x.50/51Gi.En_Hm_Blk] is set
as "Enabled" (i=1~6). When the fundamental component of zero-sequence current is greater than
the setting [x.50/51G.HMB.I_Rls], earth fault protection will be unblocked by harmonic control
element. The logic of harmonic control element is shown in Figure 3.11-5.
SET x.3I0>[x.50/51G.HMB.I_Rls]
SIG x.3I0_Ext or x.3I0_Cal

&
x.50/51G.HMB.Op
Harmonic
criterion
SET x.3I0_2nd/3I0>[x.50/51G.HMB.K_Hm2] 3
Figure 3.11-5 Logic of harmonic control element
Where:
x.3I0_2nd is secondary harmonic component of residual current.
Earth fault protection can operate instantaneously or with a fixed time delay. It can also operate
with inverse-time characteristics, and its characteristics curve complies with the standards IEC
60255-3 and ANSI C37.112. Earth fault protection can support definite-time characteristics, IEC &
ANSI standard inverse-time characteristics and user-defined inverse-time characteristics, which
are determined by the setting [x.50/51Gi.Opt_Curve] (i=1~6). The relationship between the setting
and the characteristics curve is shown in the table below.
50/51Gi.Opt_Curve Time Characteristic k α c tr

ANSIE ANSI Extremely inverse 28.2 2.0 0.1217 29.1
ANSIV ANSI Very inverse 19.61 2.0 0.491 21.6
IECN IEC Normal inverse 0.14 0.02 0 -
When the setting [x.50/51Gi.Opt_Curve] is set as "UserDefine", it means that user-defined

inverse-time characteristics is selected. These settings [x.50/51Gi.K], [x.50/51Gi.C] and

[x.50/51Gi.Alpha] are valid, and the inverse-time operating curve is determined by the three
settings.
When x.3I0>[x.50/51Gi.3I0_Set], earth fault protection operates immediately.
When x.3I0>[x.50/51Gi.3I0_Set], earth fault protection operates with a time delay

[x.50/51Gi.t_Op], and the operating characteristics curve is as shown in Figure 3.11-6.
t
3
[x.50/51Gi.t_Op]
I0
[x.50/51Gi.3I0_Set]
Figure 3.11-6 Definite-time operating curve of earth fault protection
When x.3I0>[x.50/51Gi.3I0_Set], earth fault protection begins to accumulate, and the operating
time is affected by the applied current x.3I0. The operating time will decrease with the current
increasing, but the operating time shall not less than the setting [x.50/51Gi.tmin] (i=1~6). The
Where:
I0P is the current setting [x.50/51Gi.3I0_Set].
TMS is the inverse-time time multiplier, i.e. the setting [x.50/51Gi.TMS].
K is the inverse-time coefficient, i.e. the setting [x.50/51Gi.K].
C is the inverse-time coefficient, i.e. the setting [x.50/51Gi.C].

α is the inverse-time coefficient, i.e. the setting [x.50/51Gi.Alpha].
x.3I0 is the measured residual current.
[x.50/51Gi.tmin]
I0
[x.50/51Gi.3I0_Set] ID
Figure 3.11-7 Inverse-time operating curve of earth fault protection
When the applied residual current is not a fixed value, but changes with the time, the operating
behavior of inverse-time earth fault protection is shown in the following equation.
Where:
t(x.3I0) is the theoretical operating time when the current is x.3I0.
The supported dropout characteristics of earth fault protection include instantaneous, definite-time
and ANSI inverse-time characteristics. When the operating characteristics curve is selected as
definite-time, IEC inverse-time or user-defined inverse-time characteristics, the dropout
characteristic curve can only be selected as instantaneous or definite-time characteristics, and the
alarm signal "Fail_Settings" will be issued and the device will be blocked if ANSI inverse-time
characteristics is selected. When the operating characteristics curve is selected as ANSI
inverse-time characteristics, the dropout characteristic curve can be selected as instantaneous,
definite-time and ANSI inverse-time characteristics.
When x.3I0<0.95×[x.50/51Gi.3I0_Set], earth fault protection drops out immediately.

When x.3I0<0.95×[x.50/51Gi.3I0_Set], earth fault protection drops out with a time delay
[x.50/51Gi.t_DropOut], and the sequence diagram of definite-time dropout characteristic among
start signal, operating signal and the counter is as shown in Figure 3.11-8.
Start time
x.3I0>[x.50/51Gi.3I0_Set]
3
x.50/51Gi.St
x.50/51Gi.Op
[x.50/51Gi.t_Op] Earth fault protection

operating
Operating counter
[x.50/51Gi.t_DropOut]
[x.50/51Gi.t_DropOut] [x.50/51Gi.t_DropOut]
Dropout time
Dropout time
Figure 3.11-8 Definite-time dropout characteristics of earth fault protection
When x.3I0<0.95×[x.50/51Gi.3I0_Set], earth fault protection begins to accumulate, the

accumulated value after tP (Assuming tP is less than the theoretical operating time) is calculated
according to the following equation.
If x.3I0<0.95×[x.50/51Gi.3I0_Set], earth fault protection begins to drop out, and the dropout
characteristics meets the following equations.

Where:
I0P is zero-sequence current setting [x.50/51Gi.3I0_Set].
TMS is the inverse-time time multiplier, i.e., the setting [x.50/51Gi.TMS].
tr is the dropout time coefficient, it is the dropout time required when the current drops to 0 after 3
earth fault protection operates.
x.3I0 is the measured residual current.
If 0.95×[x.50/51Gi.3I0_Set]< x.3I0<[x.50/51Gi.3I0_Set], the counter will neither accumulate nor

drop out.
The inverse-time dropout characteristics curve is shown in Figure 3.11-9.
tr
I0
[x.50/51Gi.3I0_Set]
Figure 3.11-9 Inverse-time dropout curve of earth fault protection

Start time
x.3I0>[x.50/51Gi.3I0_Set]
x.50/51Gi.St
x.50/51Gi.Op
3 [x.50/51Gi.t_Op]
Earth fault protection operating
Operating counter
Dropout time
Dropout time
Figure 3.11-10 Inverse-time dropout characteristics of earth fault protection
50/51G
x.50/51Gi.in_I3P x.50/51Gi.On
x.50/51Gi.in_I1P x.50/51Gi.Blocked
x.50/51Gi.Enable x.50/51Gi.Valid
x.50/51Gi.Block x.50/51Gi.St
X.50/51G.DIR.in_I3P x.50/51Gi.Op
x.50/51G.DIR.in_I1P x.50/51Gi.Alm
x.50/51G.DIR.in_U3P x.50/51G.DIR.FwdDir.Op
x.50/51G.HMB.in_I3P x.50/51G.DIR.RevDir.Op
x.50/51G.HMB.in_I1P x.50/51G.HMB.Op
3.11.3 I/O Signal

Table 3.11-1 Input signals of earth fault protection

1 x.50/51Gi.in_I3P Three-phase current data input for earth fault protection (i=1~4)


2 x.50/51Gi.in_I1P Single-phase current data input for earth fault protection (i=1~4)
3 x.50/51Gi.Enable Input signal of enabling stage i of earth fault protection (i=1~4)
4 x.50/51Gi.Block Input signal of blocking stage i of earth fault protection (i=1~4)
5 x.50/51G.DIR.in_I3P Three-phase current data input for direction control element
6 x.50/51G.DIR.in_I1P Single-phase current data input for direction control element
7 x.50/51G.DIR.in_U3P Three-phase voltage data input for direction control element
8 x.50/51G.HMB.in_I3P Three-phase current data input for harmonic control element
9 x.50/51G.HMB.in_ I1P Single-phase current data input for harmonic control element
Table 3.11-2 Output signals of earth fault protection

3
1 x.50/51Gi.On Stage i of earth fault protection is enabled. (i=1~4)
2 x.50/51Gi.Blocked Stage i of earth fault protection is blocked. (i=1~4)
3 x.50/51Gi.Valid Stage i of earth fault protection is valid. (i=1~4)
4 x.50/51Gi.St Stage i of earth fault protection starts. (i=1~4)
5 x.50/51Gi.Op Stage i of earth fault protection operates. (i=1~4)
6 x.50/51Gi.Alm Stage i of earth fault protection alarms. (i=1~4)
7 x.50/51G.DIR.FwdDir.Op The forward direction element of earth fault protection operates.
8 x.50/51G.DIR.RevDir.Op The reverse direction element of earth fault protection operates.
9 x.50/51G.HMB.Op The harmonic control element of earth fault protection operates.
3.11.4 Logic
SET x.3I0>[x.50/51Gi.3I0_Set]
SIG X.50/51G.DIR.FwdDir.Op x.50/51Gi.St

&
selection
Direction
SIG x.50/51G.DIR.RevDir.Op & Timer

t
SET [x.50/51Gi.Opt_Dir] t
SIG x.50/51G.HMB.Op &
EN [x.50/51Gi.En_Hm_Blk]
SIG x.50/51Gi.Pkp
&
x.50/51Gi.Op
SET [x.50/51Gi.Opt_Trp/Alm]=Trp
&
x.50/51Gi.Alm
SET [x.50/51Gi.Opt_Trp/Alm]=Alm
Figure 3.11-11 Logic diagram of earth fault overcurrent protection
3.11.5 Settings

Table 3.11-3 Settings of earth fault overcurrent protection

1 x.50/51G.DIR.RCA -180~179 ° 45
2 x.50/51G.DIR.phi_Min_Fwd 10~90 ° 90 forward direction of earth
fault protection
3 x.50/51G.DIR.phi_Max_Fwd 10~90 ° 90 forward direction of earth
fault protection
3 The minimum boundary in
4 x.50/51G.DIR.phi_Min_Rev 10~90 ° 90 reverse direction of earth
fault protection
5 x.50/51G.DIR.phi_Max_Rev 10~90 ° 90 reverse direction of earth
fault protection
6 x.50/51G.DIR.I_Min 0.050~1.000 In 0.05 current setting of
7 x.50/51G.DIR.U_Min 1.000~10.000 V 4 voltage setting of
Enabling/Disabling earth
fault protection with
direction control element is
Disabled
8 x.50/51G.DIR.En_VTS_Blk - Disabled blocked by VT circuit failure
Enabled
fails
The option of the residual
current used by earth fault
protection with direction
Ext control element
9 x.50/51Gi.DIR.Opt_3I0 - Ext
Cal Ext: the measured residual
current
Cal: the calculated residual
current
10 x.50/51G.HMB.K_Hm2 0.100~1.000 - 0.2 harmonics of harmonic
control element
11 x.50/51G.HMB.I_Rls 2.000~150.000 A 20 releasing harmonic control
element


Ext harmonic control element
12 x.50/51Gi.HMB.Opt_3I0 - Ext
current
current
3
Ext
13 x.50/51Gi.Opt_3I0 - Ext Ext: the measured residual
Cal
current
current
The zero-sequence current
14 x.50/51Gi.3I0_Set 0.050~200.000 A 15 setting for stage i of earth
fault protection (i=1~4
The operating time delay
15 x.50/51Gi.t_Op 0.000~100.000 s 0.1 for stage i of earth fault
protection (i=1~4)
16 x.50/51Gi.t_DropOut 0.000~100.000 s 0 stage i of earth fault
protection (i=1~4)
NonDirectional
characteristic for stage i of
17 x.50/51Gi.Opt_Dir Forward - NonDirectional
earth fault protection
Reverse
(i=1~4)
Enabling/Disabling stage i
Disable of earth fault protection
18 x.50/51Gi.En_Hm_Blk - Disabled
Enabling/disabling stage i
Disabled
19 x.50/51Gi.En - Enabled of earth fault protection
Enabled
(i=1~4)
of earth fault protection
Trp operate to trip or alarm
20 x.50/51Gi.Opt_Trp/Alm - Trp
Alm (i=1~4)
ANSIE The option of operating
21 x.50/51Gi.Opt_Curve - IECDefTime
ANSIV characteristics curve for


ANSIN stage i of earth fault
ANSIM protection (i=1~4)
ANSIDefTime
ANSILTE
ANSILTV
ANSILT
IECN
IECV
IEC
3 IECE
IECST
IECLT
IECDefTime
UserDefine
stage i of earth fault
protection (i=1~4
Inst
22 x.50/51Gi.Opt_Curve_DropOut DefTime - Inst
characteristics
IDMT
characteristics
stage i of inverse-time
23 x.50/51Gi.TMS 0.040~20.000 - 1
(i=1~4)
time for stage i of
24 x.50/51Gi.tmin 0.000~10.000 s 0.02
inverse-time earth fault
protection (i=1~4
of customized inverse-time
25 x.50/51Gi.K 0.0010~120.0000 - 0.14
(i=1~4)
26 x.50/51Gi.Alpha 0.0100~3.0000 - 0.02
(i=1~4)
27 x.50/51Gi.C 0.0000~1.0000 - 0 of customized inverse-time


(i=1~4)
3.12 Negative-sequence Overcurrent Protection (50/51Q, 67Q)

When a phase-to-phase fault occurs in the system, the fault current is small, and phase current
criterion may not detect the fault. At this time, negative-sequence overcurrent protection is
sensitive to the fault and can be used. Negative-sequence overcurrent protection can also be
used to detect pole disagreement operation or unbalanced load.
3
by default.

The device can provide two stages of negative-sequence overcurrent protection with independent
logic. Each stage can be independently set as definite-time characteristics or inverse-time
characteristics. For parallel lines or a ring network line, the flow direction of negative-sequence
current may be different. Considering the selectivity of negative-sequence overcurrent protection,
the direction control element can be set as no direction, forward direction and reverse direction.
Negative-sequence overcurrent protection can operate to trip or alarm and can be enabled or
disabled via the settings or the signals, for some specific applications, negative-sequence
overcurrent protection needs to be blocked by the external signal, so the device provides an input
signal to be used to block negative-sequence overcurrent protection.
EN [x.50/51Qi.En] &
x.50/51Qi.On
SIG x.50/51Qi.Enable
&
SIG x.50/51Qi.Block >=1 x.50/51Qi.Blocked
SIG Fail_Device
&
x.50/51Qi.Valid
Figure 3.12-1 Logic of enabling negative-sequence overcurrent protection
The pickup logic of negative-sequence overcurrent protection is shown in Figure 3.11-2.

SET x.I2>0.95×[x.50/51Qi.I2_Set] & x.50/51Qi.Pkp

0 500ms &
SIG x.50/51Qi.On &
FD.Pkp
SIG x.50/51Qi.Valid
SET [x.50/51Qi.Opt_Trp/Alm]=Alm
Figure 3.12-2 Pickup logic of negative-sequence protection
In order to ensure the selectivity of negative-sequence overcurrent protection, direction control

3 element can be available. The setting [x.50/51Qi.Opt_Dir] (i=1 or 2) is used to select the direction
characteristics for each stage of negative-sequence overcurrent protection: no direction, forward
direction and reverse direction are selectable. The direction control element selects
negative-sequence voltage as the polarized voltage, its operating characteristics is shown in
Figure 3.12-3.
The operation boundary of the forward direction element can be set by

[x.50/51Q.DIR.phi_Min_Fwd] and [x.50/51Q.DIR.phi_Max_Fwd]. The operation boundary of the
reverse direction element can be set by [x.50/51Q.DIR.phi_Min_Rev] and
[x.50/51Q.DIR.phi_Max_Rev].
-U2
[x.50/51Q.DIR.phi_Min_Fwd]
Non-operating I2
area
[x.50/51Q.DIR.phi_Max_Rev]
Operating area in
forward direction
[x.50/51Q.DIR.RCA]
Operating area in
reverse direction
[x.50/51Q.DIR.phi_Max_Fwd]
Non-operating
area
[x.50/51Q.DIR.phi_Min_Rev]
Figure 3.12-3 Operating characteristics of direction control element

The following table shows the relationship among the operating current, the polarized voltage and
the polarization mode.
Polarized
Polarization mode Operating current Angle difference
voltage
Negative-sequence
Negative-sequence current: I2 -U2 Angle=Angle(-U2)-Angle(I2)-RCA
voltage polarized
The logic of forward direction element and reverse direction element are shown in Figure 3.12-4.
EN [x.50/51Q.En_VTS_Blk] &
3
>=1
SIG x.VTS.Alm
SIG x.I2
Forward direction
& >=1
criterion
x.50/51Q.DIR.FwdDir.Op
SIG x.U2
SIG x.BI_En_VT &
EN x.En_VT
EN [x.50/51Q.En_VTS_Blk] &
>=1
SIG x.VTS.Alm
SIG x.I2
Reverse direction
& >=1
criterion
x.50/51Q.DIR.RevDir.Op
SIG x.U2
SIG x.BI_En_VT &
EN x.En_VT

Negative-sequence overcurrent protection can operate instantaneously or with a fixed time delay.
It can also operate with inverse-time characteristics, and its characteristics curve complies with
the standards IEC 60255-3 and ANSI C37.112. Negative-sequence overcurrent protection can
support definite-time characteristics, IEC & ANSI standard inverse-time characteristics and
user-defined inverse-time characteristics, which are determined by the setting
[x.50/51Qi.Opt_Curve] (i=1 or 2). The relationship between the setting and the characteristics
curve is shown in the table below.
50/51Qx.Opt_Curve Time Characteristic k α c tr
3 ANSIE
ANSIV
ANSI Extremely inverse
ANSI Very inverse
28.2
19.61
2.0
2.0
0.1217
0.491
29.1
21.6
IECN IEC Normal inverse 0.14 0.02 0 -
When the setting [x.50/51Qi.Opt_Curve] is set as "UserDefine", it means that user-defined

inverse-time characteristics is selected. These settings [x.50/51Qi.K], [x.50/51Qi.C] and
[x.50/51Qi.Alpha] are valid, and the inverse-time operating curve is determined by the three
settings.
When x.I2>[x.50/51Qi.I2_Set], negative-sequence overcurrent protection operates immediately.
When x.I2>[x.50/51Qi.I2_Set], negative-sequence overcurrent protection operates with a time

delay [x.50/51Qi.t_Op], the operating characteristics curve is as shown in Figure 3.12-5.

[x.50/51Qi.t_Op]
I2
[x./51Qi.I2_Set]
Figure 3.12-5 Definite-time operating curve of negative-sequence overcurrent protection
When x.I2>[x.50/51Qi.I2_Set], negative-sequence overcurrent protection begins to accumulate,

and the operating time is affected by the applied current x.I2. The operating time will decrease
with the current increasing, but the operating time shall not less than the setting [x.50/51Qi.tmin]
(i=1 or 2). The inverse-time operating characteristics equation is:
Where:
I2P is the current setting [x.50/51Qi.I2_Set].
TMS is the inverse-time time multiplier, i.e. the setting [x.50/51Qi.TMS].
K is the inverse-time coefficient, i.e. the setting [x.50/51Qi.K].
C is the inverse-time coefficient, i.e. the setting [x.50/51Qi.C].
α is the inverse-time coefficient, i.e. the setting [x.50/51Qi.Alpha].
x.I2 is the measured negative-sequence current.

3 [x.50/51Qi.tmin]
I2
[x.50/51Qi.I2_Set] ID
Figure 3.12-6 Inverse-time operating curve of negative-sequence overcurrent protection
When the applied negative-sequence current is not a fixed value, but changes with the time, the
operating behavior of inverse-time negative-sequence overcurrent protection is shown in the
following equation.
Where:
t(x.I2) is the theoretical operating time when the current is x.I2.
The supported dropout characteristics of negative-sequence overcurrent protection include

instantaneous, definite-time and ANSI inverse-time characteristics. When the operating
characteristics curve is selected as definite-time, IEC inverse-time or user-defined inverse-time
characteristics, the dropout characteristic curve can only be selected as instantaneous or
definite-time characteristics, and the alarm signal "Fail_Settings" will be issued and the device
will be blocked if ANSI inverse-time characteristics is selected. When the operating characteristics
curve is selected as ANSI inverse-time characteristics, the dropout characteristic curve can be
selected as instantaneous, definite-time and ANSI inverse-time characteristics.
When x.I2<0.95×[x.50/51Qi.I2_Set], negative-sequence overcurrent protection drops out

immediately.

When x.I2<0.95×[x.50/51Qi.I2_Set], negative-sequence overcurrent protection drops out with a

time delay [x.50/51Qi.t_DropOut], and the sequence diagram of definite-time dropout
characteristic among start signal, operating signal and the counter is as shown in Figure 3.12-7.
Start time
x.I2>[x.50/51Qi.I2_Set]
x.50/51Qi.St 3
x.50/51Qi.Op
[x.50/51Qi.t_Op] Negative-sequence overcurrent

Operating counter
[x.50/51Qi.t_DropOut]
[x.50/51Qi.t_DropOut] [50/51Qi.t_DropOut]
Dropout time
Dropout time
Figure 3.12-7 Definite-time dropout characteristics of negative-sequence overcurrent protection
When x.I2<0.95×[x.50/51Qi.I2_Set], negative-sequence overcurrent protection begins to

accumulate, the accumulated value after tP (Assuming tP is less than the theoretical operating
time) is calculated according to the following equation.
If x.I2<0.95×[x.50/51Qi.I2_Set], negative-sequence overcurrent protection begins to drop out, and

the dropout characteristics meets the following equations.

Where:
I2P is negative-sequence current setting [x.50/51Qi.I2_Set].
TMS is the inverse-time time multiplier, i.e., the setting [x.50/51Qi.TMS].
3 tr is the dropout time coefficient, it is the dropout time required when the current drops to 0 after
negative-sequence overcurrent protection operates.
x.I2 is the measured negative-sequence current.
If 0.95×[x.50/51Qi.I2_Set]< x.I2<[x.50/51Qi.I2_Set], the counter will neither accumulate nor drop

out.
The inverse-time dropout characteristics curve is shown in Figure 3.12-8.
tr
I2
[x.50/51Qi.I2_Set]
Figure 3.12-8 Inverse-time dropout curve of negative-sequence overcurrent protection

Start time
x.I2>[x.50/51Qi.I2_Set]
x.50/51Qi.St
x.50/51Qi.Op
[x.50/51Qi.t_Op]
Negative-sequence overcurrent
3
Operating counter
Dropout time
Dropout time
Figure 3.12-9 Inverse-time dropout characteristics of negative-sequence overcurrent protection
50/51Q
x.50/51Qi.in_I3P x.50/51Qi.On
x.50/51Qi.Enable x.50/51Qi.Blocked
x.50/51Qi.Valid
x.50/51Qi.Block
x.50/51Qi.St
x.50/51Q.DIR.in_I3P
x.50/51Qi.Op
x.50/51Q.DIR.in_U3P
x.50/51Qi.Alm
x.50/51Q.DIR.FwdDir.Op
x.50/51Q.DIR.RevDir.Op
3.12.3 I/O Signal

Table 3.12-1 Input signals of negative-sequence overcurrent protection

Three-phase current data input for negative-sequence overcurrent
1 x.50/51Qi.in_I3P
protection (i=1~2)
Input signal of enabling stage i of negative-sequence overcurrent protection
2 x.50/51Qi.Enable
(i=1~2)
3 x.50/51Qi.Block Input signal of blocking stage i of negative-sequence overcurrent protection


(i=1~2)
Three-phase current data input for direction control element of
4 x.50/51Q.DIR.in_I3P
negative-sequence overcurrent protection
Three-phase voltage data input for direction control element of
5 x.50/51Q.DIR.in_U3P
negative-sequence overcurrent protection
Table 3.12-2 Output signals of negative-sequence overcurrent protection

1 x.50/51Qi.On Stage i of negative-sequence overcurrent protection is enabled. (i=1~2)
3 2 x.50/51Qi.Blocked Stage i of negative-sequence overcurrent protection is blocked. (i=1~2)

3 x.50/51Qi.Valid Stage i of negative-sequence overcurrent protection is valid. (i=1~2)
4 x.50/51Qi.St Stage i of negative-sequence overcurrent protection starts. (i=1~2)
5 x.50/51Qi.Op Stage i of negative-sequence overcurrent protection operates. (i=1~2)
6 x.50/51Qi.Alm Stage i of negative-sequence overcurrent protection alarm. (i=1~2)
The forward direction element of negative-sequence overcurrent
7 x.50/51Q.DIR.FwdDir.Op
protection operates.
The reverse direction element of negative-sequence overcurrent
8 x.50/51Q.DIR.RevDir.Op
protection operates.
3.12.4 Logic
SET x.I2>[x.50/51Qi.I2_Set]
x.50/51Qi.St
SIG x.50/51Q.FwdDir.Op
&
& Timer
selection
Direction
t
SIG x.50/51Q.RevDir.Op
t
SET [x.50/51Qi.Opt_Dir]
SIG x.50/51Qi.Pkp &

x.50/51Qi.Op
SET [50/51Qx.Opt_Trp/Alm]=Trp
&
x.50/51Qi.Alm
SET [50/51Qx.Opt_Trp/Alm]=Alm
Figure 3.12-10 Logic of negative-sequence overcurrent protection
3.12.5 Settings
Table 3.12-3 Settings of negative-sequence overcurrent protection

The characteristic
1 x.50/51Q.DIR.RCA -180~179 ° 45 angle of direction
control element
2 x.50/51Q.DIR.phi_Min_Fwd 10~90 ° 90 The minimum


boundary in forward
direction of
negative-sequence
overcurrent
protection
The maximum
boundary in forward
direction of
3 x.50/51Q.DIR.phi_Max_Fwd 10~90 ° 90
negative-sequence
overcurrent
protection
3
The minimum
boundary in reverse
direction of
4 x.50/51Q.DIR.phi_Min_Rev 10~90 ° 90
negative-sequence
overcurrent
protection
The maximum
boundary in reverse
direction of
5 x.50/51Q.DIR.phi_Max_Rev 10~90 ° 90
negative-sequence
overcurrent
protection
The minimum
operating current
6 x.50/51Q.DIR.I_Min 0.050~1.000 In 0.05
setting of direction
control element
The minimum
operating voltage
7 x.50/51Q.DIR.U_Min 1.000~10.000 V 4
control element
Enabling/Disabling
negative-sequence
overcurrent
protection with
direction control
Disabled
8 x.50/51Q.DIR.En_VTS_Blk - Disabled element is blocked
Enabled
by VT circuit failure
when VT circuit
supervision is
enabled and VT
circuit fails
9 x.50/51Qi.I2_Set 0.050~200.000 A 15 The


negative-sequence
current setting for
stage i of
negative-sequence
overcurrent
protection (i=1 or 2)
The operating time
delay for stage i of
10 x.50/51Qi.t_Op 0.030~100.000 s 0.1 negative-sequence
3 overcurrent
The dropout time
11 x.50/51Qi.t_DropOut 0.000~100.000 s 0 negative-sequence
overcurrent
characteristic for
NonDirectional
stage i of
12 x.50/51Qi.Opt_Dir Forward - NonDirectional
negative-sequence
Reverse
overcurrent
Enabling/disabling
stage i of
Disabled
13 x.50/51Qi.En - Enabled negative-sequence
Enabled
overcurrent
Enabling/disabling
stage i of
negative-sequence
overcurrent
protection operate to
Trp
14 x.50/51Qi.Opt_Trp/Alm - Trp trip or alarm (i=1 or
Alm
2)
Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE The option of
ANSIV operating
15 x.50/51Qi.Opt_Curve ANSIN - IECDefTime characteristics curve
ANSIM for stage i of
ANSIDefTime negative-sequence


ANSILTE overcurrent
ANSILTV protection (i=1 or 2)
ANSILT
IECN
IECV
IEC
IECE
IECST
IECLT
IECDefTime
UserDefine
3
The option of
dropout
characteristics curve
for stage i of
negative-sequence
overcurrent
Inst
Inst: instantaneous
16 x.50/51Qi.Opt_Curve_DropOut DefTime - Inst
dropout
IDM
characteristics
DefTime:
definite-time dropout
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier
setting for stage i of
inverse-time
17 x.50/51Qi.TMS 0.040~20.000 - 1
negative-sequence
overcurrent
The minimum
operating time for
stage i of
18 x.50/51Qi.tmin 0.000~10.000 s 0.02 inverse-time
negative-sequence
overcurrent
The constant “K” for
19 x.50/51Qi.K 0.0010~120.0000 - 0.14 stage i of customized
inverse-time


negative-sequence
overcurrent
The constant “α” for
stage i of customized
inverse-time
20 x.50/51Qi.Alpha 0.0100~3.0000 - 0.02
negative-sequence
overcurrent
3 The constant “C” for

inverse-time
21 x.50/51Qi.C 0.0000~1.0000 - 0
negative-sequence
overcurrent
3.13 Thermal Overload Protection (49)
3.13.1 Application
During overload operation of a power transformer, the generated large current may cause the
transformer temperature to rise. When the temperature is high, the internal insulation of the
transformer may be aged, thereby increasing the possibility of internal failure. Continued high
temperature can also degrade the quality of the transformer oil.
Thermal overload protection is to estimates the continuous heating content of the transformer. The
estimation is made based on the measured currents and the built thermal model of the transformer
with two time constants.

through PCS-Studio software, which may be “HVS”, “MVS”, “LVS”, “LVS2”
by default.
The device provide two methods to fulfill thermal overload protection, one is to calculate thermal
accumulation according the actual measured current, and the other is applied to the scenario with
oil temperature measurement, it is to calculate temperature difference between winding
temperature and oil temperature according to the measured currents and can gain winding
temperature based on the oil temperature acquired by external transducer.
1. Method 1

Two stages overload protection are available, one stage for alarm purpose and the other stage for
trip purpose. When the temperature increases to the alarm value, thermal overload protection
issues alarm signal to remind the operator for attention, and if the temperature continues to
increase to the trip value, thermal overload protection issues trip command.
There are four thermal overload protection elements at most equipped at each side of transformer.
Thermal overload protection adopts IEC 60255-8 as thermal time characteristic, and fundamental
current or 1st to 11th harmonic current is used for protection calculation.
The device provides a thermal overload model which is based on the IEC60255-8 standard.
Refer to IEC60255-8
t
3
Ip
P=—
IB
P = 0.0
P = 0.6
P = 0.8
P = 0.9
kIB I
Figure 3.13-1 Characteristic curve of thermal overload protection
There are two types of thermal time characteristic, cold start characteristic and hot start
characteristic. The thermal overload formulas are shown as below.
1. Cold start characteristic
2
I eq
t    ln Equation 3.13-1
2
I eq  (k  I B ) 2
2. Hot start characteristic
2
I eq  I 2p
t    ln Equation 3.13-2
2
I eq  (k  I B ) 2
Where:
t is the theoretical operate time, following application of the overload current.
τ is the heating thermal time constant of the protected device, i.e. [x.49.Tau].
Ieq is the equivalent heating current, i.e. actual measured current.
IP is the steady-state load current prior to the overload for a duration which would result in

constant thermal level (duration is greater than several time constant τ), which is memory current.
For cold start characteristic, it is zero.
ln is natural logarithm
IB is the base current, i.e. [x.49.Ib_Set].
k is thermal overload coefficient, i.e. [x.49.K_Alm] or [x.49.K_Trp].
The hot start characteristic is adopted in the device. The calculation is carried out at zero of IP, so
users need not to set the value of IP.
Tripping outputs of the protection is controlled by current, even if the thermal accumulation value
3 is greater than the setting for tripping, the protection drops off instantaneously when current
disappears. Alarm outputs of the protection is not controlled by current, and only if the thermal
accumulation value is greater than the setting for alarm, alarm output contacts, which can be
connected to block the auto-reclosure, will operate.
2. Method 2
The actual windings temperature can be gained by oil temperature, which is measured by external
transducer (PT100), plus temperature difference between windings temperature and oil
temperature, i.e.,
T_windings (windings temperature) = T_oil (oil temperature) + T_Diff (temperature difference

between windings and oil)
The temperature difference can be calculated according to the current, and is changed with the
current. When the current is increased from 0 to I, the temperature accumulation complies with
the following equation.
t
I
T _ Diff  [ x.49.K _ T _ Diff ]  ( )  ( 1  e Tau )
[ x.49.Ib _ Set ]
Finally, stable temperature difference:
I
T _ Diff  [ x.49.K _ T _ Diff ]  ( )
[ x.49.Ib _ Set ]
Where:
I is the measured current
α is cooling factor, taking 1.6 or 2
t is time
Tau is time constant
According to the calculated windings temperature, the user can compare it with user-defined
temperature value, and can set stage and time delay to trip or alarm by user-defined logic.

49
X.49.in_I3P x.49.On
x.49.Enable x.49.Blocked
x.49.Block .
x.49.Clr .
.
x.49.T_Diff_B
x.49.T_Diff_C
3
3.13.4 I/O Signals

Table 3.13-1 Input signals of thermal overload protection

Three-phase current data input for thermal overload protection at x side of
1 x.49.in_I3P
transformer.
Input signal of enabling thermal overload protection at x side of transformer. It is
2 x.49.Enable
triggered from binary input or programmable logic etc.
Input signal of blocking thermal overload protection at x side of transformer. It is
3 x.49.Block
triggered from binary input or programmable logic etc.
Clear command of thermal accumulation value for thermal overload protection at x
4 x.49.Clr
side of transformer.
Table 3.13-2 Output signals of thermal overload protection

1 x.49.On Thermal overload protection at x side of transformer is enabled.
2 x.49.Blocked Thermal overload protection at x side of transformer is blocked.
3 x.49.Valid Thermal overload protection at x side of transformer is valid.
4 x.49.St Thermal overload protection at x side of transformer starts.
5 x.49.StA Phase-A thermal overload protection at x side of transformer starts.
6 x.49.StB Phase-B thermal overload protection at x side of transformer starts.
7 x.49.StC Phase-C thermal overload protection at x side of transformer starts.
8 x.49.Op Thermal overload protection at x side of transformer operates to trip.
9 x.49.Op.PhA Phase-A thermal overload protection at x side of transformer operates to trip.
10 x.49.Op.PhB Phase-B thermal overload protection at x side of transformer operates to trip.
11 x.49.Op.PhC Phase-C thermal overload protection at x side of transformer operates to trip.
12 x.49.Alm Thermal overload protection at x side of transformer operates to alarm.
13 x.49.Accu_A Phase-A thermal state of thermal overload protection at x side of transformer.
14 x.49.Accu_B Phase-B thermal state of thermal overload protection at x side of transformer.
15 x.49.Accu_C Phase-C thermal state of thermal overload protection at x side of transformer.


The calculated temperature difference of phase-A between winding temperature
16 x.49.T_Diff_A
and oil temperature.
The calculated temperature difference of phase-B between winding temperature
17 x.49.T_Diff_B
The calculated temperature difference of phase-C between winding temperature
18 x.49.T_Diff_C
3.13.5 Logic
3 EN [x.49.En_Trp] >=1
EN [x.49.En_Alm] &
x.49.On
SIG x.49.Enable
&
SIG x.49.Block >=1 x.49.Blocked
SIG Fail_Device
&
x.49.Valid
Figure 3.13-2 Logic diagram of enabling thermal overload protection (method 1)
SIG x.49.in_I3P
SET [x.49.Ib_Set]
&
0 500ms &
x.49.Pkp
SIG x.49.On
FD.Pkp
SIG x.49.Valid
Figure 3.13-3 Pickup logic of thermal overload protection (method 1)
SIG x.49.Pkp
&
SIG x.49.in_I3P x.49.St
& Timer
SET [x.49.Ib_Set] t
x.49.Alm
t
EN [x.49.En_Alm]
& Timer
t
x.49.Op
t
EN [x.49.En_Trp]
SIG x.49.Clr
Figure 3.13-4 Logic diagram of thermal overload protection (method 1)

3.13.6 Settings
Table 3.13-3 Settings of thermal overload protection

1 x.49.Ib_Set 0.050~200.000 A 15 Base current setting of thermal overload protection
Tripping setting of thermal capacity for thermal
2 x.49.K_Trp 1.000~3.000 - 1.2
overload protection
Alarm setting of thermal capacity for thermal
3 x.49.K_Alm 1.000~3.000 - 1.1
overload protection
4 x.49.Tau 0.100~100.000 min 1 Thermal time constant
5 x.49.K_T_Diff 0.000~200.000 - 30
The convertor coefficient from the current to the 3
temperature
The cooling mode of transformer, usually,
6 x.49.Alpha_Cold 1.000~2.000 - 2 natural cooling: 1.6
forced cooling: 2
Disabled Logic setting of enabling/disabling thermal overload
7 x.49.En_Trp - Disabled
Enabled protection for trip purpose
8 x.49.En_Alm - Disabled
Enabled protection for alarm purpose
3.14 Breaker Failure Protection (50BF)

When a fault happens to the power system, the device will operate to trip the circuit breaker, and
the fault will be isolated by opening the circuit breaker. If the circuit breaker fails to open within the
certain time due to some abnormalities (for example, low tripping pressure), the fault may cause
system stability being destroyed or electrical equipment being damaged. Breaker failure
protection is adopted to issue a backup tripping command to trip adjacent circuit breakers, and
isolate the fault as requested by the device.
According to the tripping information from the device and the auxiliary information (the current and
the position) of target circuit breaker, breaker failure protection constitutes the criterion to
discriminate whether the target circuit fails to open. If the criterion is confirmed, breaker failure
protection will operate to trip the target circuit breaker with the time delay [x.50BF.t_ReTrp], trip it
again with the time delay [x.50BF.t1_Op] and trip the adjacent circuit breakers with the time delay
[x.50BF.t2_Op]. As a special backup protection, breaker failure protection can quickly isolate the
fault, reduce the affected range by the fault, keep system stability and prevent generators,
transformers and other primary equipments from seriously damaged.

through PCS-Studio software, which may be “HVS”, “MVS”, “LVS” by
default.


For breaker failure protection, phase-segregated re-trip, three-phases re-trip and two time delays
are available.
3.14.1.1 Phase-segregated Re-trip
For phase-segregated tripping system, breaker failure protection provides phase-segregated

re-trip function. When breaker failure protection receives initiating signal of phase-segregated
tripping and phase overcurrent element of corresponding phase operates, the device will issue
phase-segregated tripping command to re-trip the target circuit breaker with the time delay
[x.50BF.t_ReTrp]. In order to improve the sensitivity, zero-sequence overcurrent element is added,
3 which can be enabled or disabled by the setting [x.50BF.En_3I0_1P]. In order to avoid undesired
operating of breaker failure protection and reduce the affected range, phase-segregated re-trip
does not block AR.
3.14.1.2 Three-phases Re-trip
For non phase-segregated tripping system, breaker failure protection provides three-phases
re-trip function. When breaker failure protection receives initiating signal of three-phases tripping
and phase overcurrent element of any phase operates, the device will issue three-phases tripping
command to re-trip the target circuit breaker with the time delay [x.50BF.t_ReTrp]. In order to
improve the sensitivity, both zero-sequence overcurrent element and negative-sequence
overcurrent element are added, which can be enabled or disabled by the settings
[x.50BF.En_3I0_3P] and [x.50BF.En_I2_3P]. In order to avoid undesired operating of breaker
failure protection and reduce the affected range, three-phases re-trip does not block AR.
3.14.1.3 First Time Delay
As similar as three-phase re-trip, the device will operate to re-trip the target circuit breaker again
with the time delay [x.50BF.t1_Op] when the relevant operating criterion is satisfied.
3.14.1.4 Second Time delay
As similar as three-phase re-trip, the device will operate to trip the adjacent circuit breakers with
the time delay [x.50BF.t2_Op] when the relevant operating criterion is satisfied.
3.14.1.5 Current Criterion
1. Phase overcurrent element
Where:
= A, B or C
2. Zero-sequence overcurrent element
Where:

is calculated residual current
3. Negative-sequence overcurrent element
Where:
is negative-sequence current
For some special fault (for example, mechanical protection or overvoltage protection operating),
maybe faulty current is very small and current criterion of breaker failure protection is not met, in
order to make breaker failure protection can also operate under the above situation, an input
signal "x.50BF.ExTrp_WOI" is equipped to initiate breaker failure protection, once the input signal 3
is energized, normally closed auxiliary contact of circuit breaker is chosen in addition to breaker
failure current check to trigger breaker failure timer. The device takes current as priority with CB
auxiliary contact " x.50BF.52b" as an option criterion for breaker failure check.
When the initiating signal of breaker failure protection is energized for longer than 10s, an alarm
signal "50BF.Alm_Init" will be issued, and will drop out with a time delay of 10s.
50BF
x.50BF.in_I3P x.50BF.On
x.50BF.Enable x.50BF.Blocked
x.50BF.Block x.50BF.Valid
x.50BF.ExTrpA x.50BF.St
x.50BF.ExTrpB x.50BF.StA
x.50BF.ExTrpC x.50BF.StB
x.50BF.ExTrp3P x.50BF.StC
x.50BF.ExTrp_WOI x.50BF.Op_ReTrpA
x.50BF.52b x.50BF.Op_ReTrpB
x.50BF.Op_ReTrpC
x.50BF.Op_ReTrp3P
x.50BF.Op_t1
x.50BF.Op_t2
x.50BF.Alm_Init
3.14.3 I/O Signals

Table 3.14-1 Input signals of breaker failure protection


1 x.50BF.in_I3P Three-phase current data input for breaker failure protection.
2 x.50BF.Enable Input signal of enabling breaker failure protection
3 x.50BF.Block Input signal of blocking breaker failure protection
4 x.50BF.ExtTrpA Input signal of initiating breaker failure protection (phase-A)
5 x.50BF.ExtTrpB Input signal of initiating breaker failure protection (phase-B)
6 x.50BF.ExtTrpC Input signal of initiating breaker failure protection (phase-C)
7 x.50BF.ExtTrp3P Input signal of initiating breaker failure protection (three-phases)
Input signal of initiating breaker failure protection with the position check of the
8 x.50BF.ExtTrp_WOI
circuit breaker
3 9 x.50BF.BI_52b Input signal of three-phase open position of three circuit breaker
Table 3.14-2 Output signals of breaker failure protection

1 x.50BF.On Breaker failure protection is enabled.
2 x.50BF.Blocked Breaker failure protection is blocked.
3 x.50BF.Valid Breaker failure protection is valid.
4 x.50BF.StA Breaker failure protection starts (phase-A).
5 x.50BF.StB Breaker failure protection starts (phase-B).
6 x.50BF.StC Breaker failure protection starts (phase-C).
7 x.50BF.St Breaker failure protection starts. (three-phases)
8 x.50BF.Op_ReTrpA Breaker failure protection operates to re-trip phase-A circuit breaker.
9 x.50BF.Op_ReTrpB Breaker failure protection operates to re-trip phase-B circuit breaker.
10 x.50BF.Op_ReTrpC Breaker failure protection operates to re-trip phase-C circuit breaker.
11 x.50BF.Op_ReTrp3P Breaker failure protection operates to re-trip three-phases circuit breaker.
12 x.50BF.Op_t1 Breaker failure protection operates with the time delay [x.50BF.t1_Op].
13 x.50BF.Op_t2 Breaker failure protection operates with the time delay [x.50BF.t2_Op].
14 x.50BF.Alm_Init The initiating signal of breaker failure protection is energized consistently
3.14.4 Logic
EN [x.50BF.En] &
x.50BF.On
SIG x.50BF.Enable
&
SIG x.50BF.Block >=1 x.50BF.Blocked
SIG Fail_Device
&
x.50BF.Valid
Figure 3.14-1 Logic of enabling reverse power protection

SIG x.50BF.ExtTrpA 10s 10s

>=1

>=1
SIG x.50BF.ExtTrp3P 10s 10s
SIG x.50BF.ExtTrp_WOI 10s 10s

&
EN [x.50BF.En_Alm_Init] x.50BF.Alm_Init
SIG x.50BF.Valid
Figure 3.14-2 Logic of breaker failure initiating signal abnormality 3

SIG x.50BF.Valid &
SIG x.50BF.Alm_Init
EN [x.50BF.En_ReTrp]
EN [x.50BF.En_3I0_1P] >=1
SET x.3I0>[x.50BF.3I0_Set]
& &
SIG x.50BF.ExtTrpA [x.50BF.t_ReTrp] 0 x.50BF.Op_ReTrpA
SET x.IA>[x.50BF.I_Set] x.50BF.StA
& &
SIG x.50BF.ExtTrpB [x.50BF.t_ReTrp] 0 x.50BF.Op_ReTrpB
3 SET x.IB>[x.50BF.I_Set] x.50BF.StB
& &
SIG x.50BF.ExtTrpC [x.50BF.t_ReTrp] 0 x.50BF.Op_ReTrpC
SET x.IC>[x.50BF.I_Set]
>=1 x.50BF.StC
EN [x.50BF.En_Ip]
SET x.IA>[x.50BF.I_Set]
>=1
SET x.IB>[x.50BF.I_Set] &
& [x.50BF.t_ReTrp] 0 x.50BF.Op_ReTrp3P
SET x.IC>[x.50BF.I_Set]
SIG x.50BF.Op_ReTrp3P
&
EN [x.50BF.En_3I0_3P] &
>=1
SET x.3I0>[x.50BF.3I0_Set]
>=1 &
& >=1 [x.50BF.t1_Op] 0 x.50BF.Op_t1
EN [x.50BF.En_I2_3P] &
SET x.I2>[x.50BF.I2_Set]
SIG x.50BF.ExtTrp_WOI
>=1
& x.50BF.St
EN [x.50BF.En_CB_Ctrl]
SIG x.50BF.52b
EN [x.50BF.En_t1]
&
[x.50BF.t2_Op] 0 x.50BF.Op_t2
EN [x.50BF.En_t2]
Figure 3.14-3 Logic of breaker failure protection
3.14.5 Settings
Table 3.14-3 Settings of breaker failure protection

The phase current setting of breaker failure
1 x.50BF.I_Set 0.050~200.000 A 1.000
protection
The zero-sequence current setting of
2 x.50BF.3I0_Set 0.050~200.000 A 1.000
breaker failure protection


The negative-sequence current setting of
3 x.50BF.I2_Set 0.050~200.000 A 1.000
The re-trip time delay of breaker failure
4 x.50BF.t_ReTrp 0.000~20.000 s 0.050
protection
The first time delay of breaker failure
5 x.50BF.t1_Op 0.000~20.000 s 0.100
protection
The second time delay of breaker failure
6 x.50BF.t2_Op 0.000~20.000 s 0.200
protection
Disabled
7 x.50BF.En - Enabled Enabling/disabling breaker failure protection
Enabled 3
Disabled Enabling/disabling re-trip function of breaker
8 x.50BF.En_ReTrp - Enabled
Enabled failure protection
Disabled Enabling/disabling first time delay of breaker
9 x.50BF.En_t1 - Disabled
Disabled Enabling/disabling second time delay of
Enabled breaker failure protection
Enabling/disabling zero-sequence
Disabled
11 x.50BF.En_3I0_1P - Disabled overcurrent element of breaker failure
Enabled
protection via single-phase initiating signal
Enabling/disabling phase overcurrent
Disabled
12 x.50BF.En_Ip - Disabled element of breaker failure protection via
Enabled
three-phases initiating signal
Disabled
Enabled
protection via three-phases initiating signal
Enabling/disabling negative-sequence
Disabled
14 x.50BF.En_I2_3P - Disabled overcurrent element of breaker failure
Enabled
Enabling/disabling breaker failure protection
Disabled
15 x.50BF.En_CB_Ctrl - Disabled be initiated by normally closed contact of
Enabled
circuit breaker
Disabled Enabling/disabling abnormality check of
16 x.50BF.En_Alm_Init - Disabled
Enabled breaker failure initiating signal
3.15 Phase Overvoltage Protection (59P)

In the power system, some abnormal conditions can generate high voltage, which may damage
the insulation performance of transformers, capacitors, motors and transmission lines, resulting in
equipment damage. Phase overvoltage protection can effectively detect the overvoltage that may
be generated in the system.


by default.
The device can provide two stages of phase overvoltage protection with independent logic. When
a high voltage occurs in the system, phase overvoltage protection will operate to isolate the fault
from the system after a time delay if the voltage is greater than the setting. In addition, phase
overvoltage protection also provides the alarm function to notify that there is the overvoltage in the
system and find the cause timely to prevent from further deterioration of the fault.
3 Each stage of phase overvoltage protection can be independently set as definite-time
characteristics or inverse-time characteristics. The dropout characteristics can be set as
instantaneous dropout and definite-time dropout.
Phase voltage or phase-to-phase voltage can be selected to be used by the protection calculation
via the setting [x.59P.Opt_Up/Upp]. “1-out-of-3” or “3-out-of-3” logic can be selected for the
protection criterion. (1-out-of-3 means any of three phase voltages, 3-out-of-3 means all three
phase voltages)
Phase overvoltage protection can be enabled or disabled via the settings or the signals, for some
specific applications, phase overvoltage protection needs to be blocked by the external signal, so
the device provides an input signal to be used to block phase overvoltage protection.
EN [x.59Pi.En] &
x.59Pi.On
SIG x.59Pi.Enable
&
SIG x.59Pi.Block >=1 x.59Pi.Blocked
SIG Fail_Device
&
x.59Pi.Valid
Figure 3.15-1 Logic of enabling phase overvoltage protection
The pickup logic of phase overvoltage protection is shown in Figure 3.15-2.

SET x.Ua>[x.59Pi.U_Set]
>=1
SET x.Ub>[x.59Pi.U_Set] &
SET x.Uc>[x.59Pi.U_Set]
SET [x.59P.Opt_1P/3P]=1P
SET [x.59P.Opt_1P/3P]=3P >=1

& &
& 0 500ms &
SET x.Ub>[x.59Pi.U_Set] x.59Pi.Pkp
&
SET x.59P.Opt_Up/Upp=Up FD.Pkp 3
SIG x.59Pi.On
SIG x.59Pi.Valid
SET [x.59Pi.Opt_Trp/Alm]=Alm
SET x.Uab>[x.59Pi.U_Set]
>=1
SET x.Ubc>[x.59Pi.U_Set] &
SET x.Uca>[x.59Pi.U_Set]
SET [x.59P.Opt_1P/3P]=3P >=1

& &
& 0 500ms &
SET x.Ubc>[x.59Pi.U_Set] x.59Pi.Pkp
&
SET x.59P.Opt_Up/Upp=Upp FD.Pkp
SIG x.59Pi.On
SIG x.59Pi.Valid
Figure 3.15-2 Pickup logic of phase overvoltage protection
Phase overvoltage protection can operate with a fixed time delay. It can also operate with
inverse-time characteristics, and its characteristics curve complies with the standards IEC
60255-3 and ANSI C37.112. Phase overvoltage protection can support definite-time
characteristics, IEC & ANSI standard inverse-time characteristics and user-defined inverse-time
characteristics, which are determined by the setting [x.59Pi.Opt_Curve] (i=1 or 2). The
relationship between the setting and the characteristics curve is shown in the table below.
50/51Px.Opt_Curve Time Characteristic k α c

ANSIDefTime ANSI Definite time - - -
IECDefTime IEC Definite time - - -
UserDefine UserDefine

50/51Px.Opt_Curve Time Characteristic k α c

InvTime_U Voltage inverse 1 1 0
When the setting [x.59Pi.Opt_Curve] is set as “ANSIDefTime” or “IECDefTime”, the operating

characteristics is definite-time phase overvoltage protection. When the setting [x.59Pi.Opt_Curve]
is set as "UserDefine", it means that user-defined inverse-time characteristics is selected. These
settings [x.59Pi.K], [x.59Pi.C] and [x.59Pi.Alpha] are valid, and the inverse-time operating curve is
determined by the three settings. When the setting [x.59Pi.Opt_Curve] is set as “InvTime_U”, the
settings [x.59Pi.K], [x.59Pi.C] and [x.59Pi.Alpha] are useless.
3 When x.U>[x.59Pi.U_Set], phase overvoltage protection operates with a time delay [x.59Pi.t_Op],
the operating characteristics curve is as shown in Figure 3.15-3.
[x.59Pi.t_Op]
U
[x.59Pi.U_Set]
Figure 3.15-3 Definite-time operating curve of phase overvoltage protection
When x.U>[x.59Pi.U_Set], phase overvoltage protection begins to accumulate, and the operating
time is affected by the applied voltage x.U. The operating time will decrease with the voltage
increasing, but the operating time shall not less than the setting [x.59Pi.tmin] (i=1 or 2). The
Where:
UP is the voltage setting [x.59Pi.U_Set].
TMS is the inverse-time time multiplier, i.e. the setting [x.59Pi.TMS].

K is the inverse-time coefficient, i.e. the setting [x.59Pi.K].
C is the inverse-time coefficient, i.e. the setting [x.59Pi.C].
α is the inverse-time coefficient, i.e. the setting [x.59Pi.Alpha].
x.U is the measured voltage.
[x.59Pi.tmin]
U
[x.59Pi.U_Set] UD
Figure 3.15-4 Inverse-time operating curve of phase overvoltage protection
When the applied voltage is not a fixed value, but changes with the time, the operating behavior of
inverse-time phase overvoltage protection is shown in the following equation.
Where:
t(x.U) is the theoretical operating time when the voltage is x.U.
The supported dropout characteristics of phase overvoltage protection include instantaneous and
definite-time characteristics.
When x.U<[x.59Pi.K_DropOut]×[x.59Pi.U_Set], phase overvoltage protection drops out

immediately.

When x.U<[x.59Pi.K_DropOut]×[x.59Pi.U_Set], phase overvoltage protection drops out with a

time delay [x.59Pi.t_DropOut], and the sequence diagram of definite-time dropout characteristic
among start signal, operating signal and the counter is as shown in Figure 3.15-5.
Start time
x.U>[x.59Pi.U_Set]
3 x.59Pi.St
x.59Pi.Op
[x.59Pi.t_Op] Phase overvoltage

Operating counter
[x.59Pi.t_DropOut]
[x.59Pi.t_DropOut] [x.59Pi.t_DropOut]
Dropout time
Dropout time
Figure 3.15-5 Definite-time dropout characteristics of phase overvoltage protection

59P
x.59Pi.in_U3P x.59Pi.On
x.59Pi.Enable x.59Pi.Blocked
x.59Pi.Enable x.59Pi.Valid
x.59Pi.St
x.59Pi.StA
x.59Pi.StB
3
x.59Pi.StC
x.59Pi.Op
X.59Pi.Op.PhA
x.59Pi.Op.PhB
x.59Pi.Op.PhC
x.59Pi.Alm
3.15.3 I/O Signal

Table 3.15-1 Input signals of phase overvoltage protection

1 x.59Pi.in_U3P Three-phase voltage data input for phase overvoltage protection (i=1~2)
2 x.59Pi.Enable Input signal of enabling stage i of phase overvoltage protection (i=1~2)
3 x.59Pi.Block Input signal of blocking stage i of phase overvoltage protection (i=1~2)
Table 3.15-2 Output signals of phase overvoltage protection

1 x.59Pi.On Stage i of phase overvoltage protection is enabled. (i=1~2)
2 x.59Pi.Blocked Stage i of phase overvoltage protection is blocked. (i=1~2)
3 x.59Pi.Valid Stage i of phase overvoltage protection is valid. (i=1~2)
4 x.59Pi.St Stage i of phase overvoltage protection starts. (i=1~2)
5 x.59Pi.StA Stage i of phase-A overvoltage protection starts. (i=1~2)
6 x.59Pi.StB Stage i of phase-B overvoltage protection starts. (i=1~2)
7 x.59Pi.StC Stage i of phase-C overvoltage protection starts. (i=1~2)
8 x.59Pi.Op Stage i of phase overvoltage protection operates. (i=1~2)
9 x.59Pi.Op.PhA Stage i of phase-A overvoltage protection operates. (i=1~2)
10 x.59Pi.Op.PhB Stage i of phase-B overvoltage protection operates. (i=1~2)
11 x.59Pi.Op.PhC Stage i of phase-C overvoltage protection operates. (i=1~2)
12 x.59Pi.Alm Stage i of phase overvoltage protection alarm. (i=1~2)

3.15.4 Logic
>=1
SET x.Ub>[x.59Pi.U_Set] &
x.59Pi.St
SET [x.59P.Opt_1P/3P]=3P >=1
& & Timer
SET x.Ua>[x.59Pi.U_Set] t
&
3 SET x.Ub>[x.59Pi.U_Set]
t
SET x.59P.Opt_Up/Upp=Up
SIG x.59Pi.Pkp
&
x.59Pi.Op
SET [x.59Pi.Opt_Trp/Alm]=Trp
&
x.59Pi.Alm
>=1
SET x.Ubc>[x.59Pi.U_Set] &
x.59Pi.St
SET [x.59P.Opt_1P/3P]=3P >=1
& & Timer
SET x.Uab>[x.59Pi.U_Set] t
&
t
SET x.Ubc>[x.59Pi.U_Set]
SET x.59P.Opt_Up/Upp=Upp
SIG x.59Pi.Pkp
&
x.59Pi.Op
&
x.59Pi.Alm
Figure 3.15-6 Logic of phase overvoltage protection
3.15.5 Settings
Table 3.15-3 Settings of phase overvoltage protection


The option of the voltage criterion
used by stage i of phase
3P
1 x.59Pi.Opt_1P/3P - 3P overvoltage protection (i=1 or 2)
1P
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
The option of the calculation
voltage used by stage i of phase
Up
2 x.59Pi.Opt_Up/Upp - Upp overvoltage protection (i=1 or 2)
Upp
Up: phase voltage
Upp: phase-to-phase voltage
The voltage setting for stage i of
3
3 x.59Pi.U_Set 57.700~200.000 V 115 phase overvoltage protection (i=1
or 2)
The dropout coefficient for stage i
4 x.59Pi.K_DropOut 0.930~1.000 0.98 of phase overvoltage protection
(i=1 or 2)
The operating time delay for stage
5 x.59Pi.t_Op 0.100~100.000 s 1 i of phase overvoltage protection
(i=1 or 2)
The dropout time delay for stage i
6 x.59Pi.t_DropOut 0.000~100.000 s 0 of phase overvoltage protection
(i=1 or 2)
Disabled
7 x.59Pi.En - Enabled phase overvoltage protection (i=1
Enabled
or 2)
phase overvoltage protection
Trp
8 x.59Pi.Opt_Trp/Alm - Trp operate to trip or alarm (i=1 or 2)
Alm
ANSIDefTime The option of operating
IECDefTime characteristics curve for stage i of
9 x.59Pi.Opt_Curve - IECDefTime
UserDefine phase overvoltage protection (i=1
InvTime_U or 2)
characteristics curve for stage i of
phase overvoltage protection (i=1
Inst or 2)
10 x.59Pi.Opt_Curve_DropOut - Inst
DefTime Inst: instantaneous dropout
characteristics
DefTime: definite-time dropout
characteristics
11 x.59Pi.TMS 0.040~20.000 - 1 Time multiplier setting for stage i


of inverse-time phase overvoltage
The minimum operating time for
12 x.59Pi.tmin 0.000~10.000 s 0.02 stage i of inverse-time phase
overvoltage protection (i=1 or 2)
The constant “K” for stage i of
13 x.59Pi.K 0.0010~120.0000 - 1 customized inverse-time phase
The constant “C” for stage i of
3 14 x.59Pi.Alpha 0.0100~3.0000 - 1 customized inverse-time phase

The constant “α” for stage i of
15 x.59Px.C 0.0000~1.0000 - 0 customized inverse-time phase
3.16 Residual Overvoltage Protection (59G)

If an earth fault happens to the feeder in the grounding system via high resistance, the residual
current changes little and is difficult to detect. However, the amplitude of the residual voltage
changes significantly and can be used to detect the earth fault. In addition, the transformer is
grounded via the gap in the neutral point, the residual voltage increases once a fault occurs, so
residual overvoltage protection can also be used as backup protection of the transformer. The
residual voltage can be measured from broken-delta VT, and it can also be calculated internally by
the device using three-phase voltage.

by default.
The device can provide two stages of residual overvoltage protection with independent logic.
When the residual voltage is greater than the setting, residual overvoltage protection will operate
to isolate the fault from the system after a time delay. In addition, residual overvoltage protection
also provides the alarm function to notify that there is an earth fault leading to residual voltage
generation, and find the cause timely to prevent from further deterioration of the fault.
Residual overvoltage protection supports definite-time characteristics. The dropout characteristics

can be set as instantaneous dropout and definite-time dropout. Residual overvoltage protection
can be enabled or disabled via the settings or the signals, for some specific applications, residual
overvoltage protection needs to be blocked by the external signal, so the device provides an input
signal to be used to block residual overvoltage protection.

EN [x.59Gi.En] &
x.59Gi.On
SIG x.59Gi.Enable
&
SIG x.59Gi.Block >=1 x.59Gi.Blocked
SIG Fail_Device
&
x.59Gi.Valid
Figure 3.16-1 Logic of enabling residual overvoltage protection 3

The pickup logic of residual overvoltage protection is shown in Figure 3.16-2.
SET x.3U0_Cal>[x.59Gi.K_DropOut]×[x.59Gi.3U0_Set] &

>=1
SET [x.59G.Opt_3U0]=Cal &
0 500ms &
SET x.3U0_Ext>[x.59Gi.K_DropOut]×[x.59Gi.3U0_Set] & x.59Gi.Pkp
SET [x.59Gi.Opt_3U0]=Ext
SIG x.59Gi.On
SIG x.59Gi.Valid
&
FD.Pkp
SET [x.59Gi.Opt_Trp/Alm]=Alm
Figure 3.16-2 Pickup logic of residual overvoltage protection
When x.3U0>[x.59Gi.3U0_Set], residual overvoltage protection operates with a time delay

[x.59Gi.t_Op], the operating characteristics curve is as shown in Figure 3.16-3.

[x.59Gi.t_Op]
U0
[x.59Gi.3U0_Set]
Figure 3.16-3 Definite-time operating curve of residual overvoltage protection
The supported dropout characteristics of residual overvoltage protection include instantaneous

and definite-time characteristics.
When x.3U0<[x.59Gi.K_DropOut]×[x.59Gi.3U0_Set], residual overvoltage protection drops out

immediately.
When x.3U0<[x.59Gi.K_DropOut]×[x.59Gi.3U0_Set], residual overvoltage protection drops out

with a time delay [x.59Gi.t_DropOut], and the sequence diagram of definite-time dropout
characteristic among start signal, operating signal and the counter is as shown in Figure 3.16-4.

Start time
x.3U0>[x.59Gi.3U0_Set]
x.59Gi.St
x.59Gi.Op
3
[x.59Gi.t_Op] Residual overvoltage
Operating counter
[x.59Gi.t_DropOut]
[x.59Gi.t_DropOut] [x.59Gi.t_DropOut]
Dropout time
Dropout time
Figure 3.16-4 Definite-time dropout characteristics of residual overvoltage protection
59G
x.59Gi.in_U3P x.59Gi.On
x.59Gi.in_U1P x.59Gi.Blocked
x.59Gi.Enable x.59Gi.Valid
x.59Gi.Block x.59Gi.St
x.59Gi.Op
x.59Gi.Alm
3.16.3 I/O Signal

Table 3.16-1 Input signals of residual overvoltage protection

1 x.59Gi.in_U3P Three-phase voltage data input for residual overvoltage protection (i=1~2)
2 x.59Gi.in_U1P Residual voltage input (i=1~2)
3 x.59Gi.Enable Input signal of enabling stage i of residual overvoltage protection (i=1~2)
4 x.59Gi.Block Input signal of blocking stage i of residual overvoltage protection (i=1~2)

Table 3.16-2 Output signals of residual overvoltage protection

1 x.59Gi.On Stage i of residual overvoltage protection is enabled. (i=1~2)
2 x.59Gi.Blocked Stage i of residual overvoltage protection is blocked. (i=1~2)
3 x.59Gi.Valid Stage i of residual overvoltage protection is valid. (i=1~2)
4 x.59Gi.St Stage i of residual overvoltage protection starts. (i=1~2)
5 x.59Gi.Op Stage i of residual overvoltage protection operates. (i=1~2)
6 x.59Gi.Alm Stage i of residual overvoltage protection alarm. (i=1~2)
3.16.4 Logic
3
SET x.3U0_Cal> [x.59Gi.3U0_Set] & x.59Gi.St
&
SET [x.59G.Opt_3U0]=Cal &
[x.59Gi.t_Op] 0
SET x.3U0_Ext> [x.59Gi.3U0_Set] &
SET [x.59Gi.Opt_3U0]=Ext
SIG x.59Gi.Pkp &

x.59Gi.Op
SET [x.59Gi.Opt_Trp/Alm]=Trp
&
x.59Gi.Alm
SET [x.59Gi.Opt_Trp/Alm]=Alm
Figure 3.16-5 Logic of residual overvoltage protection
3.16.5 Settings
Table 3.16-3 Settings of residual overvoltage protection

The option of the residual voltage used by
Ext residual overvoltage protection
1 x.59G.Opt_3U0 - Ext
Cal Ext: the measured residual voltage
Cal: the calculated residual voltage
The voltage setting for stage i of residual
2 x.59Gi.3U0_Set 1.000~200.000 V 50
The dropout coefficient for stage i of
3 x.59Gi.K_DropOut 0.930~1.000 - 0.98
residual overvoltage protection (i=1 or 2)
The operating time delay for stage i of
4 x.59Gi.t_Op 0.100~100.000 s 1
The dropout time delay for stage i of
5 x.59Gi.t_DropOut 0.000~100.000 s 0
6 x.59Gi.En Disabled - Enabled Enabling/disabling stage i of residual


Enabled overvoltage protection (i=1 or 2)
Enabling/disabling stage i of residual
overvoltage protection operate to trip or
Trp
7 x.59Gi.Opt_Trp/Alm - Trp alarm (i=1 or 2)
Alm
3.17 Phase Undervoltage Protection (27P)

In the power system, some abnormal conditions will lead to low voltage. Electric equipment such
as motors cannot operate for a long time under the rated voltage and need to be isolated from the 3
system timely. In addition, the voltage decreasing may be related to the shortage of system
reactive power. Shedding some reactive loads through phase undervoltage protection can
improve the voltage level of the system.

by default.

The device can provide two stages of phase undervoltage protection with independent logic.
When the voltage drops in the system and it is lower than the setting, phase undervoltage
protection will operate to isolate the fault from the system after a time delay. In addition, phase
undervoltage protection also provides the alarm function to notify that there is the undervoltage in
the system and find the cause timely to prevent from further deterioration of the fault.
Each stage of phase undervoltage protection can be independently set as definite-time

characteristics or inverse-time characteristics. The dropout characteristics can be set as
instantaneous dropout and definite-time dropout.
Phase voltage or phase-to-phase voltage can be selected to be used by the protection calculation
via the setting [x.27P.Opt_Up/Upp]. “1-out-of-3” or “3-out-of-3” logic can be selected for the
protection criterion. (1-out-of-3 means any of three phase voltages, 3-out-of-3 means all three
phase voltages). The circuit breaker position with/without the current condition can be as an
auxiliary criterion for phase undervoltage protection, which can be configured via the setting
[x.27P.Opt_LogicMode].

EN [x.27Pi.En] &
x.27Pi.On
SIG x.27Pi.Enable
&
SIG x.27Pi.Block >=1 x.27Pi.Blocked
SIG Fail_Device
&
x.27Pi.Valid
3 Figure 3.17-1 Logic of enabling phase undervoltage protection
Phase undervoltage protection can be enabled or disabled via the settings or the signals, for
some specific applications, phase undervoltage protection needs to be blocked by the external
signal, so the device provides an input signal to be used to block phase undervoltage protection.
The pickup logic of phase overvoltage protection is shown in Figure 3.17-2.
&
SET [x.27P.Opt_Up/Upp]=Upp
SET x.Uab<[x.27Pi.U_Set]
&
SET x.Ubc<[x.27Pi.U_Set]
SET x.Uca<[x.27Pi.U_Set]
>=1
&
SET x.Uab<[x.27Pi.U_Set]
>=1
SET x.Ubc<[x.27Pi.U_Set]
SET x.Uca<[x.27Pi.U_Set]
&
SET [x.27P.Opt_Up/Upp]=Up
SET x.Ua<[x.27Pi.U_Set]
&
SET x.Ub<[x.27Pi.U_Set] >=1
>=1 Voltage criterion
SET x.Uc<[x.27Pi.U_Set]
&
SET x.Ua<[x.27Pi.U_Set]
>=1
SET x.Ub<[x.27Pi.U_Set]
SET x.Uc<[x.27Pi.U_Set]

SET [x.27P.Opt_LogicMode]=None
SET [x.27P.Opt_LogicMode]=Curr & >=1

>=1
SIG x.Ip>0.04In Auxiliary criterion
SET [x.27P.Opt_LogicMode]=CBPos &
SIG CB closed position
>=1
&
>=1 3
SET [x.27P.Opt_LogicMode]=CurrOrCBPos
&
&
SET [x.27P.Opt_LogicMode]=CurrAndCBPos
SIG Voltage criterion

& x.27Pi.Pkp
SIG Auxiliary criterion 0 500ms &
&
SIG x.VTS.Alm & FD.Pkp
&
EN [x.27Pi.En_VTS_Blk]
SIG x.27Pi.On
SIG x.27Pi.Valid
Figure 3.17-2 Pickup logic of phase undervoltage protection
Phase undervoltage protection can operate with a fixed time delay. It can also operate with
inverse-time characteristics, and its characteristics curve complies with the standards IEC
60255-3 and ANSI C37.112. Phase overvoltage protection can support definite-time
characteristics, IEC & ANSI standard inverse-time characteristics and user-defined inverse-time
characteristics, which are determined by the setting [x.27Pi.Opt_Curve] (i=1 or 2). The
relationship between the setting and the characteristics curve is shown in the table below.
27Px.Opt_Curve Time Characteristic k α c

ANSIDefTime ANSI Definite time - - -
IECDefTime IEC Definite time - - -
UserDefine UserDefine
InvTime_U Voltage inverse 1 1 0

When the setting [x.27Pi.Opt_Curve] is set as “ANSIDefTime” or “IECDefTime”, the operating

characteristics is definite-time phase undervoltage protection. When the setting
[x.27Pi.Opt_Curve] is set as "UserDefine", it means that user-defined inverse-time characteristics
is selected. These settings [x.27Pi.K], [x.27Pi.C] and [x.27Pi.Alpha] are valid, and the inverse-time
operating curve is determined by the three settings. When the setting [x.27Pi.Opt_Curve] is set as
“InvTime_U”, the settings [x.27Pi.K], [x.27Pi.C] and [x.27Pi.Alpha] are useless.
When U<[x.27Pi.U_Set], phase undervoltage protection operates with a time delay [x.27Pi.t_Op],
the operating characteristics curve is as shown in Figure 3.17-3.
3 t
[x.27Pi.t_Op]
U
[x.27Pi.U_Set]
Figure 3.17-3 Definite-time operating curve of phase undervoltage protection
 Inverse-time characteristic
When x.U<[x.27Pi.U_Set], phase undervoltage protection begins to accumulate, and the

operating time is affected by the applied voltage x.U. The operating time will decrease with the
voltage decreasing, but the operating time shall not less than the setting [x.27Pi.tmin] (i=1 or 2).
The inverse-time operating characteristics equation is:
Where:
UP is the voltage setting [x.27Pi.U_Set].
TMS is the inverse-time time multiplier, i.e. the setting [x.27Pi.TMS].
K is the inverse-time coefficient, i.e. the setting [x.27Pi.K].

C is the inverse-time coefficient, i.e. the setting [x.27Pi.C].
α is the inverse-time coefficient, i.e. the setting [x.27Pi.Alpha].
x.U is the measured voltage.
[x.27Pi.tmin]
U
UD [x.27Pi.U_Set]
Figure 3.17-4 Inverse-time operating curve of phase undervoltage protection
When the applied voltage is not a fixed value, but changes with the time, the operating behavior of
inverse-time phase undervoltage protection is shown in the following equation.
Where:
t(x.U) is the theoretical operating time when the voltage is x.U.
The supported dropout characteristics of phase undervoltage protection include instantaneous

and definite-time characteristics.
When x.U>[x.27Pi.K_DropOut]×[x.27Pi.U_Set], phase undervoltage protection drops out

immediately.
When x.U>[x.27Pi.K_DropOut]×[x.27Pi.U_Set], phase undervoltage protection drops out with a

time delay [x.27Pi.t_DropOut], and the sequence diagram of definite-time dropout characteristic
among start signal, operating signal and the counter is as shown in Figure 3.17-5.
Start time
x.U<[x.27Pi.U_Set]
x.27Pi.St
3
x.27Pi.Op
[x.27Pi.t_Op] Phase undervoltage

Operating counter
[x.27Pi.t_DropOut]
[x.27Pi.t_DropOut] [x.27Pi.t_DropOut]
Dropout time
Dropout time
Figure 3.17-5 Definite-time dropout characteristics of phase undervoltage protection

27P
x.27Pi.in_U3P x.27Pi.On
x.27Pi.Enable x.27Pi.Blocked
x.27Pi.Block x.27Pi.Valid
x.27Pi.St
x.27Pi.StA
x.27Pi.StB 3
x.27Pi.StC
x.27Pi.Op
X.27Pi.Op.PhA
x.27Pi.Op.PhB
x.27Pi.Op.PhC
x.27Pi.Alm
3.17.3 I/O Signal

Table 3.17-1 Input signals of phase undervoltage protection

1 x.27Pi.in_U3P Three-phase voltage data input for phase undervoltage protection (i=1 or 2)
2 x.27Pi.Enable Input signal of enabling stage i of phase undervoltage protection (i=1 or 2)
3 x.27Pi.Block Input signal of blocking stage i of phase undervoltage protection (i=1 or 2)
Table 3.17-2 Output signals of phase undervoltage protection

1 x.27Pi.On Stage i of phase undervoltage protection is enabled. (i=1 or 2)
2 x.27Pi.Blocked Stage i of phase undervoltage protection is blocked. (i=1 or 2)
3 x.27Pi.Valid Stage i of phase undervoltage protection is valid. (i=1 or 2)
4 x.27Pi.St Stage i of phase undervoltage protection starts. (i=1 or 2)
5 x.27Pi.StA Stage i of phase-A undervoltage protection starts. (i=1 or 2)
6 x.27Pi.StB Stage i of phase-B undervoltage protection starts. (i=1 or 2)
7 x.27Pi.StC Stage i of phase-C undervoltage protection starts. (i=1 or 2)
8 x.27Pi.Op Stage i of phase undervoltage protection operates. (i=1 or 2)
9 x.27Pi.Op.PhA Stage i of phase-A undervoltage protection operates. (i=1 or 2)
10 x.27Pi.Op.PhB Stage i of phase-B undervoltage protection operates. (i=1 or 2)
11 x.27Pi.Op.PhC Stage i of phase-C undervoltage protection operates. (i=1 or 2)
12 x.27Pi.Alm Stage i of phase undervoltage protection alarm. (i=1 or 2)

3.17.4 Logic
SIG Voltage criterion x.27Pi.St

&
SIG Auxiliary criterion & Timer
t
t
SIG x.VTS.Alm &
&
EN [x.27Pi.En_VTS_Blk]
SIG x.27Pi.On
&
3 SIG x.27Pi.Pkp
x.27Pi.Op
&
x.27Pi.Alm
Figure 3.17-6 Logic of phase undervoltage protection
3.17.5 Settings
Table 3.17-3 Settings of phase undervoltage protection

The option of the
voltage criterion used
3P by phase undervoltage
1 x.27P.Opt_1P/3P - 3P
1P protection
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
The option of the
calculation voltage used
by phase undervoltage
Up
2 x.27P.Opt_Up/Upp - Up protection
Upp
Up: phase voltage
Upp: phase-to-phase
voltage
The option of auxiliary
criterion mode for
None
phase undervoltage
Curr
protection
3 x.27P.Opt_LogicMode CBPos - CurrAndCBPos
None: no check
CurrOrCBPos
Curr: check current
CurrAndCBPos
condition
CBPos: check normally


open auxiliary contact
CurrOrCBPos: check
current condition or
normally open auxiliary
contact
CurrAndCBPos: check
current condition and
contact
The voltage setting for
stage i of phase
3
4 x.27Pi.U_Set 5.000~120.000 V 80
undervoltage protection
(i=1 or 2)
The dropout coefficient
for stage i of phase
5 x.27Pi.K_DropOut 1.000 ~1.200 - 1.03
(i=1 or 2)
The operating time
6 x.27Pi.t_Op 0.100~100.000 s 1
phase undervoltage
The dropout time delay
7 x.27Pi.t_DropOut 0.000~100.000 s 0
(i=1 or 2)
Enabling/Disabling
stage i of phase
Disabled is blocked by VT circuit
8 x.27Pi.En_VTS_Blk - Disabled
Enabled failure when VT circuit
supervision is enabled
and VT circuit fails (i=1
or 2)
Enabling/disabling
Disabled stage i of phase
9 x.27Pi.En - Enabled
Enabled undervoltage protection
(i=1 or 2)
Enabling/disabling
stage i of phase
Trp undervoltage protection
10 x.27Pi.Opt_Trp/Alm - Trp
Alm operate to trip or alarm
(i=1 or 2)


The option of operating
ANSIDefTime
IECDefTime
11 x.27Pi.Opt_Curve - IECDefTime stage i of phase
UserDefine
InvTime_U
(i=1 or 2)
stage i of phase
3 12 x.27Pi.Opt_Curve_DropOut
Inst
- Inst
(i=1 or 2)
DefTime
Inst: instantaneous
Time multiplier setting
for stage i of
13 x.27Pi.TMS 0.040~20.000 - 1 inverse-time phase
(i=1 or 2)
time for stage i of
14 x.27Pi.tmin 0.030~10.000 s 0.03 inverse-time phase
(i=1 or 2)
15 x.27Pi.K 0.0010~120.0000 - 0.14 inverse-time phase
(i=1 or 2)
16 x.27Pi.Alpha 0.0100~3.0000 - 0.02 inverse-time phase
(i=1 or 2)
The constant “C” for
17 x.27Px.C 0.0000~1.0000 - 0 inverse-time phase
(i=1 or 2)

3.18 Overfrequency Protection (81O)
Frequency is an important index of the power quality, which can reflect the balance of the output
power of the generator and the active power of the load. The increase of frequency indicates that
the output power of the system is much larger than that of the load. When the system frequency is
greater than the predefined setting, the overfrequency protection will operate for removing some
part of active power supplies from the system.
The device can provide two stages of overfrequency protection. If the system frequency is greater
than the setting, overfrequency protection will operate to remove some part of active power
3
supplies from the system. Overfrequency protection is with independent definite-time
characteristics and with instantaneous dropout characteristics.
Overfrequency protection can be enabled or disabled by the settings and the signals. For some
specific applications, overfrequency protection needs to be blocked by the external signal, so the
device provides an input signal to be used to block overfrequency protection.
EN [81Oi.En] &
81Oi.On
SIG 81Oi.Enable
&
SIG 81Oi.Block >=1 81Oi.Blocked
SIG Fail_Device
&
81Oi.Valid
Figure 3.18-1 Logic of enabling overfrequency protection
The pickup logic of overfrequency protection is shown in Figure 3.18-2.
SET f>[81Oi.f_Set] &

&
SET Upp_min>[81.Upp_Blk] 0 500ms & FD.Pkp
SIG 81Oi.On 81Oi.Pkp
SIG 81Oi.Valid
Figure 3.18-2 Pickup logic of overfrequency protection
3.18.1.1 Operation Characteristics
Overfrequency protection supports definite-time characteristics complied with IEC 60255-3 and
ANSI C37.112. If the system frequency is greater than the setting [81Oi.f_Set], overfrequency
protection will operate with a time delay [81Oi.t_Op].

The operating characteristics curve of overfrequency protection is shown in Figure 3.18-3.
3 [81Oi.t_Op]
f
[81Oi.f_Set]
Figure 3.18-3 Definite-time operating curve of overfrequency protection
Overfrequency protection is with instantaneous dropout characteristics. If the system frequency is

less than the setting [81Oi.f_Set], overfrequency protection will drop out immediately.
81O
81Oi.In_U3P 81Oi.On
81Oi.Enable 81Oi.Blocked
81Oi.Block 81Oi.Valid
81Oi.St
81Oi.Op
Figure 3.18-4 Function block diagram of overfrequency protection
3.18.3 I/O Signals

Table 3.18-1 Input signals of overfrequency protection

1 81Oi.in_U3p Three-phase voltage data input for overfrequency protection (i=1~2)
2 81Oi.Enable Input signal of enabling stage i of overfrequency protection (i=1~2)
3 81Oi.Block Input signal of blocking stage i of overfrequency protection (i=1~2)
Table 3.18-2 Output signals of overfrequency protection


1 81Oi.On Stage i of overfrequency protection is enabled. (i=1~2)
2 81Oi.Blocked Stage i of overfrequency protection is blocked. (i=1~2)
3 81Oi.Valid Stage i of overfrequency protection is valid. (i=1~2)
4 81Oi.St Stage i of overfrequency protection starts. (i=1~2)
5 81Oi.Op Stage i of overfrequency protection operates. (i=1~2)
3.18.4 Logic
SET f>[81Oi.f_Set] & 81Oi.St
SET Upp_min>[81.Upp_Blk]
&
[81Oi.t_Op] 0 81Oi.Op
3
SIG 81Oi.Pkp
Figure 3.18-5 Logic of overfrequency protection
3.18.5 Settings
Table 3.18-3 Settings of overfrequency protection

The phase-to-phase voltage setting used to
1 81Oi.Upp_VCE 10.000~150.000 V 70 block stage i of overfrequency protection
(i=1~2)
The frequency setting for stage i of
2 81Oi.f_Set 50.000~65.000 Hz 52
overfrequency protection (i=1~2)
The time delay for stage i of overfrequency
3 81Oi.t_Op 0.100~100.000 s 0.3
protection (i=1~2)
Disabled Enabling/disabling stage i of overfrequency
4 81Oi.En - Enabled
Enabled protection (i=1~2)
3.19 Underfrequency Protection (81U)
Frequency is an important index of the power quality, which can reflect the balance of the output
power of the generator and the active power of the load. The decrease of frequency indicates that
the output power of the system is much less than that of the load. When the system frequency is
less than the predefined setting, the underfrequency protection will operate for shedding some
part of loads from the system.
The device can provide four stages of underfrequency protection. If the system frequency is less
than the setting, underfrequency protection will operate to shedding some part of loads from the
system. Underfrequency protection is with independent definite-time characteristics and with
instantaneous dropout characteristics.

Underfrequency protection can be enabled or disabled by the settings and the signals. For some
specific applications, underfrequency protection needs to be blocked by the external signal, so the
device provides an input signal to be used to block underfrequency protection.
EN [81Ui.En] &
81Ui.On
SIG 81Ui.Enable
&
SIG 81Ui.Block >=1 81Ui.Blocked
SIG Fail_Device
&
3 81Ui.Valid
Figure 3.19-1 Logic of enabling underfrequency protection
The pickup logic of underfrequency protection is shown in Figure 3.19-2.
SET f<[81Ui.f_Set] &

&
SET Upp_min>[81.Upp_Blk] 0 500ms & FD.Pkp
SIG 81Ui.On 81Ui.Pkp
SIG 81Ui.Valid
Figure 3.19-2 Pickup logic of underfrequency protection
3.19.1.1 Operation Characteristics
Underfrequency protection supports definite-time characteristics complied with IEC 60255-3 and
ANSI C37.112. If the system frequency is greater than the setting [81Ui.f_Set], underfrequency
protection will operate with a time delay [81Ui.t_Op].
The operating characteristics curve of underfrequency protection is shown in Figure 3.19-3.

[81Ui.t_Op]
f
[81Ui.f_Set]
Figure 3.19-3 Definite-time operating curve of underfrequency protection
Underfrequency protection is with instantaneous dropout characteristics. If the system frequency

is less than the setting [81Oi.f_Set], underfrequency protection will drop out immediately.
81U
81Ui.in_U3P 81Ui.On
81Ui.Enable 81Ui.Blocked
81Ui.Block 81Ui.Valid
81Ui.St
81Ui.Op
Figure 3.19-4 Function block diagram of underfrequency protection
3.19.3 I/O Signals

Table 3.19-1 Input signals of underfrequency protection

1 81Ui.in_U3P Three-phase voltage data input for underfrequency protection (i=1~4)
2 81Ui.Enable Input signal of enabling stage i of underfrequency protection (i=1~4)
3 81Ui.Block Input signal of blocking stage i of underfrequency protection (i=1~4)
Table 3.19-2 Output signals of underfrequency protection


1 81Ui.On Stage i of underfrequency protection is enabled. (i=1~4)
2 81Ui.Blocked Stage i of underfrequency protection is blocked. (i=1~4)
3 81Ui.Valid Stage i of underfrequency protection is valid. (i=1~4)
4 81Ui.St Stage i of underfrequency protection starts. (i=1~4)
5 81Ui.Op Stage i of underfrequency protection operates. (i=1~4)
3.19.4 Logic
SET f>[81Ui.f_Set] & 81Ui.St
3 SET Upp_min>[81.Upp_Blk]
&
[81Ui.t_Op] 0 81Ui.Op
SIG 81Ui.Pkp
Figure 3.19-5 Logic of underfrequency protection
3.19.5 Settings
Table 3.19-3 Settings of underfrequency protection

1 81Ui.Upp_VCE 10.000~150.000 V 70 block stage i of underfrequency protection
(i=1~4)
2 81Ui.f_Set 45.000~60.000 Hz 48
underfrequency protection (i=1~4)
The time delay for stage i of underfrequency
3 81Ui.t_Op 0.100~100.000 s 0.3
protection (i=1~4)
Disabled Enabling/disabling stage i of underfrequency
4 81Ui.En - Enabled
3.20 VT Circuit Supervision (VTS)

The purpose of VT circuit supervision is to detect whether VT circuit is normal. Some protection
functions should be disabled when VT circuit fails.
VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault,
poor contact of VT circuit, VT maintenance and so on. The device can detect them and issue an
alarm signal to block relevant protection functions. However, the alarm of VT circuit failure should
not be issued when the following cases happen.
1. Bus VT or bay VT is used as protection VT and the protected bus or bay is out of service.
2. Only current protection functions are enabled and VT is not connected to the device.


by default.
VT circuit supervision can detect failure of single-phase, two-phase and three-phase on protection
VT. Under normal condition, the device continuously supervises input voltage from VT, VT circuit
failure signal will be activated if residual voltage exceeds the threshold value or positive-sequence
voltage is lower than the threshold value. If the device is under pickup state due to system fault or
other abnormality, VT circuit supervision will be disabled.
Under normal conditions, the device detect residual voltage greater than the setting 3
[x.VTS.3U0_Set] to determine single-phase or two-phase VT circuit failure, and detect three times
positive-sequence voltage less than the setting [x.VTS.U1_Set] to determine three-phase VT
circuit failure. Upon detecting abnormality on VT circuit, an alarm will comes up after a time delay
of [x.VTS.t_DPU] and drop off with a time delay of [x.VTS.t_DDO] after VT circuit restored to
normal.
VT (secondary circuit) MCB auxiliary contact as a binary input can be connected to the binary
input circuit of the device. If MCB is open (i.e. [x.VTS.MCB_VT] is energized), the device will
consider the VT circuit is not in a good condition and issues an alarm without a time delay. If the
auxiliary contact is not connected to the device, VT circuit supervision will be issued with time
delay as mentioned in previous paragraph.
When VT is not connected into the device, the alarm will be not issued if the logic setting [x.En_VT]
is set as "0". However, the alarm is still issued if the binary input [x.VTS.MCB_VT] is energized, no
matter that the logic setting [x.En_VT] is set as "0" or "1".
When neutral VT fails, third harmonic of residual voltage is comparatively large. If third harmonic
amplitude of residual voltage is larger than the setting [x.VTNS.3U0_Hm3_Set] and without
operation of fault detector element, neutral VT failure alarm signal [x.VTNS.Alm] will be issued
after a time delay of [x.VTS.t_DPU] and drop off with a time delay of [x.VTS.t_DDO] after three
phases voltage restored to normal.

3.20.2 Function Block
VTS VTNS
x.VTS.in_U3P x.VTNS.Enable
x.VTS.in_I3P x.VTNS.Block
x.VTS.Enable
x.VTS.Block
x.VTS.MCB_VT
3 x.VTS.in_52b_a
x.VTS.in_52b_b
x.VTS.in_52b_b
3.20.3 I/O Signals

Table 3.20-1 Input signals of VT circuit supervision

1 x.VTS.in_U3P Three-phase voltage data input
2 x.VTS.in_I3P Three-phase current data input
3 x.VTS.Enable VT circuit supervision enabling input
4 x.VTS.Block VT circuit supervision blocking input
5 x.VTS.MCB_VT Binary input for VT MCB auxiliary contact
Binary input of auxiliary normally open contact of phase-A circuit breaker at x
6 x.VTS.in_52b_a
side of transformer
Binary input of auxiliary normally open contact of phase-B circuit breaker at x
7 x.VTS.in_52b_b
side of transformer
Binary input of auxiliary normally open contact of phase-C circuit breaker at x
8 x.VTS.in_52b_c
side of transformer
9 x.VTNS.Enable Neutral VT circuit supervision enabling input
10 x.VTNS.Block Neutral VT circuit supervision blocking input

3.20.4 Logic
&
SIG FD.Pkp
SET x.3U0>[x.VTS.3U0_Set]
>=1
SET x.U1<[x.VTS.U1_Set] &
>=1 If "FD.Pkp" operates, the circuit of time
SET [x.VTS.Opt_VT]=Bay & delay will be interrupted.
[x.VTS.t_DPU] [x.VTS.t_DDO]
SIG 52b (Three phases) >=1
&
SIG x.Ip > 0.04In
>=1
BI [x.BI_En_VT] >=1
3
x.VTS.Alm
EN [x.En_VT]
SIG [x.VTS.MCB_VT] &
EN [x.VTS.En]
&
SIG x.VTS.Enable
SIG x.VTS.Block
Figure 3.20-1 VT circuit supervision logic diagram
Ip is one measured phase current, i.e. Ia or Ib or Ic.
In is the rated phase current value.
&
SIG FD.Pkp
SET x.U03>[x.VTNS.3U0_Hm3_Set] If "FD.Pkp" operates, then circuit of

time delay will be interrupted.
& >=1
EN [x.En_VT] [x.VTS.t_DPU] [x.VTS.t_DDO] & x.VTNS.Alm
BI [x.BI_En_VT]
EN [x.VTNS.En]
&
SIG x.VTNS.Enable
SIG x.VTNS.Block
Figure 3.20-2 Neutral VT supervision logic diagram
x.U03: third harmonic amplitude of neutral point residual voltage.
If fault detector element operates or automatic reclosing cycle is in progress, and VT circuit failure
signal have been detected, then the VT circuit failure signal will be maintained, only when the fault
detector element and automatic reclosing element are all drop-off, VT circuit supervision will
return to normal operation.
3.20.5 Settings

Table 3.20-2 Settings of VT circuit supervision
No. Name Range Unit Default Remark

Disabled
1 x.VTS.En - Enabled Enabling/disabling VT circuit supervision
Enabled
Voltage selection for protection
Bus calculation from busbar VT or bay VT
2 x.VTS.Opt_VT - Bus
Bay Bus: busbar VT
Bay: bay VT
Pickup time delay of VT circuit
3 x.VTS.t_DPU 0.000~30.000 s 1.500
supervision
3 Dropoff time delay of VT circuit
4 x.VTS.t_DDO 0.000~30.000 s 10.000
supervision
Positive-sequence voltage setting of VT
5 x.VTS.U1_Set 0.00~100.00 V 30.00
circuit supervision
Zero-sequence voltage setting of VT
6 x.VTS.3U0_Set 0.00~100.00 V 8.00
circuit supervision
Disabled Alarm function of VT neutral circuit
7 x.VTNS.En - Enabled
Enabled supervision
Pickup time delay of neutral VT circuit
8 x.VTNS.t_DPU 0.000~30.000 s 1.500
supervision
Dropoff time delay of neutral VT circuit
9 x.VTNS.t_DDO 0.000~30.000 s 10.000
supervision
Zero-sequence voltage setting (third
10 x.VTNS.3U0_Hm3_Set 0.00~100.00 V 20.00 harmonic component) of neutral VT
circuit supervision
3.21 Output Map (OutMap)
Output map controls tripping outputs of protection elements and programmable logics. Each
protection element has its corresponding tripping logic setting used to configure tripping output
contacts, and 120 tripping outputs of programmable logics are equipped for visual logic
programming.

All tripping output contacts are with a settable dwell time to ensure sufficient time of tripping
command to open the circuit breaker.
3.21.1.1 Protection Element Trip Output
Each protection element can control total 32 groups of tripping output contacts by tripping logic
settings. Therefore, the user can configure the tripping output contacts of each protection element
individually though the corresponding tripping logic setting. 32 groups of independent tripping
output contacts can be defined to trip HV side, MV side, and LVS side etc. Each group of tripping
contacts can correspond to certain amount of contacts on binary output plug-in modules.

Tripping logic settings are used to specify which breakers will be tripped when some protection
element operates. This logic setting comprises 32 binary bits as follows and is expressed by a
hexadecimal number of 8 digits from 00000000H to FFFFFFFFH. The tripping logic setting is
specified as follows:
Bit Definition Bit Definition

0 Output001 16 Output017
5 Output006 21 Output022 3
“Output001” just means to drive 1st group of tripping output contacts and please refer to Chapter
“Hardware”. The tripping outputs are recorded as “Output001_OutMap ~ Output032_OutMap” by
the device when they operate, and “Outputxxx” (xxx=001, 002…032) represents “trip output xxx”
(xxx=001, 002…032). The circuit breaker corresponding with bit which is set as “1” will be tripped.
Tripping output logic settings should be set on basis of application-specific drawings.
For example, if transformer differential protection operates to make “Output001”, “Output002”,

“Output003” contacts pickup, bit “0”, bit “1” and bit “2” shall be filled with “1” and other bits shall be
filled with “0”. Then a hexadecimal number 00000007H is formed as the tripping output logic
setting, i.e. [87T.OutMap] shall be set as “00000007H”.
3.21.1.2 Programmable Trip Output
The device provides 120 programmable trip output with I/O signals and settings for users used by
visualization programming.
For example, if it is required to set stage 1 of phase overcurrent protection at HV side of the
transformer operate to issue trip command after its operation criterion is satisfied “AND” receiving
a binary input which can be a blocking signal from other device, programmable trip output can
complete the function configuration as following steps.
1. Finish required programming logic by PCS-Studio
2. Connect final output of programming logic to input signal of programmable trip output.

3. Set corresponding tripping logic setting of programmable trip output to complete the function
configuration.
3.21.2 I/O Signals

Table 3.21-1 I/O signals of programmable trip output

Outputxxx_OutMap
1 Input signal of programmable tripping output element xxx.
(xxx=001, 002…032)
3.21.3 Settings
3 Table 3.21-2 Settings of programmable trip output

OutMapxxx 00000000~ Tripping logic setting of programmable trip output
1 - 0
(xxx=001, 002…120) FFFFFFFF map xxx
t_Dwell_xxx_OutMap The pulse width setting of programmable trip
2 0.000~0.500 s 0.060
(xxx=001, 002…032) output map xxx

4 Control Functions
4 Control Functions
Table of Contents
4.1 Switchgear Control .......................................................................................... 4-1

4.1.1 Functional Description .......................................................................................................... 4-1
4.1.2 Operation Theory.................................................................................................................. 4-2
4.1.4 I/O Signals ............................................................................................................................ 4-5
4.1.5 Logics ................................................................................................................................... 4-7

4
4.1.6 Settings ................................................................................................................................. 4-8
4.2 Manual Closing Synchronism Check ............................................................. 4-9

4.2.1 Operation Theory.................................................................................................................. 4-9
4.2.3 I/O Signals .......................................................................................................................... 4-11
4.2.4 Logics ................................................................................................................................. 4-12
4.2.5 Settings ............................................................................................................................... 4-13
4.3 Voltage Switching .......................................................................................... 4-14

4.3.1 Functional Description ........................................................................................................ 4-15
4.3.3 I/O Signals .......................................................................................................................... 4-16
4.3.4 Logics ................................................................................................................................. 4-17
4.3.5 Settings ............................................................................................................................... 4-18
4.4 Tap Changer Indicator ................................................................................... 4-18

4.4.3 I/O Signals .......................................................................................................................... 4-19
4.4.4 Settings ............................................................................................................................... 4-20
List of Figures

4 Control Functions
Figure 4.1-1 Logic diagram of switchgear control ................................................................. 4-2
Figure 4.1-2 DPS synthesis logic ............................................................................................. 4-7
Figure 4.1-3 DPS alarm logic .................................................................................................... 4-7
Figure 4.1-4 Trip statistics triggering logic ............................................................................ 4-7
Figure 4.1-5 Interlocking logic ................................................................................................. 4-8
Figure 4.1-6 Manual control logic ............................................................................................ 4-8
Figure 4.2-1 Relationship between reference and synchronous voltages ....................... 4-10
Figure 4.2-2 Synchro-check logic .......................................................................................... 4-12
Figure 4.2-3 Dead charge check logic ................................................................................... 4-13
Figure 4.3-1 Voltage connection for double busbar arrangement ..................................... 4-15
4 Figure 4.3-2 Voltage connection for one and a half breakers arrangement ..................... 4-15
Figure 4.3-3 Voltage switching for double bus bar arrangement ....................................... 4-17
Figure 4.3-4 Voltage switching for 3/2 breakers arrangement (closing a bus CB) .......... 4-17
Figure 4.3-5 Voltage switching for 3/2 breakers arrangement (closing the tie CB) ......... 4-18
List of Tables
Table 4.1-1 Remote/Local control mode switch logic............................................................ 4-3
Table 4.1-2 Input signals of control function .......................................................................... 4-5
Table 4.1-3 Output signals of control function....................................................................... 4-6
Table 4.1-4 Settings of control function .................................................................................. 4-8
Table 4.2-1 Input signals of manual closing synchronism check ...................................... 4-11
Table 4.2-2 Output signals of manual closing synchronism check ................................... 4-12
Table 4.2-3 Settings of synchronism check ......................................................................... 4-13
Table 4.3-1 Input signals of voltage switching ..................................................................... 4-16
Table 4.3-2 Output signals of voltage switching .................................................................. 4-16
Table 4.3-3 Settings of voltage switching ............................................................................. 4-18
Table 4.4-1 Input signals of tap changer indicator .............................................................. 4-19
Table 4.4-2 Output signals of tap changer indicator ........................................................... 4-20
Table 4.4-3 Settings of tap changer indicator ...................................................................... 4-20

4 Control Functions
4.1 Switchgear Control

The switchgear control function is mainly used to realize operation of primary equipment such as
circuit breaker (CB), disconnect switch (DS) and earthing switch (ES). This function can be
divided into remote control and local control according to the control source location. A remote
control mainly refers to remote control commands from substation automation system (SAS) or
network control center (NCC). However, a control triggered manually from the device LCD, by a
terminal contact or by a panel handle is a local control. The switchgear control function is closely
related to interlocking, double point status (DPS), remote/local control mode switching and
tripping statistics.
4.1.1 Functional Description
A control command can realize various control signals such as the CB/DS/ES opening/closing. In
order to ensure the reliability of the control output, a locking circuit is added to each control object.
The operation is strictly in accordance with the selection, check and execution steps, to ensure 4
that the control operation can be safely and reliably implemented. In addition, the device has a
hardware self-checking and blocking function to prevent hardware damage from maloperation
output.
When the device is in the remote-control mode, the control command may be sent via the IEC
60870-5-103 or IEC 61850 protocol; when it is in the local control mode, the local operation may
be performed on the device LCD or panel handle.
A complete control process is:
1. Protocol module sends a selection command;
2. Control module responds the success or failure result of selection;
3. If the selection is successful, the protocol module sends an execution command, otherwise it
sends a cancel command;
4. Control module responds the success or failure result of execution;
5. The control operation may be open/close or up/down/stop.
When the device is in the maintenance status, it can still respond to local control commands.
The switchgear control function can cooperate with functions such as synchronism check and
interlocking criteria calculation to complete the output of the corresponding operation command. It
can realize the normal control output in one bay and the interlocking and programmable logic
configuration between bays.
This device supports the following functional control module:
Module Description
CSWI Control of circuit breaker (CB), disconnector switch (DS) or earthing switch (ES)
RMTLOC Remote or local control mode
XCBR Synthesis of CB position, three-phase or phase separated

4 Control Functions
Module Description
XSWI Synthesis of DS/ES position
SXCBR/SCSWI Trip statistics of CB/DS/ES
RSYN Synchronism check for CB closing
CILO Interlocking logic for CB/DS/ES control
MCSWI Manual control of CB/DS/ES
4.1.2 Operation Theory
The initiation of a control command may be sent to the device by the SCADA or the NCC through
protocol IEC 60870-5-103 or IEC 61850. It may also be the operation of the device LCD or the
manual triggering through configured signal. The command is sent by the CPU to the control
module for processing, and a control record is made on the CPU module according to the control
result.
4
SCADA/NCC IEC 60870-5-103
CPU
CSWI BO
IEC 61850
Control
Record
Local LCD
BI contact
Figure 4.1-1 Logic diagram of switchgear control
4.1.2.1 Remote/Local Control Mode Switch
Since the source of a control command may be SAS or NCC, or may be triggered by the device
LCD or terminal contact, it is necessary to provide a remote/local control mode switch function.
The remote/local control mode switch function determines whether the device is in the remote or
the local control permission state through the configuration of terminal contact, function key, or
binary signal. Each control object provides a remote/local input, and the control module
determines the current control authority to be remote or local according to the input value. By
default, if the input is not configured, any control operation is blocked.

4 Control Functions
Table 4.1-1 Remote/Local control mode switch logic
in_Remote in_Local Remote Control Local Control

NULL NULL Disable Disable
0 NULL Disable Enable
1 NULL Enable Disable
NULL 0 Enable Disable
NULL 1 Disable Enable
0 0 Disable Disable
0 1 Disable Enable
1 0 Enable Disable
1 1 Enable Enable
4.1.2.2 Double Point Status
A double point status (DPS), which usually indicates switchgear status, can be derived from 2
ordinary binary inputs. The signification of a DPS is shown in the following table. For switchgear
4
status, only the 2 statuses "01" and "10" indicating respectively the positions opening and closing
are valid. The other 2 statuses "00" and "11", i.e. intermediate or bad status, will cause the alarm
"DPS.Alm".
DPS Bit0 = 0 Bit0 = 1

Bit1 = 0 DPS_INT DPS_OFF
Bit1 = 1 DPS_ON DPS_BAD
The unit also supports the DPS synthesis through switchgear opening and closing positions after
jittering processing. The synthetic DPS contains original SOE timestamp. The CB control function
supports phase-separated position inputs and can synthesize these inputs into general position.
In accordance with the control object, the DPS synthesis function is divided into 2 modules: XCBR
and XSWI. The XCBR is mainly used for CB position synthesis, including phase-separated
positions, while the XSWI is used DS or ES position synthesis.
4.1.2.3 Trip Statistics
The trip statistics function takes the opening position as input count the trip times. For CB, this
device supports phase-separated and general trip statistics. The tripping statistics function is
triggered by DPS change. The statistics result is stored in non-volatile memory for power-off
holding.
Use the clear command from the menu in local LCD or customized binary signal to reset the trip
statistics.
4.1.2.4 Interlocking
The interlocking function will influence the control operation output. When the function is enabled,
the device determines whether the control operation is permitted based on the interlocking logic
result. Each control object is equipped with an independent interlocking logic which supports
unlocking operation through a binary signal.

4 Control Functions
The interlocking function is very important for the control operation of switchgears. During the
operation of primary equipment, the positions of the relevant equipment must be correct for
operation permission. For remote control, i.e. command from SAS or NCC, this device could
judge the interlocking logic depending on the message within the command; for local control
through device LCD or terminal contact, please use the corresponding logic setting to
enable/disable the interlocking function.
4.1.2.5 Manual Control
The switchgear control function supports manual control function that can be configured with a
terminal contact or binary signal to trigger the control operation.
The manual control function supports the control input configuration of selection and open/close.
When the control object selection input is configured, the signal "1" indicates that the current
control object has to be selected before a control operation; if the control object selection input is
not configured, the control command can be directly issued without judgment of selection.
4 4.1.2.6 Direct Control
For applications such as signal reset and function enable/disable, the control mode is generally
direct control, i.e. execution without selection before, direct control with normal security in IEC
61850.
The direct control function provides remote/local switch and interlocking configurations. The
control command is usually issued directly by the SAS. It also supports the command triggered by
binary signal.

4 Control Functions
CSWI：XCBR CSWI：XSWI
in_Remote in_Remote
in_Local in_Local
in_Pos_NO in_Pos_NO
in_Pos_NC
in_Pos_NC
in_Pos_A_NO
in_N_Trp
in_Pos_A_NC
in_EnaOpn
in_Pos_B_NO
in_Pos_B_NC in_EnaCls
in_Pos_C_NO in_CILO_Bypass
in_Pos_C_NC in_Manual_Sel 4
in_N_Trp
in_Manual_Opn
in_N_Trp_A
in_Manual_Cls
in_N_Trp_B
in_N_Trp_C
in_Rsyn
in_EnaOpn
in_EnaCls
in_CILO_Bypass
in_Manual_Sel
in_Manual_Opn
in_Manual_Cls
4.1.4 I/O Signals

Table 4.1-2 Input signals of control function

1 in_Remote Remote control mode
2 in_Local Local control mode
3 in_Pos_NO Normally opened contact input for DPS opening position
4 in_Pos_NC Normally closed contact input for DPS closing position
Phase A normally opened contact input for DPS opening position (only valid in CSWI:
5 in_Pos_A_NO
XCBR)
Phase A normally closed contact input for DPS closing position (only valid in CSWI:
6 in_Pos_A_NC
XCBR)
Phase B normally opened contact input for DPS opening position (only valid in CSWI:
7 in_Pos_B_NO
XCBR)

4 Control Functions

Phase B normally closed contact input for DPS closing position (only valid in CSWI:
8 in_Pos_B_NC
XCBR)
Phase C normally opened contact input for DPS opening position (only valid in CSWI:
9 in_Pos_C_NO
XCBR)
Phase C normally closed contact input for DPS closing position (only valid in CSWI:
10 in_Pos_C_NC
XCBR)
11 in_N_Trp Opening command for trip counter
12 in_N_Trp_A Phase A opening command for trip counter (only valid in CSWI: XCBR)
13 in_N_Trp_B Phase B opening command for trip counter (only valid in CSWI: XCBR)
14 in_N_Trp_C Phase C opening command for trip counter (only valid in CSWI: XCBR)
15 in_Rsyn Pointer of synchronism check element (only valid in CB control)
16 in_EnaOpn Opening permission for interlocking
17 in_EnaCls Closing permission for interlocking
4 18 in_CILO_Bypass Bypass for interlocking
19 in_Manual_Sel Selection for manual control
20 in_Manual_Opn Opening for manual control
21 in_Manual_Cls Closing for manual control
Table 4.1-3 Output signals of control function

1 Opn_Sel Opening selection
2 Cls_Sel Closing selection
3 Opn_Exec Opening operation
4 Cls_Exec Closing operation
5 Opn_Enabled Permission of opening operation
6 Cls_Enabled Permission of closing operation
7 Opn/Cls_Enabled Permission of operation (Opn_Enabled OR Cls_Enabled)
8 DPS Synthetic DPS for switchgear position
9 DPS_A Synthetic DPS for switchgear phase A position
10 DPS_B Synthetic DPS for switchgear phase B position
11 DPS_C Synthetic DPS for switchgear phase C position
12 N_Trp Tripping statistics
13 N_Trp_A Phase A tripping statistics
14 N_Trp_B Phase B tripping statistics
15 N_Trp_C Phase C tripping statistics
16 DPS.Alm Alarm signal when DPS status is BAD or INT
17 Cmd_ManSel Selection command for manual control
18 Cmd_ManOpn Opening command for manual control
19 Cmd_ManCls Closing command for manual control

4 Control Functions
4.1.5 Logics
SIG DPS_A = OFF

≥1
DPS = OFF
SIG DPS_B = OFF
SIG DPS_C = OFF
SIG DPS_A = ON
&
DPS = ON
SIG DPS_B = ON
SIG DPS_C = ON
SIG DPS_A = INT

≥1
DPS = INT
SIG DPS_B = INT
SIG DPS_C = INT
SIG DPS_A = BAD

≥1
SIG DPS_B = BAD
DPS = BAD
4
SIG DPS_C = BAD
Figure 4.1-2 DPS synthesis logic
SIG CSWI**.DPS = BAD >=1
SIG CSWI**.DPS = INT & CSWI**.Alm_DPS

[CSWI**.DPS.t_Alm] 0ms
SET [CSWI**.DPS.En_Alm]
Figure 4.1-3 DPS alarm logic
SIG Rasing edge of in_N_Trp_A

& N_Trp_A + 1
SIG DPS_A change form ON to OFF
SIG Rasing edge of in_N_Trp_B

& N_Trp_B + 1
&
SIG DPS_B change form ON to OFF
SIG Rasing edge of in_N_Trp_C

& N_Trp_C + 1
≥1
N_Trp + 1
SIG DPS_B change form ON to OFF
SIG Rasing edge of in_N_Trp

&
SIG DPS change form ON to OFF
Figure 4.1-4 Trip statistics triggering logic

4 Control Functions
Remote command from SAS/NCC

SIG with "Interlocking" flag
≥1 CSWI** interlocking
function activated
Local command from device LCD
SIG with "InterlockChk"
≥1
&
Contact triggered manual
SIG opening/closing operation
EN [CSWI**.En_Opn_Blk] ≥1
EN [CSWI**.En_Cls_Blk]
Figure 4.1-5 Interlocking logic

4
SIG in_Manual_Sel not configurated &
SIG in_Manual_Opn=1
≥1
SIG in_Manual_Sel =1 &
SIG in_Manual_Opn=1
& Opn_Exec_Man
SIG Opn_Enabled =1
SIG Control mode is Local
SIG in_Manual_Sel not configurated &
SIG in_Manual_Cls=1
≥1
SIG in_Manual_Sel =1 &
SIG in_Manual_Cls=1
& Cls_Exec_Man
SIG Cls_Enabled =1
SIG Control mode is Local
Figure 4.1-6 Manual control logic
4.1.6 Settings
Table 4.1-4 Settings of control function
No. Setting Range Unit Default Description

Delay Pick Up (DPU) time, i.e. debounce
1 CSWI**. DPS.t_DPU 0~60000 ms 500
time, for DPS

4 Control Functions

Disabled
2 CSWI**.DPS.En_Alm - Disabled Logic setting for DPS alarm
Enabled
3 CSWI**.DPS.t_Alm 0~60000 ms 500 Operation time delay of DPS alarm
Pulse Width (PW), i.e. holding time, for
4 CSWI**.t_PW_Opn 0~60000 ms 500
opening output
5 CSWI**.t_PW_Cls 0~60000 ms 500
closing output
6 DirCtrl**.t_PW_Opn 0~60000 ms 500
direct opening output
7 DirCtrl**.t_PW_Cls 0~60000 ms 500
direct closing output
Pulse Width (PW), i.e. holding time, for tap
8 84CSWI**.t_PW_Cls 0~60000 ms 500
changer closing output
9 84CSWI**.t_PW_Opn 0~60000 ms 500

Pulse Width (PW), i.e. holding time, for tap 4
changer opening output
Disabled Logic setting for interlocking logic control of
10 CSWI**.En_CILO_Opn - Disabled
Enabled closing output.
11 CSWI**.En_CILO_Cls - Disabled
Enabled opening output.
12 DirCtrl**.En_CILO_Opn - Disabled
Enabled direct closing output.
13 DirCtrl**.En_CILO_Cls - Disabled
Enabled direct opening output.
14 84CSWI**.En_CILO_Opn - Disabled
Enabled opening output of tap changer.
15 84CSWI**.En_CILO_Cls - Disabled
Enabled closing output of tap changer.
4.2 Manual Closing Synchronism Check

The purpose of synchronism check is to ensure two systems are synchronous before they are
going to be connected.
When two asynchronous systems are connected together, due to phase difference between the
two systems, larger impact will be led to the system during closing. Thus, closing operation is
applied with the synchronism check to avoid this situation and maintain the system stability. The
synchronism check includes synchro-check and dead charge check.
4.2.1 Operation Theory

4.2.1.1 Synchro-check
The comparative relationship between the reference voltage and the synchronization voltage for
synchro-check is as follow. Furthermore, the measured three-phase voltages for synchro-check
should not exceed the overvoltage threshold [25.U_OV] or lag the undervoltage threshold

4 Control Functions
[25.U_UV].
U_Ref
U_Syn
Figure 4.2-1 Relationship between reference and synchronous voltages
This figure shows the characteristics of synchro-check element used for CB closing if both
4 reference and synchronous sides are live. The element operates if the voltage difference,
frequency difference, slip frequency difference and phase angle difference are all within their
setting ranges.
 The difference between the reference voltage and the synchronization voltage is checked by
the following equation
|U_Ref- U_Syn| ≥ [25.U_Diff]
 The frequency difference between the reference side and the synchronization side is
checked by the following equation
|f(U_Ref)-f(U_Syn)| ≤ [25.f_Diff]
 The slip frequency difference is checked by the following equation
df/dt ≤ [25.df/dt]
 The phase difference between the reference voltage and the synchronization voltage is
checked by the following equation
∆δ ≤ [25.phi_Diff]
4.2.1.2 Dead Charge Check
The dead charge check mode checks only the synchro-check voltage. Several dead charge check
modes are supported in using the setting [25.Opt_Mode_DdChk]. The device compares the
reference side and the synchronous side voltages at both sides of circuit breaker with the settings
[25.U_LvChk] and [25.U_DdChk]. When the voltage is higher than [25.U_LvChk], the
corresponding side is regarded as live. When the voltage is lower than [25.U_DdChk], the
corresponding side is regarded as dead.
4.2.1.3 Voltage Input Channel
The synchronism check function is suitable for several applications. According to different
applications, user needs to configure different voltage input channel. For both the reference side

4 Control Functions
and the synchronous side, the voltage input channel may be single phase or three-phase.
While configuring through the PCS-Studio software, use the functional block MUX to synthesize a
three-phase voltage and input it for synchronism check.
MUX
SIG NR6641.Chn** in_A

SIG NR6641.Chn** in_B ABC RSYN
SIG NR6641.Chn**
in_C
in_ref
SIG NR6641.Chn** in_syn
……
In the meantime, the voltage switching logic can be adopted for the synchronism check input
channel, please refer to the following section.
4
For synchronism check voltage input channel configuration, please MAKE
SURE that the voltage source to connect to the inputs "in_ref" and
"in_syn" should be the same with that used in measurement function,
such as BayMMXU and UMMXN. Otherwise, the alarm "25.Alm_Cfg_Ch"
will be issued.
RSYN
in_ref
in_syn
in_25_Blk
in_DL_Blk
in_DB_Blk
in_SYN_Blk
in_25_Bypass
in_syn_chk
in_Dd_chk
4.2.3 I/O Signals

Table 4.2-1 Input signals of manual closing synchronism check

1 in_ref Reference voltage channel
2 in_syn Synchronization voltage channel
3 in_25_Blk Block synchronism check
4 in_DL_Blk Block live check

4 Control Functions

5 in_DB_Blk Block dead charge check
6 in_SYN_Blk Block synchro-check
7 in_25_Bypass Signal to temporarily bypass synchronism check logic
8 in_syn_chk Activate synchro-check (valid only if the setting [25.Opt_ValidMode] = Config)
9 in_Dd_chk Activate dead charge check (valid only if the setting [25.Opt_ValidMode] = Config)
Table 4.2-2 Output signals of manual closing synchronism check

1 U_Diff Voltage difference
2 phi_DIff Phase angle difference
3 f_diff Frequency difference
4 df/dt Frequency rate-of-change
5 25.SynChk_OK Satisfaction of synchro-check logic
4 6 25.DdChk_OK Satisfaction of dead charge check logic
7 25.RSYN_OK Satisfaction of synchronism check logic, i.e. SynChk_OK or DdChk_OK
4.2.4 Logics
SIG in_25_Blk
SIG in_SYN_Blk
SIG Cmd with synchro-check

SET [25.Opt_ValidMode] = Setting
&
EN [25.En_SynChk]
≥1
≥1
SET [25.Opt_ValidMode] = Config
&
SIG in_Syn_Chk
&
SIG Cmd without synchro-check
SET df/dt ≤ [25.df/dt]

SET ΔU ≤ [25.U_Diff] & 25.SynChk_OK
SET Δf ≤ [25.f_Diff]
SET Δδ ≤ [25.phi_Diff]
SET U_Ref ≤ [25.U_UV]

SET U_Ref ≥ [25.U_OV]
≥1
SET U_Syn ≤ [25.U_UV]
SET U_Syn ≥ [25.U_OV]
SET f_Ref ≤ [25.f_UV]

SET f_Ref ≥ [25.f_OV]
≥1
SET f_Syn ≤ [25.f_UV]
SET f_Syn ≥ [25.f_OV]
Figure 4.2-2 Synchro-check logic

4 Control Functions
SIG in_25_Blk
SIG in_DL_Blk
SIG in_DB_Blk
SIG Cmd with dead charge check

SET [25.Opt_ValidMode] = Setting
&
EN [25.En_DdChk]
≥1
≥1
SET [25.Opt_ValidMode] = Config 25.DdChk_OK
&
&
SIG in_Dd_Chk
&
SIG Cmd without dead charge check
SET Value.[25.Opt_Mode_DdChk]
SET U_Ref ≤ [25.U_DdChk] Dead

check
SET U_Syn ≤ [25.U_DdChk] criteria
selection
SET U_Ref ≥ [25.U_LvChk]
SET U_Syn ≥ [25.U_LvChk]
4
Figure 4.2-3 Dead charge check logic
4.2.5 Settings
Table 4.2-3 Settings of synchronism check

Selection of decision mode for
1 25.Opt_ValidMode Setting or Config Setting
synchronism check
Logic setting for synchro-check
2 25.En_SynChk Disabled or Enabled Enabled (valid only if the setting
[25.Opt_ValidMode] = Config)
Logic setting for dead charge
3 25.En_DdChk Disabled or Enabled Enabled check (valid only if the setting
[25.Opt_ValidMode] = Config)
Percentage threshold of under
4 25.U_UV 0.00~100.00 % 80.00
voltage for CB closing blocking
Percentage threshold of over
5 25.U_OV 100.00~170.00 % 170.00
voltage for CB closing blocking
Percentage threshold of under
6 25.f_UF 0.000~65.000 Hz 45.000 frequency for CB closing
blocking
Percentage threshold of over
7 25.f_OF 0.000~65.000 Hz 65.000 frequency for CB closing
blocking
Ua, Ub, Uc, Uab, Ubc, Selection of voltage for
8 25.Opt_U_SynChk Ua
Uca synchronism check
Threshold of voltage difference
9 25.U_Diff_Set 0.00~100.00 V 10.00
for synchronism check

4 Control Functions

Threshold of frequency
10 25.f_Diff_Set 0.00~2.00 Hz 0.50 difference for synchronism
check
Threshold of frequency variation
11 25.df/dt_Set 0.00~2.00 Hz/s 1.00
for synchronism check.
Threshold of phase difference
12 25.phi_Diff_Set 0.00~180.00 ° 15.00
Compensation angle of phase
13 25.phi_Comp 0.00~360.00 ° 0.00 difference for synchronism
check
SynDdRefDd
SynLvRefDd
SynDdRefLv
Selection of dead charge check
4 14 25.Opt_Mode_DdChk RefDd AnySideDd
mode
SynDd
SynLvRefDd/SynDdRefLv
AnySideDd
Threshold for voltage dead
15 25.U_DdChk 0.00~100.00 V 17.32
check
16 25.U_LvChk 0.00~100.00 V 34.64 Threshold for voltage live check
Threshold of duration for
17 25.t_Reset 0~60 s 5
synchrocheck
Circuit breaker closing time. It is
the time from receiving closing
18 25.t_Close_CB 0~2000 ms 20
command pulse till the CB is
completely closed.
 25.Opt_Mode_DdChk
No. Setting Value Dead charge check mode
1 SynDdRefDd Dead check for both the reference and the synchronization sides
2 SynLvRefDd Live check for synchronization side and dead check for reference side
3 SynDdRefLv Dead check for synchronization side and live check for reference side
4 RefDd Dead check for reference side
5 SynDd Dead check for synchronization side
6 SynLvRefDd/SynDdRefLv Option 2 or 3
7 AnySideDd Option 1, 2 or 3
4.3 Voltage Switching

The voltage switching function can be used to switch the reference and synchronization voltages
for double busbar and 3/2 CB arrangements. The "Near priority" principle is adopted by default,
and the user interface for programmable switching logic is also reserved.

4 Control Functions
4.3.1 Functional Description

The voltage switching module is used in the following scenarios:
 For double busbar arrangement, selection of appropriate voltage signals from Bus 1 and Bus
2 for synchronizing are required. Line VT signal is taken as reference to check synchronizing
with the voltage after voltage selection function. Selection approach is as follows.
Bus2
Bus1
DS1 DS2
UB1
UB2
DS1.DPS
CB.DPS CB
DS2.DPS
Ua
4
UL1 Ub
Line
Uc
Figure 4.3-1 Voltage connection for double busbar arrangement
 For one and a half breakers arrangement, selection of appropriate voltage signals among
Line1 VT, Line2 VT and Bus 2 VT as reference voltage to check synchronizing with Bus 1
voltage signal for closing breaker at Bus 1 side.
Bus1
UB1
Bus1_CB.DPS Bus1_CB
Line 1
Ua
UL1 Ub
Uc DS1
DS1.DPS
Tie_CB.DPS Tie_CB
Line 2
UL2
DS2.DPS
DS2
Bus2_CB.DPS Bus2_CB
UB2
Bus2
Figure 4.3-2 Voltage connection for one and a half breakers arrangement

4 Control Functions
VolSwitch
in_UB1_Chn Ref_Chn
in_UB2_Chn Syn_Chn
in_UL1_Chn
in_UL2_Chn
in_Bus1_CB
in_Tie_CB
in_Bus2_CB
in_DS1
in_DS2
4 4.3.3 I/O Signals

Table 4.3-1 Input signals of voltage switching

1 in_UB1_Chn Voltage channel for Bus 1
2 in_UB2_Chn Voltage channel for Bus 2
3 in_UL1_Chn Voltage channel for Line 1
4 in_UL2_Chn Voltage channel for Line 2
5 in_Bus1_CB DPS position for the Bus 1 side CB in 3/2 or double busbar arrangement
6 in_Tie_CB DPS position for the tie CB in 3/2 arrangement
7 in_Bus2_CB DPS position for the Bus 2 side CB in 3/2 or double busbar arrangement
8 in_DS1 DPS position for the Bus 1 side DS in 3/2 arrangement
9 in_DS2 DPS position for the Bus 2 side DS in 3/2 arrangement
Table 4.3-2 Output signals of voltage switching

1 Ref_Chn Reference voltage channel
2 Syn_Chn Synchronization voltage channel

4 Control Functions
4.3.4 Logics
SIG DS1.DPS=ON &

UB1_Sel
SIG DS2.DPS=OFF
SIG DS1.DPS=OFF &

UB2_Sel
SIG DS2.DPS=ON
&
Alm_Invalid_Sel
UB1 U_Syn
UB2
Figure 4.3-3 Voltage switching for double bus bar arrangement 4

SIG DS1.DPS=ON
SIG DS1.DPS=OFF
SIG Bus1_CB.DPS=ON
SIG DS2.DPS=ON
SIG DS2.DPS=OFF
SIG Bus2_CB.DPS=ON
UL1_Sel
&
UL2_Sel
&
UB2_Sel
&
Alm_Invalid_Sel
UL1 U_Ref
UL2
UB2
UB1 U_Syn
Figure 4.3-4 Voltage switching for 3/2 breakers arrangement (closing a bus CB)

4 Control Functions
SIG DS1.DPS=ON UL1_Sel
SIG DS1.DPS=OFF &

UB1_Sel
SIG Bus1_CB.DPS=ON
UL1 Uref
UB1
SIG DS2.DPS=ON UL2_Sel
SIG DS2.DPS=OFF &

UB2_Sel
SIG Bus2_CB.DPS=ON
4
UL2 Usyn
UB2
&
>=1
& Alm_Invalid_Sel
Figure 4.3-5 Voltage switching for 3/2 breakers arrangement (closing the tie CB)
4.3.5 Settings
Table 4.3-3 Settings of voltage switching
No. Setting Default Range Unit Description

Selection of circuit breaker
NoVolSel, DblBusOneCB,
1 Opt_CBConfig NoVolSel - arrangement for voltage
3/2BusCB, 3/2TieCB
switching
4.4 Tap Changer Indicator

A tap changer is a connection point selection mechanism along a power transformer winding that
allows a variable number of turns to be selected in discrete steps. A transformer with a variable
turn's ratio is produced, enabling stepped voltage regulation of the output. The tap selection may
be made via an automatic or manual tap changer mechanism.

The Tap Changer Indicator (TPI) input could be 6-bit Binary-Coded Decimal (BCD), independent

4 Control Functions
contacts, carry inputs or DC measuring transducer input. The indicator supports phase-separated
inputs and discordance alarm.
The control of tap changer is treated as a special kind of binary output in this device. The binary
outputs "84.BO_StepDown", "84.BO_StepUp" and "84.BO_EmergStop" are used to descend,
raise and stop the tap changer in comply with the principle Selection Before Operation (SBO).
Additionally, during a tap changer control process, if the situation "sliding tap" occurs, the tap
changer is out of control, i.e. steps up/down continuously, the output "84.BO_Slide_Trip" is
provided to cut off the power supply of the tap changer's motor mechanism.
YLTC
in_Tap_Pos_01 Tap_Pos_01
in_Tap_Pos_02 Tap_Pos_02 4
in_Tap_Pos_03 Tap_Pos_03
in_Tap_BI_01 84.BO_Slide_Trip
in_Tap_BI_02 84.Alm_Unmatched
……
in_Tap_BI_26
4.4.3 I/O Signals

Table 4.4-1 Input signals of tap changer indicator

1 in_Tap_Pos_01 General or phase A TPI input
2 in_Tap_Pos_02 Phase B TPI input
3 in_Tap_Pos_03 Phase C TPI input
For BCD, max. 39 positions
Example: 17 = 01 0111 (BI_06~BI_01)
1 in_Tap_BI_01
2 in_Tap_BI_02
Decimal number 0~9 of units
3 in_Tap_BI_03
4 in_Tap_BI_04
5 in_Tap_BI_05
Decimal number 0~3 of tens
6 in_Tap_BI_06
For independent contacts, max. 26 positions
Example: 17 = 0000 0000 0100 0000 0000 0000 00 (BI_26~BI_01)
**: 01~26
Decimal number 1~26
1 in_Tap_BI_**
If all inputs, i.e. in_Tap_BI_01~in_Tap_BI_26, are "0", it represents the decimal number
0

4 Control Functions

For carry inputs, max. 29 positions
Example: 17 = 011 0001 0000 00 (BI_13~BI_01)
**: 01~10
1 in_Tap_BI_**
Decimal number 0~9 of units
Validation for decimal number of units
2 in_Tap_BI_11 1: valid
0: invalid
Validation for decimal number of tens
0: invalid
Validation for decimal number of twenties
0: invalid
4 Table 4.4-2 Output signals of tap changer indicator

1 Tap_Pos_01 Converted general or phase A TPI
2 Tap_Pos_02 Converted phase B TPI
3 Tap_Pos_03 Converted phase C TPI
4 84.BO_SlideTrip Tripping output for the situation "sliding tap"
5 84.Alm_Unmatched Three-phase TPI discordance alarm
4.4.4 Settings
Table 4.4-3 Settings of tap changer indicator

Total tap changer indication number that
1 84.Num 0~26 - 26
should coordinate with the input code
Selection of tap changer indication input
code
Resv: input direct or DC analog channel
BCD: 6-bit BCD for max. 39 positions
Resv
Carry: 13-bit carry inputs for max. 29
BCD
positions
Carry
2 84.Opt.Code - BCD Independent: 26-bit independent contacts
Independent
for max. 26 positions
BCD-PhSeg
BCD-PhSeq: 18-bit BCD for max. 39
Independent-PhSeg
phase-separated positions
Independent-PhSeq: 24-bit independent
contacts for max. 8 phase-separated
positions
Delay Pick Up (DPU) time, i.e. debounce
3 84.t_DPU 0~6000 ms 500
time, for tap changer indication inputs

4 Control Functions

Logic setting for tripping output of tap
4 84.En_SlideTrip Disabled or Enabled - Disabled changer motor mechanism power supply
during "sliding tap"
Holding time for tripping output of tap
5 84.t_SlideTrip 0~6000 ms 500 changer motor mechanism power supply
during "sliding tap"

5 Measurement
5 Measurement
Table of Contents
5.1 Overview ........................................................................................................... 5-1

5.2 Primary Values ................................................................................................. 5-1
5.2.1 General Values ..................................................................................................................... 5-1
5.2.2 Angle Values ......................................................................................................................... 5-1
5.2.3 Sequence Components Values ............................................................................................ 5-2
5.2.4 Power Values ........................................................................................................................ 5-2
5.3 Secondary Values ............................................................................................ 5-3

5.3.1 General Values ..................................................................................................................... 5-3
5.3.2 Angle Values ......................................................................................................................... 5-3 5

5.3.3 Sequence Components Values ............................................................................................ 5-4
5.3.4 Power Values ........................................................................................................................ 5-4
5.4 Function Values ............................................................................................... 5-5

5.4.1 CurrSum Values ................................................................................................................... 5-5
5.4.2 Angle Values ......................................................................................................................... 5-5
5.4.3 OvExc Values ....................................................................................................................... 5-5
5.4.4 Diff Values............................................................................................................................. 5-5
5.4.5 REF Values ........................................................................................................................... 5-6
5.4.6 WdgDiff Values ..................................................................................................................... 5-7
5.4.7 ThOvLd Values ..................................................................................................................... 5-8
5.4.8 Synchrocheck ....................................................................................................................... 5-8
5.5 DC Measuring Transducers ............................................................................ 5-9

5.5.3 I/O Signals .......................................................................................................................... 5-10
5.5.4 Settings ............................................................................................................................... 5-10

5 Measurement
List of Figures
Figure 5.5-1 Characteristic curve of a DC measuring transducer input ............................. 5-9
List of Tables
Table 5.6-1 Input signals of DC measuring transducers ..................................................... 5-10
Table 5.6-2 Output signals of DC measuring transducers .................................................. 5-10
Table 5.6-3 Settings of DC measuring transducers ............................................................. 5-10

5 Measurement
5.1 Overview
This device performs continuous measurement of the analogue input quantities. The current full
scale of relay is 40 times of rated current, and there is no effect to the performance of IED due to
overflowing of current full scale. The device samples 24 points per cycle and calculates the RMS
value in each interval and updated the LCD display in every 0.5 second. The measurement data
can be displayed on the LCD of the relay front panel or on the local/remote PC via software tool.
Navigate the menu to view the sampling value through LCD screen.
5.2 Primary Values

Access path: MainMenu  “Measurements”  “Primary Values”
5.2.1 General Values
The symbol ”x” in the following measurement lists, represents some side
or bushing of transformer defined by user through PCS-Studio software, 5
which may be “HVS”, “MVS”, “LVS”, “HVS2”, “MVS2”, “LVS2”, “CWS”,
“HVB”, “MVB”, “LVB”, etc. If only one protection element is equipped, the
prefix “x.” may disappear.
No. Item Definition Unit
1 x.Ia_Pri Phase-A secondary current A
2 x.Ib_Pri Phase B primary current A
3 x.Ic_Pri Phase C primary current A
4 x.Neu.3I0_Ext_Pri External residual primary current A
5 x.Ua_Pri Phase A primary voltage kV
6 x.Ub_Pri Phase B primary voltage kV
7 x.Uc_Pri Phase C primary voltage kV
8 x.Uab_Pri Phase AB primary voltage kV
9 x.Ubc_Pri Phase BC primary voltage kV
10 x.Uca_Pri Phase CA primary voltage kV
11 x.Neu.U_Pri Residual primary voltage kV
5.2.2 Angle Values
1 x.Ang(Ia) Phase angle of phase A current °
2 x.Ang(Ib) Phase angle of phase B current °
3 x.Ang(Ic) Phase angle of phase C current °

5 Measurement
4 x.Ang(3I0_Cal) Phase angle of calculated residual current °
5 x.Neu.Ang(3I0_Ext) Phase angel of external neutral-point residual current °
6 x.Ang(Ua) Phase angle of phase A voltage °
7 x.Ang(Ub) Phase angle of phase B voltage °
8 x.Ang(Uc) Phase angle of phase C voltage °
9 x.Ang(3U0_Cal) Phase angle of calculated residual voltage °
10 x.Neu.Ang(U) Phase angle of neutral-point residual voltage °
11 x.Ang (Ia-Ib) Phase angle between phase A and phase B currents °
12 x.Ang (Ib-Ic) Phase angle between phase B and phase C currents °
13 x.Ang (Ic-Ia) Phase angle between phase C and phase A currents °
14 x.Ang (Ua-Ub) Phase angle between phase A and phase B voltages °
15 x.Ang (Ub-Uc) Phase angle between phase B and phase C voltages °
16 x.Ang (Uc-Ua) Phase angle between phase C and phase A voltages °
5 5.2.3 Sequence Components Values
1 x.I1_Pri Positive sequence primary current A
2 x.I2_Pri Negative sequence primary current A
3 x.3I0_Cal_Pri Calculated residual primary current A
4 x.U1_Pri Positive sequence primary voltage kV
5 x.U2_Pri Negative sequence primary voltage kV
6 x.3U0_Cal_Pri Calculated residual primary voltage kV
5.2.4 Power Values
1 x.Pa_Pri Phase A primary active power MW
2 x.Pb_Pri Phase B primary active power MW
3 x.Pc_Pri Phase C primary active power MW
4 x.Qa_Pri Phase A primary reactive power MVAr
5 x.Qb_Pri Phase B primary reactive power MVAr
6 x.Qc_Pri Phase C primary reactive power MVAr
7 x.Sa_Pri Phase A primary apparent power MVA
8 x.Sb_Pri Phase B primary apparent power MVA
9 x.Sc_Pri Phase C primary apparent power MVA
10 x.P_Pri Primary active power MW
11 x.Q_Pri Primary reactive power MVAr

5 Measurement
12 x.S_Pri Primary apparent power MVA
13 x.Cosa Phase A primary power factor -
14 x.Cosb Phase B primary power factor -
15 x.Cosc Phase C primary power factor -
16 x.Cos Primary power factor -
5.3 Secondary Values

Access path: MainMenu  “Measurements”  “Secondary Values”
5.3.1 General Values
1 x.Ia_Sec Phase A secondary current A
2 x.Ib_Sec Phase B secondary current A
3 x.Ic_Sec Phase C secondary current A
4 x.Neu.3I0_Ext_Sec External residual secondary current A 5

5 x.Ua_Sec Phase A secondary voltage V
6 x.Ub_Sec Phase B secondary voltage V
7 x.Uc_Sec Phase C secondary voltage V
8 x.Uab_Sec Phase AB secondary voltage V
9 x.Ubc_Sec Phase BC secondary voltage V
10 x.Uca_Sec Phase CA secondary voltage V
11 x.Neu.U_Sec Residual secondary voltage V
5.3.2 Angle Values
1 x.Ang(Ia) Phase angle of phase A current °
2 x.Ang(Ib) Phase angle of phase B current °
3 x.Ang(Ic) Phase angle of phase C current °
4 x.Ang(3I0_Cal) Phase angle of calculated residual current °
5 x.Neu.Ang(3I0_Ext) Phase angel of external neutral-point residual current °
6 x.Ang(Ua) Phase angle of phase A voltage °
7 x.Ang(Ub) Phase angle of phase B voltage °
8 x.Ang(Uc) Phase angle of phase C voltage °
9 x.Ang(3U0_Cal) Phase angle of calculated residual voltage °
Phase angle of neutral-point residual voltage or phase-to-phase

10 x.Neu.Ang(U) °
voltage

5 Measurement
11 x.Ang (Ia-Ib) Phase angle between phase A and phase B currents °
12 x.Ang (Ib-Ic) Phase angle between phase B and phase C currents °
13 x.Ang (Ic-Ia) Phase angle between phase C and phase A currents °
14 x.Ang (Ua-Ub) Phase angle between phase A and phase B voltages °
15 x.Ang (Ub-Uc) Phase angle between phase B and phase C voltages °
16 x.Ang (Uc-Ua) Phase angle between phase C and phase A voltages °
5.3.3 Sequence Components Values
1 x.I1_Sec Positive sequence secondary current A
2 x.I2_Sec Negative sequence secondary current A
3 x.3I0_Cal_Sec Calculated residual secondary current A
4 x.U1_Sec Positive sequence secondary voltage kV
5 x.U2_Sec Negative sequence secondary voltage kV
5 6 x.3U0_Cal_Sec Calculated residual secondary voltage kV
5.3.4 Power Values
1 x.Pa_Sec Phase A secondary active power MW
2 x.Pb_Sec Phase B secondary active power MW
3 x.Pc_Sec Phase C secondary active power MW
4 x.Qa_Sec Phase A secondary reactive power MVAr
5 x.Qb_Sec Phase B secondary reactive power MVAr
6 x.Qc_Sec Phase C secondary reactive power MVAr
7 x.Sa_Sec Phase A secondary apparent power MVA
8 x.Sb_Sec Phase B secondary apparent power MVA
9 x.Sc_Sec Phase C secondary apparent power MVA
10 x.P_Sec Secondary active power MW
11 x.Q_Sec Secondary reactive power MVAr
12 x.S_Sec Secondary apparent power MVA
13 x.Cosa Phase A secondary power factor -
14 x.Cosb Phase B secondary power factor -
15 x.Cosc Phase C secondary power factor -
16 x.Cos Secondary power factor -

5 Measurement
5.4 Function Values

Access path: MainMenu  “Measurements”  “Function Values”
5.4.1 CurrSum Values
1 x.Sum.Ia_Sec Sum (secondary value) of phase A currents A
2 x.Sum.Ib_Sec Sum (secondary value) of phase B currents A
3 x.Sum.Ic_Sec Sum (secondary value) of phase C currents A
4 x.Sum.I1_Sec Sum (secondary value) of positive-sequence currents A
5 x.Sum.I2_Sec Sum (secondary value) of negative-sequence currents A
6 x.Sum.3I0_Cal_Sec Sum (secondary value) of calculated residual currents A
7 x.Sum.Ang(Ia) Phase angle of the sum of phase A currents °
8 x.Sum.Ang(Ib) Phase angle of the sum of phase B currents °
9 x.Sum.Ang(Ic) Phase angle of the sum of phase C currents °
Phase angle between of phase-A sum current and phase-B sum °

10 x.Sum.Ang(Ia-Ib)
current 5
Phase angle between of phase-B sum current and phase-C sum °
11 x.Sum.Ang(Ib-Ic)
current
Phase angle between of phase-C sum current and phase-A sum °

12 x.Sum.Ang(Ic-Ia)
current
5.4.2 Angle Values
1 x.Ang(Ua-Ia) Phase angle between phase A voltage and current °
2 x.Ang(Ub-Ib) Phase angle between phase B voltage and current °
3 x.Ang(Uc-Ic) Phase angle between phase C voltage and current °
5.4.3 OvExc Values
1 f System frequency Hz
2 U/f Overexcitation multiple of definite-time overexcitation protection. /
Thermal state of inverse-time overexcitation protection. When the

3 24IDMT.ThermAccu %
value is “100%”, inverse-time overexcitation protection operates.
5.4.4 Diff Values
1 87T.Ida Phase-A differential current. p.u.
2 87T.Idb Phase-B differential current. p.u.

5 Measurement
3 87T.Idc Phase-C differential current. p.u.
4 87T.Ira Phase-A restraint current. p.u.
5 87T.Irb Phase-B restraint current. p.u.
6 87T.Irc Phase-C restraint current. p.u.
7 87T.Ia_Th Threshold value of phase-A restraint current. p.u.
8 87T.Ib_Th Threshold value of phase-B restraint current. p.u.
9 87T.Ic_Th Threshold value of phase-C restraint current. p.u.
Phase-A corrected current of branch m (m= 1,2, 3, 4, 5, 6) for

10 87T.Ia_Cr_Brm p.u.
Phase-B corrected current of branch m (m= 1,2, 3, 4, 5, 6) for

11 87T.Ib_Cr_Brm p.u.
Phase-C corrected current of branch m (m= 1,2, 3, 4, 5, 6) for

12 87T.Ic_Cr_Brm p.u.
Angle between phase-A currents of branch 1 and branch m (m= 2, 3,

13 87T.Ang(Ia)_Br1-Brm deg
4, 5, 6).
5 Angle between phase-B currents of branch 1 and branch m (m= 2, 3,
14 87T.Ang(Ib)_Br1-Brm deg
4, 5, 6).
Angle between phase-C currents of branch 1 and branch m (m= 2, 3,

15 87T.Ang(Ic)_Br1-Brm deg
4, 5, 6).
16 87T.Ida_Hm2_Pcnt Phase-A 2nd harmonic percentage of total differential current. %
17 87T.Idb_Hm2_Pcnt Phase-B 2nd harmonic percentage of total differential current. %
18 87T.Idc_Hm2_Pcnt Phase-C 2nd harmonic percentage of total differential current. %
19 87T.Ida_Hm3_Pcnt Phase-A 3rd harmonic percentage of total differential current. %
20 87T.Idb_Hm3_Pcnt Phase-B 3rd harmonic percentage of total differential current. %
21 87T.Idc_Hm3_Pcnt Phase-C 3rd harmonic percentage of total differential current. %
22 87T.Ida_Hm5_Pcnt Phase-A 5th harmonic percentage of total differential current. %
23 87T.Idb_Hm5_Pcnt Phase-B 5th harmonic percentage of total differential current. %
24 87T.Idc_Hm5_Pcnt Phase-C 5th harmonic percentage of total differential current. %
Reference current of branch m (m=1, 2, 3, 4, 5, 6) of power

25 87T.Ib_Brm A
transformer for differential protection.
5.4.5 REF Values
1 x.64REF.3I0d Residual differential current of x side REF protection. In
2 x.64REF.3I0r Residual restraint current of x side REF protection. In
3 x.64REF.3I0_Th Threshold of residual restraint current of x side REF protection. In
4 x.64REF.3I0_Cr_Brm Corrected calculated residual current for branch m of x side REF In

5 Measurement
protection (m=1, 2, 3, 4).
5 x.64REF.3I0_Cr_NP Corrected residual current from neutral CT of x side REF protection. In
Angle of calculated residual current between branch 1 and branch m

6 x.64REF.Ang(3I0)_Br1-Brm deg
of x side REF protection (m=2, 3, 4).
Angle between calculated residual current of branch 1 and current

7 x.64REF.Ang(3I0)_Br1-NP deg
from neutral CT of x side REF protection.
Corrected coefficient of current for branch m of x side REF protection

8 x.64REF.K_Brm /
(m=1, 2, 3, 4).
Corrected coefficient of current from neutral CT of x side REF

9 x. 64REF.K_NP /
protection
5.4.6 WdgDiff Values
1 87W.Ida Phase-A differential current of winding differential protection. In
2 87W.Idb Phase-B differential current of winding differential protection. In
3 87W.Idc Phase-C differential current of winding differential protection. In 5

4 87W.3I0d Residual differential current of winding differential protection. In
5 87W.Ira Phase-A restraint current of winding differential protection. In
6 87W.Irb Phase-B restraint current of winding differential protection. In
7 87W.Irc Phase-C restraint current of winding differential protection. In
8 87W.3I0r Residual restraint current of winding differential protection. In
Threshold of phase-A restraint current of winding differential

9 87W.Ia_Th In
protection.
Threshold of phase-B restraint current of winding differential

10 87W.Ib_Th In
protection.
Threshold of phase-C restraint current of winding differential

11 87W.Ic_Th In
protection.
Threshold of residual restraint current of winding differential

12 87W.3I0_Th In
protection.
Phase-A corrected current of branch m (m= 1,2, 3, 4, 5) for

13 87W.Ia_Cr_Brm In
Phase-B corrected current of branch m (m= 1,2, 3, 4, 5) for

14 87W.Ib_Cr_Brm In
Phase-C corrected current of branch m (m= 1,2, 3, 4, 5) for

15 87W.Ic_Cr_Brm In
Corrected calculated residual current for branch m (m=1, 2, 3, 4, 5)

16 87W.3I0_Cr_Brm In
of winding differential protection.
17 87W.Ang(Ia)_Br1-Brm Angle between phase-A currents of branch 1 and branch m (m= 2, 3, deg

5 Measurement
4, 5) of winding differential protection.
Angle between phase-B currents of branch 1 and branch m (m= 2, 3,

18 87W.Ang(Ib)_Br1-Brm deg
Angle between phase-C currents of branch 1 and branch m (m= 2, 3,

19 87W.Ang(Ic)_Br1-Brm deg
Angle between calculated residual current of branch 1 and branch m

20 87W.Ang(3I0)_Br1-Brm deg
(m= 2, 3, 4, 5) of winding differential protection.
Corrected coefficient of current for branch m of winding differential

21 87W.K_Brm /
protection. (m=1, 2, 3, 4, 5).
5.4.7 ThOvLd Values
Phase A thermal state of thermal overload protection. When the

1 x.49.Accu_A %
value is “1”, thermal overload protection operates.
Phase B thermal state of thermal overload protection. When the

x.49.Accu_B %
5 2
Phase C thermal state of thermal overload protection. When the

3 x.49.Accu_C %
The calculated temperature difference of phase A between winding

4 x.49.T_Diff_A ℃
temperature and oil temperature.
The calculated temperature difference of phase B between winding

5 x.49.T_Diff_B ℃
The calculated temperature difference of phase C between winding

6 x.49.T_Diff_C ℃
5.4.8 Synchrocheck
1 25.U_Ref_Sec Secondary voltage of reference side V
2 25.U_Ref_Pri Primary voltage of reference side kV
3 25.f_Ref Frequency of reference side Hz
4 25.U_Syn_Sec Secondary voltage of synchronization side V
5 25.U_Syn_Pri Primary voltage of synchronization side kV
6 25.f_Syn Synchronization side frequency Hz
7 25.U_Diff_Sec Secondary voltage difference for CB synchronism check V
8 25.U_Diff_Pri Primary voltage difference for CB synchronism check kV
9 25.phi_Diff Phase angle difference for CB synchronism check Deg
10 25.f_Diff Frequency difference for CB synchronism check Hz
11 25.df/dt Frequency variation difference for CB synchronism check Hz/s

5 Measurement
12 25.RSYN_OK The synchronism check logic is satisfied. -
13 25.SynChk_OK The synchro-check logic is satisfied. -
14 25.DdChk_OK The dead charge check logic is satisfied. -
5.5 DC Measuring Transducers

The DC measuring transducers with an input rated at 0~±20mA or 0~±10Vdc can be used in the
devices. 8 or 12 (depending on the subtype) inputs are available as the DC AI module, which can
be plugged into a plug-in module slot. Typically, slowly changing process variable such as
temperature or gas pressure are measured with such transducers.

A DC measuring transducer input typically converts a value which represents a physical quantity
such as temperature or pressure. Therefore, a characteristic curve that assigns the physical
quantity to the DC analog value is necessary. The following figure shows an example.
Temperature (⁰C) 5
Tmax
P
Tmin Tp
ITransd (mA)
ip 20
O
Figure 5.5-1 Characteristic curve of a DC measuring transducer input
In this example, the setting of the range for the scaled value goes from a usable range of 0mA to
+20mA. The measured value 0mA means a temperature of Tmin which is defined by the setting
[DCAI.Min_Transducer**] and the measured value 20mA signifies a temperature of Tmax which is
defined by the setting [DCAI.Max_Transducer**]. Thus, for the actual point P, the measured
transducer current ip can be converted into a value of temperature.

5 Measurement
AnIn
in_dc01
in_dc02
in_dc03
in_dc04
in_dc05
in_dc06
in_dc07
in_dc08
5.5.3 I/O Signals

Table 5.5-1 Input signals of DC measuring transducers

1 in_dc** Input value of DC measuring transducer channel **
5
Table 5.5-2 Output signals of DC measuring transducers

Access path: Main Menu  “Measurements”  “Primary Values” 
1 B**.DCAI.Input**_Pri “DCAI_Values”
Converted value (physical quantity) of DC measuring transducer channel **
Access path: Main Menu  “Measurements”  “Secondary Values” 
2 B**.DCAI.Input**_Sec “DCAI_Values”
Mearsured value (0~±20mA or 0~±10Vdc) of DC measuring transducer channel **
5.5.4 Settings
Table 5.5-3 Settings of DC measuring transducers
No. Setting Default Range Step Unit Description

Selection of DC analog input
type
0~10V
1 DCAI.Opt_Type_Transducer** 0~20mA - - Please refer to the
0~20mA
corresponding jumper of DC AI
module to realize the selection.
The minimal converted value
2 DCAI.Min_Transducer** 0 -60000~60000 1 -
(physical quantity)
The maximal converted value
3 DCAI.Max_Transducer** 250 -60000~60000 1 -
(physical quantity)

6 Supervision
6 Supervision
Table of Contents
6.1 Overview ........................................................................................................... 6-1

6.2 Device Hardware Supervision ........................................................................ 6-1
6.2.1 Hardware Resource Consumption Supervision ................................................................... 6-1
6.2.2 Hardware Status Supervision ............................................................................................... 6-2
6.2.3 Hardware Configuration Supervision ................................................................................... 6-3
6.2.4 Device Firmware Supervision .............................................................................................. 6-3
6.2.5 CPU Process and Module Supervision ................................................................................ 6-3
6.3 Analog Input Supervision ............................................................................... 6-3

6.4 Secondary Circuit Supervision....................................................................... 6-4
6.4.1 CT Circuit Supervision (CTS) ............................................................................................... 6-4
6.4.2 VT Circuit Supervision (VTS) ............................................................................................... 6-4
6.5 Binary Input Supervision ................................................................................ 6-4

6
6.5.1 Debounce Time .................................................................................................................... 6-4
6.5.2 Jitter Processing ................................................................................................................... 6-6
6.6 Tripping Counter Statistics ............................................................................. 6-8

6.7 Supervision Alarms and Handling Suggestion ............................................. 6-9
List of Figures
Figure 6.5-1 Sequence chart of debounce technique ........................................................... 6-5
Figure 6.5-2 Debounce time configuration page.................................................................... 6-5
Figure 6.5-3 Sequence chart of jitter processing................................................................... 6-7
List of Tables
Table 6.7-1 Alarm description..................................................................................................... 6-9
Table 6.7-2 Troubleshooting..................................................................................................... 6-11

6 Supervision

6 Supervision
6.1 Overview
Protection system is in quiescent state under normal conditions, and it is required to respond
promptly for faults occurred on power system. When the device is in energizing process before
the LED “HEALTHY” is on, the device need to be checked to ensure no abnormality. Therefore,
the automatic supervision function, which checks the health of the protection system when startup
and during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a defect is detected during initialization when DC power supply is provided to the device,
the device will be blocked with indication and alarm of relay out of service. It is suggested a trial
recovery of the device by re-energization. Please contact supplier if the device is still failure.
When a failure is detected by the automatic supervision, it is followed by a LCD message, LED
indication and alarm contact outputs. The failure alarm is also recorded in event recording report
and can be printed If required.
6.2 Device Hardware Supervision
All hardware has real-time monitoring functions, such as CPU module monitoring, communication
interface status monitoring, power supply status monitoring.
The monitoring function of CPU module also includes processor self-check, memory self-check
6
and so on. The processor self-check is checked by designing execution instructions and data
operations. Check whether the processor can execute all instructions correctly, and whether it can
correctly calculate complex data operations to determine whether it works normally. For
peripherals, it can monitor the status of the interface module, check the input and output data,
send the communication interface and receive self-loop detection. Memory self-check is used to
detect unexpected memory errors in the running process. It can effectively prevent program logic
abnormality caused by memory errors.
The status monitoring of communication interface also includes Ethernet communication interface
monitoring and differential channel communication interface monitoring. By accessing the status
register of the communication interface, the state of the corresponding interface is obtained, such
as the state of connection, the number of sending frames, the number of frames received, and the
number of wrong frames. According to the statistics of the acquired interface state, it is judged
whether the interface work is abnormal.
The hardware supervision also includes the power supply status monitoring. The voltage
monitoring chip is used by all the power supplies. The reset voltage threshold is preset to the reset
monitoring circuit. When the power supply is abnormal, the voltage monitoring chip will output the
reset signal to control CPU to be in the reset state and avoid the wrong operation.
6.2.1 Hardware Resource Consumption Supervision
1. Logic component total execution time monitoring

6 Supervision
In the process of operation, the safety allowance should always be kept and no overload
phenomenon is allowed. When the user configures logic components with PCS-Studio, the
PCS-Studio automatically calculates the time required for the theoretical execution of the
configured components. When the security limit is exceeded, the PCS-Studio will indicate that the
configuration error is not allowed to download the current configuration to the device.
2. Module data exchange monitoring
During the operation of the device, there is a lot of data exchange between modules. The number
of data exchanges is related to the number of logical components configured by the user. When
the configuration is too large to cause the number of data exchange to exceed the upper limit
supported by the device, the PCS-Studio prompts the configuration error.
3. Configuration file size monitoring
The initialization of the device depends on the configuration files of each module. The user
configured logical components will eventually be embodied in the configuration file, limited to the
hardware memory space. When the configuration file size is more than the upper limit, the
PCS-Studio prompts the configuration error.
6.2.2 Hardware Status Supervision
1. Memory ECC and parity functions.
The DDR3 memory chip has the function of ECC (Error Checking and Correcting) to eliminate
6 unexpected changes in memory caused by electromagnetic interference. The chip memory has
parity function. When an error occurs, the system can detect anomalies immediately, and
eliminate the logic abnormity caused by memory errors.
2. Memory error monitoring in code area and constant data area
In addition to the above hardware memory reliability measures, the device software is also
constantly checking the memory during operation, including code, constant data, and so on. Once
the error detection, the system will automatically restart the restore operation. If they detect the
error immediately after the restart, it may be the result of a permanent fault locking device
hardware, only at the moment and not restart.
3. Binary output relay drive monitoring
The reliability of the device is largely determined by the reliability of the export drive. By reading
the driving state of the binary output relay, the alarm signal will be generated and the device is
immediately blocked to prevent the relay from maloperation when the device is not given a
tripping order and the binary output relay driver is detected in the effective state.
4. CPU temperature monitoring
The CPU chip needs to be able to ensure long-term stability under the permissible working
temperature of the specification. Therefore, it is necessary to monitor the working temperature
monitored by CPU.

6 Supervision
6.2.3 Hardware Configuration Supervision

The device is blocked when the actual hardware configuration is not consistent with the hardware
configuration file. Compared with pre configured modules, this device will be blocked if more
module is inserted, fewer module is inserted, and wrong modules is inserted.
6.2.4 Device Firmware Supervision

1. Each hardware module configuration check code needs to be consistent with CPU module.
The device CPU module stores the configuration check codes of other modules. In initialization
procedure, it checks whether the configuration check code of each module is consistent with the
stored code in CPU module, and if it is not consistent, this device is blocked.
2. The hardware modules and process interface versions need to be consistent with the CPU
module.
If the system is incompatible with the upgrade, it will upgrade the internal interface version. At this
moment, each hardware module and process will be upgraded synchronously, otherwise the
version of the interface will be inconsistent.
3. Configuration text is correct.
The configuration text formed by the device calibration visualization project includes checking
whether the check code is wrong or not.
4. Whether any setting is over the range, whether it needs to confirm the settings.
6
If the setting exceeds the configuration range, the device is blocked; if some settings are added, it
is necessary to confirm the new values through the LCD.
6.2.5 CPU Process and Module Supervision
1. Monitor the heartbeat of the module.
In the operation procedure, the CPU module sends a time synchronization command to other
module, each module repeats heartbeat message to the CPU module, if it does not respond or the
heartbeat is abnormal, then this device is blocked.
2. Check whether the settings of other modules are consistent with the CPU module.
The actual values of all the settings in the CPU module are initialized to send to the corresponding
slave modules. In the process of operation, the setting values stored in the CPU module and the
setting values of other modules will be checked one by one. If they are not consistent, this device
will issue the alarm signal "Fail_Settings".
6.3 Analog Input Supervision
The sampling circuit of this device is designed as dual-design scheme. Each analog sampling
channel is sampled by two groups of ADC. The sampling data is self checking and inter checking
in real time. If any sampling circuit is abnormal, the device reports the alarm signal "Alm_Sample",

6 Supervision
and the protection function related to the sampling channel is disabled at the same time. When
the sampling circuit returns to normal state, the related protection is not blocked after 10s.
6.4 Secondary Circuit Supervision
The secondary circuit supervision function includes current transformer supervision (CTS),
voltage transformer supervision (VTS), power supply supervision of binary inputs and
tripping/closing circuit supervision.
6.4.1 CT Circuit Supervision (CTS)
The purpose of the CTS is to detect whether the current transformer circuit is failed. In some
cases, if the CT is failed (broken-conductor, short-circuit), related protective element should be
blocked for preventing this device from mal-operation.
See further details about the CTS, please refer Chapter 3.
6.4.2 VT Circuit Supervision (VTS)

The purpose of the VTS is to detect whether the VT analog input is normal. Because some
function, such as synchronism check, will be influenced by a voltage input failure.
The VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit
fault, poor contact of VT circuit, VT maintenance and so on. The device can detect the failure, and
6 then issue an alarm signal and block relevant function.
See further details about the VTS, please refer Chapter 3.
6.5 Binary Input Supervision

6.5.1 Debounce Time
The well-designed debounce technique is adopted in this device, and the state change of binary
input within “Debounce time” will be ignored. As shown in Figure 6.5-1.
All binary inputs should setup necessary debounce time to prevent the device from undesired
operation due to transient interference or mixed connection of AC system and DC system. When
the duration of binary input is less than the debounce time, the state of the binary input will be
ignored. When the duration of binary input is greater than the debounce time, the state of the
binary input will be validated and wrote into SOE.

6 Supervision
Binary input
state
SOE report SOE report

timestamps timestamps
Validated binary input Validated binary input
state changes state changes
1
Debounce time of Debounce time of

delayed pickup delayed dropout
Time
Figure 6.5-1 Sequence chart of debounce technique
In order to meet flexible configurable requirement for different project field, all binary inputs
provided by the device are configurable. Through the configuration tool, this device provides two
parameters to setup debounce time of delayed pickup and dropout based on specific binary
signal.
Figure 6.5-2 Debounce time configuration page
The configurable binary signals can be classified as follows:
1. Type 1
This type of binary inputs includes enable/disable of protection functions, AR mode selection,
“BI_RstTarg”, “BI_Maintenance”, disconnector position, settings group switch, open and close
command of circuit breaker and disconnector, enable/disable of auxiliary functions (for
example, manually trigger recording). It is on the premise of reliability, and the debounce time
of delayed pickup and delayed dropout is recommended to set as 100ms at least.
2. Type 2
This type of binary inputs includes “CSWIxx.Cmd_LocCtrl”, “CSWIxx.Cmd_RmtCtrl”, etc.

6 Supervision
Debounce time
BI Input Signal.X1 t1 t2 &

Time delay Output
SIG Operation condition
 Time delay is equal to 0
The debounce time of delayed pickup and delayed dropout is recommended to set as
15ms, in order to prevent binary signals from maloperation due to mixed connection of
AC system and DC system.
 Time delay is not equal to 0
The debounce time of delayed pickup and delayed dropout is recommended to set as
(-t1+ t2+Time delay)≥15ms, in order to prevent binary signals from maloperation due to
mixed connection of AC system and DC system. Where, “t1” is the debounce time of
delayed pickup, and “t2” is the debounce time of delayed dropout.
3. Type 4
This type of binary inputs is usually used as auxiliary input condition, and the debounce time
of delayed pickup and delayed dropout is recommended to set as 5ms.
6
When users have their own reasonable setting principles, they can set the
debounce time related settings according to their own setting principles.
6.5.2 Jitter Processing

This device can handle repetitive signal or so-called jitter via binary input module with the following
settings:
[Mon_Window_Jitter] T, monitoring window of binary input jitter processing
[Num_Blk_Jitter] N, times threshold to block binary input status change due to jitter
[Blk_Window_Jitter] T’, blocking window of binary input status change due to jitter
[Num_Reblk_Jitter] N’, times threshold to initiate immediately another blocking

window of binary input status change due to continuous jitter
For a binary input voltage variation, if the jitter processing function is enabled, its handling
principle is:
1. During the T,
a) If the actual jitter times < N, the block will not be initiated and the status change of this
binary input will be considered.

6 Supervision
b) If the actual jitter times ≥ N, the T’ is initiated, and the status change of binary input will
be ignored during the T’.
2. During the T’,
a) If the actual jitter times < N’, the block window will expire. The final status of this binary
input will be compared to the original one before T’, so as to determine whether there is a
change or not.
b) If the actual jitter times ≥ N’, the T’ will be initiated again immediately (i.e. restart the
timer), and the status change of binary input will be ignored during the next T’.
An example of jitter processing is shown in the following sequence chart:
Debounce time ① Input voltage level

(falling edge)
Debounce time
(rising edge)
② Jitter blocking flag
n=N
initiate jitter block
③ Signal after
❶ ❷ ❸ ❹ ❺ debounce & jitter
n = N’ processing
n=5<N=7 Prolong blocking
window
T’
T’ t7 t8
t5 t6
t11
6
T T T’
t1 t2 t3 t4 t9 t10 t
Figure 6.5-3 Sequence chart of jitter processing
①Red line Voltage variation of binary input
②Green line Blocking signal of binary input status change due to jitter
③Blue line Binary input status after debounce and jitter processing
n Actual jitter times
We take N = 7 and N’ = 5 in this example.
3. T = t2 - t1
a) n = 5 < N;

6 Supervision
b) No blocking, ② stays at 0 and ③ is tracing the voltage variation to create SOE events.
4. T = t4 - t3, at t5
a) n = 7 = N;
b) The processing initiates the blocking immediately due to jitter;
c) Jitter blocking, no more SOE event, ② changes its status to 1 and ③ stops the tracing.
5. T’ = t6 - t5
a) At t7, n = 5 =N’, the processing prolongs the blocking immediately due to jitter;
b) Jitter blocking continues, no SOE event, ② stays at 1 and ③ keeps its status.
6. T’ = t8 - t7
a) At t9, n = 5 =N’, the processing prolongs the blocking immediately due to jitter.
b) Jitter blocking continues, no SOE event, ② stays at 1 and ③ keeps its status.
7. T’ = t10 - t9
6 a) n = 2 < N’;
b) At t10, jitter unblocking, ② changes its status to 0 and ③ keeps its status.
8. At t11
a) Debounce time = t11 - t10;
b) ③ restarts to trace the voltage variation to create SOE events.
6.6 Tripping Counter Statistics
The tripping counter statistics function supports statistics of the tripping operation, such as circuit
breakers, disconnectors and so on. For phase separation circuit breaker, when the position of
phase A, B, and C is detected from close state to open state, the total position tripping counter is
added, and the tripping counter is added once when the position of the disconnector is detected
from close state to open state.
In addition, the statistics of the number of state change of circuit breakers and disconnectors are
also provided. The state change counter will add one when the position is detected from close
state to open state or from open state to close state.

6 Supervision
6.7 Supervision Alarms and Handling Suggestion
Hardware circuit and operation status of this device are self-supervised continuously. If any
abnormal condition is detected, information or report will be displayed and a corresponding alarm
will be issued.
A minor abnormality may block a certain number of protections functions while the other functions
can still work. However, if severe hardware failure or abnormality, such as PWR module failure,
DC converter failure and so on, are detected, all protection functions will be blocked and the LED
“HEALTHY” will be extinguished and blocking output contacts “BO_Fail” will be given. The
protective device then cannot work normally and maintenance is required to eliminate the failure.
All the alarm signals and the corresponding handling suggestions are listed below.
If the device is blocked or alarm signal is sent during operation, please do find out its reason with
the help of self-diagnostic record. If the reason cannot be found at site, please notify the factory
NR. Please do not simply press button “TARGET RESET” on the protection panel or re-energize
on the device.
Table 6.7-1 Alarm description
No. Item Description

Fail signals (Device will be blocked)
This signal will be issued if any fail signal picks up and it will drop off when
1 Fail_Device
all fail signals drop off.
6
This signal will be issued if any hardware or software failure is detected in
2 Fail_DeviceInit
the device initialization process.
This signal will be issued due to mismatch between the configuration of
3 Fail_BoardConfig
plug-in modules and the designing drawing of an applied-specific project.
This signal will be issued if the CCD process level configure file is parsed
4 Fail_ProcLevelConfig
wrongly or the type in the file is inconsistent with the actual device.
After configuration file is updated, settings of the file and settings saved on
5 Fail_SettingItem_Chgd the device are not matched. This signal will be issued instantaneously and
will be latched unless the recommended handling suggestion is adopted.
The value of any setting is out of scope. This signal will be issued
6 Fail_Setting_OvRange instantaneously and will be latched unless the recommended handling
suggestion is adopted.
The alarm signal will be issued instantaneously when an error is found
7 Fail_Memory
during checking memory data, and usually, it will automatically drop out.
8 Fail_ProcessConfig The configuration process does not run properly.
The board fails to register the variable, because of abnormal board,
9 Fail_BoardRegister
insufficient memory space, or incorrect configuration.
The board fails to be initialized, because of abnormal board, insufficient
10 Fail_BoardInit
memory space, or incorrect configuration.
Error is found during checking settings. The inappropriate or incorrect value
11 Fail_Settings
is set in a certain application scenario.

6 Supervision

AC current and voltage samplings are abnormal. The sampling values
12 Fail_Sample contains too large DC component or the mutual check of sampling values
from double ADs fails.
Alarm signals (Device will not be blocked)
The device is abnormal. This signal will be issued if any alarm signal picks
13 Alm_Device
up and it will drop off when all alarm signals drop out.
This signal will be issued if any hardware or software configuration wrong is
14 Alm_DeviceInit
detected in the device initialization process.
The error is found during checking the version of software downloaded to
15 Alm_Version the device. This signal will be issued instantaneously and will drop off
instantaneously.
The device is in the communication test mode. This signal will be issued
16 Alm_CommTest
instantaneously and will drop off instantaneously.
The active group set by settings in device and that set by binary input are
17 Alm_BI_SettingGrp not matched. This signal will issued instantaneously and will drop off
instantaneously.
18 Alm_TimeSyn The time synchronization abnormality alarm.
19 Alm_Insuf_Memory The memory of CPU plug-in module is insufficient.
The configuration file of IEC103 is detected to not be correct when this file
20 Alm_CfgFile_IEC103
is parsed in the device initialization process.
CPU module detects that some module is reset due to the abnormality
6 21 Alm_Board
during the device operating.
22 Bxx.Alm_Board An abnormality is detected during the module self-check.
23 Alm_Insuf_NORflash No sufficient NOR flash space used to store the program in CPU module
The network mode is inconsistent, such as the setting is set as HSR mode,
24 Alm_NetMode_Unmatched
but the actual operation mode is PRP mode.
The set value of the setting [RecDur_PostFault] is greater than the set
25 Alm_Settings_DFR
value of the setting [MaxRecDur_PostTrigDFR].
The settings which are stored in CPU module are different with the settings
26 Alm_Settings
which are used by other modules.
The device's master process is abnormal and it is blocked for more than 1
27 Alm_master
minute.
28 Alm_CfgFile_TCP1_DNP The configuration file of DNP client 1 is incorrect.
Function alarm signals (Device will not be blocked)
32 Alm_Maintenance The device is in maintenance state.
33 Alm_BOTest The device is in output test mode.
34 Alm_Sample The quality of sampling values is abnormal.

6 Supervision

Fault detector element operates for more than 50s.
35 Alm_Pkp_FD This signal will pick up with a time delay of 50s and will drop off with a time
delay of 10s.
36 x.Alm_CTS CT secondary circuit at x side fails.
37 x.VTS.Alm VT secondary circuit at x side fails.
38 x.VTNS.Alm Neutral-point VT secondary circuit at x side fails
39 87T.Alm_CTS CT secondary circuit for transformer differential protection fails.
40 x.64REF.Alm_CTS CT secondary circuit for restricted earth fault protection at x side fails.
41 87W.Alm_CTS CT secondary circuit of winding differential protection fails.
42 87T.Alm_Diff Differential current of transformer differential protection is abnormal.
43 x.64REF.Alm_Diff Differential current of restricted earth-fault protection at x side is abnormal.
44 87W.Alm_Diff Differential current of winding differential protection is abnormal.
45 24DT2.Alm Definite-time overexcitation alarm element operates.
46 24IDMT.Alm Inverse-time overexcitation alarm element operates.
47 x.49.Alm Thermal overload protection operates to issue alarm signal.
48 x.50BF.Alm_Init The initiating signal of breaker failure protection is energized consistently.
For synchronism check voltage input channel configuration, the voltage
source to connect to the inputs "in_ref" and "in_syn" should be the same
49 25.Alm_Cfg_Ch
with that used in measurement function, such as BayMMXU and UMMXN.
Otherwise, this alarm will be issued.
If a DPS signal indicating CB/DS/ES position is intermediate or bad, this
CSWIi.DPS.Alm alarm will be issued.
6
50
(i=1~15) This signal will pick up and drop off with a time delay defined by
[CSWIi.DPS.t_Alm].
51 84.Alm_Unmatched The three-phase tap positions are unmatched.
GOOSE alarm signals (Device will not be blocked)
It is an overall alarm signal and will be issued if any of the following alarm
52 GAlm_Overall signals is generated:
“GAlm_CfgFile”, “XX.GAlm_ADisc”, “XX.GAlm_BDisc”, “XX.GAlm_Cfg”
53 GAlm_CfgFile GOOSE alarm signal indicating that GOOSE configuration file is incorrect.
GOOSE alarm signal indicating that the connection of GOOSE network A is
54 XX.GAlm_ADisc
disconnected.
GOOSE alarm signal indicating that the connection of GOOSE network A is
55 XX.GAlm_BDisc
disconnected.
Between GOOSE control blocks received on network and GOOSE control
56 XX.GAlm_Cfg
blocks defined in GOOSE configuration file are unmatched.
Table 6.7-2 Troubleshooting
No. Item Handling suggestion

Fail signals
The signal is issued with other specific fail signals, and please refer to the
1 Fail_Device
handling suggestion other specific alarm signals.

6 Supervision

2 Fail_DeviceInit Please inform the manufacture or the agent for repair.
1. Go to the menu “Information→Borad Info”, check the abnormality
information.
3 Fail_BoardConfig 2. For the abnormality board, if the board is not used, then remove, and if
the board is used, then check whether the board is installed properly and
work normally.
Check whether the CCD process level configuration file of this device is
4 Fail_ProcLevelConfig exist and whether the file content is correct. May need to download and
update the correct CCD process level configuration file.
Please check the settings mentioned in the prompt message on the LCD,
5 Fail_SettingItem_Chgd and go to the menu “Settings” and select “Confirm Settings” item to
confirm settings. Then, the device will restore to normal operation stage.
Please reset setting values according to the range described in the
6 Fail_Setting_OvRange technical manual, then re-power or reboot the device and the device will
restore to normal operation state.
7 Fail_Memory Please inform the manufacture or the agent for repair.
View the menu "Initialization Error" to check the detailed reason, and send
8 Fail_ProcessConfig
the reason to the manufacture or the agent.
9 Fail_BoardRegister Please inform the manufacture or the agent for repair.
View the menu "Initialization Error" to check the detailed reason, and send
10 Fail_BoardInit
the reason to the manufacture or the agent.
6 11 Fail_Settings Please check the settings and set them correctly
Please check whether AC plug-in module is tightly plugged in the chassis. If
12 Fail_Sample
the failure is not eliminated, please replace CPU plug-in module.
Alarm signals
The signal is issued with other specific alarm signals, and please refer to
13 Alm_Device
the handling suggestion other specific alarm signals.
14 Alm_DeviceInit Please inform the manufacture or the agent to deal with it.
Users may pay no attention to the alarm signal in the project commissioning
stage, but it is needed to download the latest package file (including correct
version checksum file) provided by R&D engineer to make the alarm signal
15 Alm_Version disappear. Then users get the correct software version. It is not allowed that
the alarm signal is issued on the device already has been put into service.
the devices having being put into service so that the alarm signal
disappears.
No special treatment is needed, and disable the communication test
16 Alm_CommTest
function after the completion of the test.
Please check the value of the setting [Active_Grp] and binary inputs of
indicating active group, and make them matched. Then the “ALARM” LED
17 Alm_BI_SettingGrp
will be extinguished and the corresponding alarm message will disappear
and the device will restore to normal operation state.

6 Supervision

1. Check whether the selected clock synchronization mode matches the
clock synchronization source;
2. Check whether the wiring connection between the device and the clock
synchronization source is correct
3. Check whether the setting for selecting clock synchronization (i.e.
18 Alm_TimeSyn
[Opt_TimeSyn]) is set correctly. If there is no clock synchronization, please
set the setting [Opt_TimeSyn] as ”No TimeSyn”.
After the abnormality is removed, the “ALARM” LED will be extinguished
and the corresponding alarm message will disappear and the device will
restore to normal operation state.
19 Alm_Insuf_Memory Please inform the manufacture or the agent to deal with it.
Please inform the configuration engineer to check and confirm the contents
20 Alm_CfgFile_IEC103
of IEC 60870-5-103 configuration file.
21 Alm_Board Please inform the manufacture or the agent to deal with it.
22 Bxx.Alm_Board Please inform the manufacture or the agent to deal with it.
23 Alm_Insuf_NORflash Please inform the manufacture or the agent to deal with it.
Check the setting of network mode, or upload the device log and confirm
24 Alm_NetMode_Unmatched
with the manufacturer or agent whether the network mode is supported.
Please check the settings [RecDur_PostFault] and
25 Alm_Settings_DFR
[MaxRecDur_PostTrigDFR], and set them reasonably.
26 Alm_Settings Please inform the manufacture or the agent for repair.
27 Alm_master Please check the load of the device. 6
28 Alm_CfgFile_TCP1_DNP
29 Alm_CfgFile_TCP2_DNP Please contact the configuration engineer to check and confirm the
30 Alm_CfgFile_TCP3_DNP contents of DNP configuration file.
31 Alm_CfgFile_TCP4_DNP
Function alarm signals
It is normal prompt information of the device and does not need to be
32 Alm_Maintenance
handled.
It is normal prompt information of the device and does not need to be
33 Alm_BOTest
handled.
34 Alm_Sample Please check SV qualify if adopting IEC 61850-9-2.
Please check secondary values and protection settings. If settings are not
set reasonable to make fault detectors pick up, please reset settings, and
35 Alm_Pkp_FD
then the alarm message will disappear and the device will restore to normal
operation state.
36 x.Alm_CTS Please check the corresponding CT/VT secondary circuit. After the
37 x.VTS.Alm abnormality is eliminated, “ALARM” LED will go off automatically and
38 x.VTNS.Alm equipment returns to normal operation state.
39 87T.Alm_CTS Please check the corresponding CT secondary circuit. After the abnormality
40 x.64REF.Alm_CTS is eliminated, equipment can return to normal operation state by energizing
41 87W.Alm_CTS the binary input [BI_RstTarg]

6 Supervision

42 87T.Alm_Diff Please check the corresponding sampling values and CT secondary circuit
43 x.64REF.Alm_Diff to find out the reason resulting in the abnormality. If sample values of the
equipment are not correct, please inform the manufacturer or agent for
maintenance, and if it is caused by the failure of the CT secondary circuit or
44 87W.Alm_Diff
primary system, please finish troubleshooting according to the operating
instructions of protection relay.
45 24DT2.Alm
46 24IDMT.Alm Please treat according to the specific application requirements.
47 x.49.Alm
Please check the contacts of binary inputs "x.50BF.ExtTrpA",
48 x.50BF.Alm_Init "x.50BF.ExtTrpB", "x.50BF.ExtTrpC", "x.50BF.ExtTrp3P",
"x.50BF.ExtTrp_WOI".
49 25.Alm_Cfg_Ch Check the channel configuration for synchronism check.
CSWIi.DPS.Alm
50 Check the corresponding DPS signal
(i=1~15)
51 84.Alm_Unmatched Check the tap positions inputs.
GOOSE alarm signals
Please check Ethernet switch of GOOSE network, GOOSE configuration
52 GAlm_Overall
file and GOOSE network.
53 GAlm_CfgFile Please check GOOSE configuration file.
54 XX.GAlm_ADisc
6 55 XX.GAlm_BDisc Please check GOOSE network and GOOSE configuration file.
56 XX.GAlm_Cfg

by default.

7 System Functions
7 System Functions
Table of Contents
7.1 Clock Synchronization .................................................................................... 7-1

7.1.1 Clock Synchronization Mode ................................................................................................ 7-1
7.1.2 Clock Synchronization Abnormality ...................................................................................... 7-1
7.1.3 Clock Synchronization Priority ............................................................................................. 7-1
7.1.4 SNTP Setup .......................................................................................................................... 7-2
7.2 State Information ............................................................................................. 7-3

7.2.1 Overview ............................................................................................................................... 7-3
7.2.2 Access Method ..................................................................................................................... 7-3
7.3 Event Recording .............................................................................................. 7-4

7.3.1 Overview ............................................................................................................................... 7-4
7.3.2 Disturbance Records ............................................................................................................ 7-4
7.3.3 Supervision Events ............................................................................................................... 7-4
7.3.4 Binary Events ....................................................................................................................... 7-4
7.3.5 Device Logs .......................................................................................................................... 7-4 7

7.3.6 Control Logs ......................................................................................................................... 7-4
7.3.7 Access Method ..................................................................................................................... 7-5
7.4 Fault Recording ............................................................................................... 7-5

7.4.1 Overview ............................................................................................................................... 7-5
7.4.2 Fault Report .......................................................................................................................... 7-6
7.4.3 Fault Waveform .................................................................................................................... 7-6
7.4.4 Access Method ..................................................................................................................... 7-7
7.5 Maintenance State ........................................................................................... 7-7

7.6 Communication Test ....................................................................................... 7-8
7.7 Output Test ....................................................................................................... 7-8
7.8 Target Reset ..................................................................................................... 7-9
7.9 Switch Setting Groups .................................................................................... 7-9

7 System Functions

7 System Functions
7.1 Clock Synchronization
7.1.1 Clock Synchronization Mode

The device supports various kinds of clock synchronization methods, including hardware clock
synchronization and software clock synchronization.
1. Hardware clock synchronization ([Opt_TimeSyn]=Conventional)
 IRIG-B: IRIG-B via RS-485 differential level, TTL level or optical fibre interface
 PPS: Pulse per second (PPS) via RS-485 differential level or binary input
 PPM: Pulse per minute (PPM) via RS-485 differential level or binary input
 IEEE1588: Clock message based on IEEE1588 via optical fibre interface
2. Software clock synchronization ([Opt_TimeSyn]=SAS)
 SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network
 SNTP (BC): Broadcast SNTP mode via Ethernet network
 Message (IEC103/Modbus/DNP3.0): Clock messages through IEC103 protocol, Modbus

protocol and DNP3.0 protocol
7.1.2 Clock Synchronization Abnormality

The device provide an alarm signal "Alm_TimeSyn", which indicates the signal of clock
synchronization is abnormal or is lost. The setting [Opt_TimeSyn] should be set reasonably
according to actual clock synchronization source.
If the setting [Opt_TimeSyn] is set as "Conventional" and no hardware clock synchronization 7

signal is connected, the device will automatically switch into software clock synchronization and
issue the alarm signal. If the setting [Opt_TimeSyn] is set as "SAS" and neither hardware clock
synchronization signal nor software clock synchronization signal is connected, the device will
issue the alarm signal. If the setting [Opt_TimeSyn] is set as "NoTImeSyn" and no clock
synchronization signal is connected, the device will not issue the alarm signal. The clock
synchronization is still fulfilled when valid clock synchronization signal is received.
7.1.3 Clock Synchronization Priority

The device provides a priority-based adaptive clock synchronization scheme, which means that
the device can automatically identify multiple clock synchronization sources in the same clock
synchronization mode and choose the highest priority of lock synchronization sources.
When the setting [Opt_TimeSyn] is set as "Conventional", the device can automatically identify
clock synchronization signal among IRIG-B, PPS, PPM and IEC1588. If IRIG-B, PPS, PPM and
IEC1588 exist at the same time, the device selects IRIG-B in priority. If PPS, PPM and IEC1588
exist at the same time, the device selects IEEE1588 in priority.
When the setting [Opt_TimeSyn] is set as "SAS", the device can automatically identify whether

7 System Functions
there is valid hardware clock synchronization signal. The device selects hardware clock
synchronization signal or the combination of hardware clock synchronization signal plus software
clock synchronization signal in priority.
Clock synchronization mode Clock synchronization signal Priority selection

IRIG-B + IEEE1588 + PPS/PPM IRIG-B
IRIG-B + IEEE1588 IRIG-B
Hardware clock synchronization
IRIG-B + PPS/PPM IRIG-B
IEEE1588 + PPS/PPM IEEE1588
Priority 1: IRIG-B
Priority 2: SNTP
Priority 3: Message
IRIG-B + SNTP + Message
Only one kind of clock
synchronization signal is valid
according to the priority
Priority 1: IEEE1588
Priority 2: SNTP
Priority 3: Message
IEEE1588 + SNTP + Message
Only one kind of clock
Software clock synchronization
synchronization signal is valid
Priority 1: PPS/PPM + SNTP
Priority 2: PPS/PPM + Message
Priority 3: PPS/PPM
Priority 4: SNTP
PPS/PPM + SNTP + Message
Priority 5: Message
7 Select clock synchronization signal

(including combination mode)
7.1.4 SNTP Setup
When the device adopts SNTP to realize clock synchronization, [IP_Server_SNTP] and
[IP_StandbyServer_SNTP] shall be set correctly.
[IP_Server_SNTP] is the address of SNTP clock synchronization server which sends SNTP timing
messages to the relay or BCU. [IP_StandbyServer_SNTP] is the address of standby SNTP clock
synchronization server.
Both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are ineffective unless SNTP clock

synchronization is valid.
When both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are set as "0.0.0.0", the device
receives broadcast SNTP synchronization message.
When either [IP_Server_SNTP] or [IP_StandbyServer_SNTP] is set as "0.0.0.0", the device

adopts the setting whose value is not equal to "0.0.0.0" as SNTP server address and receives

7 System Functions
unicast SNTP synchronization message.
If neither [IP_Server_SNTP] nor [IP_StandbyServer_SNTP] is set as "0.0.0.0", the device adopts

the setting [IP_Server_SNTP] as SNTP server address to receive unicast SNTP synchronization
message. If the device does not receive any server response after 30s, it adopts the setting
[IP_StandbyServer_SNTP] as SNTP server address to receive unicast SNTP synchronization
message.
The device will switch between [IP_Server_SNTP] and [IP_StandbyServer_SNTP] repeatedly if it

does not receive any server response in 30s.
7.2 State Information
7.2.1 Overview
The device can provide real-time state information, including analog quantities (such primary
measurement value, secondary measurement value, metering value and so on) and status
quantities (supervision status, input status, output status and so on). By check these state
information, operators can know operation state of the protected equipment and whether the
device is healthy.
7.2.2 Access Method

7.2.2.1 Access by Local HMI (Human Machine Interface)
These state information can be gained via local HMI. The menu path is:
1. Analog quantities
 MainMenu  "Measurements"  "Primary Values"
 MainMenu  "Measurements"  "Secondary Values" 7

 MainMenu  "Measurements"  "Function Values"
 MainMenu  "Measurements"  "UserDef Values"
2. Status quantities
 MainMenu  "Status"  "Inputs"
 MainMenu  "Status"  "Outputs"
 MainMenu  "Status"  "Superv Status"
 MainMenu  "Status"  "Running Status"
 MainMenu  "Status"  "UserDef Status"
7.2.2.2 Access by Virtual HMI
Using the virtual LCD tool, the corresponding content can be viewed through the same menu path
as local LCD.

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7.2.2.3 Access by Communication Client
Device's state information can be uploaded into clients through message communication. For
differential protocols, the state information can be gained through corresponding communication
service.
7.2.2.4 Access by Printer
The device can print the current state information, so that the operator can observe and save the
current operation condition. The access path is:
MainMenu  "Print"  "Device Status"
7.3 Event Recording
7.3.1 Overview
The device can store the latest 1024 time-stamped disturbance records, 1024 time-stamped
binary events, 1024 time-stamped supervision events, 256 time-stamped control logs and 1024
time-stamped device logs. All the records are stored in non-volatile memory, and when the
available space is exhausted, the oldest record is automatically overwritten by the latest one.
7.3.2 Disturbance Records
When any protection element operates or drops out, such as fault detector, distance protection
etc., they will be logged in event records. Disturbance records include signal name, its value
before and after changing, and the time precision is up to 1ms.
7.3.3 Supervision Events
The device is under automatic supervision all the time. If there are any failure or abnormal
7 condition detected, such as, chip damaged, VT circuit failure and so on, it will be logged in event
records. Supervision events include signal name, its value before and after changing, and the
time precision is up to 1ms.
7.3.4 Binary Events
When there is a binary input is energized or de-energized, i.e., its state has changed from “0” to “1”
or from “1” to “0”, it will be logged in event records. Binary events include signal name, its value
7.3.5 Device Logs
If an operator executes some operations on the device, such as reboot protective device, modify
setting, etc., they will be logged in event records. Device logs include signal name, its value
7.3.6 Control Logs
When an operator executes a control command via local LCD, PCS-Studio or communication
client, it will be logged in control logs. Control logs include time stamp, controlled object, control

7 System Functions
origination, control position, operation condition, interlocking condition, control command and
operation result.
7.3.7 Access Method

7.3.7.1 Access by Local HMI
The device provides corresponding menus to view event recorders. The menu path is:
MainMenu  "Test"  "Disturb Events"
MainMenu  "Records"  "Superv Events"
MainMenu  "Records"  "IO Events"
MainMenu  "Records"  "Device Logs"
MainMenu  "Records"  "Control Logs"
as local LCD.
Event recorders can be uploaded into clients through corresponding communication service of the
protocol (including IEC60870-5-103, IEC61850, DNP3.0).
The device can print event recorders, so that the operator can observe and save the current
operation condition. The access path is:
MainMenu  "Print"  "Superv Events"

7
MainMenu  "Print"  "IO Events"
7.4 Fault Recording

7.4.1 Overview
Fault recorder can be used to have a better understanding of the behavior of the power network
and related primary and secondary equipment during and after a disturbance. Analysis of the
recorded data provides valuable information that can be used to improve existing equipment. This
information can also be used when planning for and designing new installations.
The fault recorder is comprised of the report and the waveform, which can be triggered by pickup
signals, trip signals and configurable binary signal [BI_TrigDFR].
The fault memory of the device is automatically updated with every recording. When the fault
memory is filled completely, the oldest records are overwritten automatically. Thus, the most
recent recordings are always stored safely. The maximum number of recordings is 32.

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7.4.2 Fault Report

For each fault report, the following items are included:
1. Sequence number
Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.
2. Date and time of fault occurrence
The date and time is recorded when a system fault is detected. The time resolution is 1ms.
3. Relative operating time
An operating time (not including the operating time of output relays) is recorded in the record. The
time resolution is 1ms.
4. Fault information
Including faulty phase, fault location and protection elements
7.4.3 Fault Waveform

A fault waveform contains all analog and digital quantities related to protection such as currents,
voltages, differential current, alarm elements, and binary inputs and etc.
The overall duration of a single fault recording comprises the total duration of the configurable
recording criterion, the pre-trigger time and the post-trigger time. With the fault recording
parameter, these components can be individually set. The pre-trigger waveform recorded duration
is configured via the setting [RecDur_PreTrigDFR]. The waveform recorded duration after the fault
disappears is configured via the setting [RecDur_PostFault]. The maximum post-trigger waveform
7 recorded duration is configured via the setting [MaxRecDur_PostTrigDFR].
4. [MaxRecDur_PostTrigDFR]
1. [RecDur_PreTrigDFR] 2.Pickup 3. [RecDur_PostFault]
Trigger point
Total recording time
1. Pre-trigger recording time
Use the setting [RecDur_PreTrigDFR] to set this time.
2. Pickup recording time
The pickup recording time cannot be set. It continues as long as any valid trigger condition, binary
or analog, persists (unless limited by the limit time, which is determined by the setting
[MaxRecDur_PostTrigDFR]).
3. Post-fault recording time

7 System Functions
The recording time begins after all activated triggers are reset. Use the setting [RecDur_PostFault]
to set this time.
4. Maximal post-trigger recording time
Use the setting [MaxRecDur_PostTrigDFR] to set this time. If the summation of pickup recording
time and post-fault recording time is larger than maximal post-trigger recording time, the
post-trigger recording time shall be equal to the setting [MaxRecDur_PostTrigDFR].
7.4.4 Access Method

7.4.4.1 Access by Local HMI
The device provides corresponding menus to check fault recording. The menu path is:
MainMenu  "Records"  "Disturb Records"
as local LCD.
Fault recording can be uploaded into clients through corresponding communication service of the
protocol (including IEC60870-5-103, IEC61850, DNP3.0).
The device can print fault recording, so that the operator can observe and save the current
operation condition. The access path is:
MainMenu  "Print"  "Disturb Records"

7
7.5 Maintenance State
The device provides maintenance state, i.e., the binary input [BI_Maintenance] is energized,
which is convenient for maintenance work. For adopting conventional CT/VT, binary inputs and
binary outputs, maintenance state has no influence on protection logics. For binary inputs and
binary outputs by GOOSE connections. During device maintenance, the object will send GOOSE
message with Test quality attribute. The Test quality attribute indicates to the receiver device that
the object received via a GOOSE message was created under test conditions and not operating
conditions. If the Test quality attribute received is different with the object's Test quality attribute,
binary inputs and binary outputs by GOOSE connections will be affected based on different types
of binary inputs and binary outputs. For SV (Sampling Value) message, if the Test quality attribute
received is different with the object's Test quality attribute, the relevant protection functions will be
blocked.
For IEC60870-5-103 protocol, only the messages in link layer maintained, service messages in
the application layer which is uploaded automatically are blocked, and service messages in the
application layer which is issued by the client are rejected. For IEC61850 protocol, all Test quality

7 System Functions
attribute set as "1". For DNP3.0 and ModBus protocol, they are not affected.
7.6 Communication Test
The device provides Test Mode to allow all protection elements, supervision events and binary
events to fulfill communication test, but to avoid the output contacts to close. During
communication test, protection functions are not affected, the signals generated by
communication test are recorded in relevant reports, and event recording and fault recording will
not stop recording disturbance information. The alarm signal "Alm_CommTest" will be issued to
indicate the operator when activating Test Mode and exiting Test Mode.
Communication test can be gained via local HMI and the virtual HMI, the corresponding content
can be viewed through the following menu paths:
 Events Simulation
Main Menu  "Test"  "Device Test"  "Disturb Events"
Main Menu  "Test"  "Device Test"  "Superv Events"
Main Menu  "Test"  "Device Test"  "IO Events"
 Forced Measurements
Main Menu  "Test"  "Device Test"  "Measurements"
Forced measurement ONLY affects the values modified and transmitted to

7 station control or control center. Primary circuit, secondary circuit and
device local logic will not be influenced. Forced value will remain during the
test until the exit of this menu.
If no input operation is carried out within 60s, this test will exit and return to
the previous menu automatically.
7.7 Output Test

The device provides Output Test Mode to test all outputs. Through this mode, there will be real
operations, such as contact closing and GOOSE output value change, triggered by the device to
test output circuits and links. So, protection functions outputs and the connecting primary
equipments are affected. The output signals generated by output test are not recorded, while the
entering and exiting of output test mode will be recorded in Superv Events. During the output test,
the protection functions will not stop, nor will the all recording functions.
Output test can be gained via the local LCD or virtual HMI of a debugging PC, the corresponding
content can be viewed through the following menu paths:
 Contacts Outputs

7 System Functions
Main Menu  "Test"  "Device Test"  "Contact Outputs"
 GOOSE Outputs
Main Menu  "Test"  "Device Test"  "GOOSE Outputs"
Dismantle the wiring connection if any influence on relevant primary

equipments is undesired. The output test will cause operation of relay
contacts through secondary circuit and GOOSE link.
7.8 Target Reset
The device provides target reset which can be used to reset local signals (including magnetic
latching output relays), latched LEDs, and confirm pop-up windows of reports. The function does
not affect the protection logic and communication function. There are several ways to reset.
1. Reset via local HMI
 Access menu path: MainMenu  "Local Cmd"  "Reset Target"
 Press the command pushbutton “ESC”+“ENT” on operation panel of the device under
main interface
 Press the command pushbutton " TARGET RESET" on operation panel of the device
2. Reset via virtual HMI
Access menu path: MainMenu  "Local Cmd"  "Reset Target"

7
3. Reset via binary input
Energize the binary input "BI_RstTarg"
4. Reset via IEC61870-5-103
Use ASDU20, INF19 of IEC61870-5-103 protocol
5. Reset via remote control
Use standard remote service of corresponding protocol
7.9 Switch Setting Groups
For different applications users can save the respective function settings in so-called settings
groups, and if necessary enable them quickly. Up to 10 different settings groups can be saved in
the device. In the process, only one settings group is active at any given time. During operation,
the operator can switch between setting groups.
The device will be temporarily blocked during switching setting groups. During temporary device

7 System Functions
blocking, the device will loss protection functions and communication functions. Alarm signals
"Fail_Device" and "Alm_Device" will be issued. There are several ways to switch setting groups.
1. Switch via local HMI
 Access menu path: MainMenu  "Setting"  "Global Settings"  "System Settings",

change the value of the setting [Active_Grp]
 Press the command pushbutton “MENU” under main interface (password is required)
2. Switch via virtual HMI
Access menu path: MainMenu  "Setting"  "Global Settings"  "System Settings",

modify the setting [Active_Grp]
3. Switch via binary inputs
There are 2 appropriate input signals available for switching setting group via binary inputs.
These input signals allow selection of the settings group via a binary code. If one of two
signals changes, the signal image present will result in switching over to the appropriate
settings group. If only 2 settings groups must be switched over, only 1 binary input is required.
The following table shows the possible binary codes and applicable setting groups.
External input signals can be connected with "setting_grp_bit0" and "setting_grp_bit1"

respectively by PCS-Studio.
Binary codes Group 1 Group 2 Group 3 Group 4

setting_grp_bit1 0 0 1 1
setting_grp_bit0 0 1 0 1
4. Switch via communication client

7 The communication protocols IEC 60870-5-103 or IEC 61850 can be used for switching the
setting groups via a communication connection.
 Use "General Service" of IEC61870-5-103 protocol to modify the setting [Active_Grp]
 Use "SelectActiveSG" of IEC61850 protocol to switch setting groups.

8 Hardware
8 Hardware
Table of Contents
8.1 Overview ........................................................................................................... 8-1

8.2 Typical Wiring .................................................................................................. 8-4
8.3 CT Requirement ............................................................................................. 8-10
8.4 Plug-in Module Description ...........................................................................8-11
8.4.1 Human-machine Interface Module (NR6855/NR6856) ...................................................... 8-12
8.4.2 Power Supply Module (NR6305/NR6310) ......................................................................... 8-12
8.4.3 CPU Module (NR6106) ...................................................................................................... 8-15
8.4.4 AC Analog Input Module (NR6641) .................................................................................... 8-18
8.4.5 Binary Input Module (NR6601/NR6610) ............................................................................ 8-21
8.4.6 Binary Output Module (NR6651/NR6652/NR6660) ........................................................... 8-24
8.4.7 DC Analog Input Module (NR6630/NR6631) ..................................................................... 8-28
List of Figures
Figure 8.1-1 Hardware diagram ................................................................................................ 8-1
Figure 8.1-2 Front view of PCS-978S ......................................................................................... 8-3
Figure 8.1-3 Typical rear view of PCS-978S with ring ferrule .................................................. 8-3
Figure 8.1-4 Typical rear view of PCS-978S with pin ferrule .................................................... 8-3 8
Figure 8.2-1 Typical hardware configuration with ring ferrule (6U, 1/1) .................................. 8-4
Figure 8.2-2 Typical hardware configuration with ring ferrule (6U, 1/2) .................................. 8-4
Figure 8.2-3 Typical wiring with ring ferrule (6U, 1/1) .............................................................. 8-5
Figure 8.2-4 Typical wiring with ring ferrule ((6U, 1/2)) ............................................................ 8-6
Figure 8.2-5 Typical hardware configuration with pin ferrule (6U, 1/1) ................................... 8-7
Figure 8.2-6 Typical hardware configuration with pin ferrule (6U, 1/2) ................................... 8-7
Figure 8.2-7 Typical wiring with pin ferrule (6U, 1/1) ................................................................ 8-8
Figure 8.2-8 Typical wiring with pin ferrule (6U, 1/2) ................................................................ 8-9
Figure 8.4-1 View of power supply module ............................................................................. 8-12

8 Hardware
Figure 8.4-2 View of CPU module ............................................................................................ 8-16
Figure 8.4-3 Connection of communication terminal .......................................................... 8-17
Figure 8.4-4 Jumpers of printer/RS-485 port ........................................................................ 8-17
Figure 8.4-5 Schematic diagram of CT circuit automatically closed ................................. 8-18
Figure 8.4-6 Terminal definition of analog input module .................................................... 8-19
Figure 8.4-7 Current connection examples .......................................................................... 8-20
Figure 8.4-8 Voltage connection examples........................................................................... 8-21
Figure 8.4-9 View of binary input module (NR6601A).......................................................... 8-22
Figure 8.4-10 View of binary input module (NR6610A and NR6610B) ............................... 8-23
Figure 8.4-11 View of binary output module (NR6651A) ..................................................... 8-25
Figure 8.4-12 View of binary output module (NR6651B) ..................................................... 8-26
Figure 8.4-15 View of DC analog input module NR6630A ................................................... 8-29
Figure 8.4-17 View of DC analog input module NR6631 ..................................................... 8-31
Figure 8.4-18 Wiring method of the RTD sensor.................................................................. 8-33
List of Tables
Table 8.4-1 Terminal definition and description of power supply module ............................. 8-13
Table 8.4-2 Terminal definition and description of power supply module ............................. 8-14
8 Table 8.4-3 Configuration and terminal definition of CPU module......................................... 8-16
Table 8.4-4 Terminal definition and description of binary input module ............................... 8-22
Table 8.4-5 Terminal definition and description of binary input module ............................... 8-24

8 Hardware
8.1 Overview
The modular design of this device allows this device to be easily upgraded or repaired by a
qualified service person. The faceplate is hinged to allow easy access to the configurable
modules, and back-plugging structure design makes it easy to repair or replace any module.
This device adopts one 32-bit ARM core in the CPU chip as control core for management and
monitoring function, and adopts another 32-bit ARM core in the CPU chip for all the protection
calculation. The parallel processing of sampled data can be realized in each sampling interval to
ensure ultrahigh reliability and safety of the device.
This device is developed on the basis of our latest software and hardware platform, and the new
platform major characteristics are of high reliability, networking and great capability in
anti-interference. See Figure 8.1-1 for the hardware diagram.
External
Binary Input
Conventional CT/VT A/D

Output
ARM1
Relay
A/D
Pickup
Electronic/Optic CT/VT Relay
ETHERNET
+E
LCD
Clock SYN
Power
Uaux LED ARM2
Supply
RJ45
Keypad
PRINT
Figure 8.1-1 Hardware diagram
The working process of the device is as shown in above figure: the currents and voltages from
conventional CT/VT are converted into small voltage signal and sent to ARM1 core after filtered
and A/D conversion for protection calculation and fault detector respectively (electronic/optic
CT/VT signals are sent to the device without A/D conversion). The ARM1 core carries out fault
detector, protection logic calculation, tripping output, and the ARM2 core performs SOE 8
(sequence of event) record, waveform recording, printing, communication between the device and
SAS and communication between HMI and CPU. When the fault detector detects a fault and picks
up, the positive power supply for output relay is provided.
The items can be flexibly configured depending on the situations like sampling method of the
device (conventional CT/VT or ECT/EVT), and the mode of binary output (conventional binary
output or GOOSE binary output). The configurations for PCS S series based on microcomputer
are classified into standard and optional modules.

8 Hardware
Table 8.1-1 Module configuration of this device
Module ID Module description Remark

NR6855/NR6856 Human machine interface module (HMI module) Mandatory
NR6305/NR6310 Power supply module (PWR module) Mandatory
NR6106 Main CPU module (CPU module) Mandatory
NR6641 AC analog input module (AC AI module) Mandatory
NR6601/NR6610 Binary input module (BI module) Mandatory
NR6651/NR6652//NR6660 Binary output module (BO module) Mandatory
NR6630/NR6631 DC analog input module (DC AI module) Optional
 HMI module is comprised of LCD, keypad, LED indicators and multiplex RJ45 ports for user
as human-machine interface.
 PWR module converts AC100V/110V/115V/120V/127V/220V/230V/240V/250V or

DC110V/125V/220V/250V into various DC voltage levels for modules of the device.
 CPU module provides functions like communication with SAS, event record, setting
management etc., and performs filtering, sampling, protection calculation and fault detector
calculation.
 AC AI module converts AC current and voltage from current transformers and voltage
transformers respectively to small voltage signal.
 BI module provides binary inputs via opto-couplers with rating voltage among AC110V/220V
or DC24V~250V (configurable).
 BO module provides output contacts for tripping, and signal output contact for annunciation
signal, remote signal, fault and disturbance signal, operation abnormal signal etc.
 DC AI module provides DC analog input channels 0~±20mA or 0~±10Vdc.
PCS-978S is made of a 6U height 19” chassis. Components mounted on its front include a
320×240 dot matrix LCD, a 9 button keypad, four programmable buttons, 20 LED indicators and a
multiplex RJ45 port. A monolithic micro controller is installed in the device for these functions.
Following figures show front and rear views of this device respectively.

8 Hardware
Figure 8.1-2 Front view of PCS-978S
Figure 8.1-3 Typical rear view of PCS-978S with ring ferrule
Figure 8.1-4 Typical rear view of PCS-978S with pin ferrule

8 Hardware
8.2 Typical Wiring

B01 B02 & B03 B04 & B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 P1
NR6106BA NR6641-6I6U NR6641-12I Option Option Option Option Option Option Option NR6601A NR6651A NR6305A
01 Ia1 Ia1n 02 01 Ia1 Ia1n 02 01 BI_01 BI_02 02 01 BO_01 02 01 BI_01+ BI_01- 02
03 Ib1 Ib2n 04 03 Ib1 Ib2n 04 03 BI_03 BI_04 04 03 BO_02 04 03 BI_02+ BI_02- 04
NET 05 Ic1 Ic1n 06 05 Ic1 Ic1n 06 05 BI_05 BI_06 06 05 BO_03 06 05 BI_COM BI_03 06
07 Ia2 Ia2n 08 07 Ia2 Ia2n 08 07 BI_07 BI_08 08 07 BO_04 08 07 BI_04 BI_05 08

LC
09 Ib2 Ib2n 10 09 Ib2 Ib2n 10 09 BI_09 BI_10 10 09 BO_05 10 09 BI_06 BI_07 10
LC
11 Ic2 Ic1n 12 11 Ic2 Ic1n 12 11 BI_11 BI_02 12 11 BO_06 12 11 BI_08 BI_09 12
13 Ua1 Ua1n 14 13 Ia3 Ia31n 14 13 BI_13 BI_02 14 13 BO_07 14 13 BO_01 14
15 Ub1 Ub1n 16 15 Ib3 Ib3n 16 15 BI_15 BI_02 16 15 BO_08 16 15 BO_02 16
17 Uc1 Uc1n 18 17 Ic3 Ic3n 18 17 BI_17 BI_02 18 17 BO_09 18 17 BO_03 18
01 1A 19 Ua2 Ua2n 20 19 Ia4 Ia14n 20 19 BI_19 BI_02 20 19 BO_10 20 19 BO_04 20

02 1B
03 SGND 21 Ub2 Ub2n 22 21 Ib4 Ib4n 22 21 BI_21 BI_02 22 21 BO_11 22 21 BO_05 22
04 2A
23 Uc2 Uc2n 24 23 Ic4 Ic4n 24 23 BI_23 BI_24 24 23 BO_12 24 23 BO_Fail 24
05 2B
06 SGND
25 BI_25 BI_COM 26 25 BO_13 26 25 PWR+ PWR- 26
07 SYN+
08 SYN-
09 SGND
10 SYN-TTL
CONSOLE
Ground
Figure 8.2-1 Typical hardware configuration with ring ferrule (6U, 1/1)
B01 B02 & B03 B04 B05 B06 P1
NR6106BA NR6641-6I6U Option NR6601A NR6651A NR6305A
01 Ia1 Ia1n 02 01 BI_01 BI_02 02 01 BO_01 02 01 BI_01+ BI_01- 02
03 Ib1 Ib2n 04 03 BI_03 BI_04 04 03 BO_02 04 03 BI_02+ BI_02- 04
NET 05 Ic1 Ic1n 06 05 BI_05 BI_06 06 05 BO_03 06 05 BI_COM BI_03 06
07 Ia2 Ia2n 08 07 BI_07 BI_08 08 07 BO_04 08 07 BI_04 BI_05 08

LC
09 Ib2 Ib2n 10 09 BI_09 BI_10 10 09 BO_05 10 09 BI_06 BI_07 10
LC
11 Ic2 Ic1n 12 11 BI_11 BI_02 12 11 BO_06 12 11 BI_08 BI_09 12
13 Ua1 Ua1n 14 13 BI_13 BI_02 14 13 BO_07 14 13 BO_01 14
15 Ub1 Ub1n 16 15 BI_15 BI_02 16 15 BO_08 16 15 BO_02 16
17 Uc1 Uc1n 18 17 BI_17 BI_02 18 17 BO_09 18 17 BO_03 18
01 1A 19 Ua2 Ua2n 20 19 BI_19 BI_02 20 19 BO_10 20 19 BO_04 20

02 1B
03 SGND 21 Ub2 Ub2n 22 21 BI_21 BI_02 22 21 BO_11 22 21 BO_05 22
04 2A
23 Uc2 Uc2n 24 23 BI_23 BI_24 24 23 BO_12 24 23 BO_Fail 24
05 2B
06 SGND
25 BI_25 BI_COM 26 25 BO_13 26 25 PWR+ PWR- 26
07 SYN+
08 SYN-
09 SGND
10 SYN-TTL
CONSOLE
Ground
8
Figure 8.2-2 Typical hardware configuration with ring ferrule (6U, 1/2)
The wiring is given based on above hardware configuration

8 Hardware
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0215
0216
0217
0218
0219
0220
0221
0222
0223
0224
0213
0214
Ia1 Ib1 Ic1 Ia2 Ib2 Ic2 Ua1 Ub1 Uc1 Ua2 Ub2 Uc2
BI_01 + 1301
Ethernet (RJ 45 and LC-

Connector)
BI_02 + 1302
To SCADA
…
BI_25 + 1325
1326 -
BI_01 + P101
- P102
BI_02 + P103
- P104
BI_03 + P106
1A 0101
COM
1B 0102 BI_04 + P107

SGND 0103
cable with single point earthing
…
To the screen of other coaxial
2A 0104
COM
2B 0105 BI_09 + P112

SGND 0106
P105 -
SYN+ 0107 P113
Clock SYN
SYN- 0108 BO_01 P114

SGND 0109 P115
TTL 0110 BO_02 P116
…
Console P121
BO_05 P122
1401 P123
1402 BO_01 BO_Fail P124
1403
1404 BO_02 P125 PWR+
Power External DC power
…
1425 Supply P126 supply

PWR-
1426 BO_13
Grounding Bus
Ic4 Ib4 Ia4 Ic3 Ib3 Ia3 Ic2 Ib2 Ia2 Ic1 Ib1 Ia1
8
0414
0413
0424
0423
0422
0421
0420
0419
0418
0417
0416
0415
0412
0411
0410
0409
0408
0407
0406
0405
0404
0403
0402
0401
Figure 8.2-3 Typical wiring with ring ferrule (6U, 1/1)

8 Hardware
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0215
0216
0217
0218
0219
0220
0221
0222
0223
0224
0213
0214
BI_01 + 0501

Connector) BI_02 + 0502
To SCADA
…
BI_25 + 0525
0526 -
BI_01 + P101
- P102
BI_02 + P103
- P104
BI_03 + P106
1A 0101
COM
1B 0102 BI_04 + P107

SGND 0103
…
2A 0104
COM
2B 0105 BI_09 + P112

SGND 0106
P105 -
SYN+ 0107 P113
Clock SYN
SYN- 0108 BO_01 P114

SGND 0109 P115
TTL 0110 BO_02 P116
…
Console P121
BO_05 P122
0601 P123
0602 BO_01 BO_Fail P124
0603
0604 BO_02 P125 PWR+
Power External DC power
…
0625 Supply P126 supply

PWR-
0626 BO_13
Grounding Bus
8
Figure 8.2-4 Typical wiring with ring ferrule ((6U, 1/2))

8 Hardware
B01 B02 & B03 B04 & B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 P1
NR6106BA NR6641-6I6U NR6641-12I Option Option Option Option Option Option Option NR6610A NR6660A NR6310A
01 Ia1 Ia1n 02 01 Ia1 Ia1n 02 BI_01 01 01 BI_01+ 01

BO1
BI_02 02 02 BI_01- 02
03 Ib1 Ib1n 04 03 Ib1 Ib1n 04 BI_03 03 03 BI_02+ 03
BO2
05 Ic1 Ic1n 06 05 Ic1 Ic1n 06 BI_04 04 04 BI_02- 04
NET BI_05 05 05 BI_COM 05
07 Ia2 Ia2n 08 07 Ia2 Ia2n 08 BO3
BI_06 06 06 BI_03 06
LC
09 Ib2 Ib2n 10 09 Ib2 Ib2n 10 BI_07 07 07 BI_04 07
BO4
LC BI_08 08 08 BI_05 08
11 Ic2 Ic2n 12 11 Ic2 Ic2n 12 BI_09 09 09 BI_06 09
BO5
13 Ua1 Ua1n 14 13 Ia3 Ia31n 14 BI_10 10 10 BI_07 10
BI_11 11 11 BI_08 11
15 Ub1 Ub1n 16 15 Ib3 Ib3n 16 BO6
BI_12 12 12 BI_09 12
17 Uc1 Uc1n 18 17 Ic3 Ic3n 18 BI_13 13 13 13

BO7 BO_01
BI_14 14 14 14
19 Ua2 Ua2n 20 19 Ia4 Ia14n 20 BI_15 15 15 15
BO8 BO_02
21 Ub2 Ub2n 22 21 Ib4 Ib4n 22 BI_16 16 16 16
17 17 17
23 Uc2 Uc2n 24 23 Ic4 Ic4n 24 BI_COM BO9 BO_03
18 18 18
19
BI_17 19 19 BO_04
B10 20
BI_18 20 20
21
BI_19 21 21 BO_05
B11 22
BI_20 22 22
BI_21 23 23 23
B12 BO_Fail
01 1A BI_22 24 24 24
02 1B
BI_23 25 25 PWR+ 25
03 SGND B13
04 2A
BI_24 26 26 PWR- 26
05 2B BI_25 27 27
B14
06 SGND BI_26 28 28
07 SYN+
BI_27 29 29
08 SYN- B15
09 SGND
BI_28 30 30
10 SYN-TTL BI_29 31 BO16-COM 31
BI_30 32 BO16-NO 32
BI_31 33 BO16-NC 33
CONSOLE
BI_32 34 BO17-COM 34
35 BO17-NO 35
BI_COM
36 BO17-NC 36 Ground
Figure 8.2-5 Typical hardware configuration with pin ferrule (6U, 1/1)
B01 B02 & B03 B04 B05 B06 P1
NR6106BA NR6641-6I6U Option NR6610A NR6660A NR6310A
01 Ia1 Ia1n 02 BI_01 01 01 BI_01+ 01

BO1
BI_02 02 02 BI_01- 02
03 Ib1 Ib1n 04 BI_03 03 03 BI_02+ 03
BO2
05 Ic1 Ic1n 06 BI_04 04 04 BI_02- 04
NET BI_05 05 05 BI_COM 05
07 Ia2 Ia2n 08 BO3
LC BI_06 06 06 BI_03 06
09 Ib2 Ib2n 10 BI_07 07 07 BI_04 07

BO4
LC BI_08 08 08 BI_05 08
11 Ic2 Ic2n 12 BI_09 09 09 BI_06 09
BO5
13 Ua1 Ua1n 14 BI_10 10 10 BI_07 10
BI_11 11 11 BI_08 11
15 Ub1 Ub1n 16 BO6
BI_12 12 12 BI_09 12
17 Uc1 Uc1n 18 BI_13 13 13 13

BO7 BO_01
BI_14 14 14 14
19 Ua2 Ua2n 20 BI_15 15 15 15
BO8 BO_02
21 Ub2 Ub2n 22 BI_16 16 16 16
17 17 17
23 Uc2 Uc2n 24 BI_COM BO9 BO_03
18 18 18
BI_17
BI_18
19
20
BO10
19
20
BO_04
19
20
21
8
BI_19 21 21 BO_05
BO11 22
BI_20 22 22
BI_21 23 23 23
BO12 BO_Fail
01 1A BI_22 24 24 24
02 1B
BI_23 25 25 PWR+ 25
03 SGND BO13
04 2A
BI_24 26 26 PWR- 26
05 2B BI_25 27 27
BO14
06 SGND BI_26 28 28
07 SYN+
BI_27 29 29
08 SYN- BO15
09 SGND
BI_28 30 30
10 SYN-TTL BI_29 31 BO16-COM 31
BI_30 32 BO16-NO 32
BI_31 33 BO16-NC 33
CONSOLE
BI_32 34 BO17-COM 34
35 BO17-NO 35
BI_COM
36 BO17-NC 36 Ground
Figure 8.2-6 Typical hardware configuration with pin ferrule (6U, 1/2)

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The wiring is given based on above hardware configuration
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0215
0216
0217
0218
0219
0220
0221
0222
0223
0224
0213
0214
BI_01 + 1301

Connector)
BI_02 + 1302
To SCADA
…
BI_16 + 1316
1317 -
1318 -
BI_17 + 1319
BI_18 + 1320
…
BI_32 + 1334
1A 0101
COM
1B 0102 1335 -
SGND 0103 1336 -
BI_01 + P101
2A 0104
COM
2B 0105 - P102
SGND 0106
BI_02 + P103 -
SYN+ 0107
Clock SYN
SYN- 0108 - P104
SGND 0109 BI_03 + P106

TTL 0110
Console BI_04 + P107

…
1401
1402 BO_01
BI_09 + P112
1403
1404 BO_02 P105
…
P113
1417 BO_01
BO_09 P114
1418
P115
1419 BO_02 P116
BO_10
…
1420
P121
1421 BO_05
BO_11 P122
1422
P123
…
8 1431
1432 BO_16
BO_16
BO_Fail
Power
P124
P125 PWR+
External DC power
1433
Supply P126 supply
1434 PWR-
1435 BO_17
1436 BO_17
Grounding Bus
Ic4 Ib4 Ia4 Ic3 Ib3 Ia3 Ic2 Ib2 Ia2 Ic1 Ib1 Ia1
0414
0413
0424
0423
0422
0421
0420
0419
0418
0417
0416
0415
0412
0411
0410
0409
0408
0407
0406
0405
0404
0403
0402
0401
Figure 8.2-7 Typical wiring with pin ferrule (6U, 1/1)

8 Hardware
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0215
0216
0217
0218
0219
0220
0221
0222
0223
0224
0213
0214
BI_01 + 0501

Connector)
BI_02 + 0502
To SCADA
…
BI_16 + 0516
0517 -
0518 -
BI_17 + 0519
BI_18 + 0520
…
BI_32 + 0534
1A 0101
COM
1B 0102 0535 -
SGND 0103 0536 -
BI_01 + P101
2A 0104
COM
2B 0105 - P102
SGND 0106
BI_02 + P103 -
SYN+ 0107
Clock SYN
SYN- 0108 - P104
SGND 0109 BI_03 + P106

TTL 0110
Console BI_04 + P107

…
0601
0602 BO_01
BI_09 + P112
0603
0604 BO_02 P105
…
P113
0617 BO_01
BO_09 P114
0618
P115
0619 BO_02 P116
BO_10
…
0620
8
P121
0621 BO_05
BO_11 P122
0622
P123
…
0631 BO_Fail P124

0632 BO_16 P125 PWR+
BO_16 Power External DC power
0633
Supply P126 supply
0634 PWR-
0635 BO_17
0636 BO_17
Grounding Bus
Figure 8.2-8 Typical wiring with pin ferrule (6U, 1/2)

8 Hardware
8.3 CT Requirement
1. CT Types
Generally there are three types of CT: high remanence, low remanence and no remanence.
 High remanence: TPX, TPS, P, PX.
 Low remanence: TPY, PR, and the residual magnetism does not exceed 10% of the
saturation flux.
 No remanence: TPZ level, residual magnetism can actually be ignored.
The high residual magnetism CT may have large residual magnetism. When the fault
non-periodic component and residual magnetism are in the same direction, the CT saturation
degree will be more serious. The following CT type checking calculation takes into account
the maximum residual magnetism of CT and the maximum non periodic component on the
site.
2. CT Requirement
Rated secondary limit e.m.f (volts) formula:
Esl = Kalf × Isn × (Rct + Rbn)
Kalf Accuracy limit factor: Kalf = Ipal / Ipn
Isn Rated secondary current (amps)
Rct Current transformer secondary winding resistance (ohms)
Sbn Rated burden (VAs)
Rbn Rated resistance burden (ohms): Rbn = Sbn / Isn2
Actual secondary limit e.m.f (volts) under different fault conditions:
Esl1′ = k1×Ipcf1 ×Isn×(Rct+Rb)/Ipn
Esl2′ = k2×Ipcf2 ×Isn×(Rct+Rb)/Ipn
Esl3′ = k3×Ipnt×Isn×(Rct+Rb)/Ipn
Esl4′ = k4×Ipcf4×Isn×(Rct+Rb)/Ipn
8 k1, k2, k3, k4 are transient factors.
Ipcf1 Maximum through fault current when out-zone fault (amps)
Maximum fault current through two bridge CB but not transformer when
Ipcf2
out-zone fault (amps)
Ipcf4 Maximum fault current when in-zone fault (amps)
Ipnt Transformer rated primary current (amps)
Ipn CT rated primary current (amps)

Isn CT rated secondary current (amps)

8 Hardware
Rct Current transformer secondary winding resistance (ohms)
Rb Real resistance burden (ohms): Rb = Rr + 2RL
RL Resistance of a single lead from relay to the CT (ohms)
Rr Impedance of relay phase current input (ohms)
3. K Value Requirement
1) Single CB connection, the following condition should be fulfilled
Esl > Esl1′
Esl > min (Esl3′, Esl4′)
While: k1=2，k3=30，k4=1.
2) Double CB connection, the following condition should be fulfilled:
Esl > Esl1′
Esl > Esl2′
Esl > min (Esl3′, Esl4′)
If both CTs of double CB are low remanence type, and with the same model, then k1=2,
k2=1.5, k3=30, k4=1.
Otherwise: k1=2，k2=2，k3=30，k4=1.
4. Example
Kalf=30, Isn=5A, Rct=1Ω, Sbn=60VA
Ipcf1=40000A, RL=0.5Ω, Rr=0.1Ω, Rc=0.1Ω, Ipn=2000A, Ipnt=1500A
Esl = kalf×Isn×(Rct+Rbn) = kalf×Isn×(Rct+ Sbn/Isn2)
= 30×5×(1+60/25)=510V
Esl1′ = k1×Ipcf1×Isn×(Rct+Rb)/Ipn
= 2×Ipcf1 ×Isn×(Rct+(Rr+2×RL))/Ipn
= 2×40000×5×(1+(0.1+2×0.5))/2000=420V
8
Esl3′ = k3×Ipnt×Isn×(Rct+Rb)/Ipn
=30×1500*5*(1+(0.1+2×0.5)) /2000=236.25V
Thus, Esl > Esl1′ and Esl > Esl3′
8.4 Plug-in Module Description

The device consists of power supply module (PWR), main CPU module (CPU), AI module, BI
module, BO plug-in module and DC analog input plug-in module. Terminal definitions and
application of each plug-in module are introduced as follows.

8 Hardware
8.4.1 Human-machine Interface Module (NR6855/NR6856)

The human machine interface (HMI) module is installed on the front panel of this device. It is used
to observe the running status and event information on the LCD, and configure the protection
settings and device operation mode. It can help the user to know the status of this device and
detailed event information easily, and provide convenient and friendly access interface for the
user.
8.4.2 Power Supply Module (NR6305/NR6310)

The power supply module is a DC/DC converter with electrical insulation between input and
output. It has an input voltage range as described in Chapter 2 Technical Data. The standardized
output voltages are +5Vdc and +12Vdc. The tolerances of the output voltages are continuously
monitored.
The +5Vdc output provides power supply for all the electrical elements that need +5Vdc power
supply in this device.
The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device
is in cold reserve.
Figure 8.4-1 View of power supply module
Three types of power supply modules are provided: NR6305A, NR6305B and NR6310A. The
NR6305B is same as the NR6305A except that the NR6105B can support at least 500ms power

8 Hardware
supply interruption.
8.4.2.1 NR6305A & NR6305B
The power supply module also provides 9 binary inputs, 5 binary outputs and a device failure
binary output. A 26-pin connector is fixed on the power supply module. The terminal definition of
the connector is described as below.
Table 8.4-1 Terminal definition and description of power supply module
Pin No. Symbol Description

01 BI_01+
The No.1 programmable binary input
02 BI_01-
03 BI_02+
04 BI_02-
05 BI_COM The common negative connection of the BI_01 to BI_09
06 BI_03 The No.3 programmable binary input
13
BO_01 The No.1 programmable binary output
14
15
16
17
18
19
20
21
22
23
BO_Fail The device failure signal output
24
25 PWR+ DC power supply positive input 8
26 PWR- DC power supply negative input
Grounded connection of the power supply
8.4.2.2 NR6310A
The power supply module also provides 9 binary inputs, 5 binary outputs and a device failure
binary output. A 22-pin connector and a 4-pin connector are fixed on the power supply module.
The terminal definition of the connector is described as below.

8 Hardware
Table 8.4-2 Terminal definition and description of power supply module

01 BI_01+
02 BI_01-
03 BI_02+
04 BI_02-
05 BI_COM The common negative connection of the BI_01 to BI_09
22-pin
13
14
15
16
17
18
19
20
21
22
23
BO_Fail The device failure signal output
24
4-pin
25 PWR+ DC power supply positive input
26 PWR- DC power supply negative input
Grounded connection of the power supply
8 The standard rated voltage of the PWR module is self-adaptive to

88~300Vdc or 88~275Vac. For a non-standard rated voltage power supply
module please specify when place order, and check if the rated voltage of
power supply module is the same as the voltage of power source before
the device being put into service.
The PWR module a grounding screw for device grounding. The grounding
screw shall be connected to grounding screw and then connected to the
earth copper bar of panel via dedicated grounding wire.
Effective grounding is the most important measure for a device to prevent

8 Hardware
EMI, so effective grounding must be ensured before the device is put into
service.
8.4.3 CPU Module (NR6106)
The CPU module is the central part of this device, and contains a multi-core 32-bit powerful
processor and some necessary electronic elements. This powerful processor performs all of the
functions for this device: protection function, communication function, human-machine interface
function and so on. There are several A/D conversion circuits on this module, which are used to
convert the AC analog signals to corresponding DC signals for fulfilling the demand of the
electrical level standard. A high-accuracy clock chip is contained in this module, it provide
accurate current time for this device.
The main functional details of the CPU module are listed as below:
 Protection calculation and logical judgment function
The CPU module can calculate protective elements (such as overcurrent element) on the
basis of the analog sampled values (voltages and currents) and binary inputs, then it does
logical judgment function and decides whether the device needs to trip or close.
 Communication function
The CPU module can effectively manage all communication procedures, and reliably send
out some useful information through its various communication interfaces. These interfaces
are used to communicate with a SAS or a RTU. It also can communicate with the human
machine interface module. If an event occurs (such as SOE, protective tripping event etc.),
this module will send out the relevant event information through these interfaces, and make it
be easily observed by the user.
 Auxiliary calculation
Based on the voltage and current inputs, the CPU module also can calculate out the metering
values, such as active power, reactive power and power factor etc. All these values can be
sent to a SAS or a RTU through the communication interfaces.
 Human-machine interface function
This module can respond the commands from the keypad of this device and show the results
on the LCD and LED indicators of this device. It also can show the operation situation and 8
event information for the users through the LCD and LED indicators.
 Time synchronization
This module has a local clock chip and an interface to receive time synchronized signals from
external clock source. These signals include PPS (pulse per second) signal and IRIG-B
signal. Basing on the timing message (from SAS or RTU) and the PPS signal, or basing on
the IRIG-B signal, this module can synchronize local clock with the standard clock.
The view of CPU module is shown in the following figure.

8 Hardware
Figure 8.4-2 View of CPU module
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.
The configuration and terminal definition of the CPU modules are listed in following table
Table 8.4-3 Configuration and terminal definition of CPU module
Module ID Memory Interface Terminal No. Usage Physical Layer

8 2 RJ45 Ethernet Ethernet
Twisted pair wire
2 SFP Ethernet communication
01 A
RS-485 02 B To SCADA Twisted pair wire
03 SGND
NR6106BA 1G DDR
04 A
RS-485 05 B To SCADA Twisted pair wire
06 SGND
07 SYN+ To clock
RS-485 Cable
08 SYN- synchronization

8 Hardware
09 SGND
TTL 10 SYN-TTL Cable
The correct connection is shown in Figure 8.4-3. Generally, the shielded cable with two pairs of
twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to connect
the “+” and “–” terminals of difference signal. The other pair of twisted pairs are used to connect
the signal ground of the communication interface. The module reserves a free terminal for all the
communication ports. The free terminal has no connection with any signal of the device, and it is
used to connect the external shields of the cable when connecting multiple devices in series. The
external shield of the cable shall be grounded at one of the ends only.
Twisted pair wire

A 01
B 02
COM
SGND 03
04
Twisted pair wire

SYN+ 01
Clock SYN
SYN- 02
SGND 03
04
Cable
RTS 05
PRINT
TXD 06
SGND 07
Figure 8.4-3 Connection of communication terminal
Figure 8.4-4 Jumpers of printer/RS-485 port
The 2nd RS-485 port also can be configured as a printer port through the

8 Hardware
jumpers “J10” and “J11”.
Jumper RS-485 Printer

J10 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected
J11 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected
8.4.4 AC Analog Input Module (NR6641)
The analog input module is applicable for power plant or substation with conventional VT and CT,
and it can transform high AC input values to relevant low AC output value, which are suited to the
analog inputs of the CPU module. The transformers are used both to step-down the currents and
voltages to levels appropriate to the device’s electronic circuitry and to provide effective isolation
between this device and the power system. A low pass filter circuit is connected to each
transformer (CT or VT) secondary circuit for reducing the noise of each analog AC input signal.
For the analog input module, if the plug is not put in the socket, external CT circuit is closed itself.
Just shown as below.
Plug
Socket
In
Out
plug is not put in the socket
In
8 Out
Put the plug in the socket
Figure 8.4-5 Schematic diagram of CT circuit automatically closed
There are two types of analog input modules. The rated current is adaptive (1A/5A). Please
declare which kind of AI module is needed before ordering. Maximum linear range of the current
converter is 40In.
 6CT+6VT

8 Hardware
 12CT
The terminal definition of the analog input module is shown as below.
NR6641-6I6U NR6641-12I
01 I1 I1n 02 01 I1 I1n 02
03 I2 I2n 04 03 I2 I2n 04
05 I3 I3n 06 05 I3 I3n 06
07 I4 I4n 08 07 I4 I4n 08
09 I5 I5n 10 09 I5 I5n 10
11 I6 I6n 12 11 I6 I6n 12
13 U1 U1n 14 13 I7 I7n 14
15 U2 U2n 16 15 I8 I8n 16
17 U3 U3n 18 17 I9 I9n 18
19 U4 U4n 20 19 I10 I10n 20
21 U5 U5n 22 21 I11 I11n 22
23 U6 U6n 24 23 I12 I12n 24
Figure 8.4-6 Terminal definition of analog input module
NEVER allow the current transformer (CT) secondary circuit connected to

this device to be opened while the primary system is energized. The
opened CT secondary circuit will produce a dangerously high voltage. If
this safety precaution is disregarded, personal death, severe personal
injury or considerable equipment damage will occur.
Each analog input channel can be configured according to practical

application through PCS-Studio.
8.4.4.1 Connection Examples
Some connection examples of the current transformers and voltage transformers which are
supported by this relay are shown in this section. If one of the analog inputs has no input in a
practical engineering, the relevant input terminals should be disconnected. 8
1. Current connections examples

8 Hardware
A B C A B C
Ia Ia
Ian Ian
Ib Ib
Ibn Ibn
Ic Ic
Icn Icn
I01
I01n I01
(1) I01n
A B C (3)
Ia
Ian
Ib I0s
Ibn I0sn
Ic
(4)
Icn
I01 I02
I01n I02n
(2) (5)
Figure 8.4-7 Current connection examples
Where:
(1) Current connections to three current transformers with a star-point connection for ground
current (zero sequence current or residual current).
(2) Current connections to three current transformers with a separate ground current
transformer (summation current transformer or core balance current transformer).
(3) Current connections to two current transformers with a separate ground current
transformer (summation current transformer or core balance current transformer), only
for ungrounded or compensated networks.
(4) Current connection to a core balance neutral current transformer for sensitive ground
8 fault detection, only for ungrounded or compensated networks.
(5) Current connection to a separate ground current transformer (summation current

transformer or core balance current transformer) for the No.2 zero sequence current
input of this relay.
2. Voltage connections examples

8 Hardware
A B C A B C
Ux
52 52 52 Ux 52 52 52
Uxn
Uxn
Ua Ua
Ub Ub
Uc Uc
Un Un
U0 U0
U0n U0n
(1) (2)
Figure 8.4-8 Voltage connection examples
Where:
(1) Voltage connections to three star-connected voltage transformers with open-delta

windings and additionally to any phase voltage (for synchronism check).
(2) Voltage connections to three star-connected voltage transformers with open-delta

windings and additionally to any phase-to-phase voltage (for synchronism check).
8.4.5 Binary Input Module (NR6601/NR6610)

The binary input module contains some optical isolated binary inputs which are used to monitor
the contact positions of the corresponding bay, and all the binary inputs are configurable through
PCS Studio according to practical application.
There are three kinds of BI modules available, NR6601A, NR6610A and NR6610B. The binary
input module can respectively provide 25 or 32 binary inputs, the supported rated voltages of
binary inputs are listed in Section Technical Data.
The rated voltage of binary input is optional: 24Vdc, 30Vdc, 48Vdc, 110Vdc, 8
125Vdc, 220Vdc, 110Vac or 220Vac (@50Hz), which must be specified
when placed order. It is necessary to check whether the rated voltage of
binary input module complies with site DC power supply rating before put
this device in service.
8.4.5.1 NR6601A
Each BI module is with a 26-pin connector for 25 binary inputs which share one common negative
power input and can be configurable. The pickup voltages and dropout voltages of the binary
inputs are settable by the setting [xx.U_Pickup_BI] and [xx.U_Dropoff_BI], and the range is from
50%Un to 80%Un.

8 Hardware
01 BI_01 BI_02 02
03 BI_03 BI_04 04
05 BI_05 BI_06 06
07 BI_07 BI_08 08
09 BI_09 BI_10 10
11 BI_11 BI_12 12
13 BI_13 BI_14 14
15 BI_15 BI_16 16
17 BI_17 BI_18 18
19 BI_19 BI_20 20
21 BI_21 BI_22 22
23 BI_23 BI_24 24
25 BI_25 COM- 26
Figure 8.4-9 View of binary input module (NR6601A)
Table 8.4-4 Terminal definition and description of binary input module

8 07
08
BI_07
BI_08

8 Hardware

26 BI_COM The common negative connection of the BI_01 to BI_25.
8.4.5.2 NR6610A & NR6610B
Each BI module is with two 18-pin connectors for 32 binary inputs. The first 16 binary inputs share
one common negative power input and the last 16 binary inputs share another common negative
power input. All binary inputs are configurable. The pickup voltages and dropout voltages of the
binary inputs are settable by the setting [xx.U_Pickup_BI] and [xx.U_Dropoff_BI], and the range is
from 50%Un to 80%Un. The difference between NR6610A and NR6610B is that NR6610A equips
single AD sampling and NR6610B equips dual AD sampling.
01 BI_01 19 BI_01
02 BI_02 20 BI_02
03 BI_03 21 BI_03
04 BI_04 22 BI_04
05 BI_05 23 BI_05
06 BI_06 24 BI_06
07 BI_07 25 BI_07
08 BI_08 26 BI_08
09 BI_09 27 BI_09
10 BI_10 28 BI_10
11 BI_11 29 BI_11
12 BI_12 30 BI_12
13 BI_13 31 BI_13 8
14 BI_14 32 BI_14
15 BI_15 33 BI_15
16 BI_16 34 BI_16
17 BI_COM 35 BI_COM
18 BI_COM 36 BI_COM
Figure 8.4-10 View of binary input module (NR6610A and NR6610B)

8 Hardware
Table 8.4-5 Terminal definition and description of binary input module

18-pin
17 COM-
The common negative connection of the BI_01 to BI_16.
18 (01-16)
18-pin
8 31
32
BI_29
BI_30
35 COM-
The common negative connection of the BI_17 to BI_32.
36 (17-32)
8.4.6 Binary Output Module (NR6651/NR6652/NR6660)
The binary output module consists of some necessary contact outputs, and the binary outputs are
used as tripping and closing (protection, auto-reclosing or remote control) outputs or signal

8 Hardware
outputs. It can receive tripping commands or closing commands from the CPU module, and then
executes these commands. It also can output some alarm signals from the CPU module.
The device can provide four types of binary output modules: NR6651A, NR6651B, NR6652A and
NR6660A.
8.4.6.1 NR6651A
The NR6651A provides 13 normally open contacts (NOC) with pickup relay control.
A 26-pin connector is fixed on the binary output module.
The terminal definition of the connector is shown in Figure 8.4-11.
BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
BO_13 25 26
Figure 8.4-11 View of binary output module (NR6651A)
8.4.6.2 NR6651B
8
The NR6651B provides 11 normally open contacts (NOC, the first 11 contacts) and 2 normally
close contacts (NCC, the last 2 contacts). These binary outputs are controlled by pickup relay.

8 Hardware
BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
BO_13 25 26
Figure 8.4-12 View of binary output module (NR6651B)
8.4.6.3 NR6652A
The NR6652A provides 4 normally open contacts (NOC, the first 4 contacts) with heavy capacity
for controlling the circuit breaker directly, and provides 4 general normal open contacts (NOC, the
last 4 contacts). These binary outputs are controlled by pickup relay.

8 Hardware
BO_01 01 02
03 04
BO_02 05 06
07 08
BO_03 09 10
11 12
BO_04 13 14
15 16
17 18
BO_05 19 20
BO_06 21 22
BO_07 23 24
BO_08 25 26
8.4.6.4 NR6660A
The NR6660A provides 15 normally open contacts (NOC) and 2 normally open contacts &
normally close contacts (NOC/NCC). These binary outputs are controlled by pickup relay.
Two 18-pin connectors are fixed on the binary input module.

8 Hardware
BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
18-pin
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
BO_13 25 26
BO_14 27 28
18-pin
BO_15 29 30
BO_16 32
31
BO_16 33
BO_17 35
34
BO_17 36
Each binary output can be set as a specified tripping output contact or a

signal output contact through PCS-Studio according to practical
application.
8.4.7 DC Analog Input Module (NR6630/NR6631)
The DC analog input module can provide 0~±20mA or 0~±10V input channels. Certain type can
also provide RTD sensor input channels.
8 This device provides three types of DC analog input modules: NR6630A, NR6631A and
NR6631B.
8.4.7.1 NR6630A
The NR6630A provides 12 channels of 0~±20mA or 0~±10V inputs, and all channels can be set
as 0~±20mA or 0~±10V DC signal inputs respectively through the jumpers on the module and the
related channel type setting.
Module ID Jumper 0~±20mA 0~±10V

NR6630A J1~J12 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected

8 Hardware
Figure 8.4-15 View of DC analog input module NR6630A
Two 18-pin connectors are fixed on this DC analog input module. The terminal definition of the
connector on the module NR6630A is listed as below.
Table 8.4-6 Terminal definition and description of DC analog input module NR6630A

01 DCAI_01+
The No.1 DC analog input channel
02 DCAI_01-
03 GND The grounding terminal
04 DCAI_02+
05 DCAI_02-
06
07
GND
DCAI_03+
The grounding terminal
8
08 DCAI_03-
10 DCAI_04+
11 DCAI_04-
13 DCAI_05+
14 DCAI_05-

8 Hardware
16 DCAI_06+
17 DCAI_06-
19 DCAI_07+
20 DCAI_07-
22 DCAI_08+
23 DCAI_08-
25 DCAI_09+
26 DCAI_09-
28 DCAI_10+
29 DCAI_10-
31 DCAI_11+
32 DCAI_11-
34 DCAI_12+
35 DCAI_12-
8.4.7.2 NR6631
The NR6631A provides 8 channels of 0~±20mA or 0~±10V inputs, and all channels can be set as
0~±20mA or 0~±10V DC signal inputs respectively through the jumpers on the module and the
related channel type setting.
The NR6631B provides 6 channels of 0~±20mA or 0~±10V inputs, and all channels can be set as
0~±20mA or 0~±10V DC signal inputs respectively through the jumpers on the module and the
related channel type setting. It also can support 3 channels of RTD sensor inputs.
Module ID Jumper 0~±20mA 0~±10V

NR6631A J1~J8 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected
8 NR6631B J1~J6 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected

8 Hardware
Figure 8.4-16 View of DC analog input module NR6631
A 26-pin connector is fixed on this DC analog input module.
The terminal definition of the connector of the module NR6631A is listed as below.
Table 8.4-7 Terminal definition and description of DC analog input module NR6631A

37 DCAI_01+
38 DCAI_01-
40 DCAI_02+
41 DCAI_02-
42 DCAI_03+
8
43 DCAI_03-
45 DCAI_04+
46 DCAI_04-
47 DCAI_05+
48 DCAI_05-
50 DCAI_06+
51 DCAI_06-

8 Hardware

52 DCAI_07+
53 DCAI_07-
55 DCAI_08+
56 DCAI_08-
57 Empty
58 Empty
59 Empty
60 Empty
61 Empty
62 Empty
The terminal definition of the connector of the module NR6631B is listed as below.
Table 8.4-8 Terminal definition and description of DC analog input module NR6631B

01 DCAI_01+
02 DCAI_01-
04 DCAI_02+
05 DCAI_02-
06 DCAI_03+
07 DCAI_03-
09 DCAI_04+
10 DCAI_04-
11 DCAI_05+
12 DCAI_05-
14 DCAI_06+
15 DCAI_06-
16
8 17
18
RTD1_A
GND
The No.1 RTD sensor input channel
The grounding terminal
19 RTD1_B
The No.1 RTD sensor input channel
20 RTD1_C
21 RTD2_A
22 RTD2_B The No.2 RTD sensor input channel
23 RTD2_C
24 RTD3_A
25 RTD3_B The No.3 RTD sensor input channel
26 RTD3_C

8 Hardware
The wring method of the RTD sensor to this module is shown as below.
RTDx_A RTDx_A
RTDx_B RTDx_B
RTDx_C RTDx_C
3-wire 2-wire
Figure 8.4-17 Wiring method of the RTD sensor
If a 2-wire RTD sensor is adopted, the terminal “RTDx_B” and “RTDx_C”

must be shorten together.
The terminal “RTDx_B” and “RTDx_C” must be shorten together if a RTD

input channel is not applied.

9 Settings
9 Settings
Table of Contents
9.1 Global Settings ................................................................................................ 9-1

9.1.1 System Settings.................................................................................................................... 9-1
9.1.2 Device Settings..................................................................................................................... 9-5
9.1.3 Communication Settings ...................................................................................................... 9-6
9.1.4 Disturbance Fault Recording Settings ............................................................................... 9-19
9.1.5 Label Settings ..................................................................................................................... 9-20
9.1.6 Clock Synchronization Settings .......................................................................................... 9-20
9.1.7 Supervision Settings ........................................................................................................... 9-23
9.1.8 OutMap Settings ................................................................................................................. 9-23
9.2 Protection Settings ........................................................................................ 9-24

9.2.1 Transformer Current Differential Protection Settings (87T) ............................................... 9-24
9.2.2 Restricted Earth Fault Protection Settings (64REF) .......................................................... 9-25
9.2.3 Winding Differential Protection (87W) ................................................................................ 9-26
9.2.4 Overexcitation Protection (24) ............................................................................................ 9-26
9.2.5 Phase Overcurrent Protection (50/51P, 67P) ..................................................................... 9-28
9.2.6 Earth Fault Overcurrent Protection (50/51G, 67G) ............................................................ 9-32
9.2.7 Negative-sequence Overcurrent Protection (50/51Q, 67Q) .............................................. 9-35
9.2.8 Thermal Overload Protection (49) ...................................................................................... 9-39
9.2.9 Breaker Failure Protection (50BF) ..................................................................................... 9-39

9
9.2.10 Phase Overvoltage Protection (59P) ............................................................................... 9-40
9.2.11 Residual Overvoltage Protection (59G) ........................................................................... 9-42
9.2.12 Phase Undervoltage Protection (27P) ............................................................................. 9-43
9.2.13 Overfrequency Protection (81O) ...................................................................................... 9-45
9.2.14 Underfrequency Protection (81U) .................................................................................... 9-46
9.3 Measurement and Control Settings ............................................................. 9-46

9.3.1 Function Settings ................................................................................................................ 9-46

9 Settings
9.3.2 Synchronism Check Settings ............................................................................................. 9-47
9.3.3 Double Point Status Settings ............................................................................................. 9-48
9.3.4 Control Settings .................................................................................................................. 9-49
9.3.5 Tap Changer Indicator Settings .......................................................................................... 9-49
9.3.6 Interlocking Logic Settings ................................................................................................. 9-50
9.3.7 DC Measuring Transducers Settings ................................................................................. 9-50
9.4 Logic Links ..................................................................................................... 9-51

9.4.1 Function Links .................................................................................................................... 9-51
9.4.2 GOOSE Sending Links....................................................................................................... 9-51
9.4.3 GOOSE Receiving Links .................................................................................................... 9-51
List of Tables
Table 9.1-1 Matrix of phase compensation ............................................................................. 9-3

9 Settings
9.1 Global Settings
9.1.1 System Settings

Access path: MainMenu  Settings  Global Settings  System Settings
No. Settings Range Unit Default Remark

The number of active setting group,
several setting groups can be
1 Active_Grp 1~30 - 1
configured for protection settings, and
only one is active at a time.
2 Opt_SysFreq 50.0, 60.0 Hz 50.0 The system frequency.
Name of the protected primary
Max 20
3 PrimaryEquip_Name - - equipment, such as busbar,
characters
transformer, etc.
4 Sn 0.100~5000.000 MVA 500 Transformer capacity
Primary rated voltage at HV side of
5 HVS.U1n_Plate 0.000~9999.000 kV 220
transformer stated on nameplate
Primary rated voltage at MV side of
6 MVS.U1n_Plate 0.000~9999.000 kV 110
Primary rated voltage at LV side of
7 LVS.U1n_Plate 0.000~9999.000 kV 35
Wiring o′clock of MV side with respect
8 Clk_MVS_WRT_HVS 0~11 Clk 0
to HV side
Wiring o′clock of LV side with respect
9 Clk_LVS_WRT_HVS 0~11 Clk 11
to HV side
The target o′clock that each side
10 Clk_PhComp 0~11 Clk 0 current will be shift to for phase
compensation
Logic setting of enabling/disabling
Enabled, zero-sequence current elimination for
11 HVS.En_I0Elim - Enabled
Disabled phase compensation of HV side of
transformer.
12 MVS.En_I0Elim
Enabled,
- Enabled
zero-sequence current elimination for 9
Disabled phase compensation of MV side of
transformer.
Enabled, zero-sequence current elimination for
13 LVS.En_I0Elim - Enabled
Disabled phase compensation of LV side of
transformer.
Primary voltage value of VT at x side
14 x.U1n 0.000~1100.000 kV -
of transformer
15 x.U2n 1.000~200.000 V - Secondary voltage value of VT at x

9 Settings

side of transformer
Primary rated voltage of broken-delta
16 x.Neu.U1n 0.000~1100.000 kV -
VT at x side of transformer
Secondary rated voltage of
17 x.Neu.U2n 1.000~200.000 V - broken-delta VT at x side of
transformer
Primary voltage values of VT of
18 25.Ref.U1n 1.00~1000.00 kV 110.00
reference side of synchronism check
Secondary voltage values of VT of
19 25.Ref.U2n 1.00~120.00 V 100.00
reference side of synchronism check
Primary voltage values of VT of
20 25.Syn.U1n 1.00~1000.00 kV 110.00 synchronism side of synchronism
check
Secondary voltage values of VT of
21 25.Syn.U2n 1.00~120.00 V 100.00 synchronism side of synchronism
check
Primary rated current of CT at x side
22 x.I1n 0~9999 A 1000
of transformer
Secondary rated current of CT at x
23 x.I2n 1 or 5 A 1
side of transformer
Primary rated current of neutral CT at
24 x.Neu.I1n 0~9999 A 1000
x side of transformer
Secondary rated current of neutral CT
25 x.Neu.I2n 1 or 5 A 1
at x side of transformer
Enabled,
26 x.En_VT - Enabled Logic setting to put VT into service
Disabled
Enabled, Logic setting of enabling/disabling the
27 x.En_RevCT - Disabled
Disabled current polarity of CT reversed
Logic setting of enabling/disabling the
Enabled,
28 x.Neu.En_RevCT - Disabled current polarity of neutral CT CT
Disabled
reversed
29 Opt_PhSeq ABC, ACB - ABC Option of phase sequence
9 1. [x.U1n_Plate]
They are primary rated voltage at x side of transformer or reactor stated on nameplate
The setting principle of rated phase-to-phase voltages of each side is to take the primary rated
voltage marked on the nameplate of transformer as the primary rated voltage of corresponding
side. For an on-load tap changing transformer, the voltage of transformer with tap in middle
position can be taken as the value of this setting. As to other kind of transformers, actual operation
voltage (i.e. phase-to-phase voltage) shall be taken as this setting value, otherwise the calculation
of correction coefficient may be wrong
For example, if the voltage at 220kV side is 230kV for an on-load tap changing transformer with

9 Settings
tap in its middle position, and then the setting is set as 230kV.
For one side not used in the device, please set the primary rated voltage
value of the corresponding side as “0”.
2. [Clk_MVS_WRT_HVS], [Clk_LVS_WRT_HVS]
They are the wiring o′clock of MV/LV side with respect to HV side, is the parameter shown on
transformer nameplate with the range of 0~11, and need not further calculation.
3. [Clk_PhComp]
It is the target o′clock each side current will be shift to for phase compensation.
For examples:
The vector group of a transformer is Y0/Δ11 and the target o′clock ([Clk_PhComp]) is set to “11”.
Therefore, the setting [Clk_LVS_WRT_HVS] should be set to “11”.
1. For HV side, the clock of HV side with reference to target o′clock is 1 (i.e. wiring o′clock
12-target o′clock 11) clock, so the matrix of relative o′clock 1 is adopted to compensate HV
side current. Zero-sequence current elimination has no effect on phase compensation in the
condition.
2. For LV side, the clock of LV side with reference to target o′clock is 0 (i.e. wiring o′clock 11-
target o′clock 11), so the matrix of relative o′clock 0 is adopted to compensate LV side current.
Then it is needed to decide whether zero-sequence current is eliminated and select the
corresponding matrix.
If an earthing transformer is connected at LV side out the protection zone of differential protection,
then matrix of relative o′clock 0 without zero-sequence current elimination can be selected.
If an earthing transformer is connected at LV side in the protection zone of differential protection,

then zero-sequence current must be eliminated and otherwise differential protection may operate
unexpectedly during an external fault. Therefore the matrix of relative o′clock 0 with
zero-sequence current elimination should be selected.
Table 9.1-1 Matrix of phase compensation

9
Matrix (without zero-sequence current Matrix (with zero-sequence current
Relative o'clock
elimination) elimination)
 1 0 0  2  1  1
1 
0
0 1 0 
    1 2  1
3
0 0 1  1  1 2

9 Settings

Relative o'clock
 1  1 0
1 
1   0 1  1
3
 1 0 1
 0  1 0  1  2 1
2
 0 0 1  1 
  1 1  2
  3
 1 0 0  2 1 1
 0  1 1
1 
3   1 0  1
3
 1 1 0
0 0 1  1  1 2
1 
4
 1 0 0
    2  1  1
3
0 1 0  1 2  1
 1 0 1
1 
5   1  1 0
3
 0 1  1
 1 0 0  2 1 1
6
 0  1 0 1 
  1  2 1
  3
 0 0  1  1 1  2
  1 1 0
1 
7   0  1 1
3
 1 0  1
 0 1 0  1 2  1 
8
0 0 1
1 
  1  1 2 
 3
 1 0 0  2  1  1
9
 0 1  1
1 
9   1 0 1
3
 1  1 0
 0 0  1  1 1  2
10
 1 0 0
1 
  2 1 1
 3
 0  1 0  1  2 1

9 Settings

Relative o'clock
 1 0  1
1 
11   1 1 0
3
 0  1 1
4. [x.En_RevCT]
It is used to adjust the current polarity of CT at x side of transformer, and default value is 0.
Disabled: keep connected current polarity unchanged
Enabled: make connected current polarity reversed
When the current polarity of primary CT is different with defined forward direction by PCS-978S,
the setting can be set as “Enabled”. However, it is recommended to change external wiring of
primary CT.
9.1.2 Device Settings

Access path: MainMenu  Settings  Global Settings  Device Settings

Enabling/disabling the debugging
Disabled port. Used for debugging tool
1 En_DebugPort - Enabled
Enabled connection, program download,
variable debugging, etc.
Disabled
2 En_TelnetPort - Enabled Enabling/disabling the Telnet port.
Enabled
Disabled Enabling/disabling connect to the
3 En_VirtualLCDPort - Enabled
Enabled device via the software Teldevice
Disabled Enabling/disabling print data to the
4 En_NetPrintPort - Enabled
Enabled software Netpts
5 Ctrl_Password 000~999 - 111 The control password via local LCD
Disabled Override control password via local
6 En_NoCtrlPwd - Disabled
Enabled LCD
DC
Power supply mode of binary input
9
7 Opt_Pwr_BI AC50Hz - DC
module
AC60Hz
This setting is used to set voltage level
8 B**.Un_BinaryInput 24~250 V 220
of binary input module slot B**
This setting is used to set voltage level
9 PWR.Un_BinaryInput 24~250 V 220
of binary input of PWR module
This setting is used to set pickup
10 U_Pickup_BI 50.0 ~80.0 % 63
voltage of binary input module.
11 U_Dropoff_BI 50.0~80.0 % 55 This setting is used to set dropoff

9 Settings

voltage of binary input module.
The logic setting to enable/disable the
Disabled
12 En_Jitter_Blk - Disabled jitter processing function in case of
Enabled
binary input voltage variation
Monitoring window of binary input jitter
13 Mon_Window_Jitter 0.000~500.000 s 1
processing
Times threshold to block binary input
14 Num_Blk_Jitter 2~500000 - 10
status change due to jitter
Blocking window of binary input status
15 Blk_Window_Jitter 0~500.000 s 1
change due to jitter
Times threshold to initiate immediately
another blocking window of binary
16 Num_Reblk_Jitter 1~500000 - 10
input status change due to continuous
jitter
9.1.3 Communication Settings

9.1.3.1 General Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  General Comm
Settings

0.0.0.0~ IP address of Ethernet port
1 IP_LAN1 - 198.120.0.100
255.255.255.255 A
0.0.0.0~ Subnet mask of Ethernet
2 Mask_LAN1 - 255.255.0.0
255.255.255.255 port A
3 IP_LAN2 - 198.121.0.100
255.255.255.255 B
4 Mask_LAN2 - 255.255.0.0
255.255.255.255 port B
5 IP_LAN3 - 198.122.0.100
255.255.255.255 C
9 6 Mask_LAN3
255.255.255.255
- 255.255.0.0
port C
7 IP_LAN4 - 198.123.0.100
255.255.255.255 D
8 Mask_LAN4 - 255.255.0.0
255.255.255.255 port D
Disabled Put Ethernet port B into
9 En_LAN2 - Enabled
Enabled service
Disabled Put Ethernet port C into
10 En_LAN3 - Disabled
Enabled service
11 En_LAN4 Disabled - Disabled Put Ethernet port D into

9 Settings

Enabled service
Normal
1-2:Normal, 3-4:HSR The network method of the
12 B01.Opt_NetMode 1-2:Normal, 3-4:PRP - Normal CPU module located in slot
1-2:Normal, 3-4:RSTP No.1
1-2:PRP, 3-4:HSR
4800
9600
19200
13 Baud_Printer bps 19200 Baud rate of printer port
38400
57600
115200
Disabled Enable/disable automatic
14 En_AutoPrint - Disabled
Enabled printing function
Communication protocol of
rear RS-485 serial port 1.
IEC103
15 Protocol_RS485-1 - IEC103 IEC103: IEC60870-5-103
Modbus
protocol
Modbus: Modbus protocol
Communication protocol of
rear RS-485 serial port 2.
IEC103
16 Protocol_RS485-2 - IEC103 IEC103: IEC60870-5-103
Modbus
protocol
Modbus: Modbus protocol
4800
9600
19200 Baud rate of rear RS-485
17 Baud_RS485-1 bps 19200
38400 serial port 1.
57600
115200
4800
9600
18 Baud_RS485-2
19200
38400
bps 19200
Baud rate of rear RS-485
serial port 2.
9
57600
115200
Communication address
between the device and
19 Addr_RS485-1 0~255 - 100
the SCADA or RTU via
RS-485 serial port 1.
Communication address
20 Addr_RS485-2 0~255 - 100 between the device and
the SCADA or RTU via

9 Settings

RS-485 serial port 2.
0.0.0.0~ IP address of the gateway
21 Gateway - 0.0.0.0
255.255.255.255 (router)
The setting is used to set
the Ethernet ports that are
22 Cfg_NetPorts_Bond 0~255 - 0
used as hot standby each
other.
1. [Cfg_NetPorts_Bond]
The setting is used to configure dual-networks switching, and it means that no dual-networks
switching is created when the setting is set as “0”. The device support a bond between any two
Ethernet ports, and the bond among three or above Ethernet ports is impermissible.
The devices communicate with SAS by station level network. In order to ensure reliable
communication, dual networks (i.e., network 1 and network 2) are adopted. Another special
communication mode based on dual networks is that Ethernet port 1 and Ethernet port 2 of the
device own the same IP address and MAC address, and network 1 and network 2 are used as hot
standby each other. When both network 1 and network 2 are normal, any of them is used to
communicate between the device and SAS. The device will automatically switch to the other
healthy network when one network is abnormal, which will not affect normal communication.
Taking a CPU module with four Ethernet ports as an example, each bit is corresponding with an
Ethernet port, i.e., Bit0, Bit1, Bit2 and Bit3 are corresponding with Ethernet port 1, Ethernet port 2,
Ethernet port 3 and Ethernet port 4 respectively. If a bond between Ethernet port 1 and Ethernet 2
is created, the setting [Cfg_NetPorts_Bond] is set as “3”. The specific setting is as below.
Bonding Bonding Bonding
Ethernet port 1 Ethernet port 2 Ethernet port 1 Ethernet port 3 Ethernet port 1 Ethernet port 4
Setting Setting Setting

Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0
Value Value Value
0 0 1 1 3 0 1 0 1 5 1 0 0 1 9
9 Bonding Bonding Bonding
Ethernet port 2 Ethernet port 3 Ethernet port 2 Ethernet port 4 Ethernet port 3 Ethernet port 4
Setting Setting Setting

Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0
Value Value Value
0 1 1 0 6 1 0 1 0 10 1 1 0 0 12
Ethernet port 1: Bit0, Ethernet port 2: Bit1, Ethernet port 3: Bit2, Ethernet port 4: Bit3

9 Settings
The switching logic is as below.
 After the device is powered on, network 1 is selected when the link status of both network 1
and network 2 are normal.
 When the link status of network 1 is abnormal, network 2 is selected if network 2 is normal.
 When the link status of network 1 is abnormal, network 1 is kept to work if network 2 is also
abnormal.
 When network 2 is working, network 2 is kept to work even if network 1 has been restored to
normal. The device will be switched to network 1 only if network 2 is abnormal.
9.1.3.2 IEC61850 Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  IEC61850

Settings

It is used to set the change detection
threshold for suddenly sending
1 Threshold_Measmt_Net 0.00~100.00 % 1 measurement value to the SCADA
via the device's Ethernet port using
IEC 60870-5-103
Measurement values zero drift
2 ThAbs_Measmt 0.001~0.500 - 0.02
suppression threshold
If users need to support the quality
Disabled change upload function, this
3 En_Send_MMS_Qual_Chg - Disabled
Enabled parameter should be set as
“Enabled”
It is used to select the network mode
of MMS network for the
communication with SCADA
SingleNet
SingleNet: Single network
4 Opt_DualNetMode_MMS HotStdby - SingleNet
HotStdby: Hot standby mode (always
ColdStdby
two ports in service)
ColdStdby: Cold standby mode (only
one port in service) 9
Disabled The logic setting to enable/disable
5 En_IEC62351_TCP_Port - Disabled
Enabled TCP port in IEC62351 protocol
Disabled The logic setting to enable/disable
6 En_IEC61850_TCP_Port - Enabled
Enabled TCP port in IEC61850 protocol
9.1.3.3 DNP Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  DNP Settings

1 En_TCP1_DNP Disabled - Disabled The logic setting to

9 Settings

Enabled enable/disable the
No.1 network DNP
client
The local address of
2 Addr_Slave_TCP1_DNP 0~65519 - 2 the No.1 network DNP
client
The master address of
3 Addr_Master_TCP1_DNP 0~65519 - 1 the No.1 network DNP
client
The IP address of the
0.0.0.0~
4 IP_Master_TCP1_DNP - 0.0.0.0 master of the No.1
255.255.255.255
network DNP client
The communication
5 Opt_Map_TCP1_DNP 0~4 - 0 map of the No.1
network DNP client
The timeout of the
application layer of the
6 t_AppLayer_TCP1_DNP 1~5 s 3
No.1 network DNP
client
The heartbeat time
7 t_KeepAlive_TCP1_DNP 0~7200 s 120 interval of the No.1
network DNP client
The logic setting to
enable/disable the
Disabled
8 En_UR_TCP1_DNP - Disabled unsolicited message
Enabled
function of the No.1
network DNP client
The online
retransmission number
for sending the
9 Num_URRetry_TCP1_DNP 2~10 - 3
unsolicited message of
the No.1 network DNP
9 client
The offline
retransmission interval
for sending the
10 t_UROfflRetry_TCP1_DNP 1~5000 s 60
client
The default class level
of the “Binary Input” of
11 Class_BI_TCP1_DNP 0~3 - 1
client

9 Settings

of the “Analog Input” of
12 Class_AI_TCP1_DNP 0~3 - 2
client
The selection timeout
of the remote control
13 t_Select_TCP1_DNP 0~240 s 30 and remote adjustment
of No.1 network DNP
client
The time interval of the
time synchronization
14 t_TimeSynIntvl_TCP1_DNP 0~3600 s 180
network DNP client
The “OBJ1” default
1-BISingleBit
15 Obj01DefltVar_TCP1_DNP - 1-BISingleBit variation of the No.1
2-BIWithStatus
network DNP client
1-BIChWoutT The “OBJ2” default
16 Obj02DefltVar_TCP1_DNP 2-BIChWithAbsTime - 2-BIChWithAbsTime variation of the No.1
3-BIChWithRelTime network DNP client
1-AI32Int
2-AI16Int The “OBJ30” default
17 Obj30DefltVar_TCP1_DNP 3-AI32IntWoutF - 3-AI32IntWoutF variation of the No.1
4-AI16IntWoutF network DNP client
5-AI32Flt
1-AI32IntEvWoutT The “OBJ32” default
18 Obj32DefltVar_TCP1_DNP 2-AI16IntEvWoutT - 1-AI32IntEvWoutT variation of the No.1
5-AI32FltEvWoutT network DNP client
1-AO32Int The “OBJ40” default
19 Obj40DefltVar_TCP1_DNP 2-AO16Int - 1-AO32Int variation of the No.1
3-AO32Flt network DNP client
Disabled enable/disable the
20 En_TCP2_DNP - Disabled
Enabled No.2
client
network DNP
9
client
client
0.0.0.0~
255.255.255.255
network DNP client

9 Settings

The communication
network DNP client
The timeout of the
No.2 network DNP
client
The heartbeat time
network DNP client
enable/disable the
Disabled
Enabled
network DNP client
The online
for sending the
client
The offline
for sending the
client
client
9 31 Class_AI_TCP2_DNP 0~3 - 2
client
of No.2 network DNP
client
33 t_TimeSynIntvl_TCP2_DNP 0~3600 s 180 time synchronization

9 Settings

network DNP client
1-BISingleBit
2-BIWithStatus
network DNP client
1-AI32Int
5-AI32Flt
Enabled No.3 network DNP
client
client
client
0.0.0.0~
255.255.255.255
network DNP client
The communication
43 Opt_Map_TCP3_DNP 0~4 - 0 map of the No.3 9
network DNP client
The timeout of the
No.3 network DNP
client
The heartbeat time
network DNP client
Disabled The logic setting to
46 En_UR_TCP3_DNP - Disabled
Enabled enable/disable the

9 Settings

unsolicited message
network DNP client
The online
for sending the
client
The offline
for sending the
client
client
client
of No.3 network DNP
client
network DNP client
9 53 Obj01DefltVar_TCP3_DNP
1-BISingleBit
- 1-BISingleBit variation of the No.3
2-BIWithStatus
network DNP client
1-AI32Int
5-AI32Flt

9 Settings

Enabled No.4 network DNP
client
client
client
0.0.0.0~
255.255.255.255
network DNP client
The communication
network DNP client
The timeout of the
No.4 network DNP
client
The heartbeat time
network DNP client
enable/disable the
Disabled
Enabled
network DNP client
9
The online
for sending the
client
The offline
67 t_UROfflRetry_TCP4_DNP 1~5000 s 60 retransmission interval
for sending the

9 Settings

client
client
client
of No.4 network DNP
client
network DNP client
1-BISingleBit
2-BIWithStatus
network DNP client
1-AI32Int
5-AI32Flt
9 75 Obj32DefltVar_TCP4_DNP 2-AI16IntEvWoutT
5-AI32FltEvWoutT
- 1-AI32IntEvWoutT variation of the No.4
network DNP client
9.1.3.4 IEC103 Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  IEC103 Settings

1 Opt_Caption_103 Current_Language - Current_Language The language of group

9 Settings

Fixed_Chinese caption of IEC103
Fixed_English protocol
It is recommended to be
set as “Fixed_Chinese”
if the device
communicate with
SCADA in Chinese.
This setting is only used
for IEC 103 protocol. If
NR network IEC103
protocol is used, the
setting must be set as
“Enabled”.
Disabled
2 En_Broadcast_LAN1 - Disabled Disabled: the device
Enabled
does not send UDP
messages through
Ethernet port A
Enabled: the device
sends UDP messages
through Ethernet port A
NR network IEC103
Disabled “Enabled”.
3 En_Broadcast_LAN2 - Disabled
Enabled 0: the device does not
send UDP messages
through Ethernet port B
1: the device sends UDP
messages through
Ethernet port B
9
NR network IEC103
Disabled
4 En_Broadcast_LAN3 - Disabled “Enabled”.
Enabled
Disabled: the device
does not send UDP
messages through
Ethernet port C
Enabled: the device

9 Settings

sends UDP messages
through Ethernet port C
NR network IEC103
“Enabled”.
Disabled
5 En_Broadcast_LAN4 - Disabled Disabled: the device
Enabled
does not send UDP
messages through
Ethernet port D
Enabled: the device
sends UDP messages
through Ethernet port D
This setting is used to
set the data format for
sending waveform list
using IEC 60870-5-103.
DisturbData
6 Format_Wave_Sent - File DisturbData: Send the
File
waveform list in
ASDU23 mode
File: Send the waveform
list in ASDU222 mode
It is used to set the
change detection
threshold for suddenly
sending measurement
7 Threshold_Measmt_Net 0.00~100.00 % 1.00
value to the SCADA via
the device's Ethernet
port using IEC
60870-5-103
It is used to set the time
9 period for sending the
measurement value to
8 Period_Measmt_Net 0~65535 s 30 SCADA via the device's
Ethernet port using IEC
60870-5-103 or IEC
61850.
9.1.3.5 GOOSE Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  GOOSE Settings

9 Settings

Disabled Enabling/disabling
1 En_NetA_GOOSE - Enabled
Enabled GOOSE network A
Enabling/disabling dual
GOOSE networks
Disabled
2 En_DualNet_GOOSE - Disabled (including GOOSE
Enabled
network A and GOOSE
network B).
Enabling/disabling
complex GOOSE
network modes, and
GOOSE receiving can
be fulfilled via both
GOOSE network A and
GOOSE network B or
only GOOSE network A.
When the setting is
enabled, the device can
discriminate between
single network and dual
Disabled
3 En_ComplexNet_GOOSE - Disabled network according to the
Enabled
value of “fiberno” (1:
single network, 2: dual
networks, others:
configuration error) in
configuration file
“goose.txt” for GOOSE
receiving via both
GOOSE network A and
GOOSE network B, and
the value is invalid for
GOOSE receiving via
only GOOSE network A.
The option of GOOSE
receiving mode.
9
DoubleFrameChk:
DoubleFrameChk
4 Opt_RecvMode_GOOSE - SingleFrameChk double frame check
SingleFrameChk
mode;
SingleFrameChk: single
frame check mode;
9.1.4 Disturbance Fault Recording Settings

Access path: MainMenu  Settings  Global Settings  DFR Settings

9 Settings

Waveform recorded duration before
1 RecDur_PreTrigDFR 0.000~1.000 s 0.100
the trigger element operating
Waveform recorded duration after the
2 RecDur_PostFault 0.000~10.000 s 1.000
fault happens
The maximum waveform recorded
3 MaxRecDur_PostTrigDFR 0.000~10.000 s 1.000 duration after the trigger element
operating
9.1.5 Label Settings

Access path: MainMenu  Settings  Global Settings  Label Settings
No. Setting Range Unit Default Remark

The description name of GOOSE
link。 It will affect the displayed
1 SLOT.Name_**_GCommLink - - GOOSE_Link**
GOOSE link name in "GOOSE
Superv" and other signals.
These settings are used to definite the label of each bay and busbar. They can be set by 6
characters at most. The label of each bay and busbar will influence the displayed contents of all
reports, settings and metering that related with each bay and busbar.
9.1.6 Clock Synchronization Settings

Access path: MainMenu  Settings  Global Settings  ClockSyn Settings

Conventional Select the time
1 Opt_TimeSyn SAS - NoTimeSyn synchronization mode of
NoTimeSyn the device.
The local time zone also
2 OffsetHour_UTC -12~12 - 8 refered to as the hour
offset hour from UTC
The offset minute of local
3 OffsetMinute_UTC 0~60 - 0
time from UTC
9 0.0.0.0~
server when SNTP time
4 IP_Server_SNTP - 0.0.0.0
255.255.255.255 synchronization mode is
selected
The subnet mask of the
0.0.0.0~ server when SNTP time
5 Mask_Server_SNTP - 0.0.0.0
255.255.255.255 synchronization mode is
selected
0.0.0.0~
6 IP_StandbyServer_SNTP - 0.0.0.0 standby server when
255.255.255.255
SNTP time

9 Settings

synchronization mode is
selected
The logic setting is used
Enabled to enable or disable
7 DST.En - Disabled
Disabled Daylight Saving Time
(DST)
It is used to set the
minute offset of DST, i.e.
8 DST.OffsetMinute 0~255 - 60
the difference between
DST time and local time
Jan
Feb
Mar
Apr
May
Jun It is used to set the start
9 DST.MonthInYear_Start - Mar
Jul month of DST.
Aug
Sep
Oct
Nov
Dec
1st
2nd
It is used to set the start
10 DST.WeekInMonth_Start 3nd - 1st
week of DST.
4th
Last
Sunday
Monday
Tuesday,
11 DST.DayInWeek_Start Wednesday - Sunday
day of DST.
Thursday
Friday
Saturday
9
12 DST.HourInDay_Start 0~23 - 3
hour of DST.
Jan
Feb
Mar
It is used to set the end
13 DST.MonthInYear_End Apr - Oct
month of DST.
May
Jun
Jul

9 Settings

Aug
Sep
Oct
Nov
Dec
1st
2nd
14 DST.WeekInMonth_End 3nd - 1st
week of DST.
4th
Last
Sunday
Monday
Tuesday
15 DST.DayInWeek_End Wednesday - Sunday
day of DST.
Thursday
Friday
Saturday
16 DST.HourInDay_End 0~23 - 9
hour of DST.
1. [Opt_TimeSyn]
There are three selections for clock synchronization of the device, each selection includes
different time clock synchronization signals shown in following table.
Item Description
IRIG-B (RS-485): IRIG-B via RS-485 differential level.
PPS (RS-485): Pulse per second (PPS) via RS-485 differential level.
IRIG-B (Fiber): IRIG-B via optical-fibre interface.
Conventional PPS (Fiber): Pulse per second (PPS) via optical-fibre interface.
IEEE1588 (Fiber): Clock message via IEEE1588.
PPM (DIN): Pulse per minute (PPM) via the binary input [BI_TimeSyn].
PPS (DIN): Pulse per second (PPS) via the binary input [BI_TimeSyn].
SNTP(PTP): Unicast (point to point) SNTP mode via Ethernet network.
9 SAS
SNTP(BC): Broadcast SNTP mode via Ethernet network.
IEC103: Clock messages through IEC103 protocol.
MODBUS: Clock messages through MODBUS protocol.
If time synchronization function is not needed for the device, this option can be
NoTimeSyn
selected.
When the setting [Opt_TimeSyn] is set as "SAS", if there is no conventional clock synchronization
signal, the device will not send the alarm signal "Alm_TimeSyn".
When the setting [Opt_TimeSyn] is set as "Conventional", if there is no conventional clock

synchronization signal, "SAS" mode will be enabled automatically with the alarm signal

9 Settings
"Alm_TimeSyn" being issued simultaneously.
When the setting [Opt_TimeSyn] is set as "NoTimeSyn", the device will not send time
synchronization alarm signal.
The clock message via IEC103 protocol is INVALID when the device
receives the IRIG-B signal through RC-485 port.
9.1.7 Supervision Settings

Access path: MainMenu  Settings  Global Settings  Superv Settings
No. Name Range Unit Default Remark

Disabled Enabling/disabling VT circuit
1 x.VTS.En - Enabled
Enabled supervision
Voltage selection for protection
Bus calculation from busbar VT or bay VT
2 x.VTS.Opt_VT - Bus
Bay Bus: busbar VT
Bay: bay VT
Pickup time delay of VT circuit
3 x.VTS.t_DPU 0.000~30.000 s 1.25
supervision
Dropoff time delay of VT circuit
4 x.VTS.t_DDO 0.000~30.000 s 10
supervision
Positive-sequence voltage setting of
5 x.VTS.U1_Set 0.00~100.00 V 30
VT circuit supervision
Zero-sequence voltage setting of VT
6 x.VTS.3U0_Set 0.00~100.00 V 8
circuit supervision
Disabled Alarm function of VT neutral circuit
7 x.VTNS.En - Enabled
Enabled supervision
Pickup time delay of neutral VT circuit
8 x.VTNS.t_DPU 0.000~30.000 s 1.5
supervision
Dropoff time delay of neutral VT circuit
9 x.VTNS.t_DDO 0.000~30.000 s 10
supervision
10 x.VTNS.3U0_Hm3_Set 0.00~100.00 V 20
Zero-sequence voltage setting (third
harmonic component) of neutral VT
9
circuit supervision
Enabling/disabling resetting the CT
Disabled circuit failure alarm signal
11 En_AutoRecov_Alm_CTS - Disabled
Enabled automatically after the CT circuit
resturns to normal condition.
9.1.8 OutMap Settings

Access path: MainMenu  Settings  Global Settings  OutMap Settings

9 Settings

OutMapxxx 00000000~ Tripping logic setting of programmable trip
1 - 0
(xxx=001, 002…120) FFFF FFFF output map xxx
t_Dwell_xxx_OutMap The pulse width setting of programmable
2 0.000~0.500 s 0.060
(xxx=001, 002…032) trip output map xxx
9.2 Protection Settings

9.2.1 Transformer Current Differential Protection Settings (87T)
Access path: MainMenu  Settings  Protection Settings  Diff Settings

Pickup setting of biased differential
1 87T.I_Biased 0.050~5.000 p.u. 0.5
element
Current setting of instantaneous
2 87T.I_Inst 0.050~20.000 p.u. 4
Current setting of differential circuit
3 87T.I_Alm 0.050~1.500 p.u. 0.2
abnormality alarm
4 87T.I_Knee1 0.100~3.500 p.u. 0.5
5 87T.I_Knee2 4.000~8.000 p.u. 6
Coefficient of second harmonics
9 87T.K_Hm2_Inrush 0.050~0.800 - 0.15
for inrush current detection
Coefficient of third harmonics for
10 87T.K_Hm3_Inrush 0.050~0.800 - 0.2
inrush current detection
Coefficient of third or fifth harmonic
11 87T.K_Hm3/Hm5_OvExc 0.050~0.800 - 0.25 for overexcitation detection
The recommended value is 0.25.
12 87T.En_Inst - Disabled
Disabled instantaneous differential element
9 Logic setting for enabling/disabling
Enabled,
13 87T.En_Biased - Disabled conventional biased differential
Disabled
element
14 87T.En_DPFC - Disabled
Disabled DPFC biased differential element
Option of inrush current
WaveSym discrimination principle:
15 87T.Opt_Inrush_Ident - Hm2
Hm2 WaveSym: waveform symmetry
Hm2: Harmonic principle
16 87T.Opt_BlkMode_Inrush Adaptive, - Adaptive Option of inrush blocking mode

9 Settings

2PBlk3P, Adaptive: self-adaptive one-phase
1PBlk3P inrush blocking one-phase
2PBlk3P: two-phase inrush
element
1PBlk3P: one-phase inrush
element
Enabled,
17 87T.En_Hm3_Blk - Enabled the third harmonic blocking for
Disabled
inrush current
Option of third or fifth harmonic for
overexcitation criterion
18 87T.Opt_Hm3/Hm5_OvExc Hm3, Hm5 - Hm5
Hm3: third harmonic
Hm5: fifth harmonic
Enabled,
19 87T.En_CTS_Blk - Enabled blocking biased differential element
Disabled
during CT circuit failure
9.2.2 Restricted Earth Fault Protection Settings (64REF)

Access path: MainMenu  Settings  Protection Settings  REF Settings

1 x.64REF.I_Biased 0.050~5.000 In 0.5 Pickup setting of REF
2 x.64REF.I_Alm 0.050~1.500 In 0.2 Current setting of REF abnormality alarm
Knee point setting of REF
3 x.64REF.I_Knee 0.100~4.000 In 0.5
0.5In is recommended.
Percentage restraint coefficient of REF
4 x.64REF.Slope 0.200~0.750 - 0.5
0.5 is recommended.
5 x.64REF.ROA 45.000~90.000 deg 60 Operation angle setting
Time delay for REF
6 x.64REF.t_Op 0.000~20.000 s 0
Recommended value is zero.
7 x.64REF.En Enabled, Disabled - Disabled Logic setting for enabling/disabling REF 9
8 x.64REF.En_NPCurr Enabled, Disabled - Disabled
neutral current criterion
9 x.64REF.En_CTS_Blk Enabled, Disabled - Enabled
blocking REF during CT circuit failure
Logic setting for enabling/disabling the
10 x.64REF.En_Dir_Blk Enabled, Disabled - Disabled function of direction criterion blocking
REF

9 Settings
9.2.3 Winding Differential Protection (87W)

Access path: MainMenu  Settings  Protection Settings  WdgDiff Settings

Pickup setting of biased winding differential
1 87W.I_Biased 0.100~5.000 In 0.5
protection
Current setting of winding differential protection
2 87W.I_Alm 0.050~1.500 In 0.2
abnormality alarm
Knee point setting of biased winding
3 87W.I_Knee 0.100~4.000 In 0.5
Percentage restraint coefficient of biased
4 87W.Slope 0.100~0.900 - 0.5
winding differential protection
5 87W.t_Op 0.000~20.000 s 0 Time delay for winding differential protection
Enabled,
6 87W.En_PhSeg - Disabled phase-segregated winding differential
Disabled
protection
Enabled, Logic setting for enabling/disabling residual
7 87W.En_REF - Disabled
Disabled winding differential protection
Logic setting for enabling/disabling blocking
Enabled,
8 87W.En_CTS_Blk - Enabled winding differential protection during CT circuit
Disabled
failure
9.2.4 Overexcitation Protection (24)

Access path: MainMenu  Settings  Protection Settings  OvExc Settings

It is used to set reference voltage of
overexcitation calculation, and it is usually
1 24Cal.U1n 0.000~2000.000 kV 220
set as primary rated voltage at calculated
side of transformer
Voltage option between phase voltage
and phase-to-phase voltage for
2 24Cal.Opt_Up/Upp Up, Upp - Up calculation of overexcitation protection
Up: phase voltage
9 Upp: phase-to-phase voltage
3 24DT1.K_Set 1.000~1.600 - 1.3
overexcitation protection for trip purpose
4 24DT1.t_Op 0.100~9999.000 s 1 definite-time overexcitation protection for
trip purpose
Logic setting for enabling/disabling stage
Enabled,
5 24DT1.En - Disabled 1 of definite-time overexcitation protection
Disabled
for trip purpose
6 24DT2.K_Set 1.000~1.600 - 1.3 Multiple setting of stage 2 of definite-time

9 Settings

overexcitation protection for alarm
purpose
7 24DT2.t_Alm 0.100~9999.000 s 1 definite-time overexcitation protection for
alarm purpose
Logic setting of enabling/disabling stage 2
Enabled,
8 24DT2.En - Disabled of definite-time overexcitation protection
Disabled
for alarm purpose
Highest-limit multiple setting of
9 24IDMT.K0_Set 1.000~1.700 - 1.7
inverse-time overexcitation protection: n0
10 24IDMT.t0_Op 0.100~9999.000 s 1
highest-limit setting: t0
11 24IDMT.K1_Set 1.000~1.700 - 1.65
12 24IDMT.t1_Op 0.100~9999.000 s 2
13 24IDMT.K2_Set 1.000~1.700 - 1.6
14 24IDMT.t2_Op 0.100~9999.000 s 5
15 24IDMT.K3_Set 1.000~1.700 - 1.5
16 24IDMT.t3_Op 0.100~9999.000 s 10
17 24IDMT.K4_Set 1.000~1.700 - 1.4
18 24IDMT.t4_Op 0.100~9999.000 s 20
19 24IDMT.K5_Set 1.000~1.700 - 1.3
20 24IDMT.t5_Op 0.100~9999.000 s 50
21 24IDMT.K6_Set 1.000~1.700 - 1.25

Multiple setting 6 of inverse-time 9
22 24IDMT.t6_Op 0.100~9999.000 s 100
23 24IDMT.K7_Set 1.000~1.700 - 1.2
24 24IDMT.t7_Op 0.100~9999.000 s 300
25 24IDMT.K8_Set 1.000~1.700 - 1.15
26 24IDMT.t8_Op 0.100~9999.000 s 600 Time delay setting corresponding to

9 Settings

Lowest-limit multiple setting of
27 24IDMT.K9_Set 1.000~1.700 - 1.13
inverse-time overexcitation: n9
28 24IDMT.t9_Op 0.100~9999.000 s 1000
lowest-limit multiple setting: t9
Coefficient of time delay of inverse-time
29 24IDMT.K_Alm 0.500~1.000 - 0.7 overexcitation protection for alarm
purpose
Cooling time of inverse-time
30 24IDMT.t_Cooling 0.100~9999.000 s 10
Enabled,
31 24IDMT.En_Trp - Disabled inverse-time overexcitation protection for
Disabled
trip purpose
Enabled,
32 24IDMT.En_Alm - Disabled inverse-time overexcitation protection for
Disabled
alarm purpose
9.2.5 Phase Overcurrent Protection (50/51P, 67P)

Access path: MainMenu  Settings  Protection Settings  OC Settings

Low voltage setting
1 x.50/51P.VCE.Upp 10.000~100.000 V 70 of voltage control
element
Negative-sequence
voltage setting of
2 x.50/51P.VCE.U2 2.000~57.000 V 8
voltage control
element
Zero-sequence
voltage setting of
3 x.50/51P.VCE.3U0 2.000~57.000 V 8
voltage control
element
Enabling/Disabling
9 phase overcurrent
protection with
voltage control
Disabled element is blocked
4 x.50/51P.VCE.En_VTS_Blk - Disabled
Enabled by VT circuit failure
when VT circuit
supervision is
enabled and VT
circuit fails
5 x.50/51P.DIR.RCA -180~179 ° 45 The characteristic

9 Settings

angle of direction
control element
The minimum
boundary in forward
6 x.50/51P.DIR.phi_Min_Fwd 10~90 ° 90 direction of phase
overcurrent
protection
The maximum
boundary in forward
7 x.50/51P.DIR.phi_Max_Fwd 10~90 ° 90 direction of phase
overcurrent
protection
The minimum
boundary in reverse
8 x.50/51P.DIR.phi_Min_Rev 10~90 ° 90 direction of phase
overcurrent
protection
The maximum
boundary in reverse
9 x.50/51P.DIR.phi_Max_Rev 10~90 ° 90 direction of phase
overcurrent
protection
The voltage
polarization mode of
direction control
element
Upp: phase-to-phase
voltage is used as
Upp
polarized voltage
10 x.50/51P.DIR.Opt_PolarizedVolt Up - Upp
Up: phase-to-ground
U1
voltage is used as
polarized voltage
U1:
positive-sequence
9
voltage is used as
polarized
The minimum
operating current
11 x.50/51P.DIR.I_Min 0.050~1.000 In 0.05
control element
The minimum
12 x.50/51P.DIR.U_Min 1.000~10.000 V 4 operating voltage

9 Settings

control element
Enabling/Disabling
phase overcurrent
protection with
direction control
Disabled element is blocked
13 x.50/51P.DIR.En_VTS_Blk - Disabled
Enabled by VT circuit failure
when VT circuit
supervision is
enabled and VT
circuit fails
The coefficient of
second harmonics of
14 x.50/51P.HMB.K_Hm2 0.100~1.000 - 0.2
harmonic control
element
15 x.50/51P.HMB.I_Rls 2.000~150.000 A 20 releasing harmonic
control element
The option of
harmonic blocking
mode
PhaseBlk: phase
PhaseBlk,
blocking
16 x.50/51P.HMB.Opt_Blk CrossBlk, - PhaseBlk
CrossBlk: cross
MaxPhaseBlk
blocking
MaxPhaseBlk:
maximum phase
blocking
The current setting
17 x.50/51Pi.I_Set 0.050~200.000 A 15
overcurrent
protection (i=1~6)
The operating time
9 delay for stage i of
18 x.50/51Pi.t_Op 0.000~100.000 s 0.1
phase overcurrent
protection (i=1~6)
The dropout time
19 x.50/51Pi.t_DropOut 0.000~100.000 s 0
phase overcurrent
protection (i=1~6)
Enabling/Disabling
Disabled
20 x.50/51Pi.En_Volt_Blk - Disabled stage i of phase
Enabled
overcurrent

9 Settings

protection controlled
by voltage control
element (i=1~6)
NonDirectional characteristic for
21 x.50/51Pi.Opt_Dir Forward - NonDirectional stage i of phase
Reverse overcurrent
protection (i=1~6)
Enabling/Disabling
stage i of phase
Disabled overcurrent
22 x.50/51Pi.En_Hm_Blk - Disabled
Enabled protection controlled
by harmonic control
element (i=1~6)
Enabling/disabling
23 x.50/51Pi.En - Enabled
Enabled overcurrent
protection (i=1~6)
Enabling/disabling
stage i of phase
overcurrent
Trp
24 x.50/51Pi.Opt_Trp/Alm - Trp trip or alarm (i=1~6)
Alm
Trp: for tripping
purpose
Alm: for alarm
purpose
ANSIE
ANSIV
ANSIN
ANSIM
ANSIDefTime
ANSILTE
ANSILTV
The
operating
option of
9
ANSILT characteristics curve
25 x.50/51Pi.Opt_Curve - IECDefTime
IECN for stage i of phase
IECV overcurrent
IEC protection (i=1~6)
IECE
IECST
IECLT
IECDefTime
UserDefine

9 Settings

overcurrent
protection (i=1~6)
Inst: instantaneous
Inst
dropout
26 x.50/51Pi.Opt_Curve_DropOut DefTime - Inst
characteristics
IDMT
DefTime:
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier
27 x.50/51Pi.TMS 0.040~20.000 - 1 inverse-time phase
overcurrent
protection (i=1~6)
The minimum
operating time for
stage i of
28 x.50/51Pi.tmin 0.000~10.000 s 0.02
inverse-time phase
overcurrent
protection (i=1~6)
29 x.50/51Pi.K 0.0010~120.0000 - 0.14 inverse-time phase
overcurrent
protection (i=1~6)
30 x.50/51Pi.Alpha 0.0100~3.0000 - 0.02 inverse-time phase
9 overcurrent
protection (i=1~6)
31 x.50/51Pi.C 0.0000~1.0000 - 0 inverse-time phase
overcurrent
protection (i=1~6)
9.2.6 Earth Fault Overcurrent Protection (50/51G, 67G)

Access path: MainMenu  Settings  Protection Settings  ROC Settings

9 Settings

1 x.50/51G.DIR.RCA -180~179 ° 45
2 x.50/51G.DIR.phi_Min_Fwd 10~90 ° 90 forward direction of earth
fault protection
3 x.50/51G.DIR.phi_Max_Fwd 10~90 ° 90 forward direction of earth
fault protection
4 x.50/51G.DIR.phi_Min_Rev 10~90 ° 90 reverse direction of earth
fault protection
5 x.50/51G.DIR.phi_Max_Rev 10~90 ° 90 reverse direction of earth
fault protection
6 x.50/51G.DIR.I_Min 0.050~1.000 In 0.05 current setting of direction
control element
7 x.50/51G.DIR.U_Min 1.000~10.000 V 4 voltage setting of direction
control element
Enabling/Disabling earth
fault protection with direction
Disabled control element is blocked
8 x.50/51G.DIR.En_VTS_Blk - Disabled
Enabled by VT circuit failure when VT
circuit supervision is enabled
and VT circuit fails
protection with direction
Ext control element
9 x.50/51Gi.DIR.Opt_3I0 - Ext
current
current
9
10 x.50/51G.HMB.K_Hm2 0.100~1.000 - 0.2 harmonics of harmonic
control element
11 x.50/51G.HMB.I_Rls 2.000~150.000 A 20 releasing harmonic control
element
Ext
12 x.50/51Gi.HMB.Opt_3I0 - Ext current used by earth fault
Cal

9 Settings

harmonic control element
Ext: the measured residual
current
current
Ext
13 x.50/51Gi.Opt_3I0 - Ext Ext: the measured residual
Cal
current
current
The zero-sequence current
14 x.50/51Gi.3I0_Set 0.050~200.000 A 15 setting for stage i of earth
fault protection (i=1~4
The operating time delay for
15 x.50/51Gi.t_Op 0.000~100.000 s 0.1 stage i of earth fault
protection (i=1~4)
16 x.50/51Gi.t_DropOut 0.000~100.000 s 0 stage i of earth fault
protection (i=1~4)
NonDirectional The option direction
17 x.50/51Gi.Opt_Dir Forward - NonDirectional characteristic for stage i of
Reverse earth fault protection (i=1~4)
Disable earth fault protection
18 x.50/51Gi.En_Hm_Blk - Disabled
Disabled Enabling/disabling stage i of
19 x.50/51Gi.En - Enabled
Enabled earth fault protection (i=1~4)
earth fault protection operate
Trp
9 20 x.50/51Gi.Opt_Trp/Alm
Alm
- Trp to trip or alarm (i=1~4)
ANSIE
ANSIV
ANSIN The option of operating
ANSIM characteristics curve for
21 x.50/51Gi.Opt_Curve - IECDefTime
ANSIDefTime stage i of earth fault
ANSILTE protection (i=1~4)
ANSILTV
ANSILT

9 Settings

IECN
IECV
IEC
IECE
IECST
IECLT
IECDefTime
UserDefine
stage i of earth fault
protection (i=1~4
Inst
22 x.50/51Gi.Opt_Curve_DropOut DefTime - Inst
characteristics
IDMT
characteristics
23 x.50/51Gi.TMS 0.040~20.000 - 1 stage i of inverse-time earth
fault protection (i=1~4)
The minimum operating time
24 x.50/51Gi.tmin 0.000~10.000 s 0.02 for stage i of inverse-time
earth fault protection (i=1~4
25 x.50/51Gi.K 0.0010~120.0000 - 0.14 of customized inverse-time
earth fault protection (i=1~4)
26 x.50/51Gi.Alpha 0.0100~3.0000 - 0.02 of customized inverse-time
27 x.50/51Gi.C 0.0000~1.0000 - 0 of customized inverse-time
9
9.2.7 Negative-sequence Overcurrent Protection (50/51Q, 67Q)
Access path: MainMenu  Settings  Protection Settings  NegOC Settings

The characteristic
1 x.50/51Q.DIR.RCA -180~179 ° 45 angle of direction
control element
The minimum
2 x.50/51Q.DIR.phi_Min_Fwd 10~90 ° 90
boundary in forward

9 Settings

direction of
negative-sequence
overcurrent
protection
The maximum
boundary in forward
direction of
3 x.50/51Q.DIR.phi_Max_Fwd 10~90 ° 90
negative-sequence
overcurrent
protection
The minimum
boundary in reverse
direction of
4 x.50/51Q.DIR.phi_Min_Rev 10~90 ° 90
negative-sequence
overcurrent
protection
The maximum
boundary in reverse
direction of
5 x.50/51Q.DIR.phi_Max_Rev 10~90 ° 90
negative-sequence
overcurrent
protection
The minimum
operating current
6 x.50/51Q.DIR.I_Min 0.050~1.000 In 0.05
control element
The minimum
operating voltage
7 x.50/51Q.DIR.U_Min 1.000~10.000 V 4
control element
Enabling/Disabling
negative-sequence
overcurrent
9 protection with
direction control
Disabled
8 x.50/51Q.DIR.En_VTS_Blk - Disabled element is blocked
Enabled
by VT circuit failure
when VT circuit
supervision is
enabled and VT
circuit fails
The
9 x.50/51Qi.I2_Set 0.050~200.000 A 15
negative-sequence

9 Settings

current setting for
stage i of
negative-sequence
overcurrent
The operating time
10 x.50/51Qi.t_Op 0.030~100.000 s 0.1 negative-sequence
overcurrent
The dropout time
11 x.50/51Qi.t_DropOut 0.000~100.000 s 0 negative-sequence
overcurrent
characteristic for
NonDirectional
stage i of
12 x.50/51Qi.Opt_Dir Forward - NonDirectional
negative-sequence
Reverse
overcurrent
Enabling/disabling
stage i of
Disabled
13 x.50/51Qi.En - Enabled negative-sequence
Enabled
overcurrent
Enabling/disabling
stage i of
negative-sequence
overcurrent
Trp
14 x.50/51Qi.Opt_Trp/Alm - Trp trip or alarm (i=1 or
Alm
2)
Trp: for tripping
9
purpose
Alm: for alarm
purpose
ANSIE The option of
ANSIV operating
ANSIN characteristics curve
15 x.50/51Qi.Opt_Curve - IECDefTime
ANSIM for stage i of
ANSIDefTime negative-sequence
ANSILTE overcurrent

9 Settings

ANSILTV protection (i=1 or 2)
ANSILT
IECN
IECV
IEC
IECE
IECST
IECLT
IECDefTime
UserDefine
The option of
dropout
for stage i of
negative-sequence
overcurrent
Inst
Inst: instantaneous
16 x.50/51Qi.Opt_Curve_DropOut DefTime - Inst
dropout
IDM
characteristics
DefTime:
characteristics
IDMT: inverse-time
dropout
characteristics
Time multiplier
inverse-time
17 x.50/51Qi.TMS 0.040~20.000 - 1
negative-sequence
overcurrent
The minimum
9 operating time for
stage i of
18 x.50/51Qi.tmin 0.000~10.000 s 0.02 inverse-time
negative-sequence
overcurrent
19 x.50/51Qi.K 0.0010~120.0000 - 0.14
inverse-time
negative-sequence

9 Settings

overcurrent
inverse-time
20 x.50/51Qi.Alpha 0.0100~3.0000 - 0.02
negative-sequence
overcurrent
inverse-time
21 x.50/51Qi.C 0.0000~1.0000 - 0
negative-sequence
overcurrent
9.2.8 Thermal Overload Protection (49)

Access path: MainMenu  Settings  Protection Settings  ThOvLd Settings

1 x.49.Ib_Set 0.050~200.000 A 15 Base current setting of thermal overload protection
Tripping setting of thermal capacity for thermal
2 x.49.K_Trp 1.000~3.000 - 1.2
overload protection
Alarm setting of thermal capacity for thermal
3 x.49.K_Alm 1.000~3.000 - 1.1
overload protection
4 x.49.Tau 0.100~100.000 min 1 Thermal time constant
The convertor coefficient from the current to the
5 x.49.K_T_Diff 0.000~200.000 - 30
temperature
The cooling mode of transformer, usually,
6 x.49.Alpha_Cold 1.000~2.000 - 2 natural cooling: 1.6
forced cooling: 2
7 x.49.En_Trp - Disabled
Enabled protection for trip purpose
8 x.49.En_Alm
Enabled
- Disabled
protection for alarm purpose 9
9.2.9 Breaker Failure Protection (50BF)
Access path: MainMenu  Settings  Protection Settings  BFP Settings

The phase current setting of breaker failure
1 x.50BF.I_Set 0.050~200.000 A 1.000
protection
The zero-sequence current setting of
2 x.50BF.3I0_Set 0.050~200.000 A 1.000

9 Settings

The negative-sequence current setting of
3 x.50BF.I2_Set 0.050~200.000 A 1.000
The re-trip time delay of breaker failure
4 x.50BF.t_ReTrp 0.000~20.000 s 0.050
protection
The first time delay of breaker failure
5 x.50BF.t1_Op 0.000~20.000 s 0.100
protection
The second time delay of breaker failure
6 x.50BF.t2_Op 0.000~20.000 s 0.200
protection
Disabled
7 x.50BF.En - Enabled Enabling/disabling breaker failure protection
Enabled
Disabled Enabling/disabling re-trip function of breaker
8 x.50BF.En_ReTrp - Enabled
Disabled Enabling/disabling first time delay of breaker
Disabled Enabling/disabling second time delay of
Enabled breaker failure protection
Disabled
Enabled
protection via single-phase initiating signal
Enabling/disabling phase overcurrent
Disabled
12 x.50BF.En_Ip - Disabled element of breaker failure protection via
Enabled
three-phases initiating signal
Disabled
Enabled
Enabling/disabling negative-sequence
Disabled
14 x.50BF.En_I2_3P - Disabled overcurrent element of breaker failure
Enabled
Enabling/disabling breaker failure protection
Disabled
15 x.50BF.En_CB_Ctrl - Disabled be initiated by normally closed contact of
Enabled
circuit breaker
Disabled Enabling/disabling abnormality check of
16 x.50BF.En_Alm_Init - Disabled
9 Enabled breaker failure initiating signal
9.2.10 Phase Overvoltage Protection (59P)

Access path: MainMenu  Settings  Protection Settings  OV Settings

The option of the voltage
criterion used by stage i of
3P
1 x.59Pi.Opt_1P/3P - 3P phase overvoltage
1P
3P: 3-out-of-3 mode

9 Settings

1P: 1-out-of-3 mode
The option of the
calculation voltage used by
stage i of phase
Up overvoltage protection (i=1
2 x.59Pi.Opt_Up/Upp - Upp
Upp or 2)
Up: phase voltage
Upp: phase-to-phase
voltage
The voltage setting for
stage i of phase
3 x.59Pi.U_Set 57.700~200.000 V 115
overvoltage protection (i=1
or 2)
The dropout coefficient for
stage i of phase
4 x.59Pi.K_DropOut 0.930~1.000 - 0.98
or 2)
The operating time delay
5 x.59Pi.t_Op 0.100~100.000 s 1
or 2)
stage i of phase
6 x.59Pi.t_DropOut 0.000~100.000 s 0
or 2)
Disabled
7 x.59Pi.En - Enabled of phase overvoltage
Enabled
of phase overvoltage
Trp protection operate to trip or
8 x.59Pi.Opt_Trp/Alm - Trp
Alm alarm (i=1 or 2)
9
ANSIDefTime
IECDefTime
UserDefine
InvTime_U
or 2)
Inst characteristics curve for
DefTime stage i of phase

9 Settings

or 2)
characteristics
stage i of inverse-time
11 x.59Pi.TMS 0.040~20.000 - 1
phase overvoltage
time for stage i of
or 2)
13 x.59Pi.K 0.0010~120.0000 - 1
phase overvoltage
14 x.59Pi.Alpha 0.0100~3.0000 - 1
phase overvoltage
15 x.59Px.C 0.0000~1.0000 - 0
phase overvoltage
9.2.11 Residual Overvoltage Protection (59G)

Access path: MainMenu  Settings  Protection Settings  ROV Settings

The option of the residual voltage used by
Ext residual overvoltage protection
9 1 x.59G.Opt_3U0
Cal
- Ext
Ext: the measured residual voltage
Cal: the calculated residual voltage
The voltage setting for stage i of residual
2 x.59Gi.3U0_Set 1.000~200.000 V 50
The dropout coefficient for stage i of
3 x.59Gi.K_DropOut 0.930~1.000 - 0.98
The operating time delay for stage i of
4 x.59Gi.t_Op 0.100~100.000 s 1
The dropout time delay for stage i of
5 x.59Gi.t_DropOut 0.000~100.000 s 0

9 Settings

Disabled Enabling/disabling stage i of residual
6 x.59Gi.En - Enabled
Enabled overvoltage protection (i=1 or 2)
Enabling/disabling stage i of residual
overvoltage protection operate to trip or
Trp
7 x.59Gi.Opt_Trp/Alm - Trp alarm (i=1 or 2)
Alm
9.2.12 Phase Undervoltage Protection (27P)

Access path: MainMenu  Settings  Protection Settings  UV Settings

The option of the
voltage criterion used
3P by phase undervoltage
1 x.27P.Opt_1P/3P - 3P
1P protection
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
The option of the
calculation voltage used
by phase undervoltage
Up
2 x.27P.Opt_Up/Upp - Up protection
Upp
Up: phase voltage
Upp: phase-to-phase
voltage
The option of auxiliary
criterion mode for
phase undervoltage
protection
None: no check
Curr: check current
None condition
Curr CBPos: check normally
3 x.27P.Opt_LogicMode CBPos - CurrAndCBPos open auxiliary contact 9
CurrOrCBPos CurrOrCBPos: check
CurrAndCBPos current condition or
contact
CurrAndCBPos: check
current condition and
contact
4 x.27Pi.U_Set 5.000~120.000 V 80 The voltage setting for

9 Settings

stage i of phase
(i=1 or 2)
The dropout coefficient
5 x.27Pi.K_DropOut 1.000 ~1.200 - 1.03
(i=1 or 2)
The operating time
6 x.27Pi.t_Op 0.100~100.000 s 1
phase undervoltage
The dropout time delay
7 x.27Pi.t_DropOut 0.000~100.000 s 0
(i=1 or 2)
Enabling/Disabling
stage i of phase
Disabled is blocked by VT circuit
8 x.27Pi.En_VTS_Blk - Disabled
Enabled failure when VT circuit
supervision is enabled
and VT circuit fails (i=1
or 2)
Enabling/disabling
9 x.27Pi.En - Enabled
Enabled undervoltage protection
(i=1 or 2)
Enabling/disabling
stage i of phase
Trp
10 x.27Pi.Opt_Trp/Alm - Trp operate to trip or alarm
Alm
(i=1 or 2)
9 Alm: for alarm purpose
ANSIDefTime
IECDefTime
UserDefine
InvTime_U
(i=1 or 2)
Inst characteristics curve for
DefTime stage i of phase

9 Settings

(i=1 or 2)
Inst: instantaneous
Time multiplier setting
for stage i of
13 x.27Pi.TMS 0.040~20.000 - 1 inverse-time phase
(i=1 or 2)
time for stage i of
(i=1 or 2)
15 x.27Pi.K 0.0010~120.0000 - 0.14 inverse-time phase
(i=1 or 2)
16 x.27Pi.Alpha 0.0100~3.0000 - 0.02 inverse-time phase
(i=1 or 2)
17 x.27Px.C 0.0000~1.0000 - 0 inverse-time phase
(i=1 or 2)
9.2.13 Overfrequency Protection (81O)

Access path: MainMenu  Settings  Protection Settings  FreqProt Settings
9
1 81Oi.Upp_VCE 10.000~150.000 V 70 block stage i of overfrequency protection
(i=1~2)
2 81Oi.f_Set 50.000~65.000 Hz 52
overfrequency protection (i=1~2)
The time delay for stage i of overfrequency
3 81Oi.t_Op 0.100~100.000 s 0.3
protection (i=1~2)

9 Settings

Disabled Enabling/disabling stage i of overfrequency
4 81Oi.En - Enabled
9.2.14 Underfrequency Protection (81U)

Access path: MainMenu  Settings  Protection Settings  FreqProt Settings

1 81Ui.Upp_VCE 10.000~150.000 V 70 block stage i of underfrequency protection
(i=1~4)
2 81Ui.f_Set 45.000~60.000 Hz 48
underfrequency protection (i=1~4)
The time delay for stage i of underfrequency
3 81Ui.t_Op 0.100~100.000 s 0.3
protection (i=1~4)
Disabled Enabling/disabling stage i of underfrequency
4 81Ui.En - Enabled
9.3 Measurement and Control Settings

9.3.1 Function Settings

through PCS-Studio software, which may be “HVS”, “HVS2”, “MVS”,
“MVS2”, “LVS”, “LVS2” by default.
Access path: MainMenu  Settings  Meas Control Settings  Function Settings

Threshold to limit the zero-drift influence of
power due to temperature or other
1 x.ZeroDrift_PQ 0.00~1.00 % 0.5 environmental factors. A measured value
less than this setting will be regarded as a
9 zero drift and ignored.
2 25.Ref.ZeroDrift_U 0.00~1.00 % 0.2 Threshold to limit the variation influence of
reference side/synchronization side voltage
due to temperature or other environmental
3 25.Syn.ZeroDrift_U 0.00~1.00 % 0.2
factor. A variation less than this setting will
be regarded as a zero drift and ignored.
Threshold to limit the zero-drift influence of
DC current/voltage input due to
4 B**.ZeroDrift 0.00~1.00 % 0.2
temperature or other environmental factors.
A measured value less than this setting will

9 Settings

be regarded as a zero drift and ignored.
9.3.2 Synchronism Check Settings

Access path: MainMenu  Settings  Meas Control Settings  Syn Settings

Selection of circuit breaker
NoVolSel, DblBusOneCB,
1 Opt_CBConfig - NoVolSel arrangement for voltage
3/2BusCB, 3/2TieCB
switching
Selection of decision mode
2 25.Opt_ValidMode Setting or Config - Setting
Logic setting for
synchro-check (valid only if
3 25.En_SynChk Disabled or Enabled - Enabled the setting
[25.Opt_ValidMode] =
Config)
Logic setting for dead
charge check (valid only if
4 25.En_DdChk Disabled or Enabled - Enabled the setting
[25.Opt_ValidMode] =
Config)
Percentage threshold of
5 25.U_UV 0.00~100.00 % 80.00 under voltage for CB
closing blocking
6 25.U_OV 100.00~170.00 % 170.00 over voltage for CB closing
blocking
7 25.f_UF 0.000~65.000 Hz 45.000 under frequency for CB
closing blocking
8 25.f_OF 0.000~65.000 Hz 65.000 over frequency for CB
closing blocking
Ua, Ub, Uc, Uab, Ubc, Selection of voltage for
9
9 25.Opt_U_SynChk - Ua
Uca synchronism check
Threshold of voltage
10 25.U_Diff_Set 0.00~100.00 V 10.00 difference for synchronism
check
11 25.f_Diff_Set 0.00~2.00 Hz 0.50 difference for synchronism
check
12 25.df/dt_Set 0.00~2.00 Hz/s 1.00
variation for synchronism

9 Settings

check.
Threshold of phase
13 25.phi_Diff_Set 0.00~180.00 ° 15.00 difference for synchronism
check
Compensation angle of
14 25.phi_Comp 0.00~360.00 ° 0.00 phase difference for
synchronism check
SynDdRefDd
SynLvRefDd
SynDdRefLv
Selection of dead charge
15 25.Opt_Mode_DdChk RefDd - AnySideDd
check mode
SynDd
SynLvRefDd/SynDdRefLv
AnySideDd
Threshold for voltage dead
16 25.U_DdChk 0.00~100.00 V 17.32
check
Threshold for voltage live
17 25.U_LvChk 0.00~100.00 V 34.64
check
Threshold of duration for
18 25.t_Reset 0~60 s 5
synchrocheck
Circuit breaker closing time.
It is the time from receiving
19 25.t_Close_CB 0~2000 ms 20 closing command pulse till
the CB is completely
closed.
 25.Opt_Mode_DdChk
No. Setting Value Dead charge check mode
1 SynDdRefDd Dead check for both the reference and the synchronization sides
2 SynLvRefDd Live check for synchronization side and dead check for reference side
3 SynDdRefLv Dead check for synchronization side and live check for reference side
4 RefDd Dead check for reference side

9 5 SynDd Dead check for synchronization side
6 SynLvRefDd/SynDdRefLv Option 2 or 3
7 AnySideDd Option 1, 2 or 3
9.3.3 Double Point Status Settings

Access path: MainMenu  Settings  Meas Control Settings  DPS Settings

1 CSWI**.DPS.t_DPU 0~60000 ms 500 Delay Pick Up (DPU) time, i.e. debounce

9 Settings

time, for DPS
Disabled
2 CSWI**.DPS.En_Alm - Disabled Logic setting for DPS alarm
Enabled
3 CSWI**.DPS.t_Alm 0~60000 ms 500 Operation time delay of DPS alarm
9.3.4 Control Settings

MainMenu  Settings  Meas Control Settings  Control Settings

Pulse Width (PW), i.e. holding time, for opening
1 CSWI**.t_PW_Opn 0~60000 ms 500
output
Pulse Width (PW), i.e. holding time, for closing
2 CSWI**.t_PW_Cls 0~60000 ms 500
output
Pulse Width (PW), i.e. holding time, for direct
3 DirCtrl**.t_PW_Opn 0~60000 ms 500
opening output
Pulse Width (PW), i.e. holding time, for direct
4 DirCtrl**.t_PW_Cls 0~60000 ms 500
closing output
5 84CSWI**.t_PW_Cls 0~60000 ms 500
changer closing output
6 84CSWI**.t_PW_Opn 0~60000 ms 500
changer opening output
9.3.5 Tap Changer Indicator Settings

 Access path:
MainMenu  Settings  Meas Control Settings  TP Settings

Total tap changer indication
1 84.Num 0~26 - 26 number that should coordinate with
the input code
Selection of tap changer indication
input code
Resv: input direct or DC analog
channel
9
Resv
BCD: 6-bit BCD for max. 39
BCD
positions
Carry
2 84.Opt_Code - BCD Carry: 13-bit carry inputs for max.
Independent
29 positions
BCD-PhSeg
Independent: 26-bit independent
Independent-PhSeg
contacts for max. 26 positions
BCD-PhSeq: 18-bit BCD for max.
39 phase-separated positions
Independent-PhSeq: 24-bit

9 Settings

independent contacts for max. 8
phase-separated positions
Delay Pick Up (DPU) time, i.e.
3 84.t_DPU 0~6000 ms 500 debounce time, for tap changer
indication inputs
Logic setting for tripping output of
Disabled or
4 84.En_SlideTrip - Disabled tap changer motor mechanism
Enabled
power supply during "sliding tap"
Holding time for tripping output of
5 84.t_SlideTrip 0~6000 ms 500 tap changer motor mechanism
power supply during "sliding tap"
9.3.6 Interlocking Logic Settings

 Access path:
MainMenu  Settings  Meas Control Settings  Interlock Settings

1 CSWI**.En_CILO_Opn - Disabled
Enabled opening output.
2 CSWI**.En_CILO_Cls - Disabled
Enabled closing output.
3 DirCtrl**.En_CILO_Opn - Disabled
Enabled direct opening output.
4 DirCtrl**.En_CILO_Cls - Disabled
Enabled direct closing output.
5 84CSWI**.En_CILO_Opn - Disabled
Enabled opening output of tap changer.
6 84CSWI**.En_CILO_Cls - Disabled
Enabled closing output of tap changer.
9.3.7 DC Measuring Transducers Settings

 Access path:
9 Main Menu  Settings  Meas Control Settings DCAI Settings

Selection of DC analog input type
0~10V Please refer to the corresponding

1 DCAI.Opt_Type_Transducer** - 0~20mA
0~20mA jumper of DC AI module to realize the
selection.
The minimal converted value (physical

2 DCAI.Min_Transducer** -60000~60000 - 0
quantity)

9 Settings

The maximal converted value (physical
3 DCAI.Max_Transducer** -60000~60000 - 250
quantity)
9.4 Logic Links

9.4.1 Function Links
Access path: MainMenuSettingsLogic LinksFunction Links

Disabled
1 Link_** - Enabled Enabling/disabling function link setting **
Enabled
9.4.2 GOOSE Sending Links

Access path: MainMenuSettingsLogic LinksGOOSE Send Links

Disabled Enabling/disabling GOOSE sending link setting
1 Trip**.Glink_Send - Enabled
Enabled **
9.4.3 GOOSE Receiving Links

Access path: MainMenuSettingsLogic LinksGOOSE Recv Links

Disabled Enabling/disabling GOOSE receiving link setting
1 Name**.Glink_Recv - Enabled
Enabled **

9 Settings

Appendix A Glossary
Appendix A Glossary
The abbreviations adopted in this manual are listed as below.
BOM Binary Output Module

A
C
"a" Contact is breaker auxiliary contact (ANSI
Standard Device Number 52A) that closes
C37.94 IEEE/ANSI protocol used when
when the breaker is closed and opens when
sending binary signals between IEDs
the breaker is open.
CB Circuit breaker
AC Alternating current
CID Configured IED Description
A/D converter Analog-to-digital converter
COMTRADE Standard Common Format for
AI Analog input
Transient Data Exchange format for
ANSI American National Standards Institute Disturbance recorder according to IEEE/ANSI
C37.111, 1999 / IEC 60255-24
AR Autoreclosing
CPU Central Processing Unit
ASDU Application Service Data Unit–An
ASDU can consist of one or more identical CRC Cyclic Redundancy Check
information objects. A sequence of the same
CT Current Transformer
information elements, for example measured
values, is identified by the address of the CTS Current Circuit Supervision
information object. The address of the
information object defines the associated D
address of the first information element of the
sequence. A consecutive number identifies the DBDL Dead Bus Dead Line
subsequent information elements. The number
DBLL Dead Bus Live Line
builds on this address in integral increments
(+1). DC Direct Current
DLLB Dead Line Live Bus

B
DNP Distributed Network Protocol as per IEEE
"b" Contact is breaker auxiliary contact (ANSI Std 1815-2012
Standard Device Number 52B) that closes
DPFC Deviation of Power Frequency
when the breaker is open and opens when the
Component–In case of a fault occurred in the
breaker is closed.
power system, the fault component could be
BFP Breaker failure protection analyzed into three parts: the power frequency
components before the fault, the power
BI Binary Input
frequency variables during the fault and the
BO Binary Output transient variables during the fault. DPFC is
A
the power frequency variable during the fault.
BIM Binary Input Module
PCS-978S Transformer Relay 1

Appendix A Glossary
DSP Digital Signal Processor L

DTT Direct Transfer Trip Scheme
LCD Liquid Crystal Display
E LED Light-emitting Diode
EHV Extra High Voltage M

EMC Electromagnetic Compatibility
MCB Miniature Circuit Breaker
F MMS Manufacturing Message Specification
MOV Metal-oxide Varistor

FL Fault Location
FR Fault Recorder O
G OLTC On-load Tap Changer
OOS Out-of-Step
G.703 Electrical and functional description for
digital lines used by local telephone
P
companies. Can be transported over balanced
and unbalanced lines
PD Pole Discrepancy
GIS Gas-insulated Switchgear
PDTT Permissive Direct Transfer Trip
GOOSE Generic Object-Oriented Substation
PL Programmable Logic
Event
POTT Permissive Overreaching Transfer Trip
GPS Global Positioning System
PPM Pulse Per Minute
H
PPS Pulse Per Second
HMI Human-machine Interface PRP Parallel Redundancy Protocol
HSR High-availability Seamless Redundancy PUTT Permissive Underreaching Transfer Trip
HV High-voltage
R
HVDC High-voltage Direct Current
RMS Root Mean Square
I
RSTP Rapid Spanning Tree Protocol
ICD IED Capability Description RTD Resistance Temperature Detector
IEC International Electrotechnical Commission RTU Remote Terminal Unit
IED Intelligent Electronic Device

S
A IRIG-B InterRange Instrumentation Group
Time code format B SA Substation Automation
2 PCS-978S Transformer Relay

Appendix A Glossary
SCADA Supervision, Control And Data period of time.

Acquisition
SOTF Switch-Onto-Fault
SCD Substation Configuration Description
STP Rapid Spanning Tree Protocol
SCL Substation Configuration Description
Language T
SLD Single-line Diagram
TCS Trip Circuit Supervision
SIR Source-to-line Impedance Ratio
TCP/IP Transmission Control Protocol over
SNMP Simple Network Management Internet Protocol
Protocol–An Internet standard protocol and
serves for the administration of nodes in an IP U
network.
UTC Coordinated Universal Time
SNTP Simple Network Time Protocol–A
protocol for the synchronization of clocks via
W
the Internet. With SNTP, client computers can
synchronize their clocks via the Internet with a
WI Weak end infeed
time server.
SOE Sequence of Events–An ordered, V

time-stamped log of status changes at binary
inputs (also referred to as state inputs). SOE is VT Voltage transformer
used to restore or analyze the performance, or
VTS Voltage Circuit Supervision
an electrical power system itself, over a certain
A list of function numbers used to represent electrical protection and control element. The device
function numbers used in this manual include the following:
21 Distance element 52 AC circuit breaker
24 Overexcitation element 59 Overvoltage element
25 Synchronism-check element 64 Restricted earth fault element
27 Undervoltage element 67 Directional overcurrent element
32 Power element 68 Power swing blocking element
37 Undercurrent element 78 Out-of-step element
46 Phase-balance current element 79 Reclosing element
49 Thermal overload element 81 Frequency element
50 Instantaneous overcurrent element 85 Pilot element
51 Definite-time or inverse-time overcurrent 87 Differential element

element A
These numbers are frequently used within a suffix letter to further designate their application. The
suffix letters used in this instruction manual include the following:
PCS-978S Transformer Relay 3

Appendix A Glossary
P Phase element
G Residual/Ground element
N Neutral/Ground element
Q Negative-sequence element
4 PCS-978S Transformer Relay


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About This Manual

Indicates an imminently hazardous situation that, if not avoided, will

result in death or serious injury.

Indicates a potentially hazardous situation that, if not avoided, could

result in death or serious injury.

Indicates a potentially hazardous situation that, if not avoided, may result

in minor or moderate injury or equipment damage.

Important information about the device, product handling or a certain

Instructions and Warnings

Disconnect or de-energize all external connections BEFORE opening this

PCS-978S Transformer Relay I

This device is shipped with default passwords. Default passwords should

DO NOT look into the fiber (laser) ports/connectors.

DO NOT look into the end of an optical cable connected to an optical

DO NOT perform any procedures or adjustments that this instruction

During installation, maintenance, or testing of the optical ports, ONLY use

II PCS-978S Transformer Relay

the test equipment qualified for Class 1 laser products!

Incorporated components, such as LEDs, transceivers, and laser emitters,

Equipment components are SENSITIVE to electrostatic discharge (ESD).

Insufficiently rated insulation can deteriorate under abnormal operating

SEVERE power and ground problems can occur on the communications

Use of controls or adjustments, or performance of procedures other than

The firmware may be upgraded to add new features or enhance/modify

PCS-978S Transformer Relay III

 Menu path is connected with the arrow "→" and bold.

For example: the access path of protection settings is: MainMenu→Settings→Protection

 Settings not in the table should be placed in brackets.

For example: the system setting [Opt_SysFreq]

 Cross-references are presented in italics.

For example: press the button "ENT".

& & &

>=1 >=1 >=1

 Binary signal Input

IV PCS-978S Transformer Relay

Optional definite-time or inverse-time characteristic

Fixed delay pickup (10ms), fixed delay dropout (2ms)

Settable delay pickup, fixed delay dropout

Fixed delay pickup, settable delay dropout

Settable delay pickup, settable delay dropout

PCS-978S Transformer Relay V

VI PCS-978S Transformer Relay

Three-phase Corresponding Relationship

PCS-978S Transformer Relay VII

Document Revision History

Current version: R1.00

R1.00 B1.00 2019-01-31  Form the original manual.

VIII PCS-978S Transformer Relay

1.1 Application ....................................................................................................... 1-1

Figure 1.1-1 2-windings transformer ....................................................................................... 1-1

Figure 1.1-2 3-windings transformer ....................................................................................... 1-1

Figure 1.1-3 Auto-transformer with two sides ........................................................................ 1-2

Figure 1.1-4 Auto-transformer with three sides ..................................................................... 1-2

Figure 1.1-5 Typical application of a 3-windings transformer .............................................. 1-3

PCS-978S Transformer Relay 1-a

1-b PCS-978S Transformer Relay

PCS-978S is adaptive to the following 2/3-windings transformers or autotransformer.

Figure 1.1-1 2-windings transformer

Figure 1.1-2 3-windings transformer

PCS-978S Transformer Relay 1-1

Figure 1.1-3 Auto-transformer with two sides

Figure 1.1-4 Auto-transformer with three sides