AIN SHAMS UNIVERSITY FACULTY OF ENGINEERING I-CREDIT HOURS ENGINEERING PROGRAMS COMM, CESS, MCTA Programs ) Final Exam I Semester, 2021/2022 Course Code: CSE111, CSE115, CSE141_ Time allowed: 2 Hrs. Logic Design.(UG2018), Digital Design (UG2013), Logic Design (UG2013) The Exam Consists of FIVE Questions in Two Pages. ‘Maximum Marks: 40 Marks 1/2 «© Having a (mobile-Smart Watch- earphones) inside the examination | a (541 dela - 2453 cleLall pant) Sho © halls forbidden and is considered as a cheating behavior. sell ang tb le pin asi nd « Its forbidden to have any references, nates, books, or any other sic ae é ‘materials even iit Is not related to the exam content with you in the | Sel" dls dl Mal 3} pla st was gh Upea ceen UL all ‘examination hall. Try All Questions and Assume Any Missing Information Question (1) [Lo1, Lo2] - [4 Marks] Draw the logic diagram of a combinational circuit that multiplies the binary numbers A and B. Note that A and B are given in ones-complement representation with size of 5 bits each. In your design, use 4-bit adders and external gates. You need to justify and analyze your model with neat sketches. Question (2): [Lo1, Lo2] - [8 Marks] Design a combinational circuit to implement the following function:- £(A, B,C, D, E) = ] [0o24.6.8,10,12,14, 16,18, 20,22, 24, 26,28, 30) 2 using a decoder and external gates. b+ using an 8 X 1 multiplexer and external gates. Question (3} [Lo3] - [10 Marks: 3+ 7] = ° b- Given two 4-bit numbers stored in two registers A and B, draw the logic diagram of a digital circuit that finds and stores the maximum number in a third register C. You may use any compnent given in the course lectures to achieve your goal. Question (4): [Lo3] - [12 Marks] Build a finite state machine (FSM) with an input X and an output Z. If the sequence ‘0110’ shows up on X, then a value ‘1’ should show up on 2, otherwise ‘0’. Allow overlap of Sequences (ie., end of one sequence could be the beginning of another one). Unused states should go to the initial valid state. You need to give two different designs, One for Moore and the other for Mealy. In each design case:- a) Draw the state diagram. b) Write the state stable. ¢) Find state equations, using JK flip flops. d) Draw the circuit diagram. CamScanner + li92 4>s.uaallJAIN SHAMS UNIVERSITY, FACULTY OF ENGINEERING i-CREDIT Hours Engineering Programs Programs of COMM, CESS, MCTA Feet, OTTO Cours Code SEIT, SELTS, SET Tine Mowe 7s Log Design (G20), Oiptal Dein (062013), tone Desen(UG2013) The Exam Consists of FIVE Questions in Two Pages. 2/2 Question (5) [Lo5] - [6 marks} Draw the logic diagram of a 4-bit register with four JK flip-flops and four 4 x 1 multiplexers with mode-selection inputs S: and So. The register operates according to the following function table: Regis r Operation END of Exam, Good Luck Examination Committee Exam, Date : 01/02/2022 Dr. Ahmed Saeed, Dr. Tomer Mostafa, Prof. Dr. Hossam Abdelmunim. CamScanner 4 Lig a guaall