Exavo FY. Bsc 6ub-' Digite) Flectemles. Exaro Date-:- '5/03] 'F DE Solution Set — QP Code : 00904 1.__| Attempt any three of the following: a, | Define digital signal. (1M) ‘With respect to digital signal explain the terms — digits and bits.2M) Also discuss active high and active low signal. (2M) 42 Di ¥ | & Binary system : {ndigitave se binary. which rests alta sine Hamsomesy a ane ‘have only two distinct values or states. ‘The reasons or advantages of binary system até as follows 1, Most information processing system are constructed from ‘Switches, which are binary devices. 2. Binary signals are more reliable 3. Thebasic-detision making processes required of digital systems are’ binary, | Bifs As bay guatioy So s semen: 7 netted i ny dite pga fora ic coment SN ESepeoemn nga een aa aaa “8 Sinaia binary amy 5 ty poi Wows ae ots BAY ae Te Fig. wit ow snag sige wh HSL ‘s ‘sot Bi velage ahs Yea Se LOW tel egal Noma Wircomesion Wei pete In binary logic the two levels are logical high and logical low, which generally correspond to a binary 1 and 0 respectively. Signals with onc of these two levels can be used in boolean logic for digital circuit design or analysis. ‘The use of either the higher or the lower voltage level to represent either logic state is arbitrary. The ‘two options are active high and active low. Active-high and active-low states can be mixed at will: for example, a read only memory integrated circuit may have a chip-select signal that is active-low, ‘ut the data and address bits are conventionally active-high. Occasionally a logic design is simplified ‘by inverting the choice of active level (see De Morgan's theorem). Binary signel representations Logic level Active-high signal Active-low signal Logical high 1 0 Logical low 0 1‘The name of an active-low signal is written with a bar above it to distinguish it from an active-high signal. For example, the name Q, read "Q bat" or "Q not", represents an active-low signal. be. ‘What are different numbering systems used(1M)? Convert following numbers to required numbering system (2M each) §) (11001011.01110): = (re i) (1100110.011010): = ()is ‘A numbering system is defined by digits or numerals. According to the requirement these digits can be arranged in a particular sequence. Based on number of digit identified by a numbering system, there are following numbering systems Decimal — identifies 10 digits 0 to 9 — used in general. Binary —identifies only 2 digits —0 and 1 —used by computers Octal — identifies 8 digits — 0 to 7 —used in codes ‘Hexadecimal — identifies 16 digits 0 to 9 and A to F. — used in assembly language programming. Conversions — i) — @1001011.01110): #) __(1100110.011010) 203.4375)10 102.40625):6 What are codes? (IM) Where are they used? (2M) Differentiate between weighted and non weighted codes. Give one example of each. (2M) 18 Codes Got “message keeps your information secret, lore est me sek stow bn anIS To use Codes: @) To allow computer to: perform fant scientific calculations Tike: add, robirac, vision, ‘multiplication, Jog, antilog etc. at high specd and with more precision, one shonld use lest HARDWARE. Therefore, we should have the codes which pres youll mathematical eslextations swith less mimber of steps. 2) Incomputers (digital system) we nse fork of binary mazes for theit imma operations, bat the 2xtemal world is decimal in mature. It means that conversion from inary to decimal and vice “versa.are performed often. We lee seer that the conversions berwern decimal and-biaryCa ‘become Tong and complicated for Tange mimbers For ths reason, 9 means of encning deca _mumbers that combines some features of bot, tbe decirat and binary system ts required, B) Computer also deals with Nor-mumerical Information tke: nats and ber alphabet, special: characters as well as oumibets. To allow computer to handle all these non-ramerical Jnformation, we have to-have codes. The codes which represents nom-muosncal information a. called-alphanumerie: Codes. Presently 4 seas wlkng abou coniputrs User can hae'one or mare minder of comprierch onpaters, If the user have to ot more number of eomputcr,beshe wi insist tt compres should Comorsincate with cach otter, The media for commutecabon willbe wires, wiles or ber opixs. The graphical presentation is shown in Fig, 113, ee ee, = soneniet Soe eee a soem, ee | Seon en ere ee paseo | Rise tiene ane eae Problem Unt ee sn a tt SSSI ees Seton een netstat rien i es Seg ie sso aaNOTE — use of codes can be written in brief. No marks reserved for dig. Weighted Codes ‘Weighted binary codes are those binary codes which obey the positional weight principle. Each position of the number represents a specific weight. Several systems of the codes are used to express the decimal digits 0 through 9. In these codes each decimal digit is represented by a group of four bits. Non-Weighted Codes In this type of binary codes, the positional weights are not assigned. The examples of non-weighted codes are Excess-3 code and Gray code. ‘Explain how negative numbers are represented in binary numbering system. (2M) Discuss properties of 2’s complement.(3M) |_| seo rae ts a SS acm emer coer SRT ee eS a ce ene ne oes oem ema Se ee abe es eng eee "ae Signmmencrs code (SIGN) OR SU repeats pF Cnseionguinnn wencayzs tengieeerniods © peow compe method recommen med) 244 Signed Magnitude Code:(St Representation) = 1 an sr aI nescated BC Oat the let of the mummies tke * LALA ym ~ 3.5 ¥40- “Riis notation op called signed manrstade notation, hectaae magnitude fotlows the sien, The genemiized format 8 shone follow = - Naver B= Bay a Set ‘maeneade 1B BIS \Kettsny ors bitthe orm t= ye Bs Ba By. By Bi Bay sign bis" ‘Magnieas iB Nommitie, Sit 0 —r denotes: postive amber [5 bin= I denotes negative muro: ‘Lets sy represent (+120);9 using SMirepresecention. $20 evlagiadey ~ Byun: By Ct LIDB.O Number is positive x. SbK= 0 2. By=0Be BS ‘By By Be | 2 2 é 4 ° ° ee rec | “fo chante Wom (1240 C13). simply shange Ds oN te 1TH procest 4s eatin Cie > By BeBe eB a a on oe oe ee ee: * ims agai c re want from (124) qo + £26, apsin“aegate By from I t09.S0. i at 1itig ies neetoen a Ox ba bas aes mga CITE DOO Me 120 here 29M means, 21 base. SM —» signed magritude 1411000), (148),9 Consigned maniber ‘CD. Dh est ant operon oper ix 2 code has ane oepetentation af eemm: fRetet Tea 3h So phi nd iin ere te sate: 3 code Til mghes Wt easier fo Beles ero reso a avoid some statment 1) ToSer netatomwe sow tat negative manors awe Agi Twiiteeimnexative mers have size but, Thom the sgn of a.2C number ss aly ven tse leseat Oi. wich mss ne 2:5 arch secondly from the fet that feet Hip Le ones eoniplemnert changes the shen of the ‘umber text Mcp 1c. adaition of 2 chanins the sien of te Member again if seve Say Ia Te eo wee ane SEO Clo HE Be OER alieny sven exon tal foe Bt meted Hae 128). 7 E1S0 yy cnanot st Secondly by cheering 2's comelemencsting aso'weconcinde Le. CL GET LOD, “nig tie nero, xocnnmib has tobe positives bt we ae etn 19044 “+ Rishould comin 1 Becouse'of this we'switched over to 12 Of. 45). Zscomplementat 2 complemented mmbcr tr same. Te stems thet ySuitieve. 2's compiememed snuniber, Sot aesin God'out 2 complemen oF 2C samen. You wall Reconsteeh wala Suv foranexampte: rp =O COO; ‘Vs conplement oC ig i: = st i Say = Ee ee Perform following arithmetic operations after converting the numbers to binary numbering system— i) (10)10 = (4)10@M) i) (727)8— 234)s (2M) ifi) (DADA)s + (BABA)is 1M) Bi) (00 + 4) (10102 + (0100)10 Q=10 R=10 ii) (727)2- (234) (11101011 1)2 - (10011100): (100111011) (473)s ili) DADA)I6+ BABA)IS(HOTOTOTTOIOTOp: + (TOLTTOTOIOLI T0102 (110010101 10010100) (19594)i6 £ ‘Add following BCD numbers i) $6) and (23)10(2M) ii) __ (82) and 4)10(3M) D 0101 0100 + 0010 0011 O11 1001 (79)10 i) 1000 0010 + 0011 0100 1011 0110 First digit is invalid BCD add 6 (0100) (113)10 Attempt any three of the following: 5 ‘Draw logic circuit and make truth table to prove the following Boolean theorems i) A.0=0(2M) ii) (A.B). C= A.B.) GM) i) 2 Ome pet Ree at toe os D~ <1} Fiz a0 ‘Refer Fig. 440 The tea Taste AND p Fenn SINE fA mp at LA ope oar ARS Mas at when-ooe tp Ped 3 pi A920) acs One input Mees at togie 1: Refer Fg. V4 pried Ate of AND sone ts ot tae fvel "Outpt flores amt sms any8) Both impute are having 'F sanmon init OR both inpets ace shied te single variable: Refer Fig 312 Bh IEA 20th me A Leh sae atop ne KALA Pemaketise ot Fig 243 2 Sin denice teeters thts Refer Fig, VE3 Imspectne of sahieel Are loge Wor"V one input wait be ates at W. O1P of AND Ye wilde aluans logic isd i) (AB.C=A.B.0) Associative law. Law "This saaer nthe order in hich te epertion x pb shew a het effet ie ‘same, Foreampleigcsyee x0 goa b. Using rules of Boolean algebra, solve y= (x+z)(@+y+2) GM) Draw a logic circuit using sultable gates to implement the simplified equation. (2M) Yow Ro Kevez) + X-RexvenztReeverze x 2p = Otxy+resRzeyzez Ds wriz[xekeved] ee a XY +ZI=x¥+Z Yesah‘What is meant by universal logic gate? (IM) Draw logic circuits showing construction of Ex-OR gate using NAND gate and using NOR, ite.(2M each) 3.40 _Universal Logic Gates : {tis possible to émplement AND, OR, INV (NOT), XOR. XNOR gatee using one member sets [NAND and NOR Thus, using these gates, one an realize any given logical expression. Asa result Gey are known 25 Universt logic gates. ° De Ex-OR using NAND Ex-OR using NOR F(A.B,GD) = 5 m (0,1,2,5,13,15). Draw k-map M+ IM for grouping) and find minimised Boolean expression.(2M) r . 23 ee ASE. DL SOR HI, 15) rn tamer Bot PrN From cvampic we ea consfage iat K-AIGp rep will af 8vamablet (A,B. C.D) ‘sohelusc can Be also ade up Home highest state, Highest state © 18 TO seprsent (ep end ite Ra al Sera recent Se see Gn ay ee oa spre om ah the box hee ner Spi eam Se j ‘site meRemmtiansboNes of RNG OHNE Re EA ME WH agp goo ep ey No ae0] Reo ae Ax Pip ar a ‘Ane¥ = ABD + ACD + ABD. O21, sia a‘What is meant by don’t care conditions? (IM) Explain how are they used in simplifying an expression using a k-map. (1M) Use the following example — F(AB.C,D) = 5 m (1.4, 8, 12, 13, 15) +d G,14) @M) 4.84 Don't Gare Condition = In togie circuits. or some cases ten hap in tee condiaions wo specie ouput Hxel isdofined Le, HIGH oF LOW. Ths exee maybe prevent ‘these input conditions will never occ In short. there wif be certain combinations of input levels where we don't care whether the cutpet te EIGN orlow. "Normally don’tcare staes-are epecificdthy “a Tor ewatnple say CCA. B.C) Here ‘Ent ig ae weal muntertn, that orsena (Romie OLY ao “€ + dont care condition, In above fection statee'S and Gare dont care, New you will ask how ta repeesent dont care in K-Map’? Usually 8 K-Map we pot 0 (Son care sign ir the Dow whose mumber is specified by the fonectinmaundcr ‘. As far as:cireoit desige- of suciefimetion is concerted yor (he circuit destpnery fs Ie to sake te of don’t eare condition either W-0t"Y, in order te produce sittiplest output expression. Normal \you write SOP form, you normally force dom: care output state to | and for POS form, yon force dont care-ampit state:t0°,, ‘Let's take one example to mnderstand concep clearly 92 FAG © l= Em. 4.8 12 13, 5) SS IH) Sm, in. 2 For this problem we hive drawn two K-Map. The first one dacen't encircles ‘X" (dost cae ition) and other ono encircles the XC. Fig: Ex 19 00) and (@) are the hardware design ‘Fig. Ex. $19 @) (i). shows logic cist for outpyr Y¥. we achieve from Fig. Ex. 419 (a) (D, Tn that #6 9 AND gates and 3 OR svtes Te Fig Ex. 4 19 (9 dd) logic eteult for ouput ¥ derived fom FE GSR ae Saat OE am wee TSE ce, What are disadvantages of k-map? (IM) Explain the Q-M method. (1M) . Discuss the terms ‘prime impeccant’, ‘eode word’ and ‘reduction table’ (3M)Jike Remaps it searches for terms that canter: ott-the fenslike A+ A. x + Fated so om Detret eon ‘explaining yousteps involved. frst we will eam Prime Pmaplicante Prime implicant : Let P00 be a product term ks. Boolean fiction that can be writen nem product of Werte of Ky, {foe the function F (x), the relationship for all_A such that P(A) ~ 1, F (A) 1. holds, tien P te calles srmplicant of F, means P(A} ~ Litaplies P(A) = 1. Ib means that every minicrm of P te sso andntee: F ‘Lets take one example, ‘Let's take one example. ny FOO~ AB 4BC+ ABC + AC ee ic, Asc, ABE, ABC S a ee i Hot_am implicant of F. Prime: implicant is-an éedivisiSte implicant in that it.ccases to be on implicant 3 aoa = ED ase saadsliaie stenleter.n yatta ania a | SSRSer een see main eer aT ee a, 2‘Example not compulsory Attempt any three of the following: 15 A 4 bit binary number is represented by AsAzAvAo where As, Az, Arand Ag represent the individual bits with Ao equals to the LSB. Design a logic circuit that will produce a HIGH. output whenever binary number is greater than (0010): and less than (1000)2. ‘Truth table (2M) K map(IM) equation (1M) dig (IM) ncintioonibinm bt eo EBT fa Hem wen aay or pen a kaa He) ca Ashes RR} 9 ot) FaAgot ye oy a ]ojo Abate | 0 2 nl o lol of %, Feaw diay b Convert 4 bit binary number to 4 bit gray. Draw the truth table, 2M) necessary k-maps(2M) and logic circuit. (IM)‘inputs and one SAW SoHo Se HMC [sonnin ween eer re rr loccroe eae BIG & GG] Janene ie ten enwomen|! pooner wall a Soom HM Oe Gomes Se Seesoe ene aa To prepare a oamn oo me Be ster Decimat |B; By Bs. wl Gray @bits, GG, G, G,) outputs (Refer chapter I for the table), @ ‘Truth tatile is. © Aisi we |) Now the next sop is wery simple. You draw K-Maps for Gy, G,,G, and G, SEPARATELY @ KeNiaps: ie . han = : eS, “EY ie he men, SO Be BBcol o | 3 5E. 4? 12) of Bl elo] ole Beet f. ‘I i Beart sto] tt, J, BB, 40 1) Seo] ef o | «| o | teal Gls st o a i 4043 Sy=By Gys8, 8,43, 8, SBye8, AS DSS REPS S Be] 0 | Bo] e | All A, Bao oily ott Biba a) 8B 8 #4 {fd Pa ft PS a" 2 Design a BCD to 7 segment decoder. (2M) Realize the circuit using NAND gates only. (3M)ARS “Our aim isto, design a cuca whch et sen BED e $048 LOO te ty equate coped COOL T WN dt Sek Fig S38 (a). AS Shown in Fig: 5382, ve tv ‘i ‘i . on 10 ‘lita,), g,¢ and ¢ LEDS, AM others: clare ‘Yon ko that ait LED soi tae o force semmt loge ‘| r . ‘ne examile. Find: 7 segment code for BCD hig be: OID}: Refer | ' % Code of 7 seguienttorBeD 2 ix ® | & Fis S38@) LEDON “Therefore, now wwe Have t prepare truth table whew BCD inpus em 8, BB, B, and autpats area, b, ee 8 gdp. Table 32h tuth table, Decinial | sane wane | Be TR Rl ale lelwleltts o toloafetoftototoietoi sis 1 Glaltoalritzioale tivity is 3 @leatiloloelolajpolel ry » a toleliliatalolotetrtijs) = @laijoeilotaleiopteletolal - eLeltebiiaetatets 7a tele : whi iteiaitaiateteiol oe: 7 wBlisrieLstatetete ts tee “ tlealelotolotelolosf{ ois Tigeiefijotoieselepriojsoo a [ai] ate Fe Note - K maps not mandatory. aims Gi Implement 8 bit adder using 4 bit full adder. Logic dig (3M) explaination 2M"EX. 32” implement @ te ser ang = Benatar Abi atte , ons & &~ BSS La are Ealetedie a as a oe k~ & A Be Reyes uuu y Cee - Be SH Cia connect to ote Co Gainey Operation performed is, “ Bs Ap A, y ha 8 ' Ree oS Bene ee Gji=t) GND BS Sys qs 5% Ts equivatent to, r X he KX poperand 2 a z z x ¥% ‘% operand 2 = f= Ce P 0 S|] 44% % % eae 4 ors Giladder, Fors pn adaey Ets implement some rents using bit adder Blocks Cee aa Draw cireuit(3M) and explain working 2M) of BCD subtractor.36 BCD Subtractor: ‘The 7483 is used as a basic, building block to implement BCD subttector. For BCD-subtraction. ‘nine's complement of the subtrahend is added to the minuend, The nine’s complement of a number can be Found by subtracting the given umber from tine 6), or by adding 10-10 I's complement of given tamber, For example: Find.9’s complement of (2), 9. @y™ O10}; £O, 2OOL -Oy ODIO O11 1 —2Nine'scomplemenot2y,. ‘egen a sine An People sre, Dye Ot veconplement of yg C1OD;—9 (Dio ‘ig —2 10D eee tLe aay OTT F —+Nine'scomplement ot @),,, ‘(don't tke carry into account)Tend Rae a = lider oat lore-caster fo implement therefore most widely used. The.ciront using the same is Fig 62 3.84 ‘Working of Circuit: Take Dz Dy Dy Dy= 100), = Ajo B, Bi, By Bom D,D,DjDy= 100 mrt AAA LOT . # By BB, B—>.Lads seorctany [i] OT OT + Pscomplementorey.ie. ci, _As stated catles to penfom BCD sibtnction, the 9 complement of sabtrahend (operant) is added + the minnend (operand 1), Lets Brst see the BCD ssbuactar circuit Refer Fig. 628. As chown, 4 bitadder; used fo finds complement of operand 2, ‘abit adler, 4 Bibadey provides Simple HED adder crit: a itadder, is used to getanswer introe oom, ‘Write a note on fast multiplier.68.4 Fast Multiplier : As seen\‘in-pfevious topic every’ multiplier bis multiplied with the multiplicand, Also the previous technique fails #f the multipkicand or ‘multiplier is segative. This is because partial product fora negative multiplicand must be negative: One can avoid this: problem by, converting both multistier andl smuttiplicand 10 positive numbers, perform the multiplication and eventually: take tnv's complement of the result only if the Sign of the twororiginal ntsuiberg differed. This cait be zchieved using a technique ‘called BOOTHS ALGORITHM which also spetds up multiplication. The ‘Slowehart for Booths stgorithm it depicted in Fig: 6:29, ‘Consider an-example using Booths algorithm as shown, 6-5 where, Me o-oo Q45 0001000 ator 9 ee TOO piwr 9 ‘Shift 210% OD10 | © setuh. WACASM | Fourshifts asnumberortitein: poay Geka 5 ee ‘oui ae four: 1 19 A ae ‘The MSE bit is copied onto itself Pett igor oO ‘Shite cand shifted Q, bit is always zero. Ol Tiop 4, ‘initially. eee em Fa icedi ave ¥ Stitt fo 0 ed a a One may hostevernise the Boothyaraligtie ‘feooding bles shewnin: ‘Moltiplier bit, ‘Multiplicand selected by | i biti ca oxM ® xm 1 KM i oxM Attempt any three of the following: 5 Implement following function using 8:1 Mux F(AB,CD) = m (2.4,5,7,10,14) ‘Truth table (3M) ckt dig 2M)EXASE edgy ettikungect wae FAB, 0.0) = 3m 2,45; 7, 10,14), D A.B.C,D + tourvariables are present. @) Theretore:n9, of tates will be-2"= 24 16, ) "Make: table which-comains bitsy (0000), 16 (1111) After tat wie dosen OFP Yj. gon want /1. Nokly yo suld wile dow togic in _, OP Y calintn, in the row specified by functioni.e. 2,4, 5, 7,10, 1. © Now go-ongronping 2:stes, «® es Keay observe iD ie ESBY ATOPY. “Contains "O° or "ti . : ee respectively, respective Of D-changes, then-simply: write: down logi - TCO Y isssonve ast of D tit, write‘ fn front of funtion, 1 OM ¥ is complement of D'bit, write, Truth table is as shown in Table f8, Sotn. : Inputs an St e ace Dy Donen D=0,x="D<1,%=9) Bi o ry 1 i B -- 0 I os . Yee logic) % Ban Msrcdccanall DiehenD=0, ¥= 0:01, ¥= 3 i & : 1 a a ‘ a 7 : tte 1 $ , . | ‘GND bogic'o! 7 1 Jot i $f 8 1 ; 5 a i ddd :a ie soe so csrormnrensrormmnnenere mam ‘Circuit diagtam is Shown in Fig. Be. 213 (@), Fig. Ex, 713 @) ‘What are data distributor (demultiplexer)?(IM) dig (IM) explain baste operation of 2 output demultiplexer. (3M) 7.3 __ Demuttiptexer (Data Distributor): Big, EsPentitdpledc x ecacify reverse taf mpeg i. itaceele single input and disbutes aves ‘nil oxipuis, ‘The single inpot should appear over which output fine i decided by SELECT LINES amin tf Mlipleses. th sh, the demipleser takes ene inp dna sures and selecivey ee 1 of Soni channels sts that of multiposition eit, The funetional representation Shown ig. 7. ts datn at ie tnput can te a 10 a pecitcouipul Based in seed tne combination. The relationshi ‘between sclect ines and output lines can be givent92 th. imber of select lines, n= Number of opt fines, Basic 2 Output b fw OTS Beall the basic concept is we -going fo se-AND gate to:pass input data to required-outpu | line, when proper address ( elect line sat abe ip cent oseacee Fy Aine;select tes ‘Status shoud be (O10).. Lets see Fig, 2.5. whens iexer ee Pai t Fig 75 tvhen, S_ =0, AND) is enabled and ¥4.= Dy, ¥, ‘Spy AND2 is enabled and ¥,=0, ¥,=Dix. 424 DemultiplexerSets S; Sy= 00. ANDI is emiifed. S, S, 01 AND'2 Sishibled and so. Fee UR etihe, OF tl scent %.¥-an wie ages, Mie ee L contol IFstobe=0. ¥,to ¥, al wil provide LOW tapat s ‘Outpt Sy 5s x # Yer HY 8 e a Ya Das 6 1 YBa 1 a tn Diy Draw block dig @M)and explain operation of 74180 @M)monolithic 8 bit checker / generator (shat is parity generator 1M)Parity Generator/Checker ICs: ‘Theis are-tifferent types of patty: geneister checker ICs ate avellabie-with.ditMérentinput ‘configuistons ucts bit 4-i of pariiy;generator/checker IGis:74380. acbitieht. A Pes Commonly ised ani standard type’ ‘1hisaa. G+ pefiky geneiat oF checker used'to. detect erroiSin high spied dita tranrnission, ‘oridata Retrieval aystern The figure Below shows tne pin diagram of 74:80 10. ‘This (Cican ke used torgenerate a g:bitiedd oreven parity:cade or it ean beused to checktor: ‘Dd chetien fafity fia obit cede te data bite Grit one parity bi.@_| Explain the need of preset and dear pins in RS flip flop? (IM) With neat block dig (1M) and truth table (1M) explain the working of RS flip flop.(2M)ca S35. Preset and Clear : SipFee Ween pou snpply- ies a ¥ . — "ict, nseme sont itched onthe state Of circuit is-uncertain. Ouipun is set or reset, thot is eis ORS i ne He Deve pen er SEP oc RESET, ‘Theiefore one How to-accontplsh required tritiet condition? Solution, isto use SSE (leo cals dec ea teat Glo led fret essen termi Presetnd Gear inpmiscan ie iven wa a: @) “Snebronism wink CLK (eallet sinctitsiigus Precetfeleary @ Asynchionism with CLR, (alls asynclronous Preseticteat} _Asmnehirgnous Preset and Clear yPrest ey se ~ oa pRrebet (P 3 apo ou ‘enn ap ie - Clear {G3 (OLA) $ceari@y (SREP with preserandetoar b) Syeibat Fig 8.16 —= Suits | zs & = 1 & L® o | 0 x |X of i a i i a AE ® t £ Xx x ses o | t b o 1 LB OR rae a fy tf ‘Table 85+ Truth Table of SR FF ith preset and clesLets aalyse working: (YP, = C= 0. it gives RACE condition, because out of NANDWS = 1, So avoid this condition, @Q P= 1, = 0, Thisis RESET condition of FF. ASC,=0.Q~ I, As inpucto HANDS is P= 1,1 and oniput of NANDI is Q*0. G) P,>9, C= 1, This is SET condition of FF. ASP, 0,Q= 1. Asinput to NANDYist~ 1, @= 1 and outpul'of NANDZ™ I forces: © P= C.~ 1, inthis condition SR FF sets 2s normal arid truth:table matches with’ SR FF ithout presetéclear terial, east escent ee ae aa ‘Write a note on master slave JK flip flop. Fig /836 shows M/S IK FF which is evimbination of re’ clockelt latohes; tists called as Master and second is called as lave. Maser is postively clocked a slaves negatively clocked te. “(> When CLK= Master isactive, save is inactive @) When CLK = 0 Masteris inetive, slave isactive,Tmt, Fig, 8.27 : Symbo} SOUR period rete ‘OUR pe Masteraative: | Slavewesre | atastecactie, (CiKet) | (Cik=0) | (ciK=1) Fig. 829 21etRpaid Shee aaie. 1oLK=0) ‘You sliould remember mainly above to points aitd one more point that wleutever master does, slave pes tt bie fx ret half cycle nf CLK, Working ‘ase? IK=0 Pitvioiisste'Q,=0-0,=4 @ CLE 1, 2 Masteractive, Slave imctive 2 Ouiputof Master FES=Q.-R=Q,. Gi) CLK=0, Masterinactive, Slave active: 2 QQ,Cases SMOKE 1G, = 10, <8) @ CER 1 Mawerdetive: : aap Maer, Roh @) CK 0, estorimatie: Stave aclive ip awe Qe Gina 5.94. changes « CLI, MRsieacive:Staveinnctive ‘Gutpat of Masier, Ss0 Rat Now the stoeiestable as iy ang (i). ar'same: Ava 3 ana NS 3 FF GD Bags wiggerea ik FF s > ae @) IK MasterSave FF » G6) Dake ws FF = @) Master Slave JK FF Discuss various applications of flp flops List applcations 1M explanation of each 1M 8:10 Applications of Hip. Flaps ‘indi nose have‘ sttiated al Soles of eR erates ‘ypes of FF sfiitbels and their inuhctable: itis obviotis't6 Kew the i @), Eliminating keyboard debouncine Each should be briefly discussed. ‘Attempt any three of the following: 15 Explain the working of Asynchronous / ripple counter. Dig 2M working 3 M 9.2 _ Asynchronous Counter: ‘Let's start discussing asynchronous counter, Fig. 9.1 shows genetalized block schematic’ of asynchronous counter: Asynchronous counter is also called as Ripple Counter.‘Feset iog'e (Optional combinational circuit Hig 91 Obseriaticns from Fig, 9, Q) CLE INis given f only one FF. @ Normally Type Fis prefered in tiple counter design, (@) TE yoann states less tain N' Lyon want to stop counter in belween nd restart from" (eset) sat, reset Mngt shone Be sd. { ‘Reset logic is nating bat cstnbinatonat etki. Thisllock i optional @) QO otpievious EF ghenttonedt RR, EC ine esol iain Met cover is calledas fispleéonater. Design mod — 4 regular sequential synchronous up counter using T FF State dig 1 M logic dig 2M waveforms 1M working 1M.S54 Type T Design = ‘ets star designing synchronoie coset ‘using 7: ~ 4 regula Sequential sytvoncus up Counter Uahg T= ‘Soin: (No, otstits 04 for mod eomce. @) Reguliriwans n= N, © Noort rreqatea wittheyeat 2. Sequéndi and yp means 4,2, 5 (9) s siedingram ska Be 9.600. Figs 26@) @ FF Aandi Barewet Gand G, @ fm] Hig. BX 9.60) ‘are ontput ftom conibinationt circuit to provide proper input vo % Lhe as shown in Fig, Ex. 9,68). Epa eeao ‘Avtemains constant 8 Q, toggles fom 0 -¥ de . 5: AB=OL @ At CLK eige,as T, =] ecuseB = thondlT, = 1, Aand B both -will toggle, giving 7 2 AB=10@ aa a SI" CLK edge, =0 ae ~Oanlt, «1, B= toggle CUR edge, T, Soe deme from 130, 2 ABeO0 eae + 0) and (5) wit contin ill CLK is present andl counter genomes required ection nsrmene Savonrenneane ere ee te oe Here you MAY HAVE DouRT ATS Laat a cad DOUBT OF QUERY sehen CLK cigs it chang om + The answer for the doubt is B changes f it rom 9 > 1 after propagation delay of 1 FF, then it gets ed down aa ater that signal is capable io iogete A. Ba lH aus seed © CLE ge shneson me because cages are sharp and of shor dumtion, A camo toggle depending upon newt state of B Shanges according to previos sat of B. This point very vere immomtan. ‘Write truth table for mod 6 counter in IC 7492. Block schematic 1 M explanation 2 M state table 2M 9.42 IC 7492: IC 7492 is FLL, MSI divide by 12 counter, TC 7492 is Having 2eoumteriside'A, mod. 2° 2)'and mods (+6)-counter,, 2+ Conibination of botti gives26™ 12 + + 12:counter, Block schemati¢ of IC. 74922‘Fig. 920 Shows block sGhematie ‘B.(Observe sequence carefill state 3 input No. FIG ‘A92. Formod 6 counter 16 7892 counts Homo. 128 Le isabsem). Ll fal tel eer el WyaHB UNG UNG? NG’ “Moe Fag Aly. Fin 921) Soln. :49)"Tnuth tabte O€1C 7492 for mod G counter. As ave knows icemaly {C hosed 2 and mae 6 ‘counter So use Oily mod 6 eounter. CL IN ges to Inge Band oxtts See Q, Qe Q, ons. Sate ae as'shown in Fig: Ex, 9.2460) Chk edge | @5 [Qe] Gp Basins eehatent m ya | a] o @ ee pele] a 1 am bei el @ ? a 4 oe filed a 3 i I 1 6 et oj 0 0 o Fig. BLDG Explain the difference between serial shifting and parallel shifting of data in shift register. Retidcrisxjgrop/otwetory element tt work ogeher as sont Reser singly dora bieay ‘Tro Whe register accepts parallel date and ompors parallel daa: the sme is referred ac Parallel register & Baller register. Nout shift register, iis aathing but memory element. with faci of shifting left and- ‘gt, bit by: Bit. Before going deep into shift vepter, lets see structure of buffer reser.‘One more method of loading or sifting the data is walled Serial Shifting. ‘What do you mean by sertat 2 . 7 ‘Serial: means Wit. by bit-data flow, setialy, om single ‘ine, Sell lite anon ange titen eaters Serial -25in paalet loading: The seval Siting canbe represnied ~ UF neal Block Schematically, ax shown inFig. 103, an f Site tide i eansred tx register and suai dati bit is take out, through vegister A group of Figtos connected to provi: sera! ouf, when seiiat taputis given, iscalled Stef "Baccally if you see; lending parle data is mach faster than ie sexi. Secondly, normally ge wt swith 8 bit, 16 bit, and 52 bit parallel data bits. So onescu ask; why you think: of serfal date?) answer for the question is very simple, If yom see, uptit now we are fooking of Joading the registers, nowvthink of fouding-or transmitting date at distantend. ‘Fig. 10:4 shows parallel and-seris! ¢ ‘transmission. totes sbi == |Last = Ther mn (@) Parallel data transmission (0) Serial data transmission Explain how sequence generator cireuit works.(3M) Explain with one example. (2M)OZ Shit Registy 1+ Sequence Generator Pulse Generator Block schematic structure is shown in Fig. 10.17, Fig. 1017 Basically sift register sequence generator contain basic two Blocks: © ‘N’bitshit register (S1PO type) ® Combination fogic revit. Combinations) logic circuit has input Qy_ 10 Q.q. From thisit wil decide, what should be the ne ‘ctial input for shift register block, shouid be generated, ‘30 that new state or sequence will appear. Now + ‘ell take an exansple to design sequence generator. Ex: The following puise tan is to be generated by using a shit roger Explain te slaps designing and draw logic diagram. pulse train... 1071010110 .. ‘Soin. () Observe the pulse tran carefully and you will find that main pulse train, which is repeating, is 1O11¢ ie, .. 10119, 20110, | Main Repeating \@ Calculate nuinber of distinct timing intervals, In short you calculate number of bits of pulse train our casei i, S {10110) £0846... 3) Numiber of FFs-can be given by equation, s < 2Nu1 where N = Numberof FFs, $= Number of distinct timing intervals. : s< 1 6< 2Nz3‘Here we have to find: DEBA will be abt. ‘Same way you find ¥ ésign of combinations cireait: ‘from previous te test, For example let's say ot OP ¥ of conibittional circuit; given-to shift register. so that state changes DCBA = 1611 (4 docimat. shat shontd be-inpat to-shift resister, so that Means sve have raappiy “to input of shift egiter ox in short should be 0 foreach state. The form of table is shown in Fig.10.18%c), $8 shown-in Fig. 1 ‘esionof LSB-column, Seite _| Op | | [Rh Tory r 1 2 we s iar é | & 2 sb eer : we Bd cana Fig.10.18(¢) 18(e), ouput Y of combinational circuit is-again-notling but t bit shifted@ Kap: ‘Valid states: are 14, 6, 13, 10, 8, feniniing states are-dorit-care. states exch to 13, four variable K-Map should'be used, Kees s, = asa. Eee Se Ae oat Note - Any one example ean be used, Write a note on ring counter, y= 1000 4 Q5= 001 ‘Fig. 10.13 : Waveforms for ringcounter \CK edge, with respect to 3" point, bits will shift teft :the bits are shifted left one position per positive st hogs ea le ena : 6 ‘then back to high °F, FF, svill be reser and F, is preset givin) = CLOCK ets. MSB moves'to TSB, Q59Q)):Q:-> Qs,'Q > Q aittQ, 9°), 2 Qj ONI0 CLOCK edge, with respect to 4" point bits-witl shit teft® Wonter ofsues tron “ : ; ‘Let’ write ourpat Q tor 8 bit : Iniany. ead it Sofor 8 bit FFs wilt bensed, '8Y cloceedges,Q. = 9000 0001. Risa, Ikyou require you:can also take output som O, + ford bitRefer Fig. 10:12 Initially when CLOCK =0 Q=0001 =Q= lito Fictockedgs§ = itot CLOCK edgeQ = 10ti 34 CLOCK ctge'Q = ttt ACLOCK edgeQ = 1110 Application : _-Ring counters are invalnablé when itis necessary to contol sequence of operation, ‘Mainly ring counters are used in mi 2