This data sheet is applicable to all ‘TMS44C256s symbolized with Revision *D and subsequent revisions as described on page 5-21. * 262144 x 4 Organization * Single 5-V Supply (10% Tolerance) * Performance Range: ACCESS ACCESS ACCESS READ TIME TIME «TIME OR tap) tac) tac) WRITE (mac) cac) (ca) CYCLE (Wax) (MAX) (MAX) (MIN) TuSs4256-60 Gone 1Sne GOA TONS TWS64C256-70 70ns 18ns —aSNS19078 TwassaC25680 Ons 20ns AONE 150s TMS42C256.10 100s 2505 ASS 160M TMS44C256.12 320 BOne Has 2208 * Enhanced Page Mode Operation with TAS-Before-HAS Refresh * Long Refresh Period 512-Cycle Refresh in 8 ms (Max) * 3.State Unlatched Output * Low Power Dissipation * Texas Instruments EPIC™ CMOS Process * Allinputs and Clocks Are TTL Compatible * High-Rellabilty Plastic 20-Pin 300-Mi-Wide DIP, 20/26 J-Lead Surface Mount (SOU) ((44C256-60 and '44C256-70 Available in $0J Only), 20/26 J-Lead Thin Surtace Mount (ThinSOJ), oF 20-Pin Zig-Zag In-Line (ZIP) Packages * Operation of TI's Megabit CMOS DRAMs. Can Be Controlled by TI's SN74ALS6301 and SN74ALS6302 Dynamic RAM Controllers * Operating Free-Air Temperature -0°C to 70°C description TMS44C256 262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SHGS2S5C JUNE 1006 _ REVISED NOVENGER 19 Package 50 Package (op view) (Top View, par Ves a2 os w Dos RAS cas TF é a0 ro AL a7 Az a6 ag AS. Veo a ‘op View) Vss oa 03 cas ‘TThe packages shown neve are for pout reference only “The Di package is actually 75% ofthe langth ofthe N package. PIN NOMENCLATURE, AOA ‘Adsress inputs oS Column Address Strobe Derpas —OatalnyDala Out é Data-Output Enable RAS Row-Adgress Strobe 1 Test Function w ete Enasle Voc 5.V Supoly vss Grours ‘The TMS44C256 series are high-speed, 1 048 576-bit dynamic random access memories, organized as 262 144 words of four bits each. They employ state-of-the-art EPIC™ (Enhanced Process Implanted CMOS) nology for high performance, reliabil and low power at low cost. EPICS a vacomartol Texts nsiuments Incorporated enantio TEXAS. 2 INSTRUMENTS Compt 1990 Terns Metumers reepared POST OFFICE BOX 1449. * HOUSTON, TEXAS 77001 saTMS44C256 262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY GSe58C JUNE 126 EO NOVEMBER 1250 description (continued) ‘These devices feature maximum RAS access times of 60 ns, 70s, 80 ns, 100 ns, and 120 ns, Maximum power dissipation is as low as 305 mW operating and 11 mW standby on 120 ns devices. ‘The EPIC technology permits operation from a single 5-V supply, reducing system power supply and decoupling requirements, and easing board layout. ioc peaks are 140 mA typical, and a— 1-V input voltage undershoot can te tolerated, minimizing system noise considerations. All inputs and outputs, including clocks, are compatible with Series 54/74 TTL. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility ‘The TMS44C256 is offered in a20-pin dual-in-tine (N suffix) package, a20-pin zig-zagin-line (SD sufi) package, 4 20/26 J-lead plastic surface mount SOJ (DJ suffix), and a 20/26 J-lead thin plastic surface mount SOJ (ON suffix). The TMS#4C256-60 and TMS44C256-70 are avallablein the 20/26 J-lead plastic surface mount SOJ (OJ suffix) only, These packages are guaranteed for operation from 0°C 10 70°C. operation enhanced page mode Page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is thus eliminated, The maximum number of columns that may be accessed is determined by the maximum FAS low time and the CAS: page cycle time used. With minimum CAS page cycle time, all 512 columns specified by column addresses AO through A8 can be accessed without intervening RAS cycles, Untke conventional page-mode DRAMSs, the column-address butfers in this device are activated on the faling ‘edge of RAS, The buffers act as transparent or flow-through latches while CAS is high. The falling edge of TAS latches the column addresses. This feature allows the TMS44C256 to operate ata higher data bandwidth than conventional page-mode pars, since data retrieval begins as soon as column address is valid rather than when TAS transitions low. This performance improvement is referred to as “enhanced page mode.” Valid column agaress may be presented immeciately afte nya) (How address hold time) has been satisfied, usually well in advance of the faling edge of GAS. In this case, datais obtained after tac) max (access time from CAS low). if ta(cay Max (access time from column address) has been satisfied. In the event that column addresses for the next page cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later ‘occurrence of tac) oF ta(cpy (access time from rising edge of CAS). address (AO through A8) Eighteen address bits are requited to decode 1 of 262 144 storage cell locations. Nine row-address bits are set upon pins AO through A8 and latched onto the chip by the row-address strobe (RAS). Then nine column-address bits are set up on pins AO through AB and latched onto the chip by the colurmn-address strobe (GAS). All addresses must be stable on or before the falling edges ot AAS and CAS. AS is similar to a chip enable in thatit activates the sense ampltiers as well asthe row decoder. CAS Isused as a chip select activating the output bulfer, as well as latching the address bits into the column-address butfers write enable (W) The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects the ‘ead mode and a logic low selects the write mode. The write-enable terminal can be driven from the standard TTL circuits without a pull-up resistor, The data input is disabled when the read mode is selected. When W goes low prior to TAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting a write operation with G grounded. ¥ TEXAS. INSTRUMENTS 52 Post orice WOK 443 * HOURTON, TEXAS T7001TMS44C256 262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SMGS?36C JUNE 1906 — REVISED NOVEMBER 1390 data in (DQ1-Da4) Data is written during a write or read-modity-write cycle. Depending on the mode of operation, the faling edge of CAS or W strobes data into the on-chip data latch. In an early write cycle, W is brought low prior to CAS and the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-modity-write cycle, CAS will already be low, thus the data will be strobed in by W with setup and hold times referencedto this signal. na delayed-write o reac: modity-write cycle, G must be high obring the output butfers to high-impedance prior to impressing data on the 1/O tines. data out (001-004) ‘The three-state output butler provides direct TTL compatibility (no pul-up resistor required) with afanout of two Series 74 TTL loads. Data outis the same polarity as datain. The outputisin the high-impedance (tating) state until GAS and G are brought low. In a read cycle the output becomes valid after the access time interval tac) that begins with the negative transition of CAS as long as Ry and tac ar0 Satisfied. The output becomes valid after the access time has elapsed and remains valid while CAS and G are low. CAS or G going high returns it toahigh-impedance state. This is accomplishedby bringing G high prior to applying data, thus satistying ty GHD) output enable (G) G controls the impedance of the output butters. When Gis high, the butters will remain in the high-impedance state. Bringing G low during a normal cyote will activate the output butfers putting them in the low-impedance slate. Itis necessary for both RAS and CAS to be brought low for the output butfers to go into the low-impedance slate. Once in the low-impedance state, they will remain in the low-impedance state unti either G or CAS is brought high refresh Arefresh operation mustbe performed atleast once every eight miliseconds to retain data. This canbe achieved by strobing each of the 512 rows (AD-AB). A normal read oF wre cycle wil refresh all is in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus conserving power ‘as the output butfer remains in the high-impedance state. Externally generated addresses must be used for a RAS. only refresh. Hidden refresh may be performed while maintaining valid data at the output pin, This is accomplished by holding CAS at Vi_ after a read operation and cycling RAS atter a specified precharge period, similar to a RAS-only refresh cycle. TAS-betore-RAS refresh TAS-before-AAS retreshis utlized by bringing CAS low earlier han RAS [see parameter taicLayjal andholding low afer RAS falls [see parameter taicHjAl- For successive CAS-before-RAS refresh cycles, CAS can remain low while cycling RAS, The external address is ignored and the refresh address is generated internally. ‘The external address is also ignored during the hidden refresh option, power-up ‘Toachieve proper device operation, an initial pause of 200 us followed by a minimum of eight initialization cycles is required atter power-up to the full Veg level test function pin During normal device operation the TF pin must either be disconnected or biased at a voltage less than or equal to Voc TEXAS. % INSTRUMENTS POSTOFFICEBOX'449 * HOLSTON. TEAS 7001 53TMS44C256 262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY S6052560 — JUNE 1986 — REVISED NOVEMOEA 1950 logic symbolt RAM 256K x4 —| 2009/2100 a? _ 262 143 ~} 20017/2108 C20[ROW] G23/[REFRESH ROW] 24[PWR DWN] Sp c2iicotumn) G24 23022 24,25EN par 1-9—azap Az | 26 " 1 this symbol is in accordance with ANSVIEEE Sts 9 1984 and IEG Public Pin numbers shown are ortho N package. % TEXAS. INSTRUMENTS 54 rosrortice sox 42 * HOUSTON TEAS TeeTMS44C256 262 144-WORD BY 4-BIT DYNAMIC. RANDOM, -ACCESS MEMORY $066 REVISED NOVEMBER 1990 functional block diagram mas ASW Y Y Y i Timing and Centro! —__| | — Row Asaress ‘Butlers @ 2sex | Row | 256K Array | Decode] Array Sense Ampiiirs « - 4 column <> : Address | — He} wo = sures |] smnbecode Pe] Butters ° eT] Store <>] selection FP pate ] K [>] ou | eg ‘ Sense Ampiiiors 256k | now | 256K Arrey | Decode} Array par-pas absolute maximum ratings over operating free-alr temperature range (unless otherwise noted)t Voltage range on any pin (see Note 1) 1Vto7V Voltage range on Veg : 1Vt07V ‘Short circuit output current... 50mA Power dissipation 1W Operating free-air temperature range 0°C to 70°C Storage temperature range 65*C to 180°C 1 stresses beyond those sted under “Absolute Maximum Ratings” may cause permanent damage tothe device. THs i asress rating only, and ‘unetional operation ofthe device at these c ay atherconstions bayons hose indicated inthe “Recommended Operating Condions” section of th speetieation is nol mpd. Exposure to absolute-maximum rales concitons for extended periods may affect device el ability NOTE I: ailwotlage valves inthis cata sheet are wih respect ogg, recommended operating conditions i WIN WOM MAX UNIT Veo _Supslyvalage ~ 455 55] Vv Vgg Supply volage - 2 v Vint Hah level nputvotage 2a es] v Vii Lowleval nputwatago (gee Nove 2) = oe] _v Ta Operating fee-airtemperawre 2 vol 6 NOTE: The algebeae convention, whore the are negaive (oss postive) Imi is Gosignaled as mma, used ins data sheet Tor opie votage levels ony, TEXAS, % INSTRUMENTS 55TMS44C256 262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY ass fe JUNE TH98_— REVISED NOVEMEER electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted) THEAAC256-60 | THSGACIS6 TO NT PARAMETER. TEST CONDITIONS —ee Vou Fighieveloupa votage [ign = 6ma ~ 24 za pv Vou tow-ieve! ouput vorage [log =42 mA oa wap TL Toputeurert eakage) [Vi « 0105 8V. Voc = SV. Alotherpns = Oia Veo 210 710] WA 1g Ouput eurert jenrago) | Vo = OV 10 Voc. veo = 55¥, CAS hgh a0 =o] ya IgG Readiwnte cle curent | teygay = minemum. Vog = 85 35 @o| ma ToceStanaby curent Aer 1 memory eye, BAS and CAS Tigh, Vwi = 24V 2 2 [ma ceca Average ratesh crcot]iguaiy = miniTWm, Vog = 85V, RAS oycing, CAS high ww (co (RAS ony. or CBA) _|(RAS-ony. RAS low, ater CAS low (CBR) * etm Taga Average page current ['gip) = minimum, Voc = 55 V, RAS low, CAS open 7 al mA Test "TS ) <— tw) 2 tact) — Met tac) ——> 1 amen —a (TT ones es Py ot | Po wie vm CAS : N toy te + 7 * rot bie pina $+ tevicay Hep ton, Baie * "a(CACH) asec to > tema) Me tatcamny — mica = EOC CRETE . Ht fons se thy erie 4 tnictee) wor ——— vu w Rr oonnewe Roy | SD Bon Care RXR Annas ! ste) BABAR vn * aca) ~ 6 ‘asic » taciz) Z v 001. mez {see Note 17) a co : v / on « tary > 4 ta) <> tas) Sc vm é vi NOTE 17 Ouiput may go from high-mpedance ta an invalid data sate pi tothe specified access time Texas INSTRUMENTS 512 Post OFRICK ADK 4 * HOUSTON TEXAS 7001TMS44C256 262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY MOSSE ~ JUNE 1366 REVSEO NOVEMBER 1260 early write cycle timing eto, a _§_§_{— ‘<— wre —— I — 1 Vim Aas N : \ vu um “ Teyeuny He try) te— taucty) —r — tach) —> = — sayrcny mrs <——— wer, ——* | ts CAS i 1 Q Yi ern ‘ teu(cay <—— wer, ——— . taupe) sek \e——- tayeacin. ———>} ‘wna Ph ee ‘acai, ———— i t * ie ten) 1 1 iti i oa 20.08 & Row XX column ER Sree BX p > \ “ rca) ie thoes ! | * [= tsuowcty, ————4 \ $1 teuewat) ———- $< trum ——» i te thicww vee TTT +> tsuqwer) ! SHOOT NIT MH Ww » OO OO * oe SON BERR RRR osc SOR RAR 1 +<——"“wmy ——> $n ie fs) > thoy > Ban. Soo OS ai 8%) Farr ee ERRNO , ON Don Core ON xy ERO x SONS is Ban Ete Ket TEXAS 4% INSTRUMENTS Post crFIce BOK 1449 * HOUSTON, TEXAS Tee) 543TMS44C256 262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY Suesesec— NE IEVISEO NOVEMER 1950 late write cycle timing — tare) —% re truce ri ! wo) 41 | v 1 vie os ' \ ft , } i Lt fit {ve | dé tatea) | | +—— twee) ——— 1! tycn lea | ty ttyeacwy ———— teva) > et 1 M4(CARK) ———- Tr sy eeeeee eae eee ee eee Vin sons OX Row ey ‘cowmn | RRR Bont Gare wet. eae iat ren —e | ‘antes '<¢—_—— teu(wRh) ————» LT PL ERK E RRA 1 EXKKRKKK KY BE Key RN iH SE Re LEER EE RONAN ' tego) 4 — town) —) thoy | << thar > TUTTTUKT KK, MH! YOK "Sai SRR ek Che SR AoW Vo. vn TEXAS »% INSTRUMENTS ou POST OFFICE ROK443. + HOUSTON FEXAS 77001TMS44C256 262 144-WORD BY 4-BIT OYNAMIC RANDOM-ACCESS. MEMORY MGReS06 ~ JUNE 1508 ROVENBER 1200, read-write/read-modify-write cycle timing $$ tetr'00) aS \ 1 h ' 1 I Mie wet << tweety) ——> +$—$—>— wan) ! —taccty —> \ itr te(cHAL) > ! ’ \ } ung RL 4 — wey — tsu(RA) — + Isu(CA) w( ees ath, 1 > nica r" y Min a tarry 1g 9 sauce te — toutes —> a sala) ; i | 1 tgcawey —— idem) ——_P, tac) > Her tev tac) —> 1 keto tac oa. Veceecccarensrenevcet ial Cs ‘eeenow 7) NYY ORR cea ee nD i <4 <4 * 0 news fet) 0 f Fe ton) | RETR RRR eel NOTE 17° Output may go trom high-mpedance to an invalc data sate pror tothe specified access tne 6 TEXAS, %y INSTRUMENTSTMS44C256 262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY 'SUOS2S5C —- JUNE 1996 REVISED NOVEMSER 1900 enhanced page-mode read cycle timing tanto) —+———»_ | ie— tacLaHy) —> | fe twice) > fe ma} se tachrL) > | 1 se tacaciy > 4 tacann) ~—> 1 ! | ee Meiteinay oe se tu 7 tyajog om i + 1 Column Tantcay of —_— ae se — ts) —L ! i cre) i nag, wae 1 L wo——4 | ! + Mi I I tyca) > ! he tess Meee iy) | : ar) em fe tate ‘acy (eset 10) ' a (see Note 1 (see Not ‘On par. {eee Note 17) SEA | Valid Out 1 Xion / ‘ +— ta) + 1 be tag) > : ee «Hane EXO BOERS specifications are not violated 19. Access ime is tgiGP) oF a(Ca) €ependont ® TEXAS INSTRUMENTS 516 POST OFFICE ROX 449 # HOUSTON TERAS 7700TMS44C256 262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SHGS236C — JUNE 1986 — REVIEEO NOVEMBER 1290 enhanced page-mode write cycle timing $a ———— te) —__} ' ’ \ ' | + tarucly ——— | two) tact) > | it two 1} kann, - ! ; vm os i 1 of ; i! 1 ty Te He teu fl 1 | 1 ee cat | Me tacacty | a | Bete |e tony tearing my vi vn i tanca) — > I ‘ 1 «§———tmruwy ——+-» | tegen) He ' ' fe taucyor) fe teugway > SXOTREREETERI, | _UTRETEETRRY LEER EE RN _ ASTER ee 0) —— 00) pl i oeetay wank Ae oe gy i tsu(D) ———¥¢—_—_ 1 I ee eae na RN SRR x vin & RE Sse 7 NOTES 20. A road cycle ora read:masity wie cyclo can be intermixed with he wrt cycles as long as the read and read: moaiy write tming specifications are not visited 2. Roterenced to GAS or W, whichover occurs last TEXAS, % INSTRUMENTS POST OFFICE BOX 449 * HOUSTON, TEXAS 7001 87TMS44C256 262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SMGSZ56C — JUNE 1986 — REVISEO NOVEMBER 1990 enhanced page-mode read-modify-write cycle timing tat) ree $ret $a" - } von ras N a ' Mu Say = tarmtcty + teeny I Vn as T Ke cu —_ 1 I Mn Vin a rons BOX row “i vi es jgerrersie " weno \ 1 tawcam >| PL nes ee gk tac e— tyre) ——>, 1 i 0 SER ° a Mn Pe et! i ! sua) > | t+ tacp) > <> th I fae cP) nOWLGL) Vom fem “Aw | | — tay i! i i ' ' Dar. : Min Vow = sou" 4 ; | VLvo. Meta) | tty ! i | > fe tage) | me tan) | a SRNR ; Vin 3 OR RN ve NOTES:17. Output may go fom high-impedance fo an invalid data state ria to the spectied access me 22, Atwadrwntocyciocan beintormixed with ad-mady-wrka cycles asiong.astheread andurie timing specticaions sre not violated y TEXAS. INSTRUMENTS 518 POST OFFICE BOK 1443 * HOUSTON. TEXAS 77001TMS44C256 262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SMOSSECC + LUNE 1908 + REVISE NOVEVBER 1350 RAS-only refresh timing << ter) ——___» be twenty aK Y i ‘ vo ras. N fi \ \ ! vn tacuny) —4—> | — wert) — a se teennicun von us ve fauna) ——> | ne f ‘ Vin Be ee ~ 1018 RTE, te RR : vn Vie ny Vin You oat. SURRA MME Bae LR RIKKI RI KKK RIREAR Oe FERRARO RRA wi vor o Vr Ty OT VN TERE ry I PRO COTTA EReeeccoconeeeneoneeonenens oh TEXAS % INSTRUMENTS POST OFFICE BOK 4D * HOUSTON. TEXAS 77001 518TMS44C256 262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SMGSZ56C__ JUNE 1996-_ REVISED NOVEMBER 1950 hidden refresh cycle (enhanced page mode) H— Retresh cycle —™ ¢— memory Cycle ae ‘¢— Retresh cycle aa je ——>— wir, i tir 1 « Pity | er try | ! ; | ve ie tty nn a os tN! Vs tou) | : LEE Den eS sone Dy ERR ec Mn GREENE vi TRS N MNS Neti ca i ee wea) oe a ‘aiaccy or. Yn Vou ea f Valid Date } . YiL/Vou He tao) <— terete) —> oT AEE ® TEXAS INSTRUMENTS 520 Post orrice nox 449 + WOUSOH, TEXAS T7ONTMS44C256 262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY ONE 1805 REVRO NOVEWER T3e0 automatic (CAS-before-RAS) refresh cycle timing ¢§ terra) > i p ee * _ ms Of \ / ' . we wencur tg y tacanye 4) raven - vm ons ! \ vn wn 0a Oncor NN TERRORS rete we vn ar. wz oo Yn z Min & x ‘Don Care ON ve 7 vi w ‘Don't Core °° STR cer se a 2 we device symbolization ss 7 ssacasen | vscrge con —| | neo FDP KL ON» Thingou 1 | Water Fab Code Revision Code Lot Trace Speed (20, TEXAS 4% INSTRUMENTS sr orrce wx 4 * HOUSTON, TES 70 22