CMOS Digital VLSI Design - - Unit 4 - Week 3 https://onlinecourses-archive.nptel.ac.in/noc19_...

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Unit 4 - Week 3
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Certification exam Assignment-3
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Course As per our records you have not submitted this Due on 2019-03-20, 23:59 IST.
outline
assignment.

How to access 1) In a SPICE netlist statement .dc V2 0 1.8 .01 what does .01 signifies 1 point
the portal
Applied DC bias
Week 1
Applied AC bias
Week 2 Increment in DC bias
Increment in AC bias
Week 3
No, the answer is incorrect.
SPICE
Score: 0
Simulation-II
Accepted Answers:
Combinational
Logic Design-I
Increment in DC bias

Combinational 2) In SPICE, a sequence of nonlinear operating points calculated while sweeping an input 1 point
Logic Design-II voltage or current, or a circuit parameter is termed as

Combinational
DC Analysis
Logic Design-III
AC Analysis
Combinational
Logic Design-IV DC Transfer Curve Analysis
Quiz : Noise Analysis
Assignment-3
No, the answer is incorrect.
Solution for
Score: 0
Assignment-3
Accepted Answers:
Week 4 DC Transfer Curve Analysis

Week 5 3) For a static design, which of the following statement is true? 1 point

Week 6 The gate output is connected to either power or ground

The gate output is connected to both power and ground
Week 7
The gate output is connected to power only

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1 of 4 Thursday 20 June 2019 05:35 PM

CMOS Digital VLSI Design - - Unit 4 - Week 3 https://onlinecourses-archive.nptel.ac.in/noc19_...

4) For a NMOS (threshold

Powered by voltage = Vtn) based pass transistor based AND logic, 1 point
Interaction
Session when both the gates are on, then for an input equal to 1 (equivalent to VDD) , the output
is

VDD - Vtn
2(VDD – Vtn)
VDD + 2Vtn
VDD - 2Vtn
No, the answer is incorrect.
Score: 0
Accepted Answers:
VDD - 2Vtn
5) For a NAND-2 logic, if the widths of the pull down NMOS transistors are 1 point
doubled, then assuming no change in the load capacitance, the high-to-low propagation
delay (tpHL) for input vector (1,1) is

Unchanged
Reduced by two
Increased by two
Reduced by eight
No, the answer is incorrect.
Score: 0
Accepted Answers:
Reduced by two
6) For an RC switch model, with the on –resistance of each device as R and the 1 point
intermediate load capacitance is C, the delay is then defined as

0.69 (R/2) C
0.69 RC
1.38 RC
1.38 RC/2
No, the answer is incorrect.
Score: 0
Accepted Answers:
0.69 RC
7) The propagation delay is a ______ function of fan-in 1 point

Linear
Parabolic
Quadratic
No Relation
No, the answer is incorrect.
Score: 0
Accepted Answers:
Quadratic
8) For an optimised 3-input NAND logic, if the gate size for the three NMOS are 1 point
M1, M2 and M3, where M1 and M3 are the transistor closet to the ground terminal and
power supply respective, then the optimised delay condition is given as

2 of 4 Thursday 20 June 2019 05:35 PM

CMOS Digital VLSI Design - - Unit 4 - Week 3 https://onlinecourses-archive.nptel.ac.in/noc19_...

M1> M2> M3
M1> M2 = M3
M1< M2< M3
M1> M2 = M3
No, the answer is incorrect.
Score: 0
Accepted Answers:
M1> M2> M3
9) For a 2-input NOR logic, the transition probability for zero to one transition 1 point
assuming equal probability of 0 and 1 is given as

5/16

3/16

7/32

5/32

No, the answer is incorrect.

Score: 0
Accepted Answers:
3/16

10)For reduced dynamic power dissipation, in a series network, it is recommended 1 point

to _____ the highest transition input in the network

Put Early
Delay
Does not affect
Delete
No, the answer is incorrect.
Score: 0
Accepted Answers:
Delay

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CMOS Digital VLSI Design - - Unit 4 - Week 3 https://onlinecourses-archive.nptel.ac.in/noc19_...

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