Intel® Pentium® and Celeron®

Processor N- and J- Series

Datasheet Volume 2 of 3

For Volume 1 of 3 refer to Document ID:334817

For Volume 3 of 3 refer to Document ID:334819

January 2023
Revision 006

Document Number: 334818

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Contents
1 SoC Address Map .......................................................................................................5
1.1 Root Spaces sup ................................................................................................. 5
1.2 Super Set Architecture Definition........................................................................... 5
2 Host Root Space ........................................................................................................6
2.1 Host Memory Address Space ................................................................................. 6
2.1.1 Host Memory Space Address Decode and Routing ......................................... 7
2.1.2 Abort Handling......................................................................................... 8
2.1.2.1 B-Unit Abort Handling.................................................................. 9
2.1.2.2 IOSF Abort Handling.................................................................... 9
2.1.3 Low DRAM Address Range (0 to (TOLUD - 1)................................................ 9
2.1.3.1 Legacy Video Area (A_0000h to B_FFFFh) ...................................... 9
2.1.3.2 Expansion Area (C_0000h to D_FFFFh) ........................................ 11
2.1.3.3 PAM Memory Area (E_0000h to F_FFFFh) ..................................... 11
2.1.3.4 Protected Memory Range (PMR-L: programmable)......................... 11
2.1.3.5 DMA Protected Range (DPR: Programmable) ................................ 12
2.1.3.6 TSEG SMM Range (Programmable).............................................. 12
2.1.3.7 Graphics Stolen Memory (Programmable) .................................... 12
2.1.4 Low MMIO Address Range (TOLUD to 4 GB) ............................................... 13
2.1.4.1 PCIe Memory Mapped Config Range (Programmable) ..................... 13
2.1.4.2 Host Bridge.............................................................................. 14
2.1.4.3 Integrated Graphics Device (IGD) ............................................... 15
2.1.4.4 I-Unit ...................................................................................... 16
2.1.4.5 LPC Generic Memory Range........................................................ 17
2.1.4.6 CRAB_ABORT (0xFEB0_0000 to 0xFEBF_FFFF).............................. 17
2.1.4.7 IOAPIC (0xFEC0_0000 to 0xFECF_FFFF) ...................................... 17
2.1.4.8 HPET (0xFED0_0000 – 0xFED0_33FF) ......................................... 18
2.1.4.9 TPM (0xFED4_0000 to 0xFED4_0FFF) .......................................... 18
2.1.4.10 TXT (0xFED2_0000 to 0xFED3_FFFF)........................................... 18
2.1.4.11 TPM (0xFED4_1000 to 0xFED4_3FFF) .......................................... 19
2.1.4.12 xHCI.DBC (0xFED6_0000 to 0xFED6_0FFF) .................................. 19
2.1.4.13 Local APIC (0xFEE0_0000 to 0xFEEF_FFFF) .................................. 19
2.1.4.14 IAFW (BIOS) (0xFFXX_0000 to 0xFFFF_FFFF) ............................... 20
2.1.5 High DRAM (0x1_0000_0000 to (TOUUD - 1))............................................ 22
2.1.5.1 Protected Memory Range (PMR-H: Programmable) ........................ 22
2.1.6 High MMIO Address Range (TOUUD to 0x7F_FFFF_FFFF).............................. 23
2.1.6.1 Other Ranges in High MMIO Address Ranges ................................ 23
2.2 System DRAM Address Space.............................................................................. 24
2.2.1 Physical to System DRAM Address Mapping................................................ 24
2.2.2 Case 1: 2 GB DRAM. Minimum 1 GB PCI MMIO ........................................... 24
2.2.3 Case 2: 8 GB DRAM. Minimum 1 GB PCI MMIO ........................................... 25
2.3 System Management Mode (SMM) ....................................................................... 25
2.3.1 IAFW Programming Restrictions ............................................................... 25
2.3.2 SoC Internal Enforcement of SMM Protection.............................................. 26
2.3.2.1 CPU WB Transaction to an Enabled SMM Address Space ................. 26
2.4 I/O Space ........................................................................................................ 26
2.4.1 Fixed I/O Ranges: Decode and Routing ..................................................... 27
2.4.2 Variable I/O Ranges: Decode and Routing ................................................. 29
2.4.2.1 Integrated Graphics Device (IGD) ............................................... 30
2.5 PCI Config Space............................................................................................... 30
2.5.1 Configuration Mechanisms ....................................................................... 31
2.5.1.1 Standard PCI Configuration Mechanism........................................ 31

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 2.5.1.2 PCI Express Enhanced Configuration Mechanism............................31
2.5.1.3 Type 0/Type 1 Configuration .......................................................33
2.5.2 ACPI Mode .............................................................................................33
2.5.2.1 Hybrid ACPI Configuration Object ................................................33
2.5.2.2 Fixed ACPI Configuration Object ..................................................33
2.5.2.3 IOSF2OCP Bridge ACPI Mode ......................................................33
2.6 Funny I/O Space................................................................................................34
2.6.1 RAVDMs ................................................................................................34
2.6.2 FunnyIO Address Ranges .........................................................................34
2.7 IOSF-SB Private CR Space ..................................................................................35
2.8 PCI Devices ......................................................................................................36
2.9 System Memory Protection..................................................................................36
2.9.1 PMR-L and PMR-H ...................................................................................36
2.9.2 B-Unit Isolated Memory Regions (IMRs) .....................................................36
3 CSE Root Space ........................................................................................................37
3.1 CSE Memory Address Space ................................................................................37
3.1.1 SoC System Agent Decode and Routing .....................................................37
3.1.2 Abort Handling .......................................................................................37
3.1.2.1 B-Unit Abort Handling ................................................................37
3.1.2.2 IOSF Abort Handling ..................................................................38
3.1.3 Fixed Positive Decode Ranges...................................................................38
3.1.4 Programmable Positive Decode Ranges ......................................................38
3.1.4.1 Dedicated PCI Functions.............................................................38
3.1.4.2 Switchable PCI Functions............................................................38
3.1.4.3 DRAM as Peer Address Ranges ....................................................38
3.2 System DRAM Address Space ..............................................................................39
3.3 I/O Space .........................................................................................................39
3.4 PCI Config Space ...............................................................................................39
3.5 IOSF-SB Private CR Space ..................................................................................39
3.6 PCI Devices ......................................................................................................39
4 Register Access Methods..........................................................................................43
4.1 I/O-Space Register Access Methods......................................................................43
4.1.1 Fixed I/O Register Access ........................................................................43
4.1.2 Variable I/O (I/O-Referenced) Register Access............................................43
4.1.3 PCI Configuration Register Access .............................................................44
4.1.3.1 PCI Configuration Access—CAM: I/O Indexed Scheme ....................44
4.1.3.2 PCI Configuration Access—ECAM: Memory Mapped Scheme ............45
4.2 Memory-Space Register Access Methods ...............................................................46
4.2.1 Fixed Memory-Mapped Register Access ......................................................46
4.2.2 Variable Memory (Memory-Referenced) Register Access...............................46
4.3 Apollo Lake SoC IOSF-SB Bus Access....................................................................46
4.3.1 IOSF-SB Register Addressability ...............................................................47
4.3.2 IOSF-SB Access Mechanisms ....................................................................47
4.4 Register Field Access Types.................................................................................47
4.5 Alternate Access Mode........................................................................................50
5 MCHBAR...................................................................................................................51
5.1 Registers Summary............................................................................................51
5.1.1 Noncached Region Control (B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset
6B60h ...................................................................................................51
5.2 Registers Summary............................................................................................52
5.2.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1000h.................................53
5.2.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1008h .............................55
5.2.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 100Ch .............................57
5.2.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1010h .............................58

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 5.2.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1014h ............................. 59
5.2.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1018h ............................. 60
5.2.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 101Ch ............................. 61
5.2.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1020h ............................. 62
5.2.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1024h ............................. 63
5.2.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1028h ............................. 64
5.2.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 102Ch...................... 65
5.2.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1030h ............. 67
5.2.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1034h ............. 68
5.2.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1038h.................................... 71
5.2.15 D-Unit Scheduler (D_CR_DSCH)—Offset 103Ch .......................................... 73
5.2.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1040h ............................... 74
5.2.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 104Ch ...................... 76
5.2.18 Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1050h..
77
5.2.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1054h ................ 78
5.2.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 10A4h ................................... 79
5.2.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset 10ACh ................. 80
5.2.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 10B0h............ 80
5.2.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 10B4h ............................ 81
5.2.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 10BCh ...................................... 82
5.2.25 Major Mode Control (D_CR_MMC)—Offset 1124h ........................................ 83
5.2.26 Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1128h
84
5.2.27 Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 112Ch
85
5.2.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1130h ............................ 86
5.2.29 Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1134h . 86
5.2.30 Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1138h . 87
5.2.31 Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 113Ch . 88
5.2.32 Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1140h . 89
5.2.33 Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1144h . 90
5.2.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1148h .................................. 90
5.2.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 114Ch .............. 91
5.2.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1154h........... 93
5.2.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1180h ......... 94
5.2.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1184h ................ 95
5.3 Registers Summary ........................................................................................... 96
5.3.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1200h ................................ 98
5.3.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1208h ........................... 100
5.3.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 120Ch ........................... 101
5.3.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1210h ........................... 102
5.3.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1214h ........................... 103
5.3.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1218h ........................... 104
5.3.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 121Ch ........................... 105
5.3.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1220h ........................... 107
5.3.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1224h ........................... 108
5.3.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1228h ........................... 109
5.3.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 122Ch.................... 110
5.3.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1230h ........... 111
5.3.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1234h ........... 113
5.3.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1238h.................................. 115
5.3.15 D-Unit Scheduler (D_CR_DSCH)—Offset 123Ch ........................................ 117
5.3.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1240h ............................. 119
5.3.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 124Ch .................... 120

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 5.3.18 Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1250h .
121
5.3.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1254h ............... 122
5.3.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 12A4h.................................. 123
5.3.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset 12ACh ................ 124
5.3.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 12B0h .......... 125
5.3.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 12B4h .......................... 126
5.3.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 12BCh..................................... 127
5.3.25 Major Mode Control (D_CR_MMC)—Offset 1324h....................................... 127
5.3.26 Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1328h
128
5.3.27 Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 132Ch
129
5.3.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1330h........................... 130
5.3.29 Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1334h 131
5.3.30 Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1338h 131
5.3.31 Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 133Ch 132
5.3.32 Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1340h 133
5.3.33 Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1344h 134
5.3.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1348h................................. 135
5.3.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 134Ch ............ 135
5.3.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1354h ......... 137
5.3.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1380h ....... 138
5.3.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1384h............... 139
5.4 Registers Summary.......................................................................................... 140
5.4.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1400h............................... 142
5.4.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1408h ........................... 144
5.4.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 140Ch ........................... 145
5.4.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1410h ........................... 146
5.4.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1414h ........................... 147
5.4.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1418h ........................... 148
5.4.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 141Ch ........................... 149
5.4.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1420h ........................... 151
5.4.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1424h ........................... 152
5.4.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1428h ........................... 153
5.4.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 142Ch .................... 154
5.4.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1430h............ 155
5.4.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1434h............ 157
5.4.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1438h .................................. 159
5.4.15 D-Unit Scheduler (D_CR_DSCH)—Offset 143Ch ........................................ 161
5.4.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1440h.............................. 163
5.4.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 144Ch .................... 164
5.4.18 Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1450h .
165
5.4.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1454h ............... 166
5.4.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 14A4h.................................. 167
5.4.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset 14ACh ................ 168
5.4.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 14B0h .......... 169
5.4.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 14B4h .......................... 170
5.4.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 14BCh..................................... 171
5.4.25 Major Mode Control (D_CR_MMC)—Offset 1524h....................................... 171
5.4.26 Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1528h
172
5.4.27 Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 152Ch
173

6 334818
 5.4.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1530h .......................... 174
5.4.29 Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1534h 175
5.4.30 Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1538h 175
5.4.31 Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 153Ch 176
5.4.32 Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1540h 177
5.4.33 Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1544h 178
5.4.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1548h ................................ 179
5.4.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 154Ch ............ 179
5.4.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1554h......... 181
5.4.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1580h ....... 182
5.4.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1584h .............. 183
5.5 Registers Summary ......................................................................................... 184
5.5.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1600h .............................. 186
5.5.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1608h ........................... 188
5.5.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 160Ch ........................... 189
5.5.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1610h ........................... 190
5.5.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1614h ........................... 191
5.5.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1618h ........................... 192
5.5.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 161Ch ........................... 193
5.5.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1620h ........................... 195
5.5.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1624h ........................... 196
5.5.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1628h ........................... 197
5.5.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 162Ch.................... 198
5.5.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1630h ........... 199
5.5.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1634h ........... 201
5.5.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1638h.................................. 203
5.5.15 D-Unit Scheduler (D_CR_DSCH)—Offset 163Ch ........................................ 205
5.5.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1640h ............................. 207
5.5.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 164Ch .................... 208
5.5.18 Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1650h..
209
5.5.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1654h .............. 210
5.5.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 16A4h ................................. 211
5.5.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset 16ACh ............... 212
5.5.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 16B0h.......... 213
5.5.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 16B4h .......................... 214
5.5.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 16BCh .................................... 215
5.5.25 Major Mode Control (D_CR_MMC)—Offset 1724h ...................................... 215
5.5.26 Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1728h
216
5.5.27 Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 172Ch
217
5.5.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1730h .......................... 218
5.5.29 Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1734h 219
5.5.30 Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1738h 219
5.5.31 Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 173Ch 220
5.5.32 Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1740h 221
5.5.33 Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1744h 222
5.5.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1748h ................................ 223
5.5.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 174Ch ............ 223
5.5.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1754h......... 225
5.5.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1780h ....... 226
5.5.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1784h .............. 227
5.6 Registers Summary ......................................................................................... 228
5.6.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1A00h .............................. 230

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 5.6.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1A08h ........................... 232
5.6.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 1A0Ch ........................... 233
5.6.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1A10h ........................... 234
5.6.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1A14h ........................... 235
5.6.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1A18h ........................... 236
5.6.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 1A1Ch ........................... 237
5.6.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1A20h ........................... 239
5.6.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1A24h ........................... 240
5.6.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1A28h ........................... 241
5.6.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 1A2Ch .................... 242
5.6.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1A30h............ 243
5.6.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1A34h............ 245
5.6.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1A38h .................................. 247
5.6.15 D-Unit Scheduler (D_CR_DSCH)—Offset 1A3Ch ........................................ 249
5.6.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1A40h.............................. 251
5.6.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 1A4Ch .................... 252
5.6.18 Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1A50h .
253
5.6.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1A54h............... 254
5.6.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 1AA4h ................................. 255
5.6.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset 1AACh................ 256
5.6.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 1AB0h .......... 257
5.6.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 1AB4h .......................... 258
5.6.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 1ABCh .................................... 259
5.6.25 Major Mode Control (D_CR_MMC)—Offset 1B24h ...................................... 259
5.6.26 Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1B28h
260
5.6.27 Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 1B2Ch
261
5.6.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1B30h .......................... 262
5.6.29 Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1B34h 263
5.6.30 Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1B38h 263
5.6.31 Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 1B3Ch264
5.6.32 Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1B40h 265
5.6.33 Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1B44h 266
5.6.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1B48h................................. 267
5.6.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 1B4Ch ............ 267
5.6.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1B54h ......... 269
5.6.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1B80h ....... 270
5.6.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1B84h............... 271
5.7 Registers Summary.......................................................................................... 273
5.7.1 Thermal Device Mailbox Data0
(P_CR_THERMAL_MAILBOX_DATA0_0_0_0_MCHBAR)—Offset 7000h........... 275
5.7.2 Thermal Device Mailbox Data1
(P_CR_THERMAL_MAILBOX_DATA1_0_0_0_MCHBAR)—Offset 7004h........... 276
5.7.3 Thermal Device Mailbox Interface
(P_CR_THERMAL_MAILBOX_INTERFACE_0_0_0_MCHBAR)—Offset 7008h .... 277
5.7.4 Thermal Device IRQ and Lock Configuration
(P_CR_THERMAL_DEVICE_IRQ_0_0_0_MCHBAR)—Offset 700Ch ................. 278
5.7.5 Package Thermal Interrupt Control
(P_CR_PKG_THERM_INTERRUPT_0_0_0_MCHBAR)—Offset 7010h............... 279
5.7.6 ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR
(P_CR_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR)—Offset
7014h ................................................................................................. 280
5.7.7 Package Thermal Status (P_CR_PKG_THERM_STATUS_0_0_0_MCHBAR)—Offset
701Ch ................................................................................................. 281

8 334818
 5.7.8 LPDDR DRAM Thermal (MR4) Status of Channel 01
(P_CR_MEM_MR4_TEMPERATURE_DEV1_0_0_0_MCHBAR)—Offset 7024h.... 283
5.7.9 LPDDR DRAM Thermal (MR4) Status of Channel 10
(P_CR_MEM_MR4_TEMPERATURE_DEV2_0_0_0_MCHBAR)—Offset 7028h.... 283
5.7.10 Machine Check Error Source Log (P_CR_MCA_ERROR_SRC_0_0_0_MCHBAR)—
Offset 702Ch ....................................................................................... 284
5.7.11 DDR Thermal Throttling Control
(P_CR_DDR_THERM_THRT_CTRL_0_0_0_MCHBAR)—Offset 7030h ............. 285
5.7.12 DDR Thermal Interrupt Control
(P_CR_DDR_THERM_INTERRUPT_0_0_0_MCHBAR)—Offset 7034h .............. 286
5.7.13 DDR Thermal Status (P_CR_DDR_THERM_STATUS_0_0_0_MCHBAR)—Offset
7038h................................................................................................. 288
5.7.14 Dram Energy Counter (P_CR_DDR_ENERGY_STATUS_0_0_0_MCHBAR)—Offset
7048h................................................................................................. 289
5.7.15 DDR RAPL Performance Status
(P_CR_DDR_RAPL_PERF_STATUS_0_0_0_MCHBAR)—Offset 704Ch............. 290
5.7.16 Package RAPL Performance Status
(P_CR_PACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR)—Offset 7050h...... 291
5.7.17 IA Core Performance / Power Priority Control
(P_CR_PRIMARY_PLANE_TURBO_PLCY_0_0_0_MCHBAR)—Offset 7054h ...... 292
5.7.18 Graphics Performance / Power Priority Control
(P_CR_SECONDARY_PLANE_TURBO_PLCY_0_0_0_MCHBAR)—Offset 7058h . 292
5.7.19 IA Energy Counter
(P_CR_PRIMARY_PLANE_ENERGY_STATUS_0_0_0_MCHBAR)—Offset 705Ch 293
5.7.20 Graphics Energy Counter
(P_CR_SECONDARY_PLANE_ENERGY_STATUS_0_0_0_MCHBAR)—Offset 7060h .
294
5.7.21 PACKAGE_POWER_SKU_UNIT
(P_CR_PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR)—Offset 7068h........ 295
5.7.22 SOC Energy Counter (P_CR_PACKAGE_ENERGY_STATUS_0_0_0_MCHBAR)—
Offset 706Ch ....................................................................................... 296
5.7.23 GT_PERF_STATUS (P_CR_GT_PERF_STATUS_0_0_0_MCHBAR)—Offset 7070h....
296
5.7.24 Temperature Reference and Control
(P_CR_TEMPERATURE_TARGET_0_0_0_MCHBAR)—Offset 7074h ................ 297
5.7.25 BIOS Reset Completion (P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)—Offset
7078h................................................................................................. 298
5.7.26 BIOS_MAILBOX_DATA (P_CR_BIOS_MAILBOX_DATA_0_0_0_MCHBAR)—Offset
7080h................................................................................................. 301
5.7.27 BIOS_MAILBOX_INTERFACE
(P_CR_BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR)—Offset 7084h .......... 301
5.7.28 CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset 7088h . 302
5.7.29 GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset 708Ch
303
5.7.30 SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset
7090h................................................................................................. 304
5.7.31 Memory Frequency Status
(P_CR_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset
7094h................................................................................................. 305
5.7.32 Package Power SKU and RAPL Power Control Capabilities
(P_CR_PACKAGE_POWER_SKU_0_0_0_MCHBAR)—Offset 70A0h ................ 306
5.7.33 Package RAPL Power Limit (P_CR_PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR)—
Offset 70A8h ....................................................................................... 307

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 5.7.34 IA_PERF_LIMIT_REASONS
(P_CR_IA_PERF_LIMIT_REASONS_0_0_0_MCHBAR)—Offset 70B0h............. 309
5.7.35 IA Core C0 Residency Counter
(P_CR_TELEM_IA_C0_RESIDENCY_0_0_0_MCHBAR)—Offset 70C0h ............ 312
5.7.36 Graphics C0 Residency Counter
(P_CR_TELEM_GT_C0_RESIDENCY_0_0_0_MCHBAR)—Offset 70C4h ........... 313
5.7.37 I-unit Processing System C0 Residency Counter
(P_CR_TELEM_IUNIT_C0_RESIDENCY_0_0_0_MCHBAR)—Offset 70C8h ....... 313
5.7.38 TELEM_IA_FREQ_ACCUMULATOR
(P_CR_TELEM_IA_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—Offset 70CCh ... 314
5.7.39 Graphics C0 Residency Counter
(P_CR_TELEM_GT_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—Offset 70D0h .. 314
5.7.40 I-unit Processing System C0 Residency Counter
(P_CR_TELEM_IUNIT_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—Offset 70D4h ...
315
5.7.41 Memory Active Residency
(P_CR_TELEM_FAR_MEMORY_ACTIVE_0_0_0_MCHBAR)—Offset 70E8h ....... 315
5.7.42 Package Temperatures (P_CR_PACKAGE_TEMPERATURES_0_0_0_MCHBAR)—
Offset 70F4h ........................................................................................ 316
5.7.43 Package Thermal Limit Control
(P_CR_THERMAL_LIMIT_CONTROL_0_0_0_MCHBAR)—Offset 7104h ........... 317
5.7.44 Memory Subsystem Frequency Capabilities
(P_CR_MEMSS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset 7108h 318
5.7.45 Memory Controller (MC) BIOS Reset Request and Status
(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR)—Offset 7114h ............................. 319
5.7.46 MEMSS_FREQUENCY_CAPABILITIES1
(P_CR_MEMSS_FREQUENCY_CAPABILITIES1_0_0_0_MCHBAR)—Offset 7118h...
322
5.7.47 PP1_C0_CORE_CLOCK_0_0_0_MCHBAR
(P_CR_PP1_C0_CORE_CLOCK_0_0_0_MCHBAR)—Offset 7160h .................. 323
5.7.48 Core Exists Vector (P_CR_CORE_EXISTS_VECTOR_0_0_0_MCHBAR)—Offset
7164h ................................................................................................. 324
5.7.49 Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR)—
Offset 7168h ........................................................................................ 324
5.7.50 PL3 and PL4 Control (P_CR_PL3_CONTROL_0_0_0_MCHBAR)—Offset 71F0h. 326
5.7.51 Graphics Superqueue Active Clocks
(P_CR_PP1_ANY_THREAD_ACTIVITY_0_0_0_MCHBAR)—Offset 7244h ......... 327
5.7.52 LPDDR DRAM Thermal (MR4) Status of Channel 00
(P_CR_MEM_MR4_TEMPERATURE_DEV3_0_0_0_MCHBAR)—Offset 7248h .... 328
5.7.53 LPDDR DRAM Thermal (MR4) Status of Channel 11
(P_CR_MEM_MR4_TEMPERATURE_DEV4_0_0_0_MCHBAR)—Offset 724Ch .... 329
5.8 Registers Summary.......................................................................................... 329
5.8.1 Upstream Device Arbiter Grant Count A2T
(A_CR_UPARB_GCNT_DEV_A2T_MCHBAR)—Offset 6400h .......................... 332
5.8.2 Upstream A2B Arbiter Channel 0 Grant Count
(A_CR_UPARB_GCNT_A2B_0_MCHBAR)—Offset 6404h .............................. 333
5.8.3 Upstream A2B Arbiter Channel 1 Grant Count
(A_CR_UPARB_GCNT_A2B_1_MCHBAR)—Offset 6408h .............................. 334
5.8.4 Upstream A2B Arbiter Channel 2 Grant Count
(A_CR_UPARB_GCNT_A2B_2_MCHBAR)—Offset 640Ch .............................. 335
5.8.5 Upstream A2B Arbiter Channel 3 Grant Count
(A_CR_UPARB_GCNT_A2B_3_MCHBAR)—Offset 6410h .............................. 336
5.8.6 Upstream A2B Arbiter Channel 4 Grant Count
(A_CR_UPARB_GCNT_A2B_4_MCHBAR)—Offset 6414h .............................. 337
5.8.7 Upstream A2B Arbiter Channel 5 Grant Count
(A_CR_UPARB_GCNT_A2B_5_MCHBAR)—Offset 6418h .............................. 338

10 334818
 5.8.8 Upstream A2B Arbiter Channel 6 Grant Count
(A_CR_UPARB_GCNT_A2B_6_MCHBAR)—Offset 641Ch ............................. 338
5.8.9 Upstream A2B Arbiter Channel 7 Grant Count
(A_CR_UPARB_GCNT_A2B_7_MCHBAR)—Offset 6420h.............................. 339
5.8.10 Upstream A2T Arbiter Channel 0 Grant Count
(A_CR_UPARB_GCNT_A2T_0_MCHBAR)—Offset 6424h .............................. 340
5.8.11 Upstream P2P Arbiter Channel 0 Grant Count
(A_CR_UPARB_GCNT_P2P_0_MCHBAR)—Offset 6428h .............................. 341
5.8.12 Upstream P2P Arbiter Channel 1 Grant Count
(A_CR_UPARB_GCNT_P2P_1_MCHBAR)—Offset 642Ch .............................. 342
5.8.13 Upstream Private Credit Return Grant Count Posted 0
(A_CR_CRDARB_PRIV_GCNT_DEV_P_0_MCHBAR)—Offset 6430h ............... 343
5.8.14 Upstream Private Credit Return Grant Count Posted 1
(A_CR_CRDARB_PRIV_GCNT_DEV_P_1_MCHBAR)—Offset 6434h ............... 343
5.8.15 Upstream Private Credit Return Grant Count Non-posted 0
(A_CR_CRDARB_PRIV_GCNT_DEV_N_0_MCHBAR)—Offset 6438h ............... 344
5.8.16 Upstream Private Credit Return Grant Count Posted 1
(A_CR_CRDARB_PRIV_GCNT_DEV_N_1_MCHBAR)—Offset 643Ch............... 345
5.8.17 Upstream Private Credit Return Grant Count Completion
(A_CR_CRDARB_PRIV_GCNT_DEV_C_0_MCHBAR)—Offset 6440h ............... 346
5.8.18 Upstream Shared Credit Return Grant Count Posted 0
(A_CR_CRDARB_SHRD_GCNT_DEV_P_0_MCHBAR)—Offset 6444h .............. 347
5.8.19 Upstream Shared Credit Return Grant Count Posted 1
(A_CR_CRDARB_SHRD_GCNT_DEV_P_1_MCHBAR)—Offset 6448h .............. 348
5.8.20 Upstream Shared Credit Return Grant Count Non-posted 0
(A_CR_CRDARB_SHRD_GCNT_DEV_N_0_MCHBAR)—Offset 644Ch ............. 348
5.8.21 Upstream Shared Credit Return Grant Count Posted 1
(A_CR_CRDARB_SHRD_GCNT_DEV_N_1_MCHBAR)—Offset 6450h.............. 349
5.8.22 Upstream Shared Credit Return Grant Count Completion
(A_CR_CRDARB_SHRD_GCNT_DEV_C_0_MCHBAR)—Offset 6454h.............. 350
5.8.23 Upstream Credit Arbiter Private Credit Return Class Arbiter Grant Count
(A_CR_CRDARB_PRIV_GCNT_CLS_MCHBAR)—Offset 6458h....................... 351
5.8.24 Upstream Credit Arbiter Shared Cedit Return Class Arbiter Grant Count
(A_CR_CRDARB_SHRD_GCNT_CLS_MCHBAR)—Offset 645Ch ..................... 351
5.8.25 Gazelle Queue Limit Channel 0-3 (A_CR_GZLQ_LIMIT_CH0_3_MCHBAR)—Offset
6460h................................................................................................. 352
5.8.26 Gazelle Queue Limit Channels 4-7 (A_CR_GZLQ_LIMIT_CH4_7_MCHBAR)—Offset
6464h................................................................................................. 353
5.8.27 IOMMU Arbiter Grant Count VC0a Register
(A_CR_IOMMUARB_GCNT_VC0a_0_0_0_MCHBAR)—Offset 6468h............... 353
5.8.28 IOMMU Arbiter Grant Count VC0b Register
(A_CR_IOMMUARB_GCNT_VC0b_0_0_0_MCHBAR)—Offset 646Ch .............. 354
5.8.29 IOMMU Arbiter Grant Count VC1b Register
(A_CR_IOMMUARB_GCNT_VC1b_0_0_0_MCHBAR)—Offset 6470h............... 355
5.8.30 Gazelle Queue Reserved Entries Channels 0-3
(A_CR_GZLQ_RSVD_CH0_3_MCHBAR)—Offset 6474h ............................... 356
5.8.31 Gazelle Queue Reserved Entries Channels 4-7
(A_CR_GZLQ_RSVD_CH4_7_MCHBAR)—Offset 6478h ............................... 356
5.8.32 Spare BIOS (A_CR_SPARE_BIOS_MCHBAR)—Offset 647Ch ........................ 357
5.8.33 Upcmd Credit Maximum Channel 0
(A_CR_UPCMD_CRDTMAX_CH0_0_0_0_MCHBAR)—Offset 6490h ................ 357
5.8.34 Upcmd Credit Maximum Channel 1
(A_CR_UPCMD_CRDTMAX_CH1_0_0_0_MCHBAR)—Offset 6494h ................ 358
5.8.35 Upcmd Credit Maximum Channel 2
(A_CR_UPCMD_CRDTMAX_CH2_0_0_0_MCHBAR)—Offset 6498h ................ 359
5.8.36 Upcmd Credit Maximum Channel 3
(A_CR_UPCMD_CRDTMAX_CH3_0_0_0_MCHBAR)—Offset 649Ch................ 360

334818 11
 5.8.37 Upcmd Credit Maximum Channel 4
(A_CR_UPCMD_CRDTMAX_CH4_0_0_0_MCHBAR)—Offset 64A0h ................ 360
5.8.38 Upcmd Credit Maximum Channel 5
(A_CR_UPCMD_CRDTMAX_CH5_0_0_0_MCHBAR)—Offset 64A4h ................ 361
5.8.39 Upcmd Credit Maximum Channel 6
(A_CR_UPCMD_CRDTMAX_CH6_0_0_0_MCHBAR)—Offset 64A8h ................ 362
5.8.40 Upcmd Credit Maximum Channel 7
(A_CR_UPCMD_CRDTMAX_CH7_0_0_0_MCHBAR)—Offset 64ACh ................ 362
5.8.41 MOT OUT Base Register (A_CR_MOT_OUT_BASE_0_0_0_MCHBAR)—Offset
64C0h ................................................................................................. 363
5.8.42 MOT OUT Mask Register (A_CR_MOT_OUT_MASK_0_0_0_MCHBAR)—Offset
64C4h ................................................................................................. 364
5.8.43 CHAP Select 1 (A_CR_CHAP_SLCT1_MCHBAR)—Offset 6500h ..................... 365
5.8.44 CHAP Select 2 (A_CR_CHAP_SLCT2_MCHBAR)—Offset 6504h ..................... 366
5.8.45 CHAP Select 3 (A_CR_CHAP_SLCT3_MCHBAR)—Offset 6508h ..................... 367
5.8.46 Slice and Channel Hash (A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR)—
Offset 65C0h........................................................................................ 367
5.8.47 Mirror Range Register (A_CR_MIRROR_RANGE_0_0_0_MCHBAR)—Offset 65C8h
370
5.8.48 ASYM MEM REGION 0 CONFIGURATION WITH NO INTERLEAVING
(A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR)—Offset 65D0h .................. 371
5.8.49 ASYM MEM REGION 1 CONFIGURATION WITH NO INTERLEAVING
(A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR)—Offset 65D4h .................. 372
5.8.50 Two-Way Asymmetric Memory Region Configuration
(A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR)—Offset 65D8h .......... 373
5.9 Registers Summary.......................................................................................... 374
5.9.1 B-Unit Miscellaneous Configuration (B_CR_BMISC_0_0_0_MCHBAR)—Offset
6800h ................................................................................................. 383
5.9.2 Slice 0 Memory Access Count (B_CR_MEM_ACCESS_COUNT_SLICE0)—Offset
6868h ................................................................................................. 384
5.9.3 Slice 1 Memory Access Count (B_CR_MEM_ACCESS_COUNT_SLICE1)—Offset
686Ch ................................................................................................. 384
5.9.4 IMR0 Mask (B_CR_BIMR0MASK_0_0_0_MCHBAR)—Offset 6874h ................ 385
5.9.5 IMR0 Control Policy (B_CR_BIMR0CP_0_0_0_MCHBAR)—Offset 6878h......... 386
5.9.6 IMR0 Read Access Policy (B_CR_BIMR0RAC_0_0_0_MCHBAR)—Offset 6880h 387
5.9.7 IMR0 Write Access Policy (B_CR_BIMR0WAC_0_0_0_MCHBAR)—Offset 6888h ...
392
5.9.8 IMR1 Base (B_CR_BIMR1BASE_0_0_0_MCHBAR)—Offset 6890h ................. 396
5.9.9 IMR1 Mask (B_CR_BIMR1MASK_0_0_0_MCHBAR)—Offset 6894h ................ 397
5.9.10 IMR1 Control Policy (B_CR_BIMR1CP_0_0_0_MCHBAR)—Offset 6898h......... 398
5.9.11 IMR1 Read Access Policy (B_CR_BIMR1RAC_0_0_0_MCHBAR)—Offset 68A0h399
5.9.12 IMR1 Write Access Policy (B_CR_BIMR1WAC_0_0_0_MCHBAR)—Offset 68A8h ...
404
5.9.13 Base 0 IMR2 Base (B_CR_BIMR2BASE_0_0_0_MCHBAR)—Offset 68B0h....... 409
5.9.14 IMR2 Mask (B_CR_BIMR2MASK_0_0_0_MCHBAR)—Offset 68B4h ................ 409
5.9.15 IMR2 Control Policy (B_CR_BIMR2CP_0_0_0_MCHBAR)—Offset 68B8h......... 410
5.9.16 IMR2 Read Access Policy (B_CR_BIMR2RAC_0_0_0_MCHBAR)—Offset 68C0h411
5.9.17 IMR2 Write Access Policy (B_CR_BIMR2WAC_0_0_0_MCHBAR)—Offset 68C8h ...
416
5.9.18 IMR3 Base (B_CR_BIMR3BASE_0_0_0_MCHBAR)—Offset 68D0h................. 421
5.9.19 IMR3 Mask (B_CR_BIMR3MASK_0_0_0_MCHBAR)—Offset 68D4h................ 422
5.9.20 IMR3 Control Policy (B_CR_BIMR3CP_0_0_0_MCHBAR)—Offset 68D8h ........ 423
5.9.21 IMR3 Read Access Policy (B_CR_BIMR3RAC_0_0_0_MCHBAR)—Offset 68E0h 423
5.9.22 IMR3 Write Access Policy (B_CR_BIMR3WAC_0_0_0_MCHBAR)—Offset 68E8h ...
428
5.9.23 IMR4 Base (B_CR_BIMR4BASE_0_0_0_MCHBAR)—Offset 68F0h ................. 433

12 334818
 5.9.24 IMR4 Mask (B_CR_BIMR4MASK_0_0_0_MCHBAR)—Offset 68F4h ................ 434
5.9.25 B-Unit IMR4 Control Policy (B_CR_BIMR4CP_0_0_0_MCHBAR)—Offset 68F8h435
5.9.26 IMR4 Read Access Policy (B_CR_BIMR4RAC_0_0_0_MCHBAR)—Offset 6900h 435
5.9.27 IMR4 Write Access Policy (B_CR_BIMR4WAC_0_0_0_MCHBAR)—Offset 6908h....
440
5.9.28 IMR5 Base (B_CR_BIMR5BASE_0_0_0_MCHBAR)—Offset 6910h................. 447
5.9.29 IMR5 Mask (B_CR_BIMR5MASK_0_0_0_MCHBAR)—Offset 6914h................ 447
5.9.30 IMR5 Control Policy (B_CR_BIMR5CP_0_0_0_MCHBAR)—Offset 6918h ........ 448
5.9.31 IMR5 Read Access Policy (B_CR_BIMR5RAC_0_0_0_MCHBAR)—Offset 6920h 449
5.9.32 IMR5 Write Access Policy (B_CR_BIMR5WAC_0_0_0_MCHBAR)—Offset 6928h....
454
5.9.33 IMR6 Base (B_CR_BIMR6BASE_0_0_0_MCHBAR)—Offset 6930h................. 459
5.9.34 IMR6 Mask (B_CR_BIMR6MASK_0_0_0_MCHBAR)—Offset 6934h................ 460
5.9.35 IMR6 Control Policy (B_CR_BIMR6CP_0_0_0_MCHBAR)—Offset 6938h ........ 461
5.9.36 IMR6 Read Access Policy (B_CR_BIMR6RAC_0_0_0_MCHBAR)—Offset 6940h 461
5.9.37 IMR6 Write Access Policy (B_CR_BIMR6WAC_0_0_0_MCHBAR)—Offset 6948h....
466
5.9.38 IMR7 Base (B_CR_BIMR7BASE_0_0_0_MCHBAR)—Offset 6950h................. 471
5.9.39 IMR7 Mask (B_CR_BIMR7MASK_0_0_0_MCHBAR)—Offset 6954h................ 472
5.9.40 IMR7 Control Policy (B_CR_BIMR7CP_0_0_0_MCHBAR)—Offset 6958h ........ 473
5.9.41 IMR7 Read Access Policy (B_CR_BIMR7RAC_0_0_0_MCHBAR)—Offset 6960h 473
5.9.42 IMR7 Write Access Policy (B_CR_BIMR7WAC_0_0_0_MCHBAR)—Offset 6968h....
478
5.9.43 IMR8 Base (B_CR_BIMR8BASE_0_0_0_MCHBAR)—Offset 6970h................. 483
5.9.44 IMR8 Mask (B_CR_BIMR8MASK_0_0_0_MCHBAR)—Offset 6974h................ 484
5.9.45 IMR8 Control Policy (B_CR_BIMR8CP_0_0_0_MCHBAR)—Offset 6978h ........ 485
5.9.46 IMR8 Read Access Policy (B_CR_BIMR8RAC_0_0_0_MCHBAR)—Offset 6980h 486
5.9.47 IMR8 Write Access Policy (B_CR_BIMR8WAC_0_0_0_MCHBAR)—Offset 6988h....
490
5.9.48 IMR9 Base (B_CR_BIMR9BASE_0_0_0_MCHBAR)—Offset 6990h................. 495
5.9.49 IMR9 Mask (B_CR_BIMR9MASK_0_0_0_MCHBAR)—Offset 6994h................ 496
5.9.50 IMR9 Control Policy (B_CR_BIMR9CP_0_0_0_MCHBAR)—Offset 6998h ........ 497
5.9.51 IMR9 Read Access Policy (B_CR_BIMR9RAC_0_0_0_MCHBAR)—Offset 69A0h498
5.9.52 IMR9 Write Access Policy (B_CR_BIMR9WAC_0_0_0_MCHBAR)—Offset 69A8h....
503
5.9.53 IMR10 Base (B_CR_BIMR10BASE_0_0_0_MCHBAR)—Offset 69B0h ............. 507
5.9.54 IMR10 Mask (B_CR_BIMR10MASK_0_0_0_MCHBAR)—Offset 69B4h ............ 508
5.9.55 IMR10 Control Policy (B_CR_BIMR10CP_0_0_0_MCHBAR)—Offset 69B8h..... 509
5.9.56 IMR10 Read Access Policy (B_CR_BIMR10RAC_0_0_0_MCHBAR)—Offset 69C0h .
510
5.9.57 IMR10 Write Access Policy (B_CR_BIMR10WAC_0_0_0_MCHBAR)—Offset 69C8h
515
5.9.58 IMR11 Base (B_CR_BIMR11BASE_0_0_0_MCHBAR)—Offset 69D0h ............. 520
5.9.59 IMR11 Mask (B_CR_BIMR11MASK_0_0_0_MCHBAR)—Offset 69D4h ............ 520
5.9.60 IMR11 Control Policy (B_CR_BIMR11CP_0_0_0_MCHBAR)—Offset 69D8h .... 521
5.9.61 IMR11 Read Access Policy (B_CR_BIMR11RAC_0_0_0_MCHBAR)—Offset 69E0h .
522
5.9.62 IMR11 Write Access Policy (B_CR_BIMR11WAC_0_0_0_MCHBAR)—Offset 69E8h
527
5.9.63 IMR12 Base (B_CR_BIMR12BASE_0_0_0_MCHBAR)—Offset 69F0h ............. 532
5.9.64 IMR12 Mask (B_CR_BIMR12MASK_0_0_0_MCHBAR)—Offset 69F4h ............ 533
5.9.65 IMR12 Control Policy (B_CR_BIMR12CP_0_0_0_MCHBAR)—Offset 69F8h ..... 534
5.9.66 IMR12 Read Access Policy (B_CR_BIMR12RAC_0_0_0_MCHBAR)—Offset 6A00h .
534
5.9.67 IMR12 Write Access Policy (B_CR_BIMR12WAC_0_0_0_MCHBAR)—Offset 6A08h
539

334818 13
 5.9.68 IMR13 Base (B_CR_BIMR13BASE_0_0_0_MCHBAR)—Offset 6A10h ............. 544
5.9.69 IMR13 Mask (B_CR_BIMR13MASK_0_0_0_MCHBAR)—Offset 6A14h ............ 545
5.9.70 IMR13 Control Policy (B_CR_BIMR13CP_0_0_0_MCHBAR)—Offset 6A18h ..... 546
5.9.71 IMR13 Read Access Policy (B_CR_BIMR13RAC_0_0_0_MCHBAR)—Offset 6A20h .
547
5.9.72 IMR13 Write Access Policy (B_CR_BIMR13WAC_0_0_0_MCHBAR)—Offset 6A28h
551
5.9.73 IMR14 Base (B_CR_BIMR14BASE_0_0_0_MCHBAR)—Offset 6A30h ............. 556
5.9.74 IMR14 Mask (B_CR_BIMR14MASK_0_0_0_MCHBAR)—Offset 6A34h ............ 557
5.9.75 IMR14 Control Policy (B_CR_BIMR14CP_0_0_0_MCHBAR)—Offset 6A38h ..... 558
5.9.76 IMR14 Read Access Policy (B_CR_BIMR14RAC_0_0_0_MCHBAR)—Offset 6A40h .
559
5.9.77 IMR14 Write Access Policy (B_CR_BIMR14WAC_0_0_0_MCHBAR)—Offset 6A48h
564
5.9.78 IMR15 Base (B_CR_BIMR15BASE_0_0_0_MCHBAR)—Offset 6A50h ............. 568
5.9.79 IMR15 Mask (B_CR_BIMR15MASK_0_0_0_MCHBAR)—Offset 6A54h ............ 569
5.9.80 IMR15 Control Policy (B_CR_BIMR15CP_0_0_0_MCHBAR)—Offset 6A58h ..... 570
5.9.81 IMR15 Read Access Policy (B_CR_BIMR15RAC_0_0_0_MCHBAR)—Offset 6A60h .
571
5.9.82 IMR15 Write Access Policy (B_CR_BIMR15WAC_0_0_0_MCHBAR)—Offset 6A68h
576
5.9.83 IMR16 Base (B_CR_BIMR16BASE_0_0_0_MCHBAR)—Offset 6A70h ............. 581
5.9.84 IMR16 Mask (B_CR_BIMR16MASK_0_0_0_MCHBAR)—Offset 6A74h ............ 581
5.9.85 IMR16 Control Policy (B_CR_BIMR16CP_0_0_0_MCHBAR)—Offset 6A78h ..... 582
5.9.86 IMR16 Read Access Policy (B_CR_BIMR16RAC_0_0_0_MCHBAR)—Offset 6A80h .
583
5.9.87 IMR16 Write Access Policy (B_CR_BIMR16WAC_0_0_0_MCHBAR)—Offset 6A88h
588
5.9.88 IMR17 Base (B_CR_BIMR17BASE_0_0_0_MCHBAR)—Offset 6A90h ............. 593
5.9.89 IMR17 Mask (B_CR_BIMR17MASK_0_0_0_MCHBAR)—Offset 6A94h ............ 594
5.9.90 IMR17 Control Policy (B_CR_BIMR17CP_0_0_0_MCHBAR)—Offset 6A98h ..... 595
5.9.91 IMR17 Read Access Policy (B_CR_BIMR17RAC_0_0_0_MCHBAR)—Offset 6AA0h.
595
5.9.92 IMR17 Write Access Policy (B_CR_BIMR17WAC_0_0_0_MCHBAR)—Offset 6AA8h
600
5.9.93 IMR18 Base (B_CR_BIMR18BASE_0_0_0_MCHBAR)—Offset 6AB0h ............. 605
5.9.94 IMR18 Mask (B_CR_BIMR18MASK_0_0_0_MCHBAR)—Offset 6AB4h ............ 606
5.9.95 IMR18 Control Policy (B_CR_BIMR18CP_0_0_0_MCHBAR)—Offset 6AB8h ..... 607
5.9.96 IMR18 Read Access Policy (B_CR_BIMR18RAC_0_0_0_MCHBAR)—Offset 6AC0h.
608
5.9.97 IMR18 Write Access Policy (B_CR_BIMR18WAC_0_0_0_MCHBAR)—Offset 6AC8h
612
5.9.98 IMR19 Base (B_CR_BIMR19BASE_0_0_0_MCHBAR)—Offset 6AD0h ............. 619
5.9.99 IMR19 Mask (B_CR_BIMR19MASK_0_0_0_MCHBAR)—Offset 6AD4h ............ 620
5.9.100IMR19 Control Policy (B_CR_BIMR19CP_0_0_0_MCHBAR)—Offset 6AD8h..... 621
5.9.101IMR19 Read Access Policy (B_CR_BIMR19RAC_0_0_0_MCHBAR)—Offset 6AE0h .
622
5.9.102IMR19 Write Access Policy (B_CR_BIMR19WAC_0_0_0_MCHBAR)—Offset 6AE8h
626
5.9.103MOT Out Base (B_CR_MOT_OUT_BASE_0_0_0_MCHBAR)—Offset 6AF0h...... 631
5.9.104MOT Out Mask (B_CR_MOT_OUT_MASK_0_0_0_MCHBAR)—Offset 6AF4h..... 632
5.9.105MOT Buffer Control Policy (B_CR_BMOT_BUF_CP_0_0_0_MCHBAR)—Offset
6AF8h ................................................................................................. 633
5.9.106MOT Buffer Read Access Policy (B_CR_BMOT_BUF_RAC_0_0_0_MCHBAR)—Offset
6B00h ................................................................................................. 634

14 334818
 5.9.107MOT Buffer Write Access Policy (B_CR_BMOT_BUF_WAC_0_0_0_MCHBAR)—
Offset 6B08h ....................................................................................... 639
5.9.108IMR Global BM Control Policy (B_CR_BIMRGLOBAL_BM_CP_0_0_0_MCHBAR)—
Offset 6B10h ....................................................................................... 645
5.9.109IMR Global BM Read Access Control
(B_CR_BIMRGLOBAL_BM_RAC_0_0_0_MCHBAR)—Offset 6B18h ................. 646
5.9.110IMR Global BM Write Access Policy
(B_CR_BIMRGLOBAL_BM_WAC_0_0_0_MCHBAR)—Offset 6B20h ................ 646
5.9.111Graphics Stolen Memory Control Policy (B_CR_BGSMCP_0_0_0_MCHBAR)—
Offset 6B28h ....................................................................................... 647
5.9.112GSM Read Access Policy (B_CR_BGSMRAC_0_0_0_MCHBAR)—Offset 6B30h 648
5.9.113GSM Write Access Policy (B_CR_BGSMWAC_0_0_0_MCHBAR)—Offset 6B38h 654
5.9.114TPM Control Policy (B_CR_TPM_CP_0_0_0_MCHBAR)—Offset 6B40h ........... 660
5.9.115TPM Access Control (B_CR_TPM_AC_0_0_0_MCHBAR)—Offset 6B48h.......... 661
5.9.116BGSM Control Register (B_CR_BGSM_CTRL_0_0_0_MCHBAR)—Offset 6B50h 661
5.9.117SMM Control Register (B_CR_BSMR_CTRL_0_0_0_MCHBAR)—Offset 6B54h . 662
5.9.118Default VTd Control Register (B_CR_BDEFVTDPMR_CTRL_0_0_0_MCHBAR)—
Offset 6B58h ....................................................................................... 663
5.9.119MOT Trigger Trace Control (B_CR_MOT_TRIG_TRACE_CTRL_0_0_0_MCHBAR)—
Offset 6B7Ch ....................................................................................... 664
5.9.120MOT Slice 0 Memory Pointer
(B_CR_MOT_SLICE_0_MEM_PTR_0_0_0_MCHBAR)—Offset 6B80h .............. 667
5.9.121MOT Slice 1 Memory Pointer
(B_CR_MOT_SLICE_1_MEM_PTR_0_0_0_MCHBAR)—Offset 6B88h .............. 668
5.9.122MOT Slice 0 Record ID (B_CR_MOT_SLICE_0_RECORD_ID_0_0_0_MCHBAR)—
Offset 6B90h ....................................................................................... 669
5.9.123MOT Slice 1 Record ID (B_CR_MOT_SLICE_1_RECORD_ID_0_0_0_MCHBAR)—
Offset 6B94h ....................................................................................... 669
5.9.124MOT Filter Match 0 (B_CR_MOT_FILTER_MATCH0_0_0_0_MCHBAR)—Offset
6BA0h ................................................................................................ 670
5.9.125MOT Filter Mask (B_CR_MOT_FILTER_MASK0_0_0_0_MCHBAR)—Offset 6BA8h ..
671
5.9.126MOT Filter Match 1 (B_CR_MOT_FILTER_MATCH1_0_0_0_MCHBAR)—Offset
6BB0h ................................................................................................ 672
5.9.127MOT Filter Mask 1 (B_CR_MOT_FILTER_MASK1_0_0_0_MCHBAR)—Offset 6BB8h
672
5.9.128MOT Filter Misc 0 (B_CR_MOT_FILTER_MISC0_0_0_0_MCHBAR)—Offset 6BC0h .
673
5.9.129MOT Filter Misc 1 (B_CR_MOT_FILTER_MISC1_0_0_0_MCHBAR)—Offset 6BC8h .
674
5.9.130MOT Trigger Match 0 (B_CR_MOT_TRIGGER_MATCH0_0_0_0_MCHBAR)—Offset
6BD0h ................................................................................................ 675
5.9.131MOT Trigger Mask 0 (B_CR_MOT_TRIGGER_MASK0_0_0_0_MCHBAR)—Offset
6BD8h ................................................................................................ 676
5.9.132MOT Trigger Match 1 (B_CR_MOT_TRIGGER_MATCH1_0_0_0_MCHBAR)—Offset
6BE0h ................................................................................................ 677
5.9.133MOT Trigger Mask 1 (B_CR_MOT_TRIGGER_MASK1_0_0_0_MCHBAR)—Offset
6BE8h ................................................................................................ 678
5.9.134MOT Trigger Misc 0 (B_CR_MOT_TRIGGER_MISC0_0_0_0_MCHBAR)—Offset
6BF0h................................................................................................. 679
5.9.135MOT Trigger Misc 1 (B_CR_MOT_TRIGGER_MISC1_0_0_0_MCHBAR)—Offset
6BF8h................................................................................................. 680
5.9.136BIOSWR Control Policy (B_CR_BIOSWR_CP_0_0_0_MCHBAR)—Offset 6C08h 681
5.9.137BIOSWR Read Access Policy (B_CR_BIOSWR_RAC_0_0_0_MCHBAR)—Offset
6C10h ................................................................................................ 681
5.9.138BIOSWR Write Access Policy (B_CR_BIOSWR_WAC_0_0_0_MCHBAR)—Offset
6C18h ................................................................................................ 682

334818 15
 5.9.139TPM Selector (B_CR_TPM_SELECTOR_0_0_0_MCHBAR)—Offset 6C24h ........ 682
5.9.140B-Unit Pcode/Ucode Write, All Read Control Policy Register
(B_CR_P_U_CODEWR_ALLRD_CP_0_0_0_MCHBAR)—Offset 6C28h ............. 683
5.9.141B-Unit Pcode/Ucode Read Access Policy
(B_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCHBAR)—Offset 6C30h ........... 684
5.9.142B-Unit Pcode/Ucode Write Access Policy
(B_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_MCHBAR)—Offset 6C38h .......... 684
5.9.143Default VTd BAR (B_CR_DEFVTDBAR_0_0_0_MCHBAR)—Offset 6C80h ........ 685
5.9.144Gfx VTd BAR (B_CR_GFXVTDBAR_0_0_0_MCHBAR)—Offset 6C88h ............. 686
5.9.145B-Unit Lites Group 0 Control (B_CR_LITES0_CTL_0_0_0_MCHBAR)—Offset
6C90h ................................................................................................. 687
5.9.146B-Unit Lites Group 0 Opcode Match Filter
(B_CR_LITES0_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6C94h .............. 689
5.9.147B-Unit Lites Group 0 Agent Match Filter
(B_CR_LITES0_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6C98h ................ 691
5.9.148B-Unit Lites Group 0 U2C IntData Match Filter
(B_CR_LITES0_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6C9Ch........ 693
5.9.149B-Unit Lites Group 0 Address Match Filter LITES0_ADDR_MATCH
(B_CR_LITES0_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6CA0h.................. 693
5.9.150B-Unit Lites Group 0 Address Mask Filter LITES0_ADDR_MASK
(B_CR_LITES0_ADDR_MASK_0_0_0_MCHBAR)—Offset 6CA8h.................... 694
5.9.151B-Unit Lites Group 0 Data Match Filter LITES0_DATA_MATCH
(B_CR_LITES0_DATA_MATCH_0_0_0_MCHBAR)—Offset 6CB0h .................. 695
5.9.152B-Unit Lites Group 0 Data Mask Filter LITES0_DATA_MASK
(B_CR_LITES0_DATA_MASK_0_0_0_MCHBAR)—Offset 6CB4h .................... 695
5.9.153B-Unit Lites Group 1 Control (B_CR_LITES1_CTL_0_0_0_MCHBAR)—Offset
6CC0h................................................................................................. 696
5.9.154B-Unit Lites Group 1 Opcode Match Filter
(B_CR_LITES1_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6CC4h .............. 698
5.9.155B-Unit Lites Group 1 Agent Match Filter
(B_CR_LITES1_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6CC8h ................ 700
5.9.156B-Unit Lites Group 1 U2C IntData Match Filter
(B_CR_LITES1_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6CCCh ....... 702
5.9.157B-Unit Lites Group 1 Address Match Filter LITES1_ADDR_MATCH
(B_CR_LITES1_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6CD0h ................. 702
5.9.158B-Unit Lites Group 1 Address Mask Filter LITES1_ADDR_MASK
(B_CR_LITES1_ADDR_MASK_0_0_0_MCHBAR)—Offset 6CD8h ................... 703
5.9.159B-Unit Lites Group 1 Data Match Filter LITES1_DATA_MATCH
(B_CR_LITES1_DATA_MATCH_0_0_0_MCHBAR)—Offset 6CE0h .................. 704
5.9.160B-Unit Lites Group 1 Data Mask Filter LITES1_DATA_MASK
(B_CR_LITES1_DATA_MASK_0_0_0_MCHBAR)—Offset 6CE4h .................... 704
5.9.161B-Unit Lites Group 2 Control (B_CR_LITES2_CTL_0_0_0_MCHBAR)—Offset
6CF0h ................................................................................................. 705
5.9.162B-Unit Lites Group 2 Opcode Match Filter
(B_CR_LITES2_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6CF4h .............. 707
5.9.163B-Unit Lites Group 2 Agent Match Filter
(B_CR_LITES2_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6CF8h................. 709
5.9.164B-Unit Lites Group 2 U2C IntData Match Filter
(B_CR_LITES2_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6CFCh........ 711
5.9.165B-Unit Lites Group 2 Address Match Filter LITES2_ADDR_MATCH
(B_CR_LITES2_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6D00h.................. 711
5.9.166B-Unit Lites Group 2 Address Mask Filter LITES2_ADDR_MASK
(B_CR_LITES2_ADDR_MASK_0_0_0_MCHBAR)—Offset 6D08h.................... 712
5.9.167B-Unit Lites Group 2 Data Match Filter LITES2_DATA_MATCH
(B_CR_LITES2_DATA_MATCH_0_0_0_MCHBAR)—Offset 6D10h .................. 713
5.9.168B-Unit Lites Group 2 Data Mask Filter LITES2_DATA_MASK
(B_CR_LITES2_DATA_MASK_0_0_0_MCHBAR)—Offset 6D14h .................... 713

16 334818
 5.9.169B-Unit Lites Group 3 Control (B_CR_LITES3_CTL_0_0_0_MCHBAR)—Offset
6D20h ................................................................................................ 714
5.9.170B-Unit Lites Group 3 Opcode Match Filter
(B_CR_LITES3_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6D24h ............. 716
5.9.171B-Unit Lites Group 3 Agent Match Filter
(B_CR_LITES3_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6D28h................ 718
5.9.172B-Unit Lites Group 3 U2C IntData Match Filter
(B_CR_LITES3_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6D2Ch ....... 720
5.9.173B-Unit Lites Group 3 Address Match Filter LITES3_ADDR_MATCH
(B_CR_LITES3_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6D30h ................. 720
5.9.174B-Unit Lites Group 3 Address Mask Filter LITES3_ADDR_MASK
(B_CR_LITES3_ADDR_MASK_0_0_0_MCHBAR)—Offset 6D38h ................... 721
5.9.175B-Unit Lites Group 3 Data Match Filter LITES3_DATA_MATCH
(B_CR_LITES3_DATA_MATCH_0_0_0_MCHBAR)—Offset 6D40h.................. 722
5.9.176B-Unit Lites Group 3 Data Mask Filter LITES3_DATA_MASK
(B_CR_LITES3_DATA_MASK_0_0_0_MCHBAR)—Offset 6D44h.................... 722
5.9.177B-Unit Lites and Emon Master Control LITESEMONCTL
(B_CR_LITESEMON_CTL_0_0_0_MCHBAR)—Offset 6D48h ......................... 723
5.9.178B-Unit Arbiter Control BARBCTRL0 (B_CR_BARBCTRL0)—Offset 6D4Ch........ 725
5.9.179B-Unit Arbiter Control BARBCTRL1 (B_CR_BARBCTRL1)—Offset 6D50h ........ 726
5.9.180B-Unit Scheduler Control (B_CR_BSCHWT0)—Offset 6D54h ....................... 727
5.9.181B-Unit Scheduler Control (B_CR_BSCHWT1)—Offset 6D58h ....................... 727
5.9.182B-Unit Scheduler Control (B_CR_BSCHWT2)—Offset 6D5Ch ....................... 728
5.9.183B-Unit Scheduler Control (B_CR_BSCHWT3)—Offset 6D60h ....................... 729
5.9.184B-Unit Flush Control (B_CR_BWFLUSH)—Offset 6D64h .............................. 730
5.9.185B-Unit Flush Weights (B_CR_BFLWT)—Offset 6D68h ................................. 731
5.9.186Weighted Scheduling Control of High Priority ISOC and Other Requests
(B_CR_BISOCWT)—Offset 6D6Ch ........................................................... 732
5.9.187B-Unit Control (B_CR_BCTRL2)—Offset 6D70h ......................................... 733
5.9.188Asset Classification Bits (B_CR_AC_RS0_0_0_0_MCHBAR)—Offset 6D74h .... 735
5.9.189IDI Real-Time Feature Configuration Bits (B_CR_RT_EN_0_0_0_MCHBAR)—
Offset 6D78h ....................................................................................... 735
5.9.190B-Unit Control Register 3 (B_CR_BCTRL3)—Offset 6D7Ch .......................... 736
5.9.191Asymmetric Memory Region 0 With No Interleaving Configuration
(B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR)—Offset 6E40h .................. 737
5.9.192Asymmetric Memory Region 1 With No Interleaving Configuration
(B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR)—Offset 6E44h .................. 738
5.9.193B-Unit Machine Check Mode Low (B_CR_BMCMODE_LOW)—Offset 6E48h .... 739
5.9.194B-Unit Machine Check Mode High (B_CR_BMCMODE_HIGH)—Offset 6E4Ch .. 740
5.9.195Two-Way Asymmetric Memory Region Configuration
(B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR)—Offset 6E50h .......... 740
5.10 Registers Summary ......................................................................................... 742
5.10.1 X2B_BARB_CTL1 (X2B_BARB_CTL1_MCHBAR)—Offset 7804h..................... 743
5.10.2 Clock Gating Control (CLKGATE_CTL_MCHBAR)—Offset 7808h ................... 744
5.10.3 Miscellaneous Controls (MISC_CTL_MCHBAR)—Offset 780Ch ...................... 746
5.10.4 CMiscellaneous T2A selector (T2A_SELECTOR_MISC_MCHBAR)—Offset 7818h ....
748
5.10.5 VC Read Ordering CFG (VC_READ_ORDERING_CFG_MCHBAR)—Offset 781Ch.....
749
5.10.6 VC Write Ordering CFG (VC_WRITE_ORDERING_CFG_MCHBAR)—Offset 7820h...
752
5.10.7 IDI0 C2U Credit Control (IDI0_C2U_CREDIT_CTRL_MCHBAR)—Offset 7824h 754
5.10.8 IDI1 C2U Credit Control (IDI1_C2U_CREDIT_CTRL_MCHBAR)—Offset 7828h 756
5.10.9 IDI2 C2U Credit Control (IDI2_C2U_CREDIT_CTRL_MCHBAR)—Offset 782Ch 757
5.10.10IDI3 C2U Credit Control (IDI3_C2U_CREDIT_CTRL_MCHBAR)—Offset 7830h 758
5.10.11IDI4 C2U Credit Control (IDI4_C2U_CREDIT_CTRL_MCHBAR)—Offset 7834h 759

334818 17
 5.10.12IDI5 C2U Credit Control (IDI5_C2U_CREDIT_CTRL_MCHBAR)—Offset 7838h 761
5.10.13IDI6 C2U Credit Control (IDI6_C2U_CREDIT_CTRL_MCHBAR)—Offset 783Ch 762
5.10.14IDI7 C2U Credit Control (IDI7_C2U_CREDIT_CTRL_MCHBAR)—Offset 7840h 763
5.10.15PII2 A2T Credit Control (PII2_A2T_CREDIT_CTRL_MCHBAR)—Offset 7844h .. 765
5.10.16BIOSWR Control Policy (T_CR_BIOSWR_CP_0_0_0_MCHBAR)—Offset 7848h 766
5.10.17BIOSWR Read Access Control (T_CR_BIOSWR_RAC_0_0_0_MCHBAR)—Offset
7850h ................................................................................................. 766
5.10.18BIOSWR Write Access Control (T_CR_BIOSWR_WAC_0_0_0_MCHBAR)—Offset
7858h ................................................................................................. 767
5.10.19TUnit Pcode/Ucode Write, All Read Control Policy Register
(T_CR_P_U_CODEWR_ALLRD_CP_0_0_0_MCHBAR)—Offset 7860h.............. 767
5.10.20TUnit Pcode/Ucode Read Access Control
(T_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCHBAR)—Offset 7868h ........... 768
5.10.21TUnit Pcode/Ucode Write Access Control
(T_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_MCHBAR)—Offset 7870h........... 768
5.11 ..................................................................................................................... 769
5.12 Registers Summary.......................................................................................... 771
5.12.1 Address Decode Repeats (CPGC2_ADDRESS_CONTROL)—Offset 3C18h ....... 779
5.12.2 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[0])—Offset 3C1Ch .... 780
5.12.3 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[1])—Offset 3C1Dh .... 782
5.12.4 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[2])—Offset 3C1Eh .... 783
5.12.5 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[3])—Offset 3C1Fh .... 785
5.12.6 Data Instruction (CPGC2_DATA_INSTRUCTION[0])—Offset 3C20h............... 787
5.12.7 Data Instruction (CPGC2_DATA_INSTRUCTION[1])—Offset 3C21h............... 788
5.12.8 Data Instruction (CPGC2_DATA_INSTRUCTION[2])—Offset 3C22h............... 789
5.12.9 Data Instruction (CPGC2_DATA_INSTRUCTION[3])—Offset 3C23h............... 790
5.12.10Data Rotation Repeats (CPGC2_DATA_CONTROL)—Offset 3C24h................. 791
5.12.11Address and Data Repeats Status (CPGC2_ADDRESS_DATA_STATUS)—Offset
3C28h ................................................................................................. 792
5.12.12Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[0])—Offset 3C2Ch ...
793
5.12.13Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[1])—Offset 3C2Dh ...
794
5.12.14Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[2])—Offset 3C2Eh ...
795
5.12.15Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[3])—Offset 3C2Fh....
796
5.12.16Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[4])—Offset 3C30h ...
797
5.12.17Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[5])—Offset 3C31h ...
798
5.12.18Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[6])—Offset 3C32h ...
799
5.12.19Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[7])—Offset 3C33h ...
800
5.12.20Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[0])—
Offset 3C34h........................................................................................ 801
5.12.21Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[1])—
Offset 3C35h........................................................................................ 804
5.12.22Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[2])—
Offset 3C36h........................................................................................ 809
5.12.23Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[3])—
Offset 3C37h........................................................................................ 811
5.12.24Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[4])—
Offset 3C38h........................................................................................ 813

18 334818
 5.12.25Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[5])—
Offset 3C39h ....................................................................................... 815
5.12.26Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[6])—
Offset 3C3Ah ....................................................................................... 817
5.12.27Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[7])—
Offset 3C3Bh ....................................................................................... 819
5.12.28Wait Timer Current (CPGC2_ALGORITHM_WAIT_COUNT_CURRENT)—Offset
3C3Ch ................................................................................................ 821
5.12.29Algorithm Wait Event Control (CPGC2_ALGORITHM_WAIT_EVENT_CONTROL)—
Offset 3C40h ....................................................................................... 821
5.12.30Base Repeats (CPGC2_BASE_REPEATS)—Offset 3C44h.............................. 822
5.12.31Current Base Repeats (CPGC2_BASE_REPEATS_CURRENT)—Offset 3C48h ... 823
5.12.32Base Column Repeats (CPGC2_BASE_COL_REPEATS)—Offset 3C4Ch........... 824
5.12.33Block Repeats (CPGC2_BLOCK_REPEATS)—Offset 3C50h ........................... 824
5.12.34Current Block Repeats (CPGC2_BLOCK_REPEATS_CURRENT)—Offset 3C54h 825
5.12.35Command Instruction (CPGC2_COMMAND_INSTRUCTION[0])—Offset 3C58h 825
5.12.36Command Instruction (CPGC2_COMMAND_INSTRUCTION[1])—Offset 3C59h 827
5.12.37Command Instruction (CPGC2_COMMAND_INSTRUCTION[2])—Offset 3C5Ah 828
5.12.38Command Instruction (CPGC2_COMMAND_INSTRUCTION[3])—Offset 3C5Bh 829
5.12.39Command Instruction (CPGC2_COMMAND_INSTRUCTION[4])—Offset 3C5Ch 831
5.12.40Command Instruction (CPGC2_COMMAND_INSTRUCTION[5])—Offset 3C5Dh 832
5.12.41Command Instruction (CPGC2_COMMAND_INSTRUCTION[6])—Offset 3C5Eh 834
5.12.42Command Instruction (CPGC2_COMMAND_INSTRUCTION[7])—Offset 3C5Fh 835
5.12.43Command Instruction (CPGC2_COMMAND_INSTRUCTION[8])—Offset 3C60h 836
5.12.44Command Instruction (CPGC2_COMMAND_INSTRUCTION[9])—Offset 3C61h 838
5.12.45Command Instruction (CPGC2_COMMAND_INSTRUCTION[10])—Offset 3C62h....
839
5.12.46Command Instruction (CPGC2_COMMAND_INSTRUCTION[11])—Offset 3C63h....
841
5.12.47Command Instruction (CPGC2_COMMAND_INSTRUCTION[12])—Offset 3C64h....
842
5.12.48Command Instruction (CPGC2_COMMAND_INSTRUCTION[13])—Offset 3C65h....
843
5.12.49Command Instruction (CPGC2_COMMAND_INSTRUCTION[14])—Offset 3C66h....
845
5.12.50Command Instruction (CPGC2_COMMAND_INSTRUCTION[15])—Offset 3C67h....
846
5.12.51Command Instruction (CPGC2_COMMAND_INSTRUCTION[16])—Offset 3C68h....
848
5.12.52Command Instruction (CPGC2_COMMAND_INSTRUCTION[17])—Offset 3C69h....
849
5.12.53Command Instruction (CPGC2_COMMAND_INSTRUCTION[18])—Offset 3C6Ah....
850
5.12.54Command Instruction (CPGC2_COMMAND_INSTRUCTION[19])—Offset 3C6Bh....
852
5.12.55Command Instruction (CPGC2_COMMAND_INSTRUCTION[20])—Offset 3C6Ch....
853
5.12.56Command Instruction (CPGC2_COMMAND_INSTRUCTION[21])—Offset 3C6Dh ...
855
5.12.57Command Instruction (CPGC2_COMMAND_INSTRUCTION[22])—Offset 3C6Eh....
856
5.12.58Command Instruction (CPGC2_COMMAND_INSTRUCTION[23])—Offset 3C6Fh ....
857
5.12.59Hammer Repeats (CPGC2_HAMMER_REPEATS)—Offset 3C70h.................... 859
5.12.60Current Hammer Repeats (CPGC2_HAMMER_REPEATS_CURRENT)—Offset 3C74h
859

334818 19
 5.12.61Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[0])—
Offset 3C78h........................................................................................ 860
5.12.62Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[1])—
Offset 3C79h........................................................................................ 861
5.12.63Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[2])—
Offset 3C7Ah........................................................................................ 863
5.12.64Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[3])—
Offset 3C7Bh........................................................................................ 864
5.12.65Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[4])—
Offset 3C7Ch ....................................................................................... 866
5.12.66Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[5])—
Offset 3C7Dh ....................................................................................... 867
5.12.67Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[6])—
Offset 3C7Eh........................................................................................ 869
5.12.68Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[7])—
Offset 3C7Fh ........................................................................................ 870
5.12.69Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[8])—
Offset 3C80h........................................................................................ 872
5.12.70Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[9])—
Offset 3C81h........................................................................................ 873
5.12.71Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[10])—
Offset 3C82h........................................................................................ 875
5.12.72Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[11])—
Offset 3C83h........................................................................................ 876
5.12.73Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[12])—
Offset 3C84h........................................................................................ 878
5.12.74Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[13])—
Offset 3C85h........................................................................................ 879
5.12.75Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[14])—
Offset 3C86h........................................................................................ 881
5.12.76Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[15])—
Offset 3C87h........................................................................................ 882
5.12.77Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[0])—
Offset 3C88h........................................................................................ 884
5.12.78Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[1])—
Offset 3C89h........................................................................................ 885
5.12.79Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[2])—
Offset 3C8Ah........................................................................................ 886
5.12.80Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[3])—
Offset 3C8Bh........................................................................................ 887
5.12.81Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[4])—
Offset 3C8Ch ....................................................................................... 888
5.12.82Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[5])—
Offset 3C8Dh ....................................................................................... 889
5.12.83Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[6])—
Offset 3C8Eh........................................................................................ 890
5.12.84Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[7])—
Offset 3C8Fh ........................................................................................ 892
5.12.85Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[8])—
Offset 3C90h........................................................................................ 893
5.12.86Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[9])—
Offset 3C91h........................................................................................ 894
5.12.87Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[10])—
Offset 3C92h........................................................................................ 895
5.12.88Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[11])—
Offset 3C93h........................................................................................ 896
5.12.89Offset Repeats (CPGC2_OFFSET_REPEATS[0])—Offset 3C94h ..................... 897

20 334818
 5.12.90Offset Repeats (CPGC2_OFFSET_REPEATS[1])—Offset 3C98h .................... 898
5.12.91Current Offset Repeats (CPGC2_OFFSET_REPEATS_CURRENT)—Offset 3C9Ch ....
898
5.12.92Region Low Row Address (CPGC2_REGION_LOW_ROW)—Offset 3CA0h ....... 899
5.12.93Region Low Col Address (CPGC2_REGION_LOW_COL)—Offset 3CA4h .......... 899
5.12.94Block Low Row Current (CPGC2_BLOCK_ORIGIN_ROW_CURRENT)—Offset 3CA8h
900
5.12.95Current Base Address Rank and Column
(CPGC2_BASE_ADDRESS_COL_RANK_CURRENT)—Offset 3CACh ................ 901
5.12.96Current Base Address Bank and Row
(CPGC2_BASE_ADDRESS_ROW_BANK_CURRENT)—Offset 3CB0h ............... 901
5.12.97Current Offset Address Column (CPGC2_OFFSET_ADDRESS_COL_CURRENT)—
Offset 3CB4h ....................................................................................... 902
5.12.98Current Offset Address Row (CPGC2_OFFSET_ADDRESS_ROW_CURRENT)—
Offset 3CB8h ....................................................................................... 903
5.12.99Address Size (CPGC2_ADDRESS_SIZE)—Offset 3CBCh .............................. 903
5.12.100Base Address Control (CPGC2_BASE_ADDRESS_CONTROL)—Offset 3CC0h . 905
5.12.101Address PRBS Control (CPGC2_ADDRESS_PRBS_CONTROL)—Offset 3CC4h 906
5.12.102Address PRBS Seed (CPGC2_ADDRESS_PRBS_SEED)—Offset 3CC8h ......... 908
5.12.103Current Address PRBS Status (CPGC2_ADDRESS_PRBS_CURRENT)—Offset
3CCCh ................................................................................................ 909
5.12.104Address PRBS Save (CPGC2_ADDRESS_PRBS_SAVE)—Offset 3CD0h ......... 909
5.12.105Command FSM Current State (CPGC2_CMD_FSM_CURRENT)—Offset 3CD4h.....
910
5.12.106Algorithm Wait Timer Configuration (CPGC2_WAIT_2_START_CONFIG)—Offset
3CD8h ................................................................................................ 911
5.12.107VISA Mux Selection (CPGC2_VISA_MUX_SEL)—Offset 3CDCh ................... 912
5.12.108Loopback Squencer Configuration (CPGC_LB_SEQ_CFG)—Offset 3CE0h ..... 913
5.12.109Loopback Sequencer Control (CPGC_LB_SEQ_CTL)—Offset 3CE4h ............. 915
5.12.110Loopback Loopcount Tx Status (CPGC_LB_SEQ_LOOPCOUNT_TX_STATUS)—
Offset 3CE8h ....................................................................................... 917
5.12.111Loopback Loopcount Rx Status (CPGC_LB_SEQ_LOOPCOUNT_RX_STATUS)—
Offset 3CECh ....................................................................................... 918
5.12.112Pattern Length Status (CPGC_LB_SEQ_PL_RX_STATUS)—Offset 3CF0h ...... 918
5.12.113Refresh Control (CPGC_MISC_REFRESH_CTL)—Offset 3CF4h .................... 919
5.12.114ZQ Control (CPGC_MISC_ZQ_CTL)—Offset 3CF8h ................................... 920
5.12.115ODT Control (CPGC_MISC_ODT_CTL)—Offset 3CFCh ............................... 920
5.12.116CKE Control (CPGC_MISC_CKE_CTL)—Offset 3D00h ................................ 921
5.12.117Command Rate (CPGC_MISC_CMD_RATE)—Offset 3D04h ........................ 922
5.12.118External Trigger Control (CPGC_MISC_EXT_TRIGGER)—Offset 3D08h ........ 923
5.12.119Sequence Control (CPGC_SEQ_CTL)—Offset 3D0Ch................................. 923
5.12.120Sequence Configuration A (CPGC_SEQ_CFG_A)—Offset 3D10h ................. 924
5.12.121Sequence Configuration B (CPGC_SEQ_CFG_B)—Offset 3D14h ................. 927
5.12.122Sequence Status (CPGC_SEQ_STATUS)—Offset 3D18h ............................ 927
5.12.123Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[0])—Offset
3D20h ................................................................................................ 928
5.12.124Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[1])—Offset
3D24h ................................................................................................ 929
5.12.125Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[2])—Offset
3D28h ................................................................................................ 929
5.12.126Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[3])—Offset
3D2Ch ................................................................................................ 930
5.12.127Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[4])—Offset
3D30h ................................................................................................ 930
5.12.128Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[5])—Offset
3D34h ................................................................................................ 931

334818 21
 5.12.129Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[6])—Offset
3D38h................................................................................................. 932
5.12.130Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[7])—Offset
3D3Ch ................................................................................................ 932
5.12.131Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[8])—Offset
3D40h................................................................................................. 933
5.12.132Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[9])—Offset
3D44h................................................................................................. 933
5.12.133Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[10])—Offset
3D48h................................................................................................. 934
5.12.134Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[11])—Offset
3D4Ch ................................................................................................ 935
5.12.135Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[12])—Offset
3D50h................................................................................................. 935
5.12.136Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[13])—Offset
3D54h................................................................................................. 936
5.12.137Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[14])—Offset
3D58h................................................................................................. 936
5.12.138Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[15])—Offset
3D5Ch ................................................................................................ 937
5.12.139Mode3 Fail Status LSB (CPGC2_RASTER_REPO_CONTENT_ECC1)—Offset 3D60h
938
5.12.140Mode3 Fail Status MSB (CPGC2_RASTER_REPO_CONTENT_ECC2)—Offset
3D64h................................................................................................. 939
5.12.141Read Command Count (CPGC2_READ_COMMAND_COUNT_CURRENT)—Offset
3D68h................................................................................................. 941
5.12.142Mask Errors on First N Reads (CPGC2_MASK_ERRS_FIRST_N_READS)—Offset
3D6Ch ................................................................................................ 941
5.12.143Raster Repository Status (CPGC2_RASTER_REPO_STATUS)—Offset 3D70h . 942
5.12.144Error Summary A (CPGC2_ERR_SUMMARY_A)—Offset 3D74h.................... 943
5.12.145Error Summary B (CPGC2_ERR_SUMMARY_B)—Offset 3D78h.................... 944
5.12.146Future use Reserved (CPGC2_ERR_SUMMARY_C)—Offset 3D7Ch ............... 945
5.12.147Data Pattern Generation Buffer Control (CPGC_DPAT_BUF_CTL)—Offset 3D80h
945
5.12.148Data Pattern Generation Configuration (CPGC_DPAT_CFG)—Offset 3D84h .. 947
5.12.149LFSR Configuration and Lane Rotate (CPGC_DPAT_XTRA_LFSR_CFG)—Offset
3D88h................................................................................................. 951
5.12.150Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[0])—Offset 3D8Ch 953
5.12.151Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[1])—Offset 3D90h 954
5.12.152Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[2])—Offset 3D94h 955
5.12.153Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[0])—Offset 3D98h .. 955
5.12.154Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[1])—Offset 3D9Ch.. 959
5.12.155Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[2])—Offset 3DA0h .. 962
5.12.156Invert and DC Control (CPGC_DPAT_INVDCCTL)—Offset 3DA4h ................ 965
5.12.157Data Invert/DC Enable Low (CPGC_DPAT_INV_DC_MASK_LO)—Offset 3DA8h ..
966
5.12.158Data Invert/DC Enable High (CPGC_DPAT_INV_DC_MASK_HI)—Offset 3DACh ..
967
5.12.159Byte Enable Mask Lower (CPGC_DPAT_DRAMDM)—Offset 3DB0h ............... 967
5.12.160Byte Enable Mask Upper (CPGC_DPAT_XDRAMDM)—Offset 3DB4h ............. 968
5.12.161Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[0])—Offset 3DB8h
969
5.12.162Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[1])—Offset 3DBCh
969
5.12.163Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[2])—Offset 3DC0h
970

22 334818
 5.12.164Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[0])—Offset 3DC4h
970
5.12.165Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[1])—Offset 3DC8h
971
5.12.166Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[2])—Offset 3DCCh
972
5.12.167LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[0])—Offset 3DD0h........... 973
5.12.168LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[1])—Offset 3DD4h........... 974
5.12.169LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[2])—Offset 3DD8h........... 974
5.12.170LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[0])—Offset 3DDCh ........... 975
5.12.171LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[1])—Offset 3DE0h ............ 975
5.12.172LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[2])—Offset 3DE4h ............ 976
5.12.173Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[0])—Offset
3DE8h ................................................................................................ 976
5.12.174Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[1])—Offset
3DECh ................................................................................................ 977
5.12.175Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[2])—Offset
3DF0h ................................................................................................ 977
5.12.176Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[0])—Offset
3DF4h ................................................................................................ 978
5.12.177Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[1])—Offset
3DF8h ................................................................................................ 979
5.12.178Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[2])—Offset
3DFCh ................................................................................................ 980
5.12.179Extended Pattern Buffer (CPGC_DPAT_EXTBUF[0])—Offset 3E00h ............. 981
5.12.180Extended Pattern Buffer (CPGC_DPAT_EXTBUF[1])—Offset 3E04h ............. 982
5.12.181Extended Pattern Buffer (CPGC_DPAT_EXTBUF[2])—Offset 3E08h ............. 983
5.12.182Extended Pattern Buffer (CPGC_DPAT_EXTBUF[3])—Offset 3E0Ch ............. 984
5.12.183Extended Pattern Buffer (CPGC_DPAT_EXTBUF[4])—Offset 3E10h ............. 984
5.12.184Extended Pattern Buffer (CPGC_DPAT_EXTBUF[5])—Offset 3E14h ............. 985
5.12.185Extended Pattern Buffer (CPGC_DPAT_EXTBUF[6])—Offset 3E18h ............. 986
5.12.186Extended Pattern Buffer (CPGC_DPAT_EXTBUF[7])—Offset 3E1Ch ............. 987
5.12.187Extended Pattern Buffer (CPGC_DPAT_EXTBUF[8])—Offset 3E20h ............. 988
5.12.188Extended Pattern Buffer (CPGC_DPAT_EXTBUF[9])—Offset 3E24h ............. 989
5.12.189Extended Pattern Buffer (CPGC_DPAT_EXTBUF[10])—Offset 3E28h ........... 989
5.12.190Extended Pattern Buffer (CPGC_DPAT_EXTBUF[11])—Offset 3E2Ch ........... 990
5.12.191Extended Pattern Buffer (CPGC_DPAT_EXTBUF[12])—Offset 3E30h ........... 991
5.12.192Extended Pattern Buffer (CPGC_DPAT_EXTBUF[13])—Offset 3E34h ........... 992
5.12.193Extended Pattern Buffer (CPGC_DPAT_EXTBUF[14])—Offset 3E38h ........... 993
5.12.194Extended Pattern Buffer (CPGC_DPAT_EXTBUF[15])—Offset 3E3Ch ........... 994
5.12.195Error Checker Control (CPGC_ERR_CTL)—Offset 3E40h ............................ 994
5.12.196Lane Error Mask Lower Bytes (CPGC_ERR_LNEN_LO)—Offset 3E44h .......... 996
5.12.197Lane Error Mask Upper Bytes or Extended Chunk Enable
(CPGC_ERR_LNEN_HI)—Offset 3E48h ..................................................... 997
5.12.198Lane Error Mask ECC (CPGC_ERR_XLNEN)—Offset 3E4Ch......................... 998
5.12.199Lane Error Status Lower Bytes (CPGC_ERR_STAT03)—Offset 3E50h .......... 998
5.12.200Lane Error Status Upper Bytes or Extended Chunk Error Status
(CPGC_ERR_STAT47)—Offset 3E54h ....................................................... 999
5.12.201ECC Lane Error Status (CPGC_ERR_ECC_CHNK_RANK_STAT)—Offset 3E58h.....
1000
5.12.202ByteGroup Error Status (CPGC_ERR_BYTE_NTH_PAR_STAT)—Offset 3E5Ch ......
1001
5.12.203Error Counter Control (CPGC_ERR_CNTRCTL[0])—Offset 3E60h ...............1002
5.12.204Error Counter Control (CPGC_ERR_CNTRCTL[1])—Offset 3E64h ...............1003
5.12.205Error Counter Control (CPGC_ERR_CNTRCTL[2])—Offset 3E68h ...............1004
5.12.206Error Counter Control (CPGC_ERR_CNTRCTL[3])—Offset 3E6Ch ...............1005

334818 23
 5.12.207Error Counter Control (CPGC_ERR_CNTRCTL[4])—Offset 3E70h............... 1006
5.12.208Error Counter Control (CPGC_ERR_CNTRCTL[5])—Offset 3E74h............... 1007
5.12.209Error Counter Control (CPGC_ERR_CNTRCTL[6])—Offset 3E78h............... 1008
5.12.210Error Counter Control (CPGC_ERR_CNTRCTL[7])—Offset 3E7Ch............... 1009
5.12.211Error Counter Control (CPGC_ERR_CNTRCTL[8])—Offset 3E80h............... 1010
5.12.212Error Counter (CPGC_ERR_CNTR[0])—Offset 3E84h ............................... 1011
5.12.213Error Counter (CPGC_ERR_CNTR[1])—Offset 3E88h ............................... 1012
5.12.214Error Counter (CPGC_ERR_CNTR[2])—Offset 3E8Ch............................... 1013
5.12.215Error Counter (CPGC_ERR_CNTR[3])—Offset 3E90h ............................... 1014
5.12.216Error Counter (CPGC_ERR_CNTR[4])—Offset 3E94h ............................... 1014
5.12.217Error Counter (CPGC_ERR_CNTR[5])—Offset 3E98h ............................... 1015
5.12.218Error Counter (CPGC_ERR_CNTR[6])—Offset 3E9Ch............................... 1016
5.12.219Error Counter (CPGC_ERR_CNTR[7])—Offset 3EA0h............................... 1016
5.12.220Error Counter (CPGC_ERR_CNTR[8])—Offset 3EA4h............................... 1017
5.12.221Error Counter Overflow (CPGC_ERR_CNTR_OV)—Offset 3EA8h ................ 1018
5.12.222Error Log Control and Status (CPGC_ERRLOG_CTL_STAT)—Offset 3EACh.. 1019
5.12.223Error Log Data Access (CPGC_ERRLOG_DATA)—Offset 3EB0h ................. 1020
5.12.224Loopback Error Status (CPGC_ERR_TEST_ERR_STAT)—Offset 3EB4h ....... 1021
5.12.225Rank Logical To Physical Map (CPGC_SEQ_RANK_L2P_MAPPING)—Offset 3EB8h
1022
5.12.226Bank Logical to Physical Map Low (CPGC_SEQ_BANK_L2P_MAPPING_A)—Offset
3EBCh............................................................................................... 1023
5.12.227Bank Logical to Physical Map High (CPGC_SEQ_BANK_L2P_MAPPING_B)—Offset
3EC0h ............................................................................................... 1024
5.12.228Rank Address Swizzle (CPGC_SEQ_RANK_ADDR_SWIZZLE)—Offset 3EC4h1026
5.12.229Bank Address Swizzle (CPGC_SEQ_BANK_ADDR_SWIZZLE)—Offset 3EC8h1027
5.12.230Row Address Swizzle Low (CPGC_SEQ_ROW_ADDR_SWIZZLE_A)—Offset 3ECCh
1027
5.12.231Row Address Swizzle Mid (CPGC_SEQ_ROW_ADDR_SWIZZLE_B)—Offset 3ED0h
1029
5.12.232Row Address Swizzle High (CPGC_SEQ_ROW_ADDR_SWIZZLE_C)—Offset
3ED4h............................................................................................... 1030
5.12.233Row Address XOR (CPGC_SEQ_ROW_ADDR_SWIZZLE_X)—Offset 3ED8h . 1031
5.12.234Column Address Swizzle Low (CPGC_SEQ_COL_ADDR_SWIZZLE_A)—Offset
3EDCh .............................................................................................. 1032
5.12.235Column Address Swizzle High (CPGC_SEQ_COL_ADDR_SWIZZLE_B)—Offset
3EE0h ............................................................................................... 1033
5.12.236DQ Inversion Lookup Data Low (CPGC_SEQ_ROW_ADDR_DQ_MAP0)—Offset
3EE8h ............................................................................................... 1034
5.12.237DQ Inversion Lookup Data High (CPGC_SEQ_ROW_ADDR_DQ_MAP1)—Offset
3EECh ............................................................................................... 1035
5.13 Registers Summary........................................................................................ 1037
5.13.1 CADB Control (CPGC_CADB_CTL)—Offset 42F0h ..................................... 1038
5.13.2 CADB MRS Configuration (CPGC_CADB_MRSCFG)—Offset 42F4h............... 1041
5.13.3 CADB Configuration (CPGC_CADB_CFG)—Offset 42F8h ............................ 1042
5.13.4 CADB Unisequencer 0 Pattern Buffer (CPGC_CADB_UNISEQ0_PBUF)—Offset
42FCh ............................................................................................... 1043
5.13.5 CADB Unisequencer 1 Pattern Buffer (CPGC_CADB_UNISEQ1_PBUF)—Offset
4300h ............................................................................................... 1044
5.13.6 CADB Unisequencer 2 Pattern Buffer (CPGC_CADB_UNISEQ2_PBUF)—Offset
4304h ............................................................................................... 1044
5.13.7 CADB LMN 0 Settings (CPGC_CADB_UNISEQ0_LMN)—Offset 4308h........... 1045
5.13.8 CADB LMN 1 Settings (CPGC_CADB_UNISEQ1_LMN)—Offset 430Ch .......... 1046
5.13.9 CADB LMN 2 Settings (CPGC_CADB_UNISEQ2_LMN)—Offset 4310h........... 1047
5.13.10CADB Select Unisequencer 0 Pattern Buffer
(CPGC_CADB_SEL_UNISEQ0_PBUF)—Offset 4314h ................................. 1048

24 334818
 5.13.11CADB Select Unisequencer 1 Pattern Buffer
(CPGC_CADB_SEL_UNISEQ1_PBUF)—Offset 4318h..................................1049
5.13.12CADB Select Unisequencer 2 Pattern Buffer
(CPGC_CADB_SEL_UNISEQ2_PBUF)—Offset 431Ch..................................1049
5.13.13CADB Buffer A (CPGC_CADB_BUFA[0])—Offset 4320h..............................1050
5.13.14CADB Buffer A (CPGC_CADB_BUFA[1])—Offset 4324h..............................1050
5.13.15CADB Buffer A (CPGC_CADB_BUFA[2])—Offset 4328h..............................1051
5.13.16CADB Buffer A (CPGC_CADB_BUFA[3])—Offset 432Ch .............................1052
5.13.17CADB Buffer A (CPGC_CADB_BUFA[4])—Offset 4330h..............................1053
5.13.18CADB Buffer A (CPGC_CADB_BUFA[5])—Offset 4334h..............................1053
5.13.19CADB Buffer A (CPGC_CADB_BUFA[6])—Offset 4338h..............................1054
5.13.20CADB Buffer A (CPGC_CADB_BUFA[7])—Offset 433Ch .............................1055
5.13.21CADB Buffer B (CPGC_CADB_BUFB[0])—Offset 4340h..............................1055
5.13.22CADB Buffer B (CPGC_CADB_BUFB[1])—Offset 4344h..............................1056
5.13.23CADB Buffer B (CPGC_CADB_BUFB[2])—Offset 4348h..............................1057
5.13.24CADB Buffer B (CPGC_CADB_BUFB[3])—Offset 434Ch .............................1058
5.13.25CADB Buffer B (CPGC_CADB_BUFB[4])—Offset 4350h..............................1059
5.13.26CADB Buffer B (CPGC_CADB_BUFB[5])—Offset 4354h..............................1060
5.13.27CADB Buffer B (CPGC_CADB_BUFB[6])—Offset 4358h..............................1061
5.13.28CADB Buffer B (CPGC_CADB_BUFB[7])—Offset 435Ch .............................1062
5.13.29CADB Deselect Uniseq 0 Status (CPGC_CADB_UNISEQ0STAT)—Offset 4360h .....
1063
5.13.30CADB Deselect Uniseq 1 Status (CPGC_CADB_UNISEQ1STAT)—Offset 4364h .....
1064
5.13.31CADB Deselect Uniseq 2 Status (CPGC_CADB_UNISEQ2STAT)—Offset 4368h .....
1064
5.14 Registers Summary ........................................................................................1067
5.14.1 Address Decode Repeats (CPGC2_ADDRESS_CONTROL)—Offset 4018h ......1075
5.14.2 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[0])—Offset 401Ch...1076
5.14.3 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[1])—Offset 401Dh...1078
5.14.4 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[2])—Offset 401Eh ...1079
5.14.5 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[3])—Offset 401Fh ...1081
5.14.6 Data Instruction (CPGC2_DATA_INSTRUCTION[0])—Offset 4020h .............1083
5.14.7 Data Instruction (CPGC2_DATA_INSTRUCTION[1])—Offset 4021h .............1084
5.14.8 Data Instruction (CPGC2_DATA_INSTRUCTION[2])—Offset 4022h .............1085
5.14.9 Data Instruction (CPGC2_DATA_INSTRUCTION[3])—Offset 4023h .............1086
5.14.10Data Rotation Repeats (CPGC2_DATA_CONTROL)—Offset 4024h ...............1087
5.14.11Address and Data Repeats Status (CPGC2_ADDRESS_DATA_STATUS)—Offset
4028h................................................................................................1088
5.14.12Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[0])—Offset 402Ch ....
1089
5.14.13Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[1])—Offset 402Dh ....
1090
5.14.14Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[2])—Offset 402Eh ....
1091
5.14.15Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[3])—Offset 402Fh ....
1092
5.14.16Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[4])—Offset 4030h ....
1093
5.14.17Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[5])—Offset 4031h ....
1094
5.14.18Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[6])—Offset 4032h ....
1095
5.14.19Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[7])—Offset 4033h ....
1096

334818 25
 5.14.20Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[0])—
Offset 4034h ...................................................................................... 1097
5.14.21Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[1])—
Offset 4035h ...................................................................................... 1100
5.14.22Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[2])—
Offset 4036h ...................................................................................... 1105
5.14.23Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[3])—
Offset 4037h ...................................................................................... 1107
5.14.24Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[4])—
Offset 4038h ...................................................................................... 1109
5.14.25Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[5])—
Offset 4039h ...................................................................................... 1111
5.14.26Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[6])—
Offset 403Ah...................................................................................... 1113
5.14.27Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[7])—
Offset 403Bh...................................................................................... 1115
5.14.28Wait Timer Current (CPGC2_ALGORITHM_WAIT_COUNT_CURRENT)—Offset
403Ch ............................................................................................... 1117
5.14.29Algorithm Wait Event Control (CPGC2_ALGORITHM_WAIT_EVENT_CONTROL)—
Offset 4040h ...................................................................................... 1117
5.14.30Base Repeats (CPGC2_BASE_REPEATS)—Offset 4044h ............................ 1118
5.14.31Current Base Repeats (CPGC2_BASE_REPEATS_CURRENT)—Offset 4048h .. 1119
5.14.32Base Column Repeats (CPGC2_BASE_COL_REPEATS)—Offset 404Ch ......... 1120
5.14.33Block Repeats (CPGC2_BLOCK_REPEATS)—Offset 4050h ......................... 1120
5.14.34Current Block Repeats (CPGC2_BLOCK_REPEATS_CURRENT)—Offset 4054h1121
5.14.35Command Instruction (CPGC2_COMMAND_INSTRUCTION[0])—Offset 4058h .....
1121
5.14.36Command Instruction (CPGC2_COMMAND_INSTRUCTION[1])—Offset 4059h .....
1123
5.14.37Command Instruction (CPGC2_COMMAND_INSTRUCTION[2])—Offset 405Ah .....
1124
5.14.38Command Instruction (CPGC2_COMMAND_INSTRUCTION[3])—Offset 405Bh .....
1125
5.14.39Command Instruction (CPGC2_COMMAND_INSTRUCTION[4])—Offset 405Ch .....
1127
5.14.40Command Instruction (CPGC2_COMMAND_INSTRUCTION[5])—Offset 405Dh.....
1128
5.14.41Command Instruction (CPGC2_COMMAND_INSTRUCTION[6])—Offset 405Eh .....
1130
5.14.42Command Instruction (CPGC2_COMMAND_INSTRUCTION[7])—Offset 405Fh .....
1131
5.14.43Command Instruction (CPGC2_COMMAND_INSTRUCTION[8])—Offset 4060h .....
1132
5.14.44Command Instruction (CPGC2_COMMAND_INSTRUCTION[9])—Offset 4061h .....
1134
5.14.45Command Instruction (CPGC2_COMMAND_INSTRUCTION[10])—Offset 4062h ...
1135
5.14.46Command Instruction (CPGC2_COMMAND_INSTRUCTION[11])—Offset 4063h ...
1137
5.14.47Command Instruction (CPGC2_COMMAND_INSTRUCTION[12])—Offset 4064h ...
1138
5.14.48Command Instruction (CPGC2_COMMAND_INSTRUCTION[13])—Offset 4065h ...
1139
5.14.49Command Instruction (CPGC2_COMMAND_INSTRUCTION[14])—Offset 4066h ...
1141
5.14.50Command Instruction (CPGC2_COMMAND_INSTRUCTION[15])—Offset 4067h ...
1142

26 334818
 5.14.51Command Instruction (CPGC2_COMMAND_INSTRUCTION[16])—Offset 4068h ....
1144
5.14.52Command Instruction (CPGC2_COMMAND_INSTRUCTION[17])—Offset 4069h ....
1145
5.14.53Command Instruction (CPGC2_COMMAND_INSTRUCTION[18])—Offset 406Ah....
1146
5.14.54Command Instruction (CPGC2_COMMAND_INSTRUCTION[19])—Offset 406Bh....
1148
5.14.55Command Instruction (CPGC2_COMMAND_INSTRUCTION[20])—Offset 406Ch....
1149
5.14.56Command Instruction (CPGC2_COMMAND_INSTRUCTION[21])—Offset 406Dh ...
1151
5.14.57Command Instruction (CPGC2_COMMAND_INSTRUCTION[22])—Offset 406Eh ....
1152
5.14.58Command Instruction (CPGC2_COMMAND_INSTRUCTION[23])—Offset 406Fh ....
1153
5.14.59Hammer Repeats (CPGC2_HAMMER_REPEATS)—Offset 4070h...................1155
5.14.60Current Hammer Repeats (CPGC2_HAMMER_REPEATS_CURRENT)—Offset 4074h
1155
5.14.61Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[0])—
Offset 4078h ......................................................................................1156
5.14.62Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[1])—
Offset 4079h ......................................................................................1157
5.14.63Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[2])—
Offset 407Ah ......................................................................................1159
5.14.64Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[3])—
Offset 407Bh ......................................................................................1160
5.14.65Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[4])—
Offset 407Ch ......................................................................................1162
5.14.66Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[5])—
Offset 407Dh ......................................................................................1163
5.14.67Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[6])—
Offset 407Eh ......................................................................................1165
5.14.68Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[7])—
Offset 407Fh.......................................................................................1166
5.14.69Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[8])—
Offset 4080h ......................................................................................1168
5.14.70Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[9])—
Offset 4081h ......................................................................................1169
5.14.71Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[10])—
Offset 4082h ......................................................................................1171
5.14.72Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[11])—
Offset 4083h ......................................................................................1172
5.14.73Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[12])—
Offset 4084h ......................................................................................1174
5.14.74Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[13])—
Offset 4085h ......................................................................................1175
5.14.75Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[14])—
Offset 4086h ......................................................................................1177
5.14.76Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[15])—
Offset 4087h ......................................................................................1178
5.14.77Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[0])—
Offset 4088h ......................................................................................1180
5.14.78Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[1])—
Offset 4089h ......................................................................................1181
5.14.79Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[2])—
Offset 408Ah ......................................................................................1182

334818 27
 5.14.80Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[3])—
Offset 408Bh...................................................................................... 1183
5.14.81Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[4])—
Offset 408Ch...................................................................................... 1184
5.14.82Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[5])—
Offset 408Dh ..................................................................................... 1185
5.14.83Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[6])—
Offset 408Eh ...................................................................................... 1186
5.14.84Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[7])—
Offset 408Fh ...................................................................................... 1188
5.14.85Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[8])—
Offset 4090h ...................................................................................... 1189
5.14.86Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[9])—
Offset 4091h ...................................................................................... 1190
5.14.87Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[10])—
Offset 4092h ...................................................................................... 1191
5.14.88Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[11])—
Offset 4093h ...................................................................................... 1192
5.14.89Offset Repeats (CPGC2_OFFSET_REPEATS[0])—Offset 4094h ................... 1193
5.14.90Offset Repeats (CPGC2_OFFSET_REPEATS[1])—Offset 4098h ................... 1194
5.14.91Current Offset Repeats (CPGC2_OFFSET_REPEATS_CURRENT)—Offset 409Ch ....
1194
5.14.92Region Low Row Address (CPGC2_REGION_LOW_ROW)—Offset 40A0h ...... 1195
5.14.93Region Low Col Address (CPGC2_REGION_LOW_COL)—Offset 40A4h......... 1195
5.14.94Block Low Row Current (CPGC2_BLOCK_ORIGIN_ROW_CURRENT)—Offset 40A8h
1196
5.14.95Current Base Address Rank and Column
(CPGC2_BASE_ADDRESS_COL_RANK_CURRENT)—Offset 40ACh............... 1197
5.14.96Current Base Address Bank and Row
(CPGC2_BASE_ADDRESS_ROW_BANK_CURRENT)—Offset 40B0h.............. 1197
5.14.97Current Offset Address Column (CPGC2_OFFSET_ADDRESS_COL_CURRENT)—
Offset 40B4h...................................................................................... 1198
5.14.98Current Offset Address Row (CPGC2_OFFSET_ADDRESS_ROW_CURRENT)—
Offset 40B8h...................................................................................... 1199
5.14.99Address Size (CPGC2_ADDRESS_SIZE)—Offset 40BCh............................. 1199
5.14.100Base Address Control (CPGC2_BASE_ADDRESS_CONTROL)—Offset 40C0h 1201
5.14.101Address PRBS Control (CPGC2_ADDRESS_PRBS_CONTROL)—Offset 40C4h ......
1202
5.14.102Address PRBS Seed (CPGC2_ADDRESS_PRBS_SEED)—Offset 40C8h ........ 1204
5.14.103Current Address PRBS Status (CPGC2_ADDRESS_PRBS_CURRENT)—Offset
40CCh............................................................................................... 1204
5.14.104Address PRBS Save (CPGC2_ADDRESS_PRBS_SAVE)—Offset 40D0h ........ 1205
5.14.105Command FSM Current State (CPGC2_CMD_FSM_CURRENT)—Offset 40D4h ....
1206
5.14.106Algorithm Wait Timer Configuration (CPGC2_WAIT_2_START_CONFIG)—Offset
40D8h............................................................................................... 1207
5.14.107VISA Mux Selection (CPGC2_VISA_MUX_SEL)—Offset 40DCh .................. 1208
5.14.108Loopback Squencer Configuration (CPGC_LB_SEQ_CFG)—Offset 40E0h .... 1209
5.14.109Loopback Sequencer Control (CPGC_LB_SEQ_CTL)—Offset 40E4h ........... 1211
5.14.110Loopback Loopcount Tx Status (CPGC_LB_SEQ_LOOPCOUNT_TX_STATUS)—
Offset 40E8h ...................................................................................... 1213
5.14.111Loopback Loopcount Rx Status (CPGC_LB_SEQ_LOOPCOUNT_RX_STATUS)—
Offset 40ECh...................................................................................... 1214
5.14.112Pattern Length Status (CPGC_LB_SEQ_PL_RX_STATUS)—Offset 40F0h .... 1214
5.14.113Refresh Control (CPGC_MISC_REFRESH_CTL)—Offset 40F4h................... 1215
5.14.114ZQ Control (CPGC_MISC_ZQ_CTL)—Offset 40F8h .................................. 1216
5.14.115ODT Control (CPGC_MISC_ODT_CTL)—Offset 40FCh .............................. 1216

28 334818
 5.14.116CKE Control (CPGC_MISC_CKE_CTL)—Offset 4100h ...............................1217
5.14.117Command Rate (CPGC_MISC_CMD_RATE)—Offset 4104h........................1218
5.14.118External Trigger Control (CPGC_MISC_EXT_TRIGGER)—Offset 4108h .......1219
5.14.119Sequence Control (CPGC_SEQ_CTL)—Offset 410Ch ................................1219
5.14.120Sequence Configuration A (CPGC_SEQ_CFG_A)—Offset 4110h.................1220
5.14.121Sequence Configuration B (CPGC_SEQ_CFG_B)—Offset 4114h.................1223
5.14.122Sequence Status (CPGC_SEQ_STATUS)—Offset 4118h............................1223
5.14.123Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[0])—Offset 4120h
1224
5.14.124Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[1])—Offset 4124h
1225
5.14.125Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[2])—Offset 4128h
1225
5.14.126Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[3])—Offset 412Ch
1226
5.14.127Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[4])—Offset 4130h
1226
5.14.128Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[5])—Offset 4134h
1227
5.14.129Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[6])—Offset 4138h
1228
5.14.130Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[7])—Offset 413Ch
1228
5.14.131Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[8])—Offset 4140h
1229
5.14.132Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[9])—Offset 4144h
1229
5.14.133Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[10])—Offset
4148h................................................................................................1230
5.14.134Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[11])—Offset
414Ch ...............................................................................................1231
5.14.135Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[12])—Offset
4150h................................................................................................1231
5.14.136Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[13])—Offset
4154h................................................................................................1232
5.14.137Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[14])—Offset
4158h................................................................................................1232
5.14.138Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[15])—Offset
415Ch ...............................................................................................1233
5.14.139Mode3 Fail Status LSB (CPGC2_RASTER_REPO_CONTENT_ECC1)—Offset 4160h
1234
5.14.140Mode3 Fail Status MSB (CPGC2_RASTER_REPO_CONTENT_ECC2)—Offset 4164h
1235
5.14.141Read Command Count (CPGC2_READ_COMMAND_COUNT_CURRENT)—Offset
4168h................................................................................................1237
5.14.142Mask Errors on First N Reads (CPGC2_MASK_ERRS_FIRST_N_READS)—Offset
416Ch ...............................................................................................1237
5.14.143Raster Repository Status (CPGC2_RASTER_REPO_STATUS)—Offset 4170h 1238
5.14.144Error Summary A (CPGC2_ERR_SUMMARY_A)—Offset 4174h ..................1239
5.14.145Error Summary B (CPGC2_ERR_SUMMARY_B)—Offset 4178h ..................1240
5.14.146Future use Reserved (CPGC2_ERR_SUMMARY_C)—Offset 417Ch ..............1241
5.14.147Data Pattern Generation Buffer Control (CPGC_DPAT_BUF_CTL)—Offset 4180h .
1241
5.14.148Data Pattern Generation Configuration (CPGC_DPAT_CFG)—Offset 4184h .1243
5.14.149LFSR Configuration and Lane Rotate (CPGC_DPAT_XTRA_LFSR_CFG)—Offset
4188h................................................................................................1247

334818 29
 5.14.150Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[0])—Offset 418Ch .....
1249
5.14.151Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[1])—Offset 4190h .....
1250
5.14.152Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[2])—Offset 4194h .....
1250
5.14.153Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[0])—Offset 4198h 1251
5.14.154Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[1])—Offset 419Ch 1254
5.14.155Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[2])—Offset 41A0h 1257
5.14.156Invert and DC Control (CPGC_DPAT_INVDCCTL)—Offset 41A4h ............... 1260
5.14.157Data Invert/DC Enable Low (CPGC_DPAT_INV_DC_MASK_LO)—Offset 41A8h...
1261
5.14.158Data Invert/DC Enable High (CPGC_DPAT_INV_DC_MASK_HI)—Offset 41ACh ..
1262
5.14.159Byte Enable Mask Lower (CPGC_DPAT_DRAMDM)—Offset 41B0h ............. 1262
5.14.160Byte Enable Mask Upper (CPGC_DPAT_XDRAMDM)—Offset 41B4h ........... 1263
5.14.161Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[0])—Offset 41B8h
1264
5.14.162Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[1])—Offset 41BCh
1264
5.14.163Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[2])—Offset 41C0h
1265
5.14.164Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[0])—Offset 41C4h
1265
5.14.165Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[1])—Offset 41C8h
1266
5.14.166Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[2])—Offset 41CCh
1267
5.14.167LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[0])—Offset 41D0h ......... 1268
5.14.168LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[1])—Offset 41D4h ......... 1269
5.14.169LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[2])—Offset 41D8h ......... 1269
5.14.170LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[0])—Offset 41DCh .......... 1270
5.14.171LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[1])—Offset 41E0h ........... 1270
5.14.172LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[2])—Offset 41E4h ........... 1271
5.14.173Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[0])—Offset
41E8h ............................................................................................... 1271
5.14.174Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[1])—Offset
41ECh ............................................................................................... 1272
5.14.175Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[2])—Offset
41F0h ............................................................................................... 1272
5.14.176Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[0])—Offset
41F4h ............................................................................................... 1273
5.14.177Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[1])—Offset
41F8h ............................................................................................... 1274
5.14.178Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[2])—Offset
41FCh ............................................................................................... 1275
5.14.179Extended Pattern Buffer (CPGC_DPAT_EXTBUF[0])—Offset 4200h ........... 1276
5.14.180Extended Pattern Buffer (CPGC_DPAT_EXTBUF[1])—Offset 4204h ........... 1277
5.14.181Extended Pattern Buffer (CPGC_DPAT_EXTBUF[2])—Offset 4208h ........... 1278
5.14.182Extended Pattern Buffer (CPGC_DPAT_EXTBUF[3])—Offset 420Ch ........... 1279
5.14.183Extended Pattern Buffer (CPGC_DPAT_EXTBUF[4])—Offset 4210h ........... 1279
5.14.184Extended Pattern Buffer (CPGC_DPAT_EXTBUF[5])—Offset 4214h ........... 1280
5.14.185Extended Pattern Buffer (CPGC_DPAT_EXTBUF[6])—Offset 4218h ........... 1281
5.14.186Extended Pattern Buffer (CPGC_DPAT_EXTBUF[7])—Offset 421Ch ........... 1282
5.14.187Extended Pattern Buffer (CPGC_DPAT_EXTBUF[8])—Offset 4220h ........... 1283
5.14.188Extended Pattern Buffer (CPGC_DPAT_EXTBUF[9])—Offset 4224h ........... 1284

30 334818
 5.14.189Extended Pattern Buffer (CPGC_DPAT_EXTBUF[10])—Offset 4228h ..........1284
5.14.190Extended Pattern Buffer (CPGC_DPAT_EXTBUF[11])—Offset 422Ch ..........1285
5.14.191Extended Pattern Buffer (CPGC_DPAT_EXTBUF[12])—Offset 4230h ..........1286
5.14.192Extended Pattern Buffer (CPGC_DPAT_EXTBUF[13])—Offset 4234h ..........1287
5.14.193Extended Pattern Buffer (CPGC_DPAT_EXTBUF[14])—Offset 4238h ..........1288
5.14.194Extended Pattern Buffer (CPGC_DPAT_EXTBUF[15])—Offset 423Ch ..........1289
5.14.195Error Checker Control (CPGC_ERR_CTL)—Offset 4240h ...........................1289
5.14.196Lane Error Mask Lower Bytes (CPGC_ERR_LNEN_LO)—Offset 4244h .........1291
5.14.197Lane Error Mask Upper Bytes or Extended Chunk Enable
(CPGC_ERR_LNEN_HI)—Offset 4248h ....................................................1292
5.14.198Lane Error Mask ECC (CPGC_ERR_XLNEN)—Offset 424Ch........................1293
5.14.199Lane Error Status Lower Bytes (CPGC_ERR_STAT03)—Offset 4250h .........1293
5.14.200Lane Error Status Upper Bytes or Extended Chunk Error Status
(CPGC_ERR_STAT47)—Offset 4254h ......................................................1294
5.14.201ECC Lane Error Status (CPGC_ERR_ECC_CHNK_RANK_STAT)—Offset 4258h.....
1295
5.14.202ByteGroup Error Status (CPGC_ERR_BYTE_NTH_PAR_STAT)—Offset 425Ch ......
1296
5.14.203Error Counter Control (CPGC_ERR_CNTRCTL[0])—Offset 4260h ...............1297
5.14.204Error Counter Control (CPGC_ERR_CNTRCTL[1])—Offset 4264h ...............1298
5.14.205Error Counter Control (CPGC_ERR_CNTRCTL[2])—Offset 4268h ...............1299
5.14.206Error Counter Control (CPGC_ERR_CNTRCTL[3])—Offset 426Ch ...............1300
5.14.207Error Counter Control (CPGC_ERR_CNTRCTL[4])—Offset 4270h ...............1301
5.14.208Error Counter Control (CPGC_ERR_CNTRCTL[5])—Offset 4274h ...............1302
5.14.209Error Counter Control (CPGC_ERR_CNTRCTL[6])—Offset 4278h ...............1303
5.14.210Error Counter Control (CPGC_ERR_CNTRCTL[7])—Offset 427Ch ...............1304
5.14.211Error Counter Control (CPGC_ERR_CNTRCTL[8])—Offset 4280h ...............1305
5.14.212Error Counter (CPGC_ERR_CNTR[0])—Offset 4284h ...............................1306
5.14.213Error Counter (CPGC_ERR_CNTR[1])—Offset 4288h ...............................1307
5.14.214Error Counter (CPGC_ERR_CNTR[2])—Offset 428Ch ...............................1308
5.14.215Error Counter (CPGC_ERR_CNTR[3])—Offset 4290h ...............................1309
5.14.216Error Counter (CPGC_ERR_CNTR[4])—Offset 4294h ...............................1309
5.14.217Error Counter (CPGC_ERR_CNTR[5])—Offset 4298h ...............................1310
5.14.218Error Counter (CPGC_ERR_CNTR[6])—Offset 429Ch ...............................1311
5.14.219Error Counter (CPGC_ERR_CNTR[7])—Offset 42A0h ...............................1311
5.14.220Error Counter (CPGC_ERR_CNTR[8])—Offset 42A4h ...............................1312
5.14.221Error Counter Overflow (CPGC_ERR_CNTR_OV)—Offset 42A8h ................1313
5.14.222Error Log Control and Status (CPGC_ERRLOG_CTL_STAT)—Offset 42ACh ..1314
5.14.223Error Log Data Access (CPGC_ERRLOG_DATA)—Offset 42B0h ..................1315
5.14.224Loopback Error Status (CPGC_ERR_TEST_ERR_STAT)—Offset 42B4h ........1316
5.14.225Rank Logical To Physical Map (CPGC_SEQ_RANK_L2P_MAPPING)—Offset 42B8h
1317
5.14.226Bank Logical to Physical Map Low (CPGC_SEQ_BANK_L2P_MAPPING_A)—Offset
42BCh ...............................................................................................1318
5.14.227Bank Logical to Physical Map High (CPGC_SEQ_BANK_L2P_MAPPING_B)—Offset
42C0h ...............................................................................................1319
5.14.228Rank Address Swizzle (CPGC_SEQ_RANK_ADDR_SWIZZLE)—Offset 42C4h1321
5.14.229Bank Address Swizzle (CPGC_SEQ_BANK_ADDR_SWIZZLE)—Offset 42C8h1322
5.14.230Row Address Swizzle Low (CPGC_SEQ_ROW_ADDR_SWIZZLE_A)—Offset 42CCh
1322
5.14.231Row Address Swizzle Mid (CPGC_SEQ_ROW_ADDR_SWIZZLE_B)—Offset 42D0h
1324
5.14.232Row Address Swizzle High (CPGC_SEQ_ROW_ADDR_SWIZZLE_C)—Offset
42D4h ...............................................................................................1325
5.14.233Row Address XOR (CPGC_SEQ_ROW_ADDR_SWIZZLE_X)—Offset 42D8h ..1326

334818 31
 5.14.234Column Address Swizzle Low (CPGC_SEQ_COL_ADDR_SWIZZLE_A)—Offset
42DCh .............................................................................................. 1327
5.14.235Column Address Swizzle High (CPGC_SEQ_COL_ADDR_SWIZZLE_B)—Offset
42E0h ............................................................................................... 1328
5.14.236DQ Inversion Lookup Data Low (CPGC_SEQ_ROW_ADDR_DQ_MAP0)—Offset
42E8h ............................................................................................... 1329
5.14.237DQ Inversion Lookup Data High (CPGC_SEQ_ROW_ADDR_DQ_MAP1)—Offset
42ECh ............................................................................................... 1330
5.15 Registers Summary........................................................................................ 1331
5.15.1 CADB Control (CPGC_CADB_CTL)—Offset 46F0h ..................................... 1332
5.15.2 CADB MRS Configuration (CPGC_CADB_MRSCFG)—Offset 46F4h............... 1335
5.15.3 CADB Configuration (CPGC_CADB_CFG)—Offset 46F8h ............................ 1336
5.15.4 CADB Unisequencer 0 Pattern Buffer (CPGC_CADB_UNISEQ0_PBUF)—Offset
46FCh ............................................................................................... 1337
5.15.5 CADB Unisequencer 1 Pattern Buffer (CPGC_CADB_UNISEQ1_PBUF)—Offset
4700h ............................................................................................... 1338
5.15.6 CADB Unisequencer 2 Pattern Buffer (CPGC_CADB_UNISEQ2_PBUF)—Offset
4704h ............................................................................................... 1338
5.15.7 CADB LMN 0 Settings (CPGC_CADB_UNISEQ0_LMN)—Offset 4708h........... 1339
5.15.8 CADB LMN 1 Settings (CPGC_CADB_UNISEQ1_LMN)—Offset 470Ch .......... 1340
5.15.9 CADB LMN 2 Settings (CPGC_CADB_UNISEQ2_LMN)—Offset 4710h........... 1341
5.15.10CADB Select Unisequencer 0 Pattern Buffer
(CPGC_CADB_SEL_UNISEQ0_PBUF)—Offset 4714h ................................. 1342
5.15.11CADB Select Unisequencer 1 Pattern Buffer
(CPGC_CADB_SEL_UNISEQ1_PBUF)—Offset 4718h ................................. 1343
5.15.12CADB Select Unisequencer 2 Pattern Buffer
(CPGC_CADB_SEL_UNISEQ2_PBUF)—Offset 471Ch ................................. 1343
5.15.13CADB Buffer A (CPGC_CADB_BUFA[0])—Offset 4720h ............................. 1344
5.15.14CADB Buffer A (CPGC_CADB_BUFA[1])—Offset 4724h ............................. 1344
5.15.15CADB Buffer A (CPGC_CADB_BUFA[2])—Offset 4728h ............................. 1345
5.15.16CADB Buffer A (CPGC_CADB_BUFA[3])—Offset 472Ch ............................. 1346
5.15.17CADB Buffer A (CPGC_CADB_BUFA[4])—Offset 4730h ............................. 1347
5.15.18CADB Buffer A (CPGC_CADB_BUFA[5])—Offset 4734h ............................. 1347
5.15.19CADB Buffer A (CPGC_CADB_BUFA[6])—Offset 4738h ............................. 1348
5.15.20CADB Buffer A (CPGC_CADB_BUFA[7])—Offset 473Ch ............................. 1349
5.15.21CADB Buffer B (CPGC_CADB_BUFB[0])—Offset 4740h ............................. 1349
5.15.22CADB Buffer B (CPGC_CADB_BUFB[1])—Offset 4744h ............................. 1350
5.15.23CADB Buffer B (CPGC_CADB_BUFB[2])—Offset 4748h ............................. 1351
5.15.24CADB Buffer B (CPGC_CADB_BUFB[3])—Offset 474Ch ............................. 1352
5.15.25CADB Buffer B (CPGC_CADB_BUFB[4])—Offset 4750h ............................. 1353
5.15.26CADB Buffer B (CPGC_CADB_BUFB[5])—Offset 4754h ............................. 1354
5.15.27CADB Buffer B (CPGC_CADB_BUFB[6])—Offset 4758h ............................. 1355
5.15.28CADB Buffer B (CPGC_CADB_BUFB[7])—Offset 475Ch ............................. 1356
5.15.29CADB Deselect Uniseq 0 Status (CPGC_CADB_UNISEQ0STAT)—Offset 4760h.....
1357
5.15.30CADB Deselect Uniseq 1 Status (CPGC_CADB_UNISEQ1STAT)—Offset 4764h.....
1358
5.15.31CADB Deselect Uniseq 2 Status (CPGC_CADB_UNISEQ2STAT)—Offset 4768h.....
1358
5.16 Registers Summary........................................................................................ 1361
5.16.1 Address Decode Repeats (CPGC2_ADDRESS_CONTROL)—Offset 4418h...... 1369
5.16.2 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[0])—Offset 441Ch .. 1370
5.16.3 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[1])—Offset 441Dh .. 1372
5.16.4 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[2])—Offset 441Eh .. 1374
5.16.5 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[3])—Offset 441Fh... 1375
5.16.6 Data Instruction (CPGC2_DATA_INSTRUCTION[0])—Offset 4420h ............. 1377

32 334818
 5.16.7 Data Instruction (CPGC2_DATA_INSTRUCTION[1])—Offset 4421h .............1378
5.16.8 Data Instruction (CPGC2_DATA_INSTRUCTION[2])—Offset 4422h .............1379
5.16.9 Data Instruction (CPGC2_DATA_INSTRUCTION[3])—Offset 4423h .............1380
5.16.10Data Rotation Repeats (CPGC2_DATA_CONTROL)—Offset 4424h ...............1381
5.16.11Address and Data Repeats Status (CPGC2_ADDRESS_DATA_STATUS)—Offset
4428h................................................................................................1382
5.16.12Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[0])—Offset 442Ch ....
1383
5.16.13Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[1])—Offset 442Dh ....
1384
5.16.14Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[2])—Offset 442Eh ....
1385
5.16.15Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[3])—Offset 442Fh ....
1386
5.16.16Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[4])—Offset 4430h ....
1387
5.16.17Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[5])—Offset 4431h ....
1388
5.16.18Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[6])—Offset 4432h ....
1389
5.16.19Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[7])—Offset 4433h ....
1390
5.16.20Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[0])—
Offset 4434h ......................................................................................1391
5.16.21Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[1])—
Offset 4435h ......................................................................................1394
5.16.22Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[2])—
Offset 4436h ......................................................................................1399
5.16.23Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[3])—
Offset 4437h ......................................................................................1401
5.16.24Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[4])—
Offset 4438h ......................................................................................1403
5.16.25Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[5])—
Offset 4439h ......................................................................................1405
5.16.26Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[6])—
Offset 443Ah ......................................................................................1407
5.16.27Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[7])—
Offset 443Bh ......................................................................................1409
5.16.28Wait Timer Current (CPGC2_ALGORITHM_WAIT_COUNT_CURRENT)—Offset
443Ch ...............................................................................................1411
5.16.29Algorithm Wait Event Control (CPGC2_ALGORITHM_WAIT_EVENT_CONTROL)—
Offset 4440h ......................................................................................1411
5.16.30Base Repeats (CPGC2_BASE_REPEATS)—Offset 4444h .............................1412
5.16.31Current Base Repeats (CPGC2_BASE_REPEATS_CURRENT)—Offset 4448h ..1413
5.16.32Base Column Repeats (CPGC2_BASE_COL_REPEATS)—Offset 444Ch ..........1414
5.16.33Block Repeats (CPGC2_BLOCK_REPEATS)—Offset 4450h ..........................1414
5.16.34Current Block Repeats (CPGC2_BLOCK_REPEATS_CURRENT)—Offset 4454h1415
5.16.35Command Instruction (CPGC2_COMMAND_INSTRUCTION[0])—Offset 4458h......
1415
5.16.36Command Instruction (CPGC2_COMMAND_INSTRUCTION[1])—Offset 4459h......
1417
5.16.37Command Instruction (CPGC2_COMMAND_INSTRUCTION[2])—Offset 445Ah .....
1418
5.16.38Command Instruction (CPGC2_COMMAND_INSTRUCTION[3])—Offset 445Bh .....
1419
5.16.39Command Instruction (CPGC2_COMMAND_INSTRUCTION[4])—Offset 445Ch .....
1421

334818 33
 5.16.40Command Instruction (CPGC2_COMMAND_INSTRUCTION[5])—Offset 445Dh.....
1422
5.16.41Command Instruction (CPGC2_COMMAND_INSTRUCTION[6])—Offset 445Eh .....
1424
5.16.42Command Instruction (CPGC2_COMMAND_INSTRUCTION[7])—Offset 445Fh .....
1425
5.16.43Command Instruction (CPGC2_COMMAND_INSTRUCTION[8])—Offset 4460h .....
1426
5.16.44Command Instruction (CPGC2_COMMAND_INSTRUCTION[9])—Offset 4461h .....
1428
5.16.45Command Instruction (CPGC2_COMMAND_INSTRUCTION[10])—Offset 4462h ...
1429
5.16.46Command Instruction (CPGC2_COMMAND_INSTRUCTION[11])—Offset 4463h ...
1431
5.16.47Command Instruction (CPGC2_COMMAND_INSTRUCTION[12])—Offset 4464h ...
1432
5.16.48Command Instruction (CPGC2_COMMAND_INSTRUCTION[13])—Offset 4465h ...
1433
5.16.49Command Instruction (CPGC2_COMMAND_INSTRUCTION[14])—Offset 4466h ...
1435
5.16.50Command Instruction (CPGC2_COMMAND_INSTRUCTION[15])—Offset 4467h ...
1436
5.16.51Command Instruction (CPGC2_COMMAND_INSTRUCTION[16])—Offset 4468h ...
1438
5.16.52Command Instruction (CPGC2_COMMAND_INSTRUCTION[17])—Offset 4469h ...
1439
5.16.53Command Instruction (CPGC2_COMMAND_INSTRUCTION[18])—Offset 446Ah ...
1440
5.16.54Command Instruction (CPGC2_COMMAND_INSTRUCTION[19])—Offset 446Bh ...
1442
5.16.55Command Instruction (CPGC2_COMMAND_INSTRUCTION[20])—Offset 446Ch ...
1443
5.16.56Command Instruction (CPGC2_COMMAND_INSTRUCTION[21])—Offset 446Dh ...
1445
5.16.57Command Instruction (CPGC2_COMMAND_INSTRUCTION[22])—Offset 446Eh ...
1446
5.16.58Command Instruction (CPGC2_COMMAND_INSTRUCTION[23])—Offset 446Fh ...
1447
5.16.59Hammer Repeats (CPGC2_HAMMER_REPEATS)—Offset 4470h .................. 1449
5.16.60Current Hammer Repeats (CPGC2_HAMMER_REPEATS_CURRENT)—Offset 4474h
1449
5.16.61Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[0])—
Offset 4478h ...................................................................................... 1450
5.16.62Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[1])—
Offset 4479h ...................................................................................... 1451
5.16.63Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[2])—
Offset 447Ah...................................................................................... 1453
5.16.64Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[3])—
Offset 447Bh...................................................................................... 1454
5.16.65Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[4])—
Offset 447Ch...................................................................................... 1456
5.16.66Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[5])—
Offset 447Dh ..................................................................................... 1457
5.16.67Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[6])—
Offset 447Eh ...................................................................................... 1459
5.16.68Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[7])—
Offset 447Fh ...................................................................................... 1460

34 334818
 5.16.69Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[8])—
Offset 4480h ......................................................................................1462
5.16.70Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[9])—
Offset 4481h ......................................................................................1463
5.16.71Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[10])—
Offset 4482h ......................................................................................1465
5.16.72Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[11])—
Offset 4483h ......................................................................................1466
5.16.73Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[12])—
Offset 4484h ......................................................................................1468
5.16.74Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[13])—
Offset 4485h ......................................................................................1469
5.16.75Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[14])—
Offset 4486h ......................................................................................1471
5.16.76Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[15])—
Offset 4487h ......................................................................................1472
5.16.77Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[0])—
Offset 4488h ......................................................................................1474
5.16.78Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[1])—
Offset 4489h ......................................................................................1475
5.16.79Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[2])—
Offset 448Ah ......................................................................................1476
5.16.80Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[3])—
Offset 448Bh ......................................................................................1477
5.16.81Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[4])—
Offset 448Ch ......................................................................................1478
5.16.82Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[5])—
Offset 448Dh ......................................................................................1479
5.16.83Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[6])—
Offset 448Eh ......................................................................................1480
5.16.84Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[7])—
Offset 448Fh.......................................................................................1482
5.16.85Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[8])—
Offset 4490h ......................................................................................1483
5.16.86Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[9])—
Offset 4491h ......................................................................................1484
5.16.87Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[10])—
Offset 4492h ......................................................................................1485
5.16.88Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[11])—
Offset 4493h ......................................................................................1486
5.16.89Offset Repeats (CPGC2_OFFSET_REPEATS[0])—Offset 4494h....................1487
5.16.90Offset Repeats (CPGC2_OFFSET_REPEATS[1])—Offset 4498h....................1488
5.16.91Current Offset Repeats (CPGC2_OFFSET_REPEATS_CURRENT)—Offset 449Ch ....
1488
5.16.92Region Low Row Address (CPGC2_REGION_LOW_ROW)—Offset 44A0h.......1489
5.16.93Region Low Col Address (CPGC2_REGION_LOW_COL)—Offset 44A4h .........1489
5.16.94Block Low Row Current (CPGC2_BLOCK_ORIGIN_ROW_CURRENT)—Offset 44A8h
1490
5.16.95Current Base Address Rank and Column
(CPGC2_BASE_ADDRESS_COL_RANK_CURRENT)—Offset 44ACh ...............1491
5.16.96Current Base Address Bank and Row
(CPGC2_BASE_ADDRESS_ROW_BANK_CURRENT)—Offset 44B0h ..............1491
5.16.97Current Offset Address Column (CPGC2_OFFSET_ADDRESS_COL_CURRENT)—
Offset 44B4h ......................................................................................1492
5.16.98Current Offset Address Row (CPGC2_OFFSET_ADDRESS_ROW_CURRENT)—
Offset 44B8h ......................................................................................1493
5.16.99Address Size (CPGC2_ADDRESS_SIZE)—Offset 44BCh .............................1493

334818 35
 5.16.100Base Address Control (CPGC2_BASE_ADDRESS_CONTROL)—Offset 44C0h 1495
5.16.101Address PRBS Control (CPGC2_ADDRESS_PRBS_CONTROL)—Offset 44C4h ......
1496
5.16.102Address PRBS Seed (CPGC2_ADDRESS_PRBS_SEED)—Offset 44C8h ........ 1498
5.16.103Current Address PRBS Status (CPGC2_ADDRESS_PRBS_CURRENT)—Offset
44CCh............................................................................................... 1499
5.16.104Address PRBS Save (CPGC2_ADDRESS_PRBS_SAVE)—Offset 44D0h ........ 1499
5.16.105Command FSM Current State (CPGC2_CMD_FSM_CURRENT)—Offset 44D4h ....
1500
5.16.106Algorithm Wait Timer Configuration (CPGC2_WAIT_2_START_CONFIG)—Offset
44D8h............................................................................................... 1501
5.16.107VISA Mux Selection (CPGC2_VISA_MUX_SEL)—Offset 44DCh .................. 1502
5.16.108Loopback Squencer Configuration (CPGC_LB_SEQ_CFG)—Offset 44E0h .... 1503
5.16.109Loopback Sequencer Control (CPGC_LB_SEQ_CTL)—Offset 44E4h ........... 1505
5.16.110Loopback Loopcount Tx Status (CPGC_LB_SEQ_LOOPCOUNT_TX_STATUS)—
Offset 44E8h ...................................................................................... 1507
5.16.111Loopback Loopcount Rx Status (CPGC_LB_SEQ_LOOPCOUNT_RX_STATUS)—
Offset 44ECh...................................................................................... 1508
5.16.112Pattern Length Status (CPGC_LB_SEQ_PL_RX_STATUS)—Offset 44F0h .... 1508
5.16.113Refresh Control (CPGC_MISC_REFRESH_CTL)—Offset 44F4h................... 1509
5.16.114ZQ Control (CPGC_MISC_ZQ_CTL)—Offset 44F8h .................................. 1510
5.16.115ODT Control (CPGC_MISC_ODT_CTL)—Offset 44FCh .............................. 1510
5.16.116CKE Control (CPGC_MISC_CKE_CTL)—Offset 4500h ............................... 1511
5.16.117Command Rate (CPGC_MISC_CMD_RATE)—Offset 4504h ....................... 1512
5.16.118External Trigger Control (CPGC_MISC_EXT_TRIGGER)—Offset 4508h ....... 1513
5.16.119Sequence Control (CPGC_SEQ_CTL)—Offset 450Ch................................ 1513
5.16.120Sequence Configuration A (CPGC_SEQ_CFG_A)—Offset 4510h ................ 1514
5.16.121Sequence Configuration B (CPGC_SEQ_CFG_B)—Offset 4514h ................ 1517
5.16.122Sequence Status (CPGC_SEQ_STATUS)—Offset 4518h ........................... 1517
5.16.123Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[0])—Offset 4520h
1518
5.16.124Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[1])—Offset 4524h
1519
5.16.125Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[2])—Offset 4528h
1519
5.16.126Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[3])—Offset 452Ch
1520
5.16.127Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[4])—Offset 4530h
1520
5.16.128Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[5])—Offset 4534h
1521
5.16.129Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[6])—Offset 4538h
1522
5.16.130Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[7])—Offset 453Ch
1522
5.16.131Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[8])—Offset 4540h
1523
5.16.132Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[9])—Offset 4544h
1523
5.16.133Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[10])—Offset
4548h ............................................................................................... 1524
5.16.134Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[11])—Offset
454Ch ............................................................................................... 1525
5.16.135Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[12])—Offset
4550h ............................................................................................... 1525

36 334818
 5.16.136Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[13])—Offset
4554h................................................................................................1526
5.16.137Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[14])—Offset
4558h................................................................................................1526
5.16.138Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[15])—Offset
455Ch ...............................................................................................1527
5.16.139Mode3 Fail Status LSB (CPGC2_RASTER_REPO_CONTENT_ECC1)—Offset 4560h
1528
5.16.140Mode3 Fail Status MSB (CPGC2_RASTER_REPO_CONTENT_ECC2)—Offset 4564h
1529
5.16.141Read Command Count (CPGC2_READ_COMMAND_COUNT_CURRENT)—Offset
4568h................................................................................................1531
5.16.142Mask Errors on First N Reads (CPGC2_MASK_ERRS_FIRST_N_READS)—Offset
456Ch ...............................................................................................1531
5.16.143Raster Repository Status (CPGC2_RASTER_REPO_STATUS)—Offset 4570h 1532
5.16.144Error Summary A (CPGC2_ERR_SUMMARY_A)—Offset 4574h ..................1533
5.16.145Error Summary B (CPGC2_ERR_SUMMARY_B)—Offset 4578h ..................1534
5.16.146Future use Reserved (CPGC2_ERR_SUMMARY_C)—Offset 457Ch ..............1535
5.16.147Data Pattern Generation Buffer Control (CPGC_DPAT_BUF_CTL)—Offset 4580h .
1535
5.16.148Data Pattern Generation Configuration (CPGC_DPAT_CFG)—Offset 4584h .1537
5.16.149LFSR Configuration and Lane Rotate (CPGC_DPAT_XTRA_LFSR_CFG)—Offset
4588h................................................................................................1541
5.16.150Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[0])—Offset 458Ch .....
1543
5.16.151Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[1])—Offset 4590h......
1544
5.16.152Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[2])—Offset 4594h......
1545
5.16.153Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[0])—Offset 4598h .1545
5.16.154Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[1])—Offset 459Ch.1549
5.16.155Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[2])—Offset 45A0h.1552
5.16.156Invert and DC Control (CPGC_DPAT_INVDCCTL)—Offset 45A4h ...............1555
5.16.157Data Invert/DC Enable Low (CPGC_DPAT_INV_DC_MASK_LO)—Offset 45A8h ...
1556
5.16.158Data Invert/DC Enable High (CPGC_DPAT_INV_DC_MASK_HI)—Offset 45ACh...
1557
5.16.159Byte Enable Mask Lower (CPGC_DPAT_DRAMDM)—Offset 45B0h ..............1557
5.16.160Byte Enable Mask Upper (CPGC_DPAT_XDRAMDM)—Offset 45B4h ............1558
5.16.161Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[0])—Offset 45B8h
1559
5.16.162Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[1])—Offset 45BCh
1559
5.16.163Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[2])—Offset 45C0h
1560
5.16.164Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[0])—Offset 45C4h
1560
5.16.165Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[1])—Offset 45C8h
1561
5.16.166Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[2])—Offset 45CCh
1562
5.16.167LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[0])—Offset 45D0h ..........1563
5.16.168LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[1])—Offset 45D4h ..........1564
5.16.169LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[2])—Offset 45D8h ..........1564
5.16.170LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[0])—Offset 45DCh ...........1565
5.16.171LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[1])—Offset 45E0h ...........1565

334818 37
 5.16.172LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[2])—Offset 45E4h ........... 1566
5.16.173Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[0])—Offset
45E8h ............................................................................................... 1566
5.16.174Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[1])—Offset
45ECh ............................................................................................... 1567
5.16.175Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[2])—Offset
45F0h ............................................................................................... 1567
5.16.176Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[0])—Offset
45F4h ............................................................................................... 1568
5.16.177Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[1])—Offset
45F8h ............................................................................................... 1569
5.16.178Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[2])—Offset
45FCh ............................................................................................... 1570
5.16.179Extended Pattern Buffer (CPGC_DPAT_EXTBUF[0])—Offset 4600h ........... 1571
5.16.180Extended Pattern Buffer (CPGC_DPAT_EXTBUF[1])—Offset 4604h ........... 1572
5.16.181Extended Pattern Buffer (CPGC_DPAT_EXTBUF[2])—Offset 4608h ........... 1573
5.16.182Extended Pattern Buffer (CPGC_DPAT_EXTBUF[3])—Offset 460Ch ........... 1574
5.16.183Extended Pattern Buffer (CPGC_DPAT_EXTBUF[4])—Offset 4610h ........... 1574
5.16.184Extended Pattern Buffer (CPGC_DPAT_EXTBUF[5])—Offset 4614h ........... 1575
5.16.185Extended Pattern Buffer (CPGC_DPAT_EXTBUF[6])—Offset 4618h ........... 1576
5.16.186Extended Pattern Buffer (CPGC_DPAT_EXTBUF[7])—Offset 461Ch ........... 1577
5.16.187Extended Pattern Buffer (CPGC_DPAT_EXTBUF[8])—Offset 4620h ........... 1578
5.16.188Extended Pattern Buffer (CPGC_DPAT_EXTBUF[9])—Offset 4624h ........... 1579
5.16.189Extended Pattern Buffer (CPGC_DPAT_EXTBUF[10])—Offset 4628h.......... 1579
5.16.190Extended Pattern Buffer (CPGC_DPAT_EXTBUF[11])—Offset 462Ch.......... 1580
5.16.191Extended Pattern Buffer (CPGC_DPAT_EXTBUF[12])—Offset 4630h.......... 1581
5.16.192Extended Pattern Buffer (CPGC_DPAT_EXTBUF[13])—Offset 4634h.......... 1582
5.16.193Extended Pattern Buffer (CPGC_DPAT_EXTBUF[14])—Offset 4638h.......... 1583
5.16.194Extended Pattern Buffer (CPGC_DPAT_EXTBUF[15])—Offset 463Ch.......... 1584
5.16.195Error Checker Control (CPGC_ERR_CTL)—Offset 4640h .......................... 1584
5.16.196Lane Error Mask Lower Bytes (CPGC_ERR_LNEN_LO)—Offset 4644h ........ 1586
5.16.197Lane Error Mask Upper Bytes or Extended Chunk Enable
(CPGC_ERR_LNEN_HI)—Offset 4648h.................................................... 1587
5.16.198Lane Error Mask ECC (CPGC_ERR_XLNEN)—Offset 464Ch ....................... 1588
5.16.199Lane Error Status Lower Bytes (CPGC_ERR_STAT03)—Offset 4650h......... 1588
5.16.200Lane Error Status Upper Bytes or Extended Chunk Error Status
(CPGC_ERR_STAT47)—Offset 4654h ..................................................... 1589
5.16.201ECC Lane Error Status (CPGC_ERR_ECC_CHNK_RANK_STAT)—Offset 4658h ....
1590
5.16.202ByteGroup Error Status (CPGC_ERR_BYTE_NTH_PAR_STAT)—Offset 465Ch .....
1591
5.16.203Error Counter Control (CPGC_ERR_CNTRCTL[0])—Offset 4660h............... 1592
5.16.204Error Counter Control (CPGC_ERR_CNTRCTL[1])—Offset 4664h............... 1593
5.16.205Error Counter Control (CPGC_ERR_CNTRCTL[2])—Offset 4668h............... 1594
5.16.206Error Counter Control (CPGC_ERR_CNTRCTL[3])—Offset 466Ch............... 1595
5.16.207Error Counter Control (CPGC_ERR_CNTRCTL[4])—Offset 4670h............... 1596
5.16.208Error Counter Control (CPGC_ERR_CNTRCTL[5])—Offset 4674h............... 1597
5.16.209Error Counter Control (CPGC_ERR_CNTRCTL[6])—Offset 4678h............... 1598
5.16.210Error Counter Control (CPGC_ERR_CNTRCTL[7])—Offset 467Ch............... 1599
5.16.211Error Counter Control (CPGC_ERR_CNTRCTL[8])—Offset 4680h............... 1600
5.16.212Error Counter (CPGC_ERR_CNTR[0])—Offset 4684h ............................... 1601
5.16.213Error Counter (CPGC_ERR_CNTR[1])—Offset 4688h ............................... 1602
5.16.214Error Counter (CPGC_ERR_CNTR[2])—Offset 468Ch............................... 1603
5.16.215Error Counter (CPGC_ERR_CNTR[3])—Offset 4690h ............................... 1604
5.16.216Error Counter (CPGC_ERR_CNTR[4])—Offset 4694h ............................... 1604
5.16.217Error Counter (CPGC_ERR_CNTR[5])—Offset 4698h ............................... 1605

38 334818
 5.16.218Error Counter (CPGC_ERR_CNTR[6])—Offset 469Ch ...............................1606
5.16.219Error Counter (CPGC_ERR_CNTR[7])—Offset 46A0h ...............................1606
5.16.220Error Counter (CPGC_ERR_CNTR[8])—Offset 46A4h ...............................1607
5.16.221Error Counter Overflow (CPGC_ERR_CNTR_OV)—Offset 46A8h ................1608
5.16.222Error Log Control and Status (CPGC_ERRLOG_CTL_STAT)—Offset 46ACh ..1609
5.16.223Error Log Data Access (CPGC_ERRLOG_DATA)—Offset 46B0h ..................1610
5.16.224Loopback Error Status (CPGC_ERR_TEST_ERR_STAT)—Offset 46B4h ........1611
5.16.225Rank Logical To Physical Map (CPGC_SEQ_RANK_L2P_MAPPING)—Offset 46B8h
1612
5.16.226Bank Logical to Physical Map Low (CPGC_SEQ_BANK_L2P_MAPPING_A)—Offset
46BCh ...............................................................................................1613
5.16.227Bank Logical to Physical Map High (CPGC_SEQ_BANK_L2P_MAPPING_B)—Offset
46C0h ...............................................................................................1614
5.16.228Rank Address Swizzle (CPGC_SEQ_RANK_ADDR_SWIZZLE)—Offset 46C4h1616
5.16.229Bank Address Swizzle (CPGC_SEQ_BANK_ADDR_SWIZZLE)—Offset 46C8h1617
5.16.230Row Address Swizzle Low (CPGC_SEQ_ROW_ADDR_SWIZZLE_A)—Offset 46CCh
1617
5.16.231Row Address Swizzle Mid (CPGC_SEQ_ROW_ADDR_SWIZZLE_B)—Offset 46D0h
1619
5.16.232Row Address Swizzle High (CPGC_SEQ_ROW_ADDR_SWIZZLE_C)—Offset
46D4h ...............................................................................................1620
5.16.233Row Address XOR (CPGC_SEQ_ROW_ADDR_SWIZZLE_X)—Offset 46D8h ..1621
5.16.234Column Address Swizzle Low (CPGC_SEQ_COL_ADDR_SWIZZLE_A)—Offset
46DCh ...............................................................................................1622
5.16.235Column Address Swizzle High (CPGC_SEQ_COL_ADDR_SWIZZLE_B)—Offset
46E0h................................................................................................1623
5.16.236DQ Inversion Lookup Data Low (CPGC_SEQ_ROW_ADDR_DQ_MAP0)—Offset
46E8h................................................................................................1624
5.16.237DQ Inversion Lookup Data High (CPGC_SEQ_ROW_ADDR_DQ_MAP1)—Offset
46ECh ...............................................................................................1625
5.17 Registers Summary ........................................................................................1627
5.17.1 Noncached Region Control (B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset
6B60h ...............................................................................................1627
5.18 Registers Summary ........................................................................................1629
5.18.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1000h .............................1630
5.18.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1008h ..........................1632
5.18.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 100Ch ..........................1633
5.18.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1010h ..........................1634
5.18.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1014h ..........................1635
5.18.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1018h ..........................1636
5.18.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 101Ch ..........................1637
5.18.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1020h ..........................1639
5.18.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1024h ..........................1640
5.18.10DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1028h ..........................1641
5.18.11D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 102Ch...................1642
5.18.12D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1030h ..........1643
5.18.13D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1034h ..........1645
5.18.14DRAM Refresh Control (D_CR_DRFC)—Offset 1038h.................................1647
5.18.15D-Unit Scheduler (D_CR_DSCH)—Offset 103Ch .......................................1649
5.18.16DRAM Calibration Control (D_CR_DCAL)—Offset 1040h ............................1651
5.18.17VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 104Ch ...................1652
5.18.18Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1050h..
1653
5.18.19TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1054h .............1654
5.18.20Data Scrambler (D_CR_SCRAMCTRL)—Offset 10A4h ................................1655
5.18.21Error Injection Address Register (D_CR_ERR_INJ)—Offset 10ACh ..............1656

334818 39
 5.18.22Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 10B0h ........ 1657
5.18.23Error Log Register (D_CR_ERR_ECC_LOG)—Offset 10B4h ........................ 1658
5.18.24D-Unit Status (D_CR_DFUSESTAT)—Offset 10BCh................................... 1659
5.18.25Major Mode Control (D_CR_MMC)—Offset 1124h..................................... 1659
5.18.26Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1128h
1660
5.18.27Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 112Ch
1661
5.18.28Access Class Initial Priority (D_CR_ACCIP)—Offset 1130h......................... 1662
5.18.29Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1134h.....
1663
5.18.30Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1138h.....
1663
5.18.31Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 113Ch ....
1664
5.18.32Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1140h.....
1665
5.18.33Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1144h.....
1666
5.18.34Deadline Threshold (D_CR_DL_THRS)—Offset 1148h............................... 1667
5.18.35Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 114Ch .......... 1667
5.18.36DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1154h ....... 1669
5.18.37DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1180h ..... 1670
5.18.38MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1184h............. 1671
5.19 Registers Summary........................................................................................ 1673
5.19.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1200h............................. 1674
5.19.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1208h ......................... 1676
5.19.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 120Ch ......................... 1677
5.19.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1210h ......................... 1678
5.19.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1214h ......................... 1679
5.19.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1218h ......................... 1680
5.19.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 121Ch ......................... 1681
5.19.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1220h ......................... 1683
5.19.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1224h ......................... 1684
5.19.10DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1228h ......................... 1685
5.19.11D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 122Ch .................. 1686
5.19.12D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1230h.......... 1687
5.19.13D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1234h.......... 1689
5.19.14DRAM Refresh Control (D_CR_DRFC)—Offset 1238h ................................ 1691
5.19.15D-Unit Scheduler (D_CR_DSCH)—Offset 123Ch ...................................... 1693
5.19.16DRAM Calibration Control (D_CR_DCAL)—Offset 1240h............................ 1695
5.19.17VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 124Ch .................. 1696
5.19.18Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1250h .
1697
5.19.19TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1254h ............. 1698
5.19.20Data Scrambler (D_CR_SCRAMCTRL)—Offset 12A4h................................ 1699
5.19.21Error Injection Address Register (D_CR_ERR_INJ)—Offset 12ACh .............. 1700
5.19.22Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 12B0h ........ 1701
5.19.23Error Log Register (D_CR_ERR_ECC_LOG)—Offset 12B4h ........................ 1702
5.19.24D-Unit Status (D_CR_DFUSESTAT)—Offset 12BCh................................... 1703
5.19.25Major Mode Control (D_CR_MMC)—Offset 1324h..................................... 1703
5.19.26Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1328h
1704
5.19.27Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 132Ch
1705
5.19.28Access Class Initial Priority (D_CR_ACCIP)—Offset 1330h......................... 1706

40 334818
 5.19.29Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1334h .....
1707
5.19.30Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1338h .....
1707
5.19.31Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 133Ch .....
1708
5.19.32Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1340h .....
1709
5.19.33Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1344h .....
1710
5.19.34Deadline Threshold (D_CR_DL_THRS)—Offset 1348h ...............................1711
5.19.35Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 134Ch ...........1711
5.19.36DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1354h........1713
5.19.37DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1380h ......1714
5.19.38MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1384h .............1715
5.20 Registers Summary ........................................................................................1717
5.20.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1400h .............................1718
5.20.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1408h ..........................1720
5.20.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 140Ch ..........................1721
5.20.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1410h ..........................1722
5.20.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1414h ..........................1723
5.20.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1418h ..........................1724
5.20.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 141Ch ..........................1725
5.20.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1420h ..........................1727
5.20.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1424h ..........................1728
5.20.10DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1428h ..........................1729
5.20.11D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 142Ch...................1730
5.20.12D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1430h ..........1731
5.20.13D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1434h ..........1733
5.20.14DRAM Refresh Control (D_CR_DRFC)—Offset 1438h.................................1735
5.20.15D-Unit Scheduler (D_CR_DSCH)—Offset 143Ch .......................................1737
5.20.16DRAM Calibration Control (D_CR_DCAL)—Offset 1440h ............................1739
5.20.17VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 144Ch ...................1740
5.20.18Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1450h..
1741
5.20.19TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1454h .............1742
5.20.20Data Scrambler (D_CR_SCRAMCTRL)—Offset 14A4h ................................1743
5.20.21Error Injection Address Register (D_CR_ERR_INJ)—Offset 14ACh ..............1744
5.20.22Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 14B0h.........1745
5.20.23Error Log Register (D_CR_ERR_ECC_LOG)—Offset 14B4h .........................1746
5.20.24D-Unit Status (D_CR_DFUSESTAT)—Offset 14BCh ...................................1747
5.20.25Major Mode Control (D_CR_MMC)—Offset 1524h .....................................1747
5.20.26Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1528h
1748
5.20.27Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 152Ch
1749
5.20.28Access Class Initial Priority (D_CR_ACCIP)—Offset 1530h .........................1750
5.20.29Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1534h .....
1751
5.20.30Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1538h .....
1751
5.20.31Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 153Ch .....
1752
5.20.32Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1540h .....
1753

334818 41
 5.20.33Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1544h.....
1754
5.20.34Deadline Threshold (D_CR_DL_THRS)—Offset 1548h............................... 1755
5.20.35Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 154Ch .......... 1755
5.20.36DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1554h ....... 1757
5.20.37DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1580h ..... 1758
5.20.38MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1584h............. 1759
5.21 Registers Summary........................................................................................ 1761
5.21.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1600h............................. 1762
5.21.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1608h ......................... 1764
5.21.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 160Ch ......................... 1765
5.21.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1610h ......................... 1766
5.21.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1614h ......................... 1767
5.21.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1618h ......................... 1768
5.21.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 161Ch ......................... 1769
5.21.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1620h ......................... 1771
5.21.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1624h ......................... 1772
5.21.10DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1628h ......................... 1773
5.21.11D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 162Ch .................. 1774
5.21.12D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1630h.......... 1775
5.21.13D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1634h.......... 1777
5.21.14DRAM Refresh Control (D_CR_DRFC)—Offset 1638h ................................ 1779
5.21.15D-Unit Scheduler (D_CR_DSCH)—Offset 163Ch ...................................... 1781
5.21.16DRAM Calibration Control (D_CR_DCAL)—Offset 1640h............................ 1783
5.21.17VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 164Ch .................. 1784
5.21.18Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1650h .
1785
5.21.19TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1654h ............. 1786
5.21.20Data Scrambler (D_CR_SCRAMCTRL)—Offset 16A4h................................ 1787
5.21.21Error Injection Address Register (D_CR_ERR_INJ)—Offset 16ACh .............. 1788
5.21.22Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 16B0h ........ 1789
5.21.23Error Log Register (D_CR_ERR_ECC_LOG)—Offset 16B4h ........................ 1790
5.21.24D-Unit Status (D_CR_DFUSESTAT)—Offset 16BCh................................... 1791
5.21.25Major Mode Control (D_CR_MMC)—Offset 1724h..................................... 1791
5.21.26Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1728h
1792
5.21.27Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 172Ch
1793
5.21.28Access Class Initial Priority (D_CR_ACCIP)—Offset 1730h......................... 1794
5.21.29Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1734h.....
1795
5.21.30Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1738h.....
1795
5.21.31Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 173Ch ....
1796
5.21.32Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1740h.....
1797
5.21.33Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1744h.....
1798
5.21.34Deadline Threshold (D_CR_DL_THRS)—Offset 1748h............................... 1799
5.21.35Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 174Ch .......... 1799
5.21.36DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1754h ....... 1801
5.21.37DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1780h ..... 1802
5.21.38MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1784h............. 1803
5.22 Registers Summary........................................................................................ 1805

42 334818
 5.22.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1A00h .............................1806
5.22.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1A08h ..........................1808
5.22.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 1A0Ch..........................1809
5.22.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1A10h ..........................1810
5.22.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1A14h ..........................1811
5.22.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1A18h ..........................1812
5.22.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 1A1Ch..........................1813
5.22.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1A20h ..........................1815
5.22.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1A24h ..........................1816
5.22.10DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1A28h ..........................1817
5.22.11D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 1A2Ch ..................1818
5.22.12D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1A30h ..........1819
5.22.13D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1A34h ..........1821
5.22.14DRAM Refresh Control (D_CR_DRFC)—Offset 1A38h ................................1823
5.22.15D-Unit Scheduler (D_CR_DSCH)—Offset 1A3Ch .......................................1825
5.22.16DRAM Calibration Control (D_CR_DCAL)—Offset 1A40h ............................1827
5.22.17VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 1A4Ch ...................1828
5.22.18Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1A50h..
1829
5.22.19TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1A54h .............1830
5.22.20Data Scrambler (D_CR_SCRAMCTRL)—Offset 1AA4h ................................1831
5.22.21Error Injection Address Register (D_CR_ERR_INJ)—Offset 1AACh ..............1832
5.22.22Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 1AB0h.........1833
5.22.23Error Log Register (D_CR_ERR_ECC_LOG)—Offset 1AB4h .........................1834
5.22.24D-Unit Status (D_CR_DFUSESTAT)—Offset 1ABCh ...................................1835
5.22.25Major Mode Control (D_CR_MMC)—Offset 1B24h .....................................1835
5.22.26Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1B28h
1836
5.22.27Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 1B2Ch
1837
5.22.28Access Class Initial Priority (D_CR_ACCIP)—Offset 1B30h .........................1838
5.22.29Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1B34h .....
1839
5.22.30Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1B38h .....
1839
5.22.31Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 1B3Ch .....
1840
5.22.32Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1B40h .....
1841
5.22.33Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1B44h .....
1842
5.22.34Deadline Threshold (D_CR_DL_THRS)—Offset 1B48h ...............................1843
5.22.35Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 1B4Ch...........1843
5.22.36DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1B54h........1845
5.22.37DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1B80h ......1846
5.22.38MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1B84h .............1847
5.23 Registers Summary ........................................................................................1849
5.23.1 Thermal Device Mailbox Data0
(P_CR_THERMAL_MAILBOX_DATA0_0_0_0_MCHBAR)—Offset 7000h .........1851
5.23.2 Thermal Device Mailbox Data1
(P_CR_THERMAL_MAILBOX_DATA1_0_0_0_MCHBAR)—Offset 7004h .........1852
5.23.3 Thermal Device Mailbox Interface
(P_CR_THERMAL_MAILBOX_INTERFACE_0_0_0_MCHBAR)—Offset 7008h ...1853
5.23.4 Thermal Device IRQ and Lock Configuration
(P_CR_THERMAL_DEVICE_IRQ_0_0_0_MCHBAR)—Offset 700Ch ...............1854

334818 43
 5.23.5 Package Thermal Interrupt Control
(P_CR_PKG_THERM_INTERRUPT_0_0_0_MCHBAR)—Offset 7010h............. 1855
5.23.6 ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR
(P_CR_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR)—Offset
7014h ............................................................................................... 1856
5.23.7 Package Thermal Status (P_CR_PKG_THERM_STATUS_0_0_0_MCHBAR)—Offset
701Ch ............................................................................................... 1857
5.23.8 LPDDR DRAM Thermal (MR4) Status of Channel 01
(P_CR_MEM_MR4_TEMPERATURE_DEV1_0_0_0_MCHBAR)—Offset 7024h .. 1859
5.23.9 LPDDR DRAM Thermal (MR4) Status of Channel 10
(P_CR_MEM_MR4_TEMPERATURE_DEV2_0_0_0_MCHBAR)—Offset 7028h .. 1859
5.23.10Machine Check Error Source Log (P_CR_MCA_ERROR_SRC_0_0_0_MCHBAR)—
Offset 702Ch...................................................................................... 1860
5.23.11DDR Thermal Throttling Control
(P_CR_DDR_THERM_THRT_CTRL_0_0_0_MCHBAR)—Offset 7030h ............ 1861
5.23.12DDR Thermal Interrupt Control
(P_CR_DDR_THERM_INTERRUPT_0_0_0_MCHBAR)—Offset 7034h ............ 1862
5.23.13DDR Thermal Status (P_CR_DDR_THERM_STATUS_0_0_0_MCHBAR)—Offset
7038h ............................................................................................... 1864
5.23.14Dram Energy Counter (P_CR_DDR_ENERGY_STATUS_0_0_0_MCHBAR)—Offset
7048h ............................................................................................... 1865
5.23.15DDR RAPL Performance Status
(P_CR_DDR_RAPL_PERF_STATUS_0_0_0_MCHBAR)—Offset 704Ch ........... 1866
5.23.16Package RAPL Performance Status
(P_CR_PACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR)—Offset 7050h .... 1867
5.23.17IA Core Performance / Power Priority Control
(P_CR_PRIMARY_PLANE_TURBO_PLCY_0_0_0_MCHBAR)—Offset 7054h .... 1868
5.23.18Graphics Performance / Power Priority Control
(P_CR_SECONDARY_PLANE_TURBO_PLCY_0_0_0_MCHBAR)—Offset 7058h 1868
5.23.19IA Energy Counter
(P_CR_PRIMARY_PLANE_ENERGY_STATUS_0_0_0_MCHBAR)—Offset 705Ch .....
1869
5.23.20Graphics Energy Counter
(P_CR_SECONDARY_PLANE_ENERGY_STATUS_0_0_0_MCHBAR)—Offset 7060h.
1870
5.23.21PACKAGE_POWER_SKU_UNIT
(P_CR_PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR)—Offset 7068h ...... 1871
5.23.22SOC Energy Counter (P_CR_PACKAGE_ENERGY_STATUS_0_0_0_MCHBAR)—
Offset 706Ch...................................................................................... 1872
5.23.23GT_PERF_STATUS (P_CR_GT_PERF_STATUS_0_0_0_MCHBAR)—Offset 7070h ...
1872
5.23.24Temperature Reference and Control
(P_CR_TEMPERATURE_TARGET_0_0_0_MCHBAR)—Offset 7074h .............. 1873
5.23.25BIOS Reset Completion (P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)—Offset
7078h ............................................................................................... 1874
5.23.26BIOS_MAILBOX_DATA (P_CR_BIOS_MAILBOX_DATA_0_0_0_MCHBAR)—Offset
7080h ............................................................................................... 1877
5.23.27BIOS_MAILBOX_INTERFACE
(P_CR_BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR)—Offset 7084h ........ 1877
5.23.28CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset 7088h 1878
5.23.29GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset 708Ch
1879
5.23.30SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset
7090h ............................................................................................... 1880

44 334818
 5.23.31Memory Frequency Status
(P_CR_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset
7094h................................................................................................1881
5.23.32Package Power SKU and RAPL Power Control Capabilities
(P_CR_PACKAGE_POWER_SKU_0_0_0_MCHBAR)—Offset 70A0h ...............1882
5.23.33Package RAPL Power Limit (P_CR_PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR)—
Offset 70A8h ......................................................................................1883
5.23.34IA_PERF_LIMIT_REASONS
(P_CR_IA_PERF_LIMIT_REASONS_0_0_0_MCHBAR)—Offset 70B0h ...........1885
5.23.35IA Core C0 Residency Counter
(P_CR_TELEM_IA_C0_RESIDENCY_0_0_0_MCHBAR)—Offset 70C0h...........1888
5.23.36Graphics C0 Residency Counter
(P_CR_TELEM_GT_C0_RESIDENCY_0_0_0_MCHBAR)—Offset 70C4h ..........1889
5.23.37I-unit Processing System C0 Residency Counter
(P_CR_TELEM_IUNIT_C0_RESIDENCY_0_0_0_MCHBAR)—Offset 70C8h......1889
5.23.38TELEM_IA_FREQ_ACCUMULATOR
(P_CR_TELEM_IA_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—Offset 70CCh..1890
5.23.39Graphics C0 Residency Counter
(P_CR_TELEM_GT_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—Offset 70D0h .1890
5.23.40I-unit Processing System C0 Residency Counter
(P_CR_TELEM_IUNIT_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—Offset 70D4h....
1891
5.23.41Memory Active Residency
(P_CR_TELEM_FAR_MEMORY_ACTIVE_0_0_0_MCHBAR)—Offset 70E8h ......1891
5.23.42Package Temperatures (P_CR_PACKAGE_TEMPERATURES_0_0_0_MCHBAR)—
Offset 70F4h.......................................................................................1892
5.23.43Package Thermal Limit Control
(P_CR_THERMAL_LIMIT_CONTROL_0_0_0_MCHBAR)—Offset 7104h ..........1893
5.23.44Memory Subsystem Frequency Capabilities
(P_CR_MEMSS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset 7108h .....
1894
5.23.45Memory Controller (MC) BIOS Reset Request and Status
(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR)—Offset 7114h ...........................1895
5.23.46MEMSS_FREQUENCY_CAPABILITIES1
(P_CR_MEMSS_FREQUENCY_CAPABILITIES1_0_0_0_MCHBAR)—Offset 7118h ...
1898
5.23.47PP1_C0_CORE_CLOCK_0_0_0_MCHBAR
(P_CR_PP1_C0_CORE_CLOCK_0_0_0_MCHBAR)—Offset 7160h .................1899
5.23.48Core Exists Vector (P_CR_CORE_EXISTS_VECTOR_0_0_0_MCHBAR)—Offset
7164h................................................................................................1900
5.23.49Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR)—
Offset 7168h ......................................................................................1900
5.23.50PL3 and PL4 Control (P_CR_PL3_CONTROL_0_0_0_MCHBAR)—Offset 71F0h ......
1902
5.23.51Graphics Superqueue Active Clocks
(P_CR_PP1_ANY_THREAD_ACTIVITY_0_0_0_MCHBAR)—Offset 7244h........1903
5.23.52LPDDR DRAM Thermal (MR4) Status of Channel 00
(P_CR_MEM_MR4_TEMPERATURE_DEV3_0_0_0_MCHBAR)—Offset 7248h...1904
5.23.53LPDDR DRAM Thermal (MR4) Status of Channel 11
(P_CR_MEM_MR4_TEMPERATURE_DEV4_0_0_0_MCHBAR)—Offset 724Ch ..1905
5.24 Registers Summary ........................................................................................1907
5.24.1 Upstream Device Arbiter Grant Count A2T
(A_CR_UPARB_GCNT_DEV_A2T_MCHBAR)—Offset 6400h .........................1909
5.24.2 Upstream A2B Arbiter Channel 0 Grant Count
(A_CR_UPARB_GCNT_A2B_0_MCHBAR)—Offset 6404h.............................1910
5.24.3 Upstream A2B Arbiter Channel 1 Grant Count
(A_CR_UPARB_GCNT_A2B_1_MCHBAR)—Offset 6408h.............................1911

334818 45
 5.24.4 Upstream A2B Arbiter Channel 2 Grant Count
(A_CR_UPARB_GCNT_A2B_2_MCHBAR)—Offset 640Ch ............................ 1912
5.24.5 Upstream A2B Arbiter Channel 3 Grant Count
(A_CR_UPARB_GCNT_A2B_3_MCHBAR)—Offset 6410h ............................ 1913
5.24.6 Upstream A2B Arbiter Channel 4 Grant Count
(A_CR_UPARB_GCNT_A2B_4_MCHBAR)—Offset 6414h ............................ 1914
5.24.7 Upstream A2B Arbiter Channel 5 Grant Count
(A_CR_UPARB_GCNT_A2B_5_MCHBAR)—Offset 6418h ............................ 1915
5.24.8 Upstream A2B Arbiter Channel 6 Grant Count
(A_CR_UPARB_GCNT_A2B_6_MCHBAR)—Offset 641Ch ............................ 1916
5.24.9 Upstream A2B Arbiter Channel 7 Grant Count
(A_CR_UPARB_GCNT_A2B_7_MCHBAR)—Offset 6420h ............................ 1916
5.24.10Upstream A2T Arbiter Channel 0 Grant Count
(A_CR_UPARB_GCNT_A2T_0_MCHBAR)—Offset 6424h ............................ 1917
5.24.11Upstream P2P Arbiter Channel 0 Grant Count
(A_CR_UPARB_GCNT_P2P_0_MCHBAR)—Offset 6428h ............................ 1918
5.24.12Upstream P2P Arbiter Channel 1 Grant Count
(A_CR_UPARB_GCNT_P2P_1_MCHBAR)—Offset 642Ch ............................ 1919
5.24.13Upstream Private Credit Return Grant Count Posted 0
(A_CR_CRDARB_PRIV_GCNT_DEV_P_0_MCHBAR)—Offset 6430h .............. 1920
5.24.14Upstream Private Credit Return Grant Count Posted 1
(A_CR_CRDARB_PRIV_GCNT_DEV_P_1_MCHBAR)—Offset 6434h .............. 1921
5.24.15Upstream Private Credit Return Grant Count Non-posted 0
(A_CR_CRDARB_PRIV_GCNT_DEV_N_0_MCHBAR)—Offset 6438h ............. 1921
5.24.16Upstream Private Credit Return Grant Count Posted 1
(A_CR_CRDARB_PRIV_GCNT_DEV_N_1_MCHBAR)—Offset 643Ch ............. 1922
5.24.17Upstream Private Credit Return Grant Count Completion
(A_CR_CRDARB_PRIV_GCNT_DEV_C_0_MCHBAR)—Offset 6440h.............. 1923
5.24.18Upstream Shared Credit Return Grant Count Posted 0
(A_CR_CRDARB_SHRD_GCNT_DEV_P_0_MCHBAR)—Offset 6444h ............ 1924
5.24.19Upstream Shared Credit Return Grant Count Posted 1
(A_CR_CRDARB_SHRD_GCNT_DEV_P_1_MCHBAR)—Offset 6448h ............ 1925
5.24.20Upstream Shared Credit Return Grant Count Non-posted 0
(A_CR_CRDARB_SHRD_GCNT_DEV_N_0_MCHBAR)—Offset 644Ch ............ 1925
5.24.21Upstream Shared Credit Return Grant Count Posted 1
(A_CR_CRDARB_SHRD_GCNT_DEV_N_1_MCHBAR)—Offset 6450h ............ 1926
5.24.22Upstream Shared Credit Return Grant Count Completion
(A_CR_CRDARB_SHRD_GCNT_DEV_C_0_MCHBAR)—Offset 6454h ............ 1927
5.24.23Upstream Credit Arbiter Private Credit Return Class Arbiter Grant Count
(A_CR_CRDARB_PRIV_GCNT_CLS_MCHBAR)—Offset 6458h ..................... 1928
5.24.24Upstream Credit Arbiter Shared Cedit Return Class Arbiter Grant Count
(A_CR_CRDARB_SHRD_GCNT_CLS_MCHBAR)—Offset 645Ch.................... 1928
5.24.25Gazelle Queue Limit Channel 0-3 (A_CR_GZLQ_LIMIT_CH0_3_MCHBAR)—Offset
6460h ............................................................................................... 1929
5.24.26Gazelle Queue Limit Channels 4-7 (A_CR_GZLQ_LIMIT_CH4_7_MCHBAR)—Offset
6464h ............................................................................................... 1930
5.24.27IOMMU Arbiter Grant Count VC0a Register
(A_CR_IOMMUARB_GCNT_VC0a_0_0_0_MCHBAR)—Offset 6468h ............. 1930
5.24.28IOMMU Arbiter Grant Count VC0b Register
(A_CR_IOMMUARB_GCNT_VC0b_0_0_0_MCHBAR)—Offset 646Ch ............. 1931
5.24.29IOMMU Arbiter Grant Count VC1b Register
(A_CR_IOMMUARB_GCNT_VC1b_0_0_0_MCHBAR)—Offset 6470h ............. 1932
5.24.30Gazelle Queue Reserved Entries Channels 0-3
(A_CR_GZLQ_RSVD_CH0_3_MCHBAR)—Offset 6474h ............................. 1933
5.24.31Gazelle Queue Reserved Entries Channels 4-7
(A_CR_GZLQ_RSVD_CH4_7_MCHBAR)—Offset 6478h ............................. 1933
5.24.32Spare BIOS (A_CR_SPARE_BIOS_MCHBAR)—Offset 647Ch....................... 1934

46 334818
 5.24.33Upcmd Credit Maximum Channel 0
(A_CR_UPCMD_CRDTMAX_CH0_0_0_0_MCHBAR)—Offset 6490h ...............1934
5.24.34Upcmd Credit Maximum Channel 1
(A_CR_UPCMD_CRDTMAX_CH1_0_0_0_MCHBAR)—Offset 6494h ...............1935
5.24.35Upcmd Credit Maximum Channel 2
(A_CR_UPCMD_CRDTMAX_CH2_0_0_0_MCHBAR)—Offset 6498h ...............1936
5.24.36Upcmd Credit Maximum Channel 3
(A_CR_UPCMD_CRDTMAX_CH3_0_0_0_MCHBAR)—Offset 649Ch...............1937
5.24.37Upcmd Credit Maximum Channel 4
(A_CR_UPCMD_CRDTMAX_CH4_0_0_0_MCHBAR)—Offset 64A0h...............1937
5.24.38Upcmd Credit Maximum Channel 5
(A_CR_UPCMD_CRDTMAX_CH5_0_0_0_MCHBAR)—Offset 64A4h...............1938
5.24.39Upcmd Credit Maximum Channel 6
(A_CR_UPCMD_CRDTMAX_CH6_0_0_0_MCHBAR)—Offset 64A8h...............1939
5.24.40Upcmd Credit Maximum Channel 7
(A_CR_UPCMD_CRDTMAX_CH7_0_0_0_MCHBAR)—Offset 64ACh ..............1939
5.24.41MOT OUT Base Register (A_CR_MOT_OUT_BASE_0_0_0_MCHBAR)—Offset
64C0h ...............................................................................................1940
5.24.42MOT OUT Mask Register (A_CR_MOT_OUT_MASK_0_0_0_MCHBAR)—Offset
64C4h ...............................................................................................1941
5.24.43CHAP Select 1 (A_CR_CHAP_SLCT1_MCHBAR)—Offset 6500h....................1942
5.24.44CHAP Select 2 (A_CR_CHAP_SLCT2_MCHBAR)—Offset 6504h....................1943
5.24.45CHAP Select 3 (A_CR_CHAP_SLCT3_MCHBAR)—Offset 6508h....................1944
5.24.46Slice and Channel Hash (A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR)—
Offset 65C0h ......................................................................................1944
5.24.47Mirror Range Register (A_CR_MIRROR_RANGE_0_0_0_MCHBAR)—Offset 65C8h.
1947
5.24.48ASYM MEM REGION 0 CONFIGURATION WITH NO INTERLEAVING
(A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR)—Offset 65D0h .................1948
5.24.49ASYM MEM REGION 1 CONFIGURATION WITH NO INTERLEAVING
(A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR)—Offset 65D4h .................1949
5.24.50Two-Way Asymmetric Memory Region Configuration
(A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR)—Offset 65D8h .........1950
5.25 Registers Summary ........................................................................................1953
5.25.1 B-Unit Miscellaneous Configuration (B_CR_BMISC_0_0_0_MCHBAR)—Offset
6800h................................................................................................1961
5.25.2 Slice 0 Memory Access Count (B_CR_MEM_ACCESS_COUNT_SLICE0)—Offset
6868h................................................................................................1962
5.25.3 Slice 1 Memory Access Count (B_CR_MEM_ACCESS_COUNT_SLICE1)—Offset
686Ch ...............................................................................................1963
5.25.4 IMR0 Mask (B_CR_BIMR0MASK_0_0_0_MCHBAR)—Offset 6874h...............1964
5.25.5 IMR0 Control Policy (B_CR_BIMR0CP_0_0_0_MCHBAR)—Offset 6878h .......1965
5.25.6 IMR0 Read Access Policy (B_CR_BIMR0RAC_0_0_0_MCHBAR)—Offset 6880h .....
1965
5.25.7 IMR0 Write Access Policy (B_CR_BIMR0WAC_0_0_0_MCHBAR)—Offset 6888h....
1971
5.25.8 IMR1 Base (B_CR_BIMR1BASE_0_0_0_MCHBAR)—Offset 6890h................1978
5.25.9 IMR1 Mask (B_CR_BIMR1MASK_0_0_0_MCHBAR)—Offset 6894h...............1979
5.25.10IMR1 Control Policy (B_CR_BIMR1CP_0_0_0_MCHBAR)—Offset 6898h .......1980
5.25.11IMR1 Read Access Policy (B_CR_BIMR1RAC_0_0_0_MCHBAR)—Offset 68A0h .....
1980
5.25.12IMR1 Write Access Policy (B_CR_BIMR1WAC_0_0_0_MCHBAR)—Offset 68A8h....
1985
5.25.13Base 0 IMR2 Base (B_CR_BIMR2BASE_0_0_0_MCHBAR)—Offset 68B0h .....1990
5.25.14IMR2 Mask (B_CR_BIMR2MASK_0_0_0_MCHBAR)—Offset 68B4h...............1991
5.25.15IMR2 Control Policy (B_CR_BIMR2CP_0_0_0_MCHBAR)—Offset 68B8h .......1992

334818 47
 5.25.16IMR2 Read Access Policy (B_CR_BIMR2RAC_0_0_0_MCHBAR)—Offset 68C0h ....
1992
5.25.17IMR2 Write Access Policy (B_CR_BIMR2WAC_0_0_0_MCHBAR)—Offset 68C8h ...
1997
5.25.18IMR3 Base (B_CR_BIMR3BASE_0_0_0_MCHBAR)—Offset 68D0h............... 2002
5.25.19IMR3 Mask (B_CR_BIMR3MASK_0_0_0_MCHBAR)—Offset 68D4h.............. 2003
5.25.20IMR3 Control Policy (B_CR_BIMR3CP_0_0_0_MCHBAR)—Offset 68D8h ...... 2004
5.25.21IMR3 Read Access Policy (B_CR_BIMR3RAC_0_0_0_MCHBAR)—Offset 68E0h ....
2005
5.25.22IMR3 Write Access Policy (B_CR_BIMR3WAC_0_0_0_MCHBAR)—Offset 68E8h ...
2009
5.25.23IMR4 Base (B_CR_BIMR4BASE_0_0_0_MCHBAR)—Offset 68F0h ............... 2014
5.25.24IMR4 Mask (B_CR_BIMR4MASK_0_0_0_MCHBAR)—Offset 68F4h .............. 2015
5.25.25B-Unit IMR4 Control Policy (B_CR_BIMR4CP_0_0_0_MCHBAR)—Offset 68F8h ....
2016
5.25.26IMR4 Read Access Policy (B_CR_BIMR4RAC_0_0_0_MCHBAR)—Offset 6900h ....
2017
5.25.27IMR4 Write Access Policy (B_CR_BIMR4WAC_0_0_0_MCHBAR)—Offset 6908h ...
2022
5.25.28IMR5 Base (B_CR_BIMR5BASE_0_0_0_MCHBAR)—Offset 6910h ............... 2028
5.25.29IMR5 Mask (B_CR_BIMR5MASK_0_0_0_MCHBAR)—Offset 6914h .............. 2029
5.25.30IMR5 Control Policy (B_CR_BIMR5CP_0_0_0_MCHBAR)—Offset 6918h....... 2030
5.25.31IMR5 Read Access Policy (B_CR_BIMR5RAC_0_0_0_MCHBAR)—Offset 6920h ....
2031
5.25.32IMR5 Write Access Policy (B_CR_BIMR5WAC_0_0_0_MCHBAR)—Offset 6928h ...
2035
5.25.33IMR6 Base (B_CR_BIMR6BASE_0_0_0_MCHBAR)—Offset 6930h ............... 2040
5.25.34IMR6 Mask (B_CR_BIMR6MASK_0_0_0_MCHBAR)—Offset 6934h .............. 2041
5.25.35IMR6 Control Policy (B_CR_BIMR6CP_0_0_0_MCHBAR)—Offset 6938h....... 2042
5.25.36IMR6 Read Access Policy (B_CR_BIMR6RAC_0_0_0_MCHBAR)—Offset 6940h ....
2043
5.25.37IMR6 Write Access Policy (B_CR_BIMR6WAC_0_0_0_MCHBAR)—Offset 6948h ...
2048
5.25.38IMR7 Base (B_CR_BIMR7BASE_0_0_0_MCHBAR)—Offset 6950h ............... 2052
5.25.39IMR7 Mask (B_CR_BIMR7MASK_0_0_0_MCHBAR)—Offset 6954h .............. 2053
5.25.40IMR7 Control Policy (B_CR_BIMR7CP_0_0_0_MCHBAR)—Offset 6958h....... 2054
5.25.41IMR7 Read Access Policy (B_CR_BIMR7RAC_0_0_0_MCHBAR)—Offset 6960h ....
2055
5.25.42IMR7 Write Access Policy (B_CR_BIMR7WAC_0_0_0_MCHBAR)—Offset 6968h ...
2060
5.25.43IMR8 Base (B_CR_BIMR8BASE_0_0_0_MCHBAR)—Offset 6970h ............... 2065
5.25.44IMR8 Mask (B_CR_BIMR8MASK_0_0_0_MCHBAR)—Offset 6974h .............. 2065
5.25.45IMR8 Control Policy (B_CR_BIMR8CP_0_0_0_MCHBAR)—Offset 6978h....... 2066
5.25.46IMR8 Read Access Policy (B_CR_BIMR8RAC_0_0_0_MCHBAR)—Offset 6980h ....
2067
5.25.47IMR8 Write Access Policy (B_CR_BIMR8WAC_0_0_0_MCHBAR)—Offset 6988h ...
2072
5.25.48IMR9 Base (B_CR_BIMR9BASE_0_0_0_MCHBAR)—Offset 6990h ............... 2077
5.25.49IMR9 Mask (B_CR_BIMR9MASK_0_0_0_MCHBAR)—Offset 6994h .............. 2078
5.25.50IMR9 Control Policy (B_CR_BIMR9CP_0_0_0_MCHBAR)—Offset 6998h....... 2079
5.25.51IMR9 Read Access Policy (B_CR_BIMR9RAC_0_0_0_MCHBAR)—Offset 69A0h ....
2079
5.25.52IMR9 Write Access Policy (B_CR_BIMR9WAC_0_0_0_MCHBAR)—Offset 69A8h ...
2085
5.25.53IMR10 Base (B_CR_BIMR10BASE_0_0_0_MCHBAR)—Offset 69B0h ........... 2089
5.25.54IMR10 Mask (B_CR_BIMR10MASK_0_0_0_MCHBAR)—Offset 69B4h .......... 2090

48 334818
 5.25.55IMR10 Control Policy (B_CR_BIMR10CP_0_0_0_MCHBAR)—Offset 69B8h....2091
5.25.56IMR10 Read Access Policy (B_CR_BIMR10RAC_0_0_0_MCHBAR)—Offset 69C0h .
2092
5.25.57IMR10 Write Access Policy (B_CR_BIMR10WAC_0_0_0_MCHBAR)—Offset 69C8h
2097
5.25.58IMR11 Base (B_CR_BIMR11BASE_0_0_0_MCHBAR)—Offset 69D0h ............2102
5.25.59IMR11 Mask (B_CR_BIMR11MASK_0_0_0_MCHBAR)—Offset 69D4h ...........2102
5.25.60IMR11 Control Policy (B_CR_BIMR11CP_0_0_0_MCHBAR)—Offset 69D8h ...2103
5.25.61IMR11 Read Access Policy (B_CR_BIMR11RAC_0_0_0_MCHBAR)—Offset 69E0h .
2104
5.25.62IMR11 Write Access Policy (B_CR_BIMR11WAC_0_0_0_MCHBAR)—Offset 69E8h
2109
5.25.63IMR12 Base (B_CR_BIMR12BASE_0_0_0_MCHBAR)—Offset 69F0h ............2114
5.25.64IMR12 Mask (B_CR_BIMR12MASK_0_0_0_MCHBAR)—Offset 69F4h ...........2115
5.25.65IMR12 Control Policy (B_CR_BIMR12CP_0_0_0_MCHBAR)—Offset 69F8h ....2116
5.25.66IMR12 Read Access Policy (B_CR_BIMR12RAC_0_0_0_MCHBAR)—Offset 6A00h .
2116
5.25.67IMR12 Write Access Policy (B_CR_BIMR12WAC_0_0_0_MCHBAR)—Offset 6A08h
2121
5.25.68IMR13 Base (B_CR_BIMR13BASE_0_0_0_MCHBAR)—Offset 6A10h ............2126
5.25.69IMR13 Mask (B_CR_BIMR13MASK_0_0_0_MCHBAR)—Offset 6A14h ...........2127
5.25.70IMR13 Control Policy (B_CR_BIMR13CP_0_0_0_MCHBAR)—Offset 6A18h....2128
5.25.71IMR13 Read Access Policy (B_CR_BIMR13RAC_0_0_0_MCHBAR)—Offset 6A20h .
2129
5.25.72IMR13 Write Access Policy (B_CR_BIMR13WAC_0_0_0_MCHBAR)—Offset 6A28h
2134
5.25.73IMR14 Base (B_CR_BIMR14BASE_0_0_0_MCHBAR)—Offset 6A30h ............2138
5.25.74IMR14 Mask (B_CR_BIMR14MASK_0_0_0_MCHBAR)—Offset 6A34h ...........2139
5.25.75IMR14 Control Policy (B_CR_BIMR14CP_0_0_0_MCHBAR)—Offset 6A38h....2140
5.25.76IMR14 Read Access Policy (B_CR_BIMR14RAC_0_0_0_MCHBAR)—Offset 6A40h .
2141
5.25.77IMR14 Write Access Policy (B_CR_BIMR14WAC_0_0_0_MCHBAR)—Offset 6A48h
2146
5.25.78IMR15 Base (B_CR_BIMR15BASE_0_0_0_MCHBAR)—Offset 6A50h ............2151
5.25.79IMR15 Mask (B_CR_BIMR15MASK_0_0_0_MCHBAR)—Offset 6A54h ...........2151
5.25.80IMR15 Control Policy (B_CR_BIMR15CP_0_0_0_MCHBAR)—Offset 6A58h....2152
5.25.81IMR15 Read Access Policy (B_CR_BIMR15RAC_0_0_0_MCHBAR)—Offset 6A60h .
2153
5.25.82IMR15 Write Access Policy (B_CR_BIMR15WAC_0_0_0_MCHBAR)—Offset 6A68h
2158
5.25.83IMR16 Base (B_CR_BIMR16BASE_0_0_0_MCHBAR)—Offset 6A70h ............2163
5.25.84IMR16 Mask (B_CR_BIMR16MASK_0_0_0_MCHBAR)—Offset 6A74h ...........2164
5.25.85IMR16 Control Policy (B_CR_BIMR16CP_0_0_0_MCHBAR)—Offset 6A78h....2165
5.25.86IMR16 Read Access Policy (B_CR_BIMR16RAC_0_0_0_MCHBAR)—Offset 6A80h .
2165
5.25.87IMR16 Write Access Policy (B_CR_BIMR16WAC_0_0_0_MCHBAR)—Offset 6A88h
2170
5.25.88IMR17 Base (B_CR_BIMR17BASE_0_0_0_MCHBAR)—Offset 6A90h ............2175
5.25.89IMR17 Mask (B_CR_BIMR17MASK_0_0_0_MCHBAR)—Offset 6A94h ...........2176
5.25.90IMR17 Control Policy (B_CR_BIMR17CP_0_0_0_MCHBAR)—Offset 6A98h....2177
5.25.91IMR17 Read Access Policy (B_CR_BIMR17RAC_0_0_0_MCHBAR)—Offset 6AA0h .
2178
5.25.92IMR17 Write Access Policy (B_CR_BIMR17WAC_0_0_0_MCHBAR)—Offset 6AA8h
2183
5.25.93IMR18 Base (B_CR_BIMR18BASE_0_0_0_MCHBAR)—Offset 6AB0h ............2187
5.25.94IMR18 Mask (B_CR_BIMR18MASK_0_0_0_MCHBAR)—Offset 6AB4h ...........2188

334818 49
 5.25.95IMR18 Control Policy (B_CR_BIMR18CP_0_0_0_MCHBAR)—Offset 6AB8h ... 2189
5.25.96IMR18 Read Access Policy (B_CR_BIMR18RAC_0_0_0_MCHBAR)—Offset 6AC0h.
2190
5.25.97IMR18 Write Access Policy (B_CR_BIMR18WAC_0_0_0_MCHBAR)—Offset 6AC8h
2195
5.25.98IMR19 Base (B_CR_BIMR19BASE_0_0_0_MCHBAR)—Offset 6AD0h ........... 2201
5.25.99IMR19 Mask (B_CR_BIMR19MASK_0_0_0_MCHBAR)—Offset 6AD4h .......... 2202
5.25.100IMR19 Control Policy (B_CR_BIMR19CP_0_0_0_MCHBAR)—Offset 6AD8h . 2203
5.25.101IMR19 Read Access Policy (B_CR_BIMR19RAC_0_0_0_MCHBAR)—Offset 6AE0h
2204
5.25.102IMR19 Write Access Policy (B_CR_BIMR19WAC_0_0_0_MCHBAR)—Offset 6AE8h
2209
5.25.103MOT Out Base (B_CR_MOT_OUT_BASE_0_0_0_MCHBAR)—Offset 6AF0h .. 2213
5.25.104MOT Out Mask (B_CR_MOT_OUT_MASK_0_0_0_MCHBAR)—Offset 6AF4h . 2214
5.25.105MOT Buffer Control Policy (B_CR_BMOT_BUF_CP_0_0_0_MCHBAR)—Offset
6AF8h ............................................................................................... 2215
5.25.106MOT Buffer Read Access Policy (B_CR_BMOT_BUF_RAC_0_0_0_MCHBAR)—
Offset 6B00h...................................................................................... 2216
5.25.107MOT Buffer Write Access Policy (B_CR_BMOT_BUF_WAC_0_0_0_MCHBAR)—
Offset 6B08h...................................................................................... 2221
5.25.108IMR Global BM Control Policy (B_CR_BIMRGLOBAL_BM_CP_0_0_0_MCHBAR)—
Offset 6B10h...................................................................................... 2227
5.25.109IMR Global BM Read Access Control
(B_CR_BIMRGLOBAL_BM_RAC_0_0_0_MCHBAR)—Offset 6B18h ............... 2228
5.25.110IMR Global BM Write Access Policy
(B_CR_BIMRGLOBAL_BM_WAC_0_0_0_MCHBAR)—Offset 6B20h .............. 2228
5.25.111Graphics Stolen Memory Control Policy (B_CR_BGSMCP_0_0_0_MCHBAR)—
Offset 6B28h...................................................................................... 2229
5.25.112GSM Read Access Policy (B_CR_BGSMRAC_0_0_0_MCHBAR)—Offset 6B30h ....
2230
5.25.113GSM Write Access Policy (B_CR_BGSMWAC_0_0_0_MCHBAR)—Offset 6B38h ...
2236
5.25.114TPM Control Policy (B_CR_TPM_CP_0_0_0_MCHBAR)—Offset 6B40h ........ 2242
5.25.115TPM Access Control (B_CR_TPM_AC_0_0_0_MCHBAR)—Offset 6B48h....... 2243
5.25.116BGSM Control Register (B_CR_BGSM_CTRL_0_0_0_MCHBAR)—Offset 6B50h ...
2243
5.25.117SMM Control Register (B_CR_BSMR_CTRL_0_0_0_MCHBAR)—Offset 6B54h .....
2244
5.25.118Default VTd Control Register (B_CR_BDEFVTDPMR_CTRL_0_0_0_MCHBAR)—
Offset 6B58h...................................................................................... 2245
5.25.119MOT Trigger Trace Control (B_CR_MOT_TRIG_TRACE_CTRL_0_0_0_MCHBAR)—
Offset 6B7Ch...................................................................................... 2246
5.25.120MOT Slice 0 Memory Pointer
(B_CR_MOT_SLICE_0_MEM_PTR_0_0_0_MCHBAR)—Offset 6B80h ............ 2249
5.25.121MOT Slice 1 Memory Pointer
(B_CR_MOT_SLICE_1_MEM_PTR_0_0_0_MCHBAR)—Offset 6B88h ............ 2250
5.25.122MOT Slice 0 Record ID (B_CR_MOT_SLICE_0_RECORD_ID_0_0_0_MCHBAR)—
Offset 6B90h...................................................................................... 2251
5.25.123MOT Slice 1 Record ID (B_CR_MOT_SLICE_1_RECORD_ID_0_0_0_MCHBAR)—
Offset 6B94h...................................................................................... 2251
5.25.124MOT Filter Match 0 (B_CR_MOT_FILTER_MATCH0_0_0_0_MCHBAR)—Offset
6BA0h............................................................................................... 2252
5.25.125MOT Filter Mask (B_CR_MOT_FILTER_MASK0_0_0_0_MCHBAR)—Offset 6BA8h
2253
5.25.126MOT Filter Match 1 (B_CR_MOT_FILTER_MATCH1_0_0_0_MCHBAR)—Offset
6BB0h............................................................................................... 2254

50 334818
 5.25.127MOT Filter Mask 1 (B_CR_MOT_FILTER_MASK1_0_0_0_MCHBAR)—Offset
6BB8h ...............................................................................................2254
5.25.128MOT Filter Misc 0 (B_CR_MOT_FILTER_MISC0_0_0_0_MCHBAR)—Offset 6BC0h
2255
5.25.129MOT Filter Misc 1 (B_CR_MOT_FILTER_MISC1_0_0_0_MCHBAR)—Offset 6BC8h
2256
5.25.130MOT Trigger Match 0 (B_CR_MOT_TRIGGER_MATCH0_0_0_0_MCHBAR)—Offset
6BD0h ...............................................................................................2257
5.25.131MOT Trigger Mask 0 (B_CR_MOT_TRIGGER_MASK0_0_0_0_MCHBAR)—Offset
6BD8h ...............................................................................................2258
5.25.132MOT Trigger Match 1 (B_CR_MOT_TRIGGER_MATCH1_0_0_0_MCHBAR)—Offset
6BE0h ...............................................................................................2259
5.25.133MOT Trigger Mask 1 (B_CR_MOT_TRIGGER_MASK1_0_0_0_MCHBAR)—Offset
6BE8h ...............................................................................................2260
5.25.134MOT Trigger Misc 0 (B_CR_MOT_TRIGGER_MISC0_0_0_0_MCHBAR)—Offset
6BF0h................................................................................................2261
5.25.135MOT Trigger Misc 1 (B_CR_MOT_TRIGGER_MISC1_0_0_0_MCHBAR)—Offset
6BF8h................................................................................................2262
5.25.136BIOSWR Control Policy (B_CR_BIOSWR_CP_0_0_0_MCHBAR)—Offset 6C08h....
2263
5.25.137BIOSWR Read Access Policy (B_CR_BIOSWR_RAC_0_0_0_MCHBAR)—Offset
6C10h ...............................................................................................2263
5.25.138BIOSWR Write Access Policy (B_CR_BIOSWR_WAC_0_0_0_MCHBAR)—Offset
6C18h ...............................................................................................2264
5.25.139TPM Selector (B_CR_TPM_SELECTOR_0_0_0_MCHBAR)—Offset 6C24h .....2264
5.25.140B-Unit Pcode/Ucode Write, All Read Control Policy Register
(B_CR_P_U_CODEWR_ALLRD_CP_0_0_0_MCHBAR)—Offset 6C28h ............2265
5.25.141B-Unit Pcode/Ucode Read Access Policy
(B_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCHBAR)—Offset 6C30h..........2266
5.25.142B-Unit Pcode/Ucode Write Access Policy
(B_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_MCHBAR)—Offset 6C38h .........2266
5.25.143Default VTd BAR (B_CR_DEFVTDBAR_0_0_0_MCHBAR)—Offset 6C80h .....2267
5.25.144Gfx VTd BAR (B_CR_GFXVTDBAR_0_0_0_MCHBAR)—Offset 6C88h...........2268
5.25.145B-Unit Lites Group 0 Control (B_CR_LITES0_CTL_0_0_0_MCHBAR)—Offset
6C90h ...............................................................................................2269
5.25.146B-Unit Lites Group 0 Opcode Match Filter
(B_CR_LITES0_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6C94h.............2271
5.25.147B-Unit Lites Group 0 Agent Match Filter
(B_CR_LITES0_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6C98h ...............2273
5.25.148B-Unit Lites Group 0 U2C IntData Match Filter
(B_CR_LITES0_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6C9Ch ......2275
5.25.149B-Unit Lites Group 0 Address Match Filter LITES0_ADDR_MATCH
(B_CR_LITES0_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6CA0h ................2275
5.25.150B-Unit Lites Group 0 Address Mask Filter LITES0_ADDR_MASK
(B_CR_LITES0_ADDR_MASK_0_0_0_MCHBAR)—Offset 6CA8h ..................2276
5.25.151B-Unit Lites Group 0 Data Match Filter LITES0_DATA_MATCH
(B_CR_LITES0_DATA_MATCH_0_0_0_MCHBAR)—Offset 6CB0h.................2277
5.25.152B-Unit Lites Group 0 Data Mask Filter LITES0_DATA_MASK
(B_CR_LITES0_DATA_MASK_0_0_0_MCHBAR)—Offset 6CB4h...................2277
5.25.153B-Unit Lites Group 1 Control (B_CR_LITES1_CTL_0_0_0_MCHBAR)—Offset
6CC0h ...............................................................................................2278
5.25.154B-Unit Lites Group 1 Opcode Match Filter
(B_CR_LITES1_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6CC4h.............2280
5.25.155B-Unit Lites Group 1 Agent Match Filter
(B_CR_LITES1_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6CC8h ...............2282
5.25.156B-Unit Lites Group 1 U2C IntData Match Filter
(B_CR_LITES1_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6CCCh ......2284

334818 51
 5.25.157B-Unit Lites Group 1 Address Match Filter LITES1_ADDR_MATCH
(B_CR_LITES1_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6CD0h ............... 2284
5.25.158B-Unit Lites Group 1 Address Mask Filter LITES1_ADDR_MASK
(B_CR_LITES1_ADDR_MASK_0_0_0_MCHBAR)—Offset 6CD8h ................. 2285
5.25.159B-Unit Lites Group 1 Data Match Filter LITES1_DATA_MATCH
(B_CR_LITES1_DATA_MATCH_0_0_0_MCHBAR)—Offset 6CE0h ................ 2286
5.25.160B-Unit Lites Group 1 Data Mask Filter LITES1_DATA_MASK
(B_CR_LITES1_DATA_MASK_0_0_0_MCHBAR)—Offset 6CE4h .................. 2286
5.25.161B-Unit Lites Group 2 Control (B_CR_LITES2_CTL_0_0_0_MCHBAR)—Offset
6CF0h ............................................................................................... 2287
5.25.162B-Unit Lites Group 2 Opcode Match Filter
(B_CR_LITES2_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6CF4h ............ 2289
5.25.163B-Unit Lites Group 2 Agent Match Filter
(B_CR_LITES2_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6CF8h............... 2291
5.25.164B-Unit Lites Group 2 U2C IntData Match Filter
(B_CR_LITES2_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6CFCh...... 2293
5.25.165B-Unit Lites Group 2 Address Match Filter LITES2_ADDR_MATCH
(B_CR_LITES2_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6D00h................ 2293
5.25.166B-Unit Lites Group 2 Address Mask Filter LITES2_ADDR_MASK
(B_CR_LITES2_ADDR_MASK_0_0_0_MCHBAR)—Offset 6D08h.................. 2294
5.25.167B-Unit Lites Group 2 Data Match Filter LITES2_DATA_MATCH
(B_CR_LITES2_DATA_MATCH_0_0_0_MCHBAR)—Offset 6D10h ................ 2295
5.25.168B-Unit Lites Group 2 Data Mask Filter LITES2_DATA_MASK
(B_CR_LITES2_DATA_MASK_0_0_0_MCHBAR)—Offset 6D14h .................. 2295
5.25.169B-Unit Lites Group 3 Control (B_CR_LITES3_CTL_0_0_0_MCHBAR)—Offset
6D20h............................................................................................... 2296
5.25.170B-Unit Lites Group 3 Opcode Match Filter
(B_CR_LITES3_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6D24h ............ 2298
5.25.171B-Unit Lites Group 3 Agent Match Filter
(B_CR_LITES3_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6D28h .............. 2300
5.25.172B-Unit Lites Group 3 U2C IntData Match Filter
(B_CR_LITES3_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6D2Ch ..... 2302
5.25.173B-Unit Lites Group 3 Address Match Filter LITES3_ADDR_MATCH
(B_CR_LITES3_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6D30h................ 2302
5.25.174B-Unit Lites Group 3 Address Mask Filter LITES3_ADDR_MASK
(B_CR_LITES3_ADDR_MASK_0_0_0_MCHBAR)—Offset 6D38h.................. 2303
5.25.175B-Unit Lites Group 3 Data Match Filter LITES3_DATA_MATCH
(B_CR_LITES3_DATA_MATCH_0_0_0_MCHBAR)—Offset 6D40h ................ 2304
5.25.176B-Unit Lites Group 3 Data Mask Filter LITES3_DATA_MASK
(B_CR_LITES3_DATA_MASK_0_0_0_MCHBAR)—Offset 6D44h .................. 2304
5.25.177B-Unit Lites and Emon Master Control LITESEMONCTL
(B_CR_LITESEMON_CTL_0_0_0_MCHBAR)—Offset 6D48h........................ 2305
5.25.178B-Unit Arbiter Control BARBCTRL0 (B_CR_BARBCTRL0)—Offset 6D4Ch..... 2307
5.25.179B-Unit Arbiter Control BARBCTRL1 (B_CR_BARBCTRL1)—Offset 6D50h ..... 2308
5.25.180B-Unit Scheduler Control (B_CR_BSCHWT0)—Offset 6D54h .................... 2309
5.25.181B-Unit Scheduler Control (B_CR_BSCHWT1)—Offset 6D58h .................... 2309
5.25.182B-Unit Scheduler Control (B_CR_BSCHWT2)—Offset 6D5Ch .................... 2310
5.25.183B-Unit Scheduler Control (B_CR_BSCHWT3)—Offset 6D60h .................... 2311
5.25.184B-Unit Flush Control (B_CR_BWFLUSH)—Offset 6D64h ........................... 2312
5.25.185B-Unit Flush Weights (B_CR_BFLWT)—Offset 6D68h .............................. 2313
5.25.186Weighted Scheduling Control of High Priority ISOC and Other Requests
(B_CR_BISOCWT)—Offset 6D6Ch ......................................................... 2314
5.25.187B-Unit Control (B_CR_BCTRL2)—Offset 6D70h ...................................... 2315
5.25.188Asset Classification Bits (B_CR_AC_RS0_0_0_0_MCHBAR)—Offset 6D74h . 2317
5.25.189IDI Real-Time Feature Configuration Bits (B_CR_RT_EN_0_0_0_MCHBAR)—
Offset 6D78h ..................................................................................... 2317
5.25.190B-Unit Control Register 3 (B_CR_BCTRL3)—Offset 6D7Ch ....................... 2318

52 334818
 5.25.191Asymmetric Memory Region 0 With No Interleaving Configuration
(B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR)—Offset 6E40h .................2319
5.25.192Asymmetric Memory Region 1 With No Interleaving Configuration
(B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR)—Offset 6E44h .................2320
5.25.193B-Unit Machine Check Mode Low (B_CR_BMCMODE_LOW)—Offset 6E48h ..2321
5.25.194B-Unit Machine Check Mode High (B_CR_BMCMODE_HIGH)—Offset 6E4Ch 2322
5.25.195Two-Way Asymmetric Memory Region Configuration
(B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR)—Offset 6E50h .........2322
5.26 Registers Summary ........................................................................................2325
5.26.1 X2B_BARB_CTL1 (X2B_BARB_CTL1_MCHBAR)—Offset 7804h....................2326
5.26.2 Clock Gating Control (CLKGATE_CTL_MCHBAR)—Offset 7808h ..................2327
5.26.3 Miscellaneous Controls (MISC_CTL_MCHBAR)—Offset 780Ch .....................2329
5.26.4 CMiscellaneous T2A selector (T2A_SELECTOR_MISC_MCHBAR)—Offset 7818h ....
2331
5.26.5 VC Read Ordering CFG (VC_READ_ORDERING_CFG_MCHBAR)—Offset 781Ch.....
2332
5.26.6 VC Write Ordering CFG (VC_WRITE_ORDERING_CFG_MCHBAR)—Offset 7820h...
2334
5.26.7 IDI0 C2U Credit Control (IDI0_C2U_CREDIT_CTRL_MCHBAR)—Offset 7824h......
2337
5.26.8 IDI1 C2U Credit Control (IDI1_C2U_CREDIT_CTRL_MCHBAR)—Offset 7828h......
2338
5.26.9 IDI2 C2U Credit Control (IDI2_C2U_CREDIT_CTRL_MCHBAR)—Offset 782Ch......
2339
5.26.10IDI3 C2U Credit Control (IDI3_C2U_CREDIT_CTRL_MCHBAR)—Offset 7830h......
2341
5.26.11IDI4 C2U Credit Control (IDI4_C2U_CREDIT_CTRL_MCHBAR)—Offset 7834h......
2342
5.26.12IDI5 C2U Credit Control (IDI5_C2U_CREDIT_CTRL_MCHBAR)—Offset 7838h......
2343
5.26.13IDI6 C2U Credit Control (IDI6_C2U_CREDIT_CTRL_MCHBAR)—Offset 783Ch......
2344
5.26.14IDI7 C2U Credit Control (IDI7_C2U_CREDIT_CTRL_MCHBAR)—Offset 7840h......
2346
5.26.15PII2 A2T Credit Control (PII2_A2T_CREDIT_CTRL_MCHBAR)—Offset 7844h 2347
5.26.16BIOSWR Control Policy (T_CR_BIOSWR_CP_0_0_0_MCHBAR)—Offset 7848h .....
2348
5.26.17BIOSWR Read Access Control (T_CR_BIOSWR_RAC_0_0_0_MCHBAR)—Offset
7850h................................................................................................2349
5.26.18BIOSWR Write Access Control (T_CR_BIOSWR_WAC_0_0_0_MCHBAR)—Offset
7858h................................................................................................2349
5.26.19TUnit Pcode/Ucode Write, All Read Control Policy Register
(T_CR_P_U_CODEWR_ALLRD_CP_0_0_0_MCHBAR)—Offset 7860h ............2350
5.26.20TUnit Pcode/Ucode Read Access Control
(T_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCHBAR)—Offset 7868h ..........2350
5.26.21TUnit Pcode/Ucode Write Access Control
(T_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_MCHBAR)—Offset 7870h .........2351
6 Graphics and Displays ..........................................................................................2353
6.1 Registers Summary ........................................................................................2355
6.1.1 (CTXREG1)—Offset FF4h .....................................................................2355
6.1.2 (PAVP1)—Offset 31030h.......................................................................2355
6.1.3 (PAVP2)—Offset 323A4h .....................................................................2356
7 MDSI ....................................................................................................................2357
7.1 Registers Summary ........................................................................................2357
7.1.1 LJPLL_RW_CONTROL_1 (LJPLL_CR_RW_CONTROL_1)—Offset 10h .............2357

334818 53
 7.1.2 LJPLL_RW_CONTROL_2 (LJPLL_CR_RW_CONTROL_2)—Offset 14h ............ 2357
7.1.3 dsipll_cp (dsipll_cp)—Offset 20h ........................................................... 2358
7.1.4 dsipll_rac (dsipll_rac)—Offset 28h ......................................................... 2359
7.1.5 dsipll_wac (dsipll_wac)—Offset 30h....................................................... 2359
7.2 ................................................................................................................... 2359
7.3 Registers Summary........................................................................................ 2361
7.3.1 LJPLL_RW_CONTROL_1 (LJPLL_CR_RW_CONTROL_1)—Offset 10h ............ 2361
7.3.2 LJPLL_RW_CONTROL_2 (LJPLL_CR_RW_CONTROL_2)—Offset 14h ............ 2361
7.3.3 dsipll_cp (dsipll_cp)—Offset 20h ........................................................... 2362
7.3.4 dsipll_rac (dsipll_rac)—Offset 28h ......................................................... 2362
7.3.5 dsipll_wac (dsipll_wac)—Offset 30h....................................................... 2363
8 System Agent....................................................................................................... 2365
8.1 Registers Summary........................................................................................ 2365
8.1.1 B-Unit Copy of the MCHBAR (B_CR_MCHBAR_LO_0_0_0_PCI)—Offset 48h . 2365
8.1.2 B-Unit Copy of the MCHBAR (B_CR_MCHBAR_HI_0_0_0_PCI)—Offset 4Ch . 2366
8.1.3 B-Unit Shadow of GGC (B_CR_GGC_0_0_0_PCI)—Offset 50h ................... 2367
8.1.4 B-Unit Shadow of the DEVEN Register (B_CR_DEVEN_0_0_0_PCI)—Offset 54h ..
2369
8.1.5 B-Unit PCI Express Enhanced Configuration Range Base Address Low
(B_CR_PCIEXBAR_LO_0_0_0_PCI)—Offset 60h ...................................... 2370
8.1.6 B-Unit PCI Express Enhanced Configuration Range Base Address High
(B_CR_PCIEXBAR_HI_0_0_0_PCI)—Offset 64h ....................................... 2371
8.1.7 Top of Upper Usable DRAM Low (B_CR_TOUUD_LO_0_0_0_PCI)—Offset A8h.....
2372
8.1.8 Top of Upper Usable DRAM High (B_CR_TOUUD_HI_0_0_0_PCI)—Offset ACh ....
2372
8.1.9 Base of Graphics Stolen Memory (B_CR_BGSM_0_0_0_PCI)—Offset B4h.... 2373
8.1.10 B-Unit Copy of the TSEG Memory Base (B_CR_TSEGMB_0_0_0_PCI)—Offset B8h
2374
8.1.11 Top of Lower Usable DRAM (B_CR_TOLUD_0_0_0_PCI)—Offset BCh .......... 2375
8.1.12 Capability ID0 A (B_CR_CAPID0_A_0_0_0_PCI)—Offset E4h .................... 2376
8.1.13 Capability ID0 B (B_CR_CAPID0_B_0_0_0_PCI)—Offset E8h .................... 2378
8.2 Registers Summary........................................................................................ 2379
8.2.1 B-Unit Copy of PCICMD for IGD (B_CR_PCICMD_0_2_0_PCI)—Offset 4h .... 2379
8.2.2 B-Unit Copy of GTTMMADR (B_CR_GTTMMADR_LO_0_2_0_PCI)—Offset 10h .....
2380
8.2.3 B-Unit Copy of GTTMMADR (B_CR_GTTMMADR_HI_0_2_0_PCI)—Offset 14h......
2381
8.2.4 B-Unit Copy of GMADR (B_CR_GMADR_LO_0_2_0_PCI)—Offset 18h.......... 2382
8.2.5 B-Unit Copy of GMADR (B_CR_GMADR_HI_0_2_0_PCI)—Offset 1Ch .......... 2383
8.2.6 B-Unit Copy of the IOBAR (B_CR_IOBAR_0_2_0_PCI)—Offset 20h ............ 2383
8.2.7 B-Unit Copy of Device 2 Control Register (B_CR_DEV2CTL_0_2_0_PCI)—Offset
58h................................................................................................... 2384
8.2.8 B-Unit Copy of MSAC (B_CR_MSAC_0_2_0_PCI)—Offset 62h .................... 2385
8.2.9 B-Unit Copy of Device 2 Control Register (B_CR_DEVICECTL_0_2_0_PCI)—Offset
78h................................................................................................... 2386
8.2.10 B-Unit Copy of PMCS for IGD (B_CR_PMCS_0_2_0_PCI)—Offset D4h......... 2387
8.3 Registers Summary........................................................................................ 2388
8.3.1 PCICMD for I-Unit in Device 3 Mode (B_CR_PCICMD_0_3_0_PCI)—Offset 4h .....
2389
8.3.2 B-Unit Copy of I-Unit BAR (B_CR_ISPMMADR_LO_0_3_0_PCI)—Offset 10h 2389
8.3.3 B-Unit Copy of I-Unit BAR (B_CR_ISPMMADR_HI_0_3_0_PCI)—Offset 14h . 2390
8.3.4 B-Unit Copy of Device 3 Control Register (B_CR_DEVICECTL_0_3_0_PCI)—Offset
78h................................................................................................... 2391

54 334818
 8.3.5 B-Unit Copy of PMCS for I-Unit Device 0/3/0 (B_CR_PMCS_0_3_0_PCI)—Offset
D4h...................................................................................................2392
8.4 Registers Summary ........................................................................................2393
8.4.1 B-Unit Copy of the I/O Decode Ranges Register for LPC (B_CR_IOD_LPC)—Offset
80h ...................................................................................................2393
8.4.2 B-Unit Copy of the I/O Enables Register for LPC (B_CR_IOE_LPC)—Offset 82h....
2395
8.4.3 B_LGIR1_LPC (B_CR_LGIR1_LPC)—Offset 84h ........................................2395
8.4.4 B_LGIR2_LPC (B_CR_LGIR2_LPC)—Offset 88h ........................................2396
8.4.5 B_LGIR3_LPC (B_CR_LGIR3_LPC)—Offset 8Ch ........................................2397
8.4.6 B_LGIR4_LPC (B_CR_LGIR4_LPC)—Offset 90h ........................................2398
8.4.7 B-Unit Copy of the LPC Generic Memory Range Register for LPC
(B_CR_LGMR_LPC)—Offset 98h.............................................................2399
8.4.8 B-Unit Copy of the BIOS Decode Enable Register for LPC (B_CR_BDE_LPC)—
Offset D8h .........................................................................................2399
8.5 Registers Summary ........................................................................................2401
8.5.1 B-Unit Copy of the TCO Base Address Register for Legacy SMBUS
(B_CR_TCOBASE_SMBUS)—Offset 50h...................................................2401
8.5.2 B-Unit Copy of the TCO Control Register for Legacy SMBUS
(B_CR_TCOCTL_SMBUS)—Offset 54h .....................................................2401
8.6 Registers Summary ........................................................................................2402
8.6.1 B-Unit Copy of the BIOS Decode Enable register for SPI (B_CR_BDE_SPI)—Offset
D8h...................................................................................................2402
8.7 Registers Summary ........................................................................................2403
8.7.1 B-Unit Copy of IOBAR MMIO INDEX (B_CR_INDEX_0_2_0_IOBAR)—Offset 0h ....
2404
8.8 Registers Summary ........................................................................................2404
8.8.1 B-Unit Shadow of Legacy VGA Decode GR and MSR Bits
(B_CR_VGADEC_0_2_0_VGABAR)—Offset 0h..........................................2404
8.9 Registers Summary ........................................................................................2405
8.9.1 B-Unit Copy of Default VTd BAR PMEN (B_CR_PMEN_REG_0_0_0_DEFVTDBAR)—
Offset 64h ..........................................................................................2406
8.9.2 B-Unit Copy of Default VTd BAR PLM Base Register
(B_CR_PLMBASE_REG_0_0_0_DEFVTDBAR)—Offset 68h ..........................2406
8.9.3 B-Unit Copy of Default VTd BAR PLM Limit Register
(B_CR_PLMLIMIT_REG_0_0_0_DEFVTDBAR)—Offset 6Ch .........................2407
8.9.4 B-Unit Copy of Default VTd BAR PHM Base Register
(B_CR_PHMBASE_REG_0_0_0_DEFVTDBAR)—Offset 70h .........................2408
8.9.5 B-Unit Copy of Default VTd BAR PHM Limit Register
(B_CR_PHMLIMIT_REG_0_0_0_DEFVTDBAR)—Offset 78h .........................2409
8.10 ...................................................................................................................2410
8.11 Registers Summary ........................................................................................2411
8.11.1 B-Unit Copy of the MCHBAR (B_CR_MCHBAR_LO_0_0_0_PCI)—Offset 48h..2411
8.11.2 B-Unit Copy of the MCHBAR (B_CR_MCHBAR_HI_0_0_0_PCI)—Offset 4Ch ..2412
8.11.3 B-Unit Shadow of GGC (B_CR_GGC_0_0_0_PCI)—Offset 50h ....................2413
8.11.4 B-Unit Shadow of the DEVEN Register (B_CR_DEVEN_0_0_0_PCI)—Offset 54h...
2415
8.11.5 B-Unit PCI Express Enhanced Configuration Range Base Address Low
(B_CR_PCIEXBAR_LO_0_0_0_PCI)—Offset 60h .......................................2416
8.11.6 B-Unit PCI Express Enhanced Configuration Range Base Address High
(B_CR_PCIEXBAR_HI_0_0_0_PCI)—Offset 64h .......................................2417
8.11.7 Top of Upper Usable DRAM Low (B_CR_TOUUD_LO_0_0_0_PCI)—Offset A8h .....
2418
8.11.8 Top of Upper Usable DRAM High (B_CR_TOUUD_HI_0_0_0_PCI)—Offset ACh.....
2418
8.11.9 Base of Graphics Stolen Memory (B_CR_BGSM_0_0_0_PCI)—Offset B4h ....2419

334818 55
 8.11.10B-Unit Copy of the TSEG Memory Base (B_CR_TSEGMB_0_0_0_PCI)—Offset B8h
2420
8.11.11Top of Lower Usable DRAM (B_CR_TOLUD_0_0_0_PCI)—Offset BCh .......... 2421
8.11.12Capability ID0 A (B_CR_CAPID0_A_0_0_0_PCI)—Offset E4h .................... 2422
8.11.13Capability ID0 B (B_CR_CAPID0_B_0_0_0_PCI)—Offset E8h .................... 2424
8.12 Registers Summary........................................................................................ 2427
8.12.1 B-Unit Copy of PCICMD for IGD (B_CR_PCICMD_0_2_0_PCI)—Offset 4h .... 2427
8.12.2 B-Unit Copy of GTTMMADR (B_CR_GTTMMADR_LO_0_2_0_PCI)—Offset 10h .....
2428
8.12.3 B-Unit Copy of GTTMMADR (B_CR_GTTMMADR_HI_0_2_0_PCI)—Offset 14h......
2429
8.12.4 B-Unit Copy of GMADR (B_CR_GMADR_LO_0_2_0_PCI)—Offset 18h.......... 2430
8.12.5 B-Unit Copy of GMADR (B_CR_GMADR_HI_0_2_0_PCI)—Offset 1Ch .......... 2431
8.12.6 B-Unit Copy of the IOBAR (B_CR_IOBAR_0_2_0_PCI)—Offset 20h ............ 2431
8.12.7 B-Unit Copy of Device 2 Control Register (B_CR_DEV2CTL_0_2_0_PCI)—Offset
58h................................................................................................... 2432
8.12.8 B-Unit Copy of MSAC (B_CR_MSAC_0_2_0_PCI)—Offset 62h .................... 2432
8.12.9 B-Unit Copy of Device 2 Control Register (B_CR_DEVICECTL_0_2_0_PCI)—Offset
78h................................................................................................... 2433
8.12.10B-Unit Copy of PMCS for IGD (B_CR_PMCS_0_2_0_PCI)—Offset D4h......... 2435
8.13 Registers Summary........................................................................................ 2437
8.13.1 PCICMD for I-Unit in Device 3 Mode (B_CR_PCICMD_0_3_0_PCI)—Offset 4h .....
2437
8.13.2 B-Unit Copy of I-Unit BAR (B_CR_ISPMMADR_LO_0_3_0_PCI)—Offset 10h 2438
8.13.3 B-Unit Copy of I-Unit BAR (B_CR_ISPMMADR_HI_0_3_0_PCI)—Offset 14h . 2438
8.13.4 B-Unit Copy of Device 3 Control Register (B_CR_DEVICECTL_0_3_0_PCI)—Offset
78h................................................................................................... 2439
8.13.5 B-Unit Copy of PMCS for I-Unit Device 0/3/0 (B_CR_PMCS_0_3_0_PCI)—Offset
D4h .................................................................................................. 2440
8.14 Registers Summary........................................................................................ 2443
8.14.1 B-Unit Copy of the I/O Decode Ranges Register for LPC (B_CR_IOD_LPC)—Offset
80h................................................................................................... 2443
8.14.2 B-Unit Copy of the I/O Enables Register for LPC (B_CR_IOE_LPC)—Offset 82h ...
2444
8.14.3 B_LGIR1_LPC (B_CR_LGIR1_LPC)—Offset 84h........................................ 2445
8.14.4 B_LGIR2_LPC (B_CR_LGIR2_LPC)—Offset 88h........................................ 2446
8.14.5 B_LGIR3_LPC (B_CR_LGIR3_LPC)—Offset 8Ch ....................................... 2447
8.14.6 B_LGIR4_LPC (B_CR_LGIR4_LPC)—Offset 90h........................................ 2448
8.14.7 B-Unit Copy of the LPC Generic Memory Range Register for LPC
(B_CR_LGMR_LPC)—Offset 98h ............................................................ 2448
8.14.8 B-Unit Copy of the BIOS Decode Enable Register for LPC (B_CR_BDE_LPC)—
Offset D8h ......................................................................................... 2449
8.15 Registers Summary........................................................................................ 2451
8.15.1 B-Unit Copy of the TCO Base Address Register for Legacy SMBUS
(B_CR_TCOBASE_SMBUS)—Offset 50h .................................................. 2451
8.15.2 B-Unit Copy of the TCO Control Register for Legacy SMBUS
(B_CR_TCOCTL_SMBUS)—Offset 54h .................................................... 2451
8.16 Registers Summary........................................................................................ 2453
8.16.1 B-Unit Copy of the BIOS Decode Enable register for SPI (B_CR_BDE_SPI)—Offset
D8h .................................................................................................. 2453
8.17 Registers Summary........................................................................................ 2455
8.17.1 B-Unit Copy of IOBAR MMIO INDEX (B_CR_INDEX_0_2_0_IOBAR)—Offset 0h ...
2455
8.18 Registers Summary........................................................................................ 2457
8.18.1 B-Unit Shadow of Legacy VGA Decode GR and MSR Bits
(B_CR_VGADEC_0_2_0_VGABAR)—Offset 0h ......................................... 2457

56 334818
 8.19 Registers Summary ........................................................................................2459
8.19.1 B-Unit Copy of Default VTd BAR PMEN (B_CR_PMEN_REG_0_0_0_DEFVTDBAR)—
Offset 64h ..........................................................................................2459
8.19.2 B-Unit Copy of Default VTd BAR PLM Base Register
(B_CR_PLMBASE_REG_0_0_0_DEFVTDBAR)—Offset 68h ..........................2460
8.19.3 B-Unit Copy of Default VTd BAR PLM Limit Register
(B_CR_PLMLIMIT_REG_0_0_0_DEFVTDBAR)—Offset 6Ch .........................2461
8.19.4 B-Unit Copy of Default VTd BAR PHM Base Register
(B_CR_PHMBASE_REG_0_0_0_DEFVTDBAR)—Offset 70h .........................2461
8.19.5 B-Unit Copy of Default VTd BAR PHM Limit Register
(B_CR_PHMLIMIT_REG_0_0_0_DEFVTDBAR)—Offset 78h .........................2462
9 C-Unit ...................................................................................................................2465
9.1 Registers Summary ........................................................................................2465
9.1.1 Device ID and Vendor ID Register (DEVICE_ID_VENDOR_ID_0_0_0_PCI)—Offset
0h .....................................................................................................2466
9.1.2 PCI Status and PCI Command Register (PCI_STATUS_COMMAND_0_0_0_PCI)—
Offset 4h............................................................................................2466
9.1.3 PCI Revision ID and PCI Class Code Register
(REVISION_ID_CLASS_CODE_0_0_0_PCI)—Offset 8h ..............................2467
9.1.4 Master Latency Timer and Header Type Register
(MASTER_LATENCY_TIME_0_0_0_PCI)—Offset Ch ...................................2468
9.1.5 PCI Subsystem Vendor ID and PCI Subsystem ID (SVID_SID_0_0_0_PCI)—Offset
2Ch ...................................................................................................2469
9.1.6 Capability Register Pointer (CAPPTR_0_0_0_PCI)—Offset 34h ...................2469
9.1.7 Memory Controller Hub Base Address Register (MCHBAR_LO_0_0_0_PCI)—Offset
48h ...................................................................................................2470
9.1.8 Memory Controller Hub Base Address Register (MCHBAR_HI_0_0_0_PCI)—Offset
4Ch ...................................................................................................2471
9.1.9 Graphics and Memory Controller Hub Graphics Control Register
(GGC_0_0_0_PCI)—Offset 50h .............................................................2471
9.1.10 Device Enable Register (DEVEN_0_0_0_PCI)—Offset 54h .........................2473
9.1.11 Protected Audio Video Path Control (PAVPC_0_0_0_PCI)—Offset 58h .........2474
9.1.12 PCI Express Enhanced Configuration Range Base Address Low
(PCIEXBAR_LO_0_0_0_PCI)—Offset 60h ................................................2476
9.1.13 PCI Express Enhanced Configuration Range Base Address High
(PCIEXBAR_HI_0_0_0_PCI)—Offset 64h.................................................2477
9.1.14 Top of Upper Usable DRAM Low (TOUUD_LO_0_0_0_PCI)—Offset A8h .......2477
9.1.15 Top of Upper Usable DRAM High (TOUUD_HI_0_0_0_PCI)—Offset ACh .......2478
9.1.16 Base of Data Stolen Memory (BDSM_0_0_0_PCI)—Offset B0h ...................2479
9.1.17 Base of Graphics Stolen Memory (BGSM_0_0_0_PCI)—Offset B4h .............2480
9.1.18 Top Segment Memory Base (TSEGMB_0_0_0_PCI)—Offset B8h .................2481
9.1.19 Top of Lower Usable DRAM (TOLUD_0_0_0_PCI)—Offset BCh....................2481
9.1.20 Scratchpad (SKPD_0_0_0_PCI)—Offset DCh ...........................................2482
9.1.21 Capability ID0 Capability Control (CAPID0_CAPCTRL0_0_0_0_PCI)—Offset E0h ..
2483
9.1.22 Capability ID0 A (CAPID0_A_0_0_0_PCI)—Offset E4h ..............................2483
9.1.23 Capability ID0 B (CAPID0_B_0_0_0_PCI)—Offset E8h ..............................2485
9.1.24 Design and Engineering Backup Register 0 (DEBUP0_0_0_0_PCI)—Offset F8h ....
2486
9.1.25 Design and Engineering Backup Register 1 (DEBUP1_0_0_0_PCI)—Offset FCh....
2487
9.1.26 I/O Buffer Control (IOBCTL)—Offset 061Ch .............................................2487
9.1.27 Power Management Control And Status (PCS)—Offset 0054h ....................2489
9.1.28 LTRC_D013C_PCE—Offset 1048h ..........................................................2491
9.1.29 PID_PC—Offset 0050h .........................................................................2492
9.2 Registers Summary ........................................................................................2493

334818 57
 9.2.1 Thermal Management Base Address Register (TMBAR_LO_0_0_1_PCI)—Offset
10h................................................................................................... 2493
9.2.2 Thermal Management Base Address Register (TMBAR_HI_0_0_1_PCI)—Offset
14h................................................................................................... 2494
9.3 ................................................................................................................... 2495
9.4 Registers Summary........................................................................................ 2497
9.4.1 Device ID and Vendor ID Register (DEVICE_ID_VENDOR_ID_0_0_0_PCI)—Offset
0h .................................................................................................... 2498
9.4.2 PCI Status and PCI Command Register (PCI_STATUS_COMMAND_0_0_0_PCI)—
Offset 4h ........................................................................................... 2498
9.4.3 PCI Revision ID and PCI Class Code Register
(REVISION_ID_CLASS_CODE_0_0_0_PCI)—Offset 8h ............................. 2499
9.4.4 Master Latency Timer and Header Type Register
(MASTER_LATENCY_TIME_0_0_0_PCI)—Offset Ch .................................. 2500
9.4.5 PCI Subsystem Vendor ID and PCI Subsystem ID (SVID_SID_0_0_0_PCI)—Offset
2Ch .................................................................................................. 2501
9.4.6 Capability Register Pointer (CAPPTR_0_0_0_PCI)—Offset 34h ................... 2501
9.4.7 Memory Controller Hub Base Address Register (MCHBAR_LO_0_0_0_PCI)—Offset
48h................................................................................................... 2502
9.4.8 Memory Controller Hub Base Address Register (MCHBAR_HI_0_0_0_PCI)—Offset
4Ch .................................................................................................. 2503
9.4.9 Graphics and Memory Controller Hub Graphics Control Register
(GGC_0_0_0_PCI)—Offset 50h ............................................................. 2503
9.4.10 Device Enable Register (DEVEN_0_0_0_PCI)—Offset 54h ......................... 2505
9.4.11 Protected Audio Video Path Control (PAVPC_0_0_0_PCI)—Offset 58h......... 2506
9.4.12 PCI Express Enhanced Configuration Range Base Address Low
(PCIEXBAR_LO_0_0_0_PCI)—Offset 60h................................................ 2508
9.4.13 PCI Express Enhanced Configuration Range Base Address High
(PCIEXBAR_HI_0_0_0_PCI)—Offset 64h ................................................ 2509
9.4.14 Top of Upper Usable DRAM Low (TOUUD_LO_0_0_0_PCI)—Offset A8h ....... 2509
9.4.15 Top of Upper Usable DRAM High (TOUUD_HI_0_0_0_PCI)—Offset ACh ...... 2510
9.4.16 Base of Data Stolen Memory (BDSM_0_0_0_PCI)—Offset B0h .................. 2511
9.4.17 Base of Graphics Stolen Memory (BGSM_0_0_0_PCI)—Offset B4h ............. 2512
9.4.18 Top Segment Memory Base (TSEGMB_0_0_0_PCI)—Offset B8h ................ 2513
9.4.19 Top of Lower Usable DRAM (TOLUD_0_0_0_PCI)—Offset BCh ................... 2513
9.4.20 Scratchpad (SKPD_0_0_0_PCI)—Offset DCh........................................... 2514
9.4.21 Capability ID0 Capability Control (CAPID0_CAPCTRL0_0_0_0_PCI)—Offset E0h..
2515
9.4.22 Capability ID0 A (CAPID0_A_0_0_0_PCI)—Offset E4h.............................. 2515
9.4.23 Capability ID0 B (CAPID0_B_0_0_0_PCI)—Offset E8h.............................. 2517
9.4.24 Design and Engineering Backup Register 0 (DEBUP0_0_0_0_PCI)—Offset F8h ...
2518
9.4.25 Design and Engineering Backup Register 1 (DEBUP1_0_0_0_PCI)—Offset FCh ...
2519
9.4.26 I/O Buffer Control (IOBCTL)—Offset 061Ch ............................................ 2519
9.4.27 Power Management Control And Status (PCS)—Offset 0054h .................... 2521
9.4.28 LTRC_D013C_PCE—Offset 1048h .......................................................... 2523
9.4.29 PID_PC—Offset 0050h ......................................................................... 2524
9.5 Registers Summary........................................................................................ 2527
9.5.1 Thermal Management Base Address Register (TMBAR_LO_0_0_1_PCI)—Offset
10h................................................................................................... 2527
9.5.2 Thermal Management Base Address Register (TMBAR_HI_0_0_1_PCI)—Offset
14h................................................................................................... 2528
10 Imaging Control................................................................................................... 2529
10.1 Registers Summary........................................................................................ 2529
10.1.1 (VID_DID)—Offset 0h......................................................................... 2529

58 334818
 10.1.2 (PCICMD_PCISTS)—Offset 4h ..............................................................2530
10.1.3 (RID_CC)—Offset 8h...........................................................................2531
10.1.4 (CLS_MLT_HT_BIST)—Offset Ch...........................................................2532
10.1.5 (ISPMMADR_LOW)—Offset 10h ............................................................2533
10.1.6 (ISPMMADR_HIGH)—Offset 14h ...........................................................2534
10.1.7 (SVID_SID)—Offset 2Ch......................................................................2534
10.1.8 (CAPPOINT)—Offset 34h .....................................................................2535
10.1.9 (INTR)—Offset 3Ch.............................................................................2535
10.1.10 (PCIECAPHDR_PCIECAP)—Offset 70h ....................................................2536
10.1.11 (DEVICECAP)—Offset 74h....................................................................2537
10.1.12 (DEVICECTL_DEVICESTS)—Offset 78h ..................................................2538
10.1.13 (MSI_CAPID)—Offset ACh....................................................................2539
10.1.14 (MSI_ADDRESS_LO)—Offset B0h .........................................................2540
10.1.15 (MSI_ADDRESS_HI)—Offset B4h ..........................................................2540
10.1.16 (MSI_DATA)—Offset B8h .....................................................................2541
10.1.17 (PMCAP)—Offset D0h ..........................................................................2542
10.1.18(PMCS)—Offset D4h ............................................................................2542
10.1.19(SENSOR_FREQ_CTL)—Offset 16Ch .......................................................2543
10.1.20(SENSOR_CLK_CTL)—Offset 170h .........................................................2544
10.1.21NFC_CFG ...........................................................................................2545
10.1.22IUNIT_CFG .........................................................................................2546
10.2 ...................................................................................................................2547
10.3 Registers Summary ........................................................................................2549
10.3.1 (VID_DID)—Offset 0h .........................................................................2549
10.3.2 (PCICMD_PCISTS)—Offset 4h ..............................................................2550
10.3.3 (RID_CC)—Offset 8h...........................................................................2551
10.3.4 (CLS_MLT_HT_BIST)—Offset Ch...........................................................2552
10.3.5 (ISPMMADR_LOW)—Offset 10h ............................................................2553
10.3.6 (ISPMMADR_HIGH)—Offset 14h ...........................................................2554
10.3.7 (SVID_SID)—Offset 2Ch......................................................................2554
10.3.8 (CAPPOINT)—Offset 34h .....................................................................2555
10.3.9 (INTR)—Offset 3Ch.............................................................................2555
10.3.10 (PCIECAPHDR_PCIECAP)—Offset 70h ....................................................2556
10.3.11 (DEVICECAP)—Offset 74h....................................................................2557
10.3.12 (DEVICECTL_DEVICESTS)—Offset 78h ..................................................2558
10.3.13 (MSI_CAPID)—Offset ACh....................................................................2559
10.3.14 (MSI_ADDRESS_LO)—Offset B0h .........................................................2560
10.3.15 (MSI_ADDRESS_HI)—Offset B4h ..........................................................2560
10.3.16 (MSI_DATA)—Offset B8h .....................................................................2561
10.3.17 (PMCAP)—Offset D0h ..........................................................................2562
10.3.18(PMCS)—Offset D4h ............................................................................2562
10.3.19(SENSOR_FREQ_CTL)—Offset 16Ch .......................................................2563
10.3.20(SENSOR_CLK_CTL)—Offset 170h .........................................................2564
10.3.21NFC_CFG ...........................................................................................2565
10.3.22IUNIT_CFG .........................................................................................2566
11 Audio Controller ...................................................................................................2569
11.1 Registers Summary ........................................................................................2569
11.1.1 Vendor Identification (VID)—Offset 0h ...................................................2570
11.1.2 Device ID (DID)—Offset 2h...................................................................2571
11.1.3 Command (CMD)—Offset 4h .................................................................2571
11.1.4 Status (STS)—Offset 6h .......................................................................2572
11.1.5 Revision Identification (RID)—Offset 8h..................................................2573
11.1.6 Programming Interface (PI)—Offset 9h...................................................2574
11.1.7 Sub Class Code (SCC)—Offset Ah ..........................................................2574

334818 59
 11.1.8 Base Class Code (BCC)—Offset Bh ........................................................ 2575
11.1.9 Cache Line Size (CLS)—Offset Ch.......................................................... 2575
11.1.10Latency Timer (LT)—Offset Dh.............................................................. 2576
11.1.11Header Type (HTYPE)—Offset Eh........................................................... 2576
11.1.12Built-in Self Test (BIST)—Offset Fh ....................................................... 2577
11.1.13Intel HD Audio Base Lower Address (HDALBA)—Offset 10h ....................... 2577
11.1.14Intel HD Audio Base Upper Address (HDAUBA)—Offset 14h ...................... 2578
11.1.15Shadowed PCI Configuration Lower Base Address (SPCLBA)—Offset 18h .... 2578
11.1.16Shadowed PCI Configuration Upper Base Address (SPCUBA)—Offset 1Ch.... 2579
11.1.17Audio DSP Lower Base Address (ADSPLBA)—Offset 20h ........................... 2579
11.1.18Audio DSP Upper Base Address (ADSPUBA)—Offset 24h........................... 2580
11.1.19Subsystem Vendor ID (SVID)—Offset 2Ch.............................................. 2581
11.1.20Subsystem ID (SID)—Offset 2Eh........................................................... 2581
11.1.21Capability Pointer (CAPPTR)—Offset 34h ................................................ 2582
11.1.22Interrupt Line (INTLN)—Offset 3Ch ....................................................... 2582
11.1.23Interrupt Pin (INTPN)—Offset 3Dh......................................................... 2583
11.1.24Test Mode 1 register (TM1)—Offset 43h ................................................. 2583
11.1.25PCI Power Management Capability ID (PID)—Offset 50h .......................... 2584
11.1.26MSI Capability ID (MID)—Offset 60h ..................................................... 2585
11.1.27MSI Message Control (MMC)—Offset 62h ............................................... 2585
11.1.28MSI Message Lower Address (MMLA)—Offset 64h.................................... 2586
11.1.29MSI Message Upper Address (MMUA)—Offset 68h ................................... 2586
11.1.30MSI Message Data (MMD)—Offset 6Ch................................................... 2587
11.1.31PCI Express Capability ID (PXID)—Offset 70h ......................................... 2587
11.1.32PCI Express Capabilities (PXC)—Offset 72h ............................................ 2588
11.1.33Device Capabilities (DEVCAP)—Offset 74h .............................................. 2588
11.1.34Device Control (DEVC)—Offset 78h ....................................................... 2589
11.1.35Device Status (DEVS)—Offset 7Ah ........................................................ 2591
11.1.36Vendor Specific Capability Identifiers (VSCID)—Offset 80h ....................... 2591
11.1.37Vendor Specific Extended Capability (VSECID)—Offset 84h....................... 2592
11.1.38Device Idle Pointer (DEVIDLEPTR)—Offset 8Ch ....................................... 2593
11.1.39Device Idle Power On Latency (DEVIDLEPOL)—Offset 90h ........................ 2593
11.1.40Virtual Channel Enhanced Capability Header (VCCAP)—Offset 100h ........... 2594
11.1.41Port VC Capability Register 1 (PVCCAP1)—Offset 104h ............................. 2595
11.1.42Port VC Capability Register 2 (PVCCAP2)—Offset 108h ............................. 2596
11.1.43Port VC Control Register (PVCCTL)—Offset 10Ch ..................................... 2596
11.1.44Port VC Status Register (PVCSTS)—Offset 10Eh ...................................... 2597
11.1.45VC0 Resource Capability Register (VC0CAP)—Offset 110h ........................ 2597
11.1.46VC0 Resource Control Register (VC0CTL)—Offset 114h ............................ 2598
11.1.47VC0 Resource Status Register (VC0STS)—Offset 11Ah ............................. 2599
11.1.48VCi Resource Capability Register (VCiCAP)—Offset 11Ch .......................... 2600
11.1.49VCi Resource Control Register (VCiCTL)—Offset 120h .............................. 2600
11.1.50VCi Resource Status Register (VCiSTS)—Offset 126h ............................... 2601
11.1.51Root Complex Link Declaration Enhanced (RCCAP)—Offset 130h ............... 2602
11.1.52Element Self Description (ESD)—Offset 134h.......................................... 2602
11.1.53Link 1 Description (L1DESC)—Offset 140h.............................................. 2603
11.1.54Link 1 Lower Address (L1LADD)—Offset 148h ......................................... 2604
11.1.55Link 1 Upper Address (L1UADD)—Offset 14Ch ........................................ 2604
11.1.56I/O Buffer Control (IOBCTL)—Offset 061Ch ............................................ 2605
11.1.57Power Management Control And Status (PCS)—Offset 0054h .................... 2606
11.1.58LTRC_D013C_PCE—Offset 1048h .......................................................... 2608
11.1.59PID_PC—Offset 0050h ......................................................................... 2609
11.2 Registers Summary........................................................................................ 2610
11.2.1 Global Capabilities (GCAP)—Offset 0h .................................................... 2624
11.2.2 Minor Version (VMIN)—Offset 2h........................................................... 2624

60 334818
 11.2.3 Major Version (VMAJ)—Offset 3h ...........................................................2625
11.2.4 Output Payload Capability (OUTPAY)—Offset 4h.......................................2625
11.2.5 Input Payload Capability (INPAY)—Offset 6h ...........................................2626
11.2.6 Global Control (GCTL)—Offset 8h...........................................................2627
11.2.7 Wake Enable (WAKEEN)—Offset Ch .......................................................2629
11.2.8 Wake Status (WAKESTS)—Offset Eh ......................................................2629
11.2.9 Global Status (GSTS)—Offset 10h..........................................................2630
11.2.10Global Capabilities 2 (GCAP2)—Offset 12h ..............................................2630
11.2.11Linked List Capabilities Header (LLCH)—Offset 14h ..................................2631
11.2.12Output Stream Payload Capability (OUTSTRMPAY)—Offset 18h ..................2632
11.2.13Input Stream Payload Capability (INSTRMPAY)—Offset 1Ah.......................2632
11.2.14Interrupt Control (INTCTL)—Offset 20h ..................................................2633
11.2.15Interrupt Status (INTSTS)—Offset 24h ...................................................2634
11.2.16Wall Clock Counter (WALCLK)—Offset 30h ..............................................2635
11.2.17Stream Synchronization (SSYNC)—Offset 38h .........................................2636
11.2.18CORB Lower Base Address (CORBLBASE)—Offset 40h ..............................2637
11.2.19CORB Upper Base Address (CORBUBASE)—Offset 44h ..............................2637
11.2.20CORB Write Pointer (CORBWP)—Offset 48h.............................................2638
11.2.21CORB Read Pointer (CORBRP)—Offset 4Ah..............................................2638
11.2.22CORB Control (CORBCTL)—Offset 4Ch....................................................2639
11.2.23CORB Status (CORBSTS)—Offset 4Dh ....................................................2640
11.2.24CORB Size (CORBSIZE)—Offset 4Eh.......................................................2640
11.2.25RIRB Lower Base Address (RIRBLBASE)—Offset 50h ................................2641
11.2.26RIRB Upper Base Address (RIRBUBASE)—Offset 54h ................................2642
11.2.27RIRB Write Pointer (RIRBWP)—Offset 58h...............................................2642
11.2.28Response Interrupt Count (RINTCNT)—Offset 5Ah ...................................2643
11.2.29RIRB Control (RIRBCTL)—Offset 5Ch......................................................2643
11.2.30RIRB Status (RIRBSTS)—Offset 5Dh ......................................................2644
11.2.31RIRB Size (RIRBSIZE)—Offset 5Eh.........................................................2645
11.2.32Immediate Command Status (ICS)—Offset 68h .......................................2645
11.2.33DMA Position Lower Base Address (DPLBASE)—Offset 70h ........................2646
11.2.34DMA Position Upper Base Address (DPUBASE)—Offset 74h........................2647
11.2.35Input/Output Stream Descriptor x Control (ISD0CTL)—Offset 80h..............2648
11.2.36Input/Output Stream Descriptor x Status (ISD0STS)—Offset 83h ..............2649
11.2.37Input/Output Stream Descriptor x Link Position in Buffer (ISD0LPIB)—Offset 84h
2651
11.2.38Input/Output Stream Descriptor x Cyclic Buffer Length (ISD0CBL)—Offset 88h ...
2651
11.2.39Input/Output Stream Descriptor x Last Valid Index (ISD0LVI)—Offset 8Ch ..2652
11.2.40Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW)—Offset
8Eh ...................................................................................................2653
11.2.41Input/Output Stream Descriptor x FIFO Size (ISD0FIFOS)—Offset 90h .......2653
11.2.42Input/Output Stream Descriptor x Format (ISD0FMT)—Offset 92h .............2654
11.2.43Input/Output Stream Descriptor x FIFO Limit (ISD0FIFOL)—Offset 94h.......2656
11.2.44Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD0BDLPLBA)—Offset 98h .....................................................2656
11.2.45Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD0BDLPUBA)—Offset 9Ch.....................................................2657
11.2.46Input/Output Stream Descriptor x Control (ISD1CTL)—Offset A0h..............2657
11.2.47Input/Output Stream Descriptor x Status (ISD1STS)—Offset A3h ..............2659
11.2.48Input/Output Stream Descriptor x Link Position in Buffer (ISD1LPIB)—Offset A4h
2661
11.2.49Input/Output Stream Descriptor x Cyclic Buffer Length (ISD1CBL)—Offset A8h...
2661
11.2.50Input/Output Stream Descriptor x Last Valid Index (ISD1LVI)—Offset ACh..2662

334818 61
 11.2.51Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD1FIFOW)—Offset
AEh .................................................................................................. 2663
11.2.52Input/Output Stream Descriptor x FIFO Size (ISD1FIFOS)—Offset B0h....... 2663
11.2.53Input/Output Stream Descriptor x Format (ISD1FMT)—Offset B2h............. 2664
11.2.54Input/Output Stream Descriptor x FIFO Limit (ISD1FIFOL)—Offset B4h ...... 2666
11.2.55Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD1BDLPLBA)—Offset B8h..................................................... 2666
11.2.56Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD1BDLPUBA)—Offset BCh .................................................... 2667
11.2.57Input/Output Stream Descriptor x Control (ISD2CTL)—Offset C0h ............. 2667
11.2.58Input/Output Stream Descriptor x Status (ISD2STS)—Offset C3h.............. 2669
11.2.59Input/Output Stream Descriptor x Link Position in Buffer (ISD2LPIB)—Offset C4h
2671
11.2.60Input/Output Stream Descriptor x Cyclic Buffer Length (ISD2CBL)—Offset C8h ..
2671
11.2.61Input/Output Stream Descriptor x Last Valid Index (ISD2LVI)—Offset CCh . 2672
11.2.62Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD2FIFOW)—Offset
CEh .................................................................................................. 2673
11.2.63Input/Output Stream Descriptor x FIFO Size (ISD2FIFOS)—Offset D0h ...... 2673
11.2.64Input/Output Stream Descriptor x Format (ISD2FMT)—Offset D2h ............ 2674
11.2.65Input/Output Stream Descriptor x FIFO Limit (ISD2FIFOL)—Offset D4h...... 2676
11.2.66Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD2BDLPLBA)—Offset D8h .................................................... 2676
11.2.67Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD2BDLPUBA)—Offset DCh.................................................... 2677
11.2.68Input/Output Stream Descriptor x Control (ISD3CTL)—Offset E0h ............. 2677
11.2.69Input/Output Stream Descriptor x Status (ISD3STS)—Offset E3h .............. 2679
11.2.70Input/Output Stream Descriptor x Link Position in Buffer (ISD3LPIB)—Offset E4h
2681
11.2.71Input/Output Stream Descriptor x Cyclic Buffer Length (ISD3CBL)—Offset E8h ..
2681
11.2.72Input/Output Stream Descriptor x Last Valid Index (ISD3LVI)—Offset ECh . 2682
11.2.73Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD3FIFOW)—Offset
EEh................................................................................................... 2683
11.2.74Input/Output Stream Descriptor x FIFO Size (ISD3FIFOS)—Offset F0h ....... 2683
11.2.75Input/Output Stream Descriptor x Format (ISD3FMT)—Offset F2h ............. 2684
11.2.76Input/Output Stream Descriptor x FIFO Limit (ISD3FIFOL)—Offset F4h ...... 2686
11.2.77Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD3BDLPLBA)—Offset F8h ..................................................... 2686
11.2.78Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD3BDLPUBA)—Offset FCh .................................................... 2687
11.2.79Input/Output Stream Descriptor x Control (ISD4CTL)—Offset 100h ........... 2687
11.2.80Input/Output Stream Descriptor x Status (ISD4STS)—Offset 103h ............ 2689
11.2.81Input/Output Stream Descriptor x Link Position in Buffer (ISD4LPIB)—Offset 104h
2691
11.2.82Input/Output Stream Descriptor x Cyclic Buffer Length (ISD4CBL)—Offset 108h.
2691
11.2.83Input/Output Stream Descriptor x Last Valid Index (ISD4LVI)—Offset 10Ch 2692
11.2.84Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD4FIFOW)—Offset
10Eh ................................................................................................. 2693
11.2.85Input/Output Stream Descriptor x FIFO Size (ISD4FIFOS)—Offset 110h ..... 2693
11.2.86Input/Output Stream Descriptor x Format (ISD4FMT)—Offset 112h ........... 2694
11.2.87Input/Output Stream Descriptor x FIFO Limit (ISD4FIFOL)—Offset 114h .... 2696
11.2.88Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD4BDLPLBA)—Offset 118h ................................................... 2696

62 334818
 11.2.89Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD4BDLPUBA)—Offset 11Ch ...................................................2697
11.2.90Input/Output Stream Descriptor x Control (ISD5CTL)—Offset 120h ............2697
11.2.91Input/Output Stream Descriptor x Status (ISD5STS)—Offset 123h.............2699
11.2.92Input/Output Stream Descriptor x Link Position in Buffer (ISD5LPIB)—Offset 124h
2701
11.2.93Input/Output Stream Descriptor x Cyclic Buffer Length (ISD5CBL)—Offset 128h .
2701
11.2.94Input/Output Stream Descriptor x Last Valid Index (ISD5LVI)—Offset 12Ch 2702
11.2.95Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD5FIFOW)—Offset
12Eh .................................................................................................2703
11.2.96Input/Output Stream Descriptor x FIFO Size (ISD5FIFOS)—Offset 130h......2703
11.2.97Input/Output Stream Descriptor x Format (ISD5FMT)—Offset 132h............2704
11.2.98Input/Output Stream Descriptor x FIFO Limit (ISD5FIFOL)—Offset 134h .....2706
11.2.99Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD5BDLPLBA)—Offset 138h....................................................2706
11.2.100Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD5BDLPUBA)—Offset 13Ch ...................................................2707
11.2.101Input/Output Stream Descriptor x Control (ISD6CTL)—Offset 140h ..........2707
11.2.102Input/Output Stream Descriptor x Status (ISD6STS)—Offset 143h ...........2709
11.2.103Input/Output Stream Descriptor x Link Position in Buffer (ISD6LPIB)—Offset
144h .................................................................................................2711
11.2.104Input/Output Stream Descriptor x Cyclic Buffer Length (ISD6CBL)—Offset 148h
2711
11.2.105Input/Output Stream Descriptor x Last Valid Index (ISD6LVI)—Offset 14Ch......
2712
11.2.106Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD6FIFOW)—
Offset 14Eh ........................................................................................2713
11.2.107Input/Output Stream Descriptor x FIFO Size (ISD6FIFOS)—Offset 150h ....2713
11.2.108Input/Output Stream Descriptor x Format (ISD6FMT)—Offset 152h ..........2714
11.2.109Input/Output Stream Descriptor x FIFO Limit (ISD6FIFOL)—Offset 154h ...2716
11.2.110Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD6BDLPLBA)—Offset 158h....................................................2716
11.2.111Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD6BDLPUBA)—Offset 15Ch ...................................................2717
11.2.112Input/Output Stream Descriptor x Control (OSD0CTL)—Offset 160h .........2717
11.2.113Input/Output Stream Descriptor x Status (OSD0STS)—Offset 163h ..........2719
11.2.114Input/Output Stream Descriptor x Link Position in Buffer (OSD0LPIB)—Offset
164h .................................................................................................2721
11.2.115Input/Output Stream Descriptor x Cyclic Buffer Length (OSD0CBL)—Offset 168h
2721
11.2.116Input/Output Stream Descriptor x Last Valid Index (OSD0LVI)—Offset 16Ch.....
2722
11.2.117Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD0FIFOW)—
Offset 16Eh ........................................................................................2723
11.2.118Input/Output Stream Descriptor x FIFO Size (OSD0FIFOS)—Offset 170h ...2723
11.2.119Input/Output Stream Descriptor x Format (OSD0FMT)—Offset 172h .........2724
11.2.120Input/Output Stream Descriptor x FIFO Limit (OSD0FIFOL)—Offset 174h ..2726
11.2.121Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD0BDLPLBA)—Offset 178h...................................................2726
11.2.122Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD0BDLPUBA)—Offset 17Ch ..................................................2727
11.2.123Input/Output Stream Descriptor x Control (OSD1CTL)—Offset 180h .........2728
11.2.124Input/Output Stream Descriptor x Status (OSD1STS)—Offset 183h ..........2729
11.2.125Input/Output Stream Descriptor x Link Position in Buffer (OSD1LPIB)—Offset
184h .................................................................................................2731

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 11.2.126Input/Output Stream Descriptor x Cyclic Buffer Length (OSD1CBL)—Offset 188h
2731
11.2.127Input/Output Stream Descriptor x Last Valid Index (OSD1LVI)—Offset 18Ch ....
2732
11.2.128Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD1FIFOW)—
Offset 18Eh........................................................................................ 2733
11.2.129Input/Output Stream Descriptor x FIFO Size (OSD1FIFOS)—Offset 190h... 2733
11.2.130Input/Output Stream Descriptor x Format (OSD1FMT)—Offset 192h......... 2734
11.2.131Input/Output Stream Descriptor x FIFO Limit (OSD1FIFOL)—Offset 194h .. 2736
11.2.132Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD1BDLPLBA)—Offset 198h .................................................. 2736
11.2.133Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD1BDLPUBA)—Offset 19Ch ................................................. 2737
11.2.134Input/Output Stream Descriptor x Control (OSD2CTL)—Offset 1A0h......... 2738
11.2.135Input/Output Stream Descriptor x Status (OSD2STS)—Offset 1A3h.......... 2739
11.2.136Input/Output Stream Descriptor x Link Position in Buffer (OSD2LPIB)—Offset
1A4h................................................................................................. 2741
11.2.137Input/Output Stream Descriptor x Cyclic Buffer Length (OSD2CBL)—Offset 1A8h
2741
11.2.138Input/Output Stream Descriptor x Last Valid Index (OSD2LVI)—Offset 1ACh ....
2742
11.2.139Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD2FIFOW)—
Offset 1AEh ....................................................................................... 2743
11.2.140Input/Output Stream Descriptor x FIFO Size (OSD2FIFOS)—Offset 1B0h .. 2743
11.2.141Input/Output Stream Descriptor x Format (OSD2FMT)—Offset 1B2h ........ 2744
11.2.142Input/Output Stream Descriptor x FIFO Limit (OSD2FIFOL)—Offset 1B4h.. 2746
11.2.143Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD2BDLPLBA)—Offset 1B8h .................................................. 2746
11.2.144Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD2BDLPUBA)—Offset 1BCh ................................................. 2747
11.2.145Input/Output Stream Descriptor x Control (OSD3CTL)—Offset 1C0h......... 2748
11.2.146Input/Output Stream Descriptor x Status (OSD3STS)—Offset 1C3h.......... 2749
11.2.147Input/Output Stream Descriptor x Link Position in Buffer (OSD3LPIB)—Offset
1C4h................................................................................................. 2751
11.2.148Input/Output Stream Descriptor x Cyclic Buffer Length (OSD3CBL)—Offset 1C8h
2751
11.2.149Input/Output Stream Descriptor x Last Valid Index (OSD3LVI)—Offset 1CCh ....
2752
11.2.150Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD3FIFOW)—
Offset 1CEh ....................................................................................... 2753
11.2.151Input/Output Stream Descriptor x FIFO Size (OSD3FIFOS)—Offset 1D0h .. 2753
11.2.152Input/Output Stream Descriptor x Format (OSD3FMT)—Offset 1D2h ........ 2754
11.2.153Input/Output Stream Descriptor x FIFO Limit (OSD3FIFOL)—Offset 1D4h . 2756
11.2.154Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD3BDLPLBA)—Offset 1D8h.................................................. 2756
11.2.155Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD3BDLPUBA)—Offset 1DCh ................................................. 2757
11.2.156Input/Output Stream Descriptor x Control (OSD4CTL)—Offset 1E0h ......... 2758
11.2.157Input/Output Stream Descriptor x Status (OSD4STS)—Offset 1E3h.......... 2759
11.2.158Input/Output Stream Descriptor x Link Position in Buffer (OSD4LPIB)—Offset
1E4h ................................................................................................. 2761
11.2.159Input/Output Stream Descriptor x Cyclic Buffer Length (OSD4CBL)—Offset 1E8h
2761
11.2.160Input/Output Stream Descriptor x Last Valid Index (OSD4LVI)—Offset 1ECh ....
2762
11.2.161Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD4FIFOW)—
Offset 1EEh........................................................................................ 2763

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 11.2.162Input/Output Stream Descriptor x FIFO Size (OSD4FIFOS)—Offset 1F0h ...2763
11.2.163Input/Output Stream Descriptor x Format (OSD4FMT)—Offset 1F2h .........2764
11.2.164Input/Output Stream Descriptor x FIFO Limit (OSD4FIFOL)—Offset 1F4h...2766
11.2.165Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD4BDLPLBA)—Offset 1F8h...................................................2766
11.2.166Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD4BDLPUBA)—Offset 1FCh ..................................................2767
11.2.167Input/Output Stream Descriptor x Control (OSD5CTL)—Offset 200h .........2767
11.2.168Input/Output Stream Descriptor x Status (OSD5STS)—Offset 203h ..........2769
11.2.169Input/Output Stream Descriptor x Link Position in Buffer (OSD5LPIB)—Offset
204h .................................................................................................2771
11.2.170Input/Output Stream Descriptor x Cyclic Buffer Length (OSD5CBL)—Offset 208h
2771
11.2.171Input/Output Stream Descriptor x Last Valid Index (OSD5LVI)—Offset 20Ch.....
2772
11.2.172Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD5FIFOW)—
Offset 20Eh ........................................................................................2773
11.2.173Input/Output Stream Descriptor x FIFO Size (OSD5FIFOS)—Offset 210h ...2773
11.2.174Input/Output Stream Descriptor x Format (OSD5FMT)—Offset 212h .........2774
11.2.175Input/Output Stream Descriptor x FIFO Limit (OSD5FIFOL)—Offset 214h ..2776
11.2.176Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD5BDLPLBA)—Offset 218h...................................................2776
11.2.177Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD5BDLPUBA)—Offset 21Ch ..................................................2777
11.2.178Global Time Synchronization Capability Header (GTSCH)—Offset 500h ......2778
11.2.179Global Time Synchronization Controller Adjust Control (GTSCTLAC)—Offset 50Ch
2778
11.2.180Global Time Synchronization Capture Control (GTSCC0)—Offset 520h .......2779
11.2.181Wall Frame Counter Captured (WALFCC0)—Offset 524h ..........................2780
11.2.182Time Stamp Counter Captured Lower (TSCCL0)—Offset 528h ..................2781
11.2.183Time Stamp Counter Captured Upper (TSCCU0)—Offset 52Ch..................2781
11.2.184Linear Link Position Frame Offset Captured (LLPFOC0)—Offset 534h .........2782
11.2.185Linear Link Position Captured Lower (LLPCL0)—Offset 538h .....................2782
11.2.186Linear Link Position Captured Upper (LLPCU0)—Offset 53Ch ....................2783
11.2.187Global Time Synchronization Capture Control (GTSCC1)—Offset 540h .......2783
11.2.188Wall Frame Counter Captured (WALFCC1)—Offset 544h ..........................2784
11.2.189Time Stamp Counter Captured Lower (TSCCL1)—Offset 548h ..................2785
11.2.190Time Stamp Counter Captured Upper (TSCCU1)—Offset 54Ch..................2785
11.2.191Linear Link Position Frame Offset Captured (LLPFOC1)—Offset 554h .........2786
11.2.192Linear Link Position Captured Lower (LLPCL1)—Offset 558h .....................2786
11.2.193Linear Link Position Captured Upper (LLPCU1)—Offset 55Ch ....................2787
11.2.194Software Position Based FIFO Capability Header (SPBFCH)—Offset 700h ...2787
11.2.195Software Position Based FIFO Control (SPBFCTL)—Offset 704h.................2788
11.2.196Input/Output Stream Descriptor x Software Position in Buffer (ISD0SPIB)—
Offset 708h ........................................................................................2789
11.2.197Input/Output Stream Descriptor x Max FIFO Size (ISD0MAXFIFOS)—Offset 70Ch
2789
11.2.198Input/Output Stream Descriptor x Software Position in Buffer (ISD1SPIB)—
Offset 710h ........................................................................................2790
11.2.199Input/Output Stream Descriptor x Max FIFO Size (ISD1MAXFIFOS)—Offset 714h
2790
11.2.200Input/Output Stream Descriptor x Software Position in Buffer (ISD2SPIB)—
Offset 718h ........................................................................................2791
11.2.201Input/Output Stream Descriptor x Max FIFO Size (ISD2MAXFIFOS)—Offset 71Ch
2792

334818 65
 11.2.202Input/Output Stream Descriptor x Software Position in Buffer (ISD3SPIB)—
Offset 720h........................................................................................ 2792
11.2.203Input/Output Stream Descriptor x Max FIFO Size (ISD3MAXFIFOS)—Offset 724h
2793
11.2.204Input/Output Stream Descriptor x Software Position in Buffer (ISD4SPIB)—
Offset 728h........................................................................................ 2793
11.2.205Input/Output Stream Descriptor x Max FIFO Size (ISD4MAXFIFOS)—Offset 72Ch
2794
11.2.206Input/Output Stream Descriptor x Software Position in Buffer (ISD5SPIB)—
Offset 730h........................................................................................ 2795
11.2.207Input/Output Stream Descriptor x Max FIFO Size (ISD5MAXFIFOS)—Offset 734h
2795
11.2.208Input/Output Stream Descriptor x Software Position in Buffer (ISD6SPIB)—
Offset 738h........................................................................................ 2796
11.2.209Input/Output Stream Descriptor x Max FIFO Size (ISD6MAXFIFOS)—Offset 73Ch
2796
11.2.210Input/Output Stream Descriptor x Software Position in Buffer (OSD0SPIB)—
Offset 740h........................................................................................ 2797
11.2.211Input/Output Stream Descriptor x Max FIFO Size (OSD0MAXFIFOS)—Offset
744h ................................................................................................. 2798
11.2.212Input/Output Stream Descriptor x Software Position in Buffer (OSD1SPIB)—
Offset 748h........................................................................................ 2798
11.2.213Input/Output Stream Descriptor x Max FIFO Size (OSD1MAXFIFOS)—Offset
74Ch................................................................................................. 2799
11.2.214Input/Output Stream Descriptor x Software Position in Buffer (OSD2SPIB)—
Offset 750h........................................................................................ 2799
11.2.215Input/Output Stream Descriptor x Max FIFO Size (OSD2MAXFIFOS)—Offset
754h ................................................................................................. 2800
11.2.216Input/Output Stream Descriptor x Software Position in Buffer (OSD3SPIB)—
Offset 758h........................................................................................ 2800
11.2.217Input/Output Stream Descriptor x Max FIFO Size (OSD3MAXFIFOS)—Offset
75Ch................................................................................................. 2801
11.2.218Input/Output Stream Descriptor x Software Position in Buffer (OSD4SPIB)—
Offset 760h........................................................................................ 2802
11.2.219Input/Output Stream Descriptor x Max FIFO Size (OSD4MAXFIFOS)—Offset
764h ................................................................................................. 2802
11.2.220Input/Output Stream Descriptor x Software Position in Buffer (OSD5SPIB)—
Offset 768h........................................................................................ 2803
11.2.221Input/Output Stream Descriptor x Max FIFO Size (OSD5MAXFIFOS)—Offset
76Ch................................................................................................. 2803
11.2.222Processing Pipe Capability Header (PPCH)—Offset 800h .......................... 2804
11.2.223Processing Pipe Control (PPCTL)—Offset 804h ....................................... 2805
11.2.224Processing Pipe Status (PPSTS)—Offset 808h ........................................ 2806
11.2.225Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC0LLPL)—Offset 810h .................................................................. 2806
11.2.226Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC0LLPU)—Offset 814h ................................................................. 2807
11.2.227Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC0LDPL)—Offset 818h ................................................................. 2807
11.2.228Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC0LDPU)—Offset 81Ch................................................................. 2808
11.2.229Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC1LLPL)—Offset 820h .................................................................. 2809
11.2.230Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC1LLPU)—Offset 824h ................................................................. 2809
11.2.231Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC1LDPL)—Offset 828h ................................................................. 2810

66 334818
 11.2.232Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC1LDPU)—Offset 82Ch .................................................................2810
11.2.233Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC2LLPL)—Offset 830h ..................................................................2811
11.2.234Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC2LLPU)—Offset 834h ..................................................................2811
11.2.235Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC2LDPL)—Offset 838h ..................................................................2812
11.2.236Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC2LDPU)—Offset 83Ch .................................................................2812
11.2.237Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC3LLPL)—Offset 840h ..................................................................2813
11.2.238Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC3LLPU)—Offset 844h ..................................................................2814
11.2.239Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC3LDPL)—Offset 848h ..................................................................2814
11.2.240Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC3LDPU)—Offset 84Ch .................................................................2815
11.2.241Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC4LLPL)—Offset 850h ..................................................................2815
11.2.242Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC4LLPU)—Offset 854h ..................................................................2816
11.2.243Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC4LDPL)—Offset 858h ..................................................................2816
11.2.244Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC4LDPU)—Offset 85Ch .................................................................2817
11.2.245Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC5LLPL)—Offset 860h ..................................................................2818
11.2.246Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC5LLPU)—Offset 864h ..................................................................2818
11.2.247Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC5LDPL)—Offset 868h ..................................................................2819
11.2.248Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC5LDPU)—Offset 86Ch .................................................................2819
11.2.249Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC6LLPL)—Offset 870h ..................................................................2820
11.2.250Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC6LLPU)—Offset 874h ..................................................................2821
11.2.251Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC6LDPL)—Offset 878h ..................................................................2821
11.2.252Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC6LDPU)—Offset 87Ch .................................................................2822
11.2.253Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC0LLPL)—Offset 880h .................................................................2822
11.2.254Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC0LLPU)—Offset 884h .................................................................2823
11.2.255Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC0LDPL)—Offset 888h .................................................................2823
11.2.256Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC0LDPU)—Offset 88Ch ................................................................2824
11.2.257Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC1LLPL)—Offset 890h .................................................................2825
11.2.258Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC1LLPU)—Offset 894h .................................................................2825
11.2.259Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC1LDPL)—Offset 898h .................................................................2826

334818 67
 11.2.260Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC1LDPU)—Offset 89Ch................................................................ 2826
11.2.261Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC2LLPL)—Offset 8A0h................................................................. 2827
11.2.262Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC2LLPU)—Offset 8A4h ................................................................ 2828
11.2.263Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC2LDPL)—Offset 8A8h ................................................................ 2828
11.2.264Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC2LDPU)—Offset 8ACh ............................................................... 2829
11.2.265Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC3LLPL)—Offset 8B0h................................................................. 2829
11.2.266Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC3LLPU)—Offset 8B4h ................................................................ 2830
11.2.267Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC3LDPL)—Offset 8B8h ................................................................ 2830
11.2.268Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC3LDPU)—Offset 8BCh ............................................................... 2831
11.2.269Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC4LLPL)—Offset 8C0h................................................................. 2832
11.2.270Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC4LLPU)—Offset 8C4h ................................................................ 2832
11.2.271Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC4LDPL)—Offset 8C8h ................................................................ 2833
11.2.272Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC4LDPU)—Offset 8CCh ............................................................... 2833
11.2.273Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC5LLPL)—Offset 8D0h ................................................................ 2834
11.2.274Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC5LLPU)—Offset 8D4h ................................................................ 2835
11.2.275Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC5LDPL)—Offset 8D8h ................................................................ 2835
11.2.276Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC5LDPU)—Offset 8DCh ............................................................... 2836
11.2.277Input/Output Processing Pipe's Link Connection x Control (IPPLC0CTL)—Offset
8E0h ................................................................................................. 2836
11.2.278Input/Output Processing Pipe's Link Connection x Format (IPPLC0FMT)—Offset
8E4h ................................................................................................. 2838
11.2.279Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC0LLPL)—Offset 8E8h .................................................................. 2839
11.2.280Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC0LLPU)—Offset 8ECh .................................................................. 2840
11.2.281Input/Output Processing Pipe's Link Connection x Control (IPPLC1CTL)—Offset
8F0h ................................................................................................. 2840
11.2.282Input/Output Processing Pipe's Link Connection x Format (IPPLC1FMT)—Offset
8F4h ................................................................................................. 2841
11.2.283Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC1LLPL)—Offset 8F8h................................................................... 2843
11.2.284Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC1LLPU)—Offset 8FCh .................................................................. 2843
11.2.285Input/Output Processing Pipe's Link Connection x Control (IPPLC2CTL)—Offset
900h ................................................................................................. 2844
11.2.286Input/Output Processing Pipe's Link Connection x Format (IPPLC2FMT)—Offset
904h ................................................................................................. 2845
11.2.287Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC2LLPL)—Offset 908h .................................................................. 2846

68 334818
 11.2.288Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC2LLPU)—Offset 90Ch ..................................................................2847
11.2.289Input/Output Processing Pipe's Link Connection x Control (IPPLC3CTL)—Offset
910h .................................................................................................2847
11.2.290Input/Output Processing Pipe's Link Connection x Format (IPPLC3FMT)—Offset
914h .................................................................................................2849
11.2.291Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC3LLPL)—Offset 918h ...................................................................2850
11.2.292Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC3LLPU)—Offset 91Ch ..................................................................2851
11.2.293Input/Output Processing Pipe's Link Connection x Control (IPPLC4CTL)—Offset
920h .................................................................................................2851
11.2.294Input/Output Processing Pipe's Link Connection x Format (IPPLC4FMT)—Offset
924h .................................................................................................2852
11.2.295Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC4LLPL)—Offset 928h ...................................................................2854
11.2.296Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC4LLPU)—Offset 92Ch ..................................................................2854
11.2.297Input/Output Processing Pipe's Link Connection x Control (IPPLC5CTL)—Offset
930h .................................................................................................2855
11.2.298Input/Output Processing Pipe's Link Connection x Format (IPPLC5FMT)—Offset
934h .................................................................................................2856
11.2.299Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC5LLPL)—Offset 938h ...................................................................2857
11.2.300Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC5LLPU)—Offset 93Ch ..................................................................2858
11.2.301Input/Output Processing Pipe's Link Connection x Control (IPPLC6CTL)—Offset
940h .................................................................................................2858
11.2.302Input/Output Processing Pipe's Link Connection x Format (IPPLC6FMT)—Offset
944h .................................................................................................2860
11.2.303Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC6LLPL)—Offset 948h ...................................................................2861
11.2.304Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC6LLPU)—Offset 94Ch ..................................................................2862
11.2.305Input/Output Processing Pipe's Link Connection x Control (OPPLC0CTL)—Offset
950h .................................................................................................2862
11.2.306Input/Output Processing Pipe's Link Connection x Format (OPPLC0FMT)—Offset
954h .................................................................................................2863
11.2.307Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC0LLPL)—Offset 958h ..................................................................2865
11.2.308Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC0LLPU)—Offset 95Ch .................................................................2865
11.2.309Input/Output Processing Pipe's Link Connection x Control (OPPLC1CTL)—Offset
960h .................................................................................................2866
11.2.310Input/Output Processing Pipe's Link Connection x Format (OPPLC1FMT)—Offset
964h .................................................................................................2867
11.2.311Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC1LLPL)—Offset 968h ..................................................................2868
11.2.312Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC1LLPU)—Offset 96Ch .................................................................2869
11.2.313Input/Output Processing Pipe's Link Connection x Control (OPPLC2CTL)—Offset
970h .................................................................................................2869
11.2.314Input/Output Processing Pipe's Link Connection x Format (OPPLC2FMT)—Offset
974h .................................................................................................2871
11.2.315Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC2LLPL)—Offset 978h ..................................................................2872

334818 69
 11.2.316Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC2LLPU)—Offset 97Ch................................................................. 2873
11.2.317Input/Output Processing Pipe's Link Connection x Control (OPPLC3CTL)—Offset
980h ................................................................................................. 2873
11.2.318Input/Output Processing Pipe's Link Connection x Format (OPPLC3FMT)—Offset
984h ................................................................................................. 2874
11.2.319Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC3LLPL)—Offset 988h ................................................................. 2876
11.2.320Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC3LLPU)—Offset 98Ch................................................................. 2876
11.2.321Input/Output Processing Pipe's Link Connection x Control (OPPLC4CTL)—Offset
990h ................................................................................................. 2877
11.2.322Input/Output Processing Pipe's Link Connection x Format (OPPLC4FMT)—Offset
994h ................................................................................................. 2878
11.2.323Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC4LLPL)—Offset 998h ................................................................. 2879
11.2.324Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC4LLPU)—Offset 99Ch................................................................. 2880
11.2.325Input/Output Processing Pipe's Link Connection x Control (OPPLC5CTL)—Offset
9A0h................................................................................................. 2880
11.2.326Input/Output Processing Pipe's Link Connection x Format (OPPLC5FMT)—Offset
9A4h................................................................................................. 2882
11.2.327Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC5LLPL)—Offset 9A8h ................................................................. 2883
11.2.328Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC5LLPU)—Offset 9ACh................................................................. 2884
11.2.329Multiple Links Capability Header (MLCH)—Offset C00h............................ 2884
11.2.330Multiple Links Capability Declaration (MLCD)—Offset C04h ...................... 2885
11.2.331Link x Capabilities (LCAP0)—Offset C40h .............................................. 2885
11.2.332Link x Output Stream ID Mapping Valid (LOSIDV0)—Offset C48h ............. 2886
11.2.333Link x SDI Identifier (LSDIID0)—Offset C4Ch ........................................ 2888
11.2.334Link x Per Stream Output Overhead (LPSOO0)—Offset C50h ................... 2889
11.2.335Link x Per Stream Input Overhead (LPSIO0)—Offset C52h ...................... 2890
11.2.336Link x Wall Frame Counter (LWALFC0)—Offset C58h .............................. 2890
11.2.337Link x Output Payload Capability (LOUTPAY6M0)—Offset C60h ................ 2891
11.2.338Link x Output Payload Capability (LOUTPAY12M0)—Offset C62h............... 2892
11.2.339Link x Output Payload Capability (LOUTPAY24M0)—Offset C64h............... 2893
11.2.340Link x Output Payload Capability (LOUTPAY48M0)—Offset C66h............... 2894
11.2.341Link x Output Payload Capability (LOUTPAY96M0)—Offset C68h............... 2895
11.2.342Link x Output Payload Capability (LOUTPAY192M0)—Offset C6Ah............. 2896
11.2.343Link x Input Payload Capability (LINPAY6M0)—Offset C70h ..................... 2897
11.2.344Link x Input Payload Capability (LINPAY12M0)—Offset C72h ................... 2898
11.2.345Link x Input Payload Capability (LINPAY24M0)—Offset C74h ................... 2899
11.2.346Link x Input Payload Capability (LINPAY48M0)—Offset C76h ................... 2900
11.2.347Link x Input Payload Capability (LINPAY96M0)—Offset C78h ................... 2901
11.2.348Link x Input Payload Capability (LINPAY192M0)—Offset C7Ah ................. 2902
11.2.349Link x Capabilities (LCAP1)—Offset C80h .............................................. 2903
11.2.350Link x Output Stream ID Mapping Valid (LOSIDV1)—Offset C88h ............. 2904
11.2.351Link x SDI Identifier (LSDIID1)—Offset C8Ch ........................................ 2906
11.2.352Link x Per Stream Output Overhead (LPSOO1)—Offset C90h ................... 2907
11.2.353Link x Per Stream Input Overhead (LPSIO1)—Offset C92h ...................... 2907
11.2.354Link x Wall Frame Counter (LWALFC1)—Offset C98h .............................. 2908
11.2.355Link x Output Payload Capability (LOUTPAY6M1)—Offset CA0h ................ 2908
11.2.356Link x Output Payload Capability (LOUTPAY12M1)—Offset CA2h .............. 2909
11.2.357Link x Output Payload Capability (LOUTPAY24M1)—Offset CA4h .............. 2910
11.2.358Link x Output Payload Capability (LOUTPAY48M1)—Offset CA6h .............. 2911

70 334818
 11.2.359Link x Output Payload Capability (LOUTPAY96M1)—Offset CA8h ...............2912
11.2.360Link x Output Payload Capability (LOUTPAY192M1)—Offset CAAh .............2913
11.2.361Link x Input Payload Capability (LINPAY6M1)—Offset CB0h .....................2914
11.2.362Link x Input Payload Capability (LINPAY12M1)—Offset CB2h....................2915
11.2.363Link x Input Payload Capability (LINPAY24M1)—Offset CB4h....................2916
11.2.364Link x Input Payload Capability (LINPAY48M1)—Offset CB6h....................2917
11.2.365Link x Input Payload Capability (LINPAY96M1)—Offset CB8h....................2918
11.2.366Link x Input Payload Capability (LINPAY192M1)—Offset CBAh ..................2919
11.2.367DMA Resume Capability Header (DRSMCH)—Offset 1F00h .......................2920
11.2.368DMA Resume Control (DRSMCTL)—Offset 1F04h ....................................2921
11.2.369DMA Position in Buffer Resume (ISD0DPIBR)—Offset 1F08h ....................2921
11.2.370DMA Position in Buffer Resume (ISD1DPIBR)—Offset 1F10h ....................2922
11.2.371DMA Position in Buffer Resume (ISD2DPIBR)—Offset 1F18h ....................2922
11.2.372DMA Position in Buffer Resume (ISD3DPIBR)—Offset 1F20h ....................2923
11.2.373DMA Position in Buffer Resume (ISD4DPIBR)—Offset 1F28h ....................2923
11.2.374DMA Position in Buffer Resume (ISD5DPIBR)—Offset 1F30h ....................2924
11.2.375DMA Position in Buffer Resume (ISD6DPIBR)—Offset 1F38h ....................2924
11.2.376DMA Position in Buffer Resume (OSD0DPIBR)—Offset 1F40h ...................2925
11.2.377DMA Position in Buffer Resume (OSD1DPIBR)—Offset 1F48h ...................2925
11.2.378DMA Position in Buffer Resume (OSD2DPIBR)—Offset 1F50h ...................2926
11.2.379DMA Position in Buffer Resume (OSD3DPIBR)—Offset 1F58h ...................2926
11.2.380DMA Position in Buffer Resume (OSD4DPIBR)—Offset 1F60h ...................2927
11.2.381DMA Position in Buffer Resume (OSD5DPIBR)—Offset 1F68h ...................2927
11.2.382Wall Clock Alias (WLCLKA)—Offset 2030h..............................................2928
11.2.383Input Stream Descriptor 0 Link Position in Buffer Alias (ISD0LPIBA)—Offset
2084h................................................................................................2928
11.2.384Input Stream Descriptor 0 Link Position in Buffer Alias (ISD1LPIBA)—Offset
20A4h ...............................................................................................2929
11.2.385Input Stream Descriptor 0 Link Position in Buffer Alias (ISD2LPIBA)—Offset
20C4h ...............................................................................................2930
11.2.386Input Stream Descriptor 0 Link Position in Buffer Alias (ISD3LPIBA)—Offset
20E4h................................................................................................2930
11.2.387Input Stream Descriptor 0 Link Position in Buffer Alias (ISD4LPIBA)—Offset
2104h................................................................................................2931
11.2.388Input Stream Descriptor 0 Link Position in Buffer Alias (ISD5LPIBA)—Offset
2124h................................................................................................2931
11.2.389Input Stream Descriptor 0 Link Position in Buffer Alias (ISD6LPIBA)—Offset
2144h................................................................................................2932
11.2.390Input Stream Descriptor 0 Link Position in Buffer Alias (OSD0LPIBA)—Offset
2164h................................................................................................2932
11.2.391Input Stream Descriptor 0 Link Position in Buffer Alias (OSD1LPIBA)—Offset
2184h................................................................................................2933
11.2.392Input Stream Descriptor 0 Link Position in Buffer Alias (OSD2LPIBA)—Offset
21A4h ...............................................................................................2934
11.2.393Input Stream Descriptor 0 Link Position in Buffer Alias (OSD3LPIBA)—Offset
21C4h ...............................................................................................2934
11.2.394Input Stream Descriptor 0 Link Position in Buffer Alias (OSD4LPIBA)—Offset
21E4h................................................................................................2935
11.2.395Input Stream Descriptor 0 Link Position in Buffer Alias (OSD5LPIBA)—Offset
2204h................................................................................................2935
11.3 ...................................................................................................................2936
11.4 Registers Summary ........................................................................................2937
11.4.1 Vendor Identification (VID)—Offset 0h ...................................................2938
11.4.2 Device ID (DID)—Offset 2h...................................................................2939
11.4.3 Command (CMD)—Offset 4h .................................................................2939
11.4.4 Status (STS)—Offset 6h .......................................................................2940

334818 71
 11.4.5 Revision Identification (RID)—Offset 8h ................................................. 2941
11.4.6 Programming Interface (PI)—Offset 9h .................................................. 2942
11.4.7 Sub Class Code (SCC)—Offset Ah.......................................................... 2942
11.4.8 Base Class Code (BCC)—Offset Bh ........................................................ 2943
11.4.9 Cache Line Size (CLS)—Offset Ch.......................................................... 2943
11.4.10Latency Timer (LT)—Offset Dh.............................................................. 2943
11.4.11Header Type (HTYPE)—Offset Eh........................................................... 2944
11.4.12Built-in Self Test (BIST)—Offset Fh ....................................................... 2944
11.4.13Intel HD Audio Base Lower Address (HDALBA)—Offset 10h ....................... 2945
11.4.14Intel HD Audio Base Upper Address (HDAUBA)—Offset 14h ...................... 2946
11.4.15Shadowed PCI Configuration Lower Base Address (SPCLBA)—Offset 18h .... 2946
11.4.16Shadowed PCI Configuration Upper Base Address (SPCUBA)—Offset 1Ch.... 2947
11.4.17Audio DSP Lower Base Address (ADSPLBA)—Offset 20h ........................... 2947
11.4.18Audio DSP Upper Base Address (ADSPUBA)—Offset 24h........................... 2948
11.4.19Subsystem Vendor ID (SVID)—Offset 2Ch.............................................. 2948
11.4.20Subsystem ID (SID)—Offset 2Eh........................................................... 2949
11.4.21Capability Pointer (CAPPTR)—Offset 34h ................................................ 2950
11.4.22Interrupt Line (INTLN)—Offset 3Ch ....................................................... 2950
11.4.23Interrupt Pin (INTPN)—Offset 3Dh......................................................... 2951
11.4.24Test Mode 1 register (TM1)—Offset 43h ................................................. 2951
11.4.25PCI Power Management Capability ID (PID)—Offset 50h .......................... 2952
11.4.26MSI Capability ID (MID)—Offset 60h ..................................................... 2952
11.4.27MSI Message Control (MMC)—Offset 62h ............................................... 2953
11.4.28MSI Message Lower Address (MMLA)—Offset 64h.................................... 2954
11.4.29MSI Message Upper Address (MMUA)—Offset 68h ................................... 2954
11.4.30MSI Message Data (MMD)—Offset 6Ch................................................... 2954
11.4.31PCI Express Capability ID (PXID)—Offset 70h ......................................... 2955
11.4.32PCI Express Capabilities (PXC)—Offset 72h ............................................ 2955
11.4.33Device Capabilities (DEVCAP)—Offset 74h .............................................. 2956
11.4.34Device Control (DEVC)—Offset 78h ....................................................... 2957
11.4.35Device Status (DEVS)—Offset 7Ah ........................................................ 2959
11.4.36Vendor Specific Capability Identifiers (VSCID)—Offset 80h ....................... 2959
11.4.37Vendor Specific Extended Capability (VSECID)—Offset 84h....................... 2960
11.4.38Device Idle Pointer (DEVIDLEPTR)—Offset 8Ch ....................................... 2961
11.4.39Device Idle Power On Latency (DEVIDLEPOL)—Offset 90h ........................ 2961
11.4.40Virtual Channel Enhanced Capability Header (VCCAP)—Offset 100h ........... 2962
11.4.41Port VC Capability Register 1 (PVCCAP1)—Offset 104h ............................. 2963
11.4.42Port VC Capability Register 2 (PVCCAP2)—Offset 108h ............................. 2964
11.4.43Port VC Control Register (PVCCTL)—Offset 10Ch ..................................... 2964
11.4.44Port VC Status Register (PVCSTS)—Offset 10Eh ...................................... 2965
11.4.45VC0 Resource Capability Register (VC0CAP)—Offset 110h ........................ 2965
11.4.46VC0 Resource Control Register (VC0CTL)—Offset 114h ............................ 2966
11.4.47VC0 Resource Status Register (VC0STS)—Offset 11Ah ............................. 2967
11.4.48VCi Resource Capability Register (VCiCAP)—Offset 11Ch .......................... 2968
11.4.49VCi Resource Control Register (VCiCTL)—Offset 120h .............................. 2968
11.4.50VCi Resource Status Register (VCiSTS)—Offset 126h ............................... 2969
11.4.51Root Complex Link Declaration Enhanced (RCCAP)—Offset 130h ............... 2970
11.4.52Element Self Description (ESD)—Offset 134h.......................................... 2970
11.4.53Link 1 Description (L1DESC)—Offset 140h.............................................. 2971
11.4.54Link 1 Lower Address (L1LADD)—Offset 148h ......................................... 2972
11.4.55Link 1 Upper Address (L1UADD)—Offset 14Ch ........................................ 2972
11.4.56I/O Buffer Control (IOBCTL)—Offset 061Ch ............................................ 2973
11.4.57Power Management Control And Status (PCS)—Offset 0054h .................... 2974
11.4.58LTRC_D013C_PCE—Offset 1048h .......................................................... 2976
11.4.59PID_PC—Offset 0050h ......................................................................... 2977

72 334818
 11.5 Registers Summary ........................................................................................2979
11.5.1 Global Capabilities (GCAP)—Offset 0h ....................................................2992
11.5.2 Minor Version (VMIN)—Offset 2h ...........................................................2993
11.5.3 Major Version (VMAJ)—Offset 3h ...........................................................2993
11.5.4 Output Payload Capability (OUTPAY)—Offset 4h.......................................2994
11.5.5 Input Payload Capability (INPAY)—Offset 6h ...........................................2994
11.5.6 Global Control (GCTL)—Offset 8h...........................................................2995
11.5.7 Wake Enable (WAKEEN)—Offset Ch .......................................................2997
11.5.8 Wake Status (WAKESTS)—Offset Eh ......................................................2997
11.5.9 Global Status (GSTS)—Offset 10h..........................................................2998
11.5.10Global Capabilities 2 (GCAP2)—Offset 12h ..............................................2998
11.5.11Linked List Capabilities Header (LLCH)—Offset 14h ..................................2999
11.5.12Output Stream Payload Capability (OUTSTRMPAY)—Offset 18h ..................3000
11.5.13Input Stream Payload Capability (INSTRMPAY)—Offset 1Ah.......................3000
11.5.14Interrupt Control (INTCTL)—Offset 20h ..................................................3001
11.5.15Interrupt Status (INTSTS)—Offset 24h ...................................................3002
11.5.16Wall Clock Counter (WALCLK)—Offset 30h ..............................................3003
11.5.17Stream Synchronization (SSYNC)—Offset 38h .........................................3004
11.5.18CORB Lower Base Address (CORBLBASE)—Offset 40h ..............................3005
11.5.19CORB Upper Base Address (CORBUBASE)—Offset 44h ..............................3005
11.5.20CORB Write Pointer (CORBWP)—Offset 48h.............................................3006
11.5.21CORB Read Pointer (CORBRP)—Offset 4Ah..............................................3006
11.5.22CORB Control (CORBCTL)—Offset 4Ch....................................................3007
11.5.23CORB Status (CORBSTS)—Offset 4Dh ....................................................3008
11.5.24CORB Size (CORBSIZE)—Offset 4Eh.......................................................3008
11.5.25RIRB Lower Base Address (RIRBLBASE)—Offset 50h ................................3009
11.5.26RIRB Upper Base Address (RIRBUBASE)—Offset 54h ................................3010
11.5.27RIRB Write Pointer (RIRBWP)—Offset 58h...............................................3010
11.5.28Response Interrupt Count (RINTCNT)—Offset 5Ah ...................................3011
11.5.29RIRB Control (RIRBCTL)—Offset 5Ch......................................................3011
11.5.30RIRB Status (RIRBSTS)—Offset 5Dh ......................................................3012
11.5.31RIRB Size (RIRBSIZE)—Offset 5Eh.........................................................3013
11.5.32Immediate Command Status (ICS)—Offset 68h .......................................3013
11.5.33DMA Position Lower Base Address (DPLBASE)—Offset 70h ........................3014
11.5.34DMA Position Upper Base Address (DPUBASE)—Offset 74h........................3015
11.5.35Input/Output Stream Descriptor x Control (ISD0CTL)—Offset 80h..............3016
11.5.36Input/Output Stream Descriptor x Status (ISD0STS)—Offset 83h ..............3017
11.5.37Input/Output Stream Descriptor x Link Position in Buffer (ISD0LPIB)—Offset 84h
3019
11.5.38Input/Output Stream Descriptor x Cyclic Buffer Length (ISD0CBL)—Offset 88h ...
3019
11.5.39Input/Output Stream Descriptor x Last Valid Index (ISD0LVI)—Offset 8Ch ..3020
11.5.40Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW)—Offset
8Eh ...................................................................................................3021
11.5.41Input/Output Stream Descriptor x FIFO Size (ISD0FIFOS)—Offset 90h .......3021
11.5.42Input/Output Stream Descriptor x Format (ISD0FMT)—Offset 92h .............3022
11.5.43Input/Output Stream Descriptor x FIFO Limit (ISD0FIFOL)—Offset 94h.......3024
11.5.44Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD0BDLPLBA)—Offset 98h .....................................................3024
11.5.45Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD0BDLPUBA)—Offset 9Ch.....................................................3025
11.5.46Input/Output Stream Descriptor x Control (ISD1CTL)—Offset A0h..............3025
11.5.47Input/Output Stream Descriptor x Status (ISD1STS)—Offset A3h ..............3027
11.5.48Input/Output Stream Descriptor x Link Position in Buffer (ISD1LPIB)—Offset A4h
3029

334818 73
 11.5.49Input/Output Stream Descriptor x Cyclic Buffer Length (ISD1CBL)—Offset A8h ..
3029
11.5.50Input/Output Stream Descriptor x Last Valid Index (ISD1LVI)—Offset ACh . 3030
11.5.51Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD1FIFOW)—Offset
AEh .................................................................................................. 3031
11.5.52Input/Output Stream Descriptor x FIFO Size (ISD1FIFOS)—Offset B0h....... 3031
11.5.53Input/Output Stream Descriptor x Format (ISD1FMT)—Offset B2h............. 3032
11.5.54Input/Output Stream Descriptor x FIFO Limit (ISD1FIFOL)—Offset B4h ...... 3034
11.5.55Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD1BDLPLBA)—Offset B8h..................................................... 3034
11.5.56Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD1BDLPUBA)—Offset BCh .................................................... 3035
11.5.57Input/Output Stream Descriptor x Control (ISD2CTL)—Offset C0h ............. 3035
11.5.58Input/Output Stream Descriptor x Status (ISD2STS)—Offset C3h.............. 3037
11.5.59Input/Output Stream Descriptor x Link Position in Buffer (ISD2LPIB)—Offset C4h
3039
11.5.60Input/Output Stream Descriptor x Cyclic Buffer Length (ISD2CBL)—Offset C8h ..
3039
11.5.61Input/Output Stream Descriptor x Last Valid Index (ISD2LVI)—Offset CCh . 3040
11.5.62Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD2FIFOW)—Offset
CEh .................................................................................................. 3041
11.5.63Input/Output Stream Descriptor x FIFO Size (ISD2FIFOS)—Offset D0h ...... 3041
11.5.64Input/Output Stream Descriptor x Format (ISD2FMT)—Offset D2h ............ 3042
11.5.65Input/Output Stream Descriptor x FIFO Limit (ISD2FIFOL)—Offset D4h...... 3044
11.5.66Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD2BDLPLBA)—Offset D8h .................................................... 3044
11.5.67Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD2BDLPUBA)—Offset DCh.................................................... 3045
11.5.68Input/Output Stream Descriptor x Control (ISD3CTL)—Offset E0h ............. 3045
11.5.69Input/Output Stream Descriptor x Status (ISD3STS)—Offset E3h .............. 3047
11.5.70Input/Output Stream Descriptor x Link Position in Buffer (ISD3LPIB)—Offset E4h
3049
11.5.71Input/Output Stream Descriptor x Cyclic Buffer Length (ISD3CBL)—Offset E8h ..
3049
11.5.72Input/Output Stream Descriptor x Last Valid Index (ISD3LVI)—Offset ECh . 3050
11.5.73Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD3FIFOW)—Offset
EEh................................................................................................... 3051
11.5.74Input/Output Stream Descriptor x FIFO Size (ISD3FIFOS)—Offset F0h ....... 3051
11.5.75Input/Output Stream Descriptor x Format (ISD3FMT)—Offset F2h ............. 3052
11.5.76Input/Output Stream Descriptor x FIFO Limit (ISD3FIFOL)—Offset F4h ...... 3054
11.5.77Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD3BDLPLBA)—Offset F8h ..................................................... 3054
11.5.78Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD3BDLPUBA)—Offset FCh .................................................... 3055
11.5.79Input/Output Stream Descriptor x Control (ISD4CTL)—Offset 100h ........... 3055
11.5.80Input/Output Stream Descriptor x Status (ISD4STS)—Offset 103h ............ 3057
11.5.81Input/Output Stream Descriptor x Link Position in Buffer (ISD4LPIB)—Offset 104h
3059
11.5.82Input/Output Stream Descriptor x Cyclic Buffer Length (ISD4CBL)—Offset 108h.
3059
11.5.83Input/Output Stream Descriptor x Last Valid Index (ISD4LVI)—Offset 10Ch 3060
11.5.84Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD4FIFOW)—Offset
10Eh ................................................................................................. 3061
11.5.85Input/Output Stream Descriptor x FIFO Size (ISD4FIFOS)—Offset 110h ..... 3061
11.5.86Input/Output Stream Descriptor x Format (ISD4FMT)—Offset 112h ........... 3062
11.5.87Input/Output Stream Descriptor x FIFO Limit (ISD4FIFOL)—Offset 114h .... 3064

74 334818
 11.5.88Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD4BDLPLBA)—Offset 118h....................................................3064
11.5.89Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD4BDLPUBA)—Offset 11Ch ...................................................3065
11.5.90Input/Output Stream Descriptor x Control (ISD5CTL)—Offset 120h ............3065
11.5.91Input/Output Stream Descriptor x Status (ISD5STS)—Offset 123h.............3067
11.5.92Input/Output Stream Descriptor x Link Position in Buffer (ISD5LPIB)—Offset 124h
3069
11.5.93Input/Output Stream Descriptor x Cyclic Buffer Length (ISD5CBL)—Offset 128h .
3069
11.5.94Input/Output Stream Descriptor x Last Valid Index (ISD5LVI)—Offset 12Ch 3070
11.5.95Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD5FIFOW)—Offset
12Eh .................................................................................................3071
11.5.96Input/Output Stream Descriptor x FIFO Size (ISD5FIFOS)—Offset 130h......3071
11.5.97Input/Output Stream Descriptor x Format (ISD5FMT)—Offset 132h............3072
11.5.98Input/Output Stream Descriptor x FIFO Limit (ISD5FIFOL)—Offset 134h .....3074
11.5.99Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD5BDLPLBA)—Offset 138h....................................................3074
11.5.100Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD5BDLPUBA)—Offset 13Ch ...................................................3075
11.5.101Input/Output Stream Descriptor x Control (ISD6CTL)—Offset 140h ..........3075
11.5.102Input/Output Stream Descriptor x Status (ISD6STS)—Offset 143h ...........3077
11.5.103Input/Output Stream Descriptor x Link Position in Buffer (ISD6LPIB)—Offset
144h .................................................................................................3079
11.5.104Input/Output Stream Descriptor x Cyclic Buffer Length (ISD6CBL)—Offset 148h
3079
11.5.105Input/Output Stream Descriptor x Last Valid Index (ISD6LVI)—Offset 14Ch......
3080
11.5.106Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD6FIFOW)—
Offset 14Eh ........................................................................................3081
11.5.107Input/Output Stream Descriptor x FIFO Size (ISD6FIFOS)—Offset 150h ....3081
11.5.108Input/Output Stream Descriptor x Format (ISD6FMT)—Offset 152h ..........3082
11.5.109Input/Output Stream Descriptor x FIFO Limit (ISD6FIFOL)—Offset 154h ...3084
11.5.110Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD6BDLPLBA)—Offset 158h....................................................3084
11.5.111Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD6BDLPUBA)—Offset 15Ch ...................................................3085
11.5.112Input/Output Stream Descriptor x Control (OSD0CTL)—Offset 160h .........3085
11.5.113Input/Output Stream Descriptor x Status (OSD0STS)—Offset 163h ..........3087
11.5.114Input/Output Stream Descriptor x Link Position in Buffer (OSD0LPIB)—Offset
164h .................................................................................................3089
11.5.115Input/Output Stream Descriptor x Cyclic Buffer Length (OSD0CBL)—Offset 168h
3089
11.5.116Input/Output Stream Descriptor x Last Valid Index (OSD0LVI)—Offset 16Ch.....
3090
11.5.117Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD0FIFOW)—
Offset 16Eh ........................................................................................3091
11.5.118Input/Output Stream Descriptor x FIFO Size (OSD0FIFOS)—Offset 170h ...3091
11.5.119Input/Output Stream Descriptor x Format (OSD0FMT)—Offset 172h .........3092
11.5.120Input/Output Stream Descriptor x FIFO Limit (OSD0FIFOL)—Offset 174h ..3094
11.5.121Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD0BDLPLBA)—Offset 178h...................................................3094
11.5.122Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD0BDLPUBA)—Offset 17Ch ..................................................3095
11.5.123Input/Output Stream Descriptor x Control (OSD1CTL)—Offset 180h .........3096
11.5.124Input/Output Stream Descriptor x Status (OSD1STS)—Offset 183h ..........3097

334818 75
 11.5.125Input/Output Stream Descriptor x Link Position in Buffer (OSD1LPIB)—Offset
184h ................................................................................................. 3099
11.5.126Input/Output Stream Descriptor x Cyclic Buffer Length (OSD1CBL)—Offset 188h
3099
11.5.127Input/Output Stream Descriptor x Last Valid Index (OSD1LVI)—Offset 18Ch ....
3100
11.5.128Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD1FIFOW)—
Offset 18Eh........................................................................................ 3101
11.5.129Input/Output Stream Descriptor x FIFO Size (OSD1FIFOS)—Offset 190h... 3101
11.5.130Input/Output Stream Descriptor x Format (OSD1FMT)—Offset 192h......... 3102
11.5.131Input/Output Stream Descriptor x FIFO Limit (OSD1FIFOL)—Offset 194h .. 3104
11.5.132Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD1BDLPLBA)—Offset 198h .................................................. 3104
11.5.133Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD1BDLPUBA)—Offset 19Ch ................................................. 3105
11.5.134Input/Output Stream Descriptor x Control (OSD2CTL)—Offset 1A0h......... 3106
11.5.135Input/Output Stream Descriptor x Status (OSD2STS)—Offset 1A3h.......... 3107
11.5.136Input/Output Stream Descriptor x Link Position in Buffer (OSD2LPIB)—Offset
1A4h................................................................................................. 3109
11.5.137Input/Output Stream Descriptor x Cyclic Buffer Length (OSD2CBL)—Offset 1A8h
3109
11.5.138Input/Output Stream Descriptor x Last Valid Index (OSD2LVI)—Offset 1ACh ....
3110
11.5.139Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD2FIFOW)—
Offset 1AEh ....................................................................................... 3111
11.5.140Input/Output Stream Descriptor x FIFO Size (OSD2FIFOS)—Offset 1B0h .. 3111
11.5.141Input/Output Stream Descriptor x Format (OSD2FMT)—Offset 1B2h ........ 3112
11.5.142Input/Output Stream Descriptor x FIFO Limit (OSD2FIFOL)—Offset 1B4h.. 3114
11.5.143Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD2BDLPLBA)—Offset 1B8h .................................................. 3114
11.5.144Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD2BDLPUBA)—Offset 1BCh ................................................. 3115
11.5.145Input/Output Stream Descriptor x Control (OSD3CTL)—Offset 1C0h......... 3116
11.5.146Input/Output Stream Descriptor x Status (OSD3STS)—Offset 1C3h.......... 3117
11.5.147Input/Output Stream Descriptor x Link Position in Buffer (OSD3LPIB)—Offset
1C4h................................................................................................. 3119
11.5.148Input/Output Stream Descriptor x Cyclic Buffer Length (OSD3CBL)—Offset 1C8h
3119
11.5.149Input/Output Stream Descriptor x Last Valid Index (OSD3LVI)—Offset 1CCh ....
3120
11.5.150Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD3FIFOW)—
Offset 1CEh ....................................................................................... 3121
11.5.151Input/Output Stream Descriptor x FIFO Size (OSD3FIFOS)—Offset 1D0h .. 3121
11.5.152Input/Output Stream Descriptor x Format (OSD3FMT)—Offset 1D2h ........ 3122
11.5.153Input/Output Stream Descriptor x FIFO Limit (OSD3FIFOL)—Offset 1D4h . 3124
11.5.154Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD3BDLPLBA)—Offset 1D8h.................................................. 3124
11.5.155Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD3BDLPUBA)—Offset 1DCh ................................................. 3125
11.5.156Input/Output Stream Descriptor x Control (OSD4CTL)—Offset 1E0h ......... 3126
11.5.157Input/Output Stream Descriptor x Status (OSD4STS)—Offset 1E3h.......... 3127
11.5.158Input/Output Stream Descriptor x Link Position in Buffer (OSD4LPIB)—Offset
1E4h ................................................................................................. 3129
11.5.159Input/Output Stream Descriptor x Cyclic Buffer Length (OSD4CBL)—Offset 1E8h
3129
11.5.160Input/Output Stream Descriptor x Last Valid Index (OSD4LVI)—Offset 1ECh ....
3130

76 334818
 11.5.161Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD4FIFOW)—
Offset 1EEh ........................................................................................3131
11.5.162Input/Output Stream Descriptor x FIFO Size (OSD4FIFOS)—Offset 1F0h ...3131
11.5.163Input/Output Stream Descriptor x Format (OSD4FMT)—Offset 1F2h .........3132
11.5.164Input/Output Stream Descriptor x FIFO Limit (OSD4FIFOL)—Offset 1F4h...3134
11.5.165Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD4BDLPLBA)—Offset 1F8h...................................................3134
11.5.166Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD4BDLPUBA)—Offset 1FCh ..................................................3135
11.5.167Input/Output Stream Descriptor x Control (OSD5CTL)—Offset 200h .........3135
11.5.168Input/Output Stream Descriptor x Status (OSD5STS)—Offset 203h ..........3137
11.5.169Input/Output Stream Descriptor x Link Position in Buffer (OSD5LPIB)—Offset
204h .................................................................................................3139
11.5.170Input/Output Stream Descriptor x Cyclic Buffer Length (OSD5CBL)—Offset 208h
3139
11.5.171Input/Output Stream Descriptor x Last Valid Index (OSD5LVI)—Offset 20Ch.....
3140
11.5.172Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD5FIFOW)—
Offset 20Eh ........................................................................................3141
11.5.173Input/Output Stream Descriptor x FIFO Size (OSD5FIFOS)—Offset 210h ...3141
11.5.174Input/Output Stream Descriptor x Format (OSD5FMT)—Offset 212h .........3142
11.5.175Input/Output Stream Descriptor x FIFO Limit (OSD5FIFOL)—Offset 214h ..3144
11.5.176Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD5BDLPLBA)—Offset 218h...................................................3144
11.5.177Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD5BDLPUBA)—Offset 21Ch ..................................................3145
11.5.178Global Time Synchronization Capability Header (GTSCH)—Offset 500h ......3146
11.5.179Global Time Synchronization Controller Adjust Control (GTSCTLAC)—Offset 50Ch
3146
11.5.180Global Time Synchronization Capture Control (GTSCC0)—Offset 520h .......3147
11.5.181Wall Frame Counter Captured (WALFCC0)—Offset 524h ..........................3148
11.5.182Time Stamp Counter Captured Lower (TSCCL0)—Offset 528h ..................3149
11.5.183Time Stamp Counter Captured Upper (TSCCU0)—Offset 52Ch..................3149
11.5.184Linear Link Position Frame Offset Captured (LLPFOC0)—Offset 534h .........3150
11.5.185Linear Link Position Captured Lower (LLPCL0)—Offset 538h .....................3150
11.5.186Linear Link Position Captured Upper (LLPCU0)—Offset 53Ch ....................3151
11.5.187Global Time Synchronization Capture Control (GTSCC1)—Offset 540h .......3151
11.5.188Wall Frame Counter Captured (WALFCC1)—Offset 544h ..........................3152
11.5.189Time Stamp Counter Captured Lower (TSCCL1)—Offset 548h ..................3153
11.5.190Time Stamp Counter Captured Upper (TSCCU1)—Offset 54Ch..................3153
11.5.191Linear Link Position Frame Offset Captured (LLPFOC1)—Offset 554h .........3154
11.5.192Linear Link Position Captured Lower (LLPCL1)—Offset 558h .....................3154
11.5.193Linear Link Position Captured Upper (LLPCU1)—Offset 55Ch ....................3155
11.5.194Software Position Based FIFO Capability Header (SPBFCH)—Offset 700h ...3155
11.5.195Software Position Based FIFO Control (SPBFCTL)—Offset 704h.................3156
11.5.196Input/Output Stream Descriptor x Software Position in Buffer (ISD0SPIB)—
Offset 708h ........................................................................................3157
11.5.197Input/Output Stream Descriptor x Max FIFO Size (ISD0MAXFIFOS)—Offset 70Ch
3157
11.5.198Input/Output Stream Descriptor x Software Position in Buffer (ISD1SPIB)—
Offset 710h ........................................................................................3158
11.5.199Input/Output Stream Descriptor x Max FIFO Size (ISD1MAXFIFOS)—Offset 714h
3158
11.5.200Input/Output Stream Descriptor x Software Position in Buffer (ISD2SPIB)—
Offset 718h ........................................................................................3159

334818 77
 11.5.201Input/Output Stream Descriptor x Max FIFO Size (ISD2MAXFIFOS)—Offset 71Ch
3160
11.5.202Input/Output Stream Descriptor x Software Position in Buffer (ISD3SPIB)—
Offset 720h........................................................................................ 3160
11.5.203Input/Output Stream Descriptor x Max FIFO Size (ISD3MAXFIFOS)—Offset 724h
3161
11.5.204Input/Output Stream Descriptor x Software Position in Buffer (ISD4SPIB)—
Offset 728h........................................................................................ 3161
11.5.205Input/Output Stream Descriptor x Max FIFO Size (ISD4MAXFIFOS)—Offset 72Ch
3162
11.5.206Input/Output Stream Descriptor x Software Position in Buffer (ISD5SPIB)—
Offset 730h........................................................................................ 3163
11.5.207Input/Output Stream Descriptor x Max FIFO Size (ISD5MAXFIFOS)—Offset 734h
3163
11.5.208Input/Output Stream Descriptor x Software Position in Buffer (ISD6SPIB)—
Offset 738h........................................................................................ 3164
11.5.209Input/Output Stream Descriptor x Max FIFO Size (ISD6MAXFIFOS)—Offset 73Ch
3164
11.5.210Input/Output Stream Descriptor x Software Position in Buffer (OSD0SPIB)—
Offset 740h........................................................................................ 3165
11.5.211Input/Output Stream Descriptor x Max FIFO Size (OSD0MAXFIFOS)—Offset
744h ................................................................................................. 3166
11.5.212Input/Output Stream Descriptor x Software Position in Buffer (OSD1SPIB)—
Offset 748h........................................................................................ 3166
11.5.213Input/Output Stream Descriptor x Max FIFO Size (OSD1MAXFIFOS)—Offset
74Ch................................................................................................. 3167
11.5.214Input/Output Stream Descriptor x Software Position in Buffer (OSD2SPIB)—
Offset 750h........................................................................................ 3167
11.5.215Input/Output Stream Descriptor x Max FIFO Size (OSD2MAXFIFOS)—Offset
754h ................................................................................................. 3168
11.5.216Input/Output Stream Descriptor x Software Position in Buffer (OSD3SPIB)—
Offset 758h........................................................................................ 3168
11.5.217Input/Output Stream Descriptor x Max FIFO Size (OSD3MAXFIFOS)—Offset
75Ch................................................................................................. 3169
11.5.218Input/Output Stream Descriptor x Software Position in Buffer (OSD4SPIB)—
Offset 760h........................................................................................ 3170
11.5.219Input/Output Stream Descriptor x Max FIFO Size (OSD4MAXFIFOS)—Offset
764h ................................................................................................. 3170
11.5.220Input/Output Stream Descriptor x Software Position in Buffer (OSD5SPIB)—
Offset 768h........................................................................................ 3171
11.5.221Input/Output Stream Descriptor x Max FIFO Size (OSD5MAXFIFOS)—Offset
76Ch................................................................................................. 3171
11.5.222Processing Pipe Capability Header (PPCH)—Offset 800h .......................... 3172
11.5.223Processing Pipe Control (PPCTL)—Offset 804h ....................................... 3173
11.5.224Processing Pipe Status (PPSTS)—Offset 808h ........................................ 3174
11.5.225Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC0LLPL)—Offset 810h .................................................................. 3174
11.5.226Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC0LLPU)—Offset 814h ................................................................. 3175
11.5.227Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC0LDPL)—Offset 818h ................................................................. 3175
11.5.228Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC0LDPU)—Offset 81Ch................................................................. 3176
11.5.229Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC1LLPL)—Offset 820h .................................................................. 3177
11.5.230Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC1LLPU)—Offset 824h ................................................................. 3177

78 334818
 11.5.231Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC1LDPL)—Offset 828h ..................................................................3178
11.5.232Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC1LDPU)—Offset 82Ch .................................................................3178
11.5.233Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC2LLPL)—Offset 830h ..................................................................3179
11.5.234Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC2LLPU)—Offset 834h ..................................................................3179
11.5.235Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC2LDPL)—Offset 838h ..................................................................3180
11.5.236Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC2LDPU)—Offset 83Ch .................................................................3180
11.5.237Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC3LLPL)—Offset 840h ..................................................................3181
11.5.238Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC3LLPU)—Offset 844h ..................................................................3182
11.5.239Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC3LDPL)—Offset 848h ..................................................................3182
11.5.240Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC3LDPU)—Offset 84Ch .................................................................3183
11.5.241Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC4LLPL)—Offset 850h ..................................................................3183
11.5.242Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC4LLPU)—Offset 854h ..................................................................3184
11.5.243Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC4LDPL)—Offset 858h ..................................................................3184
11.5.244Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC4LDPU)—Offset 85Ch .................................................................3185
11.5.245Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC5LLPL)—Offset 860h ..................................................................3186
11.5.246Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC5LLPU)—Offset 864h ..................................................................3186
11.5.247Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC5LDPL)—Offset 868h ..................................................................3187
11.5.248Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC5LDPU)—Offset 86Ch .................................................................3187
11.5.249Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC6LLPL)—Offset 870h ..................................................................3188
11.5.250Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC6LLPU)—Offset 874h ..................................................................3189
11.5.251Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC6LDPL)—Offset 878h ..................................................................3189
11.5.252Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC6LDPU)—Offset 87Ch .................................................................3190
11.5.253Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC0LLPL)—Offset 880h .................................................................3190
11.5.254Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC0LLPU)—Offset 884h .................................................................3191
11.5.255Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC0LDPL)—Offset 888h .................................................................3191
11.5.256Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC0LDPU)—Offset 88Ch ................................................................3192
11.5.257Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC1LLPL)—Offset 890h .................................................................3193
11.5.258Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC1LLPU)—Offset 894h .................................................................3193

334818 79
 11.5.259Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC1LDPL)—Offset 898h ................................................................ 3194
11.5.260Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC1LDPU)—Offset 89Ch................................................................ 3194
11.5.261Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC2LLPL)—Offset 8A0h................................................................. 3195
11.5.262Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC2LLPU)—Offset 8A4h ................................................................ 3196
11.5.263Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC2LDPL)—Offset 8A8h ................................................................ 3196
11.5.264Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC2LDPU)—Offset 8ACh ............................................................... 3197
11.5.265Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC3LLPL)—Offset 8B0h................................................................. 3197
11.5.266Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC3LLPU)—Offset 8B4h ................................................................ 3198
11.5.267Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC3LDPL)—Offset 8B8h ................................................................ 3198
11.5.268Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC3LDPU)—Offset 8BCh ............................................................... 3199
11.5.269Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC4LLPL)—Offset 8C0h................................................................. 3200
11.5.270Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC4LLPU)—Offset 8C4h ................................................................ 3200
11.5.271Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC4LDPL)—Offset 8C8h ................................................................ 3201
11.5.272Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC4LDPU)—Offset 8CCh ............................................................... 3201
11.5.273Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC5LLPL)—Offset 8D0h ................................................................ 3202
11.5.274Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC5LLPU)—Offset 8D4h ................................................................ 3203
11.5.275Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC5LDPL)—Offset 8D8h ................................................................ 3203
11.5.276Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC5LDPU)—Offset 8DCh ............................................................... 3204
11.5.277Input/Output Processing Pipe's Link Connection x Control (IPPLC0CTL)—Offset
8E0h ................................................................................................. 3204
11.5.278Input/Output Processing Pipe's Link Connection x Format (IPPLC0FMT)—Offset
8E4h ................................................................................................. 3206
11.5.279Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC0LLPL)—Offset 8E8h .................................................................. 3207
11.5.280Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC0LLPU)—Offset 8ECh .................................................................. 3208
11.5.281Input/Output Processing Pipe's Link Connection x Control (IPPLC1CTL)—Offset
8F0h ................................................................................................. 3208
11.5.282Input/Output Processing Pipe's Link Connection x Format (IPPLC1FMT)—Offset
8F4h ................................................................................................. 3209
11.5.283Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC1LLPL)—Offset 8F8h................................................................... 3211
11.5.284Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC1LLPU)—Offset 8FCh .................................................................. 3212
11.5.285Input/Output Processing Pipe's Link Connection x Control (IPPLC2CTL)—Offset
900h ................................................................................................. 3212
11.5.286Input/Output Processing Pipe's Link Connection x Format (IPPLC2FMT)—Offset
904h ................................................................................................. 3213

80 334818
 11.5.287Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC2LLPL)—Offset 908h ...................................................................3215
11.5.288Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC2LLPU)—Offset 90Ch ..................................................................3215
11.5.289Input/Output Processing Pipe's Link Connection x Control (IPPLC3CTL)—Offset
910h .................................................................................................3216
11.5.290Input/Output Processing Pipe's Link Connection x Format (IPPLC3FMT)—Offset
914h .................................................................................................3217
11.5.291Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC3LLPL)—Offset 918h ...................................................................3218
11.5.292Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC3LLPU)—Offset 91Ch ..................................................................3219
11.5.293Input/Output Processing Pipe's Link Connection x Control (IPPLC4CTL)—Offset
920h .................................................................................................3219
11.5.294Input/Output Processing Pipe's Link Connection x Format (IPPLC4FMT)—Offset
924h .................................................................................................3221
11.5.295Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC4LLPL)—Offset 928h ...................................................................3222
11.5.296Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC4LLPU)—Offset 92Ch ..................................................................3223
11.5.297Input/Output Processing Pipe's Link Connection x Control (IPPLC5CTL)—Offset
930h .................................................................................................3223
11.5.298Input/Output Processing Pipe's Link Connection x Format (IPPLC5FMT)—Offset
934h .................................................................................................3224
11.5.299Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC5LLPL)—Offset 938h ...................................................................3226
11.5.300Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC5LLPU)—Offset 93Ch ..................................................................3226
11.5.301Input/Output Processing Pipe's Link Connection x Control (IPPLC6CTL)—Offset
940h .................................................................................................3227
11.5.302Input/Output Processing Pipe's Link Connection x Format (IPPLC6FMT)—Offset
944h .................................................................................................3228
11.5.303Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC6LLPL)—Offset 948h ...................................................................3229
11.5.304Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC6LLPU)—Offset 94Ch ..................................................................3230
11.5.305Input/Output Processing Pipe's Link Connection x Control (OPPLC0CTL)—Offset
950h .................................................................................................3230
11.5.306Input/Output Processing Pipe's Link Connection x Format (OPPLC0FMT)—Offset
954h .................................................................................................3232
11.5.307Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC0LLPL)—Offset 958h ..................................................................3233
11.5.308Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC0LLPU)—Offset 95Ch .................................................................3234
11.5.309Input/Output Processing Pipe's Link Connection x Control (OPPLC1CTL)—Offset
960h .................................................................................................3234
11.5.310Input/Output Processing Pipe's Link Connection x Format (OPPLC1FMT)—Offset
964h .................................................................................................3235
11.5.311Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC1LLPL)—Offset 968h ..................................................................3237
11.5.312Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC1LLPU)—Offset 96Ch .................................................................3237
11.5.313Input/Output Processing Pipe's Link Connection x Control (OPPLC2CTL)—Offset
970h .................................................................................................3238
11.5.314Input/Output Processing Pipe's Link Connection x Format (OPPLC2FMT)—Offset
974h .................................................................................................3239

334818 81
 11.5.315Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC2LLPL)—Offset 978h ................................................................. 3240
11.5.316Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC2LLPU)—Offset 97Ch................................................................. 3241
11.5.317Input/Output Processing Pipe's Link Connection x Control (OPPLC3CTL)—Offset
980h ................................................................................................. 3241
11.5.318Input/Output Processing Pipe's Link Connection x Format (OPPLC3FMT)—Offset
984h ................................................................................................. 3243
11.5.319Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC3LLPL)—Offset 988h ................................................................. 3244
11.5.320Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC3LLPU)—Offset 98Ch................................................................. 3245
11.5.321Input/Output Processing Pipe's Link Connection x Control (OPPLC4CTL)—Offset
990h ................................................................................................. 3245
11.5.322Input/Output Processing Pipe's Link Connection x Format (OPPLC4FMT)—Offset
994h ................................................................................................. 3246
11.5.323Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC4LLPL)—Offset 998h ................................................................. 3248
11.5.324Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC4LLPU)—Offset 99Ch................................................................. 3248
11.5.325Input/Output Processing Pipe's Link Connection x Control (OPPLC5CTL)—Offset
9A0h................................................................................................. 3249
11.5.326Input/Output Processing Pipe's Link Connection x Format (OPPLC5FMT)—Offset
9A4h................................................................................................. 3250
11.5.327Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC5LLPL)—Offset 9A8h ................................................................. 3251
11.5.328Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC5LLPU)—Offset 9ACh................................................................. 3252
11.5.329Multiple Links Capability Header (MLCH)—Offset C00h............................ 3252
11.5.330Multiple Links Capability Declaration (MLCD)—Offset C04h ...................... 3253
11.5.331Link x Capabilities (LCAP0)—Offset C40h .............................................. 3254
11.5.332Link x Output Stream ID Mapping Valid (LOSIDV0)—Offset C48h ............. 3255
11.5.333Link x SDI Identifier (LSDIID0)—Offset C4Ch ........................................ 3256
11.5.334Link x Per Stream Output Overhead (LPSOO0)—Offset C50h ................... 3258
11.5.335Link x Per Stream Input Overhead (LPSIO0)—Offset C52h ...................... 3258
11.5.336Link x Wall Frame Counter (LWALFC0)—Offset C58h .............................. 3259
11.5.337Link x Output Payload Capability (LOUTPAY6M0)—Offset C60h ................ 3259
11.5.338Link x Output Payload Capability (LOUTPAY12M0)—Offset C62h............... 3260
11.5.339Link x Output Payload Capability (LOUTPAY24M0)—Offset C64h............... 3261
11.5.340Link x Output Payload Capability (LOUTPAY48M0)—Offset C66h............... 3262
11.5.341Link x Output Payload Capability (LOUTPAY96M0)—Offset C68h............... 3263
11.5.342Link x Output Payload Capability (LOUTPAY192M0)—Offset C6Ah............. 3264
11.5.343Link x Input Payload Capability (LINPAY6M0)—Offset C70h ..................... 3265
11.5.344Link x Input Payload Capability (LINPAY12M0)—Offset C72h ................... 3266
11.5.345Link x Input Payload Capability (LINPAY24M0)—Offset C74h ................... 3267
11.5.346Link x Input Payload Capability (LINPAY48M0)—Offset C76h ................... 3268
11.5.347Link x Input Payload Capability (LINPAY96M0)—Offset C78h ................... 3269
11.5.348Link x Input Payload Capability (LINPAY192M0)—Offset C7Ah ................. 3270
11.5.349Link x Capabilities (LCAP1)—Offset C80h .............................................. 3271
11.5.350Link x Output Stream ID Mapping Valid (LOSIDV1)—Offset C88h ............. 3272
11.5.351Link x SDI Identifier (LSDIID1)—Offset C8Ch ........................................ 3274
11.5.352Link x Per Stream Output Overhead (LPSOO1)—Offset C90h ................... 3275
11.5.353Link x Per Stream Input Overhead (LPSIO1)—Offset C92h ...................... 3275
11.5.354Link x Wall Frame Counter (LWALFC1)—Offset C98h .............................. 3276
11.5.355Link x Output Payload Capability (LOUTPAY6M1)—Offset CA0h ................ 3276
11.5.356Link x Output Payload Capability (LOUTPAY12M1)—Offset CA2h .............. 3277

82 334818
 11.5.357Link x Output Payload Capability (LOUTPAY24M1)—Offset CA4h ...............3278
11.5.358Link x Output Payload Capability (LOUTPAY48M1)—Offset CA6h ...............3279
11.5.359Link x Output Payload Capability (LOUTPAY96M1)—Offset CA8h ...............3280
11.5.360Link x Output Payload Capability (LOUTPAY192M1)—Offset CAAh .............3281
11.5.361Link x Input Payload Capability (LINPAY6M1)—Offset CB0h .....................3282
11.5.362Link x Input Payload Capability (LINPAY12M1)—Offset CB2h....................3283
11.5.363Link x Input Payload Capability (LINPAY24M1)—Offset CB4h....................3284
11.5.364Link x Input Payload Capability (LINPAY48M1)—Offset CB6h....................3285
11.5.365Link x Input Payload Capability (LINPAY96M1)—Offset CB8h....................3286
11.5.366Link x Input Payload Capability (LINPAY192M1)—Offset CBAh ..................3287
11.5.367DMA Resume Capability Header (DRSMCH)—Offset 1F00h .......................3288
11.5.368DMA Resume Control (DRSMCTL)—Offset 1F04h ....................................3289
11.5.369DMA Position in Buffer Resume (ISD0DPIBR)—Offset 1F08h ....................3289
11.5.370DMA Position in Buffer Resume (ISD1DPIBR)—Offset 1F10h ....................3290
11.5.371DMA Position in Buffer Resume (ISD2DPIBR)—Offset 1F18h ....................3290
11.5.372DMA Position in Buffer Resume (ISD3DPIBR)—Offset 1F20h ....................3291
11.5.373DMA Position in Buffer Resume (ISD4DPIBR)—Offset 1F28h ....................3291
11.5.374DMA Position in Buffer Resume (ISD5DPIBR)—Offset 1F30h ....................3292
11.5.375DMA Position in Buffer Resume (ISD6DPIBR)—Offset 1F38h ....................3292
11.5.376DMA Position in Buffer Resume (OSD0DPIBR)—Offset 1F40h ...................3293
11.5.377DMA Position in Buffer Resume (OSD1DPIBR)—Offset 1F48h ...................3293
11.5.378DMA Position in Buffer Resume (OSD2DPIBR)—Offset 1F50h ...................3294
11.5.379DMA Position in Buffer Resume (OSD3DPIBR)—Offset 1F58h ...................3294
11.5.380DMA Position in Buffer Resume (OSD4DPIBR)—Offset 1F60h ...................3295
11.5.381DMA Position in Buffer Resume (OSD5DPIBR)—Offset 1F68h ...................3295
11.5.382Wall Clock Alias (WLCLKA)—Offset 2030h..............................................3296
11.5.383Input Stream Descriptor 0 Link Position in Buffer Alias (ISD0LPIBA)—Offset
2084h................................................................................................3296
11.5.384Input Stream Descriptor 0 Link Position in Buffer Alias (ISD1LPIBA)—Offset
20A4h ...............................................................................................3297
11.5.385Input Stream Descriptor 0 Link Position in Buffer Alias (ISD2LPIBA)—Offset
20C4h ...............................................................................................3298
11.5.386Input Stream Descriptor 0 Link Position in Buffer Alias (ISD3LPIBA)—Offset
20E4h................................................................................................3298
11.5.387Input Stream Descriptor 0 Link Position in Buffer Alias (ISD4LPIBA)—Offset
2104h................................................................................................3299
11.5.388Input Stream Descriptor 0 Link Position in Buffer Alias (ISD5LPIBA)—Offset
2124h................................................................................................3299
11.5.389Input Stream Descriptor 0 Link Position in Buffer Alias (ISD6LPIBA)—Offset
2144h................................................................................................3300
11.5.390Input Stream Descriptor 0 Link Position in Buffer Alias (OSD0LPIBA)—Offset
2164h................................................................................................3300
11.5.391Input Stream Descriptor 0 Link Position in Buffer Alias (OSD1LPIBA)—Offset
2184h................................................................................................3301
11.5.392Input Stream Descriptor 0 Link Position in Buffer Alias (OSD2LPIBA)—Offset
21A4h ...............................................................................................3302
11.5.393Input Stream Descriptor 0 Link Position in Buffer Alias (OSD3LPIBA)—Offset
21C4h ...............................................................................................3302
11.5.394Input Stream Descriptor 0 Link Position in Buffer Alias (OSD4LPIBA)—Offset
21E4h................................................................................................3303
11.5.395Input Stream Descriptor 0 Link Position in Buffer Alias (OSD5LPIBA)—Offset
2204h................................................................................................3303
12 Power Management Controller (PMC) ...................................................................3305
12.1 Registers Summary ........................................................................................3305
12.1.1 Power Management 1 Status and Enable (PM1_STS_EN)—Offset 0h ...........3305

334818 83
 12.1.2 Power Management 1 Control (PM1_CNT)—Offset 4h ............................... 3310
12.1.3 Power Management 1 Timer (PM1_TMR)—Offset 8h................................. 3311
12.1.4 General Purpose Event 0 Status (GPE0a_STS)—Offset 20h ....................... 3311
12.1.5 General Purpose Event 0 Status (GPE0b_STS)—Offset 24h ....................... 3315
12.1.6 General Purpose Event 0 Status (GPE0c_STS)—Offset 28h ....................... 3315
12.1.7 General Purpose Event 0 Status (GPE0d_STS)—Offset 2Ch....................... 3316
12.1.8 General Purpose Event 0 Enables (GPE0a_EN)—Offset 30h ....................... 3316
12.1.9 General Purpose Event 0 Enable (GPE0b_EN)—Offset 34h ........................ 3320
12.1.10General Purpose Event 0 Enable (GPE0c_EN)—Offset 38h ........................ 3320
12.1.11General Purpose Event 0 Enable (GPE0d_EN)—Offset 3Ch ........................ 3321
12.1.12SMI Control and Enable (SMI_EN)—Offset 40h........................................ 3321
12.1.13SMI Status Register (SMI_STS)—Offset 44h ........................................... 3324
12.1.14Device Trap Status (DEVTRAP_STS)—Offset 4Ch..................................... 3328
12.1.15General Purpose Event Control (GPE_CTRL)—Offset 50h .......................... 3329
12.1.16TCO Reload Register (TCO_RLD)—Offset 60h.......................................... 3329
12.1.17TCO Timer Status (TCO_STS)—Offset 64h.............................................. 3330
12.1.18TCO Timer Control (TCO1_CNT)—Offset 68h........................................... 3331
12.1.19TCO Timer Register (TCO_TMR)—Offset 70h........................................... 3331
12.1.20Advanced Power Management Status (APM_STS)—Offset 74h................... 3332
12.1.21Advanced Power Management Control Port (APM_CNT)—Offset 78h ........... 3333
12.1.22Direct IRQ Enables (DIRECT_IRQ_EN)—Offset 7Ch .................................. 3333
12.1.23PCI Configuration Control 1 Register(PCICFGCTR1)—Offset 200h .............. 3335
12.1.24PCI Configuration Control 2 Register(PCICFGCTR2)—Offset 204h .............. 3336
12.1.25PCI Configuration Control 3 Register(PCICFGCTR3)—Offset 208h .............. 3337
12.2 Registers Summary........................................................................................ 3338
12.2.1 Power and Reset Status (PRSTS)—Offset 1000h...................................... 3339
12.2.2 PM CFG - Power Management Configuration (PMC_CFG)—Offset 1008h ...... 3339
12.2.3 Power Management Configuration (PMC_CFG2)—Offset 100Ch.................. 3342
12.2.4 SOC Power Management Status (SOC_PM_STS)—Offset 1010h ................. 3343
12.2.5 General PM Configuration 1 (GEN_PMCON1)—Offset 1020h ...................... 3344
12.2.6 General PM Configuration 2 (GEN_PMCON2)—Offset 1024h ...................... 3347
12.2.7 General PM Configuration 3 (GEN_PMCON3)—Offset 1028h ...................... 3349
12.2.8 Configured Revision ID (CRID)—Offset 1030h ......................................... 3351
12.2.9 Function Disable 0 (FUNC_DIS_0)—Offset 1034h .................................... 3352
12.2.10Function Disable 1 (FUNC_DIS_1)—Offset 1038h .................................... 3354
12.2.11Extended Test Mode Register (ETR)—Offset 1048h .................................. 3355
12.2.12GPIO Group to General Purpose Event Register Configuration (GPIO_GPE_CFG)—
Offset 1050h ...................................................................................... 3356
12.2.13IRQ Select 0 (IRQ_SEL_0)—Offset 1064h............................................... 3358
12.2.14IRQ Select 1 (IRQ_SEL_1)—Offset 1068h............................................... 3359
12.2.15IRQ Select 2 (IRQ_SEL_2)—Offset 106Ch .............................................. 3360
12.2.16Function ACPI Enumeration 0 (FUNC_ACPI_ENUM_0)—Offset 1070h.......... 3360
12.2.17Function ACPI Enumeration 1 (FUNC_ACPI_ENUM_1)—Offset 1074h.......... 3362
12.2.18Fixed Deep S0Ix Counter Lower 32 Bits (TELEM_DEEP_S0IX_LO_HOST)—Offset
1078h ............................................................................................... 3363
12.2.19Fixed Deep S0Ix Counter Upper 32 Bits (TELEM_DEEP_S0IX_HI_HOST)—Offset
107Ch ............................................................................................... 3364
12.2.20Fixed Shallow S0Ix Counter Lower 32 Bits (TELEM_SHALLOW_S0IX_LO_HOST)—
Offset 1080h ...................................................................................... 3364
12.2.21Fixed Shallow S0Ix Counter Upper 32 Bits (TELEM_SHALLOW_S0IX_HI_HOST)—
Offset 1084h ...................................................................................... 3365
12.2.22Reserved (TELEM_MISC_FIXED_LO_HOST)—Offset 1088h........................ 3365
12.2.23Reserved register for sharing data with software upper 32 bits
(TELEM_MISC_FIXED_HI_HOST)—Offset 108Ch...................................... 3366

84 334818
 12.2.24Scratchpad for sharing data between BIOS and PMC Firmware
(BIOS_SCRATCHPAD)—Offset 1090h .....................................................3367
12.2.25Display Hot Plug Detect Control (DISPLAY_HPD_CTL)—Offset 1094h ..........3369
12.2.26OBFF Control and Status (OBFF_CTL_STS)—Offset 10C8h.........................3370
12.2.27Lock Register (LOCK)—Offset 10CCh......................................................3372
12.3 Registers Summary ........................................................................................3374
12.3.1 IPC Command (IPC_CMD)—Offset 0h .....................................................3374
12.3.2 IPC Status (IPC_STS)—Offset 4h ...........................................................3375
12.3.3 IPC Source Pointer (IPC_SPTR)—Offset 8h ..............................................3376
12.3.4 IPC Destination Pointer (IPC_DPTR)—Offset Ch .......................................3377
12.3.5 IPC Write Buffer (IPC_WBUF0)—Offset 80h .............................................3377
12.3.6 IPC Write Buffer (IPC_WBUF1)—Offset 84h .............................................3378
12.3.7 IPC Write Buffer (IPC_WBUF2)—Offset 88h .............................................3378
12.3.8 IPC Write Buffer (IPC_WBUF3)—Offset 8Ch.............................................3379
12.3.9 IPC Read Buffer (IPC_RBUF0)—Offset 90h ..............................................3379
12.3.10IPC Read Buffer (IPC_RBUF1)—Offset 94h ..............................................3380
12.3.11IPC Read Buffer (IPC_RBUF2)—Offset 98h ..............................................3380
12.3.12IPC Read Buffer (IPC_RBUF3)—Offset 9Ch ..............................................3381
12.4 Registers Summary ........................................................................................3381
12.4.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3382
12.4.2 STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..3383
12.4.3 REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
3384
12.4.4 CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ...........................................................................................3384
12.4.5 BAR -Base Address Register (BAR)—Offset 10h .......................................3385
12.4.6 BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................3386
12.4.7 BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................3386
12.4.8 BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................3387
12.4.9 (BAR2)—Offset 20h ............................................................................3388
12.4.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................3388
12.4.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ......
3389
12.4.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h...........3389
12.4.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ............3390
12.4.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h.....
3391
12.4.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................3392
12.4.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset 90h
3392
12.4.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h 3393
12.4.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................3394
12.4.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................3394
12.4.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................3395
12.5 Registers Summary ........................................................................................3396
12.5.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3397
12.5.2 STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..3397
12.5.3 REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
3399

334818 85
 12.5.4 CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ........................................................................................... 3399
12.5.5 BAR -Base Address Register (BAR)—Offset 10h....................................... 3400
12.5.6 BAR -Base Address Register High (BAR_HIGH)—Offset 14h ...................... 3401
12.5.7 BAR1 -Base Address Register1 (BAR1)—Offset 18h ................................. 3401
12.5.8 BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ................. 3402
12.5.9 (BAR2)—Offset 20h............................................................................ 3403
12.5.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch .................................................................................................. 3403
12.5.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h .....
3404
12.5.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h .......... 3404
12.5.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ............ 3405
12.5.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h ....
3406
12.5.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h ............................................................ 3407
12.5.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset 90h
3407
12.5.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h 3408
12.5.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 3409
12.5.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 3409
12.5.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 3410
12.6 Registers Summary........................................................................................ 3411
12.6.1 PWM Control Register (PWMCTRL_0)—Offset 0h...................................... 3411
12.6.2 PWM D0i3 Control Register (PWMD0i3C)—Offset 100h ............................. 3412
12.6.3 PWM Control Register (PWMCTRL_1)—Offset 400h .................................. 3413
12.6.4 PWM Control Register (PWMCTRL_2)—Offset 800h .................................. 3414
12.6.5 PWM Control Register (PWMCTRL_3)—Offset C00h .................................. 3415
12.7 Registers Summary........................................................................................ 3416
12.7.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3417
12.7.2 STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h . 3418
12.7.3 REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h......
3419
12.7.4 CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ........................................................................................... 3420
12.7.5 BAR -Base Address Register (BAR)—Offset 10h....................................... 3420
12.7.6 BAR -Base Address Register High (BAR_HIGH)—Offset 14h ...................... 3421
12.7.7 BAR1 -Base Address Register1 (BAR1)—Offset 18h ................................. 3422
12.7.8 BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ................. 3422
12.7.9 (BAR2)—Offset 20h............................................................................ 3423
12.7.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch .................................................................................................. 3423
12.7.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h .....
3424
12.7.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h .......... 3425
12.7.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ............ 3425
12.7.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h ....
3426
12.7.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h ............................................................ 3427

86 334818
 12.7.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset 90h
3428
12.7.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h 3428
12.7.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................3429
12.7.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................3430
12.7.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................3430
12.8 Registers Summary ........................................................................................3431
12.8.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3432
12.8.2 STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..3433
12.8.3 REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
3434
12.8.4 CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ...........................................................................................3434
12.8.5 BAR -Base Address Register (BAR)—Offset 10h .......................................3435
12.8.6 BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................3436
12.8.7 BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................3436
12.8.8 BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................3437
12.8.9 (BAR2)—Offset 20h ............................................................................3438
12.8.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................3438
12.8.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ......
3439
12.8.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h...........3439
12.8.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ............3440
12.8.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h.....
3441
12.8.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................3442
12.8.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset 90h
3442
12.8.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h 3443
12.8.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................3444
12.8.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................3444
12.8.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................3445
12.9 Registers Summary ........................................................................................3446
12.9.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3447
12.9.2 STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..3447
12.9.3 REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
3449
12.9.4 CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ...........................................................................................3449
12.9.5 BAR -Base Address Register (BAR)—Offset 10h .......................................3450
12.9.6 BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................3451
12.9.7 BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................3451
12.9.8 BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................3452
12.9.9 (BAR2)—Offset 20h ............................................................................3453
12.9.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................3453

334818 87
 12.9.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h .....
3454
12.9.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h .......... 3454
12.9.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ............ 3455
12.9.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h ....
3456
12.9.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h ............................................................ 3457
12.9.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset 90h
3457
12.9.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h 3458
12.9.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 3459
12.9.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 3459
12.9.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 3460
12.10 Registers Summary........................................................................................ 3461
12.10.1DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3462
12.10.2STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h . 3462
12.10.3REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h......
3464
12.10.4CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ........................................................................................... 3464
12.10.5BAR -Base Address Register (BAR)—Offset 10h....................................... 3465
12.10.6BAR -Base Address Register High (BAR_HIGH)—Offset 14h ...................... 3466
12.10.7BAR1 -Base Address Register1 (BAR1)—Offset 18h ................................. 3466
12.10.8BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ................. 3467
12.10.9 (BAR2)—Offset 20h............................................................................ 3468
12.10.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch .................................................................................................. 3468
12.10.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ....
3469
12.10.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h......... 3469
12.10.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch .......... 3470
12.10.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h...
3471
12.10.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h ............................................................ 3472
12.10.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset
90h................................................................................................... 3472
12.10.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h .....
3473
12.10.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 3474
12.10.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 3474
12.10.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 3475
12.11 ................................................................................................................... 3476
12.12 Registers Summary........................................................................................ 3477
12.12.1Power Management 1 Status and Enable (PM1_STS_EN)—Offset 0h .......... 3477
12.12.2Power Management 1 Control (PM1_CNT)—Offset 4h ............................... 3482
12.12.3Power Management 1 Timer (PM1_TMR)—Offset 8h................................. 3483
12.12.4General Purpose Event 0 Status (GPE0a_STS)—Offset 20h ....................... 3483

88 334818
 12.12.5General Purpose Event 0 Status (GPE0b_STS)—Offset 24h .......................3487
12.12.6General Purpose Event 0 Status (GPE0c_STS)—Offset 28h........................3487
12.12.7General Purpose Event 0 Status (GPE0d_STS)—Offset 2Ch .......................3488
12.12.8General Purpose Event 0 Enables (GPE0a_EN)—Offset 30h .......................3488
12.12.9General Purpose Event 0 Enable (GPE0b_EN)—Offset 34h.........................3492
12.12.10General Purpose Event 0 Enable (GPE0c_EN)—Offset 38h........................3492
12.12.11General Purpose Event 0 Enable (GPE0d_EN)—Offset 3Ch .......................3493
12.12.12SMI Control and Enable (SMI_EN)—Offset 40h.......................................3493
12.12.13SMI Status Register (SMI_STS)—Offset 44h ..........................................3496
12.12.14Device Trap Status (DEVTRAP_STS)—Offset 4Ch....................................3500
12.12.15General Purpose Event Control (GPE_CTRL)—Offset 50h .........................3501
12.12.16TCO Reload Register (TCO_RLD)—Offset 60h.........................................3501
12.12.17TCO Timer Status (TCO_STS)—Offset 64h.............................................3502
12.12.18TCO Timer Control (TCO1_CNT)—Offset 68h..........................................3503
12.12.19TCO Timer Register (TCO_TMR)—Offset 70h ..........................................3503
12.12.20Advanced Power Management Status (APM_STS)—Offset 74h..................3504
12.12.21Advanced Power Management Control Port (APM_CNT)—Offset 78h ..........3505
12.12.22Direct IRQ Enables (DIRECT_IRQ_EN)—Offset 7Ch .................................3505
12.12.23PCI Configuration Control 1 Register(PCICFGCTR1)—Offset 200h..............3507
12.12.24PCI Configuration Control 2 Register(PCICFGCTR2)—Offset 204h..............3508
12.12.25PCI Configuration Control 3 Register(PCICFGCTR3)—Offset 208h..............3509
12.13 Registers Summary ........................................................................................3511
12.13.1Power and Reset Status (PRSTS)—Offset 1000h ......................................3511
12.13.2PM CFG - Power Management Configuration (PMC_CFG)—Offset 1008h ......3512
12.13.3Power Management Configuration (PMC_CFG2)—Offset 100Ch ..................3515
12.13.4SOC Power Management Status (SOC_PM_STS)—Offset 1010h .................3516
12.13.5General PM Configuration 1 (GEN_PMCON1)—Offset 1020h.......................3517
12.13.6General PM Configuration 2 (GEN_PMCON2)—Offset 1024h.......................3520
12.13.7General PM Configuration 3 (GEN_PMCON3)—Offset 1028h.......................3522
12.13.8Configured Revision ID (CRID)—Offset 1030h .........................................3524
12.13.9Function Disable 0 (FUNC_DIS_0)—Offset 1034h.....................................3525
12.13.10Function Disable 1 (FUNC_DIS_1)—Offset 1038h ...................................3527
12.13.11Extended Test Mode Register (ETR)—Offset 1048h .................................3528
12.13.12GPIO Group to General Purpose Event Register Configuration
(GPIO_GPE_CFG)—Offset 1050h ...........................................................3529
12.13.13IRQ Select 0 (IRQ_SEL_0)—Offset 1064h..............................................3531
12.13.14IRQ Select 1 (IRQ_SEL_1)—Offset 1068h..............................................3532
12.13.15IRQ Select 2 (IRQ_SEL_2)—Offset 106Ch..............................................3533
12.13.16Function ACPI Enumeration 0 (FUNC_ACPI_ENUM_0)—Offset 1070h .........3533
12.13.17Function ACPI Enumeration 1 (FUNC_ACPI_ENUM_1)—Offset 1074h .........3535
12.13.18Fixed Deep S0Ix Counter Lower 32 Bits (TELEM_DEEP_S0IX_LO_HOST)—Offset
1078h................................................................................................3536
12.13.19Fixed Deep S0Ix Counter Upper 32 Bits (TELEM_DEEP_S0IX_HI_HOST)—Offset
107Ch ...............................................................................................3537
12.13.20Fixed Shallow S0Ix Counter Lower 32 Bits
(TELEM_SHALLOW_S0IX_LO_HOST)—Offset 1080h .................................3537
12.13.21Fixed Shallow S0Ix Counter Upper 32 Bits (TELEM_SHALLOW_S0IX_HI_HOST)—
Offset 1084h ......................................................................................3538
12.13.22Reserved (TELEM_MISC_FIXED_LO_HOST)—Offset 1088h.......................3538
12.13.23Reserved register for sharing data with software upper 32 bits
(TELEM_MISC_FIXED_HI_HOST)—Offset 108Ch ......................................3539
12.13.24Scratchpad for sharing data between BIOS and PMC Firmware
(BIOS_SCRATCHPAD)—Offset 1090h .....................................................3540
12.13.25Display Hot Plug Detect Control (DISPLAY_HPD_CTL)—Offset 1094h.........3542
12.13.26OBFF Control and Status (OBFF_CTL_STS)—Offset 10C8h .......................3543

334818 89
 12.13.27Lock Register (LOCK)—Offset 10CCh.................................................... 3545
12.14 Registers Summary........................................................................................ 3549
12.14.1IPC Command (IPC_CMD)—Offset 0h .................................................... 3549
12.14.2IPC Status (IPC_STS)—Offset 4h .......................................................... 3550
12.14.3IPC Source Pointer (IPC_SPTR)—Offset 8h ............................................. 3551
12.14.4IPC Destination Pointer (IPC_DPTR)—Offset Ch ....................................... 3552
12.14.5IPC Write Buffer (IPC_WBUF0)—Offset 80h ............................................ 3552
12.14.6IPC Write Buffer (IPC_WBUF1)—Offset 84h ............................................ 3553
12.14.7IPC Write Buffer (IPC_WBUF2)—Offset 88h ............................................ 3553
12.14.8IPC Write Buffer (IPC_WBUF3)—Offset 8Ch ............................................ 3554
12.14.9IPC Read Buffer (IPC_RBUF0)—Offset 90h.............................................. 3554
12.14.10IPC Read Buffer (IPC_RBUF1)—Offset 94h ............................................ 3555
12.14.11IPC Read Buffer (IPC_RBUF2)—Offset 98h ............................................ 3555
12.14.12IPC Read Buffer (IPC_RBUF3)—Offset 9Ch ............................................ 3556
12.15 Registers Summary........................................................................................ 3557
12.15.1DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3557
12.15.2STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h . 3558
12.15.3REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h......
3559
12.15.4CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ........................................................................................... 3560
12.15.5BAR -Base Address Register (BAR)—Offset 10h....................................... 3560
12.15.6BAR -Base Address Register High (BAR_HIGH)—Offset 14h ...................... 3561
12.15.7BAR1 -Base Address Register1 (BAR1)—Offset 18h ................................. 3562
12.15.8BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ................. 3562
12.15.9 (BAR2)—Offset 20h............................................................................ 3563
12.15.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch .................................................................................................. 3563
12.15.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ....
3564
12.15.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h......... 3565
12.15.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch .......... 3565
12.15.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h...
3566
12.15.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h ............................................................ 3567
12.15.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset
90h................................................................................................... 3568
12.15.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h .....
3568
12.15.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 3569
12.15.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 3570
12.15.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 3570
12.16 Registers Summary........................................................................................ 3573
12.16.1DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3573
12.16.2STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h . 3574
12.16.3REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h......
3575
12.16.4CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ........................................................................................... 3576
12.16.5BAR -Base Address Register (BAR)—Offset 10h....................................... 3576

90 334818
 12.16.6BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................3577
12.16.7BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................3578
12.16.8BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................3578
12.16.9 (BAR2)—Offset 20h ............................................................................3579
12.16.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................3579
12.16.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h.....
3580
12.16.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h .........3581
12.16.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ...........3581
12.16.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h ...
3582
12.16.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................3583
12.16.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset
90h ...................................................................................................3584
12.16.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h ......
3584
12.16.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................3585
12.16.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................3586
12.16.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................3586
12.17 Registers Summary ........................................................................................3589
12.17.1PWM Control Register (PWMCTRL_0)—Offset 0h ......................................3589
12.17.2PWM D0i3 Control Register (PWMD0i3C)—Offset 100h..............................3590
12.17.3PWM Control Register (PWMCTRL_1)—Offset 400h...................................3591
12.17.4PWM Control Register (PWMCTRL_2)—Offset 800h...................................3592
12.17.5PWM Control Register (PWMCTRL_3)—Offset C00h...................................3593
12.18 Registers Summary ........................................................................................3595
12.18.1DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3595
12.18.2STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..3596
12.18.3REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
3597
12.18.4CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ...........................................................................................3598
12.18.5BAR -Base Address Register (BAR)—Offset 10h .......................................3598
12.18.6BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................3599
12.18.7BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................3600
12.18.8BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................3600
12.18.9 (BAR2)—Offset 20h ............................................................................3601
12.18.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................3601
12.18.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h.....
3602
12.18.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h .........3603
12.18.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ...........3603
12.18.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h ...
3604
12.18.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................3605
12.18.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset
90h ...................................................................................................3606

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 12.18.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h .....
3606
12.18.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 3607
12.18.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 3608
12.18.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 3608
12.19 Registers Summary........................................................................................ 3611
12.19.1DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3611
12.19.2STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h . 3612
12.19.3REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h......
3613
12.19.4CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ........................................................................................... 3614
12.19.5BAR -Base Address Register (BAR)—Offset 10h....................................... 3614
12.19.6BAR -Base Address Register High (BAR_HIGH)—Offset 14h ...................... 3615
12.19.7BAR1 -Base Address Register1 (BAR1)—Offset 18h ................................. 3616
12.19.8BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ................. 3616
12.19.9 (BAR2)—Offset 20h............................................................................ 3617
12.19.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch .................................................................................................. 3617
12.19.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ....
3618
12.19.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h......... 3619
12.19.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch .......... 3619
12.19.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h...
3620
12.19.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h ............................................................ 3621
12.19.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset
90h................................................................................................... 3622
12.19.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h .....
3622
12.19.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 3623
12.19.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 3624
12.19.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 3624
12.20 Registers Summary........................................................................................ 3627
12.20.1DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3627
12.20.2STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h . 3628
12.20.3REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h......
3629
12.20.4CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ........................................................................................... 3630
12.20.5BAR -Base Address Register (BAR)—Offset 10h....................................... 3630
12.20.6BAR -Base Address Register High (BAR_HIGH)—Offset 14h ...................... 3631
12.20.7BAR1 -Base Address Register1 (BAR1)—Offset 18h ................................. 3632
12.20.8BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ................. 3632
12.20.9 (BAR2)—Offset 20h............................................................................ 3633
12.20.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch .................................................................................................. 3633

92 334818
 12.20.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h.....
3634
12.20.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h .........3635
12.20.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ...........3635
12.20.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h ...
3636
12.20.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................3637
12.20.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset
90h ...................................................................................................3638
12.20.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h ......
3638
12.20.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................3639
12.20.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................3640
12.20.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................3640
12.21 Registers Summary ........................................................................................3643
12.21.1DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3643
12.21.2STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..3644
12.21.3REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
3645
12.21.4CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ...........................................................................................3646
12.21.5BAR -Base Address Register (BAR)—Offset 10h .......................................3646
12.21.6BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................3647
12.21.7BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................3648
12.21.8BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................3648
12.21.9 (BAR2)—Offset 20h ............................................................................3649
12.21.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................3649
12.21.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h.....
3650
12.21.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h .........3651
12.21.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ...........3651
12.21.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h ...
3652
12.21.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................3653
12.21.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset
90h ...................................................................................................3654
12.21.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h ......
3654
12.21.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................3655
12.21.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................3656
12.21.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................3656
13 Power Management Controller (P-Unit) ................................................................3659
13.1 Registers Summary ........................................................................................3659
13.1.1 Device Enable Register (P_CR_DEVEN_0_0_0_PCI)—Offset 54h.................3659
13.1.2 Capability ID0 A (P_CR_CAPID0_A_0_0_0_PCI)—Offset E4h .....................3660
13.1.3 Capability ID0 B (P_CR_CAPID0_B_0_0_0_PCI)—Offset E8h .....................3662

334818 93
 13.2 Registers Summary........................................................................................ 3663
13.2.1 Device ID and Vendor ID Register (P_CR_DEVICE_ID_VENDOR_ID_0_0_1_PCI)—
Offset 0h ........................................................................................... 3664
13.2.2 PCI_STATUS_COMMAND_0_0_1_PCI
(P_CR_PCI_STATUS_COMMAND_0_0_1_PCI)—Offset 4h .......................... 3664
13.2.3 PCI Revision ID and PCI Class Code Register
(P_CR_REVISION_ID_CLASS_CODE_0_0_1_PCI)—Offset 8h .................... 3666
13.2.4 Master Latency Timer and Header Type Register
(P_CR_MASTER_LATENCY_TIME_0_0_1_PCI)—Offset Ch ......................... 3667
13.2.5 Thermal Management Base Address Register (P_CR_TMBAR_LO_0_0_1_PCI)—
Offset 10h ......................................................................................... 3668
13.2.6 Thermal Management Base Address Register (P_CR_TMBAR_HI_0_0_1_PCI)—
Offset 14h ......................................................................................... 3669
13.2.7 PCI Subsystem Vendor ID and PCI Subsystem ID
(P_CR_SVID_SID_0_0_1_PCI)—Offset 2Ch ............................................ 3669
13.2.8 CAPPTR_0_0_1_PCI (P_CR_CAPPTR_0_0_1_PCI)—Offset 34h ................... 3670
13.2.9 Interrupt and Latency Configuration (P_CR_INTR_LAT_0_0_1_PCI)—Offset 3Ch.
3671
13.2.10Device Enable Register (P_CR_DEVEN_0_0_1_PCI)—Offset 54h ................ 3671
13.2.11SCISTS_0_0_1_PCI (P_CR_SCISTS_0_0_1_PCI)—Offset 88h ................... 3672
13.2.12SCI Command (P_CR_SCICMD_0_0_1_PCI)—Offset CCh.......................... 3673
13.2.13Power Management Capabilities (P_CR_PMCAPID_0_0_1_PCI)—Offset D0h 3674
13.2.14Power Management Control and Status (P_CR_PMCS_0_0_1_PCI)—Offset D4h ..
3675
13.2.15Interrupt Status (P_CR_INTSTS_0_0_1_PCI)—Offset DCh ........................ 3676
13.2.16Capability ID0 Capability Control (P_CR_CAPID0_CAPCTRL0_0_0_1_PCI)—Offset
E0h................................................................................................... 3677
13.2.17Capability ID0 A (P_CR_CAPID0_A_0_0_1_PCI)—Offset E4h..................... 3677
13.2.18Capability ID0 B (P_CR_CAPID0_B_0_0_1_PCI)—Offset E8h..................... 3679
13.3 Registers Summary........................................................................................ 3680
13.3.1 GT_SLICE_INFO (P_CR_GT_SLICE_INFO_0_2_0_GTTMMADR)—Offset 8064h ....
3682
13.3.2 GT Hardware P-state Control Request
(P_CR_GT_HWP_REQ_0_2_0_GTTMMADR)—Offset 8068h........................ 3683
13.3.3 GT_MEM_BOUND_COUNTER_0_2_0_GTTMMADR
(P_CR_GT_MEM_BOUND_COUNTER_0_2_0_GTTMMADR)—Offset 8070h .... 3684
13.3.4 GT_SQ_OCCUPANCY_0_2_0_GTTMMADR
(P_CR_GT_SQ_OCCUPANCY_0_2_0_GTTMMADR)—Offset 8074h............... 3684
13.3.5 GT_RW_DRAM_0_2_0_GTTMMADR (P_CR_GT_RW_DRAM_0_2_0_GTTMMADR)—
Offset 8078h ...................................................................................... 3685
13.3.6 GT_P_REQ (P_CR_GT_THREAD_P_REQ_0_2_0_GTTMMADR)—Offset 807Ch 3685
13.3.7 GT_ARAT_TTT (P_CR_GT_ARAT_TTT_0_2_0_GTTMMADR)—Offset 8080h ... 3686
13.3.8 GTC6_PREWAKE_TIMER_0_2_0_GTTMMADR
(P_CR_GTC6_PREWAKE_TIMER_0_2_0_GTTMMADR)—Offset 8088h .......... 3687
13.3.9 GT_DISP_PWRON_0_2_0_GTTMMADR
(P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR)—Offset 8090h................... 3688
13.3.10GT_GFX_RC6_0_2_0_GTTMMADR (P_CR_GT_GFX_RC6_0_2_0_GTTMMADR)—
Offset 8108h ...................................................................................... 3688
13.3.11GTDRIVER_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_INTERFACE_0_2_0_GTTMMADR)—Offset 8124h ....
3689
13.3.12GTDRIVER_MAILBOX_DATA_LOW_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_DATA_LOW_0_2_0_GTTMMADR)—Offset 8128h....
3690
13.3.13GTDRIVER_MAILBOX_DATA_HIGH_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_DATA_HIGH_0_2_0_GTTMMADR)—Offset 812Ch...
3690

94 334818
 13.3.14P24C_PCODE_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_P24C_PCODE_MAILBOX_INTERFACE_0_2_0_GTTMMADR)—Offset 8130h
3691
13.3.15P24C_PCODE_MAILBOX_DATA_0_2_0_GTTMMADR
(P_CR_P24C_PCODE_MAILBOX_DATA_0_2_0_GTTMMADR)—Offset 8134h..3692
13.3.16PCODE_P24C_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_PCODE_P24C_MAILBOX_INTERFACE_0_2_0_GTTMMADR)—Offset 8138h
3692
13.3.17PCODE_P24C_MAILBOX_DATA_0_2_0_GTTMMADR
(P_CR_PCODE_P24C_MAILBOX_DATA_0_2_0_GTTMMADR)—Offset 813Ch .3693
13.3.18GT_PM_CONFIG_0_2_0_GTTMMADR
(P_CR_GT_PM_CONFIG_0_2_0_GTTMMADR)—Offset 8140h......................3694
13.3.19Graphics Interrupt Response Latency Tolerance
(P_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_0_2_0_GTTMMADR)—Offset
8150h................................................................................................3694
13.3.20GTDRIVER_P2G_EVENTS_0_2_0_GTTMMADR
(P_CR_GTDRIVER_P2G_EVENTS_0_2_0_GTTMMADR)—Offset 8160h .........3695
13.3.21GTDRIVER_G2P_EVENTS_0_2_0_GTTMMADR
(P_CR_GTDRIVER_G2P_EVENTS_0_2_0_GTTMMADR)—Offset 8164h .........3696
13.3.22CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_CORE_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—Offset 816Ch ...
3697
13.3.23GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_GRAPHICS_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—Offset
8170h................................................................................................3698
13.3.24SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—
Offset 8174h ......................................................................................3699
13.3.25Memory Frequency Status
(P_CR_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—Offset
8178h................................................................................................3700
13.3.26GT_PERF_LIMIT_REASONS
(P_CR_GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR)—Offset 8184h.......3701
13.3.27GTDRIVER_HWP_REQUEST_0_2_0_GTTMMADR
(P_CR_GTDRIVER_HWP_REQUEST_0_2_0_GTTMMADR)—Offset 8190h ......3703
13.3.28ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR
(P_CR_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_2_0_GTTMMADR)—
Offset 8198h ......................................................................................3704
13.3.29GT_VIDEO_BUSYNESS_0_2_0_GTTMMADR
(P_CR_GT_VIDEO_BUSYNESS_0_2_0_GTTMMADR)—Offset 819Ch ............3705
13.4 Registers Summary ........................................................................................3706
13.4.1 ISPDRIVER_MAILBOX_INTERFACE_0_0_0_MCHBAR
(P_CR_ISPDRIVER_MAILBOX_INTERFACE_0_0_0_MCHBAR)—Offset 7480h.3707
13.4.2 ISPDRIVER_MAILBOX_DATA_LOW_0_0_0_MCHBAR
(P_CR_ISPDRIVER_MAILBOX_DATA_LOW_0_0_0_MCHBAR)—Offset 7484h.3708
13.4.3 ISPDRIVER_MAILBOX_DATA_HIGH_0_0_0_MCHBAR
(P_CR_ISPDRIVER_MAILBOX_DATA_HIGH_0_0_0_MCHBAR)—Offset 7488h3708
13.4.4 ISPDRIVER_P2I_EVENTS_0_0_0_MCHBAR
(P_CR_ISPDRIVER_P2I_EVENTS_0_0_0_MCHBAR)—Offset 748Ch .............3709
13.4.5 ISPDRIVER_I2P_EVENTS_0_0_0_MCHBAR
(P_CR_ISPDRIVER_I2P_EVENTS_0_0_0_MCHBAR)—Offset 7490h..............3710
13.4.6 ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBA
R)—Offset 7498h ................................................................................3711
13.4.7 ISPDRIVER_HWP_REQUEST_0_0_0_MCHBAR
(P_CR_ISPDRIVER_HWP_REQUEST_0_0_0_MCHBAR)—Offset 74A0h .........3712
13.4.8 ISPDRIVER_SPARE_RW_0_0_0_MCHBAR
(P_CR_ISPDRIVER_SPARE_RW_0_0_0_MCHBAR)—Offset 74A8h ...............3713

334818 95
 13.4.9 ISPDRIVER_SPARE_RO_0_0_0_MCHBAR
(P_CR_ISPDRIVER_SPARE_RO_0_0_0_MCHBAR)—Offset 74ACh ............... 3713
13.4.10CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset
74B0h ............................................................................................... 3714
13.4.11GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—
Offset 74B4h...................................................................................... 3715
13.4.12SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHB
AR)—Offset 74B8h .............................................................................. 3715
13.4.13Memory Frequency Status
(P_CR_ISPDRIVER_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
)—Offset 74BCh.................................................................................. 3716
13.4.14ISP_PERF_LIMIT_REASONS
(P_CR_ISPDRIVER_ISP_PERF_LIMIT_REASONS_0_0_0_MCHBAR)—Offset 74CCh
3717
13.4.15I-unit Processing System C0 Residency Counter
(P_CR_ISPDRIVER_TELEM_IUNIT_C0_RESIDENCY_0_0_0_MCHBAR)—Offset
74D0h............................................................................................... 3720
13.4.16I-unit Processing System C0 Residency Counter
(P_CR_ISPDRIVER_TELEM_IUNIT_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—
Offset 74D4h ..................................................................................... 3720
13.5 ................................................................................................................... 3721
13.6 Registers Summary........................................................................................ 3723
13.6.1 Device Enable Register (P_CR_DEVEN_0_0_0_PCI)—Offset 54h ................ 3723
13.6.2 Capability ID0 A (P_CR_CAPID0_A_0_0_0_PCI)—Offset E4h..................... 3724
13.6.3 Capability ID0 B (P_CR_CAPID0_B_0_0_0_PCI)—Offset E8h..................... 3726
13.7 Registers Summary........................................................................................ 3727
13.7.1 Device ID and Vendor ID Register (P_CR_DEVICE_ID_VENDOR_ID_0_0_1_PCI)—
Offset 0h ........................................................................................... 3727
13.7.2 PCI_STATUS_COMMAND_0_0_1_PCI
(P_CR_PCI_STATUS_COMMAND_0_0_1_PCI)—Offset 4h .......................... 3728
13.7.3 PCI Revision ID and PCI Class Code Register
(P_CR_REVISION_ID_CLASS_CODE_0_0_1_PCI)—Offset 8h .................... 3730
13.7.4 Master Latency Timer and Header Type Register
(P_CR_MASTER_LATENCY_TIME_0_0_1_PCI)—Offset Ch ......................... 3731
13.7.5 Thermal Management Base Address Register (P_CR_TMBAR_LO_0_0_1_PCI)—
Offset 10h ......................................................................................... 3732
13.7.6 Thermal Management Base Address Register (P_CR_TMBAR_HI_0_0_1_PCI)—
Offset 14h ......................................................................................... 3732
13.7.7 PCI Subsystem Vendor ID and PCI Subsystem ID
(P_CR_SVID_SID_0_0_1_PCI)—Offset 2Ch ............................................ 3733
13.7.8 CAPPTR_0_0_1_PCI (P_CR_CAPPTR_0_0_1_PCI)—Offset 34h ................... 3734
13.7.9 Interrupt and Latency Configuration (P_CR_INTR_LAT_0_0_1_PCI)—Offset 3Ch.
3734
13.7.10Device Enable Register (P_CR_DEVEN_0_0_1_PCI)—Offset 54h ................ 3735
13.7.11SCISTS_0_0_1_PCI (P_CR_SCISTS_0_0_1_PCI)—Offset 88h ................... 3736
13.7.12SCI Command (P_CR_SCICMD_0_0_1_PCI)—Offset CCh.......................... 3737
13.7.13Power Management Capabilities (P_CR_PMCAPID_0_0_1_PCI)—Offset D0h 3737
13.7.14Power Management Control and Status (P_CR_PMCS_0_0_1_PCI)—Offset D4h ..
3738
13.7.15Interrupt Status (P_CR_INTSTS_0_0_1_PCI)—Offset DCh ........................ 3740
13.7.16Capability ID0 Capability Control (P_CR_CAPID0_CAPCTRL0_0_0_1_PCI)—Offset
E0h................................................................................................... 3741
13.7.17Capability ID0 A (P_CR_CAPID0_A_0_0_1_PCI)—Offset E4h..................... 3741
13.7.18Capability ID0 B (P_CR_CAPID0_B_0_0_1_PCI)—Offset E8h..................... 3743

96 334818
 13.8 Registers Summary ........................................................................................3745
13.8.1 GT_SLICE_INFO (P_CR_GT_SLICE_INFO_0_2_0_GTTMMADR)—Offset 8064h .....
3746
13.8.2 GT Hardware P-state Control Request
(P_CR_GT_HWP_REQ_0_2_0_GTTMMADR)—Offset 8068h ........................3747
13.8.3 GT_MEM_BOUND_COUNTER_0_2_0_GTTMMADR
(P_CR_GT_MEM_BOUND_COUNTER_0_2_0_GTTMMADR)—Offset 8070h.....3748
13.8.4 GT_SQ_OCCUPANCY_0_2_0_GTTMMADR
(P_CR_GT_SQ_OCCUPANCY_0_2_0_GTTMMADR)—Offset 8074h ...............3748
13.8.5 GT_RW_DRAM_0_2_0_GTTMMADR (P_CR_GT_RW_DRAM_0_2_0_GTTMMADR)—
Offset 8078h ......................................................................................3749
13.8.6 GT_P_REQ (P_CR_GT_THREAD_P_REQ_0_2_0_GTTMMADR)—Offset 807Ch 3749
13.8.7 GT_ARAT_TTT (P_CR_GT_ARAT_TTT_0_2_0_GTTMMADR)—Offset 8080h ...3750
13.8.8 GTC6_PREWAKE_TIMER_0_2_0_GTTMMADR
(P_CR_GTC6_PREWAKE_TIMER_0_2_0_GTTMMADR)—Offset 8088h...........3751
13.8.9 GT_DISP_PWRON_0_2_0_GTTMMADR
(P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR)—Offset 8090h ...................3752
13.8.10GT_GFX_RC6_0_2_0_GTTMMADR (P_CR_GT_GFX_RC6_0_2_0_GTTMMADR)—
Offset 8108h ......................................................................................3752
13.8.11GTDRIVER_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_INTERFACE_0_2_0_GTTMMADR)—Offset 8124h ....
3753
13.8.12GTDRIVER_MAILBOX_DATA_LOW_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_DATA_LOW_0_2_0_GTTMMADR)—Offset 8128h ....
3754
13.8.13GTDRIVER_MAILBOX_DATA_HIGH_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_DATA_HIGH_0_2_0_GTTMMADR)—Offset 812Ch ...
3754
13.8.14P24C_PCODE_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_P24C_PCODE_MAILBOX_INTERFACE_0_2_0_GTTMMADR)—Offset 8130h
3755
13.8.15P24C_PCODE_MAILBOX_DATA_0_2_0_GTTMMADR
(P_CR_P24C_PCODE_MAILBOX_DATA_0_2_0_GTTMMADR)—Offset 8134h..3756
13.8.16PCODE_P24C_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_PCODE_P24C_MAILBOX_INTERFACE_0_2_0_GTTMMADR)—Offset 8138h
3756
13.8.17PCODE_P24C_MAILBOX_DATA_0_2_0_GTTMMADR
(P_CR_PCODE_P24C_MAILBOX_DATA_0_2_0_GTTMMADR)—Offset 813Ch .3757
13.8.18GT_PM_CONFIG_0_2_0_GTTMMADR
(P_CR_GT_PM_CONFIG_0_2_0_GTTMMADR)—Offset 8140h......................3758
13.8.19Graphics Interrupt Response Latency Tolerance
(P_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_0_2_0_GTTMMADR)—Offset
8150h................................................................................................3758
13.8.20GTDRIVER_P2G_EVENTS_0_2_0_GTTMMADR
(P_CR_GTDRIVER_P2G_EVENTS_0_2_0_GTTMMADR)—Offset 8160h .........3759
13.8.21GTDRIVER_G2P_EVENTS_0_2_0_GTTMMADR
(P_CR_GTDRIVER_G2P_EVENTS_0_2_0_GTTMMADR)—Offset 8164h .........3760
13.8.22CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_CORE_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—Offset 816Ch ...
3761
13.8.23GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_GRAPHICS_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—Offset
8170h................................................................................................3762
13.8.24SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—
Offset 8174h ......................................................................................3763

334818 97
 13.8.25Memory Frequency Status
(P_CR_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—Offset
8178h ............................................................................................... 3764
13.8.26GT_PERF_LIMIT_REASONS
(P_CR_GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR)—Offset 8184h ...... 3765
13.8.27GTDRIVER_HWP_REQUEST_0_2_0_GTTMMADR
(P_CR_GTDRIVER_HWP_REQUEST_0_2_0_GTTMMADR)—Offset 8190h...... 3768
13.8.28ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR
(P_CR_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_2_0_GTTMMADR)—
Offset 8198h ...................................................................................... 3769
13.8.29GT_VIDEO_BUSYNESS_0_2_0_GTTMMADR
(P_CR_GT_VIDEO_BUSYNESS_0_2_0_GTTMMADR)—Offset 819Ch............ 3770
13.9 Registers Summary........................................................................................ 3773
13.9.1 ISPDRIVER_MAILBOX_INTERFACE_0_0_0_MCHBAR
(P_CR_ISPDRIVER_MAILBOX_INTERFACE_0_0_0_MCHBAR)—Offset 7480h 3774
13.9.2 ISPDRIVER_MAILBOX_DATA_LOW_0_0_0_MCHBAR
(P_CR_ISPDRIVER_MAILBOX_DATA_LOW_0_0_0_MCHBAR)—Offset 7484h 3774
13.9.3 ISPDRIVER_MAILBOX_DATA_HIGH_0_0_0_MCHBAR
(P_CR_ISPDRIVER_MAILBOX_DATA_HIGH_0_0_0_MCHBAR)—Offset 7488h3775
13.9.4 ISPDRIVER_P2I_EVENTS_0_0_0_MCHBAR
(P_CR_ISPDRIVER_P2I_EVENTS_0_0_0_MCHBAR)—Offset 748Ch ............. 3776
13.9.5 ISPDRIVER_I2P_EVENTS_0_0_0_MCHBAR
(P_CR_ISPDRIVER_I2P_EVENTS_0_0_0_MCHBAR)—Offset 7490h ............. 3777
13.9.6 ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBA
R)—Offset 7498h ................................................................................ 3777
13.9.7 ISPDRIVER_HWP_REQUEST_0_0_0_MCHBAR
(P_CR_ISPDRIVER_HWP_REQUEST_0_0_0_MCHBAR)—Offset 74A0h ......... 3779
13.9.8 ISPDRIVER_SPARE_RW_0_0_0_MCHBAR
(P_CR_ISPDRIVER_SPARE_RW_0_0_0_MCHBAR)—Offset 74A8h............... 3780
13.9.9 ISPDRIVER_SPARE_RO_0_0_0_MCHBAR
(P_CR_ISPDRIVER_SPARE_RO_0_0_0_MCHBAR)—Offset 74ACh ............... 3780
13.9.10CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset
74B0h ............................................................................................... 3781
13.9.11GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—
Offset 74B4h...................................................................................... 3782
13.9.12SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHB
AR)—Offset 74B8h .............................................................................. 3782
13.9.13Memory Frequency Status
(P_CR_ISPDRIVER_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
)—Offset 74BCh.................................................................................. 3783
13.9.14ISP_PERF_LIMIT_REASONS
(P_CR_ISPDRIVER_ISP_PERF_LIMIT_REASONS_0_0_0_MCHBAR)—Offset 74CCh
3784
13.9.15I-unit Processing System C0 Residency Counter
(P_CR_ISPDRIVER_TELEM_IUNIT_C0_RESIDENCY_0_0_0_MCHBAR)—Offset
74D0h............................................................................................... 3787
13.9.16I-unit Processing System C0 Residency Counter
(P_CR_ISPDRIVER_TELEM_IUNIT_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—
Offset 74D4h ..................................................................................... 3787
14 ITSS..................................................................................................................... 3789
14.1 Registers Summary........................................................................................ 3789
14.1.1 Version (VS)—Offset 1h ....................................................................... 3792
14.1.2 Redirection Table Entry 0 (RTE0)—Offset 10h ......................................... 3793

98 334818
 14.1.3 Redirection Table Entry 1 (RTE1)—Offset 12h..........................................3794
14.1.4 Redirection Table Entry 2 (RTE2)—Offset 14h..........................................3795
14.1.5 Redirection Table Entry 3 (RTE3)—Offset 16h..........................................3797
14.1.6 Redirection Table Entry 4 (RTE4)—Offset 18h..........................................3798
14.1.7 Redirection Table Entry 5 (RTE5)—Offset 1Ah..........................................3799
14.1.8 Redirection Table Entry 6 (RTE6)—Offset 1Ch .........................................3800
14.1.9 Redirection Table Entry 7 (RTE7)—Offset 1Eh..........................................3801
14.1.10Redirection Table Entry 8 (RTE8)—Offset 20h..........................................3802
14.1.11Redirection Table Entry 9 (RTE9)—Offset 22h..........................................3804
14.1.12Redirection Table Entry 10 (RTE10)—Offset 24h ......................................3805
14.1.13Redirection Table Entry 11 (RTE11)—Offset 26h ......................................3806
14.1.14Redirection Table Entry 12 (RTE12)—Offset 28h ......................................3807
14.1.15Redirection Table Entry 13 (RTE13)—Offset 2Ah ......................................3808
14.1.16Redirection Table Entry 14 (RTE14)—Offset 2Ch ......................................3809
14.1.17Redirection Table Entry 15 (RTE15)—Offset 2Eh ......................................3811
14.1.18Redirection Table Entry 16 (RTE16)—Offset 30h ......................................3812
14.1.19Redirection Table Entry 17 (RTE17)—Offset 32h ......................................3813
14.1.20Redirection Table Entry 18 (RTE18)—Offset 34h ......................................3814
14.1.21Redirection Table Entry 19 (RTE19)—Offset 36h ......................................3815
14.1.22Redirection Table Entry 20 (RTE20)—Offset 38h ......................................3816
14.1.23Redirection Table Entry 21 (RTE21)—Offset 3Ah ......................................3818
14.1.24Redirection Table Entry 22 (RTE22)—Offset 3Ch ......................................3819
14.1.25Redirection Table Entry 23 (RTE23)—Offset 3Eh ......................................3820
14.1.26Redirection Table Entry 24 (RTE24)—Offset 40h ......................................3821
14.1.27Redirection Table Entry 25 (RTE25)—Offset 42h ......................................3822
14.1.28Redirection Table Entry 26 (RTE26)—Offset 44h ......................................3823
14.1.29Redirection Table Entry 27 (RTE27)—Offset 46h ......................................3825
14.1.30Redirection Table Entry 28 (RTE28)—Offset 48h ......................................3826
14.1.31Redirection Table Entry 29 (RTE29)—Offset 4Ah ......................................3827
14.1.32Redirection Table Entry 30 (RTE30)—Offset 4Ch ......................................3828
14.1.33Redirection Table Entry 31 (RTE31)—Offset 4Eh ......................................3829
14.1.34Redirection Table Entry 32 (RTE32)—Offset 50h ......................................3830
14.1.35Redirection Table Entry 33 (RTE33)—Offset 52h ......................................3832
14.1.36Redirection Table Entry 34 (RTE34)—Offset 54h ......................................3833
14.1.37Redirection Table Entry 35 (RTE35)—Offset 56h ......................................3834
14.1.38Redirection Table Entry 36 (RTE36)—Offset 58h ......................................3835
14.1.39Redirection Table Entry 37 (RTE37)—Offset 5Ah ......................................3836
14.1.40Redirection Table Entry 38 (RTE38)—Offset 5Ch ......................................3837
14.1.41Redirection Table Entry 39 (RTE39)—Offset 5Eh ......................................3839
14.1.42Redirection Table Entry 40 (RTE40)—Offset 60h ......................................3840
14.1.43Redirection Table Entry 41 (RTE41)—Offset 62h ......................................3841
14.1.44Redirection Table Entry 42 (RTE42)—Offset 64h ......................................3842
14.1.45Redirection Table Entry 43 (RTE43)—Offset 66h ......................................3843
14.1.46Redirection Table Entry 44 (RTE44)—Offset 68h ......................................3844
14.1.47Redirection Table Entry 45 (RTE45)—Offset 6Ah ......................................3846
14.1.48Redirection Table Entry 46 (RTE46)—Offset 6Ch ......................................3847
14.1.49Redirection Table Entry 47 (RTE47)—Offset 6Eh ......................................3848
14.1.50Redirection Table Entry 48 (RTE48)—Offset 70h ......................................3849
14.1.51Redirection Table Entry 49 (RTE49)—Offset 72h ......................................3850
14.1.52Redirection Table Entry 50 (RTE50)—Offset 74h ......................................3851
14.1.53Redirection Table Entry 51 (RTE51)—Offset 76h ......................................3853
14.1.54Redirection Table Entry 52 (RTE52)—Offset 78h ......................................3854
14.1.55Redirection Table Entry 53 (RTE53)—Offset 7Ah ......................................3855
14.1.56Redirection Table Entry 54 (RTE54)—Offset 7Ch ......................................3856
14.1.57Redirection Table Entry 55 (RTE55)—Offset 7Eh ......................................3857

334818 99
 14.1.58Redirection Table Entry 56 (RTE56)—Offset 80h...................................... 3858
14.1.59Redirection Table Entry 57 (RTE57)—Offset 82h...................................... 3860
14.1.60Redirection Table Entry 58 (RTE58)—Offset 84h...................................... 3861
14.1.61Redirection Table Entry 59 (RTE59)—Offset 86h...................................... 3862
14.1.62Redirection Table Entry 60 (RTE60)—Offset 88h...................................... 3863
14.1.63Redirection Table Entry 61 (RTE61)—Offset 8Ah ..................................... 3864
14.1.64Redirection Table Entry 62 (RTE62)—Offset 8Ch ..................................... 3865
14.1.65Redirection Table Entry 63 (RTE63)—Offset 8Eh...................................... 3867
14.1.66Redirection Table Entry 64 (RTE64)—Offset 90h...................................... 3868
14.1.67Redirection Table Entry 65 (RTE65)—Offset 92h...................................... 3869
14.1.68Redirection Table Entry 66 (RTE66)—Offset 94h...................................... 3870
14.1.69Redirection Table Entry 67 (RTE67)—Offset 96h...................................... 3871
14.1.70Redirection Table Entry 68 (RTE68)—Offset 98h...................................... 3872
14.1.71Redirection Table Entry 69 (RTE69)—Offset 9Ah ..................................... 3874
14.1.72Redirection Table Entry 70 (RTE70)—Offset 9Ch ..................................... 3875
14.1.73Redirection Table Entry 71 (RTE71)—Offset 9Eh...................................... 3876
14.1.74Redirection Table Entry 72 (RTE72)—Offset A0h ..................................... 3877
14.1.75Redirection Table Entry 73 (RTE73)—Offset A2h ..................................... 3878
14.1.76Redirection Table Entry 74 (RTE74)—Offset A4h ..................................... 3879
14.1.77Redirection Table Entry 75 (RTE75)—Offset A6h ..................................... 3881
14.1.78Redirection Table Entry 76 (RTE76)—Offset A8h ..................................... 3882
14.1.79Redirection Table Entry 77 (RTE77)—Offset AAh ..................................... 3883
14.1.80Redirection Table Entry 78 (RTE78)—Offset ACh ..................................... 3884
14.1.81Redirection Table Entry 79 (RTE79)—Offset AEh ..................................... 3885
14.1.82Redirection Table Entry 80 (RTE80)—Offset B0h ..................................... 3886
14.1.83Redirection Table Entry 81 (RTE81)—Offset B2h ..................................... 3888
14.1.84Redirection Table Entry 82 (RTE82)—Offset B4h ..................................... 3889
14.1.85Redirection Table Entry 83 (RTE83)—Offset B6h ..................................... 3890
14.1.86Redirection Table Entry 84 (RTE84)—Offset B8h ..................................... 3891
14.1.87Redirection Table Entry 85 (RTE85)—Offset BAh ..................................... 3892
14.1.88Redirection Table Entry 86 (RTE86)—Offset BCh ..................................... 3893
14.1.89Redirection Table Entry 87 (RTE87)—Offset BEh ..................................... 3895
14.1.90Redirection Table Entry 88 (RTE88)—Offset C0h ..................................... 3896
14.1.91Redirection Table Entry 89 (RTE89)—Offset C2h ..................................... 3897
14.1.92Redirection Table Entry 90 (RTE90)—Offset C4h ..................................... 3898
14.1.93Redirection Table Entry 91 (RTE91)—Offset C6h ..................................... 3899
14.1.94Redirection Table Entry 92 (RTE92)—Offset C8h ..................................... 3900
14.1.95Redirection Table Entry 93 (RTE93)—Offset CAh ..................................... 3902
14.1.96Redirection Table Entry 94 (RTE94)—Offset CCh ..................................... 3903
14.1.97Redirection Table Entry 95 (RTE95)—Offset CEh ..................................... 3904
14.1.98Redirection Table Entry 96 (RTE96)—Offset D0h ..................................... 3905
14.1.99Redirection Table Entry 97 (RTE97)—Offset D2h ..................................... 3906
14.1.100Redirection Table Entry 98 (RTE98)—Offset D4h.................................... 3907
14.1.101Redirection Table Entry 99 (RTE99)—Offset D6h.................................... 3909
14.1.102Redirection Table Entry 100 (RTE100)—Offset D8h ................................ 3910
14.1.103Redirection Table Entry 101 (RTE101)—Offset DAh ................................ 3911
14.1.104Redirection Table Entry 102 (RTE102)—Offset DCh ................................ 3912
14.1.105Redirection Table Entry 103 (RTE103)—Offset DEh ................................ 3913
14.1.106Redirection Table Entry 104 (RTE104)—Offset E0h................................. 3914
14.1.107Redirection Table Entry 105 (RTE105)—Offset E2h................................. 3916
14.1.108Redirection Table Entry 106 (RTE106)—Offset E4h................................. 3917
14.1.109Redirection Table Entry 107 (RTE107)—Offset E6h................................. 3918
14.1.110Redirection Table Entry 108 (RTE108)—Offset E8h................................. 3919
14.1.111Redirection Table Entry 109 (RTE109)—Offset EAh ................................ 3920
14.1.112Redirection Table Entry 110 (RTE110)—Offset ECh ................................ 3921

100 334818
 14.1.113Redirection Table Entry 111 (RTE111)—Offset EEh .................................3923
14.1.114Redirection Table Entry 112 (RTE112)—Offset F0h .................................3924
14.1.115Redirection Table Entry 113 (RTE113)—Offset F2h .................................3925
14.1.116Redirection Table Entry 114 (RTE114)—Offset F4h .................................3926
14.1.117Redirection Table Entry 115 (RTE115)—Offset F6h .................................3927
14.1.118Redirection Table Entry 116 (RTE116)—Offset F8h .................................3928
14.1.119Redirection Table Entry 117 (RTE117)—Offset FAh .................................3930
14.1.120Redirection Table Entry 118 (RTE118)—Offset FCh .................................3931
14.1.121Redirection Table Entry 119 (RTE119)—Offset FEh .................................3932
14.1.122PIRQA Routing Control (PARC)—Offset 3100h ........................................3933
14.1.123PIRQB Routing Control (PBRC)—Offset 3101h ........................................3934
14.1.124PIRQC Routing Control (PCRC)—Offset 3102h ........................................3934
14.1.125PIRQD Routing Control (PDRC)—Offset 3103h........................................3935
14.1.126PIRQE Routing Control (PERC)—Offset 3104h ........................................3936
14.1.127PIRQF Routing Control (PFRC)—Offset 3105h.........................................3936
14.1.128PIRQG Routing Control (PGRC)—Offset 3106h........................................3937
14.1.129PIRQH Routing Control (PHRC)—Offset 3107h........................................3938
14.1.130PCI Interrupt Route 0 (PIR0)—Offset 3140h ..........................................3938
14.1.131PCI Interrupt Route 1 (PIR1)—Offset 3142h ..........................................3939
14.1.132PCI Interrupt Route 2 (PIR2)—Offset 3144h ..........................................3940
14.1.133PCI Interrupt Route 3(PIR3)—Offset 3146h ...........................................3941
14.1.134PCI Interrupt Route 4 (PIR4)—Offset 3148h ..........................................3942
14.1.135PCI Interrupt Route 5 (PIR5)—Offset 314Ah ..........................................3943
14.1.136PCI Interrupt Route 6 (PIR6)—Offset 314Ch ..........................................3943
14.1.137PCI Interrupt Route 7 (PIR7)—Offset 314Eh ..........................................3944
14.1.138PCI Interrupt Route 8 (PIR8)—Offset 3150h ..........................................3945
14.1.139PCI Interrupt Route 9 (PIR9)—Offset 3152h ..........................................3946
14.1.140PCI Interrupt Route 10 (PIR10)—Offset 3154h .......................................3947
14.1.141PCI Interrupt Route 11 (PIR11)—Offset 3156h .......................................3948
14.1.142PCI Interrupt Route 12 (PIR12)—Offset 3158h .......................................3948
14.1.143Interrupt Polarity Control 0 (IPC0)—Offset 3200h...................................3949
14.1.144Interrupt Polarity Control 1 (IPC1)—Offset 3204h...................................3949
14.1.145Interrupt Polarity Control 2 (IPC2)—Offset 3208h...................................3950
14.1.146Interrupt Polarity Control 3 (IPC3)—Offset 320Ch...................................3950
14.1.147ITSS Power Reduction Control (ITSSPRC)—Offset 3300h .........................3951
14.1.148SIDE Clock Timing (SIDECT)—Offset 3304h...........................................3951
14.2 Registers Summary ........................................................................................3953
14.2.1 Index Register (IDX)—Offset FEC00000h ................................................3953
14.2.2 Window Register (WDW)—Offset FEC00010h...........................................3953
14.2.3 EOI Register (EOI)—Offset FEC00040h ...................................................3954
14.3 Registers Summary ........................................................................................3954
14.3.1 NMI Status and Control (NMI_STS_CNT)—Offset 61h ...............................3955
14.3.2 NMI Enable (and Real Time Clock Index) (NMI_EN)—Offset 70h ................3956
14.3.3 Init Register (PORT92)—Offset 92h........................................................3956
14.3.4 Reset Control Register (RST_CNT)—Offset CF9h ......................................3957
14.4 Registers Summary ........................................................................................3958
14.4.1 General Capabilities and ID Register (GEN_CAP_ID)—Offset FED00000h.....3959
14.4.2 General Config Register (GEN_CFG)—Offset FED00010h ...........................3960
14.4.3 Main Counter Value (MAIN_CNTR)—Offset FED000F0h .............................3961
14.4.4 Timer 0 Config and Capabilities (TMR0_CNF_CAP)—Offset FED00100h........3962
14.4.5 Timer 0 Comparator Value (TMR0_CMP_VAL)—Offset FED00108h ..............3965
14.4.6 Timer 0 FSB Interrupt Rout Register (TMR0_FSB_INT_ROUT)—Offset FED00110h
3966
14.4.7 Timer 1 Config and Capabilities (TMR1_CNF_CAP)—Offset FED00120h........3967
14.4.8 Timer 1 Comparator Value (TMR1_CMP_VAL)—Offset FED00128h ..............3970

334818 101
 14.4.9 Timer 1 FSB Interrupt Rout Register (TMR1_FSB_INT_ROUT)—Offset FED00130h
3971
14.4.10Timer 2 Config and Capabilities (TMR2_CNF_CAP)—Offset FED00140h ....... 3972
14.4.11Timer 2 Comparator Value (TMR2_CMP_VAL)—Offset FED00148h ............. 3975
14.4.12Timer 2 FSB Interrupt Rout Register (TMR2_FSB_INT_ROUT)—Offset FED00150h
3976
14.4.13Timer 3 Config and Capabilities (TMR3_CNF_CAP)—Offset FED00160h ....... 3977
14.4.14Timer 3 Comparator Value (TMR3_CMP_VAL)—Offset FED00168h ............. 3980
14.4.15Timer 3 FSB Interrupt Rout Register (TMR3_FSB_INT_ROUT)—Offset FED00170h
3981
14.4.16Timer 4 Config and Capabilities (TMR4_CNF_CAP)—Offset FED00180h ....... 3982
14.4.17Timer 4 Comparator Value (TMR4_CMP_VAL)—Offset FED00188h ............. 3985
14.4.18Timer 4 FSB Interrupt Rout Register (TMR4_FSB_INT_ROUT)—Offset FED00190h
3986
14.4.19Timer 5 Config and Capabilities (TMR5_CNF_CAP)—Offset FED001A0h ....... 3987
14.4.20Timer 5 Comparator Value (TMR5_CMP_VAL)—Offset FED001A8h ............. 3990
14.4.21Timer 5 FSB Interrupt Rout Register (TMR5_FSB_INT_ROUT)—Offset FED001B0h
3991
14.4.22Timer 6 Config and Capabilities (TMR6_CNF_CAP)—Offset FED001C0h ....... 3992
14.4.23Timer 6 Comparator Value (TMR6_CMP_VAL)—Offset FED001C8h ............. 3995
14.4.24Timer 6 FSB Interrupt Rout Register (TMR6_FSB_INT_ROUT)—Offset FED001D0h
3996
14.4.25Timer 7 Config and Capabilities (TMR7_CNF_CAP)—Offset FED001E0h ....... 3997
14.4.26Timer 7 Comparator Value (TMR7_CMP_VAL)—Offset FED001E8h.............. 4000
14.4.27Timer 7 FSB Interrupt Rout Register (TMR7_FSB_INT_ROUT)—Offset FED001F0h
4001
14.5 Registers Summary........................................................................................ 4002
14.5.1 Master Initialization Command Word 1 (MICW1)—Offset 20h .................... 4003
14.5.2 Master Operational Control Word 2 (MOCW2)—Offset 20h ........................ 4003
14.5.3 Master Operational Control Word 3 (MOCW3)—Offset 20h ........................ 4004
14.5.4 Master Initialization Command Word 2 (MICW2)—Offset 21h .................... 4005
14.5.5 Master Initialization Command Word 3 (MICW3)—Offset 21h .................... 4006
14.5.6 Master Initialization Command Word 4 (MICW4)—Offset 21h .................... 4007
14.5.7 Master Operational Control Word 1 (MOCW1)—Offset 21h ........................ 4007
14.5.8 Slave Operational Control Word 3 (SOCW3)—Offset A0h .......................... 4008
14.5.9 Slave Initialization Command Word 1 (SICW1)—Offset A0h ...................... 4009
14.5.10Slave Operational Control Word 2 (SOCW2)—Offset A0h .......................... 4010
14.5.11Slave Initialization Command Word 3 (SICW3)—Offset A1h ...................... 4011
14.5.12Slave Initialization Command Word 4 (SICW4)—Offset A1h ...................... 4011
14.5.13Slave Operational Control Word 1 (SOCW1)—Offset A1h .......................... 4012
14.5.14Slave Initialization Command Word 2 (SICW2)—Offset A1h ...................... 4013
14.5.15Master Edge/Level Control (ELCR1)—Offset 4D0h.................................... 4013
14.5.16Slave Edge/Level Control (ELCR2)—Offset 4D1h ..................................... 4014
14.6 Registers Summary........................................................................................ 4015
14.6.1 Counter 0 - Interval Timer Status Byte Format Register (C0_ITSBFR)—Offset 40h
4015
14.6.2 Counter 0 - Counter Access Ports Register (C0_CAPR)—Offset 40h ............ 4016
14.6.3 Counter 2 - Interval Timer Status Byte Format Register (C2_ITSBFR)—Offset 42h
4017
14.6.4 Counter 2 - Counter Access Ports Register (C2_CAPR)—Offset 42h ............ 4018
14.6.5 Timer Control Word Register (TCW)—Offset 43h ..................................... 4019
14.6.6 Read Back Command (RBC)—Offset 43h ................................................ 4020
14.6.7 Counter Latch Command (CLC)—Offset 43h ........................................... 4021
14.7 ................................................................................................................... 4021
14.8 Registers Summary........................................................................................ 4023

102 334818
 14.8.1 Version (VS)—Offset 1h .......................................................................4026
14.8.2 Redirection Table Entry 0 (RTE0)—Offset 10h..........................................4027
14.8.3 Redirection Table Entry 1 (RTE1)—Offset 12h..........................................4028
14.8.4 Redirection Table Entry 2 (RTE2)—Offset 14h..........................................4029
14.8.5 Redirection Table Entry 3 (RTE3)—Offset 16h..........................................4030
14.8.6 Redirection Table Entry 4 (RTE4)—Offset 18h..........................................4032
14.8.7 Redirection Table Entry 5 (RTE5)—Offset 1Ah..........................................4033
14.8.8 Redirection Table Entry 6 (RTE6)—Offset 1Ch .........................................4034
14.8.9 Redirection Table Entry 7 (RTE7)—Offset 1Eh..........................................4035
14.8.10Redirection Table Entry 8 (RTE8)—Offset 20h..........................................4036
14.8.11Redirection Table Entry 9 (RTE9)—Offset 22h..........................................4038
14.8.12Redirection Table Entry 10 (RTE10)—Offset 24h ......................................4039
14.8.13Redirection Table Entry 11 (RTE11)—Offset 26h ......................................4040
14.8.14Redirection Table Entry 12 (RTE12)—Offset 28h ......................................4041
14.8.15Redirection Table Entry 13 (RTE13)—Offset 2Ah ......................................4042
14.8.16Redirection Table Entry 14 (RTE14)—Offset 2Ch ......................................4043
14.8.17Redirection Table Entry 15 (RTE15)—Offset 2Eh ......................................4045
14.8.18Redirection Table Entry 16 (RTE16)—Offset 30h ......................................4046
14.8.19Redirection Table Entry 17 (RTE17)—Offset 32h ......................................4047
14.8.20Redirection Table Entry 18 (RTE18)—Offset 34h ......................................4048
14.8.21Redirection Table Entry 19 (RTE19)—Offset 36h ......................................4049
14.8.22Redirection Table Entry 20 (RTE20)—Offset 38h ......................................4050
14.8.23Redirection Table Entry 21 (RTE21)—Offset 3Ah ......................................4052
14.8.24Redirection Table Entry 22 (RTE22)—Offset 3Ch ......................................4053
14.8.25Redirection Table Entry 23 (RTE23)—Offset 3Eh ......................................4054
14.8.26Redirection Table Entry 24 (RTE24)—Offset 40h ......................................4055
14.8.27Redirection Table Entry 25 (RTE25)—Offset 42h ......................................4056
14.8.28Redirection Table Entry 26 (RTE26)—Offset 44h ......................................4057
14.8.29Redirection Table Entry 27 (RTE27)—Offset 46h ......................................4059
14.8.30Redirection Table Entry 28 (RTE28)—Offset 48h ......................................4060
14.8.31Redirection Table Entry 29 (RTE29)—Offset 4Ah ......................................4061
14.8.32Redirection Table Entry 30 (RTE30)—Offset 4Ch ......................................4062
14.8.33Redirection Table Entry 31 (RTE31)—Offset 4Eh ......................................4063
14.8.34Redirection Table Entry 32 (RTE32)—Offset 50h ......................................4064
14.8.35Redirection Table Entry 33 (RTE33)—Offset 52h ......................................4066
14.8.36Redirection Table Entry 34 (RTE34)—Offset 54h ......................................4067
14.8.37Redirection Table Entry 35 (RTE35)—Offset 56h ......................................4068
14.8.38Redirection Table Entry 36 (RTE36)—Offset 58h ......................................4069
14.8.39Redirection Table Entry 37 (RTE37)—Offset 5Ah ......................................4070
14.8.40Redirection Table Entry 38 (RTE38)—Offset 5Ch ......................................4071
14.8.41Redirection Table Entry 39 (RTE39)—Offset 5Eh ......................................4073
14.8.42Redirection Table Entry 40 (RTE40)—Offset 60h ......................................4074
14.8.43Redirection Table Entry 41 (RTE41)—Offset 62h ......................................4075
14.8.44Redirection Table Entry 42 (RTE42)—Offset 64h ......................................4076
14.8.45Redirection Table Entry 43 (RTE43)—Offset 66h ......................................4077
14.8.46Redirection Table Entry 44 (RTE44)—Offset 68h ......................................4078
14.8.47Redirection Table Entry 45 (RTE45)—Offset 6Ah ......................................4080
14.8.48Redirection Table Entry 46 (RTE46)—Offset 6Ch ......................................4081
14.8.49Redirection Table Entry 47 (RTE47)—Offset 6Eh ......................................4082
14.8.50Redirection Table Entry 48 (RTE48)—Offset 70h ......................................4083
14.8.51Redirection Table Entry 49 (RTE49)—Offset 72h ......................................4084
14.8.52Redirection Table Entry 50 (RTE50)—Offset 74h ......................................4085
14.8.53Redirection Table Entry 51 (RTE51)—Offset 76h ......................................4087
14.8.54Redirection Table Entry 52 (RTE52)—Offset 78h ......................................4088
14.8.55Redirection Table Entry 53 (RTE53)—Offset 7Ah ......................................4089

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 14.8.56Redirection Table Entry 54 (RTE54)—Offset 7Ch ..................................... 4090
14.8.57Redirection Table Entry 55 (RTE55)—Offset 7Eh...................................... 4091
14.8.58Redirection Table Entry 56 (RTE56)—Offset 80h...................................... 4092
14.8.59Redirection Table Entry 57 (RTE57)—Offset 82h...................................... 4094
14.8.60Redirection Table Entry 58 (RTE58)—Offset 84h...................................... 4095
14.8.61Redirection Table Entry 59 (RTE59)—Offset 86h...................................... 4096
14.8.62Redirection Table Entry 60 (RTE60)—Offset 88h...................................... 4097
14.8.63Redirection Table Entry 61 (RTE61)—Offset 8Ah ..................................... 4098
14.8.64Redirection Table Entry 62 (RTE62)—Offset 8Ch ..................................... 4099
14.8.65Redirection Table Entry 63 (RTE63)—Offset 8Eh...................................... 4101
14.8.66Redirection Table Entry 64 (RTE64)—Offset 90h...................................... 4102
14.8.67Redirection Table Entry 65 (RTE65)—Offset 92h...................................... 4103
14.8.68Redirection Table Entry 66 (RTE66)—Offset 94h...................................... 4104
14.8.69Redirection Table Entry 67 (RTE67)—Offset 96h...................................... 4105
14.8.70Redirection Table Entry 68 (RTE68)—Offset 98h...................................... 4106
14.8.71Redirection Table Entry 69 (RTE69)—Offset 9Ah ..................................... 4108
14.8.72Redirection Table Entry 70 (RTE70)—Offset 9Ch ..................................... 4109
14.8.73Redirection Table Entry 71 (RTE71)—Offset 9Eh...................................... 4110
14.8.74Redirection Table Entry 72 (RTE72)—Offset A0h ..................................... 4111
14.8.75Redirection Table Entry 73 (RTE73)—Offset A2h ..................................... 4112
14.8.76Redirection Table Entry 74 (RTE74)—Offset A4h ..................................... 4113
14.8.77Redirection Table Entry 75 (RTE75)—Offset A6h ..................................... 4115
14.8.78Redirection Table Entry 76 (RTE76)—Offset A8h ..................................... 4116
14.8.79Redirection Table Entry 77 (RTE77)—Offset AAh ..................................... 4117
14.8.80Redirection Table Entry 78 (RTE78)—Offset ACh ..................................... 4118
14.8.81Redirection Table Entry 79 (RTE79)—Offset AEh ..................................... 4119
14.8.82Redirection Table Entry 80 (RTE80)—Offset B0h ..................................... 4120
14.8.83Redirection Table Entry 81 (RTE81)—Offset B2h ..................................... 4122
14.8.84Redirection Table Entry 82 (RTE82)—Offset B4h ..................................... 4123
14.8.85Redirection Table Entry 83 (RTE83)—Offset B6h ..................................... 4124
14.8.86Redirection Table Entry 84 (RTE84)—Offset B8h ..................................... 4125
14.8.87Redirection Table Entry 85 (RTE85)—Offset BAh ..................................... 4126
14.8.88Redirection Table Entry 86 (RTE86)—Offset BCh ..................................... 4127
14.8.89Redirection Table Entry 87 (RTE87)—Offset BEh ..................................... 4129
14.8.90Redirection Table Entry 88 (RTE88)—Offset C0h ..................................... 4130
14.8.91Redirection Table Entry 89 (RTE89)—Offset C2h ..................................... 4131
14.8.92Redirection Table Entry 90 (RTE90)—Offset C4h ..................................... 4132
14.8.93Redirection Table Entry 91 (RTE91)—Offset C6h ..................................... 4133
14.8.94Redirection Table Entry 92 (RTE92)—Offset C8h ..................................... 4134
14.8.95Redirection Table Entry 93 (RTE93)—Offset CAh ..................................... 4136
14.8.96Redirection Table Entry 94 (RTE94)—Offset CCh ..................................... 4137
14.8.97Redirection Table Entry 95 (RTE95)—Offset CEh ..................................... 4138
14.8.98Redirection Table Entry 96 (RTE96)—Offset D0h ..................................... 4139
14.8.99Redirection Table Entry 97 (RTE97)—Offset D2h ..................................... 4140
14.8.100Redirection Table Entry 98 (RTE98)—Offset D4h.................................... 4141
14.8.101Redirection Table Entry 99 (RTE99)—Offset D6h.................................... 4143
14.8.102Redirection Table Entry 100 (RTE100)—Offset D8h ................................ 4144
14.8.103Redirection Table Entry 101 (RTE101)—Offset DAh ................................ 4145
14.8.104Redirection Table Entry 102 (RTE102)—Offset DCh ................................ 4146
14.8.105Redirection Table Entry 103 (RTE103)—Offset DEh ................................ 4147
14.8.106Redirection Table Entry 104 (RTE104)—Offset E0h................................. 4148
14.8.107Redirection Table Entry 105 (RTE105)—Offset E2h................................. 4150
14.8.108Redirection Table Entry 106 (RTE106)—Offset E4h................................. 4151
14.8.109Redirection Table Entry 107 (RTE107)—Offset E6h................................. 4152
14.8.110Redirection Table Entry 108 (RTE108)—Offset E8h................................. 4153

104 334818
 14.8.111Redirection Table Entry 109 (RTE109)—Offset EAh .................................4154
14.8.112Redirection Table Entry 110 (RTE110)—Offset ECh .................................4155
14.8.113Redirection Table Entry 111 (RTE111)—Offset EEh .................................4157
14.8.114Redirection Table Entry 112 (RTE112)—Offset F0h .................................4158
14.8.115Redirection Table Entry 113 (RTE113)—Offset F2h .................................4159
14.8.116Redirection Table Entry 114 (RTE114)—Offset F4h .................................4160
14.8.117Redirection Table Entry 115 (RTE115)—Offset F6h .................................4161
14.8.118Redirection Table Entry 116 (RTE116)—Offset F8h .................................4162
14.8.119Redirection Table Entry 117 (RTE117)—Offset FAh .................................4164
14.8.120Redirection Table Entry 118 (RTE118)—Offset FCh .................................4165
14.8.121Redirection Table Entry 119 (RTE119)—Offset FEh .................................4166
14.8.122PIRQA Routing Control (PARC)—Offset 3100h ........................................4167
14.8.123PIRQB Routing Control (PBRC)—Offset 3101h ........................................4168
14.8.124PIRQC Routing Control (PCRC)—Offset 3102h ........................................4168
14.8.125PIRQD Routing Control (PDRC)—Offset 3103h........................................4169
14.8.126PIRQE Routing Control (PERC)—Offset 3104h ........................................4170
14.8.127PIRQF Routing Control (PFRC)—Offset 3105h.........................................4170
14.8.128PIRQG Routing Control (PGRC)—Offset 3106h........................................4171
14.8.129PIRQH Routing Control (PHRC)—Offset 3107h........................................4172
14.8.130PCI Interrupt Route 0 (PIR0)—Offset 3140h ..........................................4172
14.8.131PCI Interrupt Route 1 (PIR1)—Offset 3142h ..........................................4173
14.8.132PCI Interrupt Route 2 (PIR2)—Offset 3144h ..........................................4174
14.8.133PCI Interrupt Route 3(PIR3)—Offset 3146h ...........................................4175
14.8.134PCI Interrupt Route 4 (PIR4)—Offset 3148h ..........................................4176
14.8.135PCI Interrupt Route 5 (PIR5)—Offset 314Ah ..........................................4177
14.8.136PCI Interrupt Route 6 (PIR6)—Offset 314Ch ..........................................4177
14.8.137PCI Interrupt Route 7 (PIR7)—Offset 314Eh ..........................................4178
14.8.138PCI Interrupt Route 8 (PIR8)—Offset 3150h ..........................................4179
14.8.139PCI Interrupt Route 9 (PIR9)—Offset 3152h ..........................................4180
14.8.140PCI Interrupt Route 10 (PIR10)—Offset 3154h .......................................4181
14.8.141PCI Interrupt Route 11 (PIR11)—Offset 3156h .......................................4182
14.8.142PCI Interrupt Route 12 (PIR12)—Offset 3158h .......................................4182
14.8.143Interrupt Polarity Control 0 (IPC0)—Offset 3200h...................................4183
14.8.144Interrupt Polarity Control 1 (IPC1)—Offset 3204h...................................4183
14.8.145Interrupt Polarity Control 2 (IPC2)—Offset 3208h...................................4184
14.8.146Interrupt Polarity Control 3 (IPC3)—Offset 320Ch...................................4184
14.8.147ITSS Power Reduction Control (ITSSPRC)—Offset 3300h .........................4185
14.8.148SIDE Clock Timing (SIDECT)—Offset 3304h...........................................4185
14.9 Registers Summary ........................................................................................4187
14.9.1 Index Register (IDX)—Offset FEC00000h ................................................4187
14.9.2 Window Register (WDW)—Offset FEC00010h...........................................4187
14.9.3 EOI Register (EOI)—Offset FEC00040h ...................................................4188
14.10 Registers Summary ........................................................................................4189
14.10.1NMI Status and Control (NMI_STS_CNT)—Offset 61h ...............................4189
14.10.2NMI Enable (and Real Time Clock Index) (NMI_EN)—Offset 70h ................4190
14.10.3Init Register (PORT92)—Offset 92h........................................................4191
14.10.4Reset Control Register (RST_CNT)—Offset CF9h ......................................4191
14.11 Registers Summary ........................................................................................4193
14.11.1General Capabilities and ID Register (GEN_CAP_ID)—Offset FED00000h.....4194
14.11.2General Config Register (GEN_CFG)—Offset FED00010h ...........................4195
14.11.3Main Counter Value (MAIN_CNTR)—Offset FED000F0h .............................4196
14.11.4Timer 0 Config and Capabilities (TMR0_CNF_CAP)—Offset FED00100h........4196
14.11.5Timer 0 Comparator Value (TMR0_CMP_VAL)—Offset FED00108h ..............4199
14.11.6Timer 0 FSB Interrupt Rout Register (TMR0_FSB_INT_ROUT)—Offset FED00110h
4200

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 14.11.7Timer 1 Config and Capabilities (TMR1_CNF_CAP)—Offset FED00120h ....... 4201
14.11.8Timer 1 Comparator Value (TMR1_CMP_VAL)—Offset FED00128h ............. 4204
14.11.9Timer 1 FSB Interrupt Rout Register (TMR1_FSB_INT_ROUT)—Offset FED00130h
4205
14.11.10Timer 2 Config and Capabilities (TMR2_CNF_CAP)—Offset FED00140h...... 4206
14.11.11Timer 2 Comparator Value (TMR2_CMP_VAL)—Offset FED00148h ............ 4209
14.11.12Timer 2 FSB Interrupt Rout Register (TMR2_FSB_INT_ROUT)—Offset
FED00150h ........................................................................................ 4210
14.11.13Timer 3 Config and Capabilities (TMR3_CNF_CAP)—Offset FED00160h...... 4211
14.11.14Timer 3 Comparator Value (TMR3_CMP_VAL)—Offset FED00168h ............ 4214
14.11.15Timer 3 FSB Interrupt Rout Register (TMR3_FSB_INT_ROUT)—Offset
FED00170h ........................................................................................ 4215
14.11.16Timer 4 Config and Capabilities (TMR4_CNF_CAP)—Offset FED00180h...... 4216
14.11.17Timer 4 Comparator Value (TMR4_CMP_VAL)—Offset FED00188h ............ 4219
14.11.18Timer 4 FSB Interrupt Rout Register (TMR4_FSB_INT_ROUT)—Offset
FED00190h ........................................................................................ 4220
14.11.19Timer 5 Config and Capabilities (TMR5_CNF_CAP)—Offset FED001A0h ..... 4221
14.11.20Timer 5 Comparator Value (TMR5_CMP_VAL)—Offset FED001A8h ............ 4224
14.11.21Timer 5 FSB Interrupt Rout Register (TMR5_FSB_INT_ROUT)—Offset
FED001B0h........................................................................................ 4225
14.11.22Timer 6 Config and Capabilities (TMR6_CNF_CAP)—Offset FED001C0h ..... 4226
14.11.23Timer 6 Comparator Value (TMR6_CMP_VAL)—Offset FED001C8h ............ 4229
14.11.24Timer 6 FSB Interrupt Rout Register (TMR6_FSB_INT_ROUT)—Offset
FED001D0h ....................................................................................... 4230
14.11.25Timer 7 Config and Capabilities (TMR7_CNF_CAP)—Offset FED001E0h...... 4231
14.11.26Timer 7 Comparator Value (TMR7_CMP_VAL)—Offset FED001E8h ............ 4234
14.11.27Timer 7 FSB Interrupt Rout Register (TMR7_FSB_INT_ROUT)—Offset
FED001F0h ........................................................................................ 4235
14.12 Registers Summary........................................................................................ 4237
14.12.1Master Initialization Command Word 1 (MICW1)—Offset 20h .................... 4237
14.12.2Master Operational Control Word 2 (MOCW2)—Offset 20h ........................ 4238
14.12.3Master Operational Control Word 3 (MOCW3)—Offset 20h ........................ 4239
14.12.4Master Initialization Command Word 2 (MICW2)—Offset 21h .................... 4240
14.12.5Master Initialization Command Word 3 (MICW3)—Offset 21h .................... 4241
14.12.6Master Initialization Command Word 4 (MICW4)—Offset 21h .................... 4242
14.12.7Master Operational Control Word 1 (MOCW1)—Offset 21h ........................ 4242
14.12.8Slave Operational Control Word 3 (SOCW3)—Offset A0h .......................... 4243
14.12.9Slave Initialization Command Word 1 (SICW1)—Offset A0h ...................... 4244
14.12.10Slave Operational Control Word 2 (SOCW2)—Offset A0h......................... 4245
14.12.11Slave Initialization Command Word 3 (SICW3)—Offset A1h..................... 4246
14.12.12Slave Initialization Command Word 4 (SICW4)—Offset A1h..................... 4246
14.12.13Slave Operational Control Word 1 (SOCW1)—Offset A1h......................... 4247
14.12.14Slave Initialization Command Word 2 (SICW2)—Offset A1h..................... 4248
14.12.15Master Edge/Level Control (ELCR1)—Offset 4D0h .................................. 4248
14.12.16Slave Edge/Level Control (ELCR2)—Offset 4D1h .................................... 4249
14.13 Registers Summary........................................................................................ 4251
14.13.1Counter 0 - Interval Timer Status Byte Format Register (C0_ITSBFR)—Offset 40h
4251
14.13.2Counter 0 - Counter Access Ports Register (C0_CAPR)—Offset 40h ............ 4252
14.13.3Counter 2 - Interval Timer Status Byte Format Register (C2_ITSBFR)—Offset 42h
4253
14.13.4Counter 2 - Counter Access Ports Register (C2_CAPR)—Offset 42h ............ 4254
14.13.5Timer Control Word Register (TCW)—Offset 43h ..................................... 4255
14.13.6Read Back Command (RBC)—Offset 43h ................................................ 4256
14.13.7Counter Latch Command (CLC)—Offset 43h ........................................... 4257

106 334818
15 IOSF2OCP.............................................................................................................4259
15.1 Registers Summary ........................................................................................4259
15.1.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
4259
15.1.2 STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..4260
15.1.3 REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
4261
15.1.4 CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ...........................................................................................4262
15.1.5 BAR -Base Address Register (BAR)—Offset 10h .......................................4262
15.1.6 BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................4263
15.1.7 BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................4264
15.1.8 BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................4264
15.1.9 SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................4265
15.1.10EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ......
4266
15.1.11CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h...........4266
15.1.12INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ............4267
15.1.13POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h.....
4267
15.1.14PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................4268
15.1.15PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset 90h
4269
15.1.16DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h 4270
15.1.17D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................4270
15.1.18DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................4271
15.1.19D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................4272
15.2 ...................................................................................................................4273
15.3 Registers Summary ........................................................................................4275
15.3.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
4275
15.3.2 STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..4276
15.3.3 REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
4277
15.3.4 CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ...........................................................................................4278
15.3.5 BAR -Base Address Register (BAR)—Offset 10h .......................................4278
15.3.6 BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................4279
15.3.7 BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................4280
15.3.8 BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................4280
15.3.9 SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................4281
15.3.10EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ......
4282
15.3.11CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h...........4282
15.3.12INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ............4283
15.3.13POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h.....
4283
15.3.14PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................4284

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 15.3.15PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset 90h
4285
15.3.16DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h 4286
15.3.17D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 4286
15.3.18DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 4287
15.3.19D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 4288
16 PCIe..................................................................................................................... 4291
16.1 Registers Summary........................................................................................ 4291
16.1.1 Device Command; Primary Status (CMD_PSPCLKD_L1TREF_CFG—Offset
1010hTS)—Offset 4h........................................................................... 4294
16.1.2 Revision ID;Class Code (RID_CC)—Offset 8h .......................................... 4296
16.1.3 Cache Line Size; Primary Latency Timer; Header Type (CLS_PLT_HTYPE)—Offset
Ch .................................................................................................... 4297
16.1.4 Bus Numbers; Secondary Latency Timer (BNUM_SLT)—Offset 18h ............ 4298
16.1.5 I/O Base and Limit; Secondary Status (IOBL_SSTS)—Offset 1Ch............... 4298
16.1.6 Memory Base and Limit (MBL)—Offset 20h ............................................. 4300
16.1.7 Prefetchable Memory Base and Limit (PMBL)—Offset 24h ......................... 4300
16.1.8 Prefetchable Memory Base Upper 32 Bits (PMBU32)—Offset 28h ............... 4301
16.1.9 Prefetchable Memory Limit Upper 32 Bits (PMLU32)—Offset 2Ch ............... 4301
16.1.10Capabilities List Pointer (CAPP)—Offset 34h ............................................ 4302
16.1.11Interrupt Information; Bridge Control (INTR_BCTRL)—Offset 3Ch.............. 4303
16.1.12Capabilities List; PCI Express Capabilities (CLIST_XCAP)—Offset 40h ......... 4305
16.1.13Device Capabilities (DCAP)—Offset 44h.................................................. 4306
16.1.14Device Control; Device Status (DCTL_DSTS)—Offset 48h ......................... 4307
16.1.15Link Capabilities (LCAP)—Offset 4Ch...................................................... 4309
16.1.16Link Control; Link Status (LCTL_LSTS)—Offset 50h ................................. 4312
16.1.17Slot Capabilities (SLCAP)—Offset 54h .................................................... 4316
16.1.18Slot Control; Slot Status (SLCTL_SLSTS)—Offset 58h .............................. 4317
16.1.19Root Control (RCTL)—Offset 5Ch........................................................... 4318
16.1.20Root Status (RSTS)—Offset 60h............................................................ 4319
16.1.21Device Capabilities 2 (DCAP2)—Offset 64h ............................................. 4320
16.1.22Device Control 2; Device Status 2 (DCTL2_DSTS2)—Offset 68h ................ 4321
16.1.23Link Capabilities 2 (LCAP2)—Offset 6Ch ................................................. 4324
16.1.24Link Control 2; Link Status 2 (LCTL2_LSTS2)—Offset 70h ........................ 4326
16.1.25Slot Capabilities 2 (SLCAP2)—Offset 74h................................................ 4329
16.1.26Slot Control 2; Slot Status 2 (SLCTL2_SLSTS2)—Offset 78h ..................... 4330
16.1.27Message Signaled Interrupt Identifiers; Message Signaled Interrupt Message
Control (MID_MC)—Offset 80h.............................................................. 4330
16.1.28Message Signaled Interrupt Message Data (MD)—Offset 88h .................... 4331
16.1.29Subsystem Vendor Capability (SVCAP)—Offset 90h ................................. 4332
16.1.30Subsystem Vendor IDs (SVID)—Offset 94h ............................................ 4332
16.1.31Power Management Capability; PCI Power Management Capabilities
(PMCAP_PMC)—Offset A0h ................................................................... 4333
16.1.32PCI Power Management Control And Status (PMCS)—Offset A4h ............... 4334
16.1.33Advanced Error Extended Reporting Capability Header (AECH)—Offset 100h4335
16.1.34Uncorrectable Error Status (UES)—Offset 104h ....................................... 4336
16.1.35Uncorrectable Error Mask (UEM)—Offset 108h ........................................ 4337
16.1.36Uncorrectable Error Severity (UEV)—Offset 10Ch .................................... 4338
16.1.37Correctable Error Status (CES)—Offset 110h .......................................... 4339
16.1.38Correctable Error Mask (CEM)—Offset 114h............................................ 4340
16.1.39Advanced Error Capabilities and Control (AECC)—Offset 118h ................... 4341
16.1.40Header Log DW1 (HL_DW1)—Offset 11Ch .............................................. 4342

108 334818
 16.1.41Header Log DW2 (HL_DW2)—Offset 120h...............................................4342
16.1.42Header Log DW3 (HL_DW3)—Offset 124h...............................................4343
16.1.43Header Log DW4 (HL_DW4)—Offset 128h...............................................4343
16.1.44Root Error Command (REC)—Offset 12Ch ...............................................4344
16.1.45Error Source Identification (ESID)—Offset 134h.......................................4344
16.1.46ACS Extended Capability Header (ACSECH)—Offset 140h..........................4345
16.1.47ACS Capability Register (ACSCAPR)—Offset 144h ....................................4346
16.1.48ACS Control Register (ACSCTLR)—Offset 148h ........................................4347
16.1.49PTM Extended Capability Header (PTMECH)—Offset 150h..........................4348
16.1.50PTM Capability Register (PTMCAPR)—Offset 154h ....................................4349
16.1.51PTM Control Register (PTMCTLR)—Offset 158h ........................................4350
16.1.52L1 Sub-States Extended Capability Header (L1SECH)—Offset 200h ............4350
16.1.53L1 Sub-States Capabilities (L1SCAP)—Offset 204h ...................................4351
16.1.54L1 Sub-States Control 1 (L1SCTL1)—Offset 208h.....................................4353
16.1.55L1 Sub-States Control 2 (L1SCTL2)—Offset 20Ch ....................................4354
16.1.56Secondary PCI Express Extended Capability Header (SPEECH)—Offset 220h 4355
16.1.57Link Control 3 (LCTL3)—Offset 224h ......................................................4356
16.1.58Lane Error Status (LES)—Offset 228h ....................................................4357
16.1.59Lane 0 and Lane 1 Equalization Control (L01EC)—Offset 22Ch ...................4358
16.1.60Lane 2 and Lane 3 Equalization Control (L23EC)—Offset 230h ...................4360
16.1.61PCI Express Replay Timer Policy 1 (PCIERTP1)—Offset 300h .....................4361
16.1.62PCI Express Replay Timer Policy 2 (PCIERTP2)—Offset 304h .....................4363
16.1.63PCI Express Status 1 (PCIESTS1)—Offset 328h .......................................4366
16.1.64PCI Express Status 2 (PCIESTS2)—Offset 32Ch .......................................4370
16.1.65PCI Express Compliance Measurement Mode (CMM) Port Control (PCIECMMPC)—
Offset 330h ........................................................................................4372
16.1.66PCI Express Compliance Measurement Mode Symbol Buffer (PCIECMMSB)—Offset
334h .................................................................................................4374
16.1.67PTM Propagation Delay (PTMPD)—Offset 390h.........................................4375
16.1.68PTM Lower Local Master Time (PTMLLMT)—Offset 394h ............................4375
16.1.69PTM Upper Local Master Time (PTMULMT)—Offset 398h ............................4376
16.1.70PTM Pipe Stage Delay Configuration 1 (PTMPSDC1)—Offset 39Ch ..............4376
16.1.71PTM Pipe Stage Delay Configuration 2 (PTMPSDC2)—Offset 3A0h...............4377
16.1.72PTM Pipe Stage Delay Configuration 3 (PTMPSDC3)—Offset 3A4h...............4378
16.1.73PTM Pipe Stage Delay Configuration 4 (PTMPSDC4)—Offset 3A8h...............4380
16.1.74PTM Pipe Stage Delay Configuration 5 (PTMPSDC5)—Offset 3ACh ..............4381
16.1.75PTM Extended Config (PTMECFG)—Offset 3B0h........................................4382
16.1.76PTM Lower T2 Time Stamp (PTMLT2TSTMP)—Offset 3B4h .........................4385
16.1.77PTM Upper T2 Time Stamp (PTMUT2TSTMP)—Offset 3B8h ........................4386
16.1.78Strap Configuration 2 (STRPFUSECFG2)—Offset 414h ..............................4386
16.1.79Thermal and Power Throttling (TNPT)—Offset 418h..................................4387
16.1.80Dynamic Lane Switch (DYNLNSW)—Offset 41Ch ......................................4391
16.1.81Power Control Enable (PCE)—Offset 428h ...............................................4392
16.1.82PGCB Control1 (PGCBCTL1)—Offset 42Ch ...............................................4393
16.1.83PGCB Control2 (PGCBCTL2)—Offset 430h ...............................................4396
16.1.84Equalization Configuration 1 (EQCFG1)—Offset 450h................................4397
16.1.85Remote Transmitter Preset Coefficient List 1 (RTPCL1)—Offset 454h ..........4403
16.1.86Remote Transmitter Preset Coefficient List 2 (RTPCL2)—Offset 458h ..........4406
16.1.87Remote Transmitter Preset Coefficient List 3 (RTPCL3)—Offset 45Ch ..........4409
16.1.88Remote Transmitter Preset Coefficient List 4 (RTPCL4)—Offset 460h ..........4412
16.1.89Figure Of Merit Status (FOMS)—Offset 464h............................................4415
16.1.90Hardware Autonomous Equalization Control (HAEQ)—Offset 468h ..............4416
16.1.91Local Transmitter Coefficient Override 1 (LTCO1)—Offset 470h..................4419
16.1.92Local Transmitter Coefficient Override 2 (LTCO2)—Offset 474h..................4421
16.1.93GEN3 L0s Control (G3L0SCTL)—Offset 478h ...........................................4423

334818 109
 16.1.94Equalization Configuration 2 (EQCFG2)—Offset 47Ch ............................... 4425
16.1.95Monitor Mux (MM)—Offset 480h............................................................ 4428
16.1.96Lane0 P0 and P1 Preset-Coefficient Mapping (L0P0P1PCM)—Offset 500h .... 4429
16.1.97Lane0 P1, P2 and P3 Preset-Coefficient Mapping (L0P1P2P3PCM)—Offset 504h...
4430
16.1.98Lane0 P3 and P4 Preset-Coefficient Mapping (L0P3P4PCM)—Offset 508h .... 4431
16.1.99Lane0 P5 and P6 Preset-Coefficient Mapping (L0P5P6PCM)—Offset 50Ch .... 4433
16.1.100Lane0 P6, P7 and P8 Preset-Coefficient Mapping (L0P6P7P8PCM)—Offset 510h .
4434
16.1.101Lane0 P8 and P9 Preset-Coefficient Mapping (L0P8P9PCM)—Offset 514h ... 4435
16.1.102Lane0 P10 Preset-Coefficient Mapping (L0P10PCM)—Offset 518h ............. 4436
16.1.103Lane0 LF and FS (L0LFFS)—Offset 51Ch ............................................... 4437
16.1.104Lane1 P0 and P1 Preset-Coefficient Mapping (L1P0P1PCM)—Offset 520h ... 4439
16.1.105Lane1 P1, P2 and P3 Preset-Coefficient Mapping (L1P1P2P3PCM)—Offset 524h .
4440
16.1.106Lane1 P3 and P4 Preset-Coefficient Mapping (L1P3P4PCM)—Offset 528h ... 4441
16.1.107Lane1 P5 and P6 Preset-Coefficient Mapping (L1P5P6PCM)—Offset 52Ch... 4442
16.1.108Lane1 P6, P7 and P8 Preset-Coefficient Mapping (L1P6P7P8PCM)—Offset 530h .
4444
16.1.109Lane1 P8 and P9 Preset-Coefficient Mapping (L1P8P9PCM)—Offset 534h ... 4445
16.1.110Lane1 P10 Preset-Coefficient Mapping (L1P10PCM)—Offset 538h ............. 4446
16.1.111Lane1 LF and FS (L1LFFS)—Offset 53Ch ............................................... 4447
16.1.112Lane2 P0 and P1 Preset-Coefficient Mapping (L2P0P1PCM)—Offset 540h ... 4448
16.1.113Lane2 P1, P2 and P3 Preset-Coefficient Mapping (L2P1P2P3PCM)—Offset 544h .
4449
16.1.114Lane2 P3 and P4 Preset-Coefficient Mapping (L2P3P4PCM)—Offset 548h ... 4450
16.1.115Lane2 P5 and P6 Preset-Coefficient Mapping (L2P5P6PCM)—Offset 54Ch... 4452
16.1.116Lane2 P6, P7 and P8 Preset-Coefficient Mapping (L2P6P7P8PCM)—Offset 550h .
4453
16.1.117Lane2 P8 and P9 Preset-Coefficient Mapping (L2P8P9PCM)—Offset 554h ... 4454
16.1.118Lane2 P10 Preset-Coefficient Mapping (L2P10PCM)—Offset 558h ............. 4455
16.1.119Lane2 LF and FS (L2LFFS)—Offset 55Ch ............................................... 4456
16.1.120Lane3 P0 and P1 Preset-Coefficient Mapping (L3P0P1PCM)—Offset 560h ... 4457
16.1.121Lane3 P1, P2 and P3 Preset-Coefficient Mapping (L3P1P2P3PCM)—Offset 564h .
4459
16.1.122Lane3 P3 and P4 Preset-Coefficient Mapping (L3P3P4PCM)—Offset 568h ... 4460
16.1.123Lane3 P5 and P6 Preset-Coefficient Mapping (L3P5P6PCM)—Offset 56Ch... 4461
16.1.124Lane3 P6, P7 and P8 Preset-Coefficient Mapping (L3P6P7P8PCM)—Offset 570h .
4462
16.1.125Lane3 P8 and P9 Preset-Coefficient Mapping (L3P8P9PCM)—Offset 574h ... 4463
16.1.126Lane3 P10 Preset-Coefficient Mapping (L3P10PCM)—Offset 578h ............. 4464
16.1.127Lane3 LF and FS (L3LFFS)—Offset 57Ch ............................................... 4465
16.1.128Lane3 LF and FS (L3LFFS)—Offset 57Ch ............................................... 4466
16.1.129PCLKD_L1TREF_CFG—Offset 1010h ..................................................... 4468
16.2 ................................................................................................................... 4470
16.3 Registers Summary........................................................................................ 4471
16.3.1 Device Command; Primary Status (CMD_PSPCLKD_L1TREF_CFG—Offset
1010hTS)—Offset 4h........................................................................... 4474
16.3.2 Revision ID;Class Code (RID_CC)—Offset 8h .......................................... 4476
16.3.3 Cache Line Size; Primary Latency Timer; Header Type (CLS_PLT_HTYPE)—Offset
Ch .................................................................................................... 4477
16.3.4 Bus Numbers; Secondary Latency Timer (BNUM_SLT)—Offset 18h ............ 4478
16.3.5 I/O Base and Limit; Secondary Status (IOBL_SSTS)—Offset 1Ch............... 4478
16.3.6 Memory Base and Limit (MBL)—Offset 20h ............................................. 4480
16.3.7 Prefetchable Memory Base and Limit (PMBL)—Offset 24h ......................... 4480
16.3.8 Prefetchable Memory Base Upper 32 Bits (PMBU32)—Offset 28h ............... 4481

110 334818
 16.3.9 Prefetchable Memory Limit Upper 32 Bits (PMLU32)—Offset 2Ch ................4481
16.3.10Capabilities List Pointer (CAPP)—Offset 34h ............................................4482
16.3.11Interrupt Information; Bridge Control (INTR_BCTRL)—Offset 3Ch ..............4483
16.3.12Capabilities List; PCI Express Capabilities (CLIST_XCAP)—Offset 40h .........4485
16.3.13Device Capabilities (DCAP)—Offset 44h ..................................................4486
16.3.14Device Control; Device Status (DCTL_DSTS)—Offset 48h..........................4487
16.3.15Link Capabilities (LCAP)—Offset 4Ch ......................................................4489
16.3.16Link Control; Link Status (LCTL_LSTS)—Offset 50h ..................................4492
16.3.17Slot Capabilities (SLCAP)—Offset 54h.....................................................4496
16.3.18Slot Control; Slot Status (SLCTL_SLSTS)—Offset 58h...............................4497
16.3.19Root Control (RCTL)—Offset 5Ch ...........................................................4498
16.3.20Root Status (RSTS)—Offset 60h ............................................................4499
16.3.21Device Capabilities 2 (DCAP2)—Offset 64h..............................................4500
16.3.22Device Control 2; Device Status 2 (DCTL2_DSTS2)—Offset 68h.................4501
16.3.23Link Capabilities 2 (LCAP2)—Offset 6Ch..................................................4504
16.3.24Link Control 2; Link Status 2 (LCTL2_LSTS2)—Offset 70h .........................4506
16.3.25Slot Capabilities 2 (SLCAP2)—Offset 74h ................................................4509
16.3.26Slot Control 2; Slot Status 2 (SLCTL2_SLSTS2)—Offset 78h ......................4510
16.3.27Message Signaled Interrupt Identifiers; Message Signaled Interrupt Message
Control (MID_MC)—Offset 80h ..............................................................4510
16.3.28Message Signaled Interrupt Message Data (MD)—Offset 88h .....................4511
16.3.29Subsystem Vendor Capability (SVCAP)—Offset 90h ..................................4512
16.3.30Subsystem Vendor IDs (SVID)—Offset 94h .............................................4512
16.3.31Power Management Capability; PCI Power Management Capabilities
(PMCAP_PMC)—Offset A0h ...................................................................4513
16.3.32PCI Power Management Control And Status (PMCS)—Offset A4h ................4514
16.3.33Advanced Error Extended Reporting Capability Header (AECH)—Offset 100h4515
16.3.34Uncorrectable Error Status (UES)—Offset 104h .......................................4516
16.3.35Uncorrectable Error Mask (UEM)—Offset 108h .........................................4517
16.3.36Uncorrectable Error Severity (UEV)—Offset 10Ch.....................................4518
16.3.37Correctable Error Status (CES)—Offset 110h ...........................................4519
16.3.38Correctable Error Mask (CEM)—Offset 114h ............................................4520
16.3.39Advanced Error Capabilities and Control (AECC)—Offset 118h ...................4521
16.3.40Header Log DW1 (HL_DW1)—Offset 11Ch...............................................4522
16.3.41Header Log DW2 (HL_DW2)—Offset 120h...............................................4522
16.3.42Header Log DW3 (HL_DW3)—Offset 124h...............................................4523
16.3.43Header Log DW4 (HL_DW4)—Offset 128h...............................................4523
16.3.44Root Error Command (REC)—Offset 12Ch ...............................................4524
16.3.45Error Source Identification (ESID)—Offset 134h.......................................4524
16.3.46ACS Extended Capability Header (ACSECH)—Offset 140h..........................4525
16.3.47ACS Capability Register (ACSCAPR)—Offset 144h ....................................4526
16.3.48ACS Control Register (ACSCTLR)—Offset 148h ........................................4527
16.3.49PTM Extended Capability Header (PTMECH)—Offset 150h..........................4528
16.3.50PTM Capability Register (PTMCAPR)—Offset 154h ....................................4529
16.3.51PTM Control Register (PTMCTLR)—Offset 158h ........................................4530
16.3.52L1 Sub-States Extended Capability Header (L1SECH)—Offset 200h ............4530
16.3.53L1 Sub-States Capabilities (L1SCAP)—Offset 204h ...................................4531
16.3.54L1 Sub-States Control 1 (L1SCTL1)—Offset 208h.....................................4533
16.3.55L1 Sub-States Control 2 (L1SCTL2)—Offset 20Ch ....................................4534
16.3.56Secondary PCI Express Extended Capability Header (SPEECH)—Offset 220h 4535
16.3.57Link Control 3 (LCTL3)—Offset 224h ......................................................4536
16.3.58Lane Error Status (LES)—Offset 228h ....................................................4537
16.3.59Lane 0 and Lane 1 Equalization Control (L01EC)—Offset 22Ch ...................4538
16.3.60Lane 2 and Lane 3 Equalization Control (L23EC)—Offset 230h ...................4540
16.3.61PCI Express Replay Timer Policy 1 (PCIERTP1)—Offset 300h .....................4541

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 16.3.62PCI Express Replay Timer Policy 2 (PCIERTP2)—Offset 304h..................... 4543
16.3.63PCI Express Status 1 (PCIESTS1)—Offset 328h....................................... 4546
16.3.64PCI Express Status 2 (PCIESTS2)—Offset 32Ch....................................... 4550
16.3.65PCI Express Compliance Measurement Mode (CMM) Port Control (PCIECMMPC)—
Offset 330h........................................................................................ 4552
16.3.66PCI Express Compliance Measurement Mode Symbol Buffer (PCIECMMSB)—Offset
334h ................................................................................................. 4554
16.3.67PTM Propagation Delay (PTMPD)—Offset 390h ........................................ 4555
16.3.68PTM Lower Local Master Time (PTMLLMT)—Offset 394h ............................ 4555
16.3.69PTM Upper Local Master Time (PTMULMT)—Offset 398h ........................... 4556
16.3.70PTM Pipe Stage Delay Configuration 1 (PTMPSDC1)—Offset 39Ch .............. 4556
16.3.71PTM Pipe Stage Delay Configuration 2 (PTMPSDC2)—Offset 3A0h .............. 4557
16.3.72PTM Pipe Stage Delay Configuration 3 (PTMPSDC3)—Offset 3A4h .............. 4558
16.3.73PTM Pipe Stage Delay Configuration 4 (PTMPSDC4)—Offset 3A8h .............. 4560
16.3.74PTM Pipe Stage Delay Configuration 5 (PTMPSDC5)—Offset 3ACh .............. 4561
16.3.75PTM Extended Config (PTMECFG)—Offset 3B0h ....................................... 4562
16.3.76PTM Lower T2 Time Stamp (PTMLT2TSTMP)—Offset 3B4h ........................ 4565
16.3.77PTM Upper T2 Time Stamp (PTMUT2TSTMP)—Offset 3B8h ........................ 4566
16.3.78Strap Configuration 2 (STRPFUSECFG2)—Offset 414h .............................. 4566
16.3.79Thermal and Power Throttling (TNPT)—Offset 418h ................................. 4567
16.3.80Dynamic Lane Switch (DYNLNSW)—Offset 41Ch...................................... 4571
16.3.81Power Control Enable (PCE)—Offset 428h............................................... 4572
16.3.82PGCB Control1 (PGCBCTL1)—Offset 42Ch .............................................. 4573
16.3.83PGCB Control2 (PGCBCTL2)—Offset 430h............................................... 4576
16.3.84Equalization Configuration 1 (EQCFG1)—Offset 450h ............................... 4577
16.3.85Remote Transmitter Preset Coefficient List 1 (RTPCL1)—Offset 454h.......... 4583
16.3.86Remote Transmitter Preset Coefficient List 2 (RTPCL2)—Offset 458h.......... 4586
16.3.87Remote Transmitter Preset Coefficient List 3 (RTPCL3)—Offset 45Ch.......... 4589
16.3.88Remote Transmitter Preset Coefficient List 4 (RTPCL4)—Offset 460h.......... 4592
16.3.89Figure Of Merit Status (FOMS)—Offset 464h ........................................... 4595
16.3.90Hardware Autonomous Equalization Control (HAEQ)—Offset 468h ............. 4596
16.3.91Local Transmitter Coefficient Override 1 (LTCO1)—Offset 470h ................. 4599
16.3.92Local Transmitter Coefficient Override 2 (LTCO2)—Offset 474h ................. 4601
16.3.93GEN3 L0s Control (G3L0SCTL)—Offset 478h ........................................... 4603
16.3.94Equalization Configuration 2 (EQCFG2)—Offset 47Ch ............................... 4605
16.3.95Monitor Mux (MM)—Offset 480h............................................................ 4608
16.3.96Lane0 P0 and P1 Preset-Coefficient Mapping (L0P0P1PCM)—Offset 500h .... 4609
16.3.97Lane0 P1, P2 and P3 Preset-Coefficient Mapping (L0P1P2P3PCM)—Offset 504h...
4610
16.3.98Lane0 P3 and P4 Preset-Coefficient Mapping (L0P3P4PCM)—Offset 508h .... 4611
16.3.99Lane0 P5 and P6 Preset-Coefficient Mapping (L0P5P6PCM)—Offset 50Ch .... 4613
16.3.100Lane0 P6, P7 and P8 Preset-Coefficient Mapping (L0P6P7P8PCM)—Offset 510h .
4614
16.3.101Lane0 P8 and P9 Preset-Coefficient Mapping (L0P8P9PCM)—Offset 514h ... 4615
16.3.102Lane0 P10 Preset-Coefficient Mapping (L0P10PCM)—Offset 518h ............. 4616
16.3.103Lane0 LF and FS (L0LFFS)—Offset 51Ch ............................................... 4617
16.3.104Lane1 P0 and P1 Preset-Coefficient Mapping (L1P0P1PCM)—Offset 520h ... 4619
16.3.105Lane1 P1, P2 and P3 Preset-Coefficient Mapping (L1P1P2P3PCM)—Offset 524h .
4620
16.3.106Lane1 P3 and P4 Preset-Coefficient Mapping (L1P3P4PCM)—Offset 528h ... 4621
16.3.107Lane1 P5 and P6 Preset-Coefficient Mapping (L1P5P6PCM)—Offset 52Ch... 4622
16.3.108Lane1 P6, P7 and P8 Preset-Coefficient Mapping (L1P6P7P8PCM)—Offset 530h .
4624
16.3.109Lane1 P8 and P9 Preset-Coefficient Mapping (L1P8P9PCM)—Offset 534h ... 4625
16.3.110Lane1 P10 Preset-Coefficient Mapping (L1P10PCM)—Offset 538h ............. 4626

112 334818
 16.3.111Lane1 LF and FS (L1LFFS)—Offset 53Ch................................................4627
16.3.112Lane2 P0 and P1 Preset-Coefficient Mapping (L2P0P1PCM)—Offset 540h ...4628
16.3.113Lane2 P1, P2 and P3 Preset-Coefficient Mapping (L2P1P2P3PCM)—Offset 544h..
4629
16.3.114Lane2 P3 and P4 Preset-Coefficient Mapping (L2P3P4PCM)—Offset 548h ...4630
16.3.115Lane2 P5 and P6 Preset-Coefficient Mapping (L2P5P6PCM)—Offset 54Ch ...4632
16.3.116Lane2 P6, P7 and P8 Preset-Coefficient Mapping (L2P6P7P8PCM)—Offset 550h..
4633
16.3.117Lane2 P8 and P9 Preset-Coefficient Mapping (L2P8P9PCM)—Offset 554h ...4634
16.3.118Lane2 P10 Preset-Coefficient Mapping (L2P10PCM)—Offset 558h..............4635
16.3.119Lane2 LF and FS (L2LFFS)—Offset 55Ch................................................4636
16.3.120Lane3 P0 and P1 Preset-Coefficient Mapping (L3P0P1PCM)—Offset 560h ...4637
16.3.121Lane3 P1, P2 and P3 Preset-Coefficient Mapping (L3P1P2P3PCM)—Offset 564h..
4639
16.3.122Lane3 P3 and P4 Preset-Coefficient Mapping (L3P3P4PCM)—Offset 568h ...4640
16.3.123Lane3 P5 and P6 Preset-Coefficient Mapping (L3P5P6PCM)—Offset 56Ch ...4641
16.3.124Lane3 P6, P7 and P8 Preset-Coefficient Mapping (L3P6P7P8PCM)—Offset 570h..
4642
16.3.125Lane3 P8 and P9 Preset-Coefficient Mapping (L3P8P9PCM)—Offset 574h ...4643
16.3.126Lane3 P10 Preset-Coefficient Mapping (L3P10PCM)—Offset 578h..............4644
16.3.127Lane3 LF and FS (L3LFFS)—Offset 57Ch................................................4645
16.3.128Lane3 LF and FS (L3LFFS)—Offset 57Ch................................................4646
16.3.129PCLKD_L1TREF_CFG—Offset 1010h......................................................4648
17 SATA ....................................................................................................................4651
17.1 Registers Summary ........................................................................................4651
17.1.1 Command (CMD)—Offset 4h .................................................................4652
17.1.2 Device Status (STS)—Offset 6h .............................................................4653
17.1.3 Revision ID (RID)—Offset 8h ................................................................4654
17.1.4 Programming Interface (PI)—Offset 9h...................................................4654
17.1.5 Cache Line Size (CLS)—Offset Ch ..........................................................4655
17.1.6 Master Latency Timer (MLT)—Offset Dh..................................................4655
17.1.7 Header Type (HTYPE)—Offset Eh ...........................................................4656
17.1.8 MSI-X Table Base Address (MXTBA)—Offset 10h......................................4656
17.1.9 MXP Base Address (MXPBA)—Offset 14h.................................................4657
17.1.10SCMDBA (SCMDBA)—Offset 18h............................................................4658
17.1.11SCTLBA (SCTLBA)—Offset 1Ch ..............................................................4658
17.1.12AHCI Index Data Pair Base Address (AIDPBA)—Offset 20h ........................4659
17.1.13AHCI Base Address (ABAR)—Offset 24h..................................................4659
17.1.14Sub System Identifiers (SS)—Offset 2Ch ................................................4661
17.1.15Capabilities Pointer (CAP)—Offset 34h....................................................4661
17.1.16Interrupt Information (INTR)—Offset 3Ch ...............................................4662
17.1.17PCI Power Management Capability ID (PID)—Offset 70h ...........................4662
17.1.18PCI Power Management Control and Status (PMCS)—Offset 74h ................4663
17.1.19Message Signalled Interrupt Identifier (MID)—Offset 80h..........................4664
17.1.20Message Signalled Interrupt Message Control (MC)—Offset 82h .................4665
17.1.21Message Signalled Interrupt Message Data (MD)—Offset 88h ....................4665
17.1.22Port Mapping Register (MAP)—Offset 90h ...............................................4666
17.1.23SATA General Configuration (SATAGC)—Offset 9Ch..................................4667
17.1.24SATA Initialization Register Index (SIRI)—Offset A0h ...............................4670
17.1.25SATA Initialization Register Data (SIRD)—Offset A4h ...............................4671
17.1.26Serial ATA Capability Register 0 (SATACR0)—Offset A8h ...........................4671
17.1.27Serial ATA Capability Register 1 (SATACR1)—Offset ACh...........................4672
17.1.28FLR Capability ID (FLRCID)—Offset B0h .................................................4673
17.1.29FLR Capability Length and Version (FLRCAP)—Offset B2h..........................4673

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 17.1.30FLR Control (FLRCTL)—Offset B4h ......................................................... 4674
17.1.31Scratch Pad (SP)—Offset C0h ............................................................... 4675
17.1.32MSI-X Identifiers (MXID)—Offset D0h .................................................... 4675
17.1.33MSI-X Message Control (MXC)—Offset D2h ............................................ 4676
17.1.34MSI-X Table Offset / Table BIR (MXT)—Offset D4h .................................. 4676
17.1.35MSI-X PBA Offset / PBA BIR (MXP)—Offset D8h ...................................... 4677
17.1.36BIST FIS Control/Status (BFCS)—Offset E0h........................................... 4678
17.1.37BIST FIS Transmit Data 1 (BFTD1)—Offset E4h....................................... 4680
17.1.38BIST FIS Transmit Data 2 (BFTD2)—Offset E8h....................................... 4681
17.1.39Manufacturing ID (MFID)—Offset F8h .................................................... 4681
17.2 Registers Summary........................................................................................ 4682
17.2.1 AHCI Data Register (DATA)—Offset 14h................................................. 4682
17.3 Registers Summary........................................................................................ 4683
17.3.1 HBA Capabilities (GHC_CAP)—Offset 0h ................................................. 4684
17.3.2 Global HBA Control (GHC)—Offset 4h .................................................... 4687
17.3.3 Ports Implemented (GHC_PI)—Offset Ch................................................ 4688
17.3.4 AHCI Version (VS)—Offset 10h ............................................................. 4689
17.3.5 Enclosure Management Location (EM_LOC)—Offset 1Ch ........................... 4690
17.3.6 Enclosure Management Control (EM_CTL)—Offset 20h ............................. 4691
17.3.7 HBA Capabilities Extended (GHC_CAP2)—Offset 24h................................ 4692
17.3.8 Vendor Specific (VSP)—Offset A0h ........................................................ 4693
17.3.9 Vendor-Specific Capabilities Register (VS_CAP)—Offset A4h ..................... 4694
17.3.10Remapping Under NVMe (RUN)—Offset A8h ........................................... 4695
17.3.11RAID Platform ID (RPID)—Offset C0h .................................................... 4696
17.3.12Premium Feature Block (PFB)—Offset C4h.............................................. 4697
17.3.13SW Feature Mask (SFM)—Offset C8h ..................................................... 4697
17.3.14Port [0-7] Command List Base Address (PxCLB0)—Offset 100h ................. 4699
17.3.15Port [0-7] Command List Base Address Upper 32-bits (PxCLBU0)—Offset 104h ..
4699
17.3.16Port [0-7] FIS Base Address (PxFB0)—Offset 108h .................................. 4700
17.3.17Port [0-7] FIS Base Address Upper 32-bits (PxFBU0)—Offset 10Ch ............ 4700
17.3.18Port [0-7] Interrupt Status (PxIS0)—Offset 110h .................................... 4701
17.3.19Port [0-7] Interrupt Enable (PxIE0)—Offset 114h .................................... 4703
17.3.20Port [0-7] Command (PxCMD0)—Offset 118h ......................................... 4704
17.3.21Port [0-7] Task File Data (PxTFD0)—Offset 120h..................................... 4707
17.3.22Port [0-7] Signature (PxSIG0)—Offset 124h ........................................... 4708
17.3.23Port [0-7] Serial ATA Status (PxSSTS0)—Offset 128h .............................. 4708
17.3.24Port [0-7] Serial ATA Control (PxSCTL0)—Offset 12Ch ............................. 4709
17.3.25Port [0-7] Serial ATA Error (PxSERR0)—Offset 130h ................................ 4709
17.3.26Port [0-7] Serial ATA Active (PxSACT0)—Offset 134h............................... 4710
17.3.27Port [0-7] Commands Issued (PxCI0)—Offset 138h ................................. 4710
17.3.28Port [0-7] SNotification (PxSNTF0)—Offset 13Ch..................................... 4711
17.3.29Port [0-7] Device Sleep (PxDEVSLP0)—Offset 144h ................................. 4712
17.3.30Port [0-7] Command List Base Address (PxCLB1)—Offset 180h ................. 4713
17.3.31Port [0-7] Command List Base Address Upper 32-bits (PxCLBU1)—Offset 184h ..
4714
17.3.32Port [0-7] FIS Base Address (PxFB1)—Offset 188h .................................. 4714
17.3.33Port [0-7] FIS Base Address Upper 32-bits (PxFBU1)—Offset 18Ch ............ 4715
17.3.34Port [0-7] Interrupt Status (PxIS1)—Offset 190h .................................... 4715
17.3.35Port [0-7] Interrupt Enable (PxIE1)—Offset 194h .................................... 4717
17.3.36Port [0-7] Command (PxCMD1)—Offset 198h ......................................... 4719
17.3.37Port [0-7] Task File Data (PxTFD1)—Offset 1A0h..................................... 4721
17.3.38Port [0-7] Signature (PxSIG1)—Offset 1A4h ........................................... 4722
17.3.39Port [0-7] Serial ATA Status (PxSSTS1)—Offset 1A8h .............................. 4723
17.3.40Port [0-7] Serial ATA Control (PxSCTL1)—Offset 1ACh ............................. 4723

114 334818
 17.3.41Port [0-7] Serial ATA Error (PxSERR1)—Offset 1B0h ................................4724
17.3.42Port [0-7] Serial ATA Active (PxSACT1)—Offset 1B4h ...............................4724
17.3.43Port [0-7] Commands Issued (PxCI1)—Offset 1B8h .................................4725
17.3.44Port [0-7] SNotification (PxSNTF1)—Offset 1BCh .....................................4725
17.3.45Port [0-7] Device Sleep (PxDEVSLP1)—Offset 1C4h .................................4726
17.3.46Enclosure Management Message Format (EM_MF)—Offset 580h.................4728
17.3.47Enclosure Management LED (EM_LED)—Offset 584h ................................4728
17.4 Registers Summary ........................................................................................4729
17.4.1 MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)—Offset 0h ......................4730
17.4.2 MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)—Offset 4h ......................4730
17.5 Registers Summary ........................................................................................4731
17.5.1 MSI-X Table Entries 0 Message Lower Address (MXTE0MLA)—Offset 0h ......4731
17.5.2 MSI-X Table Entries 0 Message Upper Address (MXTE0MUA)—Offset 4h ......4732
17.5.3 MSI-X Table Entries 0 Message Data (MXTE0MD)—Offset 8h .....................4732
17.5.4 MSI-X Table Entries 0 Vector Control (MXTE0VC)—Offset Ch .....................4733
17.6 ...................................................................................................................4733
17.7 Registers Summary ........................................................................................4735
17.7.1 Command (CMD)—Offset 4h .................................................................4736
17.7.2 Device Status (STS)—Offset 6h .............................................................4737
17.7.3 Revision ID (RID)—Offset 8h ................................................................4738
17.7.4 Programming Interface (PI)—Offset 9h...................................................4738
17.7.5 Cache Line Size (CLS)—Offset Ch ..........................................................4739
17.7.6 Master Latency Timer (MLT)—Offset Dh..................................................4739
17.7.7 Header Type (HTYPE)—Offset Eh ...........................................................4740
17.7.8 MSI-X Table Base Address (MXTBA)—Offset 10h......................................4740
17.7.9 MXP Base Address (MXPBA)—Offset 14h.................................................4741
17.7.10SCMDBA (SCMDBA)—Offset 18h............................................................4741
17.7.11SCTLBA (SCTLBA)—Offset 1Ch ..............................................................4742
17.7.12AHCI Index Data Pair Base Address (AIDPBA)—Offset 20h ........................4743
17.7.13AHCI Base Address (ABAR)—Offset 24h..................................................4743
17.7.14Sub System Identifiers (SS)—Offset 2Ch ................................................4744
17.7.15Capabilities Pointer (CAP)—Offset 34h....................................................4745
17.7.16Interrupt Information (INTR)—Offset 3Ch ...............................................4745
17.7.17PCI Power Management Capability ID (PID)—Offset 70h ...........................4746
17.7.18PCI Power Management Control and Status (PMCS)—Offset 74h ................4746
17.7.19Message Signalled Interrupt Identifier (MID)—Offset 80h..........................4747
17.7.20Message Signalled Interrupt Message Control (MC)—Offset 82h .................4748
17.7.21Message Signalled Interrupt Message Data (MD)—Offset 88h ....................4749
17.7.22Port Mapping Register (MAP)—Offset 90h ...............................................4749
17.7.23SATA General Configuration (SATAGC)—Offset 9Ch..................................4751
17.7.24SATA Initialization Register Index (SIRI)—Offset A0h ...............................4754
17.7.25SATA Initialization Register Data (SIRD)—Offset A4h ...............................4754
17.7.26Serial ATA Capability Register 0 (SATACR0)—Offset A8h ...........................4755
17.7.27Serial ATA Capability Register 1 (SATACR1)—Offset ACh...........................4756
17.7.28FLR Capability ID (FLRCID)—Offset B0h .................................................4756
17.7.29FLR Capability Length and Version (FLRCAP)—Offset B2h..........................4757
17.7.30FLR Control (FLRCTL)—Offset B4h .........................................................4758
17.7.31Scratch Pad (SP)—Offset C0h................................................................4758
17.7.32MSI-X Identifiers (MXID)—Offset D0h ....................................................4759
17.7.33MSI-X Message Control (MXC)—Offset D2h .............................................4759
17.7.34MSI-X Table Offset / Table BIR (MXT)—Offset D4h...................................4760
17.7.35MSI-X PBA Offset / PBA BIR (MXP)—Offset D8h .......................................4761
17.7.36BIST FIS Control/Status (BFCS)—Offset E0h ...........................................4761
17.7.37BIST FIS Transmit Data 1 (BFTD1)—Offset E4h .......................................4764
17.7.38BIST FIS Transmit Data 2 (BFTD2)—Offset E8h .......................................4765

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 17.7.39Manufacturing ID (MFID)—Offset F8h .................................................... 4765
17.8 Registers Summary........................................................................................ 4767
17.8.1 AHCI Data Register (DATA)—Offset 14h................................................. 4767
17.9 Registers Summary........................................................................................ 4769
17.9.1 HBA Capabilities (GHC_CAP)—Offset 0h ................................................. 4770
17.9.2 Global HBA Control (GHC)—Offset 4h .................................................... 4772
17.9.3 Ports Implemented (GHC_PI)—Offset Ch................................................ 4774
17.9.4 AHCI Version (VS)—Offset 10h ............................................................. 4775
17.9.5 Enclosure Management Location (EM_LOC)—Offset 1Ch ........................... 4776
17.9.6 Enclosure Management Control (EM_CTL)—Offset 20h ............................. 4776
17.9.7 HBA Capabilities Extended (GHC_CAP2)—Offset 24h................................ 4778
17.9.8 Vendor Specific (VSP)—Offset A0h ........................................................ 4779
17.9.9 Vendor-Specific Capabilities Register (VS_CAP)—Offset A4h ..................... 4780
17.9.10Remapping Under NVMe (RUN)—Offset A8h ........................................... 4781
17.9.11RAID Platform ID (RPID)—Offset C0h .................................................... 4782
17.9.12Premium Feature Block (PFB)—Offset C4h.............................................. 4782
17.9.13SW Feature Mask (SFM)—Offset C8h ..................................................... 4783
17.9.14Port [0-7] Command List Base Address (PxCLB0)—Offset 100h ................. 4784
17.9.15Port [0-7] Command List Base Address Upper 32-bits (PxCLBU0)—Offset 104h ..
4785
17.9.16Port [0-7] FIS Base Address (PxFB0)—Offset 108h .................................. 4785
17.9.17Port [0-7] FIS Base Address Upper 32-bits (PxFBU0)—Offset 10Ch ............ 4786
17.9.18Port [0-7] Interrupt Status (PxIS0)—Offset 110h .................................... 4786
17.9.19Port [0-7] Interrupt Enable (PxIE0)—Offset 114h .................................... 4788
17.9.20Port [0-7] Command (PxCMD0)—Offset 118h ......................................... 4790
17.9.21Port [0-7] Task File Data (PxTFD0)—Offset 120h..................................... 4792
17.9.22Port [0-7] Signature (PxSIG0)—Offset 124h ........................................... 4793
17.9.23Port [0-7] Serial ATA Status (PxSSTS0)—Offset 128h .............................. 4794
17.9.24Port [0-7] Serial ATA Control (PxSCTL0)—Offset 12Ch ............................. 4794
17.9.25Port [0-7] Serial ATA Error (PxSERR0)—Offset 130h ................................ 4795
17.9.26Port [0-7] Serial ATA Active (PxSACT0)—Offset 134h............................... 4795
17.9.27Port [0-7] Commands Issued (PxCI0)—Offset 138h ................................. 4796
17.9.28Port [0-7] SNotification (PxSNTF0)—Offset 13Ch..................................... 4796
17.9.29Port [0-7] Device Sleep (PxDEVSLP0)—Offset 144h ................................. 4797
17.9.30Port [0-7] Command List Base Address (PxCLB1)—Offset 180h ................. 4799
17.9.31Port [0-7] Command List Base Address Upper 32-bits (PxCLBU1)—Offset 184h ..
4799
17.9.32Port [0-7] FIS Base Address (PxFB1)—Offset 188h .................................. 4800
17.9.33Port [0-7] FIS Base Address Upper 32-bits (PxFBU1)—Offset 18Ch ............ 4800
17.9.34Port [0-7] Interrupt Status (PxIS1)—Offset 190h .................................... 4801
17.9.35Port [0-7] Interrupt Enable (PxIE1)—Offset 194h .................................... 4803
17.9.36Port [0-7] Command (PxCMD1)—Offset 198h ......................................... 4804
17.9.37Port [0-7] Task File Data (PxTFD1)—Offset 1A0h..................................... 4807
17.9.38Port [0-7] Signature (PxSIG1)—Offset 1A4h ........................................... 4808
17.9.39Port [0-7] Serial ATA Status (PxSSTS1)—Offset 1A8h .............................. 4808
17.9.40Port [0-7] Serial ATA Control (PxSCTL1)—Offset 1ACh ............................. 4809
17.9.41Port [0-7] Serial ATA Error (PxSERR1)—Offset 1B0h ................................ 4809
17.9.42Port [0-7] Serial ATA Active (PxSACT1)—Offset 1B4h .............................. 4810
17.9.43Port [0-7] Commands Issued (PxCI1)—Offset 1B8h ................................. 4810
17.9.44Port [0-7] SNotification (PxSNTF1)—Offset 1BCh..................................... 4811
17.9.45Port [0-7] Device Sleep (PxDEVSLP1)—Offset 1C4h ................................. 4812
17.9.46Enclosure Management Message Format (EM_MF)—Offset 580h ................ 4813
17.9.47Enclosure Management LED (EM_LED)—Offset 584h................................ 4814
17.10 Registers Summary........................................................................................ 4817
17.10.1MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)—Offset 0h ...................... 4817

116 334818
 17.10.2MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)—Offset 4h ......................4817
17.11 Registers Summary ........................................................................................4819
17.11.1MSI-X Table Entries 0 Message Lower Address (MXTE0MLA)—Offset 0h ......4819
17.11.2MSI-X Table Entries 0 Message Upper Address (MXTE0MUA)—Offset 4h ......4819
17.11.3MSI-X Table Entries 0 Message Data (MXTE0MD)—Offset 8h .....................4820
17.11.4MSI-X Table Entries 0 Vector Control (MXTE0VC)—Offset Ch .....................4820
18 USB ......................................................................................................................4823
18.1 Registers Summary ........................................................................................4823
18.1.1 Capability Registers Length (CAPLENGTH)—Offset 0h ...............................4836
18.1.2 Host Controller Interface Version Number (HCIVERSION)—Offset 2h ..........4836
18.1.3 Structural Parameters 1 (HCSPARAMS1)—Offset 4h .................................4837
18.1.4 Structural Parameters 2 (HCSPARAMS2)—Offset 8h .................................4837
18.1.5 Structural Parameters 3 (HCSPARAMS3)—Offset Ch .................................4838
18.1.6 Capability Parameters (HCCPARAMS)—Offset 10h ....................................4839
18.1.7 Doorbell Offset (DBOFF)—Offset 14h......................................................4840
18.1.8 Runtime Register Space Offset (RTSOFF)—Offset 18h...............................4840
18.1.9 USB Command (USBCMD)—Offset 80h...................................................4840
18.1.10USB Status (USBSTS)—Offset 84h .........................................................4841
18.1.11Page Size (PAGESIZE)—Offset 88h ........................................................4842
18.1.12Device Notification Control (DNCTRL)—Offset 94h....................................4843
18.1.13Command Ring Low (CRCR_LO)—Offset 98h ...........................................4843
18.1.14Command Ring High (CRCR_HI)—Offset 9Ch...........................................4844
18.1.15Device Context Base Address Array Pointer Low (DCBAAP_LO)—Offset B0h.4844
18.1.16Device Context Base Address Array Pointer High (DCBAAP_HI)—Offset B4h 4845
18.1.17Configure (CONFIG)—Offset B8h ...........................................................4845
18.1.18Port Status and Control USB2 (PORTSC1)—Offset 480h ............................4845
18.1.19Port Power Management Status and Control USB2 (PORTPMSC1)—Offset 484h ...
4847
18.1.20Port X Hardware LPM Control Register (PORTHLPMC1)—Offset 48Ch...........4848
18.1.21Port Status and Control USB2 (PORTSC2)—Offset 490h ............................4848
18.1.22Port Power Management Status and Control USB2 (PORTPMSC2)—Offset 494h ...
4850
18.1.23Port X Hardware LPM Control Register (PORTHLPMC2)—Offset 49Ch...........4851
18.1.24Port Status and Control USB2 (PORTSC3)—Offset 4A0h ............................4851
18.1.25Port Power Management Status and Control USB2 (PORTPMSC3)—Offset 4A4h...
4853
18.1.26Port X Hardware LPM Control Register (PORTHLPMC3)—Offset 4ACh...........4854
18.1.27Port Status and Control USB2 (PORTSC4)—Offset 4B0h ............................4854
18.1.28Port Power Management Status and Control USB2 (PORTPMSC4)—Offset 4B4h...
4856
18.1.29Port X Hardware LPM Control Register (PORTHLPMC4)—Offset 4BCh...........4857
18.1.30Port Status and Control USB2 (PORTSC5)—Offset 4C0h ............................4857
18.1.31Port Power Management Status and Control USB2 (PORTPMSC5)—Offset 4C4h...
4859
18.1.32Port X Hardware LPM Control Register (PORTHLPMC5)—Offset 4CCh ..........4860
18.1.33Port Status and Control USB2 (PORTSC6)—Offset 4D0h............................4860
18.1.34Port Power Management Status and Control USB2 (PORTPMSC6)—Offset 4D4h...
4862
18.1.35Port X Hardware LPM Control Register (PORTHLPMC6)—Offset 4DCh ..........4863
18.1.36Port Status and Control USB2 (PORTSC7)—Offset 4E0h ............................4863
18.1.37Port Power Management Status and Control USB2 (PORTPMSC7)—Offset 4E4h ...
4865
18.1.38Port X Hardware LPM Control Register (PORTHLPMC7)—Offset 4ECh...........4866
18.1.39Port Status and Control USB2 (PORTSC8)—Offset 4F0h ............................4866

334818 117
 18.1.40Port Power Management Status and Control USB2 (PORTPMSC8)—Offset 4F4h ..
4868
18.1.41Port X Hardware LPM Control Register (PORTHLPMC8)—Offset 4FCh .......... 4869
18.1.42Port Status and Control USB3 (PORTSC9)—Offset 500h ........................... 4869
18.1.43Port Power Management Status and Control USB3 (PORTPMSC9)—Offset 504h ..
4871
18.1.44USB3 Port Link Info (PORTLI9)—Offset 508h .......................................... 4871
18.1.45Port Status and Control USB3 (PORTSC10)—Offset 510h.......................... 4872
18.1.46Port Power Management Status and Control USB3 (PORTPMSC10)—Offset 514h.
4873
18.1.47USB3 Port Link Info (PORTLI10)—Offset 518h......................................... 4874
18.1.48Port Status and Control USB3 (PORTSC11)—Offset 520h.......................... 4874
18.1.49Port Power Management Status and Control USB3 (PORTPMSC11)—Offset 524h.
4876
18.1.50USB3 Port Link Info (PORTLI11)—Offset 528h......................................... 4876
18.1.51Port Status and Control USB3 (PORTSC12)—Offset 530h.......................... 4877
18.1.52Port Power Management Status and Control USB3 (PORTPMSC12)—Offset 534h.
4878
18.1.53USB3 Port Link Info (PORTLI12)—Offset 538h......................................... 4879
18.1.54Port Status and Control USB3 (PORTSC13)—Offset 540h.......................... 4879
18.1.55Port Power Management Status and Control USB3 (PORTPMSC13)—Offset 544h.
4881
18.1.56USB3 Port Link Info (PORTLI13)—Offset 548h......................................... 4881
18.1.57Port Status and Control USB3 (PORTSC14)—Offset 550h.......................... 4882
18.1.58Port Power Management Status and Control USB3 (PORTPMSC14)—Offset 554h.
4883
18.1.59USB3 Port Link Info (PORTLI14)—Offset 558h......................................... 4884
18.1.60Port Status and Control USB3 (PORTSC15)—Offset 560h.......................... 4884
18.1.61Port Power Management Status and Control USB3 (PORTPMSC15)—Offset 564h.
4886
18.1.62USB3 Port Link Info (PORTLI15)—Offset 568h......................................... 4886
18.1.63Microframe Index (RTMFINDEX)—Offset 2000h ....................................... 4887
18.1.64Interrupter 1 Management (IMAN0)—Offset 2020h.................................. 4887
18.1.65Interrupter 1 Moderation (IMOD0)—Offset 2024h.................................... 4888
18.1.66Event Ring Segment Table Size 1 (ERSTSZ0)—Offset 2028h ..................... 4888
18.1.67Event Ring Segment Table Base Address Low 1 (ERSTBA_LO0)—Offset 2030h ...
4889
18.1.68Event Ring Segment Table Base Address High 1 (ERSTBA_HI0)—Offset 2034h ...
4889
18.1.69Event Ring Dequeue Pointer Low 1 (ERDP_LO0)—Offset 2038h ................. 4890
18.1.70Event Ring Dequeue Pointer High 1 (ERDP_HI0)—Offset 203Ch................. 4890
18.1.71Interrupter 2 Management (IMAN1)—Offset 2040h.................................. 4891
18.1.72Interrupter 2 Moderation (IMOD1)—Offset 2044h.................................... 4891
18.1.73Event Ring Segment Table Size 2 (ERSTSZ1)—Offset 2048h ..................... 4892
18.1.74Event Ring Segment Table Base Address Low 2 (ERSTBA_LO1)—Offset 2050h ...
4892
18.1.75Event Ring Segment Table Base Address High 2 (ERSTBA_HI1)—Offset 2054h ...
4893
18.1.76Event Ring Dequeue Pointer Low 2 (ERDP_LO1)—Offset 2058h ................. 4893
18.1.77Event Ring Dequeue Pointer High 2 (ERDP_HI1)—Offset 205Ch................. 4894
18.1.78Interrupter 3 Management (IMAN2)—Offset 2060h.................................. 4894
18.1.79Interrupter 3 Moderation (IMOD2)—Offset 2064h.................................... 4895
18.1.80Event Ring Segment Table Size 3 (ERSTSZ2)—Offset 2068h ..................... 4895
18.1.81Event Ring Segment Table Base Address Low 3 (ERSTBA_LO2)—Offset 2070h ...
4896

118 334818
 18.1.82Event Ring Segment Table Base Address High 3 (ERSTBA_HI2)—Offset 2074h ...
4896
18.1.83Event Ring Dequeue Pointer Low 3 (ERDP_LO2)—Offset 2078h..................4897
18.1.84Event Ring Dequeue Pointer High 3 (ERDP_HI2)—Offset 207Ch .................4897
18.1.85Interrupter 4 Management (IMAN3)—Offset 2080h ..................................4898
18.1.86Interrupter 4 Moderation (IMOD3)—Offset 2084h ....................................4898
18.1.87Event Ring Segment Table Size 4 (ERSTSZ3)—Offset 2088h .....................4899
18.1.88Event Ring Segment Table Base Address Low 4 (ERSTBA_LO3)—Offset 2090h....
4899
18.1.89Event Ring Segment Table Base Address High 4 (ERSTBA_HI3)—Offset 2094h ...
4900
18.1.90Event Ring Dequeue Pointer Low 4 (ERDP_LO3)—Offset 2098h..................4900
18.1.91Event Ring Dequeue Pointer High 4 (ERDP_HI3)—Offset 209Ch .................4901
18.1.92Interrupter 5 Management (IMAN4)—Offset 20A0h ..................................4901
18.1.93Interrupter 5 Moderation (IMOD4)—Offset 20A4h ....................................4902
18.1.94Event Ring Segment Table Size 5 (ERSTSZ4)—Offset 20A8h .....................4902
18.1.95Event Ring Segment Table Base Address Low 5 (ERSTBA_LO4)—Offset 20B0h....
4903
18.1.96Event Ring Segment Table Base Address High 5 (ERSTBA_HI4)—Offset 20B4h ...
4903
18.1.97Event Ring Dequeue Pointer Low 5 (ERDP_LO4)—Offset 20B8h..................4904
18.1.98Event Ring Dequeue Pointer High 5 (ERDP_HI4)—Offset 20BCh .................4904
18.1.99Interrupter 6 Management (IMAN5)—Offset 20C0h ..................................4905
18.1.100Interrupter 6 Moderation (IMOD5)—Offset 20C4h...................................4905
18.1.101Event Ring Segment Table Size 6 (ERSTSZ5)—Offset 20C8h....................4906
18.1.102Event Ring Segment Table Base Address Low 6 (ERSTBA_LO5)—Offset 20D0h ..
4906
18.1.103Event Ring Segment Table Base Address High 6 (ERSTBA_HI5)—Offset 20D4h..
4907
18.1.104Event Ring Dequeue Pointer Low 6 (ERDP_LO5)—Offset 20D8h ................4907
18.1.105Event Ring Dequeue Pointer High 6 (ERDP_HI5)—Offset 20DCh ...............4908
18.1.106Interrupter 7 Management (IMAN6)—Offset 20E0h.................................4908
18.1.107Interrupter 7 Moderation (IMOD6)—Offset 20E4h ...................................4909
18.1.108Event Ring Segment Table Size 7 (ERSTSZ6)—Offset 20E8h ....................4909
18.1.109Event Ring Segment Table Base Address Low 7 (ERSTBA_LO6)—Offset 20F0h ..
4910
18.1.110Event Ring Segment Table Base Address High 7 (ERSTBA_HI6)—Offset 20F4h ..
4910
18.1.111Event Ring Dequeue Pointer Low 7 (ERDP_LO6)—Offset 20F8h ................4911
18.1.112Event Ring Dequeue Pointer High 7 (ERDP_HI6)—Offset 20FCh ................4911
18.1.113Interrupter 8 Management (IMAN7)—Offset 2100h.................................4912
18.1.114Interrupter 8 Moderation (IMOD7)—Offset 2104h ...................................4912
18.1.115Event Ring Segment Table Size 8 (ERSTSZ7)—Offset 2108h ....................4913
18.1.116Event Ring Segment Table Base Address Low 8 (ERSTBA_LO7)—Offset 2110h ..
4913
18.1.117Event Ring Segment Table Base Address High 8 (ERSTBA_HI7)—Offset 2114h ..
4914
18.1.118Event Ring Dequeue Pointer Low 8 (ERDP_LO7)—Offset 2118h ................4914
18.1.119Event Ring Dequeue Pointer High 8 (ERDP_HI7)—Offset 211Ch................4915
18.1.120Door Bell 1 (DB0)—Offset 3000h..........................................................4915
18.1.121Door Bell 2 (DB1)—Offset 3004h..........................................................4916
18.1.122Door Bell 3 (DB2)—Offset 3008h..........................................................4916
18.1.123Door Bell 4 (DB3)—Offset 300Ch .........................................................4917
18.1.124Door Bell 5 (DB4)—Offset 3010h..........................................................4917
18.1.125Door Bell 6 (DB5)—Offset 3014h..........................................................4918
18.1.126Door Bell 7 (DB6)—Offset 3018h..........................................................4918

334818 119
 18.1.127Door Bell 8 (DB7)—Offset 301Ch ......................................................... 4919
18.1.128Door Bell 9 (DB8)—Offset 3020h ......................................................... 4919
18.1.129Door Bell 10 (DB9)—Offset 3024h ....................................................... 4920
18.1.130Door Bell 11 (DB10)—Offset 3028h...................................................... 4920
18.1.131Door Bell 12 (DB11)—Offset 302Ch ..................................................... 4921
18.1.132Door Bell 13 (DB12)—Offset 3030h...................................................... 4922
18.1.133Door Bell 14 (DB13)—Offset 3034h...................................................... 4922
18.1.134Door Bell 15 (DB14)—Offset 3038h...................................................... 4923
18.1.135Door Bell 16 (DB15)—Offset 303Ch ..................................................... 4923
18.1.136Door Bell 17 (DB16)—Offset 3040h...................................................... 4924
18.1.137Door Bell 18 (DB17)—Offset 3044h...................................................... 4924
18.1.138Door Bell 19 (DB18)—Offset 3048h...................................................... 4925
18.1.139Door Bell 20 (DB19)—Offset 304Ch ..................................................... 4925
18.1.140Door Bell 21 (DB20)—Offset 3050h...................................................... 4926
18.1.141Door Bell 22 (DB21)—Offset 3054h...................................................... 4926
18.1.142Door Bell 23 (DB22)—Offset 3058h...................................................... 4927
18.1.143Door Bell 24 (DB23)—Offset 305Ch ..................................................... 4928
18.1.144Door Bell 25 (DB24)—Offset 3060h...................................................... 4928
18.1.145Door Bell 26 (DB25)—Offset 3064h...................................................... 4929
18.1.146Door Bell 27 (DB26)—Offset 3068h...................................................... 4929
18.1.147Door Bell 28 (DB27)—Offset 306Ch ..................................................... 4930
18.1.148Door Bell 29 (DB28)—Offset 3070h...................................................... 4930
18.1.149Door Bell 30 (DB29)—Offset 3074h...................................................... 4931
18.1.150Door Bell 31 (DB30)—Offset 3078h...................................................... 4931
18.1.151Door Bell 32 (DB31)—Offset 307Ch ..................................................... 4932
18.1.152Door Bell 32 (DB32)—Offset 3080h...................................................... 4932
18.1.153XECP_SUPP_USB2_0 (XECP_SUPP_USB2_0)—Offset 8000h .................... 4933
18.1.154XECP_SUPP_USB2_1 (XECP_SUPP_USB2_1)—Offset 8004h .................... 4934
18.1.155XECP_SUPP_USB2_2 (XECP_SUPP_USB2_2)—Offset 8008h .................... 4934
18.1.156XECP_SUPP_USB2_3 (Full Speed) (XECP_SUPP_USB2_3)—Offset 8010h .. 4935
18.1.157XECP_SUPP_USB2_4 (Low Speed) (XECP_SUPP_USB2_4)—Offset 8014h .. 4936
18.1.158XECP_SUPP_USB2_5 (High Speed) (XECP_SUPP_USB2_5)—Offset 8018h . 4936
18.1.159XECP_SUPP_USB3_0 (XECP_SUPP_USB3_0)—Offset 8020h .................... 4937
18.1.160XECP_SUPP_USB3_1 (XECP_SUPP_USB3_1)—Offset 8024h .................... 4938
18.1.161XECP_SUPP_USB3_2 (XECP_SUPP_USB3_2)—Offset 8028h .................... 4938
18.1.162XECP_SUPP_USB3_3 (XECP_SUPP_USB3_3)—Offset 8030h .................... 4939
18.1.163XECP_SUPP_USB3_4 (XECP_SUPP_USB3_4)—Offset 8034h .................... 4939
18.1.164XECP_SUPP_USB3_5 (XECP_SUPP_USB3_5)—Offset 8038h .................... 4940
18.1.165XECP_SUPP_USB3_6 (XECP_SUPP_USB3_6)—Offset 803Ch .................... 4941
18.1.166XECP_SUPP_USB3_7 (XECP_SUPP_USB3_7)—Offset 8040h .................... 4941
18.1.167XECP_SUPP_USB3_8 (XECP_SUPP_USB3_8)—Offset 8044h .................... 4942
18.1.168XECP_SUPP_USB3_9 (XECP_SUPP_USB3_9)—Offset 8048h .................... 4943
18.1.169Host Controller Capability (HOST_CTRL_CAP_REG)—Offset 8070h ........... 4943
18.1.170Override EP Flow Control (HOST_CLR_MASK_REG)—Offset 8078h............ 4944
18.1.171Clear Active IN EP ID Control (HOST_CLR_IN_EP_VALID_REG)—Offset 807Ch ..
4945
18.1.172Clear Poll Mask Control (HOST_CLR_PMASK_REG)—Offset 8080h ............ 4945
18.1.173Host Control Scheduler (HOST_CTRL_SCH_REG)—Offset 8094h............... 4946
18.1.174Global Port Control (HOST_CTRL_PORT_CTRL)—Offset 80A0h ................. 4947
18.1.175PGCB Control (PGCBCTRL_REG)—Offset 80A8h ..................................... 4948
18.1.176D0I3 Control (DOI3CTRL_REG)—Offset 80ACh ...................................... 4951
18.1.177HOST_CTRL_MISC_REG (HOST_CTRL_MISC_REG)—Offset 80B0h............ 4952
18.1.178HOST_CTRL_MISC_REG2 (HOST_CTRL_MISC_REG2)—Offset 80B4h ........ 4954
18.1.179SSPE_REG (SSPE_REG)—Offset 80B8h................................................. 4956
18.1.180(SSPITPE)—Offset 80BCh ................................................................... 4956

120 334818
 18.1.181AUX Reset Control (AUX_CTRL_REG)—Offset 80C0h ...............................4957
18.1.182Super Speed Bandwidth Overload (HOST_BW_OV_SS_REG)—Offset 80C4h ......
4959
18.1.183High Speed TT Bandwidth Overload (HOST_BW_OV_HS_REG)—Offset 80C8h ...
4960
18.1.184Bandwidth Overload Full Low Speed (HOST_BW_OV_FS_LS_REG)—Offset
80CCh ...............................................................................................4961
18.1.185System Bandwidth Overload (HOST_BW_OV_SYS_REG)—Offset 80D0h.....4961
18.1.186Scheduler Async Delay (HOST_CTRL_SCH_ASYNC_DELAY_REG)—Offset 80D4h
4962
18.1.187DEVICE MODE CONTROL REG 0 (DUAL_ROLE_CFG_REG0)—Offset 80D8h .4963
18.1.188DEVICE MODE CONTROL REG 1 (DUAL_ROLE_CFG_REG1)—Offset 80DCh .4965
18.1.189AUX Power Management Control (AUX_CTRL_REG1)—Offset 80E0h ..........4966
18.1.190Battery Charge (BATTERY_CHARGE_REG)—Offset 80E4h ........................4968
18.1.191Port Watermark (HOST_CTRL_WATERMARK_REG)—Offset 80E8h .............4969
18.1.192SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG)—Offset 80ECh ...
4969
18.1.193USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1)—Offset 80F0h ..4971
18.1.194USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2)—Offset 80F4h ..4973
18.1.195USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3)—Offset 80F8h ..4974
18.1.196USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4)—Offset 80FCh ..4974
18.1.197Bandwidth Calc Control (HOST_CTRL_BW_CTRL_REG)—Offset 8100h .......4975
18.1.198Host Interface Control (HOST_IF_CTRL_REG)—Offset 8108h ...................4975
18.1.199Bandwidth Overload Burst (HOST_BW_OV_BURST_REG)—Offset 810Ch ....4976
18.1.200USB Max Bandwidth Control 4 (HOST_CTRL_BW_MAX_REG)—Offset 8128h ......
4977
18.1.201USB2 Linestate Debug (LINESTATE_DEBUG_REG)—Offset 8130h .............4977
18.1.202USB2 Protocol Gap Timer (USB2_PROTOCOL_GAP_TIMER_REG)—Offset 8134h .
4978
18.1.203USB2 Protocol Bus Timeout Timer (USB2_PROTOCOL_BTO_TIMER_REG)—Offset
813Ch ...............................................................................................4979
18.1.204Power Scheduler Control-0 (PWR_SCHED_CTRL0)—Offset 8140h .............4980
18.1.205Power Scheduler Control-2 (PWR_SCHED_CTRL2)—Offset 8144h .............4980
18.1.206AUX Power Management Control (AUX_CTRL_REG2)—Offset 8154h ..........4981
18.1.207USB2 PHY Power Management Control (USB2_PHY_PMC)—Offset 8164h ...4984
18.1.208USB Power Gating Control (USB_PGC)—Offset 8168h .............................4985
18.1.209xHCI Aux Clock Control Register (XHCI_AUX_CCR)—Offset 816Ch ............4986
18.1.210USB LPM Parameters (USB_LPM_PARAM)—Offset 8170h .........................4988
18.1.211xHC Latency Tolerance Parameters - LTV Control (XLTP_LTV1)—Offset 8174h...
4989
18.1.212xHC Latency Tolerance Parameters LTV Control 2 (XLTP_LTV2)—Offset 8178h ..
4990
18.1.213xHC Latency Tolerance Parameters - High Idle Time Control (XLTP_HITC)—Offset
817Ch ...............................................................................................4991
18.1.214xHC Latency Tolerance Parameters - Medium Idle Time Control (XLTP_MITC)—
Offset 8180h ......................................................................................4992
18.1.215xHC Latency Tolerance Parameters Low Idle Time Control (XLTP_LITC)—Offset
8184h................................................................................................4993
18.1.216HOST_CTRL_BW_MAX3_REG (HOST_CTRL_BW_MAX3_REG)—Offset 8188h......
4993
18.1.217PDDIS_REG (PDDIS_REG)—Offset 8198h ..............................................4994
18.1.218LFPS_PM_CTRL_REG (LFPS_PM_CTRL_REG)—Offset 81A0h .....................4994
18.1.219U2PDM (U2PDM)—Offset 81A4h ...........................................................4995
18.1.220U2PCM (U2PCM)—Offset 81A8h ...........................................................4995
18.1.221U3PDM (U3PDM)—Offset 81ACh...........................................................4996
18.1.222U3PCM (U3PCM)—Offset 81B0h ...........................................................4996

334818 121
 18.1.223THRM_HOST_CTRL_REG2 (THRM_HOST_CTRL_REG2)—Offset 81B4h ....... 4997
18.1.224(D0i2_CTRL_REG)—Offset 81BCh ........................................................ 4997
18.1.225 (D0i2_SCH_ALARM_CTRL_REG)—Offset 81C0h .................................... 4999
18.1.226 (USB2PMCTRL_REG)—Offset 81C4h .................................................... 5000
18.1.227ECC_PARITY_ERROR_LOG_REG (ECC_PARITY_ERROR_LOG_REG)—Offset
83F8h ............................................................................................... 5002
18.1.228ECC_POISONING_CTRL_REG (ECC_POISONING_CTRL_REG)—Offset 83FCh .....
5004
18.1.229USB2_PORT_STATE_REG (USB2_PORT_STATE_REG)—Offset 8400h ........ 5005
18.1.230USB3_PORT_STATE_REG (USB3_PORT_STATE_REG)—Offset 8408h ........ 5006
18.1.231FUS1_REG (FUS1_REG)—Offset 8410h................................................. 5006
18.1.232FUS2_REG (FUS2_REG)—Offset 8414h................................................. 5007
18.1.233FUS3_REG (FUS3_REG)—Offset 8418h................................................. 5008
18.1.234STRAP1_REG (STRAP1_REG)—Offset 841Ch ......................................... 5008
18.1.235STRAP3_REG (STRAP3_REG)—Offset 8424h.......................................... 5009
18.1.236XECP_CMDM_STS0 (XECP_CMDM_STS0)—Offset 8448h ......................... 5010
18.1.237XECP_CMDM_STS1 (XECP_CMDM_STS1)—Offset 844Ch ......................... 5011
18.1.238XECP_CMDM_STS2 (XECP_CMDM_STS2)—Offset 8450h ......................... 5012
18.1.239XECP_CMDM_STS3 (XECP_CMDM_STS3)—Offset 8454h ......................... 5012
18.1.240XECP_CMDM_STS4 (XECP_CMDM_STS4)—Offset 8458h ......................... 5013
18.1.241XECP_CMDM_STS5 (XECP_CMDM_STS5)—Offset 845Ch ......................... 5013
18.1.242AUX Power PHY Reset (UPORTS_PON_RST_REG)—Offset 8460h .............. 5014
18.1.243Latency Tolerance Control 0 (HOST_IF_LAT_TOL_CTRL_REG0)—Offset 8464h ..
5014
18.1.244USB Legacy Support Capability (USBLEGSUP)—Offset 846Ch .................. 5015
18.1.245USB Legacy Support Control Status (USBLEGCTLSTS)—Offset 8470h ....... 5016
18.1.246Port Disable Override capability register (PDO_CAPABILITY)—Offset 84F4h5017
18.1.247USB2 Port Disable Override (USB2PDO)—Offset 84F8h ........................... 5017
18.1.248USB3 Port Disable Override (USB3PDO)—Offset 84FCh........................... 5018
18.1.249HW state capability register (HW_STATE_CAPABILITY)—Offset 8500h ...... 5018
18.1.250HW state register 1 (HW_STATE_REG1)—Offset 8504h........................... 5019
18.1.251HW state register 2 (HW_STATE_REG2)—Offset 8508h........................... 5019
18.1.252HW state register 3 (HW_STATE_REG3)—Offset 850Ch .......................... 5020
18.1.253HW state register 4 (HW_STATE_REG4)—Offset 8510h........................... 5020
18.1.254CONFIG mirror capability register (CONFIG_MIRROR_CAPABILITY)—Offset
8600h ............................................................................................... 5021
18.1.255Command (CMD_MMIO)—Offset 8604h ................................................ 5021
18.1.256Device Status (STS_MMIO)—Offset 8606h ............................................ 5023
18.1.257Revision ID (RID_MMIO)—Offset 8608h ............................................... 5024
18.1.258Programming Interface (PI_MMIO)—Offset 8609h.................................. 5024
18.1.259Sub Class Code (SCC_MMIO)—Offset 860Ah ......................................... 5025
18.1.260Base Class Code (BCC_MMIO)—Offset 860Bh ........................................ 5025
18.1.261Master Latency Timer (MLT_MMIO)—Offset 860Dh................................. 5025
18.1.262Header Type (HT_MMIO)—Offset 860Eh ............................................... 5026
18.1.263Memory Base Address (MBAR_MMIO)—Offset 8610h .............................. 5026
18.1.264USB Subsystem Vendor ID (SSVID_MMIO)—Offset 862Ch ...................... 5027
18.1.265USB Subsystem ID (SSID_MMIO)—Offset 862Eh ................................... 5027
18.1.266Capabilities Pointer (CAP_PTR_MMIO)—Offset 8634h.............................. 5028
18.1.267Interrupt Line (ILINE_MMIO)—Offset 863Ch.......................................... 5028
18.1.268Interrupt Pin (IPIN_MMIO)—Offset 863Dh ............................................ 5029
18.1.269XHC System Bus Configuration 1 (XHCC1_MMIO)—Offset 8640h ............. 5029
18.1.270Clock Gating (XHCLKGTEN_MMIO)—Offset 8650h .................................. 5031
18.1.271Audio Time Synchronization (AUDSYNC_MMIO)—Offset 8658h ................ 5034
18.1.272Serial Bus Release Number (SBRN_MMIO)—Offset 8660h ....................... 5035
18.1.273Frame Length Adjustment (FLADJ_MMIO)—Offset 8661h ........................ 5035

122 334818
 18.1.274Best Effort Service Latency (BESL_MMIO)—Offset 8662h.........................5036
18.1.275PCI Power Management Capability ID (PM_CID_MMIO)—Offset 8670h ......5037
18.1.276Next Item Pointer #1 (PM_NEXT_MMIO)—Offset 8671h ..........................5037
18.1.277Power Management Capabilities (PM_CAP_MMIO)—Offset 8672h ..............5038
18.1.278Power Management Control/Status (PM_CS_MMIO)—Offset 8674h ...........5039
18.1.279Message Signaled Interrupt CID (MSI_CID_MMIO)—Offset 8680h ............5040
18.1.280Next item pointer (MSI_NEXT_MMIO)—Offset 8681h ..............................5041
18.1.281Message Signaled Interrupt Message Control (MSI_MCTL_MMIO)—Offset 8682h
5041
18.1.282Message Signaled Interrupt Message Address (MSI_MAD_MMIO)—Offset 8684h
5042
18.1.283Message Signaled Interrupt Upper Address (MSI_MUAD_MMIO)—Offset 8688h .
5043
18.1.284Message Signaled Interrupt Message Data (MSI_MD_MMIO)—Offset 868Ch ......
5043
18.1.285Device Idle Capability (DEVIDLE_MMIO)—Offset 8690h...........................5044
18.1.286Vendor Specific Header (VSHDR_MMIO)—Offset 8694h ...........................5044
18.1.287SW LTR POINTER (SWLTRPTR_MMIO)—Offset 8698h ..............................5045
18.1.288Device Idle Pointer Register (DEVIDLEPTR_MMIO)—Offset 869Ch .............5046
18.1.289Device Idle Power ON Latency (DEVIDLEPOL_MMIO)—Offset 86A0h..........5047
18.1.290High Speed Configuration 2 (HSCFG2_MMIO)—Offset 86A4h....................5048
18.1.291XHCI USB2 Overcurrent Pin Mapping 1 (U2OCM1_MMIO)—Offset 86B0h....5049
18.1.292XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM2_MMIO)—Offset 86B4h....5050
18.1.293XHCI USB3 Overcurrent Pin Mapping 1 (U3OCM1_MMIO)—Offset 86D0h ...5050
18.1.294XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM2_MMIO)—Offset 86D4h ...5051
18.1.295XHCC3 (XHCC3_MMIO)—Offset 86FCh ..................................................5051
18.1.296Debug Capability ID Register (DCID)—Offset 8700h ...............................5052
18.1.297Debug Capability Doorbell Register (DCDB)—Offset 8704h ......................5053
18.1.298Debug Capability Event Ring Segment Table Size Register (DCERSTSZ)—Offset
8708h................................................................................................5053
18.1.299Debug Capability Event Ring Segment Table Base Address Register
(DCERSTBA)—Offset 8710h ..................................................................5054
18.1.300Debug Capability Event Ring Dequeue Pointer Register (DCERDP)—Offset 8718h
5054
18.1.301Debug Capability Control Register (DCCTRL)—Offset 8720h .....................5055
18.1.302Debug Capability Status Register (DCST)—Offset 8724h .........................5056
18.1.303Debug Capability Port Status and Control Register (DCPORTSC)—Offset 8728h .
5057
18.1.304Debug Capability Context Pointer Register (DCCP)—Offset 8730h .............5059
18.1.305Debug Capability Device Descriptor Info Register 1 (DCDDI1)—Offset 8738h ....
5059
18.1.306Debug Capability Device Descriptor Info Register 2 (DCDDI2)—Offset 873Ch ....
5060
18.1.307Debug Capability Descriptor Parameters (DCDP)—Offset 8740h................5060
18.1.308 .......................................................................................................5061
18.1.309Debug Device Control ODMA (DBGDEV_CTRL_ODMA_REG)—Offset 8748h .5061
18.1.310DBC Control Register 1 (DBCCTL_REG)—Offset 8760h ............................5062
18.1.311(PORT1_PROFILE_ATTRIBUTES_REG0)—Offset 890Ch ............................5063
18.1.312(PORT1_PROFILE_ATTRIBUTES_REG1)—Offset 8910h ............................5063
18.1.313(PORT1_PROFILE_ATTRIBUTES_REG2)—Offset 8914h ............................5064
18.1.314(PORT1_PROFILE_ATTRIBUTES_REG3)—Offset 8918h ............................5065
18.1.315(PORT1_PROFILE_ATTRIBUTES_REG4)—Offset 891Ch ............................5065
18.1.316(PORT1_PROFILE_ATTRIBUTES_REG5)—Offset 8920h ............................5066
18.1.317(PORT1_PROFILE_ATTRIBUTES_REG6)—Offset 8924h ............................5067
18.1.318(PORT1_PROFILE_ATTRIBUTES_REG7)—Offset 8928h ............................5067
18.1.319(PORT1_PROFILE_ATTRIBUTES_REG8)—Offset 892Ch ............................5068

334818 123
 18.1.320(PORT1_PROFILE_ATTRIBUTES_REG9)—Offset 8930h ............................ 5069
18.1.321(PORT1_PROFILE_ATTRIBUTES_REG10)—Offset 8934h .......................... 5069
18.1.322(PORT1_PROFILE_ATTRIBUTES_REG11)—Offset 8938h .......................... 5070
18.1.323(PORT1_PROFILE_ATTRIBUTES_REG12)—Offset 893Ch .......................... 5071
18.1.324(PORT1_PROFILE_ATTRIBUTES_REG13)—Offset 8940h .......................... 5071
18.1.325(PORT1_PROFILE_ATTRIBUTES_REG14)—Offset 8944h .......................... 5072
18.1.326(PORT1_PROFILE_ATTRIBUTES_REG15)—Offset 8948h .......................... 5073
18.1.327(PORT1_PROFILE_ATTRIBUTES_REG16)—Offset 894Ch .......................... 5073
18.1.328(PORT1_PROFILE_ATTRIBUTES_REG17)—Offset 8950h .......................... 5074
18.1.329(PORT1_PROFILE_ATTRIBUTES_REG18)—Offset 8954h .......................... 5075
18.1.330(PORT1_PROFILE_ATTRIBUTES_REG19)—Offset 8958h .......................... 5075
18.1.331(PORT1_PROFILE_ATTRIBUTES_REG20)—Offset 895Ch .......................... 5076
18.1.332(PORT1_PROFILE_ATTRIBUTES_REG21)—Offset 8960h .......................... 5077
18.1.333(PORT1_PROFILE_ATTRIBUTES_REG22)—Offset 8964h .......................... 5077
18.1.334(PORT1_PROFILE_ATTRIBUTES_REG23)—Offset 8968h .......................... 5078
18.1.335(PORT1_PROFILE_ATTRIBUTES_REG24)—Offset 896Ch .......................... 5079
18.1.336(PORT1_PROFILE_ATTRIBUTES_REG25)—Offset 8970h .......................... 5079
18.1.337(PORT1_PROFILE_ATTRIBUTES_REG26)—Offset 8974h .......................... 5080
18.1.338(PORT1_PROFILE_ATTRIBUTES_REG27)—Offset 8978h .......................... 5081
18.1.339(PORT1_PROFILE_ATTRIBUTES_REG28)—Offset 897Ch .......................... 5081
18.1.340(PORT1_PROFILE_ATTRIBUTES_REG29)—Offset 8980h .......................... 5082
18.1.341(PORT1_PROFILE_ATTRIBUTES_REG30)—Offset 8984h .......................... 5083
18.1.342(PORT1_PROFILE_ATTRIBUTES_REG31)—Offset 8988h .......................... 5083
18.1.343(PORT1_PROFILE_ATTRIBUTES_REG32)—Offset 898Ch .......................... 5084
18.1.344(PORT1_PROFILE_ATTRIBUTES_REG33)—Offset 8990h .......................... 5085
18.1.345(PORT1_PROFILE_ATTRIBUTES_REG34)—Offset 8994h .......................... 5085
18.1.346(PORT1_PROFILE_ATTRIBUTES_REG35)—Offset 8998h .......................... 5086
18.1.347(PORT1_PROFILE_ATTRIBUTES_REG36)—Offset 899Ch .......................... 5087
18.1.348(PORT1_PROFILE_ATTRIBUTES_REG37)—Offset 89A0h .......................... 5087
18.1.349(PORT1_PROFILE_ATTRIBUTES_REG38)—Offset 89A4h .......................... 5088
18.1.350(PORT1_PROFILE_ATTRIBUTES_REG39)—Offset 89A8h .......................... 5089
18.1.351(PORT1_PROFILE_ATTRIBUTES_REG40)—Offset 89ACh .......................... 5089
18.1.352(PORT1_PROFILE_ATTRIBUTES_REG41)—Offset 89B0h .......................... 5090
18.1.353(PORT1_PROFILE_ATTRIBUTES_REG42)—Offset 89B4h .......................... 5091
18.1.354(PORT1_PROFILE_ATTRIBUTES_REG43)—Offset 89B8h .......................... 5091
18.1.355(PORT1_PROFILE_ATTRIBUTES_REG44)—Offset 89BCh .......................... 5092
18.1.356(PORT1_PROFILE_ATTRIBUTES_REG45)—Offset 89C0h .......................... 5093
18.1.357(PORT1_PROFILE_ATTRIBUTES_REG46)—Offset 89C4h .......................... 5093
18.1.358(PORT1_PROFILE_ATTRIBUTES_REG47)—Offset 89C8h .......................... 5094
18.1.359(PORT1_PROFILE_ATTRIBUTES_REG48)—Offset 89CCh .......................... 5095
18.1.360(PORT1_PROFILE_ATTRIBUTES_REG49)—Offset 89D0h .......................... 5095
18.1.361(PORT1_PROFILE_ATTRIBUTES_REG50)—Offset 89D4h .......................... 5096
18.1.362(PORT1_PROFILE_ATTRIBUTES_REG51)—Offset 89D8h .......................... 5097
18.1.363(PORT1_PROFILE_ATTRIBUTES_REG52)—Offset 89DCh.......................... 5097
18.1.364(PORT1_PROFILE_ATTRIBUTES_REG53)—Offset 89E0h .......................... 5098
18.1.365(PORT1_PROFILE_ATTRIBUTES_REG54)—Offset 89E4h .......................... 5099
18.1.366(PORT1_PROFILE_ATTRIBUTES_REG55)—Offset 89E8h .......................... 5099
18.1.367(PORT1_PROFILE_ATTRIBUTES_REG56)—Offset 89ECh .......................... 5100
18.1.368(PORT1_PROFILE_ATTRIBUTES_REG57)—Offset 89F0h .......................... 5101
18.1.369(PORT1_PROFILE_ATTRIBUTES_REG58)—Offset 89F4h .......................... 5101
18.1.370(PORT1_PROFILE_ATTRIBUTES_REG59)—Offset 89F8h .......................... 5102
18.1.371(PORT1_PROFILE_ATTRIBUTES_REG60)—Offset 89FCh .......................... 5103
18.1.372(PORT1_PROFILE_ATTRIBUTES_REG61)—Offset 8A00h .......................... 5103
18.1.373(PORT1_PROFILE_ATTRIBUTES_REG62)—Offset 8A04h .......................... 5104
18.1.374(PORT1_PROFILE_ATTRIBUTES_REG63)—Offset 8A08h .......................... 5105

124 334818
 18.1.375GLOBAL_TIME_SYNC_CAP_REG (GLOBAL_TIME_SYNC_CAP_REG)—Offset
8E10h................................................................................................5105
18.1.376GLOBAL_TIME_SYNC_CTRL_REG (GLOBAL_TIME_SYNC_CTRL_REG)—Offset
8E14h................................................................................................5106
18.1.377MICROFRAME_TIME_REG (MICROFRAME_TIME_REG)—Offset 8E18h.........5107
18.1.378GLOBAL_TIME_LOW_REG (GLOBAL_TIME_LOW_REG)—Offset 8E20h ........5107
18.1.379GLOBAL_TIME_HI_REG (GLOBAL_TIME_HI_REG)—Offset 8E24h ..............5108
18.1.380Debug Status Capability Register (DEBUG_STATUS_CAPABILITY_REG)—Offset
8E58h................................................................................................5109
18.1.381Host Ctrl USB3 Soft Error Count Register 1
(HOST_CTRL_USB3_ERR_COUNT_REG1)—Offset 8E5Ch ...........................5109
18.1.382Host Ctrl USB3 Soft Error Count Register 2
(HOST_CTRL_USB3_ERR_COUNT_REG2)—Offset 8E60h ...........................5110
18.1.383Host Ctrl USB3 Soft Error Count Register 3
(HOST_CTRL_USB3_ERR_COUNT_REG3)—Offset 8E64h ...........................5110
18.1.384Host Ctrl USB3 Soft Error Count Register 4
(HOST_CTRL_USB3_ERR_COUNT_REG4)—Offset 8E68h ...........................5111
18.1.385Host Ctrl USB3 Soft Error Count Register 5
(HOST_CTRL_USB3_ERR_COUNT_REG5)—Offset 8E6Ch ...........................5112
18.1.386Host Ctrl USB3 Soft Error Count Register 6
(HOST_CTRL_USB3_ERR_COUNT_REG6)—Offset 8E70h ...........................5112
18.1.387Host Ctrl USB3 Soft Error Count Register 7
(HOST_CTRL_USB3_ERR_COUNT_REG7)—Offset 8E74h ...........................5113
18.1.388IOSFCTL - Control Register (IOSFCTL)—Offset 0h...................................5113
18.1.389Power Management Control Register (PMCTL)—Offset 1D0h.....................5114
18.1.390PCI Configuration Control 1 Register (PCICFGCTR1)—Offset 200h.............5115
18.1.391c73usb280_USB2 PER PORT (USB2_PER_PORT_PP0)—Offset 4100h .........5116
18.1.392GLB ADP VBUS COMP REG (GLB_ADP_VBUS_COMP_REG)—Offset 402Bh ..5119
18.1.393c73usb280_USB2 COMPBG (USB2_COMPBG)—Offset 7F04h ....................5121
18.1.394CONFIG_3—Offset 7014h....................................................................5125
18.1.395DBC_GP2_IN_PAYLOAD_BP_LOW—Offset 1Ch .......................................5126
18.1.396DBC_GP2_IN_PAYLOAD_BP_HI—Offset 20h...........................................5126
18.1.397DBC_GP2_IN_PAYLOAD_QUALIFIERS—Offset 24h ..................................5126
18.1.398DBC_GP2_IN_STATUS_QUALIFIERS—Offset 34h ....................................5127
18.1.399DBC_GP2_IN_STATUS_BP_LOW—Offset 2Ch .........................................5127
18.1.400DBC_GP2_IN_STATUS_BP_HI—Offset 30h ............................................5128
18.1.401Host Control IDMA (HOST_CTRL_IDMA_REG)—Offset 809Ch....................5128
18.1.402Host Control Transfer Manager (HOST_CTRL_TRM_REG2) —Offset 8110h..5130
18.1.403Command Manager Control 1 (XECP_CMDM_CTRL_REG1) —Offset 818Ch .5133
18.1.404Command Manager Control 2 (XECP_CMDM_CTRL_REG2) —Offset 8190h .5135
18.1.405Command Manager Control 3 (XECP_CMDM_CTRL_REG3) —Offset 8194h .5137
18.1.406Power Control Enable (PCE_REG) —Offset 00A2h ...................................5138
18.1.407GEN_REGRW4 —Offset 00BCh .............................................................5138
18.2 Registers Summary ........................................................................................5139
18.2.1 Vendor ID (VID)—Offset 0h ..................................................................5141
18.2.2 Device ID (DID)—Offset 2h...................................................................5141
18.2.3 Command (CMD)—Offset 4h .................................................................5141
18.2.4 Device Status (STS)—Offset 6h .............................................................5142
18.2.5 Revision ID (RID)—Offset 8h ................................................................5144
18.2.6 Programming Interface (PI)—Offset 9h...................................................5144
18.2.7 Sub Class Code (SCC)—Offset Ah ..........................................................5144
18.2.8 Base Class Code (BCC)—Offset Bh .........................................................5145
18.2.9 Master Latency Timer (MLT)—Offset Dh..................................................5145
18.2.10Header Type (HT)—Offset Eh ................................................................5146
18.2.11Memory Base Address (MBAR)—Offset 10h .............................................5146
18.2.12USB Subsystem Vendor ID (SSVID)—Offset 2Ch......................................5147

334818 125
 18.2.13USB Subsystem ID (SSID)—Offset 2Eh .................................................. 5147
18.2.14Capabilities Pointer (CAP_PTR)—Offset 34h ............................................ 5148
18.2.15Interrupt Line (ILINE)—Offset 3Ch ........................................................ 5148
18.2.16Interrupt Pin (IPIN)—Offset 3Dh ........................................................... 5149
18.2.17XHC System Bus Configuration 1 (XHCC1)—Offset 40h ............................ 5149
18.2.18Clock Gating (XHCLKGTEN)—Offset 50h ................................................. 5151
18.2.19Audio Time Synchronization (AUDSYNC)—Offset 58h ............................... 5154
18.2.20Serial Bus Release Number (SBRN)—Offset 60h ...................................... 5155
18.2.21Frame Length Adjustment (FLADJ)—Offset 61h....................................... 5155
18.2.22Best Effort Service Latency (BESL)—Offset 62h....................................... 5156
18.2.23PCI Power Management Capability ID (PM_CID)—Offset 70h..................... 5157
18.2.24Next Item Pointer #1 (PM_NEXT)—Offset 71h ........................................ 5157
18.2.25Power Management Capabilities (PM_CAP)—Offset 72h ............................ 5158
18.2.26Power Management Control/Status (PM_CS)—Offset 74h ......................... 5159
18.2.27Message Signaled Interrupt CID (MSI_CID)—Offset 80h........................... 5160
18.2.28Next item pointer (MSI_NEXT)—Offset 81h ............................................ 5160
18.2.29Message Signaled Interrupt Message Control (MSI_MCTL)—Offset 82h....... 5161
18.2.30Message Signaled Interrupt Message Address (MSI_MAD)—Offset 84h ....... 5161
18.2.31Message Signaled Interrupt Upper Address (MSI_MUAD)—Offset 88h ........ 5162
18.2.32Message Signaled Interrupt Message Data (MSI_MD)—Offset 8Ch ............. 5162
18.2.33Device Idle Capability (DEVIDLE)—Offset 90h ......................................... 5163
18.2.34Vendor Specific Header (VSHDR)—Offset 94h ......................................... 5163
18.2.35SW LTR POINTER (SWLTRPTR)—Offset 98h ............................................ 5164
18.2.36Device Idle Pointer Register (DEVIDLEPTR)—Offset 9Ch ........................... 5165
18.2.37Device Idle Power ON Latency (DEVIDLEPOL)—Offset A0h........................ 5166
18.2.38High Speed Configuration 2 (HSCFG2)—Offset A4h.................................. 5166
18.2.39XHCI USB2 Overcurrent Pin Mapping 1 (U2OCM1)—Offset B0h.................. 5168
18.2.40XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM2)—Offset B4h.................. 5168
18.2.41XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM3)—Offset B8h.................. 5169
18.2.42XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM4)—Offset BCh ................. 5169
18.2.43XHCI USB3 Overcurrent Pin Mapping 1 (U3OCM1)—Offset D0h ................. 5170
18.2.44XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM2)—Offset D4h ................. 5170
18.2.45XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM3)—Offset D8h ................. 5171
18.2.46XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM4)—Offset DCh ................. 5171
18.2.47XHCC3 (XHCC3)—Offset FCh ................................................................ 5172
18.3 Registers Summary........................................................................................ 5173
18.3.1 DBC_GP2_OUT_PAYLOAD_BP_LOW (DBC_GP2_OUT_PAYLOAD_BP_LOW)—
Offset 0h ........................................................................................... 5180
18.3.2 DBC_GP2_OUT_PAYLOAD_BP_HI (DBC_GP2_OUT_PAYLOAD_BP_HI)—Offset 4h
5181
18.3.3 DBC_GP2_OUT_PAYLOAD_QUALIFIERS
(DBC_GP2_OUT_PAYLOAD_QUALIFIERS)—Offset 8h................................ 5181
18.3.4 DBC_GP2_OUT_PAYLOAD_TRANSFER_LENGTH
(DBC_GP2_OUT_PAYLOAD_TRANSFER_LENGTH)—Offset Ch ..................... 5182
18.3.5 DBC_GP2_OUT_STATUS_BP_LOW (DBC_GP2_OUT_STATUS_BP_LOW)—Offset
10h................................................................................................... 5183
18.3.6 DBC_GP2_OUT_STATUS_BP_HI (DBC_GP2_OUT_STATUS_BP_HI)—Offset 14h ..
5183
18.3.7 DBC_GP2_OUT_STATUS_QUALIFIERS (DBC_GP2_OUT_STATUS_QUALIFIERS)—
Offset 18h ......................................................................................... 5184
18.3.8 DBC_GP2_IN_PAYLOAD_BP_LOW (DBC_GP2_IN_PAYLOAD_BP_LOW)—Offset
1Ch .................................................................................................. 5185
18.3.9 DBC_GP2_IN_PAYLOAD_BP_HI (DBC_GP2_IN_PAYLOAD_BP_HI)—Offset 20h ....
5185
18.3.10DBC_GP2_IN_PAYLOAD_QUALIFIERS (DBC_GP2_IN_PAYLOAD_QUALIFIERS)—
Offset 24h ......................................................................................... 5186

126 334818
 18.3.11DBC_GP2_IN_PAYLOAD_TRANSFER_LENGTH
(DBC_GP2_IN_PAYLOAD_TRANSFER_LENGTH)—Offset 28h ......................5187
18.3.12DBC_GP2_IN_STATUS_BP_LOW (DBC_GP2_IN_STATUS_BP_LOW)—Offset 2Ch..
5187
18.3.13DBC_GP2_IN_STATUS_BP_HI (DBC_GP2_IN_STATUS_BP_HI)—Offset 30h .5188
18.3.14DBC_GP2_IN_STATUS_QUALIFIERS (DBC_GP2_IN_STATUS_QUALIFIERS)—
Offset 34h ..........................................................................................5189
18.3.15DBC_TRACE_IN_PAYLOAD_BP_LOW (DBC_TRACE_IN_PAYLOAD_BP_LOW)—
Offset 50h ..........................................................................................5189
18.3.16DBC_TRACE_IN_PAYLOAD_BP_HI (DBC_TRACE_IN_PAYLOAD_BP_HI)—Offset
54h ...................................................................................................5190
18.3.17DBC_TRACE_IN_PAYLOAD_QUALIFIERS
(DBC_TRACE_IN_PAYLOAD_QUALIFIERS)—Offset 58h .............................5191
18.3.18DBC_TRACE_IN_PAYLOAD_TRASNFER_DOORBELL
(DBC_TRACE_IN_PAYLOAD_TRANSFER_DOORBELL)—Offset 5Ch ...............5191
18.3.19DBC_TRACE_IN_STATUS_BP_LOW (DBC_TRACE_IN_STATUS_BP_LOW)—Offset
60h ...................................................................................................5192
18.3.20DBC_TRACE_IN_STATUS_BP_HI (DBC_TRACE_IN_STATUS_BP_HI)—Offset 64h .
5193
18.3.21DBC_TRACE_IN_STATUS_QUALIFIERS
(DBC_TRACE_IN_STATUS_QUALIFIERS)—Offset 68h ...............................5193
18.3.22DBConEXI Capability Port Status and Control Register (DBC_EXI_DCPORTSC)—
Offset 88h ..........................................................................................5194
18.3.23DEBUG_SW_CONTROL_STATUS_REG (DEBUG_SW_CONTROL_STATUS_REG)—
Offset 100h ........................................................................................5196
18.3.24DEBUG_REQUEST_INFO_AND_STATUS_REG
(DEBUG_REQUEST_INFO_AND_STATUS_REG)—Offset 104h .....................5197
18.3.25DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_0)—Offset 108h ......
5199
18.3.26DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_1)—Offset 10Ch ......
5199
18.3.27DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_2)—Offset 110h ......
5200
18.3.28DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_3)—Offset 114h ......
5201
18.3.29DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_4)—Offset 118h ......
5201
18.3.30DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_5)—Offset 11Ch ......
5202
18.3.31DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_6)—Offset 120h ......
5203
18.3.32DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_7)—Offset 124h ......
5203
18.3.33DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_8)—Offset 128h ......
5204
18.3.34DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_9)—Offset 12Ch ......
5205
18.3.35DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_10)—Offset 130h.....
5205
18.3.36DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_11)—Offset 134h.....
5206
18.3.37DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_12)—Offset 138h.....
5207
18.3.38DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_13)—Offset 13Ch ....
5207
18.3.39DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_14)—Offset 140h.....
5208

334818 127
 18.3.40DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_15)—Offset 144h ....
5209
18.3.41DEBUG_RESPONSE_INFO_AND_STATUS_REG
(DEBUG_RESPONSE_INFO_AND_STATUS_REG)—Offset 148h ................... 5209
18.3.42DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_0)—
Offset 180h........................................................................................ 5210
18.3.43DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_1)—
Offset 184h........................................................................................ 5211
18.3.44DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_2)—
Offset 188h........................................................................................ 5211
18.3.45DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_3)—
Offset 18Ch ....................................................................................... 5212
18.3.46DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_4)—
Offset 190h........................................................................................ 5212
18.3.47DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_5)—
Offset 194h........................................................................................ 5213
18.3.48DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_6)—
Offset 198h........................................................................................ 5213
18.3.49DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_7)—
Offset 19Ch ....................................................................................... 5214
18.3.50DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_8)—
Offset 1A0h ....................................................................................... 5215
18.3.51DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_9)—
Offset 1A4h ....................................................................................... 5215
18.3.52DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_10)—Offset 1A8h ...................... 5216
18.3.53DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_11)—Offset 1ACh ...................... 5216
18.3.54DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_12)—Offset 1B0h ...................... 5217
18.3.55DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_13)—Offset 1B4h ...................... 5218
18.3.56DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_14)—Offset 1B8h ...................... 5218
18.3.57DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_15)—Offset 1BCh ...................... 5219
18.3.58DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_16)—Offset 1C0h ...................... 5219
18.3.59DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_17)—Offset 1C4h ...................... 5220
18.3.60DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_18)—Offset 1C8h ...................... 5221
18.3.61DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_19)—Offset 1CCh ...................... 5221
18.3.62DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_20)—Offset 1D0h ...................... 5222
18.3.63DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_21)—Offset 1D4h ...................... 5222
18.3.64DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_22)—Offset 1D8h ...................... 5223
18.3.65DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_23)—Offset 1DCh ...................... 5224
18.3.66DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_24)—Offset 1E0h....................... 5224
18.3.67DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_25)—Offset 1E4h....................... 5225

128 334818
 18.3.68DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_26)—Offset 1E8h .......................5225
18.3.69DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_27)—Offset 1ECh .......................5226
18.3.70DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_28)—Offset 1F0h .......................5227
18.3.71DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_29)—Offset 1F4h .......................5227
18.3.72DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_30)—Offset 1F8h .......................5228
18.3.73DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_31)—Offset 1FCh .......................5228
18.3.74DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_32)—Offset 200h .......................5229
18.3.75DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_33)—Offset 204h .......................5230
18.3.76DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_34)—Offset 208h .......................5230
18.3.77DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_35)—Offset 20Ch .......................5231
18.3.78DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_36)—Offset 210h .......................5231
18.3.79DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_37)—Offset 214h .......................5232
18.3.80DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_38)—Offset 218h .......................5233
18.3.81DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_39)—Offset 21Ch .......................5233
18.3.82DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_40)—Offset 220h .......................5234
18.3.83DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_41)—Offset 224h .......................5234
18.3.84DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_42)—Offset 228h .......................5235
18.3.85DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_43)—Offset 22Ch .......................5236
18.3.86DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_44)—Offset 230h .......................5236
18.3.87DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_45)—Offset 234h .......................5237
18.3.88DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_46)—Offset 238h .......................5237
18.3.89DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_47)—Offset 23Ch .......................5238
18.3.90DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_48)—Offset 240h .......................5239
18.3.91DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_49)—Offset 244h .......................5239
18.3.92DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_50)—Offset 248h .......................5240
18.3.93DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_51)—Offset 24Ch .......................5240
18.3.94DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_52)—Offset 250h .......................5241
18.3.95DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_53)—Offset 254h .......................5242

334818 129
 18.3.96DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_54)—Offset 258h....................... 5242
18.3.97DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_55)—Offset 25Ch ...................... 5243
18.3.98DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_56)—Offset 260h....................... 5243
18.3.99DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_57)—Offset 264h....................... 5244
18.3.100DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_58)—Offset 268h....................... 5245
18.3.101DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_59)—Offset 26Ch ...................... 5245
18.3.102DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_60)—Offset 270h....................... 5246
18.3.103DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_61)—Offset 274h....................... 5246
18.3.104DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_62)—Offset 278h....................... 5247
18.3.105DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_63)—Offset 27Ch ...................... 5248
18.3.106DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_64)—Offset 280h....................... 5248
18.3.107DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_65)—Offset 284h....................... 5249
18.3.108DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_66)—Offset 288h....................... 5249
18.3.109DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_67)—Offset 28Ch ...................... 5250
18.3.110DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_68)—Offset 290h....................... 5251
18.3.111DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_69)—Offset 294h....................... 5251
18.3.112DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_70)—Offset 298h....................... 5252
18.3.113DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_71)—Offset 29Ch ...................... 5252
18.3.114DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_72)—Offset 2A0h ...................... 5253
18.3.115DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_73)—Offset 2A4h ...................... 5254
18.3.116DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_74)—Offset 2A8h ...................... 5254
18.3.117DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_75)—Offset 2ACh ...................... 5255
18.3.118DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_76)—Offset 2B0h ...................... 5255
18.3.119DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_77)—Offset 2B4h ...................... 5256
18.3.120DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_78)—Offset 2B8h ...................... 5257
18.3.121DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_79)—Offset 2BCh ...................... 5257
18.3.122DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_80)—Offset 2C0h ...................... 5258
18.3.123DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_81)—Offset 2C4h ...................... 5258

130 334818
 18.3.124DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_82)—Offset 2C8h .......................5259
18.3.125DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_83)—Offset 2CCh .......................5260
18.3.126DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_84)—Offset 2D0h .......................5260
18.3.127DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_85)—Offset 2D4h .......................5261
18.3.128DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_86)—Offset 2D8h .......................5261
18.3.129DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_87)—Offset 2DCh.......................5262
18.3.130DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_88)—Offset 2E0h .......................5263
18.3.131DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_89)—Offset 2E4h .......................5263
18.3.132DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_90)—Offset 2E8h .......................5264
18.3.133DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_91)—Offset 2ECh .......................5264
18.3.134DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_92)—Offset 2F0h .......................5265
18.3.135DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_93)—Offset 2F4h .......................5266
18.3.136DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_94)—Offset 2F8h .......................5266
18.3.137DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_95)—Offset 2FCh .......................5267
18.3.138DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_96)—Offset 300h .......................5267
18.3.139DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_97)—Offset 304h .......................5268
18.3.140DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_98)—Offset 308h .......................5269
18.3.141DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_99)—Offset 30Ch .......................5269
18.3.142DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_100)—Offset 310h .....................5270
18.3.143DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_101)—Offset 314h .....................5271
18.3.144DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_102)—Offset 318h .....................5271
18.3.145DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_103)—Offset 31Ch .....................5272
18.3.146DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_104)—Offset 320h .....................5273
18.3.147DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_105)—Offset 324h .....................5273
18.3.148DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_106)—Offset 328h .....................5274
18.3.149DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_107)—Offset 32Ch .....................5275
18.3.150DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_108)—Offset 330h .....................5275
18.3.151DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_109)—Offset 334h .....................5276

334818 131
 18.3.152DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_110)—Offset 338h ..................... 5277
18.3.153DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_111)—Offset 33Ch..................... 5277
18.3.154DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_112)—Offset 340h ..................... 5278
18.3.155DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_113)—Offset 344h ..................... 5279
18.3.156DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_114)—Offset 348h ..................... 5279
18.3.157DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_115)—Offset 34Ch..................... 5280
18.3.158DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_116)—Offset 350h ..................... 5281
18.3.159DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_117)—Offset 354h ..................... 5281
18.3.160DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_118)—Offset 358h ..................... 5282
18.3.161DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_119)—Offset 35Ch..................... 5283
18.3.162DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_120)—Offset 360h ..................... 5283
18.3.163DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_121)—Offset 364h ..................... 5284
18.3.164DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_122)—Offset 368h ..................... 5285
18.3.165DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_123)—Offset 36Ch..................... 5285
18.3.166DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_124)—Offset 370h ..................... 5286
18.3.167DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_125)—Offset 374h ..................... 5287
18.3.168DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_126)—Offset 378h ..................... 5287
18.3.169DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_127)—Offset 37Ch..................... 5288
18.3.170DEBUG_RESPONSE_HEADER_STACK_REG
(DEBUG_RESPONSE_HEADER_STACK_REG_0)—Offset 380h .................... 5289
18.3.171DEBUG_RESPONSE_HEADER_STACK_REG
(DEBUG_RESPONSE_HEADER_STACK_REG_1)—Offset 384h .................... 5289
18.3.172DEBUG_RESPONSE_HEADER_STACK_REG
(DEBUG_RESPONSE_HEADER_STACK_REG_2)—Offset 388h .................... 5290
18.4 Registers Summary........................................................................................ 5291
18.4.1 DCFG (DCFG)—Offset C700h ................................................................ 5294
18.4.2 DCTL (DCTL)—Offset C704h ................................................................. 5295
18.4.3 DEVTEN (DEVTEN)—Offset C708h ......................................................... 5296
18.4.4 DSTS (DSTS)—Offset C70Ch ................................................................ 5297
18.4.5 DGCMDPAR (DGCMDPAR)—Offset C710h ............................................... 5298
18.4.6 DGCMD (DGCMD)—Offset C714h .......................................................... 5299
18.4.7 DALEPENA (DALEPENA)—Offset C720h .................................................. 5299
18.4.8 DEPCMDPAR2_0 (DEPCMDPAR2_0)—Offset C800h .................................. 5300
18.4.9 DEPCMDPAR1_0 (DEPCMDPAR1_0)—Offset C804h .................................. 5300
18.4.10DEPCMDPAR0_0 (DEPCMDPAR0_0)—Offset C808h .................................. 5301
18.4.11DEPCMD_0 (DEPCMD_0)—Offset C80Ch................................................. 5301
18.4.12DEPCMDPAR2_1 (DEPCMDPAR2_1)—Offset C810h .................................. 5302
18.4.13DEPCMDPAR1_1 (DEPCMDPAR1_1)—Offset C814h .................................. 5303
18.4.14DEPCMDPAR0_1 (DEPCMDPAR0_1)—Offset C818h .................................. 5303

132 334818
 18.4.15DEPCMD_1 (DEPCMD_1)—Offset C81Ch .................................................5304
18.4.16DEPCMDPAR2_2 (DEPCMDPAR2_2)—Offset C820h ...................................5304
18.4.17DEPCMDPAR1_2 (DEPCMDPAR1_2)—Offset C824h ...................................5305
18.4.18DEPCMDPAR0_2 (DEPCMDPAR0_2)—Offset C828h ...................................5305
18.4.19DEPCMD_2 (DEPCMD_2)—Offset C82Ch .................................................5306
18.4.20DEPCMDPAR2_3 (DEPCMDPAR2_3)—Offset C830h ...................................5307
18.4.21DEPCMDPAR1_3 (DEPCMDPAR1_3)—Offset C834h ...................................5307
18.4.22DEPCMDPAR0_3 (DEPCMDPAR0_3)—Offset C838h ...................................5308
18.4.23DEPCMD_3 (DEPCMD_3)—Offset C83Ch .................................................5308
18.4.24DEPCMDPAR2_4 (DEPCMDPAR2_4)—Offset C840h ...................................5309
18.4.25DEPCMDPAR1_4 (DEPCMDPAR1_4)—Offset C844h ...................................5309
18.4.26DEPCMDPAR0_4 (DEPCMDPAR0_4)—Offset C848h ...................................5310
18.4.27DEPCMD_4 (DEPCMD_4)—Offset C84Ch .................................................5310
18.4.28DEPCMDPAR2_5 (DEPCMDPAR2_5)—Offset C850h ...................................5311
18.4.29DEPCMDPAR1_5 (DEPCMDPAR1_5)—Offset C854h ...................................5312
18.4.30DEPCMDPAR0_5 (DEPCMDPAR0_5)—Offset C858h ...................................5312
18.4.31DEPCMD_5 (DEPCMD_5)—Offset C85Ch .................................................5313
18.4.32DEPCMDPAR2_6 (DEPCMDPAR2_6)—Offset C860h ...................................5313
18.4.33DEPCMDPAR1_6 (DEPCMDPAR1_6)—Offset C864h ...................................5314
18.4.34DEPCMDPAR0_6 (DEPCMDPAR0_6)—Offset C868h ...................................5314
18.4.35DEPCMD_6 (DEPCMD_6)—Offset C86Ch .................................................5315
18.4.36DEPCMDPAR2_7 (DEPCMDPAR2_7)—Offset C870h ...................................5316
18.4.37DEPCMDPAR1_7 (DEPCMDPAR1_7)—Offset C874h ...................................5316
18.4.38DEPCMDPAR0_7 (DEPCMDPAR0_7)—Offset C878h ...................................5317
18.4.39DEPCMD_7 (DEPCMD_7)—Offset C87Ch .................................................5317
18.4.40DEPCMDPAR2_8 (DEPCMDPAR2_8)—Offset C880h ...................................5318
18.4.41DEPCMDPAR1_8 (DEPCMDPAR1_8)—Offset C884h ...................................5318
18.4.42DEPCMDPAR0_8 (DEPCMDPAR0_8)—Offset C888h ...................................5319
18.4.43DEPCMD_8 (DEPCMD_8)—Offset C88Ch .................................................5319
18.4.44DEPCMDPAR2_9 (DEPCMDPAR2_9)—Offset C890h ...................................5320
18.4.45DEPCMDPAR1_9 (DEPCMDPAR1_9)—Offset C894h ...................................5321
18.4.46DEPCMDPAR0_9 (DEPCMDPAR0_9)—Offset C898h ...................................5321
18.4.47DEPCMD_9 (DEPCMD_9)—Offset C89Ch .................................................5322
18.4.48DEPCMDPAR2_10 (DEPCMDPAR2_10)—Offset C8A0h ...............................5322
18.4.49DEPCMDPAR1_10 (DEPCMDPAR1_10)—Offset C8A4h ...............................5323
18.4.50DEPCMDPAR0_10 (DEPCMDPAR0_10)—Offset C8A8h ...............................5323
18.4.51DEPCMD_10 (DEPCMD_10)—Offset C8ACh .............................................5324
18.4.52DEPCMDPAR2_11 (DEPCMDPAR2_11)—Offset C8B0h ...............................5325
18.4.53DEPCMDPAR1_11 (DEPCMDPAR1_11)—Offset C8B4h ...............................5325
18.4.54DEPCMDPAR0_11 (DEPCMDPAR0_11)—Offset C8B8h ...............................5326
18.4.55DEPCMD_11 (DEPCMD_11)—Offset C8BCh .............................................5326
18.4.56DEPCMDPAR2_12 (DEPCMDPAR2_12)—Offset C8C0h ...............................5327
18.4.57DEPCMDPAR1_12 (DEPCMDPAR1_12)—Offset C8C4h ...............................5327
18.4.58DEPCMDPAR0_12 (DEPCMDPAR0_12)—Offset C8C8h ...............................5328
18.4.59DEPCMD_12 (DEPCMD_12)—Offset C8CCh .............................................5328
18.4.60DEPCMDPAR2_13 (DEPCMDPAR2_13)—Offset C8D0h ...............................5329
18.4.61DEPCMDPAR1_13 (DEPCMDPAR1_13)—Offset C8D4h ...............................5330
18.4.62DEPCMDPAR0_13 (DEPCMDPAR0_13)—Offset C8D8h ...............................5330
18.4.63DEPCMD_13 (DEPCMD_13)—Offset C8DCh .............................................5331
18.4.64DEPCMDPAR2_14 (DEPCMDPAR2_14)—Offset C8E0h ...............................5331
18.4.65DEPCMDPAR1_14 (DEPCMDPAR1_14)—Offset C8E4h ...............................5332
18.4.66DEPCMDPAR0_14 (DEPCMDPAR0_14)—Offset C8E8h ...............................5332
18.4.67DEPCMD_14 (DEPCMD_14)—Offset C8ECh..............................................5333
18.4.68DEPCMDPAR2_15 (DEPCMDPAR2_15)—Offset C8F0h................................5334
18.4.69DEPCMDPAR1_15 (DEPCMDPAR1_15)—Offset C8F4h................................5334

334818 133
 18.4.70DEPCMDPAR0_15 (DEPCMDPAR0_15)—Offset C8F8h ............................... 5335
18.4.71DEPCMD_15 (DEPCMD_15)—Offset C8FCh ............................................. 5335
18.4.72DEPCMDPAR2_16 (DEPCMDPAR2_16)—Offset C900h ............................... 5336
18.4.73DEPCMDPAR1_16 (DEPCMDPAR1_16)—Offset C904h ............................... 5336
18.4.74DEPCMDPAR0_16 (DEPCMDPAR0_16)—Offset C908h ............................... 5337
18.4.75DEPCMD_16 (DEPCMD_16)—Offset C90Ch ............................................. 5337
18.4.76DEPCMDPAR2_17 (DEPCMDPAR2_17)—Offset C910h ............................... 5338
18.4.77DEPCMDPAR1_17 (DEPCMDPAR1_17)—Offset C914h ............................... 5339
18.4.78DEPCMDPAR0_17 (DEPCMDPAR0_17)—Offset C918h ............................... 5339
18.4.79DEPCMD_17 (DEPCMD_17)—Offset C91Ch ............................................. 5340
18.4.80DEPCMDPAR2_18 (DEPCMDPAR2_18)—Offset C920h ............................... 5340
18.4.81DEPCMDPAR1_18 (DEPCMDPAR1_18)—Offset C924h ............................... 5341
18.4.82DEPCMDPAR0_18 (DEPCMDPAR0_18)—Offset C928h ............................... 5341
18.4.83DEPCMD_18 (DEPCMD_18)—Offset C92Ch ............................................. 5342
18.4.84DEPCMDPAR2_19 (DEPCMDPAR2_19)—Offset C930h ............................... 5343
18.4.85DEPCMDPAR1_19 (DEPCMDPAR1_19)—Offset C934h ............................... 5343
18.4.86DEPCMDPAR0_19 (DEPCMDPAR0_19)—Offset C938h ............................... 5344
18.4.87DEPCMD_19 (DEPCMD_19)—Offset C93Ch ............................................. 5344
18.4.88DEPCMDPAR2_20 (DEPCMDPAR2_20)—Offset C940h ............................... 5345
18.4.89DEPCMDPAR1_20 (DEPCMDPAR1_20)—Offset C944h ............................... 5345
18.4.90DEPCMDPAR0_20 (DEPCMDPAR0_20)—Offset C948h ............................... 5346
18.4.91DEPCMD_20 (DEPCMD_20)—Offset C94Ch ............................................. 5346
18.4.92DEPCMDPAR2_21 (DEPCMDPAR2_21)—Offset C950h ............................... 5347
18.4.93DEPCMDPAR1_21 (DEPCMDPAR1_21)—Offset C954h ............................... 5348
18.4.94DEPCMDPAR0_21 (DEPCMDPAR0_21)—Offset C958h ............................... 5348
18.4.95DEPCMD_21 (DEPCMD_21)—Offset C95Ch ............................................. 5349
18.4.96DEPCMDPAR2_22 (DEPCMDPAR2_22)—Offset C960h ............................... 5349
18.4.97DEPCMDPAR1_22 (DEPCMDPAR1_22)—Offset C964h ............................... 5350
18.4.98DEPCMDPAR0_22 (DEPCMDPAR0_22)—Offset C968h ............................... 5350
18.4.99DEPCMD_22 (DEPCMD_22)—Offset C96Ch ............................................. 5351
18.4.100DEPCMDPAR2_23 (DEPCMDPAR2_23)—Offset C970h ............................. 5352
18.4.101DEPCMDPAR1_23 (DEPCMDPAR1_23)—Offset C974h ............................. 5352
18.4.102DEPCMDPAR0_23 (DEPCMDPAR0_23)—Offset C978h ............................. 5353
18.4.103DEPCMD_23 (DEPCMD_23)—Offset C97Ch............................................ 5353
18.4.104DEPCMDPAR2_24 (DEPCMDPAR2_24)—Offset C980h ............................. 5354
18.4.105DEPCMDPAR1_24 (DEPCMDPAR1_24)—Offset C984h ............................. 5354
18.4.106DEPCMDPAR0_24 (DEPCMDPAR0_24)—Offset C988h ............................. 5355
18.4.107DEPCMD_24 (DEPCMD_24)—Offset C98Ch............................................ 5355
18.4.108DEPCMDPAR2_25 (DEPCMDPAR2_25)—Offset C990h ............................. 5356
18.4.109DEPCMDPAR1_25 (DEPCMDPAR1_25)—Offset C994h ............................. 5357
18.4.110DEPCMDPAR0_25 (DEPCMDPAR0_25)—Offset C998h ............................. 5357
18.4.111DEPCMD_25 (DEPCMD_25)—Offset C99Ch............................................ 5358
18.4.112DEPCMDPAR2_26 (DEPCMDPAR2_26)—Offset C9A0h ............................. 5358
18.4.113DEPCMDPAR1_26 (DEPCMDPAR1_26)—Offset C9A4h ............................. 5359
18.4.114DEPCMDPAR0_26 (DEPCMDPAR0_26)—Offset C9A8h ............................. 5359
18.4.115DEPCMD_26 (DEPCMD_26)—Offset C9ACh ........................................... 5360
18.4.116DEPCMDPAR2_27 (DEPCMDPAR2_27)—Offset C9B0h ............................. 5361
18.4.117DEPCMDPAR1_27 (DEPCMDPAR1_27)—Offset C9B4h ............................. 5361
18.4.118DEPCMDPAR0_27 (DEPCMDPAR0_27)—Offset C9B8h ............................. 5362
18.4.119DEPCMD_27 (DEPCMD_27)—Offset C9BCh ........................................... 5362
18.4.120DEPCMDPAR2_28 (DEPCMDPAR2_28)—Offset C9C0h ............................. 5363
18.4.121DEPCMDPAR1_28 (DEPCMDPAR1_28)—Offset C9C4h ............................. 5363
18.4.122DEPCMDPAR0_28 (DEPCMDPAR0_28)—Offset C9C8h ............................. 5364
18.4.123DEPCMD_28 (DEPCMD_28)—Offset C9CCh ........................................... 5364
18.4.124DEPCMDPAR2_29 (DEPCMDPAR2_29)—Offset C9D0h ............................. 5365

134 334818
 18.4.125DEPCMDPAR1_29 (DEPCMDPAR1_29)—Offset C9D4h..............................5366
18.4.126DEPCMDPAR0_29 (DEPCMDPAR0_29)—Offset C9D8h..............................5366
18.4.127DEPCMD_29 (DEPCMD_29)—Offset C9DCh............................................5367
18.4.128DEPCMDPAR2_30 (DEPCMDPAR2_30)—Offset C9E0h ..............................5367
18.4.129DEPCMDPAR1_30 (DEPCMDPAR1_30)—Offset C9E4h ..............................5368
18.4.130DEPCMDPAR0_30 (DEPCMDPAR0_30)—Offset C9E8h ..............................5368
18.4.131DEPCMD_30 (DEPCMD_30)—Offset C9ECh ............................................5369
18.4.132DEPCMDPAR2_31 (DEPCMDPAR2_31)—Offset C9F0h ..............................5370
18.4.133DEPCMDPAR1_31 (DEPCMDPAR1_31)—Offset C9F4h ..............................5370
18.4.134DEPCMDPAR0_31 (DEPCMDPAR0_31)—Offset C9F8h ..............................5371
18.4.135DEPCMD_31 (DEPCMD_31)—Offset C9FCh ............................................5371
18.5 Registers Summary ........................................................................................5372
18.5.1 GSBUSCFG0 (GSBUSCFG0)—Offset C100h..............................................5374
18.5.2 GSBUSCFG1 (GSBUSCFG1)—Offset C104h..............................................5375
18.5.3 GTXTHRCFG (GTXTHRCFG)—Offset C108h ..............................................5376
18.5.4 GRXTHRCFG (GRXTHRCFG)—Offset C10Ch .............................................5376
18.5.5 GCTL (GCTL)—Offset C110h .................................................................5377
18.5.6 GPMSTS (GPMSTS)—Offset C114h .........................................................5378
18.5.7 GSTS (GSTS)—Offset C118h .................................................................5379
18.5.8 GUCTL1 (GUCTL1)—Offset C11Ch..........................................................5380
18.5.9 GSNPSID (GSNPSID)—Offset C120h ......................................................5381
18.5.10GGPIO (GGPIO)—Offset C124h..............................................................5381
18.5.11GUID (GUID)—Offset C128h .................................................................5382
18.5.12GUCTL (GUCTL)—Offset C12Ch .............................................................5382
18.5.13GBUSERRADDRLO (GBUSERRADDRLO)—Offset C130h..............................5383
18.5.14GBUSERRADDRHI (GBUSERRADDRHI)—Offset C134h...............................5384
18.5.15GPRTBIMAPLO (GPRTBIMAPLO)—Offset C138h ........................................5384
18.5.16GPRTBIMAPHI (GPRTBIMAPHI)—Offset C13Ch .........................................5385
18.5.17GHWPARAMS0 (GHWPARAMS0)—Offset C140h........................................5386
18.5.18GHWPARAMS1 (GHWPARAMS1)—Offset C144h........................................5387
18.5.19GHWPARAMS2 (GHWPARAMS2)—Offset C148h........................................5388
18.5.20GHWPARAMS3 (GHWPARAMS3)—Offset C14Ch .......................................5389
18.5.21GHWPARAMS4 (GHWPARAMS4)—Offset C150h........................................5390
18.5.22GHWPARAMS5 (GHWPARAMS5)—Offset C154h........................................5391
18.5.23GHWPARAMS6 (GHWPARAMS6)—Offset C158h........................................5392
18.5.24GHWPARAMS7 (GHWPARAMS7)—Offset C15Ch .......................................5393
18.5.25GDBGFIFOSPACE (GDBGFIFOSPACE)—Offset C160h ................................5394
18.5.26GDBGLTSSM (GDBGLTSSM)—Offset C164h .............................................5394
18.5.27GDBGLNMCC (GDBGLNMCC)—Offset C168h ............................................5396
18.5.28GDBGBMU (GDBGBMU)—Offset C16Ch ...................................................5396
18.5.29GDBGLSPMUX_DEV (GDBGLSPMUX_DEV)—Offset C170h ..........................5397
18.5.30GDBGLSP (GDBGLSP)—Offset C174h .....................................................5397
18.5.31GDBGEPINFO0 (GDBGEPINFO0)—Offset C178h .......................................5398
18.5.32GDBGEPINFO1 (GDBGEPINFO1)—Offset C17Ch .......................................5398
18.5.33GPRTBIMAP_HSLO (GPRTBIMAP_HSLO)—Offset C180h.............................5399
18.5.34GPRTBIMAP_HSHI (GPRTBIMAP_HSHI)—Offset C184h..............................5400
18.5.35GPRTBIMAP_FSLO (GPRTBIMAP_FSLO)—Offset C188h..............................5400
18.5.36GPRTBIMAP_FSHI (GPRTBIMAP_FSHI)—Offset C18Ch ..............................5401
18.5.37GUSB2PHYCFG_0 (GUSB2PHYCFG_0)—Offset C200h................................5402
18.5.38GUSB2I2CCTL_0 (GUSB2I2CCTL_0)—Offset C240h ..................................5403
18.5.39GUSB2PHYACC_ULPI_0 (GUSB2PHYACC_ULPI_0)—Offset C280h ...............5404
18.5.40GUSB3PIPECTL_0 (GUSB3PIPECTL_0)—Offset C2C0h ...............................5405
18.5.41GTXFIFOSIZ0_0 (GTXFIFOSIZ0_0)—Offset C300h ...................................5406
18.5.42GTXFIFOSIZ1_0 (GTXFIFOSIZ1_0)—Offset C304h ...................................5407
18.5.43GTXFIFOSIZ2_0 (GTXFIFOSIZ2_0)—Offset C308h ...................................5407

334818 135
 18.5.44GTXFIFOSIZ3_0 (GTXFIFOSIZ3_0)—Offset C30Ch................................... 5408
18.5.45GTXFIFOSIZ4_0 (GTXFIFOSIZ4_0)—Offset C310h................................... 5409
18.5.46GTXFIFOSIZ5_0 (GTXFIFOSIZ5_0)—Offset C314h................................... 5409
18.5.47GTXFIFOSIZ6_0 (GTXFIFOSIZ6_0)—Offset C318h................................... 5410
18.5.48GTXFIFOSIZ7_0 (GTXFIFOSIZ7_0)—Offset C31Ch................................... 5410
18.5.49GTXFIFOSIZ8_0 (GTXFIFOSIZ8_0)—Offset C320h................................... 5411
18.5.50GTXFIFOSIZ9_0 (GTXFIFOSIZ9_0)—Offset C324h................................... 5411
18.5.51GTXFIFOSIZ10_0 (GTXFIFOSIZ10_0)—Offset C328h ............................... 5412
18.5.52GTXFIFOSIZ11_0 (GTXFIFOSIZ11_0)—Offset C32Ch ............................... 5412
18.5.53GTXFIFOSIZ12_0 (GTXFIFOSIZ12_0)—Offset C330h ............................... 5413
18.5.54GTXFIFOSIZ13_0 (GTXFIFOSIZ13_0)—Offset C334h ............................... 5413
18.5.55GTXFIFOSIZ14_0 (GTXFIFOSIZ14_0)—Offset C338h ............................... 5414
18.5.56GTXFIFOSIZ15_0 (GTXFIFOSIZ15_0)—Offset C33Ch ............................... 5414
18.5.57GRXFIFOSIZ0_0 (GRXFIFOSIZ0_0)—Offset C380h .................................. 5415
18.5.58GEVNTADRLO_0 (GEVNTADRLO_0)—Offset C400h .................................. 5415
18.5.59GEVNTADRHI_0 (GEVNTADRHI_0)—Offset C404h ................................... 5416
18.5.60GEVNTSIZ_0 (GEVNTSIZ_0)—Offset C408h............................................ 5416
18.5.61GEVNTCOUNT_0 (GEVNTCOUNT_0)—Offset C40Ch.................................. 5417
18.5.62GHWPARAMS8 (GHWPARAMS8)—Offset C600h ....................................... 5418
18.5.63GTXFIFOPRIDEV (GTXFIFOPRIDEV)—Offset C610h .................................. 5418
18.5.64GFLADJ (GFLADJ)—Offset C630h .......................................................... 5419
18.6 Registers Summary........................................................................................ 5420
18.6.1 APBFC_U3PMU_CFG0 (APBFC_U3PMU_CFG0)—Offset 10F808h ................. 5420
18.6.2 APBFC_U3PMU_CFG1 (APBFC_U3PMU_CFG1)—Offset 10F80Ch ................. 5421
18.6.3 APBFC_U3PMU_CFG2 (APBFC_U3PMU_CFG2)—Offset 10F810h ................. 5423
18.6.4 APBFC_U3PMU_CFG3 (APBFC_U3PMU_CFG3)—Offset 10F814h ................. 5424
18.6.5 APBFC_U3PMU_CFG4 (APBFC_U3PMU_CFG4)—Offset 10F818h ................. 5425
18.6.6 APBFC_U3PMU_CFG5 (APBFC_U3PMU_CFG5)—Offset 10F81Ch ................. 5426
18.6.7 APBFC_U3PMU_CFG6 (APBFC_U3PMU_CFG6)—Offset 10F820h ................. 5427
18.6.8 APBFC_D0I3C (APBFC_D0I3C)—Offset 10F830h...................................... 5428
18.7 Registers Summary........................................................................................ 5429
18.7.1 (GEN_REGRW1)—Offset B0h ............................................................... 5429
18.7.2 (GEN_REGRW2)—Offset B4h ................................................................ 5429
18.7.3 (GEN_REGRW3)—Offset B8h ................................................................ 5430
18.7.4 (GEN_REGRW4)—Offset BCh ................................................................ 5430
18.7.5 (GEN_INPUT_REGRW)—Offset C0h....................................................... 5431
18.8 Registers Summary........................................................................................ 5433
18.8.1 (GEN_REGRW1)—Offset B0h ............................................................... 5433
18.8.2 (GEN_REGRW2)—Offset B4h ................................................................ 5433
18.8.3 (GEN_REGRW3)—Offset B8h ................................................................ 5434
18.8.4 (GEN_REGRW4)—Offset BCh ................................................................ 5434
18.8.5 (GEN_INPUT_REGRW)—Offset C0h....................................................... 5435
18.9 Registers Summary........................................................................................ 5437
18.9.1 (DEVVENDID)—Offset 0h .................................................................... 5437
18.9.2 (STATUSCOMMAND)—Offset 4h ............................................................ 5438
18.9.3 (REVCLASSCODE)—Offset 8h ............................................................... 5439
18.9.4 (CLLATHEADERBIST)—Offset Ch ........................................................... 5439
18.9.5 (BAR)—Offset 10h .............................................................................. 5440
18.9.6 (BAR1)—Offset 18h............................................................................. 5441
18.9.7 (SUBSYSTEMID)—Offset 2Ch................................................................ 5441
18.9.8 (EXPANSION_ROM_BASEADDR)—Offset 30h .......................................... 5442
18.9.9 (CAPABILITYPTR)—Offset 34h .............................................................. 5443
18.9.10(INTERRUPTREG)—Offset 3Ch .............................................................. 5443
18.9.11(POWERCAPID)—Offset 80h ................................................................. 5444
18.9.12(PMECTRLSTATUS)—Offset 84h ............................................................ 5444

136 334818
 18.9.13(PCIDEVIDLE_CAP_RECORD)—Offset 90h ...............................................5445
18.9.14(DEVID_VEND_SPECIFIC_REG)—Offset 94h ............................................5446
18.9.15(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................5446
18.9.16(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................5447
18.9.17(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................5448
18.10 Registers Summary ........................................................................................5449
18.10.1 (DEVVENDID)—Offset 0h.....................................................................5449
18.10.2(STATUSCOMMAND)—Offset 4h.............................................................5450
18.10.3(REVCLASSCODE)—Offset 8h ................................................................5451
18.10.4(CLLATHEADERBIST)—Offset Ch............................................................5451
18.10.5(BAR)—Offset 10h ...............................................................................5452
18.10.6(BAR1)—Offset 18h .............................................................................5453
18.10.7(SUBSYSTEMID)—Offset 2Ch ................................................................5453
18.10.8(EXPANSION_ROM_BASEADDR)—Offset 30h ...........................................5454
18.10.9(CAPABILITYPTR)—Offset 34h ...............................................................5455
18.10.10(INTERRUPTREG)—Offset 3Ch .............................................................5455
18.10.11(POWERCAPID)—Offset 80h ................................................................5456
18.10.12(PMECTRLSTATUS)—Offset 84h ...........................................................5456
18.10.13(PCIDEVIDLE_CAP_RECORD)—Offset 90h .............................................5457
18.10.14(DEVID_VEND_SPECIFIC_REG)—Offset 94h ..........................................5458
18.10.15(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h...............................5458
18.10.16(DEVICE_IDLE_POINTER_REG)—Offset 9Ch...........................................5459
18.10.17(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ...................................5460
18.11 ...................................................................................................................5460
18.12 Registers Summary ........................................................................................5461
18.12.1Capability Registers Length (CAPLENGTH)—Offset 0h ...............................5474
18.12.2Host Controller Interface Version Number (HCIVERSION)—Offset 2h ..........5474
18.12.3Structural Parameters 1 (HCSPARAMS1)—Offset 4h .................................5474
18.12.4Structural Parameters 2 (HCSPARAMS2)—Offset 8h .................................5475
18.12.5Structural Parameters 3 (HCSPARAMS3)—Offset Ch .................................5476
18.12.6Capability Parameters (HCCPARAMS)—Offset 10h ....................................5476
18.12.7Doorbell Offset (DBOFF)—Offset 14h......................................................5477
18.12.8Runtime Register Space Offset (RTSOFF)—Offset 18h...............................5478
18.12.9USB Command (USBCMD)—Offset 80h...................................................5478
18.12.10USB Status (USBSTS)—Offset 84h .......................................................5479
18.12.11Page Size (PAGESIZE)—Offset 88h .......................................................5480
18.12.12Device Notification Control (DNCTRL)—Offset 94h ..................................5480
18.12.13Command Ring Low (CRCR_LO)—Offset 98h..........................................5481
18.12.14Command Ring High (CRCR_HI)—Offset 9Ch .........................................5481
18.12.15Device Context Base Address Array Pointer Low (DCBAAP_LO)—Offset B0h ......
5482
18.12.16Device Context Base Address Array Pointer High (DCBAAP_HI)—Offset B4h ......
5482
18.12.17Configure (CONFIG)—Offset B8h..........................................................5483
18.12.18Port Status and Control USB2 (PORTSC1)—Offset 480h...........................5483
18.12.19Port Power Management Status and Control USB2 (PORTPMSC1)—Offset 484h .
5485
18.12.20Port X Hardware LPM Control Register (PORTHLPMC1)—Offset 48Ch .........5486
18.12.21Port Status and Control USB2 (PORTSC2)—Offset 490h...........................5487
18.12.22Port Power Management Status and Control USB2 (PORTPMSC2)—Offset 494h .
5488
18.12.23Port X Hardware LPM Control Register (PORTHLPMC2)—Offset 49Ch .........5489
18.12.24Port Status and Control USB2 (PORTSC3)—Offset 4A0h ..........................5490
18.12.25Port Power Management Status and Control USB2 (PORTPMSC3)—Offset 4A4h .
5491

334818 137
 18.12.26Port X Hardware LPM Control Register (PORTHLPMC3)—Offset 4ACh ........ 5492
18.12.27Port Status and Control USB2 (PORTSC4)—Offset 4B0h .......................... 5493
18.12.28Port Power Management Status and Control USB2 (PORTPMSC4)—Offset 4B4h.
5494
18.12.29Port X Hardware LPM Control Register (PORTHLPMC4)—Offset 4BCh ........ 5495
18.12.30Port Status and Control USB2 (PORTSC5)—Offset 4C0h .......................... 5496
18.12.31Port Power Management Status and Control USB2 (PORTPMSC5)—Offset 4C4h.
5497
18.12.32Port X Hardware LPM Control Register (PORTHLPMC5)—Offset 4CCh ........ 5498
18.12.33Port Status and Control USB2 (PORTSC6)—Offset 4D0h.......................... 5499
18.12.34Port Power Management Status and Control USB2 (PORTPMSC6)—Offset 4D4h
5500
18.12.35Port X Hardware LPM Control Register (PORTHLPMC6)—Offset 4DCh ........ 5501
18.12.36Port Status and Control USB2 (PORTSC7)—Offset 4E0h .......................... 5502
18.12.37Port Power Management Status and Control USB2 (PORTPMSC7)—Offset 4E4h .
5503
18.12.38Port X Hardware LPM Control Register (PORTHLPMC7)—Offset 4ECh......... 5504
18.12.39Port Status and Control USB2 (PORTSC8)—Offset 4F0h .......................... 5505
18.12.40Port Power Management Status and Control USB2 (PORTPMSC8)—Offset 4F4h .
5506
18.12.41Port X Hardware LPM Control Register (PORTHLPMC8)—Offset 4FCh ......... 5507
18.12.42Port Status and Control USB3 (PORTSC9)—Offset 500h .......................... 5508
18.12.43Port Power Management Status and Control USB3 (PORTPMSC9)—Offset 504h .
5509
18.12.44USB3 Port Link Info (PORTLI9)—Offset 508h ......................................... 5510
18.12.45Port Status and Control USB3 (PORTSC10)—Offset 510h ........................ 5510
18.12.46Port Power Management Status and Control USB3 (PORTPMSC10)—Offset 514h
5512
18.12.47USB3 Port Link Info (PORTLI10)—Offset 518h ....................................... 5512
18.12.48Port Status and Control USB3 (PORTSC11)—Offset 520h ........................ 5513
18.12.49Port Power Management Status and Control USB3 (PORTPMSC11)—Offset 524h
5514
18.12.50USB3 Port Link Info (PORTLI11)—Offset 528h ....................................... 5515
18.12.51Port Status and Control USB3 (PORTSC12)—Offset 530h ........................ 5515
18.12.52Port Power Management Status and Control USB3 (PORTPMSC12)—Offset 534h
5517
18.12.53USB3 Port Link Info (PORTLI12)—Offset 538h ....................................... 5517
18.12.54Port Status and Control USB3 (PORTSC13)—Offset 540h ........................ 5518
18.12.55Port Power Management Status and Control USB3 (PORTPMSC13)—Offset 544h
5519
18.12.56USB3 Port Link Info (PORTLI13)—Offset 548h ....................................... 5520
18.12.57Port Status and Control USB3 (PORTSC14)—Offset 550h ........................ 5520
18.12.58Port Power Management Status and Control USB3 (PORTPMSC14)—Offset 554h
5521
18.12.59USB3 Port Link Info (PORTLI14)—Offset 558h ....................................... 5522
18.12.60Port Status and Control USB3 (PORTSC15)—Offset 560h ........................ 5522
18.12.61Port Power Management Status and Control USB3 (PORTPMSC15)—Offset 564h
5524
18.12.62USB3 Port Link Info (PORTLI15)—Offset 568h ....................................... 5524
18.12.63Microframe Index (RTMFINDEX)—Offset 2000h ..................................... 5525
18.12.64Interrupter 1 Management (IMAN0)—Offset 2020h ................................ 5525
18.12.65Interrupter 1 Moderation (IMOD0)—Offset 2024h .................................. 5526
18.12.66Event Ring Segment Table Size 1 (ERSTSZ0)—Offset 2028h ................... 5526
18.12.67Event Ring Segment Table Base Address Low 1 (ERSTBA_LO0)—Offset 2030h..
5527

138 334818
 18.12.68Event Ring Segment Table Base Address High 1 (ERSTBA_HI0)—Offset 2034h ..
5527
18.12.69Event Ring Dequeue Pointer Low 1 (ERDP_LO0)—Offset 2038h ................5528
18.12.70Event Ring Dequeue Pointer High 1 (ERDP_HI0)—Offset 203Ch................5528
18.12.71Interrupter 2 Management (IMAN1)—Offset 2040h.................................5529
18.12.72Interrupter 2 Moderation (IMOD1)—Offset 2044h ...................................5529
18.12.73Event Ring Segment Table Size 2 (ERSTSZ1)—Offset 2048h ....................5530
18.12.74Event Ring Segment Table Base Address Low 2 (ERSTBA_LO1)—Offset 2050h ..
5530
18.12.75Event Ring Segment Table Base Address High 2 (ERSTBA_HI1)—Offset 2054h ..
5531
18.12.76Event Ring Dequeue Pointer Low 2 (ERDP_LO1)—Offset 2058h ................5531
18.12.77Event Ring Dequeue Pointer High 2 (ERDP_HI1)—Offset 205Ch................5532
18.12.78Interrupter 3 Management (IMAN2)—Offset 2060h.................................5532
18.12.79Interrupter 3 Moderation (IMOD2)—Offset 2064h ...................................5533
18.12.80Event Ring Segment Table Size 3 (ERSTSZ2)—Offset 2068h ....................5533
18.12.81Event Ring Segment Table Base Address Low 3 (ERSTBA_LO2)—Offset 2070h ..
5534
18.12.82Event Ring Segment Table Base Address High 3 (ERSTBA_HI2)—Offset 2074h ..
5534
18.12.83Event Ring Dequeue Pointer Low 3 (ERDP_LO2)—Offset 2078h ................5535
18.12.84Event Ring Dequeue Pointer High 3 (ERDP_HI2)—Offset 207Ch................5535
18.12.85Interrupter 4 Management (IMAN3)—Offset 2080h.................................5536
18.12.86Interrupter 4 Moderation (IMOD3)—Offset 2084h ...................................5536
18.12.87Event Ring Segment Table Size 4 (ERSTSZ3)—Offset 2088h ....................5537
18.12.88Event Ring Segment Table Base Address Low 4 (ERSTBA_LO3)—Offset 2090h ..
5537
18.12.89Event Ring Segment Table Base Address High 4 (ERSTBA_HI3)—Offset 2094h ..
5538
18.12.90Event Ring Dequeue Pointer Low 4 (ERDP_LO3)—Offset 2098h ................5538
18.12.91Event Ring Dequeue Pointer High 4 (ERDP_HI3)—Offset 209Ch................5539
18.12.92Interrupter 5 Management (IMAN4)—Offset 20A0h.................................5539
18.12.93Interrupter 5 Moderation (IMOD4)—Offset 20A4h...................................5540
18.12.94Event Ring Segment Table Size 5 (ERSTSZ4)—Offset 20A8h ....................5540
18.12.95Event Ring Segment Table Base Address Low 5 (ERSTBA_LO4)—Offset 20B0h ..
5541
18.12.96Event Ring Segment Table Base Address High 5 (ERSTBA_HI4)—Offset 20B4h ..
5541
18.12.97Event Ring Dequeue Pointer Low 5 (ERDP_LO4)—Offset 20B8h ................5542
18.12.98Event Ring Dequeue Pointer High 5 (ERDP_HI4)—Offset 20BCh................5542
18.12.99Interrupter 6 Management (IMAN5)—Offset 20C0h.................................5543
18.12.100Interrupter 6 Moderation (IMOD5)—Offset 20C4h .................................5543
18.12.101Event Ring Segment Table Size 6 (ERSTSZ5)—Offset 20C8h ..................5544
18.12.102Event Ring Segment Table Base Address Low 6 (ERSTBA_LO5)—Offset 20D0h
5544
18.12.103Event Ring Segment Table Base Address High 6 (ERSTBA_HI5)—Offset 20D4h
5545
18.12.104Event Ring Dequeue Pointer Low 6 (ERDP_LO5)—Offset 20D8h ..............5545
18.12.105Event Ring Dequeue Pointer High 6 (ERDP_HI5)—Offset 20DCh..............5546
18.12.106Interrupter 7 Management (IMAN6)—Offset 20E0h ...............................5546
18.12.107Interrupter 7 Moderation (IMOD6)—Offset 20E4h .................................5547
18.12.108Event Ring Segment Table Size 7 (ERSTSZ6)—Offset 20E8h ..................5547
18.12.109Event Ring Segment Table Base Address Low 7 (ERSTBA_LO6)—Offset 20F0h.
5548
18.12.110Event Ring Segment Table Base Address High 7 (ERSTBA_HI6)—Offset 20F4h
5548

334818 139
 18.12.111Event Ring Dequeue Pointer Low 7 (ERDP_LO6)—Offset 20F8h .............. 5549
18.12.112Event Ring Dequeue Pointer High 7 (ERDP_HI6)—Offset 20FCh.............. 5549
18.12.113Interrupter 8 Management (IMAN7)—Offset 2100h .............................. 5550
18.12.114Interrupter 8 Moderation (IMOD7)—Offset 2104h................................. 5550
18.12.115Event Ring Segment Table Size 8 (ERSTSZ7)—Offset 2108h.................. 5551
18.12.116Event Ring Segment Table Base Address Low 8 (ERSTBA_LO7)—Offset 2110h
5551
18.12.117Event Ring Segment Table Base Address High 8 (ERSTBA_HI7)—Offset 2114h
5552
18.12.118Event Ring Dequeue Pointer Low 8 (ERDP_LO7)—Offset 2118h .............. 5552
18.12.119Event Ring Dequeue Pointer High 8 (ERDP_HI7)—Offset 211Ch ............. 5553
18.12.120Door Bell 1 (DB0)—Offset 3000h ....................................................... 5553
18.12.121Door Bell 2 (DB1)—Offset 3004h ....................................................... 5554
18.12.122Door Bell 3 (DB2)—Offset 3008h ....................................................... 5554
18.12.123Door Bell 4 (DB3)—Offset 300Ch ....................................................... 5555
18.12.124Door Bell 5 (DB4)—Offset 3010h ....................................................... 5555
18.12.125Door Bell 6 (DB5)—Offset 3014h ....................................................... 5556
18.12.126Door Bell 7 (DB6)—Offset 3018h ....................................................... 5556
18.12.127Door Bell 8 (DB7)—Offset 301Ch ....................................................... 5557
18.12.128Door Bell 9 (DB8)—Offset 3020h ....................................................... 5558
18.12.129Door Bell 10 (DB9)—Offset 3024h...................................................... 5558
18.12.130Door Bell 11 (DB10)—Offset 3028h .................................................... 5559
18.12.131Door Bell 12 (DB11)—Offset 302Ch.................................................... 5559
18.12.132Door Bell 13 (DB12)—Offset 3030h .................................................... 5560
18.12.133Door Bell 14 (DB13)—Offset 3034h .................................................... 5560
18.12.134Door Bell 15 (DB14)—Offset 3038h .................................................... 5561
18.12.135Door Bell 16 (DB15)—Offset 303Ch.................................................... 5561
18.12.136Door Bell 17 (DB16)—Offset 3040h .................................................... 5562
18.12.137Door Bell 18 (DB17)—Offset 3044h .................................................... 5562
18.12.138Door Bell 19 (DB18)—Offset 3048h .................................................... 5563
18.12.139Door Bell 20 (DB19)—Offset 304Ch.................................................... 5564
18.12.140Door Bell 21 (DB20)—Offset 3050h .................................................... 5564
18.12.141Door Bell 22 (DB21)—Offset 3054h .................................................... 5565
18.12.142Door Bell 23 (DB22)—Offset 3058h .................................................... 5565
18.12.143Door Bell 24 (DB23)—Offset 305Ch.................................................... 5566
18.12.144Door Bell 25 (DB24)—Offset 3060h .................................................... 5566
18.12.145Door Bell 26 (DB25)—Offset 3064h .................................................... 5567
18.12.146Door Bell 27 (DB26)—Offset 3068h .................................................... 5567
18.12.147Door Bell 28 (DB27)—Offset 306Ch.................................................... 5568
18.12.148Door Bell 29 (DB28)—Offset 3070h .................................................... 5568
18.12.149Door Bell 30 (DB29)—Offset 3074h .................................................... 5569
18.12.150Door Bell 31 (DB30)—Offset 3078h .................................................... 5570
18.12.151Door Bell 32 (DB31)—Offset 307Ch.................................................... 5570
18.12.152Door Bell 32 (DB32)—Offset 3080h .................................................... 5571
18.12.153XECP_SUPP_USB2_0 (XECP_SUPP_USB2_0)—Offset 8000h................... 5571
18.12.154XECP_SUPP_USB2_1 (XECP_SUPP_USB2_1)—Offset 8004h................... 5572
18.12.155XECP_SUPP_USB2_2 (XECP_SUPP_USB2_2)—Offset 8008h................... 5572
18.12.156XECP_SUPP_USB2_3 (Full Speed) (XECP_SUPP_USB2_3)—Offset 8010h. 5573
18.12.157XECP_SUPP_USB2_4 (Low Speed) (XECP_SUPP_USB2_4)—Offset 8014h 5574
18.12.158XECP_SUPP_USB2_5 (High Speed) (XECP_SUPP_USB2_5)—Offset 8018h 5574
18.12.159XECP_SUPP_USB3_0 (XECP_SUPP_USB3_0)—Offset 8020h................... 5575
18.12.160XECP_SUPP_USB3_1 (XECP_SUPP_USB3_1)—Offset 8024h................... 5576
18.12.161XECP_SUPP_USB3_2 (XECP_SUPP_USB3_2)—Offset 8028h................... 5576
18.12.162XECP_SUPP_USB3_3 (XECP_SUPP_USB3_3)—Offset 8030h................... 5577
18.12.163XECP_SUPP_USB3_4 (XECP_SUPP_USB3_4)—Offset 8034h................... 5578

140 334818
 18.12.164XECP_SUPP_USB3_5 (XECP_SUPP_USB3_5)—Offset 8038h ...................5578
18.12.165XECP_SUPP_USB3_6 (XECP_SUPP_USB3_6)—Offset 803Ch ...................5579
18.12.166XECP_SUPP_USB3_7 (XECP_SUPP_USB3_7)—Offset 8040h ...................5579
18.12.167XECP_SUPP_USB3_8 (XECP_SUPP_USB3_8)—Offset 8044h ...................5580
18.12.168XECP_SUPP_USB3_9 (XECP_SUPP_USB3_9)—Offset 8048h ...................5581
18.12.169Host Controller Capability (HOST_CTRL_CAP_REG)—Offset 8070h ..........5581
18.12.170Override EP Flow Control (HOST_CLR_MASK_REG)—Offset 8078h ..........5582
18.12.171Clear Active IN EP ID Control (HOST_CLR_IN_EP_VALID_REG)—Offset 807Ch.
5583
18.12.172Clear Poll Mask Control (HOST_CLR_PMASK_REG)—Offset 8080h ...........5584
18.12.173Host Control Scheduler (HOST_CTRL_SCH_REG)—Offset 8094h .............5584
18.12.174Global Port Control (HOST_CTRL_PORT_CTRL)—Offset 80A0h ................5585
18.12.175PGCB Control (PGCBCTRL_REG)—Offset 80A8h ....................................5586
18.12.176D0I3 Control (DOI3CTRL_REG)—Offset 80ACh .....................................5589
18.12.177HOST_CTRL_MISC_REG (HOST_CTRL_MISC_REG)—Offset 80B0h...........5590
18.12.178HOST_CTRL_MISC_REG2 (HOST_CTRL_MISC_REG2)—Offset 80B4h .......5592
18.12.179SSPE_REG (SSPE_REG)—Offset 80B8h ...............................................5594
18.12.180(SSPITPE)—Offset 80BCh ..................................................................5594
18.12.181AUX Reset Control (AUX_CTRL_REG)—Offset 80C0h .............................5595
18.12.182Super Speed Bandwidth Overload (HOST_BW_OV_SS_REG)—Offset 80C4h ....
5597
18.12.183High Speed TT Bandwidth Overload (HOST_BW_OV_HS_REG)—Offset 80C8h..
5598
18.12.184Bandwidth Overload Full Low Speed (HOST_BW_OV_FS_LS_REG)—Offset
80CCh ...............................................................................................5599
18.12.185System Bandwidth Overload (HOST_BW_OV_SYS_REG)—Offset 80D0h...5599
18.12.186Scheduler Async Delay (HOST_CTRL_SCH_ASYNC_DELAY_REG)—Offset
80D4h ...............................................................................................5600
18.12.187DEVICE MODE CONTROL REG 0 (DUAL_ROLE_CFG_REG0)—Offset 80D8h5601
18.12.188DEVICE MODE CONTROL REG 1 (DUAL_ROLE_CFG_REG1)—Offset 80DCh5603
18.12.189AUX Power Management Control (AUX_CTRL_REG1)—Offset 80E0h ........5604
18.12.190Battery Charge (BATTERY_CHARGE_REG)—Offset 80E4h.......................5606
18.12.191Port Watermark (HOST_CTRL_WATERMARK_REG)—Offset 80E8h ...........5607
18.12.192SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG)—Offset 80ECh .
5607
18.12.193USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1)—Offset 80F0h.5609
18.12.194USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2)—Offset 80F4h.5611
18.12.195USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3)—Offset 80F8h.5612
18.12.196USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4)—Offset 80FCh 5612
18.12.197Bandwidth Calc Control (HOST_CTRL_BW_CTRL_REG)—Offset 8100h .....5613
18.12.198Host Interface Control (HOST_IF_CTRL_REG)—Offset 8108h..................5613
18.12.199Bandwidth Overload Burst (HOST_BW_OV_BURST_REG)—Offset 810Ch ..5614
18.12.200USB Max Bandwidth Control 4 (HOST_CTRL_BW_MAX_REG)—Offset 8128h ....
5615
18.12.201USB2 Linestate Debug (LINESTATE_DEBUG_REG)—Offset 8130h............5615
18.12.202USB2 Protocol Gap Timer (USB2_PROTOCOL_GAP_TIMER_REG)—Offset 8134h
5616
18.12.203USB2 Protocol Bus Timeout Timer (USB2_PROTOCOL_BTO_TIMER_REG)—
Offset 813Ch ......................................................................................5617
18.12.204Power Scheduler Control-0 (PWR_SCHED_CTRL0)—Offset 8140h............5618
18.12.205Power Scheduler Control-2 (PWR_SCHED_CTRL2)—Offset 8144h............5618
18.12.206AUX Power Management Control (AUX_CTRL_REG2)—Offset 8154h ........5619
18.12.207USB2 PHY Power Management Control (USB2_PHY_PMC)—Offset 8164h..5622
18.12.208USB Power Gating Control (USB_PGC)—Offset 8168h............................5623
18.12.209xHCI Aux Clock Control Register (XHCI_AUX_CCR)—Offset 816Ch ..........5624

334818 141
 18.12.210USB LPM Parameters (USB_LPM_PARAM)—Offset 8170h ....................... 5626
18.12.211xHC Latency Tolerance Parameters - LTV Control (XLTP_LTV1)—Offset 8174h
5627
18.12.212xHC Latency Tolerance Parameters LTV Control 2 (XLTP_LTV2)—Offset 8178h
5628
18.12.213xHC Latency Tolerance Parameters - High Idle Time Control (XLTP_HITC)—
Offset 817Ch...................................................................................... 5629
18.12.214xHC Latency Tolerance Parameters - Medium Idle Time Control (XLTP_MITC)—
Offset 8180h ...................................................................................... 5630
18.12.215xHC Latency Tolerance Parameters Low Idle Time Control (XLTP_LITC)—Offset
8184h ............................................................................................... 5631
18.12.216HOST_CTRL_BW_MAX3_REG (HOST_CTRL_BW_MAX3_REG)—Offset 8188h ...
5631
18.12.217PDDIS_REG (PDDIS_REG)—Offset 8198h ........................................... 5632
18.12.218LFPS_PM_CTRL_REG (LFPS_PM_CTRL_REG)—Offset 81A0h ................... 5632
18.12.219U2PDM (U2PDM)—Offset 81A4h......................................................... 5633
18.12.220U2PCM (U2PCM)—Offset 81A8h ......................................................... 5633
18.12.221U3PDM (U3PDM)—Offset 81ACh ........................................................ 5634
18.12.222U3PCM (U3PCM)—Offset 81B0h ......................................................... 5634
18.12.223THRM_HOST_CTRL_REG2 (THRM_HOST_CTRL_REG2)—Offset 81B4h ..... 5635
18.12.224(D0i2_CTRL_REG)—Offset 81BCh ...................................................... 5635
18.12.225 (D0i2_SCH_ALARM_CTRL_REG)—Offset 81C0h................................... 5637
18.12.226 (USB2PMCTRL_REG)—Offset 81C4h .................................................. 5638
18.12.227ECC_PARITY_ERROR_LOG_REG (ECC_PARITY_ERROR_LOG_REG)—Offset
83F8h ............................................................................................... 5640
18.12.228ECC_POISONING_CTRL_REG (ECC_POISONING_CTRL_REG)—Offset 83FCh ...
5643
18.12.229USB2_PORT_STATE_REG (USB2_PORT_STATE_REG)—Offset 8400h....... 5644
18.12.230USB3_PORT_STATE_REG (USB3_PORT_STATE_REG)—Offset 8408h....... 5645
18.12.231FUS1_REG (FUS1_REG)—Offset 8410h ............................................... 5645
18.12.232FUS2_REG (FUS2_REG)—Offset 8414h ............................................... 5646
18.12.233FUS3_REG (FUS3_REG)—Offset 8418h ............................................... 5647
18.12.234STRAP1_REG (STRAP1_REG)—Offset 841Ch........................................ 5647
18.12.235STRAP3_REG (STRAP3_REG)—Offset 8424h ........................................ 5648
18.12.236XECP_CMDM_STS0 (XECP_CMDM_STS0)—Offset 8448h ....................... 5649
18.12.237XECP_CMDM_STS1 (XECP_CMDM_STS1)—Offset 844Ch ....................... 5650
18.12.238XECP_CMDM_STS2 (XECP_CMDM_STS2)—Offset 8450h ....................... 5651
18.12.239XECP_CMDM_STS3 (XECP_CMDM_STS3)—Offset 8454h ....................... 5651
18.12.240XECP_CMDM_STS4 (XECP_CMDM_STS4)—Offset 8458h ....................... 5652
18.12.241XECP_CMDM_STS5 (XECP_CMDM_STS5)—Offset 845Ch ....................... 5652
18.12.242AUX Power PHY Reset (UPORTS_PON_RST_REG)—Offset 8460h............. 5653
18.12.243Latency Tolerance Control 0 (HOST_IF_LAT_TOL_CTRL_REG0)—Offset 8464h
5653
18.12.244USB Legacy Support Capability (USBLEGSUP)—Offset 846Ch................. 5654
18.12.245USB Legacy Support Control Status (USBLEGCTLSTS)—Offset 8470h...... 5655
18.12.246Port Disable Override capability register (PDO_CAPABILITY)—Offset 84F4h ....
5656
18.12.247USB2 Port Disable Override (USB2PDO)—Offset 84F8h ......................... 5656
18.12.248USB3 Port Disable Override (USB3PDO)—Offset 84FCh ......................... 5657
18.12.249HW state capability register (HW_STATE_CAPABILITY)—Offset 8500h..... 5657
18.12.250HW state register 1 (HW_STATE_REG1)—Offset 8504h ......................... 5658
18.12.251HW state register 2 (HW_STATE_REG2)—Offset 8508h ......................... 5658
18.12.252HW state register 3 (HW_STATE_REG3)—Offset 850Ch......................... 5659
18.12.253HW state register 4 (HW_STATE_REG4)—Offset 8510h ......................... 5659
18.12.254CONFIG mirror capability register (CONFIG_MIRROR_CAPABILITY)—Offset
8600h ............................................................................................... 5660

142 334818
 18.12.255Command (CMD_MMIO)—Offset 8604h ...............................................5660
18.12.256Device Status (STS_MMIO)—Offset 8606h...........................................5662
18.12.257Revision ID (RID_MMIO)—Offset 8608h ..............................................5663
18.12.258Programming Interface (PI_MMIO)—Offset 8609h ................................5663
18.12.259Sub Class Code (SCC_MMIO)—Offset 860Ah ........................................5664
18.12.260Base Class Code (BCC_MMIO)—Offset 860Bh.......................................5664
18.12.261Master Latency Timer (MLT_MMIO)—Offset 860Dh ...............................5664
18.12.262Header Type (HT_MMIO)—Offset 860Eh ..............................................5665
18.12.263Memory Base Address (MBAR_MMIO)—Offset 8610h.............................5665
18.12.264USB Subsystem Vendor ID (SSVID_MMIO)—Offset 862Ch .....................5666
18.12.265USB Subsystem ID (SSID_MMIO)—Offset 862Eh ..................................5666
18.12.266Capabilities Pointer (CAP_PTR_MMIO)—Offset 8634h ............................5667
18.12.267Interrupt Line (ILINE_MMIO)—Offset 863Ch ........................................5667
18.12.268Interrupt Pin (IPIN_MMIO)—Offset 863Dh ...........................................5668
18.12.269XHC System Bus Configuration 1 (XHCC1_MMIO)—Offset 8640h ............5668
18.12.270Clock Gating (XHCLKGTEN_MMIO)—Offset 8650h .................................5670
18.12.271Audio Time Synchronization (AUDSYNC_MMIO)—Offset 8658h ...............5675
18.12.272Serial Bus Release Number (SBRN_MMIO)—Offset 8660h ......................5675
18.12.273Frame Length Adjustment (FLADJ_MMIO)—Offset 8661h .......................5676
18.12.274Best Effort Service Latency (BESL_MMIO)—Offset 8662h .......................5677
18.12.275PCI Power Management Capability ID (PM_CID_MMIO)—Offset 8670h.....5678
18.12.276Next Item Pointer #1 (PM_NEXT_MMIO)—Offset 8671h.........................5678
18.12.277Power Management Capabilities (PM_CAP_MMIO)—Offset 8672h ............5679
18.12.278Power Management Control/Status (PM_CS_MMIO)—Offset 8674h .........5680
18.12.279Message Signaled Interrupt CID (MSI_CID_MMIO)—Offset 8680h...........5681
18.12.280Next item pointer (MSI_NEXT_MMIO)—Offset 8681h.............................5682
18.12.281Message Signaled Interrupt Message Control (MSI_MCTL_MMIO)—Offset
8682h................................................................................................5682
18.12.282Message Signaled Interrupt Message Address (MSI_MAD_MMIO)—Offset 8684h
5683
18.12.283Message Signaled Interrupt Upper Address (MSI_MUAD_MMIO)—Offset 8688h
5683
18.12.284Message Signaled Interrupt Message Data (MSI_MD_MMIO)—Offset 868Ch ....
5684
18.12.285Device Idle Capability (DEVIDLE_MMIO)—Offset 8690h .........................5684
18.12.286Vendor Specific Header (VSHDR_MMIO)—Offset 8694h .........................5685
18.12.287SW LTR POINTER (SWLTRPTR_MMIO)—Offset 8698h ............................5686
18.12.288Device Idle Pointer Register (DEVIDLEPTR_MMIO)—Offset 869Ch ...........5687
18.12.289Device Idle Power ON Latency (DEVIDLEPOL_MMIO)—Offset 86A0h ........5688
18.12.290High Speed Configuration 2 (HSCFG2_MMIO)—Offset 86A4h..................5688
18.12.291XHCI USB2 Overcurrent Pin Mapping 1 (U2OCM1_MMIO)—Offset 86B0h ..5690
18.12.292XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM2_MMIO)—Offset 86B4h ..5690
18.12.293XHCI USB3 Overcurrent Pin Mapping 1 (U3OCM1_MMIO)—Offset 86D0h..5691
18.12.294XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM2_MMIO)—Offset 86D4h..5691
18.12.295XHCC3 (XHCC3_MMIO)—Offset 86FCh ................................................5692
18.12.296Debug Capability ID Register (DCID)—Offset 8700h..............................5693
18.12.297Debug Capability Doorbell Register (DCDB)—Offset 8704h.....................5693
18.12.298Debug Capability Event Ring Segment Table Size Register (DCERSTSZ)—Offset
8708h................................................................................................5694
18.12.299Debug Capability Event Ring Segment Table Base Address Register
(DCERSTBA)—Offset 8710h ..................................................................5695
18.12.300Debug Capability Event Ring Dequeue Pointer Register (DCERDP)—Offset
8718h................................................................................................5695
18.12.301Debug Capability Control Register (DCCTRL)—Offset 8720h ...................5696
18.12.302Debug Capability Status Register (DCST)—Offset 8724h........................5697

334818 143
 18.12.303Debug Capability Port Status and Control Register (DCPORTSC)—Offset 8728h
5697
18.12.304Debug Capability Context Pointer Register (DCCP)—Offset 8730h........... 5699
18.12.305Debug Capability Device Descriptor Info Register 1 (DCDDI1)—Offset 8738h ..
5700
18.12.306Debug Capability Device Descriptor Info Register 2 (DCDDI2)—Offset 873Ch..
5700
18.12.307Debug Capability Descriptor Parameters (DCDP)—Offset 8740h ............. 5701
18.12.308..................................................................................................... 5702
18.12.309Debug Device Control ODMA (DBGDEV_CTRL_ODMA_REG)—Offset 8748h .....
5702
18.12.310DBC Control Register 1 (DBCCTL_REG)—Offset 8760h .......................... 5703
18.12.311(PORT1_PROFILE_ATTRIBUTES_REG0)—Offset 890Ch .......................... 5703
18.12.312(PORT1_PROFILE_ATTRIBUTES_REG1)—Offset 8910h .......................... 5704
18.12.313(PORT1_PROFILE_ATTRIBUTES_REG2)—Offset 8914h .......................... 5705
18.12.314(PORT1_PROFILE_ATTRIBUTES_REG3)—Offset 8918h .......................... 5705
18.12.315(PORT1_PROFILE_ATTRIBUTES_REG4)—Offset 891Ch .......................... 5706
18.12.316(PORT1_PROFILE_ATTRIBUTES_REG5)—Offset 8920h .......................... 5707
18.12.317(PORT1_PROFILE_ATTRIBUTES_REG6)—Offset 8924h .......................... 5707
18.12.318(PORT1_PROFILE_ATTRIBUTES_REG7)—Offset 8928h .......................... 5708
18.12.319(PORT1_PROFILE_ATTRIBUTES_REG8)—Offset 892Ch .......................... 5709
18.12.320(PORT1_PROFILE_ATTRIBUTES_REG9)—Offset 8930h .......................... 5709
18.12.321(PORT1_PROFILE_ATTRIBUTES_REG10)—Offset 8934h ........................ 5710
18.12.322(PORT1_PROFILE_ATTRIBUTES_REG11)—Offset 8938h ........................ 5711
18.12.323(PORT1_PROFILE_ATTRIBUTES_REG12)—Offset 893Ch ........................ 5711
18.12.324(PORT1_PROFILE_ATTRIBUTES_REG13)—Offset 8940h ........................ 5712
18.12.325(PORT1_PROFILE_ATTRIBUTES_REG14)—Offset 8944h ........................ 5713
18.12.326(PORT1_PROFILE_ATTRIBUTES_REG15)—Offset 8948h ........................ 5713
18.12.327(PORT1_PROFILE_ATTRIBUTES_REG16)—Offset 894Ch ........................ 5714
18.12.328(PORT1_PROFILE_ATTRIBUTES_REG17)—Offset 8950h ........................ 5715
18.12.329(PORT1_PROFILE_ATTRIBUTES_REG18)—Offset 8954h ........................ 5715
18.12.330(PORT1_PROFILE_ATTRIBUTES_REG19)—Offset 8958h ........................ 5716
18.12.331(PORT1_PROFILE_ATTRIBUTES_REG20)—Offset 895Ch ........................ 5717
18.12.332(PORT1_PROFILE_ATTRIBUTES_REG21)—Offset 8960h ........................ 5717
18.12.333(PORT1_PROFILE_ATTRIBUTES_REG22)—Offset 8964h ........................ 5718
18.12.334(PORT1_PROFILE_ATTRIBUTES_REG23)—Offset 8968h ........................ 5719
18.12.335(PORT1_PROFILE_ATTRIBUTES_REG24)—Offset 896Ch ........................ 5719
18.12.336(PORT1_PROFILE_ATTRIBUTES_REG25)—Offset 8970h ........................ 5720
18.12.337(PORT1_PROFILE_ATTRIBUTES_REG26)—Offset 8974h ........................ 5721
18.12.338(PORT1_PROFILE_ATTRIBUTES_REG27)—Offset 8978h ........................ 5721
18.12.339(PORT1_PROFILE_ATTRIBUTES_REG28)—Offset 897Ch ........................ 5722
18.12.340(PORT1_PROFILE_ATTRIBUTES_REG29)—Offset 8980h ........................ 5723
18.12.341(PORT1_PROFILE_ATTRIBUTES_REG30)—Offset 8984h ........................ 5723
18.12.342(PORT1_PROFILE_ATTRIBUTES_REG31)—Offset 8988h ........................ 5724
18.12.343(PORT1_PROFILE_ATTRIBUTES_REG32)—Offset 898Ch ........................ 5725
18.12.344(PORT1_PROFILE_ATTRIBUTES_REG33)—Offset 8990h ........................ 5725
18.12.345(PORT1_PROFILE_ATTRIBUTES_REG34)—Offset 8994h ........................ 5726
18.12.346(PORT1_PROFILE_ATTRIBUTES_REG35)—Offset 8998h ........................ 5727
18.12.347(PORT1_PROFILE_ATTRIBUTES_REG36)—Offset 899Ch ........................ 5727
18.12.348(PORT1_PROFILE_ATTRIBUTES_REG37)—Offset 89A0h ........................ 5728
18.12.349(PORT1_PROFILE_ATTRIBUTES_REG38)—Offset 89A4h ........................ 5729
18.12.350(PORT1_PROFILE_ATTRIBUTES_REG39)—Offset 89A8h ........................ 5729
18.12.351(PORT1_PROFILE_ATTRIBUTES_REG40)—Offset 89ACh ........................ 5730
18.12.352(PORT1_PROFILE_ATTRIBUTES_REG41)—Offset 89B0h ........................ 5731
18.12.353(PORT1_PROFILE_ATTRIBUTES_REG42)—Offset 89B4h ........................ 5731

144 334818
 18.12.354(PORT1_PROFILE_ATTRIBUTES_REG43)—Offset 89B8h .........................5732
18.12.355(PORT1_PROFILE_ATTRIBUTES_REG44)—Offset 89BCh.........................5733
18.12.356(PORT1_PROFILE_ATTRIBUTES_REG45)—Offset 89C0h .........................5733
18.12.357(PORT1_PROFILE_ATTRIBUTES_REG46)—Offset 89C4h .........................5734
18.12.358(PORT1_PROFILE_ATTRIBUTES_REG47)—Offset 89C8h .........................5735
18.12.359(PORT1_PROFILE_ATTRIBUTES_REG48)—Offset 89CCh.........................5735
18.12.360(PORT1_PROFILE_ATTRIBUTES_REG49)—Offset 89D0h.........................5736
18.12.361(PORT1_PROFILE_ATTRIBUTES_REG50)—Offset 89D4h.........................5737
18.12.362(PORT1_PROFILE_ATTRIBUTES_REG51)—Offset 89D8h.........................5737
18.12.363(PORT1_PROFILE_ATTRIBUTES_REG52)—Offset 89DCh ........................5738
18.12.364(PORT1_PROFILE_ATTRIBUTES_REG53)—Offset 89E0h .........................5739
18.12.365(PORT1_PROFILE_ATTRIBUTES_REG54)—Offset 89E4h .........................5739
18.12.366(PORT1_PROFILE_ATTRIBUTES_REG55)—Offset 89E8h .........................5740
18.12.367(PORT1_PROFILE_ATTRIBUTES_REG56)—Offset 89ECh .........................5741
18.12.368(PORT1_PROFILE_ATTRIBUTES_REG57)—Offset 89F0h .........................5741
18.12.369(PORT1_PROFILE_ATTRIBUTES_REG58)—Offset 89F4h .........................5742
18.12.370(PORT1_PROFILE_ATTRIBUTES_REG59)—Offset 89F8h .........................5743
18.12.371(PORT1_PROFILE_ATTRIBUTES_REG60)—Offset 89FCh .........................5743
18.12.372(PORT1_PROFILE_ATTRIBUTES_REG61)—Offset 8A00h .........................5744
18.12.373(PORT1_PROFILE_ATTRIBUTES_REG62)—Offset 8A04h .........................5745
18.12.374(PORT1_PROFILE_ATTRIBUTES_REG63)—Offset 8A08h .........................5745
18.12.375GLOBAL_TIME_SYNC_CAP_REG (GLOBAL_TIME_SYNC_CAP_REG)—Offset
8E10h................................................................................................5746
18.12.376GLOBAL_TIME_SYNC_CTRL_REG (GLOBAL_TIME_SYNC_CTRL_REG)—Offset
8E14h................................................................................................5747
18.12.377MICROFRAME_TIME_REG (MICROFRAME_TIME_REG)—Offset 8E18h .......5747
18.12.378GLOBAL_TIME_LOW_REG (GLOBAL_TIME_LOW_REG)—Offset 8E20h ......5748
18.12.379GLOBAL_TIME_HI_REG (GLOBAL_TIME_HI_REG)—Offset 8E24h ............5749
18.12.380Debug Status Capability Register (DEBUG_STATUS_CAPABILITY_REG)—Offset
8E58h................................................................................................5749
18.12.381Host Ctrl USB3 Soft Error Count Register 1
(HOST_CTRL_USB3_ERR_COUNT_REG1)—Offset 8E5Ch ...........................5750
18.12.382Host Ctrl USB3 Soft Error Count Register 2
(HOST_CTRL_USB3_ERR_COUNT_REG2)—Offset 8E60h ...........................5750
18.12.383Host Ctrl USB3 Soft Error Count Register 3
(HOST_CTRL_USB3_ERR_COUNT_REG3)—Offset 8E64h ...........................5751
18.12.384Host Ctrl USB3 Soft Error Count Register 4
(HOST_CTRL_USB3_ERR_COUNT_REG4)—Offset 8E68h ...........................5751
18.12.385Host Ctrl USB3 Soft Error Count Register 5
(HOST_CTRL_USB3_ERR_COUNT_REG5)—Offset 8E6Ch ...........................5752
18.12.386Host Ctrl USB3 Soft Error Count Register 6
(HOST_CTRL_USB3_ERR_COUNT_REG6)—Offset 8E70h ...........................5753
18.12.387Host Ctrl USB3 Soft Error Count Register 7
(HOST_CTRL_USB3_ERR_COUNT_REG7)—Offset 8E74h ...........................5753
18.12.388IOSFCTL - Control Register (IOSFCTL)—Offset 0h .................................5754
18.12.389Power Management Control Register (PMCTL)—Offset 1D0h...................5754
18.12.390PCI Configuration Control 1 Register (PCICFGCTR1)—Offset 200h ...........5755
18.12.391c73usb280_USB2 PER PORT (USB2_PER_PORT_PP0)—Offset 4100h .......5756
18.12.392GLB ADP VBUS COMP REG (GLB_ADP_VBUS_COMP_REG)—Offset 402Bh.5760
18.12.393c73usb280_USB2 COMPBG (USB2_COMPBG)—Offset 7F04h ..................5762
18.12.394CONFIG_3—Offset 7014h ..................................................................5765
18.12.395DBC_GP2_IN_PAYLOAD_BP_LOW—Offset 1Ch .....................................5766
18.12.396DBC_GP2_IN_PAYLOAD_BP_HI—Offset 20h .........................................5766
18.12.397DBC_GP2_IN_PAYLOAD_QUALIFIERS—Offset 24h ................................5766
18.12.398DBC_GP2_IN_STATUS_QUALIFIERS—Offset 34h ..................................5767
18.12.399DBC_GP2_IN_STATUS_BP_LOW—Offset 2Ch .......................................5767

334818 145
 18.12.400DBC_GP2_IN_STATUS_BP_HI—Offset 30h .......................................... 5768
18.12.401Host Control IDMA (HOST_CTRL_IDMA_REG)—Offset 809Ch ................. 5768
18.12.402Host Control Transfer Manager (HOST_CTRL_TRM_REG2) —Offset 8110h 5770
18.12.403Command Manager Control 1 (XECP_CMDM_CTRL_REG1) —Offset 818Ch5773
18.12.404Command Manager Control 2 (XECP_CMDM_CTRL_REG2) —Offset 8190h 5775
18.12.405Command Manager Control 3 (XECP_CMDM_CTRL_REG3) —Offset 8194h 5777
18.12.406Power Control Enable (PCE_REG) —Offset 00A2h ................................. 5778
18.12.407GEN_REGRW4 —Offset 00BCh........................................................... 5778
18.13 Registers Summary........................................................................................ 5781
18.13.1Vendor ID (VID)—Offset 0h.................................................................. 5782
18.13.2Device ID (DID)—Offset 2h .................................................................. 5782
18.13.3Command (CMD)—Offset 4h ................................................................ 5783
18.13.4Device Status (STS)—Offset 6h ............................................................ 5784
18.13.5Revision ID (RID)—Offset 8h ................................................................ 5785
18.13.6Programming Interface (PI)—Offset 9h .................................................. 5785
18.13.7Sub Class Code (SCC)—Offset Ah.......................................................... 5786
18.13.8Base Class Code (BCC)—Offset Bh ........................................................ 5786
18.13.9Master Latency Timer (MLT)—Offset Dh ................................................. 5787
18.13.10Header Type (HT)—Offset Eh .............................................................. 5787
18.13.11Memory Base Address (MBAR)—Offset 10h ........................................... 5787
18.13.12USB Subsystem Vendor ID (SSVID)—Offset 2Ch.................................... 5788
18.13.13USB Subsystem ID (SSID)—Offset 2Eh ................................................ 5789
18.13.14Capabilities Pointer (CAP_PTR)—Offset 34h........................................... 5789
18.13.15Interrupt Line (ILINE)—Offset 3Ch....................................................... 5790
18.13.16Interrupt Pin (IPIN)—Offset 3Dh.......................................................... 5790
18.13.17XHC System Bus Configuration 1 (XHCC1)—Offset 40h........................... 5790
18.13.18Clock Gating (XHCLKGTEN)—Offset 50h ............................................... 5792
18.13.19Audio Time Synchronization (AUDSYNC)—Offset 58h.............................. 5795
18.13.20Serial Bus Release Number (SBRN)—Offset 60h .................................... 5796
18.13.21Frame Length Adjustment (FLADJ)—Offset 61h ..................................... 5796
18.13.22Best Effort Service Latency (BESL)—Offset 62h ..................................... 5797
18.13.23PCI Power Management Capability ID (PM_CID)—Offset 70h ................... 5798
18.13.24Next Item Pointer #1 (PM_NEXT)—Offset 71h ....................................... 5798
18.13.25Power Management Capabilities (PM_CAP)—Offset 72h........................... 5799
18.13.26Power Management Control/Status (PM_CS)—Offset 74h ........................ 5800
18.13.27Message Signaled Interrupt CID (MSI_CID)—Offset 80h ......................... 5801
18.13.28Next item pointer (MSI_NEXT)—Offset 81h ........................................... 5802
18.13.29Message Signaled Interrupt Message Control (MSI_MCTL)—Offset 82h ..... 5802
18.13.30Message Signaled Interrupt Message Address (MSI_MAD)—Offset 84h ..... 5803
18.13.31Message Signaled Interrupt Upper Address (MSI_MUAD)—Offset 88h ....... 5803
18.13.32Message Signaled Interrupt Message Data (MSI_MD)—Offset 8Ch............ 5804
18.13.33Device Idle Capability (DEVIDLE)—Offset 90h ....................................... 5804
18.13.34Vendor Specific Header (VSHDR)—Offset 94h........................................ 5805
18.13.35SW LTR POINTER (SWLTRPTR)—Offset 98h........................................... 5806
18.13.36Device Idle Pointer Register (DEVIDLEPTR)—Offset 9Ch.......................... 5807
18.13.37Device Idle Power ON Latency (DEVIDLEPOL)—Offset A0h ...................... 5807
18.13.38High Speed Configuration 2 (HSCFG2)—Offset A4h ................................ 5808
18.13.39XHCI USB2 Overcurrent Pin Mapping 1 (U2OCM1)—Offset B0h ................ 5809
18.13.40XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM2)—Offset B4h ................ 5810
18.13.41XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM3)—Offset B8h ................ 5810
18.13.42XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM4)—Offset BCh ................ 5811
18.13.43XHCI USB3 Overcurrent Pin Mapping 1 (U3OCM1)—Offset D0h ................ 5811
18.13.44XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM2)—Offset D4h ................ 5812
18.13.45XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM3)—Offset D8h ................ 5812
18.13.46XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM4)—Offset DCh................ 5813

146 334818
 18.13.47XHCC3 (XHCC3)—Offset FCh ...............................................................5813
18.14 Registers Summary ........................................................................................5815
18.14.1DBC_GP2_OUT_PAYLOAD_BP_LOW (DBC_GP2_OUT_PAYLOAD_BP_LOW)—
Offset 0h............................................................................................5822
18.14.2DBC_GP2_OUT_PAYLOAD_BP_HI (DBC_GP2_OUT_PAYLOAD_BP_HI)—Offset 4h .
5823
18.14.3DBC_GP2_OUT_PAYLOAD_QUALIFIERS
(DBC_GP2_OUT_PAYLOAD_QUALIFIERS)—Offset 8h ................................5823
18.14.4DBC_GP2_OUT_PAYLOAD_TRANSFER_LENGTH
(DBC_GP2_OUT_PAYLOAD_TRANSFER_LENGTH)—Offset Ch .....................5824
18.14.5DBC_GP2_OUT_STATUS_BP_LOW (DBC_GP2_OUT_STATUS_BP_LOW)—Offset
10h ...................................................................................................5825
18.14.6DBC_GP2_OUT_STATUS_BP_HI (DBC_GP2_OUT_STATUS_BP_HI)—Offset 14h ...
5825
18.14.7DBC_GP2_OUT_STATUS_QUALIFIERS (DBC_GP2_OUT_STATUS_QUALIFIERS)—
Offset 18h ..........................................................................................5826
18.14.8DBC_GP2_IN_PAYLOAD_BP_LOW (DBC_GP2_IN_PAYLOAD_BP_LOW)—Offset
1Ch ...................................................................................................5827
18.14.9DBC_GP2_IN_PAYLOAD_BP_HI (DBC_GP2_IN_PAYLOAD_BP_HI)—Offset 20h.....
5827
18.14.10DBC_GP2_IN_PAYLOAD_QUALIFIERS (DBC_GP2_IN_PAYLOAD_QUALIFIERS)—
Offset 24h ..........................................................................................5828
18.14.11DBC_GP2_IN_PAYLOAD_TRANSFER_LENGTH
(DBC_GP2_IN_PAYLOAD_TRANSFER_LENGTH)—Offset 28h ......................5829
18.14.12DBC_GP2_IN_STATUS_BP_LOW (DBC_GP2_IN_STATUS_BP_LOW)—Offset 2Ch
5829
18.14.13DBC_GP2_IN_STATUS_BP_HI (DBC_GP2_IN_STATUS_BP_HI)—Offset 30h 5830
18.14.14DBC_GP2_IN_STATUS_QUALIFIERS (DBC_GP2_IN_STATUS_QUALIFIERS)—
Offset 34h ..........................................................................................5831
18.14.15DBC_TRACE_IN_PAYLOAD_BP_LOW (DBC_TRACE_IN_PAYLOAD_BP_LOW)—
Offset 50h ..........................................................................................5831
18.14.16DBC_TRACE_IN_PAYLOAD_BP_HI (DBC_TRACE_IN_PAYLOAD_BP_HI)—Offset
54h ...................................................................................................5832
18.14.17DBC_TRACE_IN_PAYLOAD_QUALIFIERS
(DBC_TRACE_IN_PAYLOAD_QUALIFIERS)—Offset 58h .............................5833
18.14.18DBC_TRACE_IN_PAYLOAD_TRASNFER_DOORBELL
(DBC_TRACE_IN_PAYLOAD_TRANSFER_DOORBELL)—Offset 5Ch ...............5833
18.14.19DBC_TRACE_IN_STATUS_BP_LOW (DBC_TRACE_IN_STATUS_BP_LOW)—Offset
60h ...................................................................................................5834
18.14.20DBC_TRACE_IN_STATUS_BP_HI (DBC_TRACE_IN_STATUS_BP_HI)—Offset 64h
5835
18.14.21DBC_TRACE_IN_STATUS_QUALIFIERS
(DBC_TRACE_IN_STATUS_QUALIFIERS)—Offset 68h ...............................5835
18.14.22DBConEXI Capability Port Status and Control Register (DBC_EXI_DCPORTSC)—
Offset 88h ..........................................................................................5836
18.14.23DEBUG_SW_CONTROL_STATUS_REG (DEBUG_SW_CONTROL_STATUS_REG)—
Offset 100h ........................................................................................5839
18.14.24DEBUG_REQUEST_INFO_AND_STATUS_REG
(DEBUG_REQUEST_INFO_AND_STATUS_REG)—Offset 104h .....................5840
18.14.25DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_0)—Offset 108h .....
5842
18.14.26DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_1)—Offset 10Ch.....
5842
18.14.27DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_2)—Offset 110h .....
5843
18.14.28DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_3)—Offset 114h .....
5844

334818 147
 18.14.29DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_4)—Offset 118h ....
5844
18.14.30DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_5)—Offset 11Ch ....
5845
18.14.31DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_6)—Offset 120h ....
5846
18.14.32DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_7)—Offset 124h ....
5846
18.14.33DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_8)—Offset 128h ....
5847
18.14.34DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_9)—Offset 12Ch ....
5848
18.14.35DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_10)—Offset 130h...
5848
18.14.36DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_11)—Offset 134h...
5849
18.14.37DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_12)—Offset 138h...
5850
18.14.38DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_13)—Offset 13Ch ..
5850
18.14.39DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_14)—Offset 140h...
5851
18.14.40DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_15)—Offset 144h...
5852
18.14.41DEBUG_RESPONSE_INFO_AND_STATUS_REG
(DEBUG_RESPONSE_INFO_AND_STATUS_REG)—Offset 148h ................... 5852
18.14.42DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_0)—Offset 180h ........................ 5853
18.14.43DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_1)—Offset 184h ........................ 5854
18.14.44DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_2)—Offset 188h ........................ 5854
18.14.45DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_3)—Offset 18Ch ........................ 5855
18.14.46DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_4)—Offset 190h ........................ 5855
18.14.47DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_5)—Offset 194h ........................ 5856
18.14.48DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_6)—Offset 198h ........................ 5856
18.14.49DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_7)—Offset 19Ch ........................ 5857
18.14.50DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_8)—Offset 1A0h ........................ 5858
18.14.51DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_9)—Offset 1A4h ........................ 5858
18.14.52DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_10)—Offset 1A8h ...................... 5859
18.14.53DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_11)—Offset 1ACh ...................... 5859
18.14.54DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_12)—Offset 1B0h ...................... 5860
18.14.55DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_13)—Offset 1B4h ...................... 5861
18.14.56DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_14)—Offset 1B8h ...................... 5861

148 334818
 18.14.57DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_15)—Offset 1BCh .......................5862
18.14.58DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_16)—Offset 1C0h .......................5862
18.14.59DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_17)—Offset 1C4h .......................5863
18.14.60DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_18)—Offset 1C8h .......................5864
18.14.61DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_19)—Offset 1CCh .......................5864
18.14.62DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_20)—Offset 1D0h .......................5865
18.14.63DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_21)—Offset 1D4h .......................5865
18.14.64DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_22)—Offset 1D8h .......................5866
18.14.65DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_23)—Offset 1DCh.......................5867
18.14.66DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_24)—Offset 1E0h .......................5867
18.14.67DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_25)—Offset 1E4h .......................5868
18.14.68DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_26)—Offset 1E8h .......................5868
18.14.69DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_27)—Offset 1ECh .......................5869
18.14.70DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_28)—Offset 1F0h .......................5870
18.14.71DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_29)—Offset 1F4h .......................5870
18.14.72DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_30)—Offset 1F8h .......................5871
18.14.73DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_31)—Offset 1FCh .......................5871
18.14.74DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_32)—Offset 200h .......................5872
18.14.75DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_33)—Offset 204h .......................5873
18.14.76DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_34)—Offset 208h .......................5873
18.14.77DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_35)—Offset 20Ch .......................5874
18.14.78DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_36)—Offset 210h .......................5874
18.14.79DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_37)—Offset 214h .......................5875
18.14.80DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_38)—Offset 218h .......................5876
18.14.81DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_39)—Offset 21Ch .......................5876
18.14.82DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_40)—Offset 220h .......................5877
18.14.83DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_41)—Offset 224h .......................5877
18.14.84DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_42)—Offset 228h .......................5878

334818 149
 18.14.85DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_43)—Offset 22Ch ...................... 5879
18.14.86DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_44)—Offset 230h....................... 5879
18.14.87DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_45)—Offset 234h....................... 5880
18.14.88DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_46)—Offset 238h....................... 5880
18.14.89DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_47)—Offset 23Ch ...................... 5881
18.14.90DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_48)—Offset 240h....................... 5882
18.14.91DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_49)—Offset 244h....................... 5882
18.14.92DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_50)—Offset 248h....................... 5883
18.14.93DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_51)—Offset 24Ch ...................... 5883
18.14.94DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_52)—Offset 250h....................... 5884
18.14.95DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_53)—Offset 254h....................... 5885
18.14.96DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_54)—Offset 258h....................... 5885
18.14.97DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_55)—Offset 25Ch ...................... 5886
18.14.98DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_56)—Offset 260h....................... 5886
18.14.99DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_57)—Offset 264h....................... 5887
18.14.100DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_58)—Offset 268h....................... 5888
18.14.101DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_59)—Offset 26Ch ...................... 5888
18.14.102DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_60)—Offset 270h....................... 5889
18.14.103DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_61)—Offset 274h....................... 5889
18.14.104DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_62)—Offset 278h....................... 5890
18.14.105DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_63)—Offset 27Ch ...................... 5891
18.14.106DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_64)—Offset 280h....................... 5891
18.14.107DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_65)—Offset 284h....................... 5892
18.14.108DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_66)—Offset 288h....................... 5892
18.14.109DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_67)—Offset 28Ch ...................... 5893
18.14.110DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_68)—Offset 290h....................... 5894
18.14.111DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_69)—Offset 294h....................... 5894
18.14.112DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_70)—Offset 298h....................... 5895

150 334818
 18.14.113DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_71)—Offset 29Ch .......................5895
18.14.114DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_72)—Offset 2A0h .......................5896
18.14.115DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_73)—Offset 2A4h .......................5897
18.14.116DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_74)—Offset 2A8h .......................5897
18.14.117DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_75)—Offset 2ACh .......................5898
18.14.118DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_76)—Offset 2B0h .......................5898
18.14.119DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_77)—Offset 2B4h .......................5899
18.14.120DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_78)—Offset 2B8h .......................5900
18.14.121DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_79)—Offset 2BCh .......................5900
18.14.122DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_80)—Offset 2C0h .......................5901
18.14.123DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_81)—Offset 2C4h .......................5901
18.14.124DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_82)—Offset 2C8h .......................5902
18.14.125DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_83)—Offset 2CCh .......................5903
18.14.126DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_84)—Offset 2D0h .......................5903
18.14.127DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_85)—Offset 2D4h .......................5904
18.14.128DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_86)—Offset 2D8h .......................5904
18.14.129DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_87)—Offset 2DCh.......................5905
18.14.130DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_88)—Offset 2E0h .......................5906
18.14.131DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_89)—Offset 2E4h .......................5906
18.14.132DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_90)—Offset 2E8h .......................5907
18.14.133DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_91)—Offset 2ECh .......................5907
18.14.134DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_92)—Offset 2F0h .......................5908
18.14.135DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_93)—Offset 2F4h .......................5909
18.14.136DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_94)—Offset 2F8h .......................5909
18.14.137DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_95)—Offset 2FCh .......................5910
18.14.138DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_96)—Offset 300h .......................5910
18.14.139DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_97)—Offset 304h .......................5911
18.14.140DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_98)—Offset 308h .......................5912

334818 151
 18.14.141DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_99)—Offset 30Ch ...................... 5912
18.14.142DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_100)—Offset 310h ..................... 5913
18.14.143DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_101)—Offset 314h ..................... 5914
18.14.144DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_102)—Offset 318h ..................... 5914
18.14.145DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_103)—Offset 31Ch..................... 5915
18.14.146DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_104)—Offset 320h ..................... 5916
18.14.147DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_105)—Offset 324h ..................... 5916
18.14.148DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_106)—Offset 328h ..................... 5917
18.14.149DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_107)—Offset 32Ch..................... 5918
18.14.150DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_108)—Offset 330h ..................... 5918
18.14.151DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_109)—Offset 334h ..................... 5919
18.14.152DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_110)—Offset 338h ..................... 5920
18.14.153DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_111)—Offset 33Ch..................... 5920
18.14.154DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_112)—Offset 340h ..................... 5921
18.14.155DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_113)—Offset 344h ..................... 5922
18.14.156DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_114)—Offset 348h ..................... 5922
18.14.157DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_115)—Offset 34Ch..................... 5923
18.14.158DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_116)—Offset 350h ..................... 5924
18.14.159DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_117)—Offset 354h ..................... 5924
18.14.160DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_118)—Offset 358h ..................... 5925
18.14.161DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_119)—Offset 35Ch..................... 5926
18.14.162DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_120)—Offset 360h ..................... 5926
18.14.163DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_121)—Offset 364h ..................... 5927
18.14.164DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_122)—Offset 368h ..................... 5928
18.14.165DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_123)—Offset 36Ch..................... 5928
18.14.166DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_124)—Offset 370h ..................... 5929
18.14.167DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_125)—Offset 374h ..................... 5930
18.14.168DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_126)—Offset 378h ..................... 5930

152 334818
 18.14.169DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_127)—Offset 37Ch .....................5931
18.14.170DEBUG_RESPONSE_HEADER_STACK_REG
(DEBUG_RESPONSE_HEADER_STACK_REG_0)—Offset 380h .....................5932
18.14.171DEBUG_RESPONSE_HEADER_STACK_REG
(DEBUG_RESPONSE_HEADER_STACK_REG_1)—Offset 384h .....................5932
18.14.172DEBUG_RESPONSE_HEADER_STACK_REG
(DEBUG_RESPONSE_HEADER_STACK_REG_2)—Offset 388h .....................5933
18.15 Registers Summary ........................................................................................5935
18.15.1DCFG (DCFG)—Offset C700h.................................................................5938
18.15.2DCTL (DCTL)—Offset C704h .................................................................5939
18.15.3DEVTEN (DEVTEN)—Offset C708h..........................................................5940
18.15.4DSTS (DSTS)—Offset C70Ch.................................................................5941
18.15.5DGCMDPAR (DGCMDPAR)—Offset C710h ................................................5942
18.15.6DGCMD (DGCMD)—Offset C714h ...........................................................5943
18.15.7DALEPENA (DALEPENA)—Offset C720h ...................................................5943
18.15.8DEPCMDPAR2_0 (DEPCMDPAR2_0)—Offset C800h ...................................5944
18.15.9DEPCMDPAR1_0 (DEPCMDPAR1_0)—Offset C804h ...................................5944
18.15.10DEPCMDPAR0_0 (DEPCMDPAR0_0)—Offset C808h .................................5945
18.15.11DEPCMD_0 (DEPCMD_0)—Offset C80Ch................................................5945
18.15.12DEPCMDPAR2_1 (DEPCMDPAR2_1)—Offset C810h .................................5946
18.15.13DEPCMDPAR1_1 (DEPCMDPAR1_1)—Offset C814h .................................5947
18.15.14DEPCMDPAR0_1 (DEPCMDPAR0_1)—Offset C818h .................................5947
18.15.15DEPCMD_1 (DEPCMD_1)—Offset C81Ch................................................5948
18.15.16DEPCMDPAR2_2 (DEPCMDPAR2_2)—Offset C820h .................................5948
18.15.17DEPCMDPAR1_2 (DEPCMDPAR1_2)—Offset C824h .................................5949
18.15.18DEPCMDPAR0_2 (DEPCMDPAR0_2)—Offset C828h .................................5949
18.15.19DEPCMD_2 (DEPCMD_2)—Offset C82Ch................................................5950
18.15.20DEPCMDPAR2_3 (DEPCMDPAR2_3)—Offset C830h .................................5951
18.15.21DEPCMDPAR1_3 (DEPCMDPAR1_3)—Offset C834h .................................5951
18.15.22DEPCMDPAR0_3 (DEPCMDPAR0_3)—Offset C838h .................................5952
18.15.23DEPCMD_3 (DEPCMD_3)—Offset C83Ch................................................5952
18.15.24DEPCMDPAR2_4 (DEPCMDPAR2_4)—Offset C840h .................................5953
18.15.25DEPCMDPAR1_4 (DEPCMDPAR1_4)—Offset C844h .................................5953
18.15.26DEPCMDPAR0_4 (DEPCMDPAR0_4)—Offset C848h .................................5954
18.15.27DEPCMD_4 (DEPCMD_4)—Offset C84Ch................................................5954
18.15.28DEPCMDPAR2_5 (DEPCMDPAR2_5)—Offset C850h .................................5955
18.15.29DEPCMDPAR1_5 (DEPCMDPAR1_5)—Offset C854h .................................5956
18.15.30DEPCMDPAR0_5 (DEPCMDPAR0_5)—Offset C858h .................................5956
18.15.31DEPCMD_5 (DEPCMD_5)—Offset C85Ch................................................5957
18.15.32DEPCMDPAR2_6 (DEPCMDPAR2_6)—Offset C860h .................................5957
18.15.33DEPCMDPAR1_6 (DEPCMDPAR1_6)—Offset C864h .................................5958
18.15.34DEPCMDPAR0_6 (DEPCMDPAR0_6)—Offset C868h .................................5958
18.15.35DEPCMD_6 (DEPCMD_6)—Offset C86Ch................................................5959
18.15.36DEPCMDPAR2_7 (DEPCMDPAR2_7)—Offset C870h .................................5960
18.15.37DEPCMDPAR1_7 (DEPCMDPAR1_7)—Offset C874h .................................5960
18.15.38DEPCMDPAR0_7 (DEPCMDPAR0_7)—Offset C878h .................................5961
18.15.39DEPCMD_7 (DEPCMD_7)—Offset C87Ch................................................5961
18.15.40DEPCMDPAR2_8 (DEPCMDPAR2_8)—Offset C880h .................................5962
18.15.41DEPCMDPAR1_8 (DEPCMDPAR1_8)—Offset C884h .................................5962
18.15.42DEPCMDPAR0_8 (DEPCMDPAR0_8)—Offset C888h .................................5963
18.15.43DEPCMD_8 (DEPCMD_8)—Offset C88Ch................................................5963
18.15.44DEPCMDPAR2_9 (DEPCMDPAR2_9)—Offset C890h .................................5964
18.15.45DEPCMDPAR1_9 (DEPCMDPAR1_9)—Offset C894h .................................5965
18.15.46DEPCMDPAR0_9 (DEPCMDPAR0_9)—Offset C898h .................................5965

334818 153
 18.15.47DEPCMD_9 (DEPCMD_9)—Offset C89Ch ............................................... 5966
18.15.48DEPCMDPAR2_10 (DEPCMDPAR2_10)—Offset C8A0h ............................. 5966
18.15.49DEPCMDPAR1_10 (DEPCMDPAR1_10)—Offset C8A4h ............................. 5967
18.15.50DEPCMDPAR0_10 (DEPCMDPAR0_10)—Offset C8A8h ............................. 5967
18.15.51DEPCMD_10 (DEPCMD_10)—Offset C8ACh ........................................... 5968
18.15.52DEPCMDPAR2_11 (DEPCMDPAR2_11)—Offset C8B0h ............................. 5969
18.15.53DEPCMDPAR1_11 (DEPCMDPAR1_11)—Offset C8B4h ............................. 5969
18.15.54DEPCMDPAR0_11 (DEPCMDPAR0_11)—Offset C8B8h ............................. 5970
18.15.55DEPCMD_11 (DEPCMD_11)—Offset C8BCh ........................................... 5970
18.15.56DEPCMDPAR2_12 (DEPCMDPAR2_12)—Offset C8C0h ............................. 5971
18.15.57DEPCMDPAR1_12 (DEPCMDPAR1_12)—Offset C8C4h ............................. 5971
18.15.58DEPCMDPAR0_12 (DEPCMDPAR0_12)—Offset C8C8h ............................. 5972
18.15.59DEPCMD_12 (DEPCMD_12)—Offset C8CCh ........................................... 5972
18.15.60DEPCMDPAR2_13 (DEPCMDPAR2_13)—Offset C8D0h ............................. 5973
18.15.61DEPCMDPAR1_13 (DEPCMDPAR1_13)—Offset C8D4h ............................. 5974
18.15.62DEPCMDPAR0_13 (DEPCMDPAR0_13)—Offset C8D8h ............................. 5974
18.15.63DEPCMD_13 (DEPCMD_13)—Offset C8DCh ........................................... 5975
18.15.64DEPCMDPAR2_14 (DEPCMDPAR2_14)—Offset C8E0h ............................. 5975
18.15.65DEPCMDPAR1_14 (DEPCMDPAR1_14)—Offset C8E4h ............................. 5976
18.15.66DEPCMDPAR0_14 (DEPCMDPAR0_14)—Offset C8E8h ............................. 5976
18.15.67DEPCMD_14 (DEPCMD_14)—Offset C8ECh............................................ 5977
18.15.68DEPCMDPAR2_15 (DEPCMDPAR2_15)—Offset C8F0h.............................. 5978
18.15.69DEPCMDPAR1_15 (DEPCMDPAR1_15)—Offset C8F4h.............................. 5978
18.15.70DEPCMDPAR0_15 (DEPCMDPAR0_15)—Offset C8F8h.............................. 5979
18.15.71DEPCMD_15 (DEPCMD_15)—Offset C8FCh............................................ 5979
18.15.72DEPCMDPAR2_16 (DEPCMDPAR2_16)—Offset C900h ............................. 5980
18.15.73DEPCMDPAR1_16 (DEPCMDPAR1_16)—Offset C904h ............................. 5980
18.15.74DEPCMDPAR0_16 (DEPCMDPAR0_16)—Offset C908h ............................. 5981
18.15.75DEPCMD_16 (DEPCMD_16)—Offset C90Ch............................................ 5981
18.15.76DEPCMDPAR2_17 (DEPCMDPAR2_17)—Offset C910h ............................. 5982
18.15.77DEPCMDPAR1_17 (DEPCMDPAR1_17)—Offset C914h ............................. 5983
18.15.78DEPCMDPAR0_17 (DEPCMDPAR0_17)—Offset C918h ............................. 5983
18.15.79DEPCMD_17 (DEPCMD_17)—Offset C91Ch............................................ 5984
18.15.80DEPCMDPAR2_18 (DEPCMDPAR2_18)—Offset C920h ............................. 5984
18.15.81DEPCMDPAR1_18 (DEPCMDPAR1_18)—Offset C924h ............................. 5985
18.15.82DEPCMDPAR0_18 (DEPCMDPAR0_18)—Offset C928h ............................. 5985
18.15.83DEPCMD_18 (DEPCMD_18)—Offset C92Ch............................................ 5986
18.15.84DEPCMDPAR2_19 (DEPCMDPAR2_19)—Offset C930h ............................. 5987
18.15.85DEPCMDPAR1_19 (DEPCMDPAR1_19)—Offset C934h ............................. 5987
18.15.86DEPCMDPAR0_19 (DEPCMDPAR0_19)—Offset C938h ............................. 5988
18.15.87DEPCMD_19 (DEPCMD_19)—Offset C93Ch............................................ 5988
18.15.88DEPCMDPAR2_20 (DEPCMDPAR2_20)—Offset C940h ............................. 5989
18.15.89DEPCMDPAR1_20 (DEPCMDPAR1_20)—Offset C944h ............................. 5989
18.15.90DEPCMDPAR0_20 (DEPCMDPAR0_20)—Offset C948h ............................. 5990
18.15.91DEPCMD_20 (DEPCMD_20)—Offset C94Ch............................................ 5990
18.15.92DEPCMDPAR2_21 (DEPCMDPAR2_21)—Offset C950h ............................. 5991
18.15.93DEPCMDPAR1_21 (DEPCMDPAR1_21)—Offset C954h ............................. 5992
18.15.94DEPCMDPAR0_21 (DEPCMDPAR0_21)—Offset C958h ............................. 5992
18.15.95DEPCMD_21 (DEPCMD_21)—Offset C95Ch............................................ 5993
18.15.96DEPCMDPAR2_22 (DEPCMDPAR2_22)—Offset C960h ............................. 5993
18.15.97DEPCMDPAR1_22 (DEPCMDPAR1_22)—Offset C964h ............................. 5994
18.15.98DEPCMDPAR0_22 (DEPCMDPAR0_22)—Offset C968h ............................. 5994
18.15.99DEPCMD_22 (DEPCMD_22)—Offset C96Ch............................................ 5995
18.15.100DEPCMDPAR2_23 (DEPCMDPAR2_23)—Offset C970h............................ 5996
18.15.101DEPCMDPAR1_23 (DEPCMDPAR1_23)—Offset C974h............................ 5996

154 334818
 18.15.102DEPCMDPAR0_23 (DEPCMDPAR0_23)—Offset C978h ............................5997
18.15.103DEPCMD_23 (DEPCMD_23)—Offset C97Ch ..........................................5997
18.15.104DEPCMDPAR2_24 (DEPCMDPAR2_24)—Offset C980h ............................5998
18.15.105DEPCMDPAR1_24 (DEPCMDPAR1_24)—Offset C984h ............................5998
18.15.106DEPCMDPAR0_24 (DEPCMDPAR0_24)—Offset C988h ............................5999
18.15.107DEPCMD_24 (DEPCMD_24)—Offset C98Ch ..........................................5999
18.15.108DEPCMDPAR2_25 (DEPCMDPAR2_25)—Offset C990h ............................6000
18.15.109DEPCMDPAR1_25 (DEPCMDPAR1_25)—Offset C994h ............................6001
18.15.110DEPCMDPAR0_25 (DEPCMDPAR0_25)—Offset C998h ............................6001
18.15.111DEPCMD_25 (DEPCMD_25)—Offset C99Ch ..........................................6002
18.15.112DEPCMDPAR2_26 (DEPCMDPAR2_26)—Offset C9A0h ............................6002
18.15.113DEPCMDPAR1_26 (DEPCMDPAR1_26)—Offset C9A4h ............................6003
18.15.114DEPCMDPAR0_26 (DEPCMDPAR0_26)—Offset C9A8h ............................6003
18.15.115DEPCMD_26 (DEPCMD_26)—Offset C9ACh ..........................................6004
18.15.116DEPCMDPAR2_27 (DEPCMDPAR2_27)—Offset C9B0h ............................6005
18.15.117DEPCMDPAR1_27 (DEPCMDPAR1_27)—Offset C9B4h ............................6005
18.15.118DEPCMDPAR0_27 (DEPCMDPAR0_27)—Offset C9B8h ............................6006
18.15.119DEPCMD_27 (DEPCMD_27)—Offset C9BCh ..........................................6006
18.15.120DEPCMDPAR2_28 (DEPCMDPAR2_28)—Offset C9C0h ............................6007
18.15.121DEPCMDPAR1_28 (DEPCMDPAR1_28)—Offset C9C4h ............................6007
18.15.122DEPCMDPAR0_28 (DEPCMDPAR0_28)—Offset C9C8h ............................6008
18.15.123DEPCMD_28 (DEPCMD_28)—Offset C9CCh ..........................................6008
18.15.124DEPCMDPAR2_29 (DEPCMDPAR2_29)—Offset C9D0h ............................6009
18.15.125DEPCMDPAR1_29 (DEPCMDPAR1_29)—Offset C9D4h ............................6010
18.15.126DEPCMDPAR0_29 (DEPCMDPAR0_29)—Offset C9D8h ............................6010
18.15.127DEPCMD_29 (DEPCMD_29)—Offset C9DCh ..........................................6011
18.15.128DEPCMDPAR2_30 (DEPCMDPAR2_30)—Offset C9E0h ............................6011
18.15.129DEPCMDPAR1_30 (DEPCMDPAR1_30)—Offset C9E4h ............................6012
18.15.130DEPCMDPAR0_30 (DEPCMDPAR0_30)—Offset C9E8h ............................6012
18.15.131DEPCMD_30 (DEPCMD_30)—Offset C9ECh ..........................................6013
18.15.132DEPCMDPAR2_31 (DEPCMDPAR2_31)—Offset C9F0h ............................6014
18.15.133DEPCMDPAR1_31 (DEPCMDPAR1_31)—Offset C9F4h ............................6014
18.15.134DEPCMDPAR0_31 (DEPCMDPAR0_31)—Offset C9F8h ............................6015
18.15.135DEPCMD_31 (DEPCMD_31)—Offset C9FCh...........................................6015
18.16 Registers Summary ........................................................................................6017
18.16.1GSBUSCFG0 (GSBUSCFG0)—Offset C100h..............................................6018
18.16.2GSBUSCFG1 (GSBUSCFG1)—Offset C104h..............................................6019
18.16.3GTXTHRCFG (GTXTHRCFG)—Offset C108h ..............................................6020
18.16.4GRXTHRCFG (GRXTHRCFG)—Offset C10Ch .............................................6021
18.16.5GCTL (GCTL)—Offset C110h .................................................................6022
18.16.6GPMSTS (GPMSTS)—Offset C114h .........................................................6023
18.16.7GSTS (GSTS)—Offset C118h .................................................................6024
18.16.8GUCTL1 (GUCTL1)—Offset C11Ch..........................................................6025
18.16.9GSNPSID (GSNPSID)—Offset C120h ......................................................6026
18.16.10GGPIO (GGPIO)—Offset C124h ............................................................6026
18.16.11GUID (GUID)—Offset C128h................................................................6027
18.16.12GUCTL (GUCTL)—Offset C12Ch ............................................................6027
18.16.13GBUSERRADDRLO (GBUSERRADDRLO)—Offset C130h ............................6028
18.16.14GBUSERRADDRHI (GBUSERRADDRHI)—Offset C134h .............................6029
18.16.15GPRTBIMAPLO (GPRTBIMAPLO)—Offset C138h.......................................6029
18.16.16GPRTBIMAPHI (GPRTBIMAPHI)—Offset C13Ch .......................................6030
18.16.17GHWPARAMS0 (GHWPARAMS0)—Offset C140h ......................................6031
18.16.18GHWPARAMS1 (GHWPARAMS1)—Offset C144h ......................................6032
18.16.19GHWPARAMS2 (GHWPARAMS2)—Offset C148h ......................................6033
18.16.20GHWPARAMS3 (GHWPARAMS3)—Offset C14Ch ......................................6034

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 18.16.21GHWPARAMS4 (GHWPARAMS4)—Offset C150h...................................... 6035
18.16.22GHWPARAMS5 (GHWPARAMS5)—Offset C154h...................................... 6036
18.16.23GHWPARAMS6 (GHWPARAMS6)—Offset C158h...................................... 6037
18.16.24GHWPARAMS7 (GHWPARAMS7)—Offset C15Ch ..................................... 6038
18.16.25GDBGFIFOSPACE (GDBGFIFOSPACE)—Offset C160h .............................. 6039
18.16.26GDBGLTSSM (GDBGLTSSM)—Offset C164h ........................................... 6039
18.16.27GDBGLNMCC (GDBGLNMCC)—Offset C168h .......................................... 6041
18.16.28GDBGBMU (GDBGBMU)—Offset C16Ch ................................................. 6041
18.16.29GDBGLSPMUX_DEV (GDBGLSPMUX_DEV)—Offset C170h ........................ 6042
18.16.30GDBGLSP (GDBGLSP)—Offset C174h ................................................... 6042
18.16.31GDBGEPINFO0 (GDBGEPINFO0)—Offset C178h ..................................... 6043
18.16.32GDBGEPINFO1 (GDBGEPINFO1)—Offset C17Ch ..................................... 6043
18.16.33GPRTBIMAP_HSLO (GPRTBIMAP_HSLO)—Offset C180h........................... 6044
18.16.34GPRTBIMAP_HSHI (GPRTBIMAP_HSHI)—Offset C184h............................ 6045
18.16.35GPRTBIMAP_FSLO (GPRTBIMAP_FSLO)—Offset C188h............................ 6045
18.16.36GPRTBIMAP_FSHI (GPRTBIMAP_FSHI)—Offset C18Ch ............................ 6046
18.16.37GUSB2PHYCFG_0 (GUSB2PHYCFG_0)—Offset C200h.............................. 6047
18.16.38GUSB2I2CCTL_0 (GUSB2I2CCTL_0)—Offset C240h................................ 6048
18.16.39GUSB2PHYACC_ULPI_0 (GUSB2PHYACC_ULPI_0)—Offset C280h ............. 6049
18.16.40GUSB3PIPECTL_0 (GUSB3PIPECTL_0)—Offset C2C0h ............................. 6050
18.16.41GTXFIFOSIZ0_0 (GTXFIFOSIZ0_0)—Offset C300h ................................. 6051
18.16.42GTXFIFOSIZ1_0 (GTXFIFOSIZ1_0)—Offset C304h ................................. 6052
18.16.43GTXFIFOSIZ2_0 (GTXFIFOSIZ2_0)—Offset C308h ................................. 6052
18.16.44GTXFIFOSIZ3_0 (GTXFIFOSIZ3_0)—Offset C30Ch ................................. 6053
18.16.45GTXFIFOSIZ4_0 (GTXFIFOSIZ4_0)—Offset C310h ................................. 6054
18.16.46GTXFIFOSIZ5_0 (GTXFIFOSIZ5_0)—Offset C314h ................................. 6054
18.16.47GTXFIFOSIZ6_0 (GTXFIFOSIZ6_0)—Offset C318h ................................. 6055
18.16.48GTXFIFOSIZ7_0 (GTXFIFOSIZ7_0)—Offset C31Ch ................................. 6055
18.16.49GTXFIFOSIZ8_0 (GTXFIFOSIZ8_0)—Offset C320h ................................. 6056
18.16.50GTXFIFOSIZ9_0 (GTXFIFOSIZ9_0)—Offset C324h ................................. 6056
18.16.51GTXFIFOSIZ10_0 (GTXFIFOSIZ10_0)—Offset C328h .............................. 6057
18.16.52GTXFIFOSIZ11_0 (GTXFIFOSIZ11_0)—Offset C32Ch.............................. 6057
18.16.53GTXFIFOSIZ12_0 (GTXFIFOSIZ12_0)—Offset C330h .............................. 6058
18.16.54GTXFIFOSIZ13_0 (GTXFIFOSIZ13_0)—Offset C334h .............................. 6058
18.16.55GTXFIFOSIZ14_0 (GTXFIFOSIZ14_0)—Offset C338h .............................. 6059
18.16.56GTXFIFOSIZ15_0 (GTXFIFOSIZ15_0)—Offset C33Ch.............................. 6059
18.16.57GRXFIFOSIZ0_0 (GRXFIFOSIZ0_0)—Offset C380h ................................. 6060
18.16.58GEVNTADRLO_0 (GEVNTADRLO_0)—Offset C400h ................................. 6060
18.16.59GEVNTADRHI_0 (GEVNTADRHI_0)—Offset C404h.................................. 6061
18.16.60GEVNTSIZ_0 (GEVNTSIZ_0)—Offset C408h .......................................... 6061
18.16.61GEVNTCOUNT_0 (GEVNTCOUNT_0)—Offset C40Ch ................................ 6062
18.16.62GHWPARAMS8 (GHWPARAMS8)—Offset C600h...................................... 6063
18.16.63GTXFIFOPRIDEV (GTXFIFOPRIDEV)—Offset C610h................................. 6063
18.16.64GFLADJ (GFLADJ)—Offset C630h ......................................................... 6064
18.17 Registers Summary........................................................................................ 6067
18.17.1APBFC_U3PMU_CFG0 (APBFC_U3PMU_CFG0)—Offset 10F808h ................. 6067
18.17.2APBFC_U3PMU_CFG1 (APBFC_U3PMU_CFG1)—Offset 10F80Ch ................. 6068
18.17.3APBFC_U3PMU_CFG2 (APBFC_U3PMU_CFG2)—Offset 10F810h ................. 6069
18.17.4APBFC_U3PMU_CFG3 (APBFC_U3PMU_CFG3)—Offset 10F814h ................. 6070
18.17.5APBFC_U3PMU_CFG4 (APBFC_U3PMU_CFG4)—Offset 10F818h ................. 6071
18.17.6APBFC_U3PMU_CFG5 (APBFC_U3PMU_CFG5)—Offset 10F81Ch ................. 6072
18.17.7APBFC_U3PMU_CFG6 (APBFC_U3PMU_CFG6)—Offset 10F820h ................. 6073
18.17.8APBFC_D0I3C (APBFC_D0I3C)—Offset 10F830h...................................... 6074
18.18 Registers Summary........................................................................................ 6077
18.18.1 (GEN_REGRW1)—Offset B0h ............................................................... 6077

156 334818
 18.18.2(GEN_REGRW2)—Offset B4h.................................................................6077
18.18.3(GEN_REGRW3)—Offset B8h.................................................................6078
18.18.4(GEN_REGRW4)—Offset BCh ................................................................6078
18.18.5 (GEN_INPUT_REGRW)—Offset C0h .......................................................6079
18.19 Registers Summary ........................................................................................6081
18.19.1 (GEN_REGRW1)—Offset B0h................................................................6081
18.19.2(GEN_REGRW2)—Offset B4h.................................................................6081
18.19.3(GEN_REGRW3)—Offset B8h.................................................................6082
18.19.4(GEN_REGRW4)—Offset BCh ................................................................6082
18.19.5 (GEN_INPUT_REGRW)—Offset C0h .......................................................6083
18.20 Registers Summary ........................................................................................6085
18.20.1 (DEVVENDID)—Offset 0h.....................................................................6085
18.20.2(STATUSCOMMAND)—Offset 4h.............................................................6086
18.20.3(REVCLASSCODE)—Offset 8h ................................................................6087
18.20.4(CLLATHEADERBIST)—Offset Ch............................................................6087
18.20.5(BAR)—Offset 10h ...............................................................................6088
18.20.6(BAR1)—Offset 18h .............................................................................6089
18.20.7(SUBSYSTEMID)—Offset 2Ch ................................................................6089
18.20.8(EXPANSION_ROM_BASEADDR)—Offset 30h ...........................................6090
18.20.9(CAPABILITYPTR)—Offset 34h ...............................................................6091
18.20.10(INTERRUPTREG)—Offset 3Ch .............................................................6091
18.20.11(POWERCAPID)—Offset 80h ................................................................6092
18.20.12(PMECTRLSTATUS)—Offset 84h ...........................................................6092
18.20.13(PCIDEVIDLE_CAP_RECORD)—Offset 90h .............................................6093
18.20.14(DEVID_VEND_SPECIFIC_REG)—Offset 94h ..........................................6094
18.20.15(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h...............................6094
18.20.16(DEVICE_IDLE_POINTER_REG)—Offset 9Ch...........................................6095
18.20.17(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ...................................6096
18.21 Registers Summary ........................................................................................6097
18.21.1 (DEVVENDID)—Offset 0h.....................................................................6097
18.21.2(STATUSCOMMAND)—Offset 4h.............................................................6098
18.21.3(REVCLASSCODE)—Offset 8h ................................................................6099
18.21.4(CLLATHEADERBIST)—Offset Ch............................................................6099
18.21.5(BAR)—Offset 10h ...............................................................................6100
18.21.6(BAR1)—Offset 18h .............................................................................6101
18.21.7(SUBSYSTEMID)—Offset 2Ch ................................................................6101
18.21.8(EXPANSION_ROM_BASEADDR)—Offset 30h ...........................................6102
18.21.9(CAPABILITYPTR)—Offset 34h ...............................................................6103
18.21.10(INTERRUPTREG)—Offset 3Ch .............................................................6103
18.21.11(POWERCAPID)—Offset 80h ................................................................6104
18.21.12(PMECTRLSTATUS)—Offset 84h ...........................................................6104
18.21.13(PCIDEVIDLE_CAP_RECORD)—Offset 90h .............................................6105
18.21.14(DEVID_VEND_SPECIFIC_REG)—Offset 94h ..........................................6106
18.21.15(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h...............................6106
18.21.16(DEVICE_IDLE_POINTER_REG)—Offset 9Ch...........................................6107
18.21.17(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ...................................6108
19 Storage ................................................................................................................6109
19.1 eMMC Registers Summary ...............................................................................6109
19.1.1 (SW_LTR_val)—Offset 804h.................................................................6109
19.1.2 (Auto_LTR_val)—Offset 808h ...............................................................6110
19.1.3 (Cap_byps)—Offset 810h ....................................................................6111
19.1.4 (Cap_byps_reg1)—Offset 814h ............................................................6111
19.1.5 (Cap_byps_reg2)—Offset 818h ............................................................6113
19.1.6 (reg_D0i3)—Offset 81Ch .....................................................................6114

334818 157
 19.1.7 (Tx_CMD_dly)—Offset 820h ................................................................ 6115
19.1.8 (Tx_DATA_dly_1)—Offset 824h ........................................................... 6116
19.1.9 (Tx_DATA_dly_2)—Offset 828h ........................................................... 6116
19.1.10 (Rx_CMD_Data_dly_1)—Offset 82Ch .................................................... 6117
19.1.11 (Rx_Strobe_Ctrl_Path)—Offset 830h .................................................... 6118
19.1.12 (Rx_CMD_Data_dly_2)—Offset 834h .................................................... 6119
19.1.13 (Master_Dll)—Offset 838h................................................................... 6120
19.1.14 (Auto_tuning)—Offset 840h ................................................................ 6121
19.1.15(emmc_Root_Space)—Offset 900h ........................................................ 6121
19.2 SD Card Registers Summary ........................................................................... 6122
19.2.1 (SW_LTR_val)—Offset 804h ................................................................ 6122
19.2.2 (Auto_LTR_val)—Offset 808h .............................................................. 6123
19.2.3 (Cap_byps)—Offset 810h .................................................................... 6124
19.2.4 (Cap_byps_reg1)—Offset 814h ............................................................ 6124
19.2.5 (Cap_byps_reg2)—Offset 818h ............................................................ 6126
19.2.6 (reg_D0i3)—Offset 81Ch..................................................................... 6127
19.2.7 (Tx_CMD_dly)—Offset 820h ................................................................ 6128
19.2.8 (Tx_DATA_dly_1)—Offset 824h ........................................................... 6129
19.2.9 (Tx_DATA_dly_2)—Offset 828h ........................................................... 6129
19.2.10 (Rx_CMD_Data_dly_1)—Offset 82Ch .................................................... 6130
19.2.11 (Rx_Strobe_Ctrl_Path)—Offset 830h .................................................... 6131
19.2.12 (Rx_CMD_Data_dly_2)—Offset 834h .................................................... 6132
19.2.13 (Master_Dll)—Offset 838h................................................................... 6133
19.2.14 (Auto_tuning)—Offset 840h ................................................................ 6134
19.3 SDIO Registers Summary ............................................................................... 6134
19.3.1 (SW_LTR_val)—Offset 804h ................................................................ 6135
19.3.2 (Auto_LTR_val)—Offset 808h .............................................................. 6136
19.3.3 (Cap_byps)—Offset 810h .................................................................... 6136
19.3.4 (Cap_byps_reg1)—Offset 814h ............................................................ 6137
19.3.5 (Cap_byps_reg2)—Offset 818h ............................................................ 6139
19.3.6 (reg_D0i3)—Offset 81Ch..................................................................... 6140
19.3.7 (Tx_CMD_dly)—Offset 820h ................................................................ 6141
19.3.8 (Tx_DATA_dly_1)—Offset 824h ........................................................... 6141
19.3.9 (Tx_DATA_dly_2)—Offset 828h ........................................................... 6142
19.3.10 (Rx_CMD_Data_dly_1)—Offset 82Ch .................................................... 6143
19.3.11 (Rx_Strobe_Ctrl_Path)—Offset 830h .................................................... 6144
19.3.12 (Rx_CMD_Data_dly_2)—Offset 834h .................................................... 6144
19.3.13 (Master_Dll)—Offset 838h................................................................... 6145
19.3.14 (Auto_tuning)—Offset 840h ................................................................ 6146
19.4 Registers Summary........................................................................................ 6147
19.4.1 (DEVVENDID)—Offset 0h .................................................................... 6147
19.4.2 (STATUSCOMMAND)—Offset 4h ............................................................ 6148
19.4.3 (REVCLASSCODE)—Offset 8h ............................................................... 6149
19.4.4 (CLLATHEADERBIST)—Offset Ch ........................................................... 6150
19.4.5 (BAR)—Offset 10h .............................................................................. 6150
19.4.6 (BAR_HIGH)—Offset 14h ..................................................................... 6151
19.4.7 (BAR1)—Offset 18h............................................................................. 6152
19.4.8 (BAR1_HIGH)—Offset 1Ch ................................................................... 6152
19.4.9 (SUBSYSTEMID)—Offset 2Ch................................................................ 6153
19.4.10(EXPANSION_ROM_BASEADDR)—Offset 30h .......................................... 6153
19.4.11(CAPABILITYPTR)—Offset 34h .............................................................. 6154
19.4.12(INTERRUPTREG)—Offset 3Ch .............................................................. 6154
19.4.13(POWERCAPID)—Offset 80h ................................................................. 6155
19.4.14(PMECTRLSTATUS)—Offset 84h ............................................................ 6156
19.4.15(PCIDEVIDLE_CAP_RECORD)—Offset 90h .............................................. 6157

158 334818
 19.4.16(DEVID_VEND_SPECIFIC_REG)—Offset 94h ............................................6157
19.4.17(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................6158
19.4.18(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................6158
19.4.19(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................6159
19.5 Registers Summary ........................................................................................6160
19.5.1 SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h..
6161
19.5.2 BlockSize Register (blocksize)—Offset 4h................................................6162
19.5.3 BlockCount Register (blockcount)—Offset 6h...........................................6162
19.5.4 Argument1 Register (argument1)—Offset 8h...........................................6163
19.5.5 TransferMode Register (transfermode)—Offset Ch....................................6163
19.5.6 Command Register (command)—Offset Eh..............................................6164
19.5.7 Response Register (response01)—Offset 10h ..........................................6165
19.5.8 Response Register (response2)—Offset 14h ............................................6166
19.5.9 Response Register (response3)—Offset 16h ............................................6166
19.5.10Response Register (response4)—Offset 18h ............................................6167
19.5.11Response Register (response5)—Offset 1Ah ............................................6167
19.5.12Response Register (response6)—Offset 1Ch ............................................6168
19.5.13Response Register (response7)—Offset 1Eh ............................................6168
19.5.14Buffer DataPort Register (dataport)—Offset 20h ......................................6169
19.5.15eMMC Presentstate Register (presentstate)—Offset 24h............................6169
19.5.16HostControl1 Register (hostcontrol1)—Offset 28h ....................................6171
19.5.17PowerControl Register (powercontrol)—Offset 29h ...................................6172
19.5.18BlockGapControl Register (blockgapcontrol)—Offset 2Ah...........................6173
19.5.19Wakeup Control Register (wakeupcontrol)—Offset 2Bh .............................6174
19.5.20Clock Control Register (clockcontrol)—Offset 2Ch ....................................6175
19.5.21Timeout Control Register (timeoutcontrol)—Offset 2Eh .............................6176
19.5.22Software Reset Register (softwarereset)—Offset 2Fh................................6176
19.5.23Normal Interrupt Status Register (normalintrsts)—Offset 30h....................6177
19.5.24ErrorInterruptStatus_Register (errorintrsts)—Offset 32h ...........................6178
19.5.25Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h.....6180
19.5.26Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h ..........6182
19.5.27Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h .....6183
19.5.28Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah...........6184
19.5.29Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch ................6186
19.5.30Host Control2 Register (hostcontrol2)—Offset 3Eh ...................................6187
19.5.31Capabilities Register (capabilities)—Offset 40h ........................................6188
19.5.32Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h .........6190
19.5.33Force Event REGISTER for AUTO CMD Error Status
(ForceEventforAUTOCMDErrorStatus)—Offset 50h....................................6191
19.5.34Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset
52h ...................................................................................................6192
19.5.35ADMA Error Status Register (admaerrsts)—Offset 54h ..............................6193
19.5.36ADMA System Address Register0&1 (admasysaddr01)—Offset 58h.............6194
19.5.37ADMA System Address Register1 (admasysaddr2)—Offset 5Ch ..................6194
19.5.38ADMA System Address Register1 (admasysaddr3)—Offset 5Eh ..................6195
19.5.39Boot Timeout Control Register (boottimeoutcnt)—Offset 70h .....................6195
19.5.40Slot Interrupt Status Register (slotintrsts)—Offset FCh .............................6196
19.5.41Host Controller Version Register (hostcontrollerver)—Offset FEh ................6197
19.6 Registers Summary ........................................................................................6197
19.6.1 (DEVVENDID)—Offset 0h.....................................................................6198
19.6.2 (STATUSCOMMAND)—Offset 4h.............................................................6198
19.6.3 (REVCLASSCODE)—Offset 8h ................................................................6199
19.6.4 (CLLATHEADERBIST)—Offset Ch............................................................6200
19.6.5 (BAR)—Offset 10h ...............................................................................6201

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 19.6.6 (BAR_HIGH)—Offset 14h ..................................................................... 6201
19.6.7 (BAR1)—Offset 18h............................................................................. 6202
19.6.8 (BAR1_HIGH)—Offset 1Ch ................................................................... 6202
19.6.9 (SUBSYSTEMID)—Offset 2Ch................................................................ 6203
19.6.10(EXPANSION_ROM_BASEADDR)—Offset 30h .......................................... 6204
19.6.11(CAPABILITYPTR)—Offset 34h .............................................................. 6204
19.6.12(INTERRUPTREG)—Offset 3Ch .............................................................. 6205
19.6.13(POWERCAPID)—Offset 80h ................................................................. 6205
19.6.14(PMECTRLSTATUS)—Offset 84h ............................................................ 6206
19.6.15(PCIDEVIDLE_CAP_RECORD)—Offset 90h .............................................. 6207
19.6.16(DEVID_VEND_SPECIFIC_REG)—Offset 94h ........................................... 6207
19.6.17(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 6208
19.6.18(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 6209
19.6.19(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 6209
19.7 Registers Summary........................................................................................ 6210
19.7.1 SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h .
6211
19.7.2 BlockSize Register (blocksize)—Offset 4h ............................................... 6212
19.7.3 BlockCount Register (blockcount)—Offset 6h .......................................... 6213
19.7.4 Argument1 Register (argument1)—Offset 8h .......................................... 6213
19.7.5 TransferMode Register (transfermode)—Offset Ch ................................... 6214
19.7.6 Command Register (command)—Offset Eh ............................................. 6214
19.7.7 Response Register (response01)—Offset 10h.......................................... 6215
19.7.8 Response Register (response2)—Offset 14h ........................................... 6216
19.7.9 Response Register (response3)—Offset 16h ........................................... 6216
19.7.10Response Register (response4)—Offset 18h ........................................... 6217
19.7.11Response Register (response5)—Offset 1Ah ........................................... 6217
19.7.12Response Register (response6)—Offset 1Ch ........................................... 6218
19.7.13Response Register (response7)—Offset 1Eh ........................................... 6218
19.7.14Buffer DataPort Register (dataport)—Offset 20h...................................... 6219
19.7.15SDIO PresentState Register (presentstate)—Offset 24h............................ 6220
19.7.16HostControl1 Register (hostcontrol1)—Offset 28h.................................... 6222
19.7.17PowerControl Register (powercontrol)—Offset 29h .................................. 6223
19.7.18BlockGapControl Register (blockgapcontrol)—Offset 2Ah .......................... 6223
19.7.19Wakeup Control Register (wakeupcontrol)—Offset 2Bh............................. 6224
19.7.20Clock Control Register (clockcontrol)—Offset 2Ch .................................... 6225
19.7.21Timeout Control Register (timeoutcontrol)—Offset 2Eh ............................ 6226
19.7.22Software Reset Register (softwarereset)—Offset 2Fh ............................... 6227
19.7.23Normal Interrupt Status Register (normalintrsts)—Offset 30h ................... 6227
19.7.24ErrorInterruptStatus_Register (errorintrsts)—Offset 32h .......................... 6229
19.7.25Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h .... 6230
19.7.26Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h .......... 6232
19.7.27Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h .... 6233
19.7.28Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah .......... 6235
19.7.29Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch ................ 6236
19.7.30Host Control2 Register (hostcontrol2)—Offset 3Eh................................... 6237
19.7.31Capabilities Register (capabilities)—Offset 40h........................................ 6238
19.7.32Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h ........ 6241
19.7.33Force Event REGISTER for AUTO CMD Error Status
(ForceEventforAUTOCMDErrorStatus)—Offset 50h ................................... 6241
19.7.34Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset
52h................................................................................................... 6242
19.7.35ADMA Error Status Register (admaerrsts)—Offset 54h ............................. 6243
19.7.36ADMA System Address Register0&1 (admasysaddr01)—Offset 58h ............ 6244
19.7.37ADMA System Address Register1 (admasysaddr2)—Offset 5Ch ................. 6245

160 334818
 19.7.38ADMA System Address Register1 (admasysaddr3)—Offset 5Eh ..................6245
19.7.39Boot Timeout Control Register (boottimeoutcnt)—Offset 70h .....................6246
19.7.40Slot Interrupt Status Register (slotintrsts)—Offset FCh .............................6246
19.7.41Host Controller Version Register (hostcontrollerver)—Offset FEh ................6247
19.8 Registers Summary ........................................................................................6248
19.8.1 (DEVVENDID)—Offset 0h.....................................................................6248
19.8.2 (STATUSCOMMAND)—Offset 4h.............................................................6249
19.8.3 (REVCLASSCODE)—Offset 8h ................................................................6250
19.8.4 (CLLATHEADERBIST)—Offset Ch............................................................6250
19.8.5 (BAR)—Offset 10h ...............................................................................6251
19.8.6 (BAR_HIGH)—Offset 14h ......................................................................6252
19.8.7 (BAR1)—Offset 18h .............................................................................6252
19.8.8 (BAR1_HIGH)—Offset 1Ch ....................................................................6253
19.8.9 (SUBSYSTEMID)—Offset 2Ch ................................................................6253
19.8.10(EXPANSION_ROM_BASEADDR)—Offset 30h ...........................................6254
19.8.11(CAPABILITYPTR)—Offset 34h ...............................................................6255
19.8.12(INTERRUPTREG)—Offset 3Ch ...............................................................6255
19.8.13(POWERCAPID)—Offset 80h..................................................................6256
19.8.14(PMECTRLSTATUS)—Offset 84h .............................................................6256
19.8.15(PCIDEVIDLE_CAP_RECORD)—Offset 90h ...............................................6257
19.8.16(DEVID_VEND_SPECIFIC_REG)—Offset 94h ............................................6258
19.8.17(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................6258
19.8.18(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................6259
19.8.19(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................6260
19.9 Registers Summary ........................................................................................6261
19.9.1 SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h..
6262
19.9.2 BlockSize Register (blocksize)—Offset 4h................................................6262
19.9.3 BlockCount Register (blockcount)—Offset 6h...........................................6263
19.9.4 Argument1 Register (argument1)—Offset 8h...........................................6263
19.9.5 TransferMode Register (transfermode)—Offset Ch....................................6264
19.9.6 Command Register (command)—Offset Eh..............................................6265
19.9.7 Response Register (response01)—Offset 10h ..........................................6266
19.9.8 Response Register (response2)—Offset 14h ............................................6266
19.9.9 Response Register (response3)—Offset 16h ............................................6267
19.9.10Response Register (response4)—Offset 18h ............................................6267
19.9.11Response Register (response5)—Offset 1Ah ............................................6268
19.9.12Response Register (response6)—Offset 1Ch ............................................6268
19.9.13Response Register (response7)—Offset 1Eh ............................................6269
19.9.14Buffer DataPort Register (dataport)—Offset 20h ......................................6269
19.9.15SD Card PresentState Register (presentstate)—Offset 24h ........................6270
19.9.16HostControl1 Register (hostcontrol1)—Offset 28h ....................................6272
19.9.17PowerControl Register (powercontrol)—Offset 29h ...................................6273
19.9.18BlockGapControl Register (blockgapcontrol)—Offset 2Ah...........................6274
19.9.19Wakeup Control Register (wakeupcontrol)—Offset 2Bh .............................6275
19.9.20Clock Control Register (clockcontrol)—Offset 2Ch ....................................6276
19.9.21Timeout Control Register (timeoutcontrol)—Offset 2Eh .............................6276
19.9.22Software Reset Register (softwarereset)—Offset 2Fh................................6277
19.9.23Normal Interrupt Status Register (normalintrsts)—Offset 30h....................6278
19.9.24ErrorInterruptStatus_Register (errorintrsts)—Offset 32h ...........................6279
19.9.25Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h.....6281
19.9.26Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h ..........6282
19.9.27Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h .....6284
19.9.28Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah...........6285
19.9.29Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch ................6286

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 19.9.30Host Control2 Register (hostcontrol2)—Offset 3Eh................................... 6287
19.9.31Capabilities Register (capabilities)—Offset 40h........................................ 6289
19.9.32Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h ........ 6291
19.9.33Force Event REGISTER for AUTO CMD Error Status
(ForceEventforAUTOCMDErrorStatus)—Offset 50h ................................... 6292
19.9.34Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset
52h................................................................................................... 6293
19.9.35ADMA Error Status Register (admaerrsts)—Offset 54h ............................. 6294
19.9.36ADMA System Address Register0&1 (admasysaddr01)—Offset 58h ............ 6294
19.9.37ADMA System Address Register1 (admasysaddr2)—Offset 5Ch ................. 6295
19.9.38ADMA System Address Register1 (admasysaddr3)—Offset 5Eh ................. 6296
19.9.39Boot Timeout Control Register (boottimeoutcnt)—Offset 70h .................... 6296
19.9.40Slot Interrupt Status Register (slotintrsts)—Offset FCh............................. 6297
19.9.41Host Controller Version Register (hostcontrollerver)—Offset FEh................ 6297
19.10 eMMC, SD Card & SDIO Idle Clock Gating Register ............................................. 6298
19.11 eMMC Registers Summary .............................................................................. 6301
19.11.1 (SW_LTR_val)—Offset 804h ................................................................ 6301
19.11.2 (Auto_LTR_val)—Offset 808h .............................................................. 6302
19.11.3 (Cap_byps)—Offset 810h .................................................................... 6303
19.11.4 (Cap_byps_reg1)—Offset 814h ............................................................ 6303
19.11.5 (Cap_byps_reg2)—Offset 818h ............................................................ 6305
19.11.6 (reg_D0i3)—Offset 81Ch..................................................................... 6306
19.11.7 (Tx_CMD_dly)—Offset 820h ................................................................ 6307
19.11.8 (Tx_DATA_dly_1)—Offset 824h ........................................................... 6307
19.11.9 (Tx_DATA_dly_2)—Offset 828h ........................................................... 6308
19.11.10 (Rx_CMD_Data_dly_1)—Offset 82Ch .................................................. 6309
19.11.11 (Rx_Strobe_Ctrl_Path)—Offset 830h ................................................... 6310
19.11.12 (Rx_CMD_Data_dly_2)—Offset 834h................................................... 6311
19.11.13 (Master_Dll)—Offset 838h ................................................................. 6312
19.11.14 (Auto_tuning)—Offset 840h ............................................................... 6312
19.11.15(emmc_Root_Space)—Offset 900h ...................................................... 6313
19.12 SD Card Registers Summary ........................................................................... 6315
19.12.1 (SW_LTR_val)—Offset 804h ................................................................ 6315
19.12.2 (Auto_LTR_val)—Offset 808h .............................................................. 6316
19.12.3 (Cap_byps)—Offset 810h .................................................................... 6317
19.12.4 (Cap_byps_reg1)—Offset 814h ............................................................ 6317
19.12.5 (Cap_byps_reg2)—Offset 818h ............................................................ 6319
19.12.6 (reg_D0i3)—Offset 81Ch..................................................................... 6320
19.12.7 (Tx_CMD_dly)—Offset 820h ................................................................ 6321
19.12.8 (Tx_DATA_dly_1)—Offset 824h ........................................................... 6321
19.12.9 (Tx_DATA_dly_2)—Offset 828h ........................................................... 6322
19.12.10 (Rx_CMD_Data_dly_1)—Offset 82Ch .................................................. 6323
19.12.11 (Rx_Strobe_Ctrl_Path)—Offset 830h ................................................... 6324
19.12.12 (Rx_CMD_Data_dly_2)—Offset 834h................................................... 6325
19.12.13 (Master_Dll)—Offset 838h ................................................................. 6326
19.12.14 (Auto_tuning)—Offset 840h ............................................................... 6326
19.13 SDIO Registers Summary ............................................................................... 6329
19.13.1 (SW_LTR_val)—Offset 804h ................................................................ 6329
19.13.2 (Auto_LTR_val)—Offset 808h .............................................................. 6330
19.13.3 (Cap_byps)—Offset 810h .................................................................... 6331
19.13.4 (Cap_byps_reg1)—Offset 814h ............................................................ 6331
19.13.5 (Cap_byps_reg2)—Offset 818h ............................................................ 6333
19.13.6 (reg_D0i3)—Offset 81Ch..................................................................... 6334
19.13.7 (Tx_CMD_dly)—Offset 820h ................................................................ 6335
19.13.8 (Tx_DATA_dly_1)—Offset 824h ........................................................... 6335

162 334818
 19.13.9 (Tx_DATA_dly_2)—Offset 828h ............................................................6336
19.13.10 (Rx_CMD_Data_dly_1)—Offset 82Ch ...................................................6337
19.13.11 (Rx_Strobe_Ctrl_Path)—Offset 830h ...................................................6338
19.13.12 (Rx_CMD_Data_dly_2)—Offset 834h ...................................................6339
19.13.13 (Master_Dll)—Offset 838h ..................................................................6340
19.13.14 (Auto_tuning)—Offset 840h................................................................6340
19.14 Registers Summary ........................................................................................6343
19.14.1 (DEVVENDID)—Offset 0h.....................................................................6343
19.14.2(STATUSCOMMAND)—Offset 4h.............................................................6344
19.14.3(REVCLASSCODE)—Offset 8h ................................................................6345
19.14.4(CLLATHEADERBIST)—Offset Ch............................................................6345
19.14.5(BAR)—Offset 10h ...............................................................................6346
19.14.6(BAR_HIGH)—Offset 14h ......................................................................6347
19.14.7(BAR1)—Offset 18h .............................................................................6347
19.14.8(BAR1_HIGH)—Offset 1Ch ....................................................................6348
19.14.9(SUBSYSTEMID)—Offset 2Ch ................................................................6348
19.14.10(EXPANSION_ROM_BASEADDR)—Offset 30h .........................................6349
19.14.11(CAPABILITYPTR)—Offset 34h .............................................................6350
19.14.12(INTERRUPTREG)—Offset 3Ch .............................................................6350
19.14.13(POWERCAPID)—Offset 80h ................................................................6351
19.14.14(PMECTRLSTATUS)—Offset 84h ...........................................................6351
19.14.15(PCIDEVIDLE_CAP_RECORD)—Offset 90h .............................................6352
19.14.16(DEVID_VEND_SPECIFIC_REG)—Offset 94h ..........................................6353
19.14.17(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h...............................6353
19.14.18(DEVICE_IDLE_POINTER_REG)—Offset 9Ch...........................................6354
19.14.19(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ...................................6355
19.15 Registers Summary ........................................................................................6357
19.15.1SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h..
6358
19.15.2BlockSize Register (blocksize)—Offset 4h................................................6358
19.15.3BlockCount Register (blockcount)—Offset 6h...........................................6359
19.15.4Argument1 Register (argument1)—Offset 8h...........................................6359
19.15.5TransferMode Register (transfermode)—Offset Ch....................................6360
19.15.6Command Register (command)—Offset Eh..............................................6361
19.15.7Response Register (response01)—Offset 10h ..........................................6362
19.15.8Response Register (response2)—Offset 14h ............................................6362
19.15.9Response Register (response3)—Offset 16h ............................................6363
19.15.10Response Register (response4)—Offset 18h...........................................6363
19.15.11Response Register (response5)—Offset 1Ah ..........................................6364
19.15.12Response Register (response6)—Offset 1Ch ..........................................6364
19.15.13Response Register (response7)—Offset 1Eh...........................................6365
19.15.14Buffer DataPort Register (dataport)—Offset 20h.....................................6365
19.15.15eMMC Presentstate Register (presentstate)—Offset 24h ..........................6366
19.15.16HostControl1 Register (hostcontrol1)—Offset 28h...................................6368
19.15.17PowerControl Register (powercontrol)—Offset 29h..................................6369
19.15.18BlockGapControl Register (blockgapcontrol)—Offset 2Ah .........................6370
19.15.19Wakeup Control Register (wakeupcontrol)—Offset 2Bh............................6371
19.15.20Clock Control Register (clockcontrol)—Offset 2Ch ...................................6371
19.15.21Timeout Control Register (timeoutcontrol)—Offset 2Eh............................6372
19.15.22Software Reset Register (softwarereset)—Offset 2Fh ..............................6373
19.15.23Normal Interrupt Status Register (normalintrsts)—Offset 30h ..................6373
19.15.24ErrorInterruptStatus_Register (errorintrsts)—Offset 32h .........................6375
19.15.25Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h ...6376
19.15.26Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h .........6378
19.15.27Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h....6379

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 19.15.28Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah......... 6381
19.15.29Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch .............. 6382
19.15.30Host Control2 Register (hostcontrol2)—Offset 3Eh ................................. 6383
19.15.31Capabilities Register (capabilities)—Offset 40h ...................................... 6384
19.15.32Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h ....... 6387
19.15.33Force Event REGISTER for AUTO CMD Error Status
(ForceEventforAUTOCMDErrorStatus)—Offset 50h ................................... 6388
19.15.34Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset
52h................................................................................................... 6389
19.15.35ADMA Error Status Register (admaerrsts)—Offset 54h ............................ 6390
19.15.36ADMA System Address Register0&1 (admasysaddr01)—Offset 58h .......... 6390
19.15.37ADMA System Address Register1 (admasysaddr2)—Offset 5Ch ................ 6391
19.15.38ADMA System Address Register1 (admasysaddr3)—Offset 5Eh ................ 6392
19.15.39Boot Timeout Control Register (boottimeoutcnt)—Offset 70h ................... 6392
19.15.40Slot Interrupt Status Register (slotintrsts)—Offset FCh ........................... 6393
19.15.41Host Controller Version Register (hostcontrollerver)—Offset FEh .............. 6393
19.16 Registers Summary........................................................................................ 6395
19.16.1 (DEVVENDID)—Offset 0h .................................................................... 6395
19.16.2(STATUSCOMMAND)—Offset 4h ............................................................ 6396
19.16.3(REVCLASSCODE)—Offset 8h ............................................................... 6397
19.16.4(CLLATHEADERBIST)—Offset Ch ........................................................... 6397
19.16.5(BAR)—Offset 10h .............................................................................. 6398
19.16.6(BAR_HIGH)—Offset 14h ..................................................................... 6399
19.16.7(BAR1)—Offset 18h............................................................................. 6399
19.16.8(BAR1_HIGH)—Offset 1Ch ................................................................... 6400
19.16.9(SUBSYSTEMID)—Offset 2Ch................................................................ 6400
19.16.10(EXPANSION_ROM_BASEADDR)—Offset 30h ......................................... 6401
19.16.11(CAPABILITYPTR)—Offset 34h ............................................................. 6402
19.16.12(INTERRUPTREG)—Offset 3Ch ............................................................. 6402
19.16.13(POWERCAPID)—Offset 80h................................................................ 6403
19.16.14(PMECTRLSTATUS)—Offset 84h ........................................................... 6403
19.16.15(PCIDEVIDLE_CAP_RECORD)—Offset 90h ............................................. 6404
19.16.16(DEVID_VEND_SPECIFIC_REG)—Offset 94h .......................................... 6405
19.16.17(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h .............................. 6405
19.16.18(DEVICE_IDLE_POINTER_REG)—Offset 9Ch .......................................... 6406
19.16.19(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................. 6407
19.17 Registers Summary........................................................................................ 6409
19.17.1SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h .
6410
19.17.2BlockSize Register (blocksize)—Offset 4h ............................................... 6410
19.17.3BlockCount Register (blockcount)—Offset 6h .......................................... 6411
19.17.4Argument1 Register (argument1)—Offset 8h .......................................... 6411
19.17.5TransferMode Register (transfermode)—Offset Ch ................................... 6412
19.17.6Command Register (command)—Offset Eh ............................................. 6413
19.17.7Response Register (response01)—Offset 10h.......................................... 6414
19.17.8Response Register (response2)—Offset 14h ........................................... 6414
19.17.9Response Register (response3)—Offset 16h ........................................... 6415
19.17.10Response Register (response4)—Offset 18h .......................................... 6415
19.17.11Response Register (response5)—Offset 1Ah .......................................... 6416
19.17.12Response Register (response6)—Offset 1Ch .......................................... 6416
19.17.13Response Register (response7)—Offset 1Eh .......................................... 6417
19.17.14Buffer DataPort Register (dataport)—Offset 20h .................................... 6417
19.17.15SDIO PresentState Register (presentstate)—Offset 24h .......................... 6418
19.17.16HostControl1 Register (hostcontrol1)—Offset 28h .................................. 6420
19.17.17PowerControl Register (powercontrol)—Offset 29h ................................. 6421

164 334818
 19.17.18BlockGapControl Register (blockgapcontrol)—Offset 2Ah .........................6422
19.17.19Wakeup Control Register (wakeupcontrol)—Offset 2Bh............................6422
19.17.20Clock Control Register (clockcontrol)—Offset 2Ch ...................................6423
19.17.21Timeout Control Register (timeoutcontrol)—Offset 2Eh............................6424
19.17.22Software Reset Register (softwarereset)—Offset 2Fh ..............................6425
19.17.23Normal Interrupt Status Register (normalintrsts)—Offset 30h ..................6425
19.17.24ErrorInterruptStatus_Register (errorintrsts)—Offset 32h .........................6427
19.17.25Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h ...6428
19.17.26Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h .........6430
19.17.27Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h....6431
19.17.28Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah .........6433
19.17.29Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch ...............6434
19.17.30Host Control2 Register (hostcontrol2)—Offset 3Eh..................................6435
19.17.31Capabilities Register (capabilities)—Offset 40h .......................................6436
19.17.32Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h........6439
19.17.33Force Event REGISTER for AUTO CMD Error Status
(ForceEventforAUTOCMDErrorStatus)—Offset 50h....................................6439
19.17.34Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset
52h ...................................................................................................6440
19.17.35ADMA Error Status Register (admaerrsts)—Offset 54h ............................6441
19.17.36ADMA System Address Register0&1 (admasysaddr01)—Offset 58h ...........6442
19.17.37ADMA System Address Register1 (admasysaddr2)—Offset 5Ch ................6443
19.17.38ADMA System Address Register1 (admasysaddr3)—Offset 5Eh.................6443
19.17.39Boot Timeout Control Register (boottimeoutcnt)—Offset 70h ...................6444
19.17.40Slot Interrupt Status Register (slotintrsts)—Offset FCh............................6444
19.17.41Host Controller Version Register (hostcontrollerver)—Offset FEh...............6445
19.18 Registers Summary ........................................................................................6447
19.18.1 (DEVVENDID)—Offset 0h.....................................................................6447
19.18.2(STATUSCOMMAND)—Offset 4h.............................................................6448
19.18.3(REVCLASSCODE)—Offset 8h ................................................................6449
19.18.4(CLLATHEADERBIST)—Offset Ch............................................................6449
19.18.5(BAR)—Offset 10h ...............................................................................6450
19.18.6(BAR_HIGH)—Offset 14h ......................................................................6451
19.18.7(BAR1)—Offset 18h .............................................................................6451
19.18.8(BAR1_HIGH)—Offset 1Ch ....................................................................6452
19.18.9(SUBSYSTEMID)—Offset 2Ch ................................................................6452
19.18.10(EXPANSION_ROM_BASEADDR)—Offset 30h .........................................6453
19.18.11(CAPABILITYPTR)—Offset 34h .............................................................6454
19.18.12(INTERRUPTREG)—Offset 3Ch .............................................................6454
19.18.13(POWERCAPID)—Offset 80h ................................................................6455
19.18.14(PMECTRLSTATUS)—Offset 84h ...........................................................6455
19.18.15(PCIDEVIDLE_CAP_RECORD)—Offset 90h .............................................6456
19.18.16(DEVID_VEND_SPECIFIC_REG)—Offset 94h ..........................................6457
19.18.17(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h...............................6457
19.18.18(DEVICE_IDLE_POINTER_REG)—Offset 9Ch...........................................6458
19.18.19(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ...................................6459
19.19 Registers Summary ........................................................................................6461
19.19.1SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h..
6462
19.19.2BlockSize Register (blocksize)—Offset 4h................................................6462
19.19.3BlockCount Register (blockcount)—Offset 6h...........................................6463
19.19.4Argument1 Register (argument1)—Offset 8h...........................................6463
19.19.5TransferMode Register (transfermode)—Offset Ch....................................6464
19.19.6Command Register (command)—Offset Eh..............................................6465
19.19.7Response Register (response01)—Offset 10h ..........................................6466

334818 165
 19.19.8Response Register (response2)—Offset 14h ........................................... 6466
19.19.9Response Register (response3)—Offset 16h ........................................... 6467
19.19.10Response Register (response4)—Offset 18h .......................................... 6467
19.19.11Response Register (response5)—Offset 1Ah .......................................... 6468
19.19.12Response Register (response6)—Offset 1Ch .......................................... 6468
19.19.13Response Register (response7)—Offset 1Eh .......................................... 6469
19.19.14Buffer DataPort Register (dataport)—Offset 20h .................................... 6469
19.19.15SD Card PresentState Register (presentstate)—Offset 24h ...................... 6470
19.19.16HostControl1 Register (hostcontrol1)—Offset 28h .................................. 6472
19.19.17PowerControl Register (powercontrol)—Offset 29h ................................. 6473
19.19.18BlockGapControl Register (blockgapcontrol)—Offset 2Ah......................... 6474
19.19.19Wakeup Control Register (wakeupcontrol)—Offset 2Bh ........................... 6475
19.19.20Clock Control Register (clockcontrol)—Offset 2Ch .................................. 6476
19.19.21Timeout Control Register (timeoutcontrol)—Offset 2Eh ........................... 6476
19.19.22Software Reset Register (softwarereset)—Offset 2Fh.............................. 6477
19.19.23Normal Interrupt Status Register (normalintrsts)—Offset 30h.................. 6478
19.19.24ErrorInterruptStatus_Register (errorintrsts)—Offset 32h......................... 6479
19.19.25Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h... 6481
19.19.26Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h ........ 6482
19.19.27Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h ... 6484
19.19.28Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah......... 6485
19.19.29Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch .............. 6487
19.19.30Host Control2 Register (hostcontrol2)—Offset 3Eh ................................. 6488
19.19.31Capabilities Register (capabilities)—Offset 40h ...................................... 6489
19.19.32Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h ....... 6491
19.19.33Force Event REGISTER for AUTO CMD Error Status
(ForceEventforAUTOCMDErrorStatus)—Offset 50h ................................... 6492
19.19.34Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset
52h................................................................................................... 6493
19.19.35ADMA Error Status Register (admaerrsts)—Offset 54h ............................ 6494
19.19.36ADMA System Address Register0&1 (admasysaddr01)—Offset 58h .......... 6495
19.19.37ADMA System Address Register1 (admasysaddr2)—Offset 5Ch ................ 6495
19.19.38ADMA System Address Register1 (admasysaddr3)—Offset 5Eh ................ 6496
19.19.39Boot Timeout Control Register (boottimeoutcnt)—Offset 70h ................... 6496
19.19.40Slot Interrupt Status Register (slotintrsts)—Offset FCh ........................... 6497
19.19.41Host Controller Version Register (hostcontrollerver)—Offset FEh .............. 6498
20 I2S....................................................................................................................... 6499
20.1 Register Summary ......................................................................................... 6499
20.1.1 SSP Control 0 (SSC0) - Offset 00h ........................................................ 6499
20.1.2 SSP Control 1 (SSC1) - Offset 04h ........................................................ 6501
20.1.3 SSP Status (SSS) - Offset 08h .............................................................. 6503
20.1.4 SSP Data (SSD) - Offset 10h ................................................................ 6505
20.1.5 SSP Time Out (SSTO) - Offset 28h ........................................................ 6506
20.1.6 SSP Programmable Serial Protocol (SSPSP) - Offset 2Ch .......................... 6506
20.1.7 SSP TX Time Slot Active (SSTSA) - Offset 30h ........................................ 6508
20.1.8 SSP RX Time Slot Active (SSRSA) - Offset 34h........................................ 6509
20.1.9 SSP Time Slot Status (SSTSS) - Offset 38h ............................................ 6509
20.1.10SSP Command/Status 2 (SSC2) - Offset 40h .......................................... 6510
20.1.11SSP Programmable Serial Protocol 2 (SSPSP2) - Offset 44h ...................... 6512
20.1.12SSP Command/Status 3 (SSC3) - Offset 48h .......................................... 6512
20.1.13SSP IO Control (SSIOC) - Offset 4Ch ..................................................... 6513
20.2 M/N Clock Synthesizer Registers ...................................................................... 6514
20.2.1 Register Summary .............................................................................. 6514
20.3 MCLK and BCLK Calculation: ........................................................................... 6515

166 334818
 20.3.1 Offset 000h: MDIVCTRL - MCLK Divider Control Register...........................6515
20.3.2 Offset 080h: MDIV0R – MCLK Divider 0 Ratio Register..............................6516
20.3.3 Offset 084h: MDIV1R – MCLK Divider 1 Ratio Register..............................6516
20.3.4 Offset 100h: I2S1_MDIVMVAL – I2S1 M/N Divider M Value Register ...........6517
20.3.5 Offset 104h: I2S1_MDIVNVAL – I2S1 M/N Divider N Value Register ...........6517
20.3.6 Offset 108h: I2S2_MDIVMVAL – I2S2 M/N Divider M Value Register ...........6518
20.3.7 Offset 10Ch: I2S2_MDIVNVAL – I2S2 M/N Divider N Value Register ...........6518
20.3.8 Offset 110h: I2S3_MDIVMVAL – I2S3 M/N Divider M Value Register ...........6519
20.3.9 Offset 114h: I2S3_MDIVNVAL – I2S3 M/N Divider N Value Register ...........6519
20.3.10Offset 118h: I2S4_MDIVMVAL – I2S4 M/N Divider M Value Register ...........6519
20.3.11Offset 11Ch: I2S4_MDIVNVAL – I2S4 M/N Divider N Value Register ...........6520
20.3.12Offset 120h: I2S5_MDIVMVAL – I2S5 M/N Divider M Value Register ...........6520
20.3.13Offset 124h: I2S5_MDIVNVAL – I2S5 M/N Divider N Value Register ...........6521
20.3.14Offset 128h: I2S6_MDIVMVAL – I2S6 M/N Divider M Value Register ...........6521
20.3.15Offset 12Ch: I2S6_MDIVNVAL – I2S6 M/N Divider N Value Register ...........6521

Tables
2-1 Memory Map Configuration Registers ............................................................................ 8
2-2 Low DRAM Default Address Decode Rule ....................................................................... 9
2-3 Legacy VGA A.......................................................................................................... 10
2-4 Legacy MDA ............................................................................................................ 10
2-5 Legacy VGA B.......................................................................................................... 11
2-6 PMR-L .................................................................................................................... 11
2-7 TSEG...................................................................................................................... 12
2-8 GSM....................................................................................................................... 12
2-9 Low MMIO Address Range ......................................................................................... 13
2-10PCIe MMCFG ........................................................................................................... 14
2-11MCHBAR ................................................................................................................. 14
2-12Default VTd BAR ...................................................................................................... 15
2-13Graphics VTd BAR .................................................................................................... 15
2-14GTTMMADR ............................................................................................................. 16
2-15GMADR................................................................................................................... 16
2-16I-Unit BAR .............................................................................................................. 17
2-17LPC Generic Memory Range....................................................................................... 17
2-18CRAB_ABORT .......................................................................................................... 17
2-19IOAPIC ................................................................................................................... 18
2-20HPET ...................................................................................................................... 18
2-21TPM locality 0 .......................................................................................................... 18
2-22TPM Locality 1-3 ...................................................................................................... 19
2-23TPM Locality 1-3 ...................................................................................................... 19
2-24xHCI.DBC ............................................................................................................... 19
2-25IOAPIC ................................................................................................................... 20
2-26BIOS1 .................................................................................................................... 20
2-27BIOS2 .................................................................................................................... 21
2-28BIOS3 .................................................................................................................... 21
2-29BIOS4 .................................................................................................................... 21
2-30High DRAM.............................................................................................................. 22
2-31PMR-H.................................................................................................................... 23
2-32High MMIO Address Range ........................................................................................ 23
2-33Fixed I/O Address Map Positive Decode ....................................................................... 27
2-34Fixed I/O Address Map Subtractive Decode.................................................................. 28
2-35Legacy Variable I/O Address Map ............................................................................... 30
2-36Display IOBAR ......................................................................................................... 30

334818 167
 2-37PCI Config PORT CF8 Mapping ....................................................................................31
2-38PCI Config Memory Bar Mapping.................................................................................32
2-39Funny I/O Address Ranges and Routing .......................................................................35
2-40P2SB MMIO Register Interface....................................................................................35
3-1 PCI Configuration Matrix: (Snapshot effective 10/12/2014 12:38 PM) ..............................40
4-1 Fixed I/O Register Access Method Example (P80 Register) .............................................43
4-2 Referenced I/O Register Access Method Example (HSTS Register) ...................................44
4-3 PCI Register Access Method Example (VID Register) .....................................................44
4-4 PCI CONFIG_ADDRESS Register (I/O PORT CF8h) Mapping ............................................44
4-5 Fixed Memory-Mapped Register Access Method Example (IDX Register) ...........................46
4-6 Memory-Mapped Register Access Method Example (_MBAR Register)...............................46
4-7 P2SB MMIO Register Interface....................................................................................47
4-8 Access Type Explanations ..........................................................................................48
4-9 Attributes/Modifiers are Applied to Base Access Types to Describe HW Interaction or Other
Details ....................................................................................................................48
5-1 Summary of pcs_regs_wrapper Registers ....................................................................51
5-2 Summary of pcs_regs_wrapper Registers ....................................................................52
5-3 Summary of pcs_regs_wrapper Registers ....................................................................96
5-4 Summary of pcs_regs_wrapper Registers .................................................................. 140
5-5 Summary of pcs_regs_wrapper Registers .................................................................. 184
5-6 Summary of memss_regs Registers .......................................................................... 228
5-7 Summary of pcs_regs_wrapper Registers .................................................................. 273
5-8 Summary of pcs_regs_wrapper Registers .................................................................. 329
5-9 Summary of pcs_regs_wrapper Registers .................................................................. 374
5-10Summary of pcs_regs_wrapper Registers .................................................................. 742
5-11Summary of cpgc_t_submap Registers ...................................................................... 771
5-12Summary of cpgc_c_submap Registers.................................................................... 1031
5-13Summary of cpgc_t_submap Registers .................................................................... 1061
5-14Summary of cpgc_c_submap Registers.................................................................... 1321
5-15Summary of cpgc_t_submap Registers .................................................................... 1351
5-16Summary of pcs_regs_wrapper Registers ................................................................ 1611
5-17Summary of pcs_regs_wrapper Registers ................................................................ 1613
5-18Summary of pcs_regs_wrapper Registers ................................................................ 1657
5-19Summary of pcs_regs_wrapper Registers ................................................................ 1701
5-20Summary of pcs_regs_wrapper Registers ................................................................ 1745
5-21Summary of memss_regs Registers ........................................................................ 1789
5-22Summary of pcs_regs_wrapper Registers ................................................................ 1833
5-23Summary of pcs_regs_wrapper Registers ................................................................ 1891
5-24Summary of pcs_regs_wrapper Registers ................................................................ 1937
5-25Summary of pcs_regs_wrapper Registers ................................................................ 2305
6-1 Summary of pcs_regs Registers.............................................................................. 2335
7-1 Summary of pcs_regs Registers.............................................................................. 2337
7-2 Summary of pcs_regs Registers.............................................................................. 2341
8-1 Summary of pcs_regs_wrapper Registers ................................................................ 2345
8-2 Summary of pcs_regs_wrapper Registers ................................................................ 2359
8-3 Summary of pcs_regs_wrapper Registers ................................................................ 2368
8-4 Summary of pcs_regs_wrapper Registers ................................................................ 2373
8-5 Summary of pcs_regs_wrapper Registers ................................................................ 2381
8-6 Summary of pcs_regs_wrapper Registers ................................................................ 2382
8-7 Summary of pcs_regs_wrapper Registers ................................................................ 2383
8-8 Summary of pcs_regs_wrapper Registers ................................................................ 2384
8-9 Summary of pcs_regs_wrapper Registers ................................................................ 2385
8-10Summary of pcs_regs_wrapper Registers ................................................................ 2391
8-11Summary of pcs_regs_wrapper Registers ................................................................ 2407
8-12Summary of pcs_regs_wrapper Registers ................................................................ 2417

168 334818
 8-13Summary of pcs_regs_wrapper Registers .................................................................2423
8-14Summary of pcs_regs_wrapper Registers .................................................................2431
8-15Summary of pcs_regs_wrapper Registers .................................................................2433
8-16Summary of pcs_regs_wrapper Registers .................................................................2435
8-17Summary of pcs_regs_wrapper Registers .................................................................2437
8-18Summary of pcs_regs_wrapper Registers .................................................................2439
9-1 Summary of pcs_regs_wrapper Registers .................................................................2445
9-2 Summary of pcs_regs_wrapper Registers .................................................................2473
9-3 Summary of pcs_regs_wrapper Registers .................................................................2477
9-4 Summary of pcs_regs_wrapper Registers .................................................................2507
10-1Summary of IUNIT_CFG Registers ...........................................................................2509
10-2Summary of IUNIT_CFG Registers ...........................................................................2529
11-1Summary of HDAHC_CFGREG Registers ...................................................................2549
11-2Summary of HDAHC_MMREG Registers ....................................................................2590
11-3Summary of HDAHC_CFGREG Registers ...................................................................2917
11-4Summary of HDAHC_MMREG Registers ....................................................................2959
12-1Summary of ACPI CR Registers ...............................................................................3285
12-2Summary of GCR CR Registers................................................................................3318
12-3Summary of IPC Registers Registers ........................................................................3354
12-4Summary of soc_regs_wrapper Registers .................................................................3361
12-5Summary of soc_regs_wrapper Registers .................................................................3376
12-6Summary of Pulse Width Modulator Controller Registers .............................................3391
12-7Summary of soc_regs_wrapper Registers .................................................................3396
12-8Summary of soc_regs_wrapper Registers .................................................................3411
12-9Summary of soc_regs_wrapper Registers .................................................................3426
12-10Summary of soc_regs_wrapper Registers ...............................................................3441
12-11Summary of ACPI CR Registers .............................................................................3457
12-12Summary of GCR CR Registers..............................................................................3491
12-13Summary of IPC Registers Registers ......................................................................3529
12-14Summary of soc_regs_wrapper Registers ...............................................................3537
12-15Summary of soc_regs_wrapper Registers ...............................................................3553
12-16Summary of Pulse Width Modulator Controller Registers ...........................................3569
12-17Summary of soc_regs_wrapper Registers ...............................................................3575
12-18Summary of soc_regs_wrapper Registers ...............................................................3591
12-19Summary of soc_regs_wrapper Registers ...............................................................3607
12-20Summary of soc_regs_wrapper Registers ...............................................................3623
13-1Summary of pcs_regs_wrapper Registers .................................................................3639
13-2Summary of pcs_regs_wrapper Registers .................................................................3643
13-3Summary of pcs_regs_wrapper Registers .................................................................3660
13-4Summary of pcs_regs_wrapper Registers .................................................................3686
13-5Summary of pcs_regs_wrapper Registers .................................................................3703
13-6Summary of pcs_regs_wrapper Registers .................................................................3707
13-7Summary of pcs_regs_wrapper Registers .................................................................3725
13-8Summary of pcs_regs_wrapper Registers .................................................................3751
14-1Summary of 0_31_0_APIC MEM Registers ................................................................3767
14-2Summary of 0_31_0_APIC MEM REG Registers .........................................................3931
14-3Summary of 0_31_0_CPU IO Registers ....................................................................3932
14-4Summary of 0_31_0_HPET MEM SPT Registers .........................................................3936
14-5Summary of 0_31_0_INTR IO Registers ...................................................................3980
14-6Summary of 0_31_0_LEG_8254_TIMER IO Registers .................................................3993
14-7Summary of 0_31_0_APIC MEM Registers ................................................................4001
14-8Summary of 0_31_0_APIC MEM REG Registers .........................................................4165
14-9Summary of 0_31_0_CPU IO Registers ....................................................................4167
14-10Summary of 0_31_0_HPET MEM SPT Registers........................................................4171
14-11Summary of 0_31_0_INTR IO Registers .................................................................4215

334818 169
 14-12Summary of 0_31_0_LEG_8254_TIMER IO Registers............................................... 4229
15-1Summary of map_iosf2ocp_pci_configreg Registers .................................................. 4237
15-2Summary of map_iosf2ocp_pci_configreg Registers .................................................. 4253
16-1Summary of pcie_cfg Registers .............................................................................. 4269
16-2Summary of pcie_cfg Registers .............................................................................. 4449
17-1Summary of sata_configreg_top Registers ............................................................... 4629
17-2Summary of sata_configreg_top Registers ............................................................... 4660
17-3Summary of sata_configreg_top Registers ............................................................... 4661
17-4Summary of sata_configreg_top Registers ............................................................... 4707
17-5Summary of sata_configreg_top Registers ............................................................... 4709
17-6Summary of sata_configreg_top Registers ............................................................... 4713
17-7Summary of sata_configreg_top Registers ............................................................... 4745
17-8Summary of sata_configreg_top Registers ............................................................... 4747
17-9Summary of sata_configreg_top Registers ............................................................... 4795
17-10Summary of sata_configreg_top Registers ............................................................. 4797
18-1Summary of 0_20_0_USBx MMIO Registers Registers ............................................... 4801
18-2Summary of 0_20_0_USBx PCI Config Registers Registers ......................................... 5117
18-3Summary of 0_20_0_usbx_exi_on_dbc_registers Registers........................................ 5150
18-4Summary of USBX device top Registers ................................................................... 5269
18-5Summary of USBX device top Registers ................................................................... 5350
18-6Summary of USBX device top Registers ................................................................... 5398
18-7Summary of USBX device top Registers ................................................................... 5407
18-8Summary of USBX device top Registers ................................................................... 5411
18-9Summary of USBX device top Registers ................................................................... 5415
18-10Summary of USBX device top Registers ................................................................. 5427
18-11Summary of 0_20_0_USBx MMIO Registers Registers.............................................. 5439
18-12Summary of 0_20_0_USBx PCI Config Registers Registers ....................................... 5757
18-13Summary of 0_20_0_usbx_exi_on_dbc_registers Registers ...................................... 5791
18-14Summary of USBX device top Registers ................................................................. 5909
18-15Summary of USBX device top Registers ................................................................. 5991
18-16Summary of USBX device top Registers ................................................................. 6041
18-17Summary of USBX device top Registers ................................................................. 6051
18-18Summary of USBX device top Registers ................................................................. 6055
18-19Summary of USBX device top Registers ................................................................. 6059
18-20Summary of USBX device top Registers ................................................................. 6071
19-1Summary of CONVERGE_LAYER Registers................................................................ 6083
19-2Summary of CONVERGE_LAYER Registers................................................................ 6096
19-3Summary of CONVERGE_LAYER Registers................................................................ 6108
19-4Summary of soc_regs_wrapper Registers ................................................................ 6121
19-5Summary of SDHOST_OCP Registers ...................................................................... 6134
19-6Summary of soc_regs_wrapper Registers ................................................................ 6171
19-7Summary of SDHOST_OCP Registers ...................................................................... 6184
19-8Summary of soc_regs_wrapper Registers ................................................................ 6222
19-9Summary of SDHOST_OCP Registers ...................................................................... 6235
19-10Summary of CONVERGE_LAYER Registers .............................................................. 6275
19-11Summary of CONVERGE_LAYER Registers .............................................................. 6289
19-12Summary of CONVERGE_LAYER Registers .............................................................. 6303
19-13Summary of soc_regs_wrapper Registers............................................................... 6317
19-14Summary of SDHOST_OCP Registers..................................................................... 6331
19-15Summary of soc_regs_wrapper Registers............................................................... 6369
19-16Summary of SDHOST_OCP Registers..................................................................... 6383
19-17Summary of soc_regs_wrapper Registers............................................................... 6421
19-18Summary of SDHOST_OCP Registers..................................................................... 6435

170 334818
Revision History

Document Revision
Description Revision Date
Number Number

September
334818 001 Initial release
2016
• Updated Chapter 10 with new registers
• Updated Chapter 14 by removing a few registers
334818 002 • Updated Chapter 16 with new registers April 2020
• Updated Chapter 19 with new registers
• Added Chapter 20, “I2S”
334818 003 • fixed formatting June 2020
334818 004 • Added section 4.3, “Apollo Lake SoC IOSF-SB Bus Access” December 2020
• Updated Section 18.1.192 SuperSpeed Port Link Control
334818 005 (HOST_CTRL_PORT_LINK_REG)—Offset 80ECh November 2021
• Updated Section 18.1.393 USB2 COMPBG (USB2_COMPBG)—Offset 7F04h
334818 006 • Updated Chapter 16 with new registers January 2023

§§

334818 171
172 334818
1 SoC Address Map .......................................................................................................5
1.1 Root Spaces sup ................................................................................................. 5
1.2 Super Set Architecture Definition........................................................................... 5
2 Host Root Space ........................................................................................................6
2.1 Host Memory Address Space ................................................................................. 6
2.1.1 Host Memory Space Address Decode and Routing ......................................... 7
2.1.2 Abort Handling......................................................................................... 8
2.1.2.1 B-Unit Abort Handling.................................................................. 9
2.1.2.2 IOSF Abort Handling.................................................................... 9
2.1.3 Low DRAM Address Range (0 to (TOLUD - 1)................................................ 9
2.1.3.1 Legacy Video Area (A_0000h to B_FFFFh) ...................................... 9
2.1.3.2 Expansion Area (C_0000h to D_FFFFh) ........................................ 11
2.1.3.3 PAM Memory Area (E_0000h to F_FFFFh) ..................................... 11
2.1.3.4 Protected Memory Range (PMR-L: programmable)......................... 11
2.1.3.5 DMA Protected Range (DPR: Programmable) ................................ 12
2.1.3.6 TSEG SMM Range (Programmable).............................................. 12
2.1.3.7 Graphics Stolen Memory (Programmable) .................................... 12
2.1.4 Low MMIO Address Range (TOLUD to 4 GB) ............................................... 13
2.1.4.1 PCIe Memory Mapped Config Range (Programmable) ..................... 13
2.1.4.2 Host Bridge.............................................................................. 14
2.1.4.3 Integrated Graphics Device (IGD) ............................................... 15
2.1.4.4 I-Unit ...................................................................................... 16
2.1.4.5 LPC Generic Memory Range........................................................ 17
2.1.4.6 CRAB_ABORT (0xFEB0_0000 to 0xFEBF_FFFF).............................. 17
2.1.4.7 IOAPIC (0xFEC0_0000 to 0xFECF_FFFF) ...................................... 17
2.1.4.8 HPET (0xFED0_0000 – 0xFED0_33FF) ......................................... 18
2.1.4.9 TPM (0xFED4_0000 to 0xFED4_0FFF) .......................................... 18
2.1.4.10 TXT (0xFED2_0000 to 0xFED3_FFFF)........................................... 18
2.1.4.11 TPM (0xFED4_1000 to 0xFED4_3FFF) .......................................... 19
2.1.4.12 xHCI.DBC (0xFED6_0000 to 0xFED6_0FFF) .................................. 19
2.1.4.13 Local APIC (0xFEE0_0000 to 0xFEEF_FFFF) .................................. 19
2.1.4.14 IAFW (BIOS) (0xFFXX_0000 to 0xFFFF_FFFF) ............................... 20
2.1.5 High DRAM (0x1_0000_0000 to (TOUUD - 1))............................................ 22
2.1.5.1 Protected Memory Range (PMR-H: Programmable) ........................ 22
2.1.6 High MMIO Address Range (TOUUD to 0x7F_FFFF_FFFF).............................. 23
2.1.6.1 Other Ranges in High MMIO Address Ranges ................................ 23
2.2 System DRAM Address Space.............................................................................. 24
2.2.1 Physical to System DRAM Address Mapping................................................ 24
2.2.2 Case 1: 2 GB DRAM. Minimum 1 GB PCI MMIO ........................................... 24
2.2.3 Case 2: 8 GB DRAM. Minimum 1 GB PCI MMIO ........................................... 25
2.3 System Management Mode (SMM) ....................................................................... 25
2.3.1 IAFW Programming Restrictions ............................................................... 25
2.3.2 SoC Internal Enforcement of SMM Protection.............................................. 26
2.3.2.1 CPU WB Transaction to an Enabled SMM Address Space ................. 26
2.4 I/O Space ........................................................................................................ 26
2.4.1 Fixed I/O Ranges: Decode and Routing ..................................................... 27
2.4.2 Variable I/O Ranges: Decode and Routing ................................................. 29
2.4.2.1 Integrated Graphics Device (IGD) ............................................... 30
2.5 PCI Config Space............................................................................................... 30
2.5.1 Configuration Mechanisms ....................................................................... 31
2.5.1.1 Standard PCI Configuration Mechanism........................................ 31
2.5.1.2 PCI Express Enhanced Configuration Mechanism ........................... 31
2.5.1.3 Type 0/Type 1 Configuration ...................................................... 33
2.5.2 ACPI Mode ............................................................................................ 33
2.5.2.1 Hybrid ACPI Configuration Object ................................................ 33
2.5.2.2 Fixed ACPI Configuration Object.................................................. 33

334818 1
 2.5.2.3 IOSF2OCP Bridge ACPI Mode ......................................................33
2.6 Funny I/O Space................................................................................................34
2.6.1 RAVDMs ................................................................................................34
2.6.2 FunnyIO Address Ranges .........................................................................34
2.7 IOSF-SB Private CR Space ..................................................................................35
2.8 PCI Devices ......................................................................................................36
2.9 System Memory Protection..................................................................................36
2.9.1 PMR-L and PMR-H ...................................................................................36
2.9.2 B-Unit Isolated Memory Regions (IMRs) .....................................................36
3 CSE Root Space ........................................................................................................37
3.1 CSE Memory Address Space ................................................................................37
3.1.1 SoC System Agent Decode and Routing .....................................................37
3.1.2 Abort Handling .......................................................................................37
3.1.2.1 B-Unit Abort Handling ................................................................37
3.1.2.2 IOSF Abort Handling ..................................................................38
3.1.3 Fixed Positive Decode Ranges...................................................................38
3.1.4 Programmable Positive Decode Ranges ......................................................38
3.1.4.1 Dedicated PCI Functions.............................................................38
3.1.4.2 Switchable PCI Functions............................................................38
3.1.4.3 DRAM as Peer Address Ranges ....................................................38
3.2 System DRAM Address Space ..............................................................................39
3.3 I/O Space .........................................................................................................39
3.4 PCI Config Space ...............................................................................................39
3.5 IOSF-SB Private CR Space ..................................................................................39
3.6 PCI Devices ......................................................................................................39
4 Register Access Methods..........................................................................................43
4.1 I/O-Space Register Access Methods......................................................................43
4.1.1 Fixed I/O Register Access ........................................................................43
4.1.2 Variable I/O (I/O-Referenced) Register Access............................................43
4.1.3 PCI Configuration Register Access .............................................................44
4.1.3.1 PCI Configuration Access—CAM: I/O Indexed Scheme ....................44
4.1.3.2 PCI Configuration Access—ECAM: Memory Mapped Scheme ............45
4.2 Memory-Space Register Access Methods ...............................................................46
4.2.1 Fixed Memory-Mapped Register Access ......................................................46
4.2.2 Variable Memory (Memory-Referenced) Register Access...............................46
4.3 Apollo Lake SoC IOSF-SB Bus Access....................................................................46
4.3.1 IOSF-SB Register Addressability ...............................................................47
4.3.2 IOSF-SB Access Mechanisms ....................................................................47
4.4 Register Field Access Types.................................................................................47
4.5 Alternate Access Mode........................................................................................50
5 MCHBAR...................................................................................................................51
5.1 Registers Summary............................................................................................51
5.1.1 Noncached Region Control (B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset
6B60h ...................................................................................................51
5.2 Registers Summary............................................................................................52
5.2.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1000h.................................53
5.2.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1008h .............................55
5.2.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 100Ch .............................57
5.2.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1010h .............................58
5.2.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1014h .............................59
5.2.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1018h .............................60
5.2.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 101Ch .............................61
5.2.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1020h .............................62

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 5.2.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1024h ............................. 63
5.2.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1028h ............................. 64
5.2.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 102Ch...................... 65
5.2.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1030h ............. 67
5.2.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1034h ............. 68
5.2.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1038h.................................... 71
5.2.15 D-Unit Scheduler (D_CR_DSCH)—Offset 103Ch .......................................... 73
5.2.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1040h ............................... 74
5.2.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 104Ch ...................... 76
5.2.18 Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1050h..
77
5.2.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1054h ................ 78
5.2.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 10A4h ................................... 79
5.2.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset 10ACh ................. 80
5.2.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 10B0h............ 80
5.2.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 10B4h ............................ 81
5.2.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 10BCh ...................................... 82
5.2.25 Major Mode Control (D_CR_MMC)—Offset 1124h ........................................ 83
5.2.26 Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1128h
84
5.2.27 Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 112Ch
85
5.2.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1130h ............................ 86
5.2.29 Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1134h . 86
5.2.30 Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1138h . 87
5.2.31 Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 113Ch . 88
5.2.32 Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1140h . 89
5.2.33 Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1144h . 90
5.2.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1148h .................................. 90
5.2.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 114Ch .............. 91
5.2.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1154h........... 93
5.2.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1180h ......... 94
5.2.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1184h ................ 95
5.3 Registers Summary ........................................................................................... 96
5.3.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1200h ................................ 98
5.3.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1208h ........................... 100
5.3.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 120Ch ........................... 101
5.3.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1210h ........................... 102
5.3.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1214h ........................... 103
5.3.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1218h ........................... 104
5.3.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 121Ch ........................... 105
5.3.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1220h ........................... 107
5.3.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1224h ........................... 108
5.3.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1228h ........................... 109
5.3.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 122Ch.................... 110
5.3.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1230h ........... 111
5.3.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1234h ........... 113
5.3.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1238h.................................. 115
5.3.15 D-Unit Scheduler (D_CR_DSCH)—Offset 123Ch ........................................ 117
5.3.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1240h ............................. 119
5.3.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 124Ch .................... 120
5.3.18 Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1250h..
121
5.3.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1254h .............. 122
5.3.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 12A4h ................................. 123

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 5.3.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset 12ACh ................ 124
5.3.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 12B0h .......... 125
5.3.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 12B4h .......................... 126
5.3.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 12BCh..................................... 127
5.3.25 Major Mode Control (D_CR_MMC)—Offset 1324h....................................... 127
5.3.26 Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1328h
128
5.3.27 Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 132Ch
129
5.3.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1330h........................... 130
5.3.29 Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1334h 131
5.3.30 Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1338h 131
5.3.31 Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 133Ch 132
5.3.32 Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1340h 133
5.3.33 Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1344h 134
5.3.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1348h................................. 135
5.3.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 134Ch ............ 135
5.3.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1354h ......... 137
5.3.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1380h ....... 138
5.3.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1384h............... 139
5.4 Registers Summary.......................................................................................... 140
5.4.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1400h............................... 142
5.4.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1408h ........................... 144
5.4.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 140Ch ........................... 145
5.4.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1410h ........................... 146
5.4.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1414h ........................... 147
5.4.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1418h ........................... 148
5.4.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 141Ch ........................... 149
5.4.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1420h ........................... 151
5.4.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1424h ........................... 152
5.4.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1428h ........................... 153
5.4.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 142Ch .................... 154
5.4.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1430h............ 155
5.4.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1434h............ 157
5.4.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1438h .................................. 159
5.4.15 D-Unit Scheduler (D_CR_DSCH)—Offset 143Ch ........................................ 161
5.4.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1440h.............................. 163
5.4.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 144Ch .................... 164
5.4.18 Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1450h .
165
5.4.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1454h ............... 166
5.4.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 14A4h.................................. 167
5.4.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset 14ACh ................ 168
5.4.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 14B0h .......... 169
5.4.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 14B4h .......................... 170
5.4.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 14BCh..................................... 171
5.4.25 Major Mode Control (D_CR_MMC)—Offset 1524h....................................... 171
5.4.26 Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1528h
172
5.4.27 Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 152Ch
173
5.4.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1530h........................... 174
5.4.29 Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1534h 175
5.4.30 Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1538h 175
5.4.31 Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 153Ch 176

4 334818
 5.4.32 Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1540h 177
5.4.33 Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1544h 178
5.4.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1548h ................................ 179
5.4.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 154Ch ............ 179
5.4.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1554h......... 181
5.4.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1580h ....... 182
5.4.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1584h .............. 183
5.5 Registers Summary ......................................................................................... 184
5.5.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1600h .............................. 186
5.5.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1608h ........................... 188
5.5.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 160Ch ........................... 189
5.5.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1610h ........................... 190
5.5.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1614h ........................... 191
5.5.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1618h ........................... 192
5.5.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 161Ch ........................... 193
5.5.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1620h ........................... 195
5.5.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1624h ........................... 196
5.5.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1628h ........................... 197
5.5.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 162Ch.................... 198
5.5.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1630h ........... 199
5.5.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1634h ........... 201
5.5.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1638h.................................. 203
5.5.15 D-Unit Scheduler (D_CR_DSCH)—Offset 163Ch ........................................ 205
5.5.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1640h ............................. 207
5.5.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 164Ch .................... 208
5.5.18 Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1650h..
209
5.5.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1654h .............. 210
5.5.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 16A4h ................................. 211
5.5.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset 16ACh ............... 212
5.5.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 16B0h.......... 213
5.5.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 16B4h .......................... 214
5.5.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 16BCh .................................... 215
5.5.25 Major Mode Control (D_CR_MMC)—Offset 1724h ...................................... 215
5.5.26 Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1728h
216
5.5.27 Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 172Ch
217
5.5.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1730h .......................... 218
5.5.29 Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1734h 219
5.5.30 Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1738h 219
5.5.31 Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 173Ch 220
5.5.32 Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1740h 221
5.5.33 Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1744h 222
5.5.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1748h ................................ 223
5.5.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 174Ch ............ 223
5.5.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1754h......... 225
5.5.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1780h ....... 226
5.5.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1784h .............. 227
5.6 Registers Summary ......................................................................................... 228
5.6.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1A00h .............................. 230
5.6.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1A08h ........................... 232
5.6.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 1A0Ch........................... 233
5.6.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1A10h ........................... 234
5.6.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1A14h ........................... 235

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 5.6.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1A18h ........................... 236
5.6.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 1A1Ch ........................... 237
5.6.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1A20h ........................... 239
5.6.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1A24h ........................... 240
5.6.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1A28h ........................... 241
5.6.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 1A2Ch .................... 242
5.6.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1A30h............ 243
5.6.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1A34h............ 245
5.6.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1A38h .................................. 247
5.6.15 D-Unit Scheduler (D_CR_DSCH)—Offset 1A3Ch ........................................ 249
5.6.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1A40h.............................. 251
5.6.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 1A4Ch .................... 252
5.6.18 Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1A50h .
253
5.6.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1A54h............... 254
5.6.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 1AA4h ................................. 255
5.6.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset 1AACh................ 256
5.6.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 1AB0h .......... 257
5.6.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 1AB4h .......................... 258
5.6.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 1ABCh .................................... 259
5.6.25 Major Mode Control (D_CR_MMC)—Offset 1B24h ...................................... 259
5.6.26 Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1B28h
260
5.6.27 Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 1B2Ch
261
5.6.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1B30h .......................... 262
5.6.29 Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1B34h 263
5.6.30 Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1B38h 263
5.6.31 Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 1B3Ch264
5.6.32 Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1B40h 265
5.6.33 Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1B44h 266
5.6.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1B48h................................. 267
5.6.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 1B4Ch ............ 267
5.6.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1B54h ......... 269
5.6.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1B80h ....... 270
5.6.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1B84h............... 271
5.7 Registers Summary.......................................................................................... 273
5.7.1 Thermal Device Mailbox Data0
(P_CR_THERMAL_MAILBOX_DATA0_0_0_0_MCHBAR)—Offset 7000h........... 275
5.7.2 Thermal Device Mailbox Data1
(P_CR_THERMAL_MAILBOX_DATA1_0_0_0_MCHBAR)—Offset 7004h........... 276
5.7.3 Thermal Device Mailbox Interface
(P_CR_THERMAL_MAILBOX_INTERFACE_0_0_0_MCHBAR)—Offset 7008h .... 277
5.7.4 Thermal Device IRQ and Lock Configuration
(P_CR_THERMAL_DEVICE_IRQ_0_0_0_MCHBAR)—Offset 700Ch ................. 278
5.7.5 Package Thermal Interrupt Control
(P_CR_PKG_THERM_INTERRUPT_0_0_0_MCHBAR)—Offset 7010h............... 279
5.7.6 ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR
(P_CR_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR)—Offset
7014h ................................................................................................. 280
5.7.7 Package Thermal Status (P_CR_PKG_THERM_STATUS_0_0_0_MCHBAR)—Offset
701Ch ................................................................................................. 281
5.7.8 LPDDR DRAM Thermal (MR4) Status of Channel 01
(P_CR_MEM_MR4_TEMPERATURE_DEV1_0_0_0_MCHBAR)—Offset 7024h .... 283
5.7.9 LPDDR DRAM Thermal (MR4) Status of Channel 10
(P_CR_MEM_MR4_TEMPERATURE_DEV2_0_0_0_MCHBAR)—Offset 7028h .... 283

6 334818
 5.7.10 Machine Check Error Source Log (P_CR_MCA_ERROR_SRC_0_0_0_MCHBAR)—
Offset 702Ch ....................................................................................... 284
5.7.11 DDR Thermal Throttling Control
(P_CR_DDR_THERM_THRT_CTRL_0_0_0_MCHBAR)—Offset 7030h ............. 285
5.7.12 DDR Thermal Interrupt Control
(P_CR_DDR_THERM_INTERRUPT_0_0_0_MCHBAR)—Offset 7034h .............. 286
5.7.13 DDR Thermal Status (P_CR_DDR_THERM_STATUS_0_0_0_MCHBAR)—Offset
7038h................................................................................................. 288
5.7.14 Dram Energy Counter (P_CR_DDR_ENERGY_STATUS_0_0_0_MCHBAR)—Offset
7048h................................................................................................. 289
5.7.15 DDR RAPL Performance Status
(P_CR_DDR_RAPL_PERF_STATUS_0_0_0_MCHBAR)—Offset 704Ch............. 290
5.7.16 Package RAPL Performance Status
(P_CR_PACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR)—Offset 7050h...... 291
5.7.17 IA Core Performance / Power Priority Control
(P_CR_PRIMARY_PLANE_TURBO_PLCY_0_0_0_MCHBAR)—Offset 7054h ...... 292
5.7.18 Graphics Performance / Power Priority Control
(P_CR_SECONDARY_PLANE_TURBO_PLCY_0_0_0_MCHBAR)—Offset 7058h . 292
5.7.19 IA Energy Counter
(P_CR_PRIMARY_PLANE_ENERGY_STATUS_0_0_0_MCHBAR)—Offset 705Ch 293
5.7.20 Graphics Energy Counter
(P_CR_SECONDARY_PLANE_ENERGY_STATUS_0_0_0_MCHBAR)—Offset 7060h .
294
5.7.21 PACKAGE_POWER_SKU_UNIT
(P_CR_PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR)—Offset 7068h........ 295
5.7.22 SOC Energy Counter (P_CR_PACKAGE_ENERGY_STATUS_0_0_0_MCHBAR)—
Offset 706Ch ....................................................................................... 296
5.7.23 GT_PERF_STATUS (P_CR_GT_PERF_STATUS_0_0_0_MCHBAR)—Offset 7070h....
296
5.7.24 Temperature Reference and Control
(P_CR_TEMPERATURE_TARGET_0_0_0_MCHBAR)—Offset 7074h ................ 297
5.7.25 BIOS Reset Completion (P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)—Offset
7078h................................................................................................. 298
5.7.26 BIOS_MAILBOX_DATA (P_CR_BIOS_MAILBOX_DATA_0_0_0_MCHBAR)—Offset
7080h................................................................................................. 301
5.7.27 BIOS_MAILBOX_INTERFACE
(P_CR_BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR)—Offset 7084h .......... 301
5.7.28 CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset 7088h . 302
5.7.29 GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset 708Ch
303
5.7.30 SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset
7090h................................................................................................. 304
5.7.31 Memory Frequency Status
(P_CR_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset
7094h................................................................................................. 305
5.7.32 Package Power SKU and RAPL Power Control Capabilities
(P_CR_PACKAGE_POWER_SKU_0_0_0_MCHBAR)—Offset 70A0h ................ 306
5.7.33 Package RAPL Power Limit (P_CR_PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR)—
Offset 70A8h ....................................................................................... 307
5.7.34 IA_PERF_LIMIT_REASONS
(P_CR_IA_PERF_LIMIT_REASONS_0_0_0_MCHBAR)—Offset 70B0h ............ 309
5.7.35 IA Core C0 Residency Counter
(P_CR_TELEM_IA_C0_RESIDENCY_0_0_0_MCHBAR)—Offset 70C0h............ 312

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 5.7.36 Graphics C0 Residency Counter
(P_CR_TELEM_GT_C0_RESIDENCY_0_0_0_MCHBAR)—Offset 70C4h ........... 313
5.7.37 I-unit Processing System C0 Residency Counter
(P_CR_TELEM_IUNIT_C0_RESIDENCY_0_0_0_MCHBAR)—Offset 70C8h ....... 313
5.7.38 TELEM_IA_FREQ_ACCUMULATOR
(P_CR_TELEM_IA_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—Offset 70CCh ... 314
5.7.39 Graphics C0 Residency Counter
(P_CR_TELEM_GT_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—Offset 70D0h .. 314
5.7.40 I-unit Processing System C0 Residency Counter
(P_CR_TELEM_IUNIT_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—Offset 70D4h ...
315
5.7.41 Memory Active Residency
(P_CR_TELEM_FAR_MEMORY_ACTIVE_0_0_0_MCHBAR)—Offset 70E8h ....... 315
5.7.42 Package Temperatures (P_CR_PACKAGE_TEMPERATURES_0_0_0_MCHBAR)—
Offset 70F4h ........................................................................................ 316
5.7.43 Package Thermal Limit Control
(P_CR_THERMAL_LIMIT_CONTROL_0_0_0_MCHBAR)—Offset 7104h ........... 317
5.7.44 Memory Subsystem Frequency Capabilities
(P_CR_MEMSS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset 7108h 318
5.7.45 Memory Controller (MC) BIOS Reset Request and Status
(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR)—Offset 7114h ............................. 319
5.7.46 MEMSS_FREQUENCY_CAPABILITIES1
(P_CR_MEMSS_FREQUENCY_CAPABILITIES1_0_0_0_MCHBAR)—Offset 7118h...
322
5.7.47 PP1_C0_CORE_CLOCK_0_0_0_MCHBAR
(P_CR_PP1_C0_CORE_CLOCK_0_0_0_MCHBAR)—Offset 7160h .................. 323
5.7.48 Core Exists Vector (P_CR_CORE_EXISTS_VECTOR_0_0_0_MCHBAR)—Offset
7164h ................................................................................................. 324
5.7.49 Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR)—
Offset 7168h ........................................................................................ 324
5.7.50 PL3 and PL4 Control (P_CR_PL3_CONTROL_0_0_0_MCHBAR)—Offset 71F0h. 326
5.7.51 Graphics Superqueue Active Clocks
(P_CR_PP1_ANY_THREAD_ACTIVITY_0_0_0_MCHBAR)—Offset 7244h ......... 327
5.7.52 LPDDR DRAM Thermal (MR4) Status of Channel 00
(P_CR_MEM_MR4_TEMPERATURE_DEV3_0_0_0_MCHBAR)—Offset 7248h .... 328
5.7.53 LPDDR DRAM Thermal (MR4) Status of Channel 11
(P_CR_MEM_MR4_TEMPERATURE_DEV4_0_0_0_MCHBAR)—Offset 724Ch .... 329
5.8 Registers Summary.......................................................................................... 329
5.8.1 Upstream Device Arbiter Grant Count A2T
(A_CR_UPARB_GCNT_DEV_A2T_MCHBAR)—Offset 6400h .......................... 332
5.8.2 Upstream A2B Arbiter Channel 0 Grant Count
(A_CR_UPARB_GCNT_A2B_0_MCHBAR)—Offset 6404h .............................. 333
5.8.3 Upstream A2B Arbiter Channel 1 Grant Count
(A_CR_UPARB_GCNT_A2B_1_MCHBAR)—Offset 6408h .............................. 334
5.8.4 Upstream A2B Arbiter Channel 2 Grant Count
(A_CR_UPARB_GCNT_A2B_2_MCHBAR)—Offset 640Ch .............................. 335
5.8.5 Upstream A2B Arbiter Channel 3 Grant Count
(A_CR_UPARB_GCNT_A2B_3_MCHBAR)—Offset 6410h .............................. 336
5.8.6 Upstream A2B Arbiter Channel 4 Grant Count
(A_CR_UPARB_GCNT_A2B_4_MCHBAR)—Offset 6414h .............................. 337
5.8.7 Upstream A2B Arbiter Channel 5 Grant Count
(A_CR_UPARB_GCNT_A2B_5_MCHBAR)—Offset 6418h .............................. 338
5.8.8 Upstream A2B Arbiter Channel 6 Grant Count
(A_CR_UPARB_GCNT_A2B_6_MCHBAR)—Offset 641Ch .............................. 338
5.8.9 Upstream A2B Arbiter Channel 7 Grant Count
(A_CR_UPARB_GCNT_A2B_7_MCHBAR)—Offset 6420h .............................. 339

8 334818
 5.8.10 Upstream A2T Arbiter Channel 0 Grant Count
(A_CR_UPARB_GCNT_A2T_0_MCHBAR)—Offset 6424h .............................. 340
5.8.11 Upstream P2P Arbiter Channel 0 Grant Count
(A_CR_UPARB_GCNT_P2P_0_MCHBAR)—Offset 6428h .............................. 341
5.8.12 Upstream P2P Arbiter Channel 1 Grant Count
(A_CR_UPARB_GCNT_P2P_1_MCHBAR)—Offset 642Ch .............................. 342
5.8.13 Upstream Private Credit Return Grant Count Posted 0
(A_CR_CRDARB_PRIV_GCNT_DEV_P_0_MCHBAR)—Offset 6430h ............... 343
5.8.14 Upstream Private Credit Return Grant Count Posted 1
(A_CR_CRDARB_PRIV_GCNT_DEV_P_1_MCHBAR)—Offset 6434h ............... 343
5.8.15 Upstream Private Credit Return Grant Count Non-posted 0
(A_CR_CRDARB_PRIV_GCNT_DEV_N_0_MCHBAR)—Offset 6438h ............... 344
5.8.16 Upstream Private Credit Return Grant Count Posted 1
(A_CR_CRDARB_PRIV_GCNT_DEV_N_1_MCHBAR)—Offset 643Ch............... 345
5.8.17 Upstream Private Credit Return Grant Count Completion
(A_CR_CRDARB_PRIV_GCNT_DEV_C_0_MCHBAR)—Offset 6440h ............... 346
5.8.18 Upstream Shared Credit Return Grant Count Posted 0
(A_CR_CRDARB_SHRD_GCNT_DEV_P_0_MCHBAR)—Offset 6444h .............. 347
5.8.19 Upstream Shared Credit Return Grant Count Posted 1
(A_CR_CRDARB_SHRD_GCNT_DEV_P_1_MCHBAR)—Offset 6448h .............. 348
5.8.20 Upstream Shared Credit Return Grant Count Non-posted 0
(A_CR_CRDARB_SHRD_GCNT_DEV_N_0_MCHBAR)—Offset 644Ch ............. 348
5.8.21 Upstream Shared Credit Return Grant Count Posted 1
(A_CR_CRDARB_SHRD_GCNT_DEV_N_1_MCHBAR)—Offset 6450h.............. 349
5.8.22 Upstream Shared Credit Return Grant Count Completion
(A_CR_CRDARB_SHRD_GCNT_DEV_C_0_MCHBAR)—Offset 6454h.............. 350
5.8.23 Upstream Credit Arbiter Private Credit Return Class Arbiter Grant Count
(A_CR_CRDARB_PRIV_GCNT_CLS_MCHBAR)—Offset 6458h....................... 351
5.8.24 Upstream Credit Arbiter Shared Cedit Return Class Arbiter Grant Count
(A_CR_CRDARB_SHRD_GCNT_CLS_MCHBAR)—Offset 645Ch ..................... 351
5.8.25 Gazelle Queue Limit Channel 0-3 (A_CR_GZLQ_LIMIT_CH0_3_MCHBAR)—Offset
6460h................................................................................................. 352
5.8.26 Gazelle Queue Limit Channels 4-7 (A_CR_GZLQ_LIMIT_CH4_7_MCHBAR)—Offset
6464h................................................................................................. 353
5.8.27 IOMMU Arbiter Grant Count VC0a Register
(A_CR_IOMMUARB_GCNT_VC0a_0_0_0_MCHBAR)—Offset 6468h............... 353
5.8.28 IOMMU Arbiter Grant Count VC0b Register
(A_CR_IOMMUARB_GCNT_VC0b_0_0_0_MCHBAR)—Offset 646Ch .............. 354
5.8.29 IOMMU Arbiter Grant Count VC1b Register
(A_CR_IOMMUARB_GCNT_VC1b_0_0_0_MCHBAR)—Offset 6470h............... 355
5.8.30 Gazelle Queue Reserved Entries Channels 0-3
(A_CR_GZLQ_RSVD_CH0_3_MCHBAR)—Offset 6474h ............................... 356
5.8.31 Gazelle Queue Reserved Entries Channels 4-7
(A_CR_GZLQ_RSVD_CH4_7_MCHBAR)—Offset 6478h ............................... 356
5.8.32 Spare BIOS (A_CR_SPARE_BIOS_MCHBAR)—Offset 647Ch ........................ 357
5.8.33 Upcmd Credit Maximum Channel 0
(A_CR_UPCMD_CRDTMAX_CH0_0_0_0_MCHBAR)—Offset 6490h ................ 357
5.8.34 Upcmd Credit Maximum Channel 1
(A_CR_UPCMD_CRDTMAX_CH1_0_0_0_MCHBAR)—Offset 6494h ................ 358
5.8.35 Upcmd Credit Maximum Channel 2
(A_CR_UPCMD_CRDTMAX_CH2_0_0_0_MCHBAR)—Offset 6498h ................ 359
5.8.36 Upcmd Credit Maximum Channel 3
(A_CR_UPCMD_CRDTMAX_CH3_0_0_0_MCHBAR)—Offset 649Ch................ 360
5.8.37 Upcmd Credit Maximum Channel 4
(A_CR_UPCMD_CRDTMAX_CH4_0_0_0_MCHBAR)—Offset 64A0h................ 360
5.8.38 Upcmd Credit Maximum Channel 5
(A_CR_UPCMD_CRDTMAX_CH5_0_0_0_MCHBAR)—Offset 64A4h................ 361

334818 9
 5.8.39 Upcmd Credit Maximum Channel 6
(A_CR_UPCMD_CRDTMAX_CH6_0_0_0_MCHBAR)—Offset 64A8h ................ 362
5.8.40 Upcmd Credit Maximum Channel 7
(A_CR_UPCMD_CRDTMAX_CH7_0_0_0_MCHBAR)—Offset 64ACh ................ 362
5.8.41 MOT OUT Base Register (A_CR_MOT_OUT_BASE_0_0_0_MCHBAR)—Offset
64C0h ................................................................................................. 363
5.8.42 MOT OUT Mask Register (A_CR_MOT_OUT_MASK_0_0_0_MCHBAR)—Offset
64C4h ................................................................................................. 364
5.8.43 CHAP Select 1 (A_CR_CHAP_SLCT1_MCHBAR)—Offset 6500h ..................... 365
5.8.44 CHAP Select 2 (A_CR_CHAP_SLCT2_MCHBAR)—Offset 6504h ..................... 366
5.8.45 CHAP Select 3 (A_CR_CHAP_SLCT3_MCHBAR)—Offset 6508h ..................... 367
5.8.46 Slice and Channel Hash (A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR)—
Offset 65C0h........................................................................................ 367
5.8.47 Mirror Range Register (A_CR_MIRROR_RANGE_0_0_0_MCHBAR)—Offset 65C8h
370
5.8.48 ASYM MEM REGION 0 CONFIGURATION WITH NO INTERLEAVING
(A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR)—Offset 65D0h .................. 371
5.8.49 ASYM MEM REGION 1 CONFIGURATION WITH NO INTERLEAVING
(A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR)—Offset 65D4h .................. 372
5.8.50 Two-Way Asymmetric Memory Region Configuration
(A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR)—Offset 65D8h .......... 373
5.9 Registers Summary.......................................................................................... 374
5.9.1 B-Unit Miscellaneous Configuration (B_CR_BMISC_0_0_0_MCHBAR)—Offset
6800h ................................................................................................. 383
5.9.2 Slice 0 Memory Access Count (B_CR_MEM_ACCESS_COUNT_SLICE0)—Offset
6868h ................................................................................................. 384
5.9.3 Slice 1 Memory Access Count (B_CR_MEM_ACCESS_COUNT_SLICE1)—Offset
686Ch ................................................................................................. 384
5.9.4 IMR0 Mask (B_CR_BIMR0MASK_0_0_0_MCHBAR)—Offset 6874h ................ 385
5.9.5 IMR0 Control Policy (B_CR_BIMR0CP_0_0_0_MCHBAR)—Offset 6878h......... 386
5.9.6 IMR0 Read Access Policy (B_CR_BIMR0RAC_0_0_0_MCHBAR)—Offset 6880h 387
5.9.7 IMR0 Write Access Policy (B_CR_BIMR0WAC_0_0_0_MCHBAR)—Offset 6888h ...
392
5.9.8 IMR1 Base (B_CR_BIMR1BASE_0_0_0_MCHBAR)—Offset 6890h ................. 396
5.9.9 IMR1 Mask (B_CR_BIMR1MASK_0_0_0_MCHBAR)—Offset 6894h ................ 397
5.9.10 IMR1 Control Policy (B_CR_BIMR1CP_0_0_0_MCHBAR)—Offset 6898h......... 398
5.9.11 IMR1 Read Access Policy (B_CR_BIMR1RAC_0_0_0_MCHBAR)—Offset 68A0h399
5.9.12 IMR1 Write Access Policy (B_CR_BIMR1WAC_0_0_0_MCHBAR)—Offset 68A8h ...
404
5.9.13 Base 0 IMR2 Base (B_CR_BIMR2BASE_0_0_0_MCHBAR)—Offset 68B0h....... 409
5.9.14 IMR2 Mask (B_CR_BIMR2MASK_0_0_0_MCHBAR)—Offset 68B4h ................ 409
5.9.15 IMR2 Control Policy (B_CR_BIMR2CP_0_0_0_MCHBAR)—Offset 68B8h......... 410
5.9.16 IMR2 Read Access Policy (B_CR_BIMR2RAC_0_0_0_MCHBAR)—Offset 68C0h411
5.9.17 IMR2 Write Access Policy (B_CR_BIMR2WAC_0_0_0_MCHBAR)—Offset 68C8h ...
416
5.9.18 IMR3 Base (B_CR_BIMR3BASE_0_0_0_MCHBAR)—Offset 68D0h................. 421
5.9.19 IMR3 Mask (B_CR_BIMR3MASK_0_0_0_MCHBAR)—Offset 68D4h................ 422
5.9.20 IMR3 Control Policy (B_CR_BIMR3CP_0_0_0_MCHBAR)—Offset 68D8h ........ 423
5.9.21 IMR3 Read Access Policy (B_CR_BIMR3RAC_0_0_0_MCHBAR)—Offset 68E0h 423
5.9.22 IMR3 Write Access Policy (B_CR_BIMR3WAC_0_0_0_MCHBAR)—Offset 68E8h ...
428
5.9.23 IMR4 Base (B_CR_BIMR4BASE_0_0_0_MCHBAR)—Offset 68F0h ................. 433
5.9.24 IMR4 Mask (B_CR_BIMR4MASK_0_0_0_MCHBAR)—Offset 68F4h ................ 434
5.9.25 B-Unit IMR4 Control Policy (B_CR_BIMR4CP_0_0_0_MCHBAR)—Offset 68F8h435
5.9.26 IMR4 Read Access Policy (B_CR_BIMR4RAC_0_0_0_MCHBAR)—Offset 6900h 435

10 334818
 5.9.27 IMR4 Write Access Policy (B_CR_BIMR4WAC_0_0_0_MCHBAR)—Offset 6908h....
440
5.9.28 IMR5 Base (B_CR_BIMR5BASE_0_0_0_MCHBAR)—Offset 6910h................. 447
5.9.29 IMR5 Mask (B_CR_BIMR5MASK_0_0_0_MCHBAR)—Offset 6914h................ 447
5.9.30 IMR5 Control Policy (B_CR_BIMR5CP_0_0_0_MCHBAR)—Offset 6918h ........ 448
5.9.31 IMR5 Read Access Policy (B_CR_BIMR5RAC_0_0_0_MCHBAR)—Offset 6920h 449
5.9.32 IMR5 Write Access Policy (B_CR_BIMR5WAC_0_0_0_MCHBAR)—Offset 6928h....
454
5.9.33 IMR6 Base (B_CR_BIMR6BASE_0_0_0_MCHBAR)—Offset 6930h................. 459
5.9.34 IMR6 Mask (B_CR_BIMR6MASK_0_0_0_MCHBAR)—Offset 6934h................ 460
5.9.35 IMR6 Control Policy (B_CR_BIMR6CP_0_0_0_MCHBAR)—Offset 6938h ........ 461
5.9.36 IMR6 Read Access Policy (B_CR_BIMR6RAC_0_0_0_MCHBAR)—Offset 6940h 461
5.9.37 IMR6 Write Access Policy (B_CR_BIMR6WAC_0_0_0_MCHBAR)—Offset 6948h....
466
5.9.38 IMR7 Base (B_CR_BIMR7BASE_0_0_0_MCHBAR)—Offset 6950h................. 471
5.9.39 IMR7 Mask (B_CR_BIMR7MASK_0_0_0_MCHBAR)—Offset 6954h................ 472
5.9.40 IMR7 Control Policy (B_CR_BIMR7CP_0_0_0_MCHBAR)—Offset 6958h ........ 473
5.9.41 IMR7 Read Access Policy (B_CR_BIMR7RAC_0_0_0_MCHBAR)—Offset 6960h 473
5.9.42 IMR7 Write Access Policy (B_CR_BIMR7WAC_0_0_0_MCHBAR)—Offset 6968h....
478
5.9.43 IMR8 Base (B_CR_BIMR8BASE_0_0_0_MCHBAR)—Offset 6970h................. 483
5.9.44 IMR8 Mask (B_CR_BIMR8MASK_0_0_0_MCHBAR)—Offset 6974h................ 484
5.9.45 IMR8 Control Policy (B_CR_BIMR8CP_0_0_0_MCHBAR)—Offset 6978h ........ 485
5.9.46 IMR8 Read Access Policy (B_CR_BIMR8RAC_0_0_0_MCHBAR)—Offset 6980h 486
5.9.47 IMR8 Write Access Policy (B_CR_BIMR8WAC_0_0_0_MCHBAR)—Offset 6988h....
490
5.9.48 IMR9 Base (B_CR_BIMR9BASE_0_0_0_MCHBAR)—Offset 6990h................. 495
5.9.49 IMR9 Mask (B_CR_BIMR9MASK_0_0_0_MCHBAR)—Offset 6994h................ 496
5.9.50 IMR9 Control Policy (B_CR_BIMR9CP_0_0_0_MCHBAR)—Offset 6998h ........ 497
5.9.51 IMR9 Read Access Policy (B_CR_BIMR9RAC_0_0_0_MCHBAR)—Offset 69A0h498
5.9.52 IMR9 Write Access Policy (B_CR_BIMR9WAC_0_0_0_MCHBAR)—Offset 69A8h....
503
5.9.53 IMR10 Base (B_CR_BIMR10BASE_0_0_0_MCHBAR)—Offset 69B0h ............. 507
5.9.54 IMR10 Mask (B_CR_BIMR10MASK_0_0_0_MCHBAR)—Offset 69B4h ............ 508
5.9.55 IMR10 Control Policy (B_CR_BIMR10CP_0_0_0_MCHBAR)—Offset 69B8h..... 509
5.9.56 IMR10 Read Access Policy (B_CR_BIMR10RAC_0_0_0_MCHBAR)—Offset 69C0h .
510
5.9.57 IMR10 Write Access Policy (B_CR_BIMR10WAC_0_0_0_MCHBAR)—Offset 69C8h
515
5.9.58 IMR11 Base (B_CR_BIMR11BASE_0_0_0_MCHBAR)—Offset 69D0h ............. 520
5.9.59 IMR11 Mask (B_CR_BIMR11MASK_0_0_0_MCHBAR)—Offset 69D4h ............ 520
5.9.60 IMR11 Control Policy (B_CR_BIMR11CP_0_0_0_MCHBAR)—Offset 69D8h .... 521
5.9.61 IMR11 Read Access Policy (B_CR_BIMR11RAC_0_0_0_MCHBAR)—Offset 69E0h .
522
5.9.62 IMR11 Write Access Policy (B_CR_BIMR11WAC_0_0_0_MCHBAR)—Offset 69E8h
527
5.9.63 IMR12 Base (B_CR_BIMR12BASE_0_0_0_MCHBAR)—Offset 69F0h ............. 532
5.9.64 IMR12 Mask (B_CR_BIMR12MASK_0_0_0_MCHBAR)—Offset 69F4h ............ 533
5.9.65 IMR12 Control Policy (B_CR_BIMR12CP_0_0_0_MCHBAR)—Offset 69F8h ..... 534
5.9.66 IMR12 Read Access Policy (B_CR_BIMR12RAC_0_0_0_MCHBAR)—Offset 6A00h .
534
5.9.67 IMR12 Write Access Policy (B_CR_BIMR12WAC_0_0_0_MCHBAR)—Offset 6A08h
539
5.9.68 IMR13 Base (B_CR_BIMR13BASE_0_0_0_MCHBAR)—Offset 6A10h ............. 544
5.9.69 IMR13 Mask (B_CR_BIMR13MASK_0_0_0_MCHBAR)—Offset 6A14h ............ 545
5.9.70 IMR13 Control Policy (B_CR_BIMR13CP_0_0_0_MCHBAR)—Offset 6A18h..... 546

334818 11
 5.9.71 IMR13 Read Access Policy (B_CR_BIMR13RAC_0_0_0_MCHBAR)—Offset 6A20h .
547
5.9.72 IMR13 Write Access Policy (B_CR_BIMR13WAC_0_0_0_MCHBAR)—Offset 6A28h
551
5.9.73 IMR14 Base (B_CR_BIMR14BASE_0_0_0_MCHBAR)—Offset 6A30h ............. 556
5.9.74 IMR14 Mask (B_CR_BIMR14MASK_0_0_0_MCHBAR)—Offset 6A34h ............ 557
5.9.75 IMR14 Control Policy (B_CR_BIMR14CP_0_0_0_MCHBAR)—Offset 6A38h ..... 558
5.9.76 IMR14 Read Access Policy (B_CR_BIMR14RAC_0_0_0_MCHBAR)—Offset 6A40h .
559
5.9.77 IMR14 Write Access Policy (B_CR_BIMR14WAC_0_0_0_MCHBAR)—Offset 6A48h
564
5.9.78 IMR15 Base (B_CR_BIMR15BASE_0_0_0_MCHBAR)—Offset 6A50h ............. 568
5.9.79 IMR15 Mask (B_CR_BIMR15MASK_0_0_0_MCHBAR)—Offset 6A54h ............ 569
5.9.80 IMR15 Control Policy (B_CR_BIMR15CP_0_0_0_MCHBAR)—Offset 6A58h ..... 570
5.9.81 IMR15 Read Access Policy (B_CR_BIMR15RAC_0_0_0_MCHBAR)—Offset 6A60h .
571
5.9.82 IMR15 Write Access Policy (B_CR_BIMR15WAC_0_0_0_MCHBAR)—Offset 6A68h
576
5.9.83 IMR16 Base (B_CR_BIMR16BASE_0_0_0_MCHBAR)—Offset 6A70h ............. 581
5.9.84 IMR16 Mask (B_CR_BIMR16MASK_0_0_0_MCHBAR)—Offset 6A74h ............ 581
5.9.85 IMR16 Control Policy (B_CR_BIMR16CP_0_0_0_MCHBAR)—Offset 6A78h ..... 582
5.9.86 IMR16 Read Access Policy (B_CR_BIMR16RAC_0_0_0_MCHBAR)—Offset 6A80h .
583
5.9.87 IMR16 Write Access Policy (B_CR_BIMR16WAC_0_0_0_MCHBAR)—Offset 6A88h
588
5.9.88 IMR17 Base (B_CR_BIMR17BASE_0_0_0_MCHBAR)—Offset 6A90h ............. 593
5.9.89 IMR17 Mask (B_CR_BIMR17MASK_0_0_0_MCHBAR)—Offset 6A94h ............ 594
5.9.90 IMR17 Control Policy (B_CR_BIMR17CP_0_0_0_MCHBAR)—Offset 6A98h ..... 595
5.9.91 IMR17 Read Access Policy (B_CR_BIMR17RAC_0_0_0_MCHBAR)—Offset 6AA0h.
595
5.9.92 IMR17 Write Access Policy (B_CR_BIMR17WAC_0_0_0_MCHBAR)—Offset 6AA8h
600
5.9.93 IMR18 Base (B_CR_BIMR18BASE_0_0_0_MCHBAR)—Offset 6AB0h ............. 605
5.9.94 IMR18 Mask (B_CR_BIMR18MASK_0_0_0_MCHBAR)—Offset 6AB4h ............ 606
5.9.95 IMR18 Control Policy (B_CR_BIMR18CP_0_0_0_MCHBAR)—Offset 6AB8h ..... 607
5.9.96 IMR18 Read Access Policy (B_CR_BIMR18RAC_0_0_0_MCHBAR)—Offset 6AC0h.
608
5.9.97 IMR18 Write Access Policy (B_CR_BIMR18WAC_0_0_0_MCHBAR)—Offset 6AC8h
612
5.9.98 IMR19 Base (B_CR_BIMR19BASE_0_0_0_MCHBAR)—Offset 6AD0h ............. 619
5.9.99 IMR19 Mask (B_CR_BIMR19MASK_0_0_0_MCHBAR)—Offset 6AD4h ............ 620
5.9.100IMR19 Control Policy (B_CR_BIMR19CP_0_0_0_MCHBAR)—Offset 6AD8h..... 621
5.9.101IMR19 Read Access Policy (B_CR_BIMR19RAC_0_0_0_MCHBAR)—Offset 6AE0h .
622
5.9.102IMR19 Write Access Policy (B_CR_BIMR19WAC_0_0_0_MCHBAR)—Offset 6AE8h
626
5.9.103MOT Out Base (B_CR_MOT_OUT_BASE_0_0_0_MCHBAR)—Offset 6AF0h...... 631
5.9.104MOT Out Mask (B_CR_MOT_OUT_MASK_0_0_0_MCHBAR)—Offset 6AF4h..... 632
5.9.105MOT Buffer Control Policy (B_CR_BMOT_BUF_CP_0_0_0_MCHBAR)—Offset
6AF8h ................................................................................................. 633
5.9.106MOT Buffer Read Access Policy (B_CR_BMOT_BUF_RAC_0_0_0_MCHBAR)—Offset
6B00h ................................................................................................. 634
5.9.107MOT Buffer Write Access Policy (B_CR_BMOT_BUF_WAC_0_0_0_MCHBAR)—
Offset 6B08h........................................................................................ 639
5.9.108IMR Global BM Control Policy (B_CR_BIMRGLOBAL_BM_CP_0_0_0_MCHBAR)—
Offset 6B10h........................................................................................ 645

12 334818
 5.9.109IMR Global BM Read Access Control
(B_CR_BIMRGLOBAL_BM_RAC_0_0_0_MCHBAR)—Offset 6B18h ................. 646
5.9.110IMR Global BM Write Access Policy
(B_CR_BIMRGLOBAL_BM_WAC_0_0_0_MCHBAR)—Offset 6B20h ................ 646
5.9.111Graphics Stolen Memory Control Policy (B_CR_BGSMCP_0_0_0_MCHBAR)—
Offset 6B28h ....................................................................................... 647
5.9.112GSM Read Access Policy (B_CR_BGSMRAC_0_0_0_MCHBAR)—Offset 6B30h 648
5.9.113GSM Write Access Policy (B_CR_BGSMWAC_0_0_0_MCHBAR)—Offset 6B38h 654
5.9.114TPM Control Policy (B_CR_TPM_CP_0_0_0_MCHBAR)—Offset 6B40h ........... 660
5.9.115TPM Access Control (B_CR_TPM_AC_0_0_0_MCHBAR)—Offset 6B48h.......... 661
5.9.116BGSM Control Register (B_CR_BGSM_CTRL_0_0_0_MCHBAR)—Offset 6B50h 661
5.9.117SMM Control Register (B_CR_BSMR_CTRL_0_0_0_MCHBAR)—Offset 6B54h . 662
5.9.118Default VTd Control Register (B_CR_BDEFVTDPMR_CTRL_0_0_0_MCHBAR)—
Offset 6B58h ....................................................................................... 663
5.9.119MOT Trigger Trace Control (B_CR_MOT_TRIG_TRACE_CTRL_0_0_0_MCHBAR)—
Offset 6B7Ch ....................................................................................... 664
5.9.120MOT Slice 0 Memory Pointer
(B_CR_MOT_SLICE_0_MEM_PTR_0_0_0_MCHBAR)—Offset 6B80h .............. 667
5.9.121MOT Slice 1 Memory Pointer
(B_CR_MOT_SLICE_1_MEM_PTR_0_0_0_MCHBAR)—Offset 6B88h .............. 668
5.9.122MOT Slice 0 Record ID (B_CR_MOT_SLICE_0_RECORD_ID_0_0_0_MCHBAR)—
Offset 6B90h ....................................................................................... 669
5.9.123MOT Slice 1 Record ID (B_CR_MOT_SLICE_1_RECORD_ID_0_0_0_MCHBAR)—
Offset 6B94h ....................................................................................... 669
5.9.124MOT Filter Match 0 (B_CR_MOT_FILTER_MATCH0_0_0_0_MCHBAR)—Offset
6BA0h ................................................................................................ 670
5.9.125MOT Filter Mask (B_CR_MOT_FILTER_MASK0_0_0_0_MCHBAR)—Offset 6BA8h ..
671
5.9.126MOT Filter Match 1 (B_CR_MOT_FILTER_MATCH1_0_0_0_MCHBAR)—Offset
6BB0h ................................................................................................ 672
5.9.127MOT Filter Mask 1 (B_CR_MOT_FILTER_MASK1_0_0_0_MCHBAR)—Offset 6BB8h
672
5.9.128MOT Filter Misc 0 (B_CR_MOT_FILTER_MISC0_0_0_0_MCHBAR)—Offset 6BC0h .
673
5.9.129MOT Filter Misc 1 (B_CR_MOT_FILTER_MISC1_0_0_0_MCHBAR)—Offset 6BC8h .
674
5.9.130MOT Trigger Match 0 (B_CR_MOT_TRIGGER_MATCH0_0_0_0_MCHBAR)—Offset
6BD0h ................................................................................................ 675
5.9.131MOT Trigger Mask 0 (B_CR_MOT_TRIGGER_MASK0_0_0_0_MCHBAR)—Offset
6BD8h ................................................................................................ 676
5.9.132MOT Trigger Match 1 (B_CR_MOT_TRIGGER_MATCH1_0_0_0_MCHBAR)—Offset
6BE0h ................................................................................................ 677
5.9.133MOT Trigger Mask 1 (B_CR_MOT_TRIGGER_MASK1_0_0_0_MCHBAR)—Offset
6BE8h ................................................................................................ 678
5.9.134MOT Trigger Misc 0 (B_CR_MOT_TRIGGER_MISC0_0_0_0_MCHBAR)—Offset
6BF0h................................................................................................. 679
5.9.135MOT Trigger Misc 1 (B_CR_MOT_TRIGGER_MISC1_0_0_0_MCHBAR)—Offset
6BF8h................................................................................................. 680
5.9.136BIOSWR Control Policy (B_CR_BIOSWR_CP_0_0_0_MCHBAR)—Offset 6C08h 681
5.9.137BIOSWR Read Access Policy (B_CR_BIOSWR_RAC_0_0_0_MCHBAR)—Offset
6C10h ................................................................................................ 681
5.9.138BIOSWR Write Access Policy (B_CR_BIOSWR_WAC_0_0_0_MCHBAR)—Offset
6C18h ................................................................................................ 682
5.9.139TPM Selector (B_CR_TPM_SELECTOR_0_0_0_MCHBAR)—Offset 6C24h........ 682
5.9.140B-Unit Pcode/Ucode Write, All Read Control Policy Register
(B_CR_P_U_CODEWR_ALLRD_CP_0_0_0_MCHBAR)—Offset 6C28h ............. 683

334818 13
 5.9.141B-Unit Pcode/Ucode Read Access Policy
(B_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCHBAR)—Offset 6C30h ........... 684
5.9.142B-Unit Pcode/Ucode Write Access Policy
(B_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_MCHBAR)—Offset 6C38h .......... 684
5.9.143Default VTd BAR (B_CR_DEFVTDBAR_0_0_0_MCHBAR)—Offset 6C80h ........ 685
5.9.144Gfx VTd BAR (B_CR_GFXVTDBAR_0_0_0_MCHBAR)—Offset 6C88h ............. 686
5.9.145B-Unit Lites Group 0 Control (B_CR_LITES0_CTL_0_0_0_MCHBAR)—Offset
6C90h ................................................................................................. 687
5.9.146B-Unit Lites Group 0 Opcode Match Filter
(B_CR_LITES0_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6C94h .............. 689
5.9.147B-Unit Lites Group 0 Agent Match Filter
(B_CR_LITES0_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6C98h ................ 691
5.9.148B-Unit Lites Group 0 U2C IntData Match Filter
(B_CR_LITES0_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6C9Ch........ 693
5.9.149B-Unit Lites Group 0 Address Match Filter LITES0_ADDR_MATCH
(B_CR_LITES0_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6CA0h.................. 693
5.9.150B-Unit Lites Group 0 Address Mask Filter LITES0_ADDR_MASK
(B_CR_LITES0_ADDR_MASK_0_0_0_MCHBAR)—Offset 6CA8h.................... 694
5.9.151B-Unit Lites Group 0 Data Match Filter LITES0_DATA_MATCH
(B_CR_LITES0_DATA_MATCH_0_0_0_MCHBAR)—Offset 6CB0h .................. 695
5.9.152B-Unit Lites Group 0 Data Mask Filter LITES0_DATA_MASK
(B_CR_LITES0_DATA_MASK_0_0_0_MCHBAR)—Offset 6CB4h .................... 695
5.9.153B-Unit Lites Group 1 Control (B_CR_LITES1_CTL_0_0_0_MCHBAR)—Offset
6CC0h................................................................................................. 696
5.9.154B-Unit Lites Group 1 Opcode Match Filter
(B_CR_LITES1_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6CC4h .............. 698
5.9.155B-Unit Lites Group 1 Agent Match Filter
(B_CR_LITES1_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6CC8h ................ 700
5.9.156B-Unit Lites Group 1 U2C IntData Match Filter
(B_CR_LITES1_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6CCCh ....... 702
5.9.157B-Unit Lites Group 1 Address Match Filter LITES1_ADDR_MATCH
(B_CR_LITES1_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6CD0h ................. 702
5.9.158B-Unit Lites Group 1 Address Mask Filter LITES1_ADDR_MASK
(B_CR_LITES1_ADDR_MASK_0_0_0_MCHBAR)—Offset 6CD8h ................... 703
5.9.159B-Unit Lites Group 1 Data Match Filter LITES1_DATA_MATCH
(B_CR_LITES1_DATA_MATCH_0_0_0_MCHBAR)—Offset 6CE0h .................. 704
5.9.160B-Unit Lites Group 1 Data Mask Filter LITES1_DATA_MASK
(B_CR_LITES1_DATA_MASK_0_0_0_MCHBAR)—Offset 6CE4h .................... 704
5.9.161B-Unit Lites Group 2 Control (B_CR_LITES2_CTL_0_0_0_MCHBAR)—Offset
6CF0h ................................................................................................. 705
5.9.162B-Unit Lites Group 2 Opcode Match Filter
(B_CR_LITES2_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6CF4h .............. 707
5.9.163B-Unit Lites Group 2 Agent Match Filter
(B_CR_LITES2_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6CF8h................. 709
5.9.164B-Unit Lites Group 2 U2C IntData Match Filter
(B_CR_LITES2_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6CFCh........ 711
5.9.165B-Unit Lites Group 2 Address Match Filter LITES2_ADDR_MATCH
(B_CR_LITES2_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6D00h.................. 711
5.9.166B-Unit Lites Group 2 Address Mask Filter LITES2_ADDR_MASK
(B_CR_LITES2_ADDR_MASK_0_0_0_MCHBAR)—Offset 6D08h.................... 712
5.9.167B-Unit Lites Group 2 Data Match Filter LITES2_DATA_MATCH
(B_CR_LITES2_DATA_MATCH_0_0_0_MCHBAR)—Offset 6D10h .................. 713
5.9.168B-Unit Lites Group 2 Data Mask Filter LITES2_DATA_MASK
(B_CR_LITES2_DATA_MASK_0_0_0_MCHBAR)—Offset 6D14h .................... 713
5.9.169B-Unit Lites Group 3 Control (B_CR_LITES3_CTL_0_0_0_MCHBAR)—Offset
6D20h................................................................................................. 714

14 334818
 5.9.170B-Unit Lites Group 3 Opcode Match Filter
(B_CR_LITES3_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6D24h ............. 716
5.9.171B-Unit Lites Group 3 Agent Match Filter
(B_CR_LITES3_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6D28h................ 718
5.9.172B-Unit Lites Group 3 U2C IntData Match Filter
(B_CR_LITES3_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6D2Ch ....... 720
5.9.173B-Unit Lites Group 3 Address Match Filter LITES3_ADDR_MATCH
(B_CR_LITES3_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6D30h ................. 720
5.9.174B-Unit Lites Group 3 Address Mask Filter LITES3_ADDR_MASK
(B_CR_LITES3_ADDR_MASK_0_0_0_MCHBAR)—Offset 6D38h ................... 721
5.9.175B-Unit Lites Group 3 Data Match Filter LITES3_DATA_MATCH
(B_CR_LITES3_DATA_MATCH_0_0_0_MCHBAR)—Offset 6D40h.................. 722
5.9.176B-Unit Lites Group 3 Data Mask Filter LITES3_DATA_MASK
(B_CR_LITES3_DATA_MASK_0_0_0_MCHBAR)—Offset 6D44h.................... 722
5.9.177B-Unit Lites and Emon Master Control LITESEMONCTL
(B_CR_LITESEMON_CTL_0_0_0_MCHBAR)—Offset 6D48h ......................... 723
5.9.178B-Unit Arbiter Control BARBCTRL0 (B_CR_BARBCTRL0)—Offset 6D4Ch........ 725
5.9.179B-Unit Arbiter Control BARBCTRL1 (B_CR_BARBCTRL1)—Offset 6D50h ........ 726
5.9.180B-Unit Scheduler Control (B_CR_BSCHWT0)—Offset 6D54h ....................... 727
5.9.181B-Unit Scheduler Control (B_CR_BSCHWT1)—Offset 6D58h ....................... 727
5.9.182B-Unit Scheduler Control (B_CR_BSCHWT2)—Offset 6D5Ch ....................... 728
5.9.183B-Unit Scheduler Control (B_CR_BSCHWT3)—Offset 6D60h ....................... 729
5.9.184B-Unit Flush Control (B_CR_BWFLUSH)—Offset 6D64h .............................. 730
5.9.185B-Unit Flush Weights (B_CR_BFLWT)—Offset 6D68h ................................. 731
5.9.186Weighted Scheduling Control of High Priority ISOC and Other Requests
(B_CR_BISOCWT)—Offset 6D6Ch ........................................................... 732
5.9.187B-Unit Control (B_CR_BCTRL2)—Offset 6D70h ......................................... 733
5.9.188Asset Classification Bits (B_CR_AC_RS0_0_0_0_MCHBAR)—Offset 6D74h .... 735
5.9.189IDI Real-Time Feature Configuration Bits (B_CR_RT_EN_0_0_0_MCHBAR)—
Offset 6D78h ....................................................................................... 735
5.9.190B-Unit Control Register 3 (B_CR_BCTRL3)—Offset 6D7Ch .......................... 736
5.9.191Asymmetric Memory Region 0 With No Interleaving Configuration
(B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR)—Offset 6E40h .................. 737
5.9.192Asymmetric Memory Region 1 With No Interleaving Configuration
(B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR)—Offset 6E44h .................. 738
5.9.193B-Unit Machine Check Mode Low (B_CR_BMCMODE_LOW)—Offset 6E48h .... 739
5.9.194B-Unit Machine Check Mode High (B_CR_BMCMODE_HIGH)—Offset 6E4Ch .. 740
5.9.195Two-Way Asymmetric Memory Region Configuration
(B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR)—Offset 6E50h .......... 740
5.10 Registers Summary ......................................................................................... 742
5.10.1 X2B_BARB_CTL1 (X2B_BARB_CTL1_MCHBAR)—Offset 7804h..................... 743
5.10.2 Clock Gating Control (CLKGATE_CTL_MCHBAR)—Offset 7808h ................... 744
5.10.3 Miscellaneous Controls (MISC_CTL_MCHBAR)—Offset 780Ch ...................... 746
5.10.4 CMiscellaneous T2A selector (T2A_SELECTOR_MISC_MCHBAR)—Offset 7818h ....
748
5.10.5 VC Read Ordering CFG (VC_READ_ORDERING_CFG_MCHBAR)—Offset 781Ch.....
749
5.10.6 VC Write Ordering CFG (VC_WRITE_ORDERING_CFG_MCHBAR)—Offset 7820h...
752
5.10.7 IDI0 C2U Credit Control (IDI0_C2U_CREDIT_CTRL_MCHBAR)—Offset 7824h 754
5.10.8 IDI1 C2U Credit Control (IDI1_C2U_CREDIT_CTRL_MCHBAR)—Offset 7828h 756
5.10.9 IDI2 C2U Credit Control (IDI2_C2U_CREDIT_CTRL_MCHBAR)—Offset 782Ch 757
5.10.10IDI3 C2U Credit Control (IDI3_C2U_CREDIT_CTRL_MCHBAR)—Offset 7830h 758
5.10.11IDI4 C2U Credit Control (IDI4_C2U_CREDIT_CTRL_MCHBAR)—Offset 7834h 759
5.10.12IDI5 C2U Credit Control (IDI5_C2U_CREDIT_CTRL_MCHBAR)—Offset 7838h 761
5.10.13IDI6 C2U Credit Control (IDI6_C2U_CREDIT_CTRL_MCHBAR)—Offset 783Ch 762

334818 15
 5.10.14IDI7 C2U Credit Control (IDI7_C2U_CREDIT_CTRL_MCHBAR)—Offset 7840h 763
5.10.15PII2 A2T Credit Control (PII2_A2T_CREDIT_CTRL_MCHBAR)—Offset 7844h .. 765
5.10.16BIOSWR Control Policy (T_CR_BIOSWR_CP_0_0_0_MCHBAR)—Offset 7848h 766
5.10.17BIOSWR Read Access Control (T_CR_BIOSWR_RAC_0_0_0_MCHBAR)—Offset
7850h ................................................................................................. 766
5.10.18BIOSWR Write Access Control (T_CR_BIOSWR_WAC_0_0_0_MCHBAR)—Offset
7858h ................................................................................................. 767
5.10.19TUnit Pcode/Ucode Write, All Read Control Policy Register
(T_CR_P_U_CODEWR_ALLRD_CP_0_0_0_MCHBAR)—Offset 7860h.............. 767
5.10.20TUnit Pcode/Ucode Read Access Control
(T_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCHBAR)—Offset 7868h ........... 768
5.10.21TUnit Pcode/Ucode Write Access Control
(T_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_MCHBAR)—Offset 7870h........... 768
5.11 ..................................................................................................................... 769
5.12 Registers Summary.......................................................................................... 771
5.12.1 Address Decode Repeats (CPGC2_ADDRESS_CONTROL)—Offset 3C18h ....... 779
5.12.2 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[0])—Offset 3C1Ch .... 780
5.12.3 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[1])—Offset 3C1Dh .... 782
5.12.4 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[2])—Offset 3C1Eh .... 783
5.12.5 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[3])—Offset 3C1Fh .... 785
5.12.6 Data Instruction (CPGC2_DATA_INSTRUCTION[0])—Offset 3C20h............... 787
5.12.7 Data Instruction (CPGC2_DATA_INSTRUCTION[1])—Offset 3C21h............... 788
5.12.8 Data Instruction (CPGC2_DATA_INSTRUCTION[2])—Offset 3C22h............... 789
5.12.9 Data Instruction (CPGC2_DATA_INSTRUCTION[3])—Offset 3C23h............... 790
5.12.10Data Rotation Repeats (CPGC2_DATA_CONTROL)—Offset 3C24h................. 791
5.12.11Address and Data Repeats Status (CPGC2_ADDRESS_DATA_STATUS)—Offset
3C28h ................................................................................................. 792
5.12.12Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[0])—Offset 3C2Ch ...
793
5.12.13Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[1])—Offset 3C2Dh ...
794
5.12.14Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[2])—Offset 3C2Eh ...
795
5.12.15Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[3])—Offset 3C2Fh....
796
5.12.16Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[4])—Offset 3C30h ...
797
5.12.17Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[5])—Offset 3C31h ...
798
5.12.18Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[6])—Offset 3C32h ...
799
5.12.19Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[7])—Offset 3C33h ...
800
5.12.20Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[0])—
Offset 3C34h........................................................................................ 801
5.12.21Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[1])—
Offset 3C35h........................................................................................ 803
5.12.22Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[2])—
Offset 3C36h........................................................................................ 805
5.12.23Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[3])—
Offset 3C37h........................................................................................ 807
5.12.24Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[4])—
Offset 3C38h........................................................................................ 809
5.12.25Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[5])—
Offset 3C39h........................................................................................ 811
5.12.26Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[6])—
Offset 3C3Ah........................................................................................ 813

16 334818
 5.12.27Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[7])—
Offset 3C3Bh ....................................................................................... 815
5.12.28Wait Timer Current (CPGC2_ALGORITHM_WAIT_COUNT_CURRENT)—Offset
3C3Ch ................................................................................................ 817
5.12.29Algorithm Wait Event Control (CPGC2_ALGORITHM_WAIT_EVENT_CONTROL)—
Offset 3C40h ....................................................................................... 818
5.12.30Base Repeats (CPGC2_BASE_REPEATS)—Offset 3C44h.............................. 819
5.12.31Current Base Repeats (CPGC2_BASE_REPEATS_CURRENT)—Offset 3C48h ... 819
5.12.32Base Column Repeats (CPGC2_BASE_COL_REPEATS)—Offset 3C4Ch........... 820
5.12.33Block Repeats (CPGC2_BLOCK_REPEATS)—Offset 3C50h ........................... 820
5.12.34Current Block Repeats (CPGC2_BLOCK_REPEATS_CURRENT)—Offset 3C54h 821
5.12.35Command Instruction (CPGC2_COMMAND_INSTRUCTION[0])—Offset 3C58h 821
5.12.36Command Instruction (CPGC2_COMMAND_INSTRUCTION[1])—Offset 3C59h 823
5.12.37Command Instruction (CPGC2_COMMAND_INSTRUCTION[2])—Offset 3C5Ah 824
5.12.38Command Instruction (CPGC2_COMMAND_INSTRUCTION[3])—Offset 3C5Bh 826
5.12.39Command Instruction (CPGC2_COMMAND_INSTRUCTION[4])—Offset 3C5Ch 827
5.12.40Command Instruction (CPGC2_COMMAND_INSTRUCTION[5])—Offset 3C5Dh 828
5.12.41Command Instruction (CPGC2_COMMAND_INSTRUCTION[6])—Offset 3C5Eh 830
5.12.42Command Instruction (CPGC2_COMMAND_INSTRUCTION[7])—Offset 3C5Fh 831
5.12.43Command Instruction (CPGC2_COMMAND_INSTRUCTION[8])—Offset 3C60h 833
5.12.44Command Instruction (CPGC2_COMMAND_INSTRUCTION[9])—Offset 3C61h 834
5.12.45Command Instruction (CPGC2_COMMAND_INSTRUCTION[10])—Offset 3C62h....
835
5.12.46Command Instruction (CPGC2_COMMAND_INSTRUCTION[11])—Offset 3C63h....
837
5.12.47Command Instruction (CPGC2_COMMAND_INSTRUCTION[12])—Offset 3C64h....
838
5.12.48Command Instruction (CPGC2_COMMAND_INSTRUCTION[13])—Offset 3C65h....
840
5.12.49Command Instruction (CPGC2_COMMAND_INSTRUCTION[14])—Offset 3C66h....
841
5.12.50Command Instruction (CPGC2_COMMAND_INSTRUCTION[15])—Offset 3C67h....
842
5.12.51Command Instruction (CPGC2_COMMAND_INSTRUCTION[16])—Offset 3C68h....
844
5.12.52Command Instruction (CPGC2_COMMAND_INSTRUCTION[17])—Offset 3C69h....
845
5.12.53Command Instruction (CPGC2_COMMAND_INSTRUCTION[18])—Offset 3C6Ah....
847
5.12.54Command Instruction (CPGC2_COMMAND_INSTRUCTION[19])—Offset 3C6Bh....
848
5.12.55Command Instruction (CPGC2_COMMAND_INSTRUCTION[20])—Offset 3C6Ch....
849
5.12.56Command Instruction (CPGC2_COMMAND_INSTRUCTION[21])—Offset 3C6Dh ...
851
5.12.57Command Instruction (CPGC2_COMMAND_INSTRUCTION[22])—Offset 3C6Eh....
852
5.12.58Command Instruction (CPGC2_COMMAND_INSTRUCTION[23])—Offset 3C6Fh ....
854
5.12.59Hammer Repeats (CPGC2_HAMMER_REPEATS)—Offset 3C70h.................... 855
5.12.60Current Hammer Repeats (CPGC2_HAMMER_REPEATS_CURRENT)—Offset 3C74h
855
5.12.61Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[0])—
Offset 3C78h ....................................................................................... 856
5.12.62Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[1])—
Offset 3C79h ....................................................................................... 858

334818 17
 5.12.63Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[2])—
Offset 3C7Ah........................................................................................ 859
5.12.64Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[3])—
Offset 3C7Bh........................................................................................ 861
5.12.65Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[4])—
Offset 3C7Ch ....................................................................................... 862
5.12.66Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[5])—
Offset 3C7Dh ....................................................................................... 864
5.12.67Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[6])—
Offset 3C7Eh........................................................................................ 865
5.12.68Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[7])—
Offset 3C7Fh ........................................................................................ 867
5.12.69Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[8])—
Offset 3C80h........................................................................................ 868
5.12.70Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[9])—
Offset 3C81h........................................................................................ 870
5.12.71Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[10])—
Offset 3C82h........................................................................................ 871
5.12.72Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[11])—
Offset 3C83h........................................................................................ 873
5.12.73Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[12])—
Offset 3C84h........................................................................................ 874
5.12.74Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[13])—
Offset 3C85h........................................................................................ 876
5.12.75Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[14])—
Offset 3C86h........................................................................................ 877
5.12.76Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[15])—
Offset 3C87h........................................................................................ 879
5.12.77Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[0])—
Offset 3C88h........................................................................................ 880
5.12.78Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[1])—
Offset 3C89h........................................................................................ 881
5.12.79Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[2])—
Offset 3C8Ah........................................................................................ 882
5.12.80Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[3])—
Offset 3C8Bh........................................................................................ 883
5.12.81Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[4])—
Offset 3C8Ch ....................................................................................... 884
5.12.82Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[5])—
Offset 3C8Dh ....................................................................................... 886
5.12.83Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[6])—
Offset 3C8Eh........................................................................................ 887
5.12.84Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[7])—
Offset 3C8Fh ........................................................................................ 888
5.12.85Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[8])—
Offset 3C90h........................................................................................ 889
5.12.86Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[9])—
Offset 3C91h........................................................................................ 890
5.12.87Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[10])—
Offset 3C92h........................................................................................ 891
5.12.88Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[11])—
Offset 3C93h........................................................................................ 892
5.12.89Offset Repeats (CPGC2_OFFSET_REPEATS[0])—Offset 3C94h ..................... 893
5.12.90Offset Repeats (CPGC2_OFFSET_REPEATS[1])—Offset 3C98h ..................... 894
5.12.91Current Offset Repeats (CPGC2_OFFSET_REPEATS_CURRENT)—Offset 3C9Ch....
894
5.12.92Region Low Row Address (CPGC2_REGION_LOW_ROW)—Offset 3CA0h ........ 895

18 334818
 5.12.93Region Low Col Address (CPGC2_REGION_LOW_COL)—Offset 3CA4h .......... 896
5.12.94Block Low Row Current (CPGC2_BLOCK_ORIGIN_ROW_CURRENT)—Offset 3CA8h
896
5.12.95Current Base Address Rank and Column
(CPGC2_BASE_ADDRESS_COL_RANK_CURRENT)—Offset 3CACh ................ 897
5.12.96Current Base Address Bank and Row
(CPGC2_BASE_ADDRESS_ROW_BANK_CURRENT)—Offset 3CB0h ............... 898
5.12.97Current Offset Address Column (CPGC2_OFFSET_ADDRESS_COL_CURRENT)—
Offset 3CB4h ....................................................................................... 898
5.12.98Current Offset Address Row (CPGC2_OFFSET_ADDRESS_ROW_CURRENT)—
Offset 3CB8h ....................................................................................... 899
5.12.99Address Size (CPGC2_ADDRESS_SIZE)—Offset 3CBCh .............................. 900
5.12.100Base Address Control (CPGC2_BASE_ADDRESS_CONTROL)—Offset 3CC0h . 901
5.12.101Address PRBS Control (CPGC2_ADDRESS_PRBS_CONTROL)—Offset 3CC4h 903
5.12.102Address PRBS Seed (CPGC2_ADDRESS_PRBS_SEED)—Offset 3CC8h ......... 904
5.12.103Current Address PRBS Status (CPGC2_ADDRESS_PRBS_CURRENT)—Offset
3CCCh ................................................................................................ 905
5.12.104Address PRBS Save (CPGC2_ADDRESS_PRBS_SAVE)—Offset 3CD0h ......... 905
5.12.105Command FSM Current State (CPGC2_CMD_FSM_CURRENT)—Offset 3CD4h.....
906
5.12.106Algorithm Wait Timer Configuration (CPGC2_WAIT_2_START_CONFIG)—Offset
3CD8h ................................................................................................ 907
5.12.107VISA Mux Selection (CPGC2_VISA_MUX_SEL)—Offset 3CDCh ................... 908
5.12.108Loopback Squencer Configuration (CPGC_LB_SEQ_CFG)—Offset 3CE0h ..... 909
5.12.109Loopback Sequencer Control (CPGC_LB_SEQ_CTL)—Offset 3CE4h ............. 911
5.12.110Loopback Loopcount Tx Status (CPGC_LB_SEQ_LOOPCOUNT_TX_STATUS)—
Offset 3CE8h ....................................................................................... 913
5.12.111Loopback Loopcount Rx Status (CPGC_LB_SEQ_LOOPCOUNT_RX_STATUS)—
Offset 3CECh ....................................................................................... 914
5.12.112Pattern Length Status (CPGC_LB_SEQ_PL_RX_STATUS)—Offset 3CF0h ...... 914
5.12.113Refresh Control (CPGC_MISC_REFRESH_CTL)—Offset 3CF4h .................... 915
5.12.114ZQ Control (CPGC_MISC_ZQ_CTL)—Offset 3CF8h ................................... 916
5.12.115ODT Control (CPGC_MISC_ODT_CTL)—Offset 3CFCh ............................... 916
5.12.116CKE Control (CPGC_MISC_CKE_CTL)—Offset 3D00h ................................ 917
5.12.117Command Rate (CPGC_MISC_CMD_RATE)—Offset 3D04h ........................ 918
5.12.118External Trigger Control (CPGC_MISC_EXT_TRIGGER)—Offset 3D08h ........ 919
5.12.119Sequence Control (CPGC_SEQ_CTL)—Offset 3D0Ch................................. 919
5.12.120Sequence Configuration A (CPGC_SEQ_CFG_A)—Offset 3D10h ................. 920
5.12.121Sequence Configuration B (CPGC_SEQ_CFG_B)—Offset 3D14h ................. 923
5.12.122Sequence Status (CPGC_SEQ_STATUS)—Offset 3D18h ............................ 923
5.12.123Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[0])—Offset
3D20h ................................................................................................ 924
5.12.124Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[1])—Offset
3D24h ................................................................................................ 925
5.12.125Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[2])—Offset
3D28h ................................................................................................ 925
5.12.126Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[3])—Offset
3D2Ch ................................................................................................ 926
5.12.127Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[4])—Offset
3D30h ................................................................................................ 926
5.12.128Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[5])—Offset
3D34h ................................................................................................ 927
5.12.129Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[6])—Offset
3D38h ................................................................................................ 928
5.12.130Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[7])—Offset
3D3Ch ................................................................................................ 928

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 5.12.131Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[8])—Offset
3D40h................................................................................................. 929
5.12.132Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[9])—Offset
3D44h................................................................................................. 929
5.12.133Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[10])—Offset
3D48h................................................................................................. 930
5.12.134Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[11])—Offset
3D4Ch ................................................................................................ 931
5.12.135Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[12])—Offset
3D50h................................................................................................. 931
5.12.136Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[13])—Offset
3D54h................................................................................................. 932
5.12.137Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[14])—Offset
3D58h................................................................................................. 932
5.12.138Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[15])—Offset
3D5Ch ................................................................................................ 933
5.12.139Mode3 Fail Status LSB (CPGC2_RASTER_REPO_CONTENT_ECC1)—Offset 3D60h
934
5.12.140Mode3 Fail Status MSB (CPGC2_RASTER_REPO_CONTENT_ECC2)—Offset
3D64h................................................................................................. 935
5.12.141Read Command Count (CPGC2_READ_COMMAND_COUNT_CURRENT)—Offset
3D68h................................................................................................. 937
5.12.142Mask Errors on First N Reads (CPGC2_MASK_ERRS_FIRST_N_READS)—Offset
3D6Ch ................................................................................................ 937
5.12.143Raster Repository Status (CPGC2_RASTER_REPO_STATUS)—Offset 3D70h . 938
5.12.144Error Summary A (CPGC2_ERR_SUMMARY_A)—Offset 3D74h.................... 939
5.12.145Error Summary B (CPGC2_ERR_SUMMARY_B)—Offset 3D78h.................... 940
5.12.146Future use Reserved (CPGC2_ERR_SUMMARY_C)—Offset 3D7Ch ............... 941
5.12.147Data Pattern Generation Buffer Control (CPGC_DPAT_BUF_CTL)—Offset 3D80h
941
5.12.148Data Pattern Generation Configuration (CPGC_DPAT_CFG)—Offset 3D84h .. 943
5.12.149LFSR Configuration and Lane Rotate (CPGC_DPAT_XTRA_LFSR_CFG)—Offset
3D88h................................................................................................. 947
5.12.150Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[0])—Offset 3D8Ch 949
5.12.151Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[1])—Offset 3D90h 950
5.12.152Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[2])—Offset 3D94h 950
5.12.153Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[0])—Offset 3D98h .. 951
5.12.154Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[1])—Offset 3D9Ch.. 954
5.12.155Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[2])—Offset 3DA0h .. 957
5.12.156Invert and DC Control (CPGC_DPAT_INVDCCTL)—Offset 3DA4h ................ 960
5.12.157Data Invert/DC Enable Low (CPGC_DPAT_INV_DC_MASK_LO)—Offset 3DA8h ..
961
5.12.158Data Invert/DC Enable High (CPGC_DPAT_INV_DC_MASK_HI)—Offset 3DACh ..
962
5.12.159Byte Enable Mask Lower (CPGC_DPAT_DRAMDM)—Offset 3DB0h ............... 962
5.12.160Byte Enable Mask Upper (CPGC_DPAT_XDRAMDM)—Offset 3DB4h ............. 963
5.12.161Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[0])—Offset 3DB8h
964
5.12.162Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[1])—Offset 3DBCh
964
5.12.163Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[2])—Offset 3DC0h
965
5.12.164Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[0])—Offset 3DC4h
965
5.12.165Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[1])—Offset 3DC8h
966

20 334818
 5.12.166Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[2])—Offset 3DCCh
967
5.12.167LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[0])—Offset 3DD0h........... 968
5.12.168LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[1])—Offset 3DD4h........... 969
5.12.169LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[2])—Offset 3DD8h........... 969
5.12.170LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[0])—Offset 3DDCh ........... 970
5.12.171LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[1])—Offset 3DE0h ............ 970
5.12.172LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[2])—Offset 3DE4h ............ 971
5.12.173Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[0])—Offset
3DE8h ................................................................................................ 971
5.12.174Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[1])—Offset
3DECh ................................................................................................ 972
5.12.175Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[2])—Offset
3DF0h ................................................................................................ 972
5.12.176Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[0])—Offset
3DF4h ................................................................................................ 973
5.12.177Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[1])—Offset
3DF8h ................................................................................................ 974
5.12.178Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[2])—Offset
3DFCh ................................................................................................ 975
5.12.179Extended Pattern Buffer (CPGC_DPAT_EXTBUF[0])—Offset 3E00h ............. 976
5.12.180Extended Pattern Buffer (CPGC_DPAT_EXTBUF[1])—Offset 3E04h ............. 977
5.12.181Extended Pattern Buffer (CPGC_DPAT_EXTBUF[2])—Offset 3E08h ............. 978
5.12.182Extended Pattern Buffer (CPGC_DPAT_EXTBUF[3])—Offset 3E0Ch ............. 979
5.12.183Extended Pattern Buffer (CPGC_DPAT_EXTBUF[4])—Offset 3E10h ............. 979
5.12.184Extended Pattern Buffer (CPGC_DPAT_EXTBUF[5])—Offset 3E14h ............. 980
5.12.185Extended Pattern Buffer (CPGC_DPAT_EXTBUF[6])—Offset 3E18h ............. 981
5.12.186Extended Pattern Buffer (CPGC_DPAT_EXTBUF[7])—Offset 3E1Ch ............. 982
5.12.187Extended Pattern Buffer (CPGC_DPAT_EXTBUF[8])—Offset 3E20h ............. 983
5.12.188Extended Pattern Buffer (CPGC_DPAT_EXTBUF[9])—Offset 3E24h ............. 984
5.12.189Extended Pattern Buffer (CPGC_DPAT_EXTBUF[10])—Offset 3E28h ........... 984
5.12.190Extended Pattern Buffer (CPGC_DPAT_EXTBUF[11])—Offset 3E2Ch ........... 985
5.12.191Extended Pattern Buffer (CPGC_DPAT_EXTBUF[12])—Offset 3E30h ........... 986
5.12.192Extended Pattern Buffer (CPGC_DPAT_EXTBUF[13])—Offset 3E34h ........... 987
5.12.193Extended Pattern Buffer (CPGC_DPAT_EXTBUF[14])—Offset 3E38h ........... 988
5.12.194Extended Pattern Buffer (CPGC_DPAT_EXTBUF[15])—Offset 3E3Ch ........... 989
5.12.195Error Checker Control (CPGC_ERR_CTL)—Offset 3E40h ............................ 989
5.12.196Lane Error Mask Lower Bytes (CPGC_ERR_LNEN_LO)—Offset 3E44h .......... 991
5.12.197Lane Error Mask Upper Bytes or Extended Chunk Enable
(CPGC_ERR_LNEN_HI)—Offset 3E48h ..................................................... 992
5.12.198Lane Error Mask ECC (CPGC_ERR_XLNEN)—Offset 3E4Ch......................... 993
5.12.199Lane Error Status Lower Bytes (CPGC_ERR_STAT03)—Offset 3E50h .......... 993
5.12.200Lane Error Status Upper Bytes or Extended Chunk Error Status
(CPGC_ERR_STAT47)—Offset 3E54h ....................................................... 994
5.12.201ECC Lane Error Status (CPGC_ERR_ECC_CHNK_RANK_STAT)—Offset 3E58h.....
995
5.12.202ByteGroup Error Status (CPGC_ERR_BYTE_NTH_PAR_STAT)—Offset 3E5Ch 996
5.12.203Error Counter Control (CPGC_ERR_CNTRCTL[0])—Offset 3E60h ................ 997
5.12.204Error Counter Control (CPGC_ERR_CNTRCTL[1])—Offset 3E64h ................ 998
5.12.205Error Counter Control (CPGC_ERR_CNTRCTL[2])—Offset 3E68h ................ 999
5.12.206Error Counter Control (CPGC_ERR_CNTRCTL[3])—Offset 3E6Ch ...............1000
5.12.207Error Counter Control (CPGC_ERR_CNTRCTL[4])—Offset 3E70h ...............1001
5.12.208Error Counter Control (CPGC_ERR_CNTRCTL[5])—Offset 3E74h ...............1002
5.12.209Error Counter Control (CPGC_ERR_CNTRCTL[6])—Offset 3E78h ...............1003
5.12.210Error Counter Control (CPGC_ERR_CNTRCTL[7])—Offset 3E7Ch ...............1004
5.12.211Error Counter Control (CPGC_ERR_CNTRCTL[8])—Offset 3E80h ...............1005

334818 21
 5.12.212Error Counter (CPGC_ERR_CNTR[0])—Offset 3E84h ............................... 1006
5.12.213Error Counter (CPGC_ERR_CNTR[1])—Offset 3E88h ............................... 1007
5.12.214Error Counter (CPGC_ERR_CNTR[2])—Offset 3E8Ch............................... 1008
5.12.215Error Counter (CPGC_ERR_CNTR[3])—Offset 3E90h ............................... 1009
5.12.216Error Counter (CPGC_ERR_CNTR[4])—Offset 3E94h ............................... 1009
5.12.217Error Counter (CPGC_ERR_CNTR[5])—Offset 3E98h ............................... 1010
5.12.218Error Counter (CPGC_ERR_CNTR[6])—Offset 3E9Ch............................... 1011
5.12.219Error Counter (CPGC_ERR_CNTR[7])—Offset 3EA0h............................... 1011
5.12.220Error Counter (CPGC_ERR_CNTR[8])—Offset 3EA4h............................... 1012
5.12.221Error Counter Overflow (CPGC_ERR_CNTR_OV)—Offset 3EA8h ................ 1013
5.12.222Error Log Control and Status (CPGC_ERRLOG_CTL_STAT)—Offset 3EACh.. 1014
5.12.223Error Log Data Access (CPGC_ERRLOG_DATA)—Offset 3EB0h ................. 1015
5.12.224Loopback Error Status (CPGC_ERR_TEST_ERR_STAT)—Offset 3EB4h ....... 1016
5.12.225Rank Logical To Physical Map (CPGC_SEQ_RANK_L2P_MAPPING)—Offset 3EB8h
1017
5.12.226Bank Logical to Physical Map Low (CPGC_SEQ_BANK_L2P_MAPPING_A)—Offset
3EBCh............................................................................................... 1018
5.12.227Bank Logical to Physical Map High (CPGC_SEQ_BANK_L2P_MAPPING_B)—Offset
3EC0h ............................................................................................... 1019
5.12.228Rank Address Swizzle (CPGC_SEQ_RANK_ADDR_SWIZZLE)—Offset 3EC4h1021
5.12.229Bank Address Swizzle (CPGC_SEQ_BANK_ADDR_SWIZZLE)—Offset 3EC8h1022
5.12.230Row Address Swizzle Low (CPGC_SEQ_ROW_ADDR_SWIZZLE_A)—Offset 3ECCh
1022
5.12.231Row Address Swizzle Mid (CPGC_SEQ_ROW_ADDR_SWIZZLE_B)—Offset 3ED0h
1024
5.12.232Row Address Swizzle High (CPGC_SEQ_ROW_ADDR_SWIZZLE_C)—Offset
3ED4h............................................................................................... 1025
5.12.233Row Address XOR (CPGC_SEQ_ROW_ADDR_SWIZZLE_X)—Offset 3ED8h . 1026
5.12.234Column Address Swizzle Low (CPGC_SEQ_COL_ADDR_SWIZZLE_A)—Offset
3EDCh .............................................................................................. 1027
5.12.235Column Address Swizzle High (CPGC_SEQ_COL_ADDR_SWIZZLE_B)—Offset
3EE0h ............................................................................................... 1028
5.12.236DQ Inversion Lookup Data Low (CPGC_SEQ_ROW_ADDR_DQ_MAP0)—Offset
3EE8h ............................................................................................... 1029
5.12.237DQ Inversion Lookup Data High (CPGC_SEQ_ROW_ADDR_DQ_MAP1)—Offset
3EECh ............................................................................................... 1030
5.13 Registers Summary........................................................................................ 1031
5.13.1 CADB Control (CPGC_CADB_CTL)—Offset 42F0h ..................................... 1032
5.13.2 CADB MRS Configuration (CPGC_CADB_MRSCFG)—Offset 42F4h............... 1035
5.13.3 CADB Configuration (CPGC_CADB_CFG)—Offset 42F8h ............................ 1036
5.13.4 CADB Unisequencer 0 Pattern Buffer (CPGC_CADB_UNISEQ0_PBUF)—Offset
42FCh ............................................................................................... 1037
5.13.5 CADB Unisequencer 1 Pattern Buffer (CPGC_CADB_UNISEQ1_PBUF)—Offset
4300h ............................................................................................... 1038
5.13.6 CADB Unisequencer 2 Pattern Buffer (CPGC_CADB_UNISEQ2_PBUF)—Offset
4304h ............................................................................................... 1038
5.13.7 CADB LMN 0 Settings (CPGC_CADB_UNISEQ0_LMN)—Offset 4308h........... 1039
5.13.8 CADB LMN 1 Settings (CPGC_CADB_UNISEQ1_LMN)—Offset 430Ch .......... 1040
5.13.9 CADB LMN 2 Settings (CPGC_CADB_UNISEQ2_LMN)—Offset 4310h........... 1041
5.13.10CADB Select Unisequencer 0 Pattern Buffer
(CPGC_CADB_SEL_UNISEQ0_PBUF)—Offset 4314h ................................. 1042
5.13.11CADB Select Unisequencer 1 Pattern Buffer
(CPGC_CADB_SEL_UNISEQ1_PBUF)—Offset 4318h ................................. 1043
5.13.12CADB Select Unisequencer 2 Pattern Buffer
(CPGC_CADB_SEL_UNISEQ2_PBUF)—Offset 431Ch ................................. 1043
5.13.13CADB Buffer A (CPGC_CADB_BUFA[0])—Offset 4320h ............................. 1044

22 334818
 5.13.14CADB Buffer A (CPGC_CADB_BUFA[1])—Offset 4324h..............................1044
5.13.15CADB Buffer A (CPGC_CADB_BUFA[2])—Offset 4328h..............................1045
5.13.16CADB Buffer A (CPGC_CADB_BUFA[3])—Offset 432Ch .............................1046
5.13.17CADB Buffer A (CPGC_CADB_BUFA[4])—Offset 4330h..............................1047
5.13.18CADB Buffer A (CPGC_CADB_BUFA[5])—Offset 4334h..............................1047
5.13.19CADB Buffer A (CPGC_CADB_BUFA[6])—Offset 4338h..............................1048
5.13.20CADB Buffer A (CPGC_CADB_BUFA[7])—Offset 433Ch .............................1049
5.13.21CADB Buffer B (CPGC_CADB_BUFB[0])—Offset 4340h..............................1049
5.13.22CADB Buffer B (CPGC_CADB_BUFB[1])—Offset 4344h..............................1050
5.13.23CADB Buffer B (CPGC_CADB_BUFB[2])—Offset 4348h..............................1051
5.13.24CADB Buffer B (CPGC_CADB_BUFB[3])—Offset 434Ch .............................1052
5.13.25CADB Buffer B (CPGC_CADB_BUFB[4])—Offset 4350h..............................1053
5.13.26CADB Buffer B (CPGC_CADB_BUFB[5])—Offset 4354h..............................1054
5.13.27CADB Buffer B (CPGC_CADB_BUFB[6])—Offset 4358h..............................1055
5.13.28CADB Buffer B (CPGC_CADB_BUFB[7])—Offset 435Ch .............................1056
5.13.29CADB Deselect Uniseq 0 Status (CPGC_CADB_UNISEQ0STAT)—Offset 4360h .....
1057
5.13.30CADB Deselect Uniseq 1 Status (CPGC_CADB_UNISEQ1STAT)—Offset 4364h .....
1058
5.13.31CADB Deselect Uniseq 2 Status (CPGC_CADB_UNISEQ2STAT)—Offset 4368h .....
1058
5.14 Registers Summary ........................................................................................1061
5.14.1 Address Decode Repeats (CPGC2_ADDRESS_CONTROL)—Offset 4018h ......1069
5.14.2 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[0])—Offset 401Ch...1070
5.14.3 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[1])—Offset 401Dh...1072
5.14.4 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[2])—Offset 401Eh ...1073
5.14.5 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[3])—Offset 401Fh ...1075
5.14.6 Data Instruction (CPGC2_DATA_INSTRUCTION[0])—Offset 4020h .............1077
5.14.7 Data Instruction (CPGC2_DATA_INSTRUCTION[1])—Offset 4021h .............1078
5.14.8 Data Instruction (CPGC2_DATA_INSTRUCTION[2])—Offset 4022h .............1079
5.14.9 Data Instruction (CPGC2_DATA_INSTRUCTION[3])—Offset 4023h .............1080
5.14.10Data Rotation Repeats (CPGC2_DATA_CONTROL)—Offset 4024h ...............1081
5.14.11Address and Data Repeats Status (CPGC2_ADDRESS_DATA_STATUS)—Offset
4028h................................................................................................1082
5.14.12Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[0])—Offset 402Ch ....
1083
5.14.13Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[1])—Offset 402Dh ....
1084
5.14.14Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[2])—Offset 402Eh ....
1085
5.14.15Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[3])—Offset 402Fh ....
1086
5.14.16Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[4])—Offset 4030h ....
1087
5.14.17Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[5])—Offset 4031h ....
1088
5.14.18Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[6])—Offset 4032h ....
1089
5.14.19Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[7])—Offset 4033h ....
1090
5.14.20Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[0])—
Offset 4034h ......................................................................................1091
5.14.21Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[1])—
Offset 4035h ......................................................................................1093
5.14.22Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[2])—
Offset 4036h ......................................................................................1095

334818 23
 5.14.23Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[3])—
Offset 4037h ...................................................................................... 1097
5.14.24Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[4])—
Offset 4038h ...................................................................................... 1099
5.14.25Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[5])—
Offset 4039h ...................................................................................... 1101
5.14.26Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[6])—
Offset 403Ah...................................................................................... 1103
5.14.27Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[7])—
Offset 403Bh...................................................................................... 1105
5.14.28Wait Timer Current (CPGC2_ALGORITHM_WAIT_COUNT_CURRENT)—Offset
403Ch ............................................................................................... 1107
5.14.29Algorithm Wait Event Control (CPGC2_ALGORITHM_WAIT_EVENT_CONTROL)—
Offset 4040h ...................................................................................... 1108
5.14.30Base Repeats (CPGC2_BASE_REPEATS)—Offset 4044h ............................ 1109
5.14.31Current Base Repeats (CPGC2_BASE_REPEATS_CURRENT)—Offset 4048h .. 1109
5.14.32Base Column Repeats (CPGC2_BASE_COL_REPEATS)—Offset 404Ch ......... 1110
5.14.33Block Repeats (CPGC2_BLOCK_REPEATS)—Offset 4050h ......................... 1110
5.14.34Current Block Repeats (CPGC2_BLOCK_REPEATS_CURRENT)—Offset 4054h1111
5.14.35Command Instruction (CPGC2_COMMAND_INSTRUCTION[0])—Offset 4058h .....
1111
5.14.36Command Instruction (CPGC2_COMMAND_INSTRUCTION[1])—Offset 4059h .....
1113
5.14.37Command Instruction (CPGC2_COMMAND_INSTRUCTION[2])—Offset 405Ah .....
1114
5.14.38Command Instruction (CPGC2_COMMAND_INSTRUCTION[3])—Offset 405Bh .....
1116
5.14.39Command Instruction (CPGC2_COMMAND_INSTRUCTION[4])—Offset 405Ch .....
1117
5.14.40Command Instruction (CPGC2_COMMAND_INSTRUCTION[5])—Offset 405Dh.....
1118
5.14.41Command Instruction (CPGC2_COMMAND_INSTRUCTION[6])—Offset 405Eh .....
1120
5.14.42Command Instruction (CPGC2_COMMAND_INSTRUCTION[7])—Offset 405Fh .....
1121
5.14.43Command Instruction (CPGC2_COMMAND_INSTRUCTION[8])—Offset 4060h .....
1123
5.14.44Command Instruction (CPGC2_COMMAND_INSTRUCTION[9])—Offset 4061h .....
1124
5.14.45Command Instruction (CPGC2_COMMAND_INSTRUCTION[10])—Offset 4062h ...
1125
5.14.46Command Instruction (CPGC2_COMMAND_INSTRUCTION[11])—Offset 4063h ...
1127
5.14.47Command Instruction (CPGC2_COMMAND_INSTRUCTION[12])—Offset 4064h ...
1128
5.14.48Command Instruction (CPGC2_COMMAND_INSTRUCTION[13])—Offset 4065h ...
1130
5.14.49Command Instruction (CPGC2_COMMAND_INSTRUCTION[14])—Offset 4066h ...
1131
5.14.50Command Instruction (CPGC2_COMMAND_INSTRUCTION[15])—Offset 4067h ...
1132
5.14.51Command Instruction (CPGC2_COMMAND_INSTRUCTION[16])—Offset 4068h ...
1134
5.14.52Command Instruction (CPGC2_COMMAND_INSTRUCTION[17])—Offset 4069h ...
1135
5.14.53Command Instruction (CPGC2_COMMAND_INSTRUCTION[18])—Offset 406Ah ...
1137

24 334818
 5.14.54Command Instruction (CPGC2_COMMAND_INSTRUCTION[19])—Offset 406Bh....
1138
5.14.55Command Instruction (CPGC2_COMMAND_INSTRUCTION[20])—Offset 406Ch....
1139
5.14.56Command Instruction (CPGC2_COMMAND_INSTRUCTION[21])—Offset 406Dh ...
1141
5.14.57Command Instruction (CPGC2_COMMAND_INSTRUCTION[22])—Offset 406Eh ....
1142
5.14.58Command Instruction (CPGC2_COMMAND_INSTRUCTION[23])—Offset 406Fh ....
1144
5.14.59Hammer Repeats (CPGC2_HAMMER_REPEATS)—Offset 4070h...................1145
5.14.60Current Hammer Repeats (CPGC2_HAMMER_REPEATS_CURRENT)—Offset 4074h
1145
5.14.61Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[0])—
Offset 4078h ......................................................................................1146
5.14.62Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[1])—
Offset 4079h ......................................................................................1148
5.14.63Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[2])—
Offset 407Ah ......................................................................................1149
5.14.64Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[3])—
Offset 407Bh ......................................................................................1151
5.14.65Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[4])—
Offset 407Ch ......................................................................................1152
5.14.66Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[5])—
Offset 407Dh ......................................................................................1154
5.14.67Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[6])—
Offset 407Eh ......................................................................................1155
5.14.68Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[7])—
Offset 407Fh.......................................................................................1157
5.14.69Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[8])—
Offset 4080h ......................................................................................1158
5.14.70Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[9])—
Offset 4081h ......................................................................................1160
5.14.71Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[10])—
Offset 4082h ......................................................................................1161
5.14.72Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[11])—
Offset 4083h ......................................................................................1163
5.14.73Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[12])—
Offset 4084h ......................................................................................1164
5.14.74Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[13])—
Offset 4085h ......................................................................................1166
5.14.75Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[14])—
Offset 4086h ......................................................................................1167
5.14.76Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[15])—
Offset 4087h ......................................................................................1169
5.14.77Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[0])—
Offset 4088h ......................................................................................1170
5.14.78Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[1])—
Offset 4089h ......................................................................................1171
5.14.79Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[2])—
Offset 408Ah ......................................................................................1172
5.14.80Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[3])—
Offset 408Bh ......................................................................................1173
5.14.81Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[4])—
Offset 408Ch ......................................................................................1175
5.14.82Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[5])—
Offset 408Dh ......................................................................................1176

334818 25
 5.14.83Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[6])—
Offset 408Eh ...................................................................................... 1177
5.14.84Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[7])—
Offset 408Fh ...................................................................................... 1178
5.14.85Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[8])—
Offset 4090h ...................................................................................... 1179
5.14.86Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[9])—
Offset 4091h ...................................................................................... 1180
5.14.87Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[10])—
Offset 4092h ...................................................................................... 1181
5.14.88Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[11])—
Offset 4093h ...................................................................................... 1182
5.14.89Offset Repeats (CPGC2_OFFSET_REPEATS[0])—Offset 4094h ................... 1183
5.14.90Offset Repeats (CPGC2_OFFSET_REPEATS[1])—Offset 4098h ................... 1184
5.14.91Current Offset Repeats (CPGC2_OFFSET_REPEATS_CURRENT)—Offset 409Ch ....
1184
5.14.92Region Low Row Address (CPGC2_REGION_LOW_ROW)—Offset 40A0h ...... 1185
5.14.93Region Low Col Address (CPGC2_REGION_LOW_COL)—Offset 40A4h......... 1186
5.14.94Block Low Row Current (CPGC2_BLOCK_ORIGIN_ROW_CURRENT)—Offset 40A8h
1186
5.14.95Current Base Address Rank and Column
(CPGC2_BASE_ADDRESS_COL_RANK_CURRENT)—Offset 40ACh............... 1187
5.14.96Current Base Address Bank and Row
(CPGC2_BASE_ADDRESS_ROW_BANK_CURRENT)—Offset 40B0h.............. 1188
5.14.97Current Offset Address Column (CPGC2_OFFSET_ADDRESS_COL_CURRENT)—
Offset 40B4h...................................................................................... 1188
5.14.98Current Offset Address Row (CPGC2_OFFSET_ADDRESS_ROW_CURRENT)—
Offset 40B8h...................................................................................... 1189
5.14.99Address Size (CPGC2_ADDRESS_SIZE)—Offset 40BCh............................. 1190
5.14.100Base Address Control (CPGC2_BASE_ADDRESS_CONTROL)—Offset 40C0h 1191
5.14.101Address PRBS Control (CPGC2_ADDRESS_PRBS_CONTROL)—Offset 40C4h ......
1193
5.14.102Address PRBS Seed (CPGC2_ADDRESS_PRBS_SEED)—Offset 40C8h ........ 1194
5.14.103Current Address PRBS Status (CPGC2_ADDRESS_PRBS_CURRENT)—Offset
40CCh............................................................................................... 1195
5.14.104Address PRBS Save (CPGC2_ADDRESS_PRBS_SAVE)—Offset 40D0h ........ 1195
5.14.105Command FSM Current State (CPGC2_CMD_FSM_CURRENT)—Offset 40D4h ....
1196
5.14.106Algorithm Wait Timer Configuration (CPGC2_WAIT_2_START_CONFIG)—Offset
40D8h............................................................................................... 1197
5.14.107VISA Mux Selection (CPGC2_VISA_MUX_SEL)—Offset 40DCh .................. 1198
5.14.108Loopback Squencer Configuration (CPGC_LB_SEQ_CFG)—Offset 40E0h .... 1199
5.14.109Loopback Sequencer Control (CPGC_LB_SEQ_CTL)—Offset 40E4h ........... 1201
5.14.110Loopback Loopcount Tx Status (CPGC_LB_SEQ_LOOPCOUNT_TX_STATUS)—
Offset 40E8h ...................................................................................... 1203
5.14.111Loopback Loopcount Rx Status (CPGC_LB_SEQ_LOOPCOUNT_RX_STATUS)—
Offset 40ECh...................................................................................... 1204
5.14.112Pattern Length Status (CPGC_LB_SEQ_PL_RX_STATUS)—Offset 40F0h .... 1204
5.14.113Refresh Control (CPGC_MISC_REFRESH_CTL)—Offset 40F4h................... 1205
5.14.114ZQ Control (CPGC_MISC_ZQ_CTL)—Offset 40F8h .................................. 1206
5.14.115ODT Control (CPGC_MISC_ODT_CTL)—Offset 40FCh .............................. 1206
5.14.116CKE Control (CPGC_MISC_CKE_CTL)—Offset 4100h ............................... 1207
5.14.117Command Rate (CPGC_MISC_CMD_RATE)—Offset 4104h ....................... 1208
5.14.118External Trigger Control (CPGC_MISC_EXT_TRIGGER)—Offset 4108h ....... 1209
5.14.119Sequence Control (CPGC_SEQ_CTL)—Offset 410Ch................................ 1209
5.14.120Sequence Configuration A (CPGC_SEQ_CFG_A)—Offset 4110h ................ 1210

26 334818
 5.14.121Sequence Configuration B (CPGC_SEQ_CFG_B)—Offset 4114h.................1213
5.14.122Sequence Status (CPGC_SEQ_STATUS)—Offset 4118h............................1213
5.14.123Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[0])—Offset 4120h
1214
5.14.124Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[1])—Offset 4124h
1215
5.14.125Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[2])—Offset 4128h
1215
5.14.126Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[3])—Offset 412Ch
1216
5.14.127Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[4])—Offset 4130h
1216
5.14.128Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[5])—Offset 4134h
1217
5.14.129Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[6])—Offset 4138h
1218
5.14.130Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[7])—Offset 413Ch
1218
5.14.131Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[8])—Offset 4140h
1219
5.14.132Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[9])—Offset 4144h
1219
5.14.133Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[10])—Offset
4148h................................................................................................1220
5.14.134Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[11])—Offset
414Ch ...............................................................................................1221
5.14.135Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[12])—Offset
4150h................................................................................................1221
5.14.136Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[13])—Offset
4154h................................................................................................1222
5.14.137Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[14])—Offset
4158h................................................................................................1222
5.14.138Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[15])—Offset
415Ch ...............................................................................................1223
5.14.139Mode3 Fail Status LSB (CPGC2_RASTER_REPO_CONTENT_ECC1)—Offset 4160h
1224
5.14.140Mode3 Fail Status MSB (CPGC2_RASTER_REPO_CONTENT_ECC2)—Offset 4164h
1225
5.14.141Read Command Count (CPGC2_READ_COMMAND_COUNT_CURRENT)—Offset
4168h................................................................................................1227
5.14.142Mask Errors on First N Reads (CPGC2_MASK_ERRS_FIRST_N_READS)—Offset
416Ch ...............................................................................................1227
5.14.143Raster Repository Status (CPGC2_RASTER_REPO_STATUS)—Offset 4170h 1228
5.14.144Error Summary A (CPGC2_ERR_SUMMARY_A)—Offset 4174h ..................1229
5.14.145Error Summary B (CPGC2_ERR_SUMMARY_B)—Offset 4178h ..................1230
5.14.146Future use Reserved (CPGC2_ERR_SUMMARY_C)—Offset 417Ch ..............1231
5.14.147Data Pattern Generation Buffer Control (CPGC_DPAT_BUF_CTL)—Offset 4180h .
1231
5.14.148Data Pattern Generation Configuration (CPGC_DPAT_CFG)—Offset 4184h .1233
5.14.149LFSR Configuration and Lane Rotate (CPGC_DPAT_XTRA_LFSR_CFG)—Offset
4188h................................................................................................1237
5.14.150Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[0])—Offset 418Ch .....
1239
5.14.151Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[1])—Offset 4190h......
1240
5.14.152Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[2])—Offset 4194h......
1240

334818 27
 5.14.153Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[0])—Offset 4198h 1241
5.14.154Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[1])—Offset 419Ch 1244
5.14.155Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[2])—Offset 41A0h 1247
5.14.156Invert and DC Control (CPGC_DPAT_INVDCCTL)—Offset 41A4h ............... 1250
5.14.157Data Invert/DC Enable Low (CPGC_DPAT_INV_DC_MASK_LO)—Offset 41A8h...
1251
5.14.158Data Invert/DC Enable High (CPGC_DPAT_INV_DC_MASK_HI)—Offset 41ACh ..
1252
5.14.159Byte Enable Mask Lower (CPGC_DPAT_DRAMDM)—Offset 41B0h ............. 1252
5.14.160Byte Enable Mask Upper (CPGC_DPAT_XDRAMDM)—Offset 41B4h ........... 1253
5.14.161Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[0])—Offset 41B8h
1254
5.14.162Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[1])—Offset 41BCh
1254
5.14.163Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[2])—Offset 41C0h
1255
5.14.164Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[0])—Offset 41C4h
1255
5.14.165Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[1])—Offset 41C8h
1256
5.14.166Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[2])—Offset 41CCh
1257
5.14.167LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[0])—Offset 41D0h ......... 1258
5.14.168LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[1])—Offset 41D4h ......... 1259
5.14.169LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[2])—Offset 41D8h ......... 1259
5.14.170LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[0])—Offset 41DCh .......... 1260
5.14.171LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[1])—Offset 41E0h ........... 1260
5.14.172LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[2])—Offset 41E4h ........... 1261
5.14.173Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[0])—Offset
41E8h ............................................................................................... 1261
5.14.174Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[1])—Offset
41ECh ............................................................................................... 1262
5.14.175Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[2])—Offset
41F0h ............................................................................................... 1262
5.14.176Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[0])—Offset
41F4h ............................................................................................... 1263
5.14.177Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[1])—Offset
41F8h ............................................................................................... 1264
5.14.178Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[2])—Offset
41FCh ............................................................................................... 1265
5.14.179Extended Pattern Buffer (CPGC_DPAT_EXTBUF[0])—Offset 4200h ........... 1266
5.14.180Extended Pattern Buffer (CPGC_DPAT_EXTBUF[1])—Offset 4204h ........... 1267
5.14.181Extended Pattern Buffer (CPGC_DPAT_EXTBUF[2])—Offset 4208h ........... 1268
5.14.182Extended Pattern Buffer (CPGC_DPAT_EXTBUF[3])—Offset 420Ch ........... 1269
5.14.183Extended Pattern Buffer (CPGC_DPAT_EXTBUF[4])—Offset 4210h ........... 1269
5.14.184Extended Pattern Buffer (CPGC_DPAT_EXTBUF[5])—Offset 4214h ........... 1270
5.14.185Extended Pattern Buffer (CPGC_DPAT_EXTBUF[6])—Offset 4218h ........... 1271
5.14.186Extended Pattern Buffer (CPGC_DPAT_EXTBUF[7])—Offset 421Ch ........... 1272
5.14.187Extended Pattern Buffer (CPGC_DPAT_EXTBUF[8])—Offset 4220h ........... 1273
5.14.188Extended Pattern Buffer (CPGC_DPAT_EXTBUF[9])—Offset 4224h ........... 1274
5.14.189Extended Pattern Buffer (CPGC_DPAT_EXTBUF[10])—Offset 4228h.......... 1274
5.14.190Extended Pattern Buffer (CPGC_DPAT_EXTBUF[11])—Offset 422Ch.......... 1275
5.14.191Extended Pattern Buffer (CPGC_DPAT_EXTBUF[12])—Offset 4230h.......... 1276
5.14.192Extended Pattern Buffer (CPGC_DPAT_EXTBUF[13])—Offset 4234h.......... 1277
5.14.193Extended Pattern Buffer (CPGC_DPAT_EXTBUF[14])—Offset 4238h.......... 1278
5.14.194Extended Pattern Buffer (CPGC_DPAT_EXTBUF[15])—Offset 423Ch.......... 1279

28 334818
 5.14.195Error Checker Control (CPGC_ERR_CTL)—Offset 4240h ...........................1279
5.14.196Lane Error Mask Lower Bytes (CPGC_ERR_LNEN_LO)—Offset 4244h .........1281
5.14.197Lane Error Mask Upper Bytes or Extended Chunk Enable
(CPGC_ERR_LNEN_HI)—Offset 4248h ....................................................1282
5.14.198Lane Error Mask ECC (CPGC_ERR_XLNEN)—Offset 424Ch........................1283
5.14.199Lane Error Status Lower Bytes (CPGC_ERR_STAT03)—Offset 4250h .........1283
5.14.200Lane Error Status Upper Bytes or Extended Chunk Error Status
(CPGC_ERR_STAT47)—Offset 4254h ......................................................1284
5.14.201ECC Lane Error Status (CPGC_ERR_ECC_CHNK_RANK_STAT)—Offset 4258h.....
1285
5.14.202ByteGroup Error Status (CPGC_ERR_BYTE_NTH_PAR_STAT)—Offset 425Ch ......
1286
5.14.203Error Counter Control (CPGC_ERR_CNTRCTL[0])—Offset 4260h ...............1287
5.14.204Error Counter Control (CPGC_ERR_CNTRCTL[1])—Offset 4264h ...............1288
5.14.205Error Counter Control (CPGC_ERR_CNTRCTL[2])—Offset 4268h ...............1289
5.14.206Error Counter Control (CPGC_ERR_CNTRCTL[3])—Offset 426Ch ...............1290
5.14.207Error Counter Control (CPGC_ERR_CNTRCTL[4])—Offset 4270h ...............1291
5.14.208Error Counter Control (CPGC_ERR_CNTRCTL[5])—Offset 4274h ...............1292
5.14.209Error Counter Control (CPGC_ERR_CNTRCTL[6])—Offset 4278h ...............1293
5.14.210Error Counter Control (CPGC_ERR_CNTRCTL[7])—Offset 427Ch ...............1294
5.14.211Error Counter Control (CPGC_ERR_CNTRCTL[8])—Offset 4280h ...............1295
5.14.212Error Counter (CPGC_ERR_CNTR[0])—Offset 4284h ...............................1296
5.14.213Error Counter (CPGC_ERR_CNTR[1])—Offset 4288h ...............................1297
5.14.214Error Counter (CPGC_ERR_CNTR[2])—Offset 428Ch ...............................1298
5.14.215Error Counter (CPGC_ERR_CNTR[3])—Offset 4290h ...............................1299
5.14.216Error Counter (CPGC_ERR_CNTR[4])—Offset 4294h ...............................1299
5.14.217Error Counter (CPGC_ERR_CNTR[5])—Offset 4298h ...............................1300
5.14.218Error Counter (CPGC_ERR_CNTR[6])—Offset 429Ch ...............................1301
5.14.219Error Counter (CPGC_ERR_CNTR[7])—Offset 42A0h ...............................1301
5.14.220Error Counter (CPGC_ERR_CNTR[8])—Offset 42A4h ...............................1302
5.14.221Error Counter Overflow (CPGC_ERR_CNTR_OV)—Offset 42A8h ................1303
5.14.222Error Log Control and Status (CPGC_ERRLOG_CTL_STAT)—Offset 42ACh ..1304
5.14.223Error Log Data Access (CPGC_ERRLOG_DATA)—Offset 42B0h ..................1305
5.14.224Loopback Error Status (CPGC_ERR_TEST_ERR_STAT)—Offset 42B4h ........1306
5.14.225Rank Logical To Physical Map (CPGC_SEQ_RANK_L2P_MAPPING)—Offset 42B8h
1307
5.14.226Bank Logical to Physical Map Low (CPGC_SEQ_BANK_L2P_MAPPING_A)—Offset
42BCh ...............................................................................................1308
5.14.227Bank Logical to Physical Map High (CPGC_SEQ_BANK_L2P_MAPPING_B)—Offset
42C0h ...............................................................................................1309
5.14.228Rank Address Swizzle (CPGC_SEQ_RANK_ADDR_SWIZZLE)—Offset 42C4h1311
5.14.229Bank Address Swizzle (CPGC_SEQ_BANK_ADDR_SWIZZLE)—Offset 42C8h1312
5.14.230Row Address Swizzle Low (CPGC_SEQ_ROW_ADDR_SWIZZLE_A)—Offset 42CCh
1312
5.14.231Row Address Swizzle Mid (CPGC_SEQ_ROW_ADDR_SWIZZLE_B)—Offset 42D0h
1314
5.14.232Row Address Swizzle High (CPGC_SEQ_ROW_ADDR_SWIZZLE_C)—Offset
42D4h ...............................................................................................1315
5.14.233Row Address XOR (CPGC_SEQ_ROW_ADDR_SWIZZLE_X)—Offset 42D8h ..1316
5.14.234Column Address Swizzle Low (CPGC_SEQ_COL_ADDR_SWIZZLE_A)—Offset
42DCh ...............................................................................................1317
5.14.235Column Address Swizzle High (CPGC_SEQ_COL_ADDR_SWIZZLE_B)—Offset
42E0h................................................................................................1318
5.14.236DQ Inversion Lookup Data Low (CPGC_SEQ_ROW_ADDR_DQ_MAP0)—Offset
42E8h................................................................................................1319

334818 29
 5.14.237DQ Inversion Lookup Data High (CPGC_SEQ_ROW_ADDR_DQ_MAP1)—Offset
42ECh ............................................................................................... 1320
5.15 Registers Summary........................................................................................ 1321
5.15.1 CADB Control (CPGC_CADB_CTL)—Offset 46F0h ..................................... 1322
5.15.2 CADB MRS Configuration (CPGC_CADB_MRSCFG)—Offset 46F4h............... 1325
5.15.3 CADB Configuration (CPGC_CADB_CFG)—Offset 46F8h ............................ 1326
5.15.4 CADB Unisequencer 0 Pattern Buffer (CPGC_CADB_UNISEQ0_PBUF)—Offset
46FCh ............................................................................................... 1327
5.15.5 CADB Unisequencer 1 Pattern Buffer (CPGC_CADB_UNISEQ1_PBUF)—Offset
4700h ............................................................................................... 1328
5.15.6 CADB Unisequencer 2 Pattern Buffer (CPGC_CADB_UNISEQ2_PBUF)—Offset
4704h ............................................................................................... 1328
5.15.7 CADB LMN 0 Settings (CPGC_CADB_UNISEQ0_LMN)—Offset 4708h........... 1329
5.15.8 CADB LMN 1 Settings (CPGC_CADB_UNISEQ1_LMN)—Offset 470Ch .......... 1330
5.15.9 CADB LMN 2 Settings (CPGC_CADB_UNISEQ2_LMN)—Offset 4710h........... 1331
5.15.10CADB Select Unisequencer 0 Pattern Buffer
(CPGC_CADB_SEL_UNISEQ0_PBUF)—Offset 4714h ................................. 1332
5.15.11CADB Select Unisequencer 1 Pattern Buffer
(CPGC_CADB_SEL_UNISEQ1_PBUF)—Offset 4718h ................................. 1333
5.15.12CADB Select Unisequencer 2 Pattern Buffer
(CPGC_CADB_SEL_UNISEQ2_PBUF)—Offset 471Ch ................................. 1333
5.15.13CADB Buffer A (CPGC_CADB_BUFA[0])—Offset 4720h ............................. 1334
5.15.14CADB Buffer A (CPGC_CADB_BUFA[1])—Offset 4724h ............................. 1334
5.15.15CADB Buffer A (CPGC_CADB_BUFA[2])—Offset 4728h ............................. 1335
5.15.16CADB Buffer A (CPGC_CADB_BUFA[3])—Offset 472Ch ............................. 1336
5.15.17CADB Buffer A (CPGC_CADB_BUFA[4])—Offset 4730h ............................. 1337
5.15.18CADB Buffer A (CPGC_CADB_BUFA[5])—Offset 4734h ............................. 1337
5.15.19CADB Buffer A (CPGC_CADB_BUFA[6])—Offset 4738h ............................. 1338
5.15.20CADB Buffer A (CPGC_CADB_BUFA[7])—Offset 473Ch ............................. 1339
5.15.21CADB Buffer B (CPGC_CADB_BUFB[0])—Offset 4740h ............................. 1339
5.15.22CADB Buffer B (CPGC_CADB_BUFB[1])—Offset 4744h ............................. 1340
5.15.23CADB Buffer B (CPGC_CADB_BUFB[2])—Offset 4748h ............................. 1341
5.15.24CADB Buffer B (CPGC_CADB_BUFB[3])—Offset 474Ch ............................. 1342
5.15.25CADB Buffer B (CPGC_CADB_BUFB[4])—Offset 4750h ............................. 1343
5.15.26CADB Buffer B (CPGC_CADB_BUFB[5])—Offset 4754h ............................. 1344
5.15.27CADB Buffer B (CPGC_CADB_BUFB[6])—Offset 4758h ............................. 1345
5.15.28CADB Buffer B (CPGC_CADB_BUFB[7])—Offset 475Ch ............................. 1346
5.15.29CADB Deselect Uniseq 0 Status (CPGC_CADB_UNISEQ0STAT)—Offset 4760h.....
1347
5.15.30CADB Deselect Uniseq 1 Status (CPGC_CADB_UNISEQ1STAT)—Offset 4764h.....
1348
5.15.31CADB Deselect Uniseq 2 Status (CPGC_CADB_UNISEQ2STAT)—Offset 4768h.....
1348
5.16 Registers Summary........................................................................................ 1351
5.16.1 Address Decode Repeats (CPGC2_ADDRESS_CONTROL)—Offset 4418h...... 1359
5.16.2 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[0])—Offset 441Ch .. 1360
5.16.3 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[1])—Offset 441Dh .. 1362
5.16.4 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[2])—Offset 441Eh .. 1364
5.16.5 Address Instruction (CPGC2_ADDRESS_INSTRUCTION[3])—Offset 441Fh... 1365
5.16.6 Data Instruction (CPGC2_DATA_INSTRUCTION[0])—Offset 4420h ............. 1367
5.16.7 Data Instruction (CPGC2_DATA_INSTRUCTION[1])—Offset 4421h ............. 1368
5.16.8 Data Instruction (CPGC2_DATA_INSTRUCTION[2])—Offset 4422h ............. 1369
5.16.9 Data Instruction (CPGC2_DATA_INSTRUCTION[3])—Offset 4423h ............. 1370
5.16.10Data Rotation Repeats (CPGC2_DATA_CONTROL)—Offset 4424h............... 1371
5.16.11Address and Data Repeats Status (CPGC2_ADDRESS_DATA_STATUS)—Offset
4428h ............................................................................................... 1372

30 334818
 5.16.12Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[0])—Offset 442Ch ....
1373
5.16.13Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[1])—Offset 442Dh ....
1374
5.16.14Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[2])—Offset 442Eh ....
1375
5.16.15Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[3])—Offset 442Fh ....
1376
5.16.16Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[4])—Offset 4430h ....
1377
5.16.17Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[5])—Offset 4431h ....
1378
5.16.18Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[6])—Offset 4432h ....
1379
5.16.19Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[7])—Offset 4433h ....
1380
5.16.20Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[0])—
Offset 4434h ......................................................................................1381
5.16.21Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[1])—
Offset 4435h ......................................................................................1383
5.16.22Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[2])—
Offset 4436h ......................................................................................1385
5.16.23Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[3])—
Offset 4437h ......................................................................................1387
5.16.24Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[4])—
Offset 4438h ......................................................................................1389
5.16.25Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[5])—
Offset 4439h ......................................................................................1391
5.16.26Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[6])—
Offset 443Ah ......................................................................................1393
5.16.27Algorithm Instruction Control (CPGC2_ALGORITHM_INSTRUCTION_CTRL[7])—
Offset 443Bh ......................................................................................1395
5.16.28Wait Timer Current (CPGC2_ALGORITHM_WAIT_COUNT_CURRENT)—Offset
443Ch ...............................................................................................1397
5.16.29Algorithm Wait Event Control (CPGC2_ALGORITHM_WAIT_EVENT_CONTROL)—
Offset 4440h ......................................................................................1398
5.16.30Base Repeats (CPGC2_BASE_REPEATS)—Offset 4444h .............................1399
5.16.31Current Base Repeats (CPGC2_BASE_REPEATS_CURRENT)—Offset 4448h ..1399
5.16.32Base Column Repeats (CPGC2_BASE_COL_REPEATS)—Offset 444Ch ..........1400
5.16.33Block Repeats (CPGC2_BLOCK_REPEATS)—Offset 4450h ..........................1400
5.16.34Current Block Repeats (CPGC2_BLOCK_REPEATS_CURRENT)—Offset 4454h1401
5.16.35Command Instruction (CPGC2_COMMAND_INSTRUCTION[0])—Offset 4458h......
1401
5.16.36Command Instruction (CPGC2_COMMAND_INSTRUCTION[1])—Offset 4459h......
1403
5.16.37Command Instruction (CPGC2_COMMAND_INSTRUCTION[2])—Offset 445Ah .....
1404
5.16.38Command Instruction (CPGC2_COMMAND_INSTRUCTION[3])—Offset 445Bh .....
1406
5.16.39Command Instruction (CPGC2_COMMAND_INSTRUCTION[4])—Offset 445Ch .....
1407
5.16.40Command Instruction (CPGC2_COMMAND_INSTRUCTION[5])—Offset 445Dh .....
1408
5.16.41Command Instruction (CPGC2_COMMAND_INSTRUCTION[6])—Offset 445Eh......
1410
5.16.42Command Instruction (CPGC2_COMMAND_INSTRUCTION[7])—Offset 445Fh ......
1411

334818 31
 5.16.43Command Instruction (CPGC2_COMMAND_INSTRUCTION[8])—Offset 4460h .....
1413
5.16.44Command Instruction (CPGC2_COMMAND_INSTRUCTION[9])—Offset 4461h .....
1414
5.16.45Command Instruction (CPGC2_COMMAND_INSTRUCTION[10])—Offset 4462h ...
1415
5.16.46Command Instruction (CPGC2_COMMAND_INSTRUCTION[11])—Offset 4463h ...
1417
5.16.47Command Instruction (CPGC2_COMMAND_INSTRUCTION[12])—Offset 4464h ...
1418
5.16.48Command Instruction (CPGC2_COMMAND_INSTRUCTION[13])—Offset 4465h ...
1420
5.16.49Command Instruction (CPGC2_COMMAND_INSTRUCTION[14])—Offset 4466h ...
1421
5.16.50Command Instruction (CPGC2_COMMAND_INSTRUCTION[15])—Offset 4467h ...
1422
5.16.51Command Instruction (CPGC2_COMMAND_INSTRUCTION[16])—Offset 4468h ...
1424
5.16.52Command Instruction (CPGC2_COMMAND_INSTRUCTION[17])—Offset 4469h ...
1425
5.16.53Command Instruction (CPGC2_COMMAND_INSTRUCTION[18])—Offset 446Ah ...
1427
5.16.54Command Instruction (CPGC2_COMMAND_INSTRUCTION[19])—Offset 446Bh ...
1428
5.16.55Command Instruction (CPGC2_COMMAND_INSTRUCTION[20])—Offset 446Ch ...
1429
5.16.56Command Instruction (CPGC2_COMMAND_INSTRUCTION[21])—Offset 446Dh ...
1431
5.16.57Command Instruction (CPGC2_COMMAND_INSTRUCTION[22])—Offset 446Eh ...
1432
5.16.58Command Instruction (CPGC2_COMMAND_INSTRUCTION[23])—Offset 446Fh ...
1434
5.16.59Hammer Repeats (CPGC2_HAMMER_REPEATS)—Offset 4470h .................. 1435
5.16.60Current Hammer Repeats (CPGC2_HAMMER_REPEATS_CURRENT)—Offset 4474h
1435
5.16.61Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[0])—
Offset 4478h ...................................................................................... 1436
5.16.62Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[1])—
Offset 4479h ...................................................................................... 1438
5.16.63Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[2])—
Offset 447Ah...................................................................................... 1439
5.16.64Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[3])—
Offset 447Bh...................................................................................... 1441
5.16.65Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[4])—
Offset 447Ch...................................................................................... 1442
5.16.66Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[5])—
Offset 447Dh ..................................................................................... 1444
5.16.67Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[6])—
Offset 447Eh ...................................................................................... 1445
5.16.68Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[7])—
Offset 447Fh ...................................................................................... 1447
5.16.69Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[8])—
Offset 4480h ...................................................................................... 1448
5.16.70Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[9])—
Offset 4481h ...................................................................................... 1450
5.16.71Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[10])—
Offset 4482h ...................................................................................... 1451

32 334818
 5.16.72Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[11])—
Offset 4483h ......................................................................................1453
5.16.73Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[12])—
Offset 4484h ......................................................................................1454
5.16.74Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[13])—
Offset 4485h ......................................................................................1456
5.16.75Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[14])—
Offset 4486h ......................................................................................1457
5.16.76Offset Address Instruction (CPGC2_OFFSET_ADDRESS_INSTRUCTION[15])—
Offset 4487h ......................................................................................1459
5.16.77Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[0])—
Offset 4488h ......................................................................................1460
5.16.78Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[1])—
Offset 4489h ......................................................................................1461
5.16.79Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[2])—
Offset 448Ah ......................................................................................1462
5.16.80Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[3])—
Offset 448Bh ......................................................................................1463
5.16.81Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[4])—
Offset 448Ch ......................................................................................1465
5.16.82Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[5])—
Offset 448Dh ......................................................................................1466
5.16.83Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[6])—
Offset 448Eh ......................................................................................1467
5.16.84Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[7])—
Offset 448Fh.......................................................................................1468
5.16.85Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[8])—
Offset 4490h ......................................................................................1469
5.16.86Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[9])—
Offset 4491h ......................................................................................1470
5.16.87Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[10])—
Offset 4492h ......................................................................................1471
5.16.88Offset Command Instruction (CPGC2_OFFSET_COMMAND_INSTRUCTION[11])—
Offset 4493h ......................................................................................1472
5.16.89Offset Repeats (CPGC2_OFFSET_REPEATS[0])—Offset 4494h....................1473
5.16.90Offset Repeats (CPGC2_OFFSET_REPEATS[1])—Offset 4498h....................1474
5.16.91Current Offset Repeats (CPGC2_OFFSET_REPEATS_CURRENT)—Offset 449Ch ....
1474
5.16.92Region Low Row Address (CPGC2_REGION_LOW_ROW)—Offset 44A0h.......1475
5.16.93Region Low Col Address (CPGC2_REGION_LOW_COL)—Offset 44A4h .........1476
5.16.94Block Low Row Current (CPGC2_BLOCK_ORIGIN_ROW_CURRENT)—Offset 44A8h
1476
5.16.95Current Base Address Rank and Column
(CPGC2_BASE_ADDRESS_COL_RANK_CURRENT)—Offset 44ACh ...............1477
5.16.96Current Base Address Bank and Row
(CPGC2_BASE_ADDRESS_ROW_BANK_CURRENT)—Offset 44B0h ..............1478
5.16.97Current Offset Address Column (CPGC2_OFFSET_ADDRESS_COL_CURRENT)—
Offset 44B4h ......................................................................................1478
5.16.98Current Offset Address Row (CPGC2_OFFSET_ADDRESS_ROW_CURRENT)—
Offset 44B8h ......................................................................................1479
5.16.99Address Size (CPGC2_ADDRESS_SIZE)—Offset 44BCh .............................1480
5.16.100Base Address Control (CPGC2_BASE_ADDRESS_CONTROL)—Offset 44C0h 1481
5.16.101Address PRBS Control (CPGC2_ADDRESS_PRBS_CONTROL)—Offset 44C4h ......
1483
5.16.102Address PRBS Seed (CPGC2_ADDRESS_PRBS_SEED)—Offset 44C8h ........1484
5.16.103Current Address PRBS Status (CPGC2_ADDRESS_PRBS_CURRENT)—Offset
44CCh ...............................................................................................1485

334818 33
 5.16.104Address PRBS Save (CPGC2_ADDRESS_PRBS_SAVE)—Offset 44D0h ........ 1485
5.16.105Command FSM Current State (CPGC2_CMD_FSM_CURRENT)—Offset 44D4h ....
1486
5.16.106Algorithm Wait Timer Configuration (CPGC2_WAIT_2_START_CONFIG)—Offset
44D8h............................................................................................... 1487
5.16.107VISA Mux Selection (CPGC2_VISA_MUX_SEL)—Offset 44DCh .................. 1488
5.16.108Loopback Squencer Configuration (CPGC_LB_SEQ_CFG)—Offset 44E0h .... 1489
5.16.109Loopback Sequencer Control (CPGC_LB_SEQ_CTL)—Offset 44E4h ........... 1491
5.16.110Loopback Loopcount Tx Status (CPGC_LB_SEQ_LOOPCOUNT_TX_STATUS)—
Offset 44E8h ...................................................................................... 1493
5.16.111Loopback Loopcount Rx Status (CPGC_LB_SEQ_LOOPCOUNT_RX_STATUS)—
Offset 44ECh...................................................................................... 1494
5.16.112Pattern Length Status (CPGC_LB_SEQ_PL_RX_STATUS)—Offset 44F0h .... 1494
5.16.113Refresh Control (CPGC_MISC_REFRESH_CTL)—Offset 44F4h................... 1495
5.16.114ZQ Control (CPGC_MISC_ZQ_CTL)—Offset 44F8h .................................. 1496
5.16.115ODT Control (CPGC_MISC_ODT_CTL)—Offset 44FCh .............................. 1496
5.16.116CKE Control (CPGC_MISC_CKE_CTL)—Offset 4500h ............................... 1497
5.16.117Command Rate (CPGC_MISC_CMD_RATE)—Offset 4504h ....................... 1498
5.16.118External Trigger Control (CPGC_MISC_EXT_TRIGGER)—Offset 4508h ....... 1499
5.16.119Sequence Control (CPGC_SEQ_CTL)—Offset 450Ch................................ 1499
5.16.120Sequence Configuration A (CPGC_SEQ_CFG_A)—Offset 4510h ................ 1500
5.16.121Sequence Configuration B (CPGC_SEQ_CFG_B)—Offset 4514h ................ 1503
5.16.122Sequence Status (CPGC_SEQ_STATUS)—Offset 4518h ........................... 1503
5.16.123Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[0])—Offset 4520h
1504
5.16.124Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[1])—Offset 4524h
1505
5.16.125Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[2])—Offset 4528h
1505
5.16.126Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[3])—Offset 452Ch
1506
5.16.127Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[4])—Offset 4530h
1506
5.16.128Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[5])—Offset 4534h
1507
5.16.129Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[6])—Offset 4538h
1508
5.16.130Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[7])—Offset 453Ch
1508
5.16.131Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[8])—Offset 4540h
1509
5.16.132Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[9])—Offset 4544h
1509
5.16.133Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[10])—Offset
4548h ............................................................................................... 1510
5.16.134Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[11])—Offset
454Ch ............................................................................................... 1511
5.16.135Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[12])—Offset
4550h ............................................................................................... 1511
5.16.136Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[13])—Offset
4554h ............................................................................................... 1512
5.16.137Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[14])—Offset
4558h ............................................................................................... 1512
5.16.138Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[15])—Offset
455Ch ............................................................................................... 1513
5.16.139Mode3 Fail Status LSB (CPGC2_RASTER_REPO_CONTENT_ECC1)—Offset 4560h
1514

34 334818
 5.16.140Mode3 Fail Status MSB (CPGC2_RASTER_REPO_CONTENT_ECC2)—Offset 4564h
1515
5.16.141Read Command Count (CPGC2_READ_COMMAND_COUNT_CURRENT)—Offset
4568h................................................................................................1517
5.16.142Mask Errors on First N Reads (CPGC2_MASK_ERRS_FIRST_N_READS)—Offset
456Ch ...............................................................................................1517
5.16.143Raster Repository Status (CPGC2_RASTER_REPO_STATUS)—Offset 4570h 1518
5.16.144Error Summary A (CPGC2_ERR_SUMMARY_A)—Offset 4574h ..................1519
5.16.145Error Summary B (CPGC2_ERR_SUMMARY_B)—Offset 4578h ..................1520
5.16.146Future use Reserved (CPGC2_ERR_SUMMARY_C)—Offset 457Ch ..............1521
5.16.147Data Pattern Generation Buffer Control (CPGC_DPAT_BUF_CTL)—Offset 4580h .
1521
5.16.148Data Pattern Generation Configuration (CPGC_DPAT_CFG)—Offset 4584h .1523
5.16.149LFSR Configuration and Lane Rotate (CPGC_DPAT_XTRA_LFSR_CFG)—Offset
4588h................................................................................................1527
5.16.150Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[0])—Offset 458Ch .....
1529
5.16.151Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[1])—Offset 4590h......
1530
5.16.152Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[2])—Offset 4594h......
1530
5.16.153Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[0])—Offset 4598h .1531
5.16.154Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[1])—Offset 459Ch.1534
5.16.155Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[2])—Offset 45A0h.1537
5.16.156Invert and DC Control (CPGC_DPAT_INVDCCTL)—Offset 45A4h ...............1540
5.16.157Data Invert/DC Enable Low (CPGC_DPAT_INV_DC_MASK_LO)—Offset 45A8h ...
1541
5.16.158Data Invert/DC Enable High (CPGC_DPAT_INV_DC_MASK_HI)—Offset 45ACh...
1542
5.16.159Byte Enable Mask Lower (CPGC_DPAT_DRAMDM)—Offset 45B0h ..............1542
5.16.160Byte Enable Mask Upper (CPGC_DPAT_XDRAMDM)—Offset 45B4h ............1543
5.16.161Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[0])—Offset 45B8h
1544
5.16.162Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[1])—Offset 45BCh
1544
5.16.163Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[2])—Offset 45C0h
1545
5.16.164Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[0])—Offset 45C4h
1545
5.16.165Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[1])—Offset 45C8h
1546
5.16.166Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[2])—Offset 45CCh
1547
5.16.167LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[0])—Offset 45D0h ..........1548
5.16.168LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[1])—Offset 45D4h ..........1549
5.16.169LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[2])—Offset 45D8h ..........1549
5.16.170LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[0])—Offset 45DCh ...........1550
5.16.171LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[1])—Offset 45E0h ...........1550
5.16.172LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[2])—Offset 45E4h ...........1551
5.16.173Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[0])—Offset
45E8h................................................................................................1551
5.16.174Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[1])—Offset
45ECh ...............................................................................................1552
5.16.175Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[2])—Offset
45F0h................................................................................................1552

334818 35
 5.16.176Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[0])—Offset
45F4h ............................................................................................... 1553
5.16.177Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[1])—Offset
45F8h ............................................................................................... 1554
5.16.178Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[2])—Offset
45FCh ............................................................................................... 1555
5.16.179Extended Pattern Buffer (CPGC_DPAT_EXTBUF[0])—Offset 4600h ........... 1556
5.16.180Extended Pattern Buffer (CPGC_DPAT_EXTBUF[1])—Offset 4604h ........... 1557
5.16.181Extended Pattern Buffer (CPGC_DPAT_EXTBUF[2])—Offset 4608h ........... 1558
5.16.182Extended Pattern Buffer (CPGC_DPAT_EXTBUF[3])—Offset 460Ch ........... 1559
5.16.183Extended Pattern Buffer (CPGC_DPAT_EXTBUF[4])—Offset 4610h ........... 1559
5.16.184Extended Pattern Buffer (CPGC_DPAT_EXTBUF[5])—Offset 4614h ........... 1560
5.16.185Extended Pattern Buffer (CPGC_DPAT_EXTBUF[6])—Offset 4618h ........... 1561
5.16.186Extended Pattern Buffer (CPGC_DPAT_EXTBUF[7])—Offset 461Ch ........... 1562
5.16.187Extended Pattern Buffer (CPGC_DPAT_EXTBUF[8])—Offset 4620h ........... 1563
5.16.188Extended Pattern Buffer (CPGC_DPAT_EXTBUF[9])—Offset 4624h ........... 1564
5.16.189Extended Pattern Buffer (CPGC_DPAT_EXTBUF[10])—Offset 4628h.......... 1564
5.16.190Extended Pattern Buffer (CPGC_DPAT_EXTBUF[11])—Offset 462Ch.......... 1565
5.16.191Extended Pattern Buffer (CPGC_DPAT_EXTBUF[12])—Offset 4630h.......... 1566
5.16.192Extended Pattern Buffer (CPGC_DPAT_EXTBUF[13])—Offset 4634h.......... 1567
5.16.193Extended Pattern Buffer (CPGC_DPAT_EXTBUF[14])—Offset 4638h.......... 1568
5.16.194Extended Pattern Buffer (CPGC_DPAT_EXTBUF[15])—Offset 463Ch.......... 1569
5.16.195Error Checker Control (CPGC_ERR_CTL)—Offset 4640h .......................... 1569
5.16.196Lane Error Mask Lower Bytes (CPGC_ERR_LNEN_LO)—Offset 4644h ........ 1571
5.16.197Lane Error Mask Upper Bytes or Extended Chunk Enable
(CPGC_ERR_LNEN_HI)—Offset 4648h.................................................... 1572
5.16.198Lane Error Mask ECC (CPGC_ERR_XLNEN)—Offset 464Ch ....................... 1573
5.16.199Lane Error Status Lower Bytes (CPGC_ERR_STAT03)—Offset 4650h......... 1573
5.16.200Lane Error Status Upper Bytes or Extended Chunk Error Status
(CPGC_ERR_STAT47)—Offset 4654h ..................................................... 1574
5.16.201ECC Lane Error Status (CPGC_ERR_ECC_CHNK_RANK_STAT)—Offset 4658h ....
1575
5.16.202ByteGroup Error Status (CPGC_ERR_BYTE_NTH_PAR_STAT)—Offset 465Ch .....
1576
5.16.203Error Counter Control (CPGC_ERR_CNTRCTL[0])—Offset 4660h............... 1577
5.16.204Error Counter Control (CPGC_ERR_CNTRCTL[1])—Offset 4664h............... 1578
5.16.205Error Counter Control (CPGC_ERR_CNTRCTL[2])—Offset 4668h............... 1579
5.16.206Error Counter Control (CPGC_ERR_CNTRCTL[3])—Offset 466Ch............... 1580
5.16.207Error Counter Control (CPGC_ERR_CNTRCTL[4])—Offset 4670h............... 1581
5.16.208Error Counter Control (CPGC_ERR_CNTRCTL[5])—Offset 4674h............... 1582
5.16.209Error Counter Control (CPGC_ERR_CNTRCTL[6])—Offset 4678h............... 1583
5.16.210Error Counter Control (CPGC_ERR_CNTRCTL[7])—Offset 467Ch............... 1584
5.16.211Error Counter Control (CPGC_ERR_CNTRCTL[8])—Offset 4680h............... 1585
5.16.212Error Counter (CPGC_ERR_CNTR[0])—Offset 4684h ............................... 1586
5.16.213Error Counter (CPGC_ERR_CNTR[1])—Offset 4688h ............................... 1587
5.16.214Error Counter (CPGC_ERR_CNTR[2])—Offset 468Ch............................... 1588
5.16.215Error Counter (CPGC_ERR_CNTR[3])—Offset 4690h ............................... 1589
5.16.216Error Counter (CPGC_ERR_CNTR[4])—Offset 4694h ............................... 1589
5.16.217Error Counter (CPGC_ERR_CNTR[5])—Offset 4698h ............................... 1590
5.16.218Error Counter (CPGC_ERR_CNTR[6])—Offset 469Ch............................... 1591
5.16.219Error Counter (CPGC_ERR_CNTR[7])—Offset 46A0h............................... 1591
5.16.220Error Counter (CPGC_ERR_CNTR[8])—Offset 46A4h............................... 1592
5.16.221Error Counter Overflow (CPGC_ERR_CNTR_OV)—Offset 46A8h ................ 1593
5.16.222Error Log Control and Status (CPGC_ERRLOG_CTL_STAT)—Offset 46ACh.. 1594
5.16.223Error Log Data Access (CPGC_ERRLOG_DATA)—Offset 46B0h ................. 1595

36 334818
 5.16.224Loopback Error Status (CPGC_ERR_TEST_ERR_STAT)—Offset 46B4h ........1596
5.16.225Rank Logical To Physical Map (CPGC_SEQ_RANK_L2P_MAPPING)—Offset 46B8h
1597
5.16.226Bank Logical to Physical Map Low (CPGC_SEQ_BANK_L2P_MAPPING_A)—Offset
46BCh ...............................................................................................1598
5.16.227Bank Logical to Physical Map High (CPGC_SEQ_BANK_L2P_MAPPING_B)—Offset
46C0h ...............................................................................................1599
5.16.228Rank Address Swizzle (CPGC_SEQ_RANK_ADDR_SWIZZLE)—Offset 46C4h1601
5.16.229Bank Address Swizzle (CPGC_SEQ_BANK_ADDR_SWIZZLE)—Offset 46C8h1602
5.16.230Row Address Swizzle Low (CPGC_SEQ_ROW_ADDR_SWIZZLE_A)—Offset 46CCh
1602
5.16.231Row Address Swizzle Mid (CPGC_SEQ_ROW_ADDR_SWIZZLE_B)—Offset 46D0h
1604
5.16.232Row Address Swizzle High (CPGC_SEQ_ROW_ADDR_SWIZZLE_C)—Offset
46D4h ...............................................................................................1605
5.16.233Row Address XOR (CPGC_SEQ_ROW_ADDR_SWIZZLE_X)—Offset 46D8h ..1606
5.16.234Column Address Swizzle Low (CPGC_SEQ_COL_ADDR_SWIZZLE_A)—Offset
46DCh ...............................................................................................1607
5.16.235Column Address Swizzle High (CPGC_SEQ_COL_ADDR_SWIZZLE_B)—Offset
46E0h................................................................................................1608
5.16.236DQ Inversion Lookup Data Low (CPGC_SEQ_ROW_ADDR_DQ_MAP0)—Offset
46E8h................................................................................................1609
5.16.237DQ Inversion Lookup Data High (CPGC_SEQ_ROW_ADDR_DQ_MAP1)—Offset
46ECh ...............................................................................................1610
5.17 Registers Summary ........................................................................................1611
5.17.1 Noncached Region Control (B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset
6B60h ...............................................................................................1611
5.18 Registers Summary ........................................................................................1613
5.18.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1000h .............................1614
5.18.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1008h ..........................1616
5.18.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 100Ch ..........................1617
5.18.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1010h ..........................1618
5.18.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1014h ..........................1619
5.18.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1018h ..........................1620
5.18.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 101Ch ..........................1621
5.18.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1020h ..........................1623
5.18.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1024h ..........................1624
5.18.10DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1028h ..........................1625
5.18.11D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 102Ch...................1626
5.18.12D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1030h ..........1627
5.18.13D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1034h ..........1629
5.18.14DRAM Refresh Control (D_CR_DRFC)—Offset 1038h.................................1631
5.18.15D-Unit Scheduler (D_CR_DSCH)—Offset 103Ch .......................................1633
5.18.16DRAM Calibration Control (D_CR_DCAL)—Offset 1040h ............................1635
5.18.17VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 104Ch ...................1636
5.18.18Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1050h..
1637
5.18.19TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1054h .............1638
5.18.20Data Scrambler (D_CR_SCRAMCTRL)—Offset 10A4h ................................1639
5.18.21Error Injection Address Register (D_CR_ERR_INJ)—Offset 10ACh ..............1640
5.18.22Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 10B0h.........1641
5.18.23Error Log Register (D_CR_ERR_ECC_LOG)—Offset 10B4h .........................1642
5.18.24D-Unit Status (D_CR_DFUSESTAT)—Offset 10BCh ...................................1643
5.18.25Major Mode Control (D_CR_MMC)—Offset 1124h .....................................1643
5.18.26Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1128h
1644

334818 37
 5.18.27Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 112Ch
1645
5.18.28Access Class Initial Priority (D_CR_ACCIP)—Offset 1130h......................... 1646
5.18.29Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1134h.....
1647
5.18.30Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1138h.....
1647
5.18.31Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 113Ch ....
1648
5.18.32Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1140h.....
1649
5.18.33Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1144h.....
1650
5.18.34Deadline Threshold (D_CR_DL_THRS)—Offset 1148h............................... 1651
5.18.35Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 114Ch .......... 1651
5.18.36DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1154h ....... 1653
5.18.37DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1180h ..... 1654
5.18.38MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1184h............. 1655
5.19 Registers Summary........................................................................................ 1657
5.19.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1200h............................. 1658
5.19.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1208h ......................... 1660
5.19.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 120Ch ......................... 1661
5.19.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1210h ......................... 1662
5.19.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1214h ......................... 1663
5.19.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1218h ......................... 1664
5.19.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 121Ch ......................... 1665
5.19.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1220h ......................... 1667
5.19.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1224h ......................... 1668
5.19.10DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1228h ......................... 1669
5.19.11D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 122Ch .................. 1670
5.19.12D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1230h.......... 1671
5.19.13D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1234h.......... 1673
5.19.14DRAM Refresh Control (D_CR_DRFC)—Offset 1238h ................................ 1675
5.19.15D-Unit Scheduler (D_CR_DSCH)—Offset 123Ch ...................................... 1677
5.19.16DRAM Calibration Control (D_CR_DCAL)—Offset 1240h............................ 1679
5.19.17VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 124Ch .................. 1680
5.19.18Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1250h .
1681
5.19.19TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1254h ............. 1682
5.19.20Data Scrambler (D_CR_SCRAMCTRL)—Offset 12A4h................................ 1683
5.19.21Error Injection Address Register (D_CR_ERR_INJ)—Offset 12ACh .............. 1684
5.19.22Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 12B0h ........ 1685
5.19.23Error Log Register (D_CR_ERR_ECC_LOG)—Offset 12B4h ........................ 1686
5.19.24D-Unit Status (D_CR_DFUSESTAT)—Offset 12BCh................................... 1687
5.19.25Major Mode Control (D_CR_MMC)—Offset 1324h..................................... 1687
5.19.26Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1328h
1688
5.19.27Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 132Ch
1689
5.19.28Access Class Initial Priority (D_CR_ACCIP)—Offset 1330h......................... 1690
5.19.29Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1334h.....
1691
5.19.30Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1338h.....
1691
5.19.31Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 133Ch ....
1692

38 334818
 5.19.32Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1340h .....
1693
5.19.33Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1344h .....
1694
5.19.34Deadline Threshold (D_CR_DL_THRS)—Offset 1348h ...............................1695
5.19.35Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 134Ch ...........1695
5.19.36DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1354h........1697
5.19.37DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1380h ......1698
5.19.38MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1384h .............1699
5.20 Registers Summary ........................................................................................1701
5.20.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1400h .............................1702
5.20.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1408h ..........................1704
5.20.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 140Ch ..........................1705
5.20.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1410h ..........................1706
5.20.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1414h ..........................1707
5.20.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1418h ..........................1708
5.20.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 141Ch ..........................1709
5.20.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1420h ..........................1711
5.20.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1424h ..........................1712
5.20.10DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1428h ..........................1713
5.20.11D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 142Ch...................1714
5.20.12D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1430h ..........1715
5.20.13D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1434h ..........1717
5.20.14DRAM Refresh Control (D_CR_DRFC)—Offset 1438h.................................1719
5.20.15D-Unit Scheduler (D_CR_DSCH)—Offset 143Ch .......................................1721
5.20.16DRAM Calibration Control (D_CR_DCAL)—Offset 1440h ............................1723
5.20.17VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 144Ch ...................1724
5.20.18Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1450h..
1725
5.20.19TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1454h .............1726
5.20.20Data Scrambler (D_CR_SCRAMCTRL)—Offset 14A4h ................................1727
5.20.21Error Injection Address Register (D_CR_ERR_INJ)—Offset 14ACh ..............1728
5.20.22Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 14B0h.........1729
5.20.23Error Log Register (D_CR_ERR_ECC_LOG)—Offset 14B4h .........................1730
5.20.24D-Unit Status (D_CR_DFUSESTAT)—Offset 14BCh ...................................1731
5.20.25Major Mode Control (D_CR_MMC)—Offset 1524h .....................................1731
5.20.26Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1528h
1732
5.20.27Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 152Ch
1733
5.20.28Access Class Initial Priority (D_CR_ACCIP)—Offset 1530h .........................1734
5.20.29Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1534h .....
1735
5.20.30Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1538h .....
1735
5.20.31Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 153Ch .....
1736
5.20.32Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1540h .....
1737
5.20.33Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1544h .....
1738
5.20.34Deadline Threshold (D_CR_DL_THRS)—Offset 1548h ...............................1739
5.20.35Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 154Ch ...........1739
5.20.36DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1554h........1741
5.20.37DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1580h ......1742
5.20.38MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1584h .............1743

334818 39
 5.21 Registers Summary........................................................................................ 1745
5.21.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1600h............................. 1746
5.21.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1608h ......................... 1748
5.21.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 160Ch ......................... 1749
5.21.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1610h ......................... 1750
5.21.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1614h ......................... 1751
5.21.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1618h ......................... 1752
5.21.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 161Ch ......................... 1753
5.21.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1620h ......................... 1755
5.21.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1624h ......................... 1756
5.21.10DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1628h ......................... 1757
5.21.11D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 162Ch .................. 1758
5.21.12D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1630h.......... 1759
5.21.13D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1634h.......... 1761
5.21.14DRAM Refresh Control (D_CR_DRFC)—Offset 1638h ................................ 1763
5.21.15D-Unit Scheduler (D_CR_DSCH)—Offset 163Ch ...................................... 1765
5.21.16DRAM Calibration Control (D_CR_DCAL)—Offset 1640h............................ 1767
5.21.17VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 164Ch .................. 1768
5.21.18Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1650h .
1769
5.21.19TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1654h ............. 1770
5.21.20Data Scrambler (D_CR_SCRAMCTRL)—Offset 16A4h................................ 1771
5.21.21Error Injection Address Register (D_CR_ERR_INJ)—Offset 16ACh .............. 1772
5.21.22Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 16B0h ........ 1773
5.21.23Error Log Register (D_CR_ERR_ECC_LOG)—Offset 16B4h ........................ 1774
5.21.24D-Unit Status (D_CR_DFUSESTAT)—Offset 16BCh................................... 1775
5.21.25Major Mode Control (D_CR_MMC)—Offset 1724h..................................... 1775
5.21.26Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1728h
1776
5.21.27Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 172Ch
1777
5.21.28Access Class Initial Priority (D_CR_ACCIP)—Offset 1730h......................... 1778
5.21.29Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1734h.....
1779
5.21.30Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1738h.....
1779
5.21.31Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 173Ch ....
1780
5.21.32Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1740h.....
1781
5.21.33Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1744h.....
1782
5.21.34Deadline Threshold (D_CR_DL_THRS)—Offset 1748h............................... 1783
5.21.35Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 174Ch .......... 1783
5.21.36DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1754h ....... 1785
5.21.37DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1780h ..... 1786
5.21.38MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1784h............. 1787
5.22 Registers Summary........................................................................................ 1789
5.22.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1A00h ............................ 1790
5.22.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1A08h ......................... 1792
5.22.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 1A0Ch ......................... 1793
5.22.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1A10h ......................... 1794
5.22.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1A14h ......................... 1795
5.22.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1A18h ......................... 1796
5.22.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 1A1Ch ......................... 1797

40 334818
 5.22.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1A20h ..........................1799
5.22.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1A24h ..........................1800
5.22.10DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1A28h ..........................1801
5.22.11D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 1A2Ch ..................1802
5.22.12D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1A30h ..........1803
5.22.13D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1A34h ..........1805
5.22.14DRAM Refresh Control (D_CR_DRFC)—Offset 1A38h ................................1807
5.22.15D-Unit Scheduler (D_CR_DSCH)—Offset 1A3Ch .......................................1809
5.22.16DRAM Calibration Control (D_CR_DCAL)—Offset 1A40h ............................1811
5.22.17VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 1A4Ch ...................1812
5.22.18Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset 1A50h..
1813
5.22.19TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1A54h .............1814
5.22.20Data Scrambler (D_CR_SCRAMCTRL)—Offset 1AA4h ................................1815
5.22.21Error Injection Address Register (D_CR_ERR_INJ)—Offset 1AACh ..............1816
5.22.22Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 1AB0h.........1817
5.22.23Error Log Register (D_CR_ERR_ECC_LOG)—Offset 1AB4h .........................1818
5.22.24D-Unit Status (D_CR_DFUSESTAT)—Offset 1ABCh ...................................1819
5.22.25Major Mode Control (D_CR_MMC)—Offset 1B24h .....................................1819
5.22.26Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset 1B28h
1820
5.22.27Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—Offset 1B2Ch
1821
5.22.28Access Class Initial Priority (D_CR_ACCIP)—Offset 1B30h .........................1822
5.22.29Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset 1B34h .....
1823
5.22.30Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset 1B38h .....
1823
5.22.31Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset 1B3Ch .....
1824
5.22.32Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset 1B40h .....
1825
5.22.33Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset 1B44h .....
1826
5.22.34Deadline Threshold (D_CR_DL_THRS)—Offset 1B48h ...............................1827
5.22.35Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 1B4Ch...........1827
5.22.36DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1B54h........1829
5.22.37DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1B80h ......1830
5.22.38MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1B84h .............1831
5.23 Registers Summary ........................................................................................1833
5.23.1 Thermal Device Mailbox Data0
(P_CR_THERMAL_MAILBOX_DATA0_0_0_0_MCHBAR)—Offset 7000h .........1835
5.23.2 Thermal Device Mailbox Data1
(P_CR_THERMAL_MAILBOX_DATA1_0_0_0_MCHBAR)—Offset 7004h .........1836
5.23.3 Thermal Device Mailbox Interface
(P_CR_THERMAL_MAILBOX_INTERFACE_0_0_0_MCHBAR)—Offset 7008h ...1837
5.23.4 Thermal Device IRQ and Lock Configuration
(P_CR_THERMAL_DEVICE_IRQ_0_0_0_MCHBAR)—Offset 700Ch ...............1838
5.23.5 Package Thermal Interrupt Control
(P_CR_PKG_THERM_INTERRUPT_0_0_0_MCHBAR)—Offset 7010h .............1839
5.23.6 ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR
(P_CR_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR)—Offset
7014h................................................................................................1840
5.23.7 Package Thermal Status (P_CR_PKG_THERM_STATUS_0_0_0_MCHBAR)—Offset
701Ch ...............................................................................................1841

334818 41
 5.23.8 LPDDR DRAM Thermal (MR4) Status of Channel 01
(P_CR_MEM_MR4_TEMPERATURE_DEV1_0_0_0_MCHBAR)—Offset 7024h .. 1843
5.23.9 LPDDR DRAM Thermal (MR4) Status of Channel 10
(P_CR_MEM_MR4_TEMPERATURE_DEV2_0_0_0_MCHBAR)—Offset 7028h .. 1843
5.23.10Machine Check Error Source Log (P_CR_MCA_ERROR_SRC_0_0_0_MCHBAR)—
Offset 702Ch...................................................................................... 1844
5.23.11DDR Thermal Throttling Control
(P_CR_DDR_THERM_THRT_CTRL_0_0_0_MCHBAR)—Offset 7030h ............ 1845
5.23.12DDR Thermal Interrupt Control
(P_CR_DDR_THERM_INTERRUPT_0_0_0_MCHBAR)—Offset 7034h ............ 1846
5.23.13DDR Thermal Status (P_CR_DDR_THERM_STATUS_0_0_0_MCHBAR)—Offset
7038h ............................................................................................... 1848
5.23.14Dram Energy Counter (P_CR_DDR_ENERGY_STATUS_0_0_0_MCHBAR)—Offset
7048h ............................................................................................... 1849
5.23.15DDR RAPL Performance Status
(P_CR_DDR_RAPL_PERF_STATUS_0_0_0_MCHBAR)—Offset 704Ch ........... 1850
5.23.16Package RAPL Performance Status
(P_CR_PACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR)—Offset 7050h .... 1851
5.23.17IA Core Performance / Power Priority Control
(P_CR_PRIMARY_PLANE_TURBO_PLCY_0_0_0_MCHBAR)—Offset 7054h .... 1852
5.23.18Graphics Performance / Power Priority Control
(P_CR_SECONDARY_PLANE_TURBO_PLCY_0_0_0_MCHBAR)—Offset 7058h 1852
5.23.19IA Energy Counter
(P_CR_PRIMARY_PLANE_ENERGY_STATUS_0_0_0_MCHBAR)—Offset 705Ch .....
1853
5.23.20Graphics Energy Counter
(P_CR_SECONDARY_PLANE_ENERGY_STATUS_0_0_0_MCHBAR)—Offset 7060h.
1854
5.23.21PACKAGE_POWER_SKU_UNIT
(P_CR_PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR)—Offset 7068h ...... 1855
5.23.22SOC Energy Counter (P_CR_PACKAGE_ENERGY_STATUS_0_0_0_MCHBAR)—
Offset 706Ch...................................................................................... 1856
5.23.23GT_PERF_STATUS (P_CR_GT_PERF_STATUS_0_0_0_MCHBAR)—Offset 7070h ...
1856
5.23.24Temperature Reference and Control
(P_CR_TEMPERATURE_TARGET_0_0_0_MCHBAR)—Offset 7074h .............. 1857
5.23.25BIOS Reset Completion (P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)—Offset
7078h ............................................................................................... 1858
5.23.26BIOS_MAILBOX_DATA (P_CR_BIOS_MAILBOX_DATA_0_0_0_MCHBAR)—Offset
7080h ............................................................................................... 1861
5.23.27BIOS_MAILBOX_INTERFACE
(P_CR_BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR)—Offset 7084h ........ 1861
5.23.28CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset 7088h 1862
5.23.29GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset 708Ch
1863
5.23.30SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset
7090h ............................................................................................... 1864
5.23.31Memory Frequency Status
(P_CR_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset
7094h ............................................................................................... 1865
5.23.32Package Power SKU and RAPL Power Control Capabilities
(P_CR_PACKAGE_POWER_SKU_0_0_0_MCHBAR)—Offset 70A0h............... 1866
5.23.33Package RAPL Power Limit (P_CR_PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR)—
Offset 70A8h...................................................................................... 1867

42 334818
 5.23.34IA_PERF_LIMIT_REASONS
(P_CR_IA_PERF_LIMIT_REASONS_0_0_0_MCHBAR)—Offset 70B0h ...........1869
5.23.35IA Core C0 Residency Counter
(P_CR_TELEM_IA_C0_RESIDENCY_0_0_0_MCHBAR)—Offset 70C0h...........1872
5.23.36Graphics C0 Residency Counter
(P_CR_TELEM_GT_C0_RESIDENCY_0_0_0_MCHBAR)—Offset 70C4h ..........1873
5.23.37I-unit Processing System C0 Residency Counter
(P_CR_TELEM_IUNIT_C0_RESIDENCY_0_0_0_MCHBAR)—Offset 70C8h......1873
5.23.38TELEM_IA_FREQ_ACCUMULATOR
(P_CR_TELEM_IA_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—Offset 70CCh..1874
5.23.39Graphics C0 Residency Counter
(P_CR_TELEM_GT_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—Offset 70D0h .1874
5.23.40I-unit Processing System C0 Residency Counter
(P_CR_TELEM_IUNIT_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—Offset 70D4h....
1875
5.23.41Memory Active Residency
(P_CR_TELEM_FAR_MEMORY_ACTIVE_0_0_0_MCHBAR)—Offset 70E8h ......1875
5.23.42Package Temperatures (P_CR_PACKAGE_TEMPERATURES_0_0_0_MCHBAR)—
Offset 70F4h.......................................................................................1876
5.23.43Package Thermal Limit Control
(P_CR_THERMAL_LIMIT_CONTROL_0_0_0_MCHBAR)—Offset 7104h ..........1877
5.23.44Memory Subsystem Frequency Capabilities
(P_CR_MEMSS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset 7108h .....
1878
5.23.45Memory Controller (MC) BIOS Reset Request and Status
(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR)—Offset 7114h ...........................1879
5.23.46MEMSS_FREQUENCY_CAPABILITIES1
(P_CR_MEMSS_FREQUENCY_CAPABILITIES1_0_0_0_MCHBAR)—Offset 7118h ...
1882
5.23.47PP1_C0_CORE_CLOCK_0_0_0_MCHBAR
(P_CR_PP1_C0_CORE_CLOCK_0_0_0_MCHBAR)—Offset 7160h .................1883
5.23.48Core Exists Vector (P_CR_CORE_EXISTS_VECTOR_0_0_0_MCHBAR)—Offset
7164h................................................................................................1884
5.23.49Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR)—
Offset 7168h ......................................................................................1884
5.23.50PL3 and PL4 Control (P_CR_PL3_CONTROL_0_0_0_MCHBAR)—Offset 71F0h ......
1886
5.23.51Graphics Superqueue Active Clocks
(P_CR_PP1_ANY_THREAD_ACTIVITY_0_0_0_MCHBAR)—Offset 7244h........1887
5.23.52LPDDR DRAM Thermal (MR4) Status of Channel 00
(P_CR_MEM_MR4_TEMPERATURE_DEV3_0_0_0_MCHBAR)—Offset 7248h...1888
5.23.53LPDDR DRAM Thermal (MR4) Status of Channel 11
(P_CR_MEM_MR4_TEMPERATURE_DEV4_0_0_0_MCHBAR)—Offset 724Ch ..1889
5.24 Registers Summary ........................................................................................1891
5.24.1 Upstream Device Arbiter Grant Count A2T
(A_CR_UPARB_GCNT_DEV_A2T_MCHBAR)—Offset 6400h .........................1893
5.24.2 Upstream A2B Arbiter Channel 0 Grant Count
(A_CR_UPARB_GCNT_A2B_0_MCHBAR)—Offset 6404h.............................1894
5.24.3 Upstream A2B Arbiter Channel 1 Grant Count
(A_CR_UPARB_GCNT_A2B_1_MCHBAR)—Offset 6408h.............................1895
5.24.4 Upstream A2B Arbiter Channel 2 Grant Count
(A_CR_UPARB_GCNT_A2B_2_MCHBAR)—Offset 640Ch ............................1896
5.24.5 Upstream A2B Arbiter Channel 3 Grant Count
(A_CR_UPARB_GCNT_A2B_3_MCHBAR)—Offset 6410h.............................1897
5.24.6 Upstream A2B Arbiter Channel 4 Grant Count
(A_CR_UPARB_GCNT_A2B_4_MCHBAR)—Offset 6414h.............................1898

334818 43
 5.24.7 Upstream A2B Arbiter Channel 5 Grant Count
(A_CR_UPARB_GCNT_A2B_5_MCHBAR)—Offset 6418h ............................ 1899
5.24.8 Upstream A2B Arbiter Channel 6 Grant Count
(A_CR_UPARB_GCNT_A2B_6_MCHBAR)—Offset 641Ch ............................ 1900
5.24.9 Upstream A2B Arbiter Channel 7 Grant Count
(A_CR_UPARB_GCNT_A2B_7_MCHBAR)—Offset 6420h ............................ 1900
5.24.10Upstream A2T Arbiter Channel 0 Grant Count
(A_CR_UPARB_GCNT_A2T_0_MCHBAR)—Offset 6424h ............................ 1901
5.24.11Upstream P2P Arbiter Channel 0 Grant Count
(A_CR_UPARB_GCNT_P2P_0_MCHBAR)—Offset 6428h ............................ 1902
5.24.12Upstream P2P Arbiter Channel 1 Grant Count
(A_CR_UPARB_GCNT_P2P_1_MCHBAR)—Offset 642Ch ............................ 1903
5.24.13Upstream Private Credit Return Grant Count Posted 0
(A_CR_CRDARB_PRIV_GCNT_DEV_P_0_MCHBAR)—Offset 6430h .............. 1904
5.24.14Upstream Private Credit Return Grant Count Posted 1
(A_CR_CRDARB_PRIV_GCNT_DEV_P_1_MCHBAR)—Offset 6434h .............. 1905
5.24.15Upstream Private Credit Return Grant Count Non-posted 0
(A_CR_CRDARB_PRIV_GCNT_DEV_N_0_MCHBAR)—Offset 6438h ............. 1905
5.24.16Upstream Private Credit Return Grant Count Posted 1
(A_CR_CRDARB_PRIV_GCNT_DEV_N_1_MCHBAR)—Offset 643Ch ............. 1906
5.24.17Upstream Private Credit Return Grant Count Completion
(A_CR_CRDARB_PRIV_GCNT_DEV_C_0_MCHBAR)—Offset 6440h.............. 1907
5.24.18Upstream Shared Credit Return Grant Count Posted 0
(A_CR_CRDARB_SHRD_GCNT_DEV_P_0_MCHBAR)—Offset 6444h ............ 1908
5.24.19Upstream Shared Credit Return Grant Count Posted 1
(A_CR_CRDARB_SHRD_GCNT_DEV_P_1_MCHBAR)—Offset 6448h ............ 1909
5.24.20Upstream Shared Credit Return Grant Count Non-posted 0
(A_CR_CRDARB_SHRD_GCNT_DEV_N_0_MCHBAR)—Offset 644Ch ............ 1909
5.24.21Upstream Shared Credit Return Grant Count Posted 1
(A_CR_CRDARB_SHRD_GCNT_DEV_N_1_MCHBAR)—Offset 6450h ............ 1910
5.24.22Upstream Shared Credit Return Grant Count Completion
(A_CR_CRDARB_SHRD_GCNT_DEV_C_0_MCHBAR)—Offset 6454h ............ 1911
5.24.23Upstream Credit Arbiter Private Credit Return Class Arbiter Grant Count
(A_CR_CRDARB_PRIV_GCNT_CLS_MCHBAR)—Offset 6458h ..................... 1912
5.24.24Upstream Credit Arbiter Shared Cedit Return Class Arbiter Grant Count
(A_CR_CRDARB_SHRD_GCNT_CLS_MCHBAR)—Offset 645Ch.................... 1912
5.24.25Gazelle Queue Limit Channel 0-3 (A_CR_GZLQ_LIMIT_CH0_3_MCHBAR)—Offset
6460h ............................................................................................... 1913
5.24.26Gazelle Queue Limit Channels 4-7 (A_CR_GZLQ_LIMIT_CH4_7_MCHBAR)—Offset
6464h ............................................................................................... 1914
5.24.27IOMMU Arbiter Grant Count VC0a Register
(A_CR_IOMMUARB_GCNT_VC0a_0_0_0_MCHBAR)—Offset 6468h ............. 1914
5.24.28IOMMU Arbiter Grant Count VC0b Register
(A_CR_IOMMUARB_GCNT_VC0b_0_0_0_MCHBAR)—Offset 646Ch ............. 1915
5.24.29IOMMU Arbiter Grant Count VC1b Register
(A_CR_IOMMUARB_GCNT_VC1b_0_0_0_MCHBAR)—Offset 6470h ............. 1916
5.24.30Gazelle Queue Reserved Entries Channels 0-3
(A_CR_GZLQ_RSVD_CH0_3_MCHBAR)—Offset 6474h ............................. 1917
5.24.31Gazelle Queue Reserved Entries Channels 4-7
(A_CR_GZLQ_RSVD_CH4_7_MCHBAR)—Offset 6478h ............................. 1917
5.24.32Spare BIOS (A_CR_SPARE_BIOS_MCHBAR)—Offset 647Ch....................... 1918
5.24.33Upcmd Credit Maximum Channel 0
(A_CR_UPCMD_CRDTMAX_CH0_0_0_0_MCHBAR)—Offset 6490h .............. 1918
5.24.34Upcmd Credit Maximum Channel 1
(A_CR_UPCMD_CRDTMAX_CH1_0_0_0_MCHBAR)—Offset 6494h .............. 1919
5.24.35Upcmd Credit Maximum Channel 2
(A_CR_UPCMD_CRDTMAX_CH2_0_0_0_MCHBAR)—Offset 6498h .............. 1920

44 334818
 5.24.36Upcmd Credit Maximum Channel 3
(A_CR_UPCMD_CRDTMAX_CH3_0_0_0_MCHBAR)—Offset 649Ch...............1921
5.24.37Upcmd Credit Maximum Channel 4
(A_CR_UPCMD_CRDTMAX_CH4_0_0_0_MCHBAR)—Offset 64A0h...............1921
5.24.38Upcmd Credit Maximum Channel 5
(A_CR_UPCMD_CRDTMAX_CH5_0_0_0_MCHBAR)—Offset 64A4h...............1922
5.24.39Upcmd Credit Maximum Channel 6
(A_CR_UPCMD_CRDTMAX_CH6_0_0_0_MCHBAR)—Offset 64A8h...............1923
5.24.40Upcmd Credit Maximum Channel 7
(A_CR_UPCMD_CRDTMAX_CH7_0_0_0_MCHBAR)—Offset 64ACh ..............1923
5.24.41MOT OUT Base Register (A_CR_MOT_OUT_BASE_0_0_0_MCHBAR)—Offset
64C0h ...............................................................................................1924
5.24.42MOT OUT Mask Register (A_CR_MOT_OUT_MASK_0_0_0_MCHBAR)—Offset
64C4h ...............................................................................................1925
5.24.43CHAP Select 1 (A_CR_CHAP_SLCT1_MCHBAR)—Offset 6500h....................1926
5.24.44CHAP Select 2 (A_CR_CHAP_SLCT2_MCHBAR)—Offset 6504h....................1927
5.24.45CHAP Select 3 (A_CR_CHAP_SLCT3_MCHBAR)—Offset 6508h....................1928
5.24.46Slice and Channel Hash (A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR)—
Offset 65C0h ......................................................................................1928
5.24.47Mirror Range Register (A_CR_MIRROR_RANGE_0_0_0_MCHBAR)—Offset 65C8h.
1931
5.24.48ASYM MEM REGION 0 CONFIGURATION WITH NO INTERLEAVING
(A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR)—Offset 65D0h .................1932
5.24.49ASYM MEM REGION 1 CONFIGURATION WITH NO INTERLEAVING
(A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR)—Offset 65D4h .................1933
5.24.50Two-Way Asymmetric Memory Region Configuration
(A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR)—Offset 65D8h .........1934
5.25 Registers Summary ........................................................................................1937
5.25.1 B-Unit Miscellaneous Configuration (B_CR_BMISC_0_0_0_MCHBAR)—Offset
6800h................................................................................................1945
5.25.2 Slice 0 Memory Access Count (B_CR_MEM_ACCESS_COUNT_SLICE0)—Offset
6868h................................................................................................1946
5.25.3 Slice 1 Memory Access Count (B_CR_MEM_ACCESS_COUNT_SLICE1)—Offset
686Ch ...............................................................................................1947
5.25.4 IMR0 Mask (B_CR_BIMR0MASK_0_0_0_MCHBAR)—Offset 6874h...............1948
5.25.5 IMR0 Control Policy (B_CR_BIMR0CP_0_0_0_MCHBAR)—Offset 6878h .......1949
5.25.6 IMR0 Read Access Policy (B_CR_BIMR0RAC_0_0_0_MCHBAR)—Offset 6880h .....
1949
5.25.7 IMR0 Write Access Policy (B_CR_BIMR0WAC_0_0_0_MCHBAR)—Offset 6888h....
1954
5.25.8 IMR1 Base (B_CR_BIMR1BASE_0_0_0_MCHBAR)—Offset 6890h................1959
5.25.9 IMR1 Mask (B_CR_BIMR1MASK_0_0_0_MCHBAR)—Offset 6894h...............1960
5.25.10IMR1 Control Policy (B_CR_BIMR1CP_0_0_0_MCHBAR)—Offset 6898h .......1961
5.25.11IMR1 Read Access Policy (B_CR_BIMR1RAC_0_0_0_MCHBAR)—Offset 68A0h .....
1961
5.25.12IMR1 Write Access Policy (B_CR_BIMR1WAC_0_0_0_MCHBAR)—Offset 68A8h....
1966
5.25.13Base 0 IMR2 Base (B_CR_BIMR2BASE_0_0_0_MCHBAR)—Offset 68B0h .....1971
5.25.14IMR2 Mask (B_CR_BIMR2MASK_0_0_0_MCHBAR)—Offset 68B4h...............1972
5.25.15IMR2 Control Policy (B_CR_BIMR2CP_0_0_0_MCHBAR)—Offset 68B8h .......1973
5.25.16IMR2 Read Access Policy (B_CR_BIMR2RAC_0_0_0_MCHBAR)—Offset 68C0h .....
1974
5.25.17IMR2 Write Access Policy (B_CR_BIMR2WAC_0_0_0_MCHBAR)—Offset 68C8h....
1978
5.25.18IMR3 Base (B_CR_BIMR3BASE_0_0_0_MCHBAR)—Offset 68D0h ...............1983
5.25.19IMR3 Mask (B_CR_BIMR3MASK_0_0_0_MCHBAR)—Offset 68D4h ..............1984
5.25.20IMR3 Control Policy (B_CR_BIMR3CP_0_0_0_MCHBAR)—Offset 68D8h .......1985

334818 45
 5.25.21IMR3 Read Access Policy (B_CR_BIMR3RAC_0_0_0_MCHBAR)—Offset 68E0h ....
1986
5.25.22IMR3 Write Access Policy (B_CR_BIMR3WAC_0_0_0_MCHBAR)—Offset 68E8h ...
1991
5.25.23IMR4 Base (B_CR_BIMR4BASE_0_0_0_MCHBAR)—Offset 68F0h ............... 1995
5.25.24IMR4 Mask (B_CR_BIMR4MASK_0_0_0_MCHBAR)—Offset 68F4h .............. 1996
5.25.25B-Unit IMR4 Control Policy (B_CR_BIMR4CP_0_0_0_MCHBAR)—Offset 68F8h ....
1997
5.25.26IMR4 Read Access Policy (B_CR_BIMR4RAC_0_0_0_MCHBAR)—Offset 6900h ....
1998
5.25.27IMR4 Write Access Policy (B_CR_BIMR4WAC_0_0_0_MCHBAR)—Offset 6908h ...
2003
5.25.28IMR5 Base (B_CR_BIMR5BASE_0_0_0_MCHBAR)—Offset 6910h ............... 2009
5.25.29IMR5 Mask (B_CR_BIMR5MASK_0_0_0_MCHBAR)—Offset 6914h .............. 2010
5.25.30IMR5 Control Policy (B_CR_BIMR5CP_0_0_0_MCHBAR)—Offset 6918h....... 2011
5.25.31IMR5 Read Access Policy (B_CR_BIMR5RAC_0_0_0_MCHBAR)—Offset 6920h ....
2012
5.25.32IMR5 Write Access Policy (B_CR_BIMR5WAC_0_0_0_MCHBAR)—Offset 6928h ...
2016
5.25.33IMR6 Base (B_CR_BIMR6BASE_0_0_0_MCHBAR)—Offset 6930h ............... 2021
5.25.34IMR6 Mask (B_CR_BIMR6MASK_0_0_0_MCHBAR)—Offset 6934h .............. 2022
5.25.35IMR6 Control Policy (B_CR_BIMR6CP_0_0_0_MCHBAR)—Offset 6938h....... 2023
5.25.36IMR6 Read Access Policy (B_CR_BIMR6RAC_0_0_0_MCHBAR)—Offset 6940h ....
2024
5.25.37IMR6 Write Access Policy (B_CR_BIMR6WAC_0_0_0_MCHBAR)—Offset 6948h ...
2029
5.25.38IMR7 Base (B_CR_BIMR7BASE_0_0_0_MCHBAR)—Offset 6950h ............... 2033
5.25.39IMR7 Mask (B_CR_BIMR7MASK_0_0_0_MCHBAR)—Offset 6954h .............. 2034
5.25.40IMR7 Control Policy (B_CR_BIMR7CP_0_0_0_MCHBAR)—Offset 6958h....... 2035
5.25.41IMR7 Read Access Policy (B_CR_BIMR7RAC_0_0_0_MCHBAR)—Offset 6960h ....
2036
5.25.42IMR7 Write Access Policy (B_CR_BIMR7WAC_0_0_0_MCHBAR)—Offset 6968h ...
2041
5.25.43IMR8 Base (B_CR_BIMR8BASE_0_0_0_MCHBAR)—Offset 6970h ............... 2046
5.25.44IMR8 Mask (B_CR_BIMR8MASK_0_0_0_MCHBAR)—Offset 6974h .............. 2046
5.25.45IMR8 Control Policy (B_CR_BIMR8CP_0_0_0_MCHBAR)—Offset 6978h....... 2047
5.25.46IMR8 Read Access Policy (B_CR_BIMR8RAC_0_0_0_MCHBAR)—Offset 6980h ....
2048
5.25.47IMR8 Write Access Policy (B_CR_BIMR8WAC_0_0_0_MCHBAR)—Offset 6988h ...
2053
5.25.48IMR9 Base (B_CR_BIMR9BASE_0_0_0_MCHBAR)—Offset 6990h ............... 2058
5.25.49IMR9 Mask (B_CR_BIMR9MASK_0_0_0_MCHBAR)—Offset 6994h .............. 2059
5.25.50IMR9 Control Policy (B_CR_BIMR9CP_0_0_0_MCHBAR)—Offset 6998h....... 2060
5.25.51IMR9 Read Access Policy (B_CR_BIMR9RAC_0_0_0_MCHBAR)—Offset 69A0h ....
2060
5.25.52IMR9 Write Access Policy (B_CR_BIMR9WAC_0_0_0_MCHBAR)—Offset 69A8h ...
2065
5.25.53IMR10 Base (B_CR_BIMR10BASE_0_0_0_MCHBAR)—Offset 69B0h ........... 2070
5.25.54IMR10 Mask (B_CR_BIMR10MASK_0_0_0_MCHBAR)—Offset 69B4h .......... 2071
5.25.55IMR10 Control Policy (B_CR_BIMR10CP_0_0_0_MCHBAR)—Offset 69B8h ... 2072
5.25.56IMR10 Read Access Policy (B_CR_BIMR10RAC_0_0_0_MCHBAR)—Offset 69C0h.
2073
5.25.57IMR10 Write Access Policy (B_CR_BIMR10WAC_0_0_0_MCHBAR)—Offset 69C8h
2077
5.25.58IMR11 Base (B_CR_BIMR11BASE_0_0_0_MCHBAR)—Offset 69D0h ........... 2082
5.25.59IMR11 Mask (B_CR_BIMR11MASK_0_0_0_MCHBAR)—Offset 69D4h .......... 2083

46 334818
 5.25.60IMR11 Control Policy (B_CR_BIMR11CP_0_0_0_MCHBAR)—Offset 69D8h ...2084
5.25.61IMR11 Read Access Policy (B_CR_BIMR11RAC_0_0_0_MCHBAR)—Offset 69E0h .
2085
5.25.62IMR11 Write Access Policy (B_CR_BIMR11WAC_0_0_0_MCHBAR)—Offset 69E8h
2090
5.25.63IMR12 Base (B_CR_BIMR12BASE_0_0_0_MCHBAR)—Offset 69F0h ............2094
5.25.64IMR12 Mask (B_CR_BIMR12MASK_0_0_0_MCHBAR)—Offset 69F4h ...........2095
5.25.65IMR12 Control Policy (B_CR_BIMR12CP_0_0_0_MCHBAR)—Offset 69F8h ....2096
5.25.66IMR12 Read Access Policy (B_CR_BIMR12RAC_0_0_0_MCHBAR)—Offset 6A00h .
2097
5.25.67IMR12 Write Access Policy (B_CR_BIMR12WAC_0_0_0_MCHBAR)—Offset 6A08h
2102
5.25.68IMR13 Base (B_CR_BIMR13BASE_0_0_0_MCHBAR)—Offset 6A10h ............2107
5.25.69IMR13 Mask (B_CR_BIMR13MASK_0_0_0_MCHBAR)—Offset 6A14h ...........2107
5.25.70IMR13 Control Policy (B_CR_BIMR13CP_0_0_0_MCHBAR)—Offset 6A18h....2108
5.25.71IMR13 Read Access Policy (B_CR_BIMR13RAC_0_0_0_MCHBAR)—Offset 6A20h .
2109
5.25.72IMR13 Write Access Policy (B_CR_BIMR13WAC_0_0_0_MCHBAR)—Offset 6A28h
2114
5.25.73IMR14 Base (B_CR_BIMR14BASE_0_0_0_MCHBAR)—Offset 6A30h ............2119
5.25.74IMR14 Mask (B_CR_BIMR14MASK_0_0_0_MCHBAR)—Offset 6A34h ...........2120
5.25.75IMR14 Control Policy (B_CR_BIMR14CP_0_0_0_MCHBAR)—Offset 6A38h....2121
5.25.76IMR14 Read Access Policy (B_CR_BIMR14RAC_0_0_0_MCHBAR)—Offset 6A40h .
2121
5.25.77IMR14 Write Access Policy (B_CR_BIMR14WAC_0_0_0_MCHBAR)—Offset 6A48h
2126
5.25.78IMR15 Base (B_CR_BIMR15BASE_0_0_0_MCHBAR)—Offset 6A50h ............2131
5.25.79IMR15 Mask (B_CR_BIMR15MASK_0_0_0_MCHBAR)—Offset 6A54h ...........2132
5.25.80IMR15 Control Policy (B_CR_BIMR15CP_0_0_0_MCHBAR)—Offset 6A58h....2133
5.25.81IMR15 Read Access Policy (B_CR_BIMR15RAC_0_0_0_MCHBAR)—Offset 6A60h .
2134
5.25.82IMR15 Write Access Policy (B_CR_BIMR15WAC_0_0_0_MCHBAR)—Offset 6A68h
2138
5.25.83IMR16 Base (B_CR_BIMR16BASE_0_0_0_MCHBAR)—Offset 6A70h ............2143
5.25.84IMR16 Mask (B_CR_BIMR16MASK_0_0_0_MCHBAR)—Offset 6A74h ...........2144
5.25.85IMR16 Control Policy (B_CR_BIMR16CP_0_0_0_MCHBAR)—Offset 6A78h....2145
5.25.86IMR16 Read Access Policy (B_CR_BIMR16RAC_0_0_0_MCHBAR)—Offset 6A80h .
2146
5.25.87IMR16 Write Access Policy (B_CR_BIMR16WAC_0_0_0_MCHBAR)—Offset 6A88h
2151
5.25.88IMR17 Base (B_CR_BIMR17BASE_0_0_0_MCHBAR)—Offset 6A90h ............2155
5.25.89IMR17 Mask (B_CR_BIMR17MASK_0_0_0_MCHBAR)—Offset 6A94h ...........2156
5.25.90IMR17 Control Policy (B_CR_BIMR17CP_0_0_0_MCHBAR)—Offset 6A98h....2157
5.25.91IMR17 Read Access Policy (B_CR_BIMR17RAC_0_0_0_MCHBAR)—Offset 6AA0h .
2158
5.25.92IMR17 Write Access Policy (B_CR_BIMR17WAC_0_0_0_MCHBAR)—Offset 6AA8h
2163
5.25.93IMR18 Base (B_CR_BIMR18BASE_0_0_0_MCHBAR)—Offset 6AB0h ............2168
5.25.94IMR18 Mask (B_CR_BIMR18MASK_0_0_0_MCHBAR)—Offset 6AB4h ...........2168
5.25.95IMR18 Control Policy (B_CR_BIMR18CP_0_0_0_MCHBAR)—Offset 6AB8h ...2169
5.25.96IMR18 Read Access Policy (B_CR_BIMR18RAC_0_0_0_MCHBAR)—Offset 6AC0h .
2170
5.25.97IMR18 Write Access Policy (B_CR_BIMR18WAC_0_0_0_MCHBAR)—Offset 6AC8h
2175
5.25.98IMR19 Base (B_CR_BIMR19BASE_0_0_0_MCHBAR)—Offset 6AD0h............2181
5.25.99IMR19 Mask (B_CR_BIMR19MASK_0_0_0_MCHBAR)—Offset 6AD4h...........2182

334818 47
 5.25.100IMR19 Control Policy (B_CR_BIMR19CP_0_0_0_MCHBAR)—Offset 6AD8h . 2183
5.25.101IMR19 Read Access Policy (B_CR_BIMR19RAC_0_0_0_MCHBAR)—Offset 6AE0h
2184
5.25.102IMR19 Write Access Policy (B_CR_BIMR19WAC_0_0_0_MCHBAR)—Offset 6AE8h
2189
5.25.103MOT Out Base (B_CR_MOT_OUT_BASE_0_0_0_MCHBAR)—Offset 6AF0h .. 2193
5.25.104MOT Out Mask (B_CR_MOT_OUT_MASK_0_0_0_MCHBAR)—Offset 6AF4h . 2194
5.25.105MOT Buffer Control Policy (B_CR_BMOT_BUF_CP_0_0_0_MCHBAR)—Offset
6AF8h ............................................................................................... 2195
5.25.106MOT Buffer Read Access Policy (B_CR_BMOT_BUF_RAC_0_0_0_MCHBAR)—
Offset 6B00h...................................................................................... 2196
5.25.107MOT Buffer Write Access Policy (B_CR_BMOT_BUF_WAC_0_0_0_MCHBAR)—
Offset 6B08h...................................................................................... 2201
5.25.108IMR Global BM Control Policy (B_CR_BIMRGLOBAL_BM_CP_0_0_0_MCHBAR)—
Offset 6B10h...................................................................................... 2207
5.25.109IMR Global BM Read Access Control
(B_CR_BIMRGLOBAL_BM_RAC_0_0_0_MCHBAR)—Offset 6B18h ............... 2208
5.25.110IMR Global BM Write Access Policy
(B_CR_BIMRGLOBAL_BM_WAC_0_0_0_MCHBAR)—Offset 6B20h .............. 2208
5.25.111Graphics Stolen Memory Control Policy (B_CR_BGSMCP_0_0_0_MCHBAR)—
Offset 6B28h...................................................................................... 2209
5.25.112GSM Read Access Policy (B_CR_BGSMRAC_0_0_0_MCHBAR)—Offset 6B30h ....
2210
5.25.113GSM Write Access Policy (B_CR_BGSMWAC_0_0_0_MCHBAR)—Offset 6B38h ...
2216
5.25.114TPM Control Policy (B_CR_TPM_CP_0_0_0_MCHBAR)—Offset 6B40h ........ 2222
5.25.115TPM Access Control (B_CR_TPM_AC_0_0_0_MCHBAR)—Offset 6B48h....... 2223
5.25.116BGSM Control Register (B_CR_BGSM_CTRL_0_0_0_MCHBAR)—Offset 6B50h ...
2223
5.25.117SMM Control Register (B_CR_BSMR_CTRL_0_0_0_MCHBAR)—Offset 6B54h .....
2224
5.25.118Default VTd Control Register (B_CR_BDEFVTDPMR_CTRL_0_0_0_MCHBAR)—
Offset 6B58h...................................................................................... 2225
5.25.119MOT Trigger Trace Control (B_CR_MOT_TRIG_TRACE_CTRL_0_0_0_MCHBAR)—
Offset 6B7Ch...................................................................................... 2226
5.25.120MOT Slice 0 Memory Pointer
(B_CR_MOT_SLICE_0_MEM_PTR_0_0_0_MCHBAR)—Offset 6B80h ............ 2229
5.25.121MOT Slice 1 Memory Pointer
(B_CR_MOT_SLICE_1_MEM_PTR_0_0_0_MCHBAR)—Offset 6B88h ............ 2230
5.25.122MOT Slice 0 Record ID (B_CR_MOT_SLICE_0_RECORD_ID_0_0_0_MCHBAR)—
Offset 6B90h...................................................................................... 2231
5.25.123MOT Slice 1 Record ID (B_CR_MOT_SLICE_1_RECORD_ID_0_0_0_MCHBAR)—
Offset 6B94h...................................................................................... 2231
5.25.124MOT Filter Match 0 (B_CR_MOT_FILTER_MATCH0_0_0_0_MCHBAR)—Offset
6BA0h............................................................................................... 2232
5.25.125MOT Filter Mask (B_CR_MOT_FILTER_MASK0_0_0_0_MCHBAR)—Offset 6BA8h
2233
5.25.126MOT Filter Match 1 (B_CR_MOT_FILTER_MATCH1_0_0_0_MCHBAR)—Offset
6BB0h............................................................................................... 2234
5.25.127MOT Filter Mask 1 (B_CR_MOT_FILTER_MASK1_0_0_0_MCHBAR)—Offset
6BB8h............................................................................................... 2234
5.25.128MOT Filter Misc 0 (B_CR_MOT_FILTER_MISC0_0_0_0_MCHBAR)—Offset 6BC0h
2235
5.25.129MOT Filter Misc 1 (B_CR_MOT_FILTER_MISC1_0_0_0_MCHBAR)—Offset 6BC8h
2236
5.25.130MOT Trigger Match 0 (B_CR_MOT_TRIGGER_MATCH0_0_0_0_MCHBAR)—Offset
6BD0h............................................................................................... 2237

48 334818
 5.25.131MOT Trigger Mask 0 (B_CR_MOT_TRIGGER_MASK0_0_0_0_MCHBAR)—Offset
6BD8h ...............................................................................................2238
5.25.132MOT Trigger Match 1 (B_CR_MOT_TRIGGER_MATCH1_0_0_0_MCHBAR)—Offset
6BE0h ...............................................................................................2239
5.25.133MOT Trigger Mask 1 (B_CR_MOT_TRIGGER_MASK1_0_0_0_MCHBAR)—Offset
6BE8h ...............................................................................................2240
5.25.134MOT Trigger Misc 0 (B_CR_MOT_TRIGGER_MISC0_0_0_0_MCHBAR)—Offset
6BF0h................................................................................................2241
5.25.135MOT Trigger Misc 1 (B_CR_MOT_TRIGGER_MISC1_0_0_0_MCHBAR)—Offset
6BF8h................................................................................................2242
5.25.136BIOSWR Control Policy (B_CR_BIOSWR_CP_0_0_0_MCHBAR)—Offset 6C08h....
2243
5.25.137BIOSWR Read Access Policy (B_CR_BIOSWR_RAC_0_0_0_MCHBAR)—Offset
6C10h ...............................................................................................2243
5.25.138BIOSWR Write Access Policy (B_CR_BIOSWR_WAC_0_0_0_MCHBAR)—Offset
6C18h ...............................................................................................2244
5.25.139TPM Selector (B_CR_TPM_SELECTOR_0_0_0_MCHBAR)—Offset 6C24h .....2244
5.25.140B-Unit Pcode/Ucode Write, All Read Control Policy Register
(B_CR_P_U_CODEWR_ALLRD_CP_0_0_0_MCHBAR)—Offset 6C28h ............2245
5.25.141B-Unit Pcode/Ucode Read Access Policy
(B_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCHBAR)—Offset 6C30h..........2246
5.25.142B-Unit Pcode/Ucode Write Access Policy
(B_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_MCHBAR)—Offset 6C38h .........2246
5.25.143Default VTd BAR (B_CR_DEFVTDBAR_0_0_0_MCHBAR)—Offset 6C80h .....2247
5.25.144Gfx VTd BAR (B_CR_GFXVTDBAR_0_0_0_MCHBAR)—Offset 6C88h...........2248
5.25.145B-Unit Lites Group 0 Control (B_CR_LITES0_CTL_0_0_0_MCHBAR)—Offset
6C90h ...............................................................................................2249
5.25.146B-Unit Lites Group 0 Opcode Match Filter
(B_CR_LITES0_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6C94h.............2251
5.25.147B-Unit Lites Group 0 Agent Match Filter
(B_CR_LITES0_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6C98h ...............2253
5.25.148B-Unit Lites Group 0 U2C IntData Match Filter
(B_CR_LITES0_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6C9Ch ......2255
5.25.149B-Unit Lites Group 0 Address Match Filter LITES0_ADDR_MATCH
(B_CR_LITES0_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6CA0h ................2255
5.25.150B-Unit Lites Group 0 Address Mask Filter LITES0_ADDR_MASK
(B_CR_LITES0_ADDR_MASK_0_0_0_MCHBAR)—Offset 6CA8h ..................2256
5.25.151B-Unit Lites Group 0 Data Match Filter LITES0_DATA_MATCH
(B_CR_LITES0_DATA_MATCH_0_0_0_MCHBAR)—Offset 6CB0h.................2257
5.25.152B-Unit Lites Group 0 Data Mask Filter LITES0_DATA_MASK
(B_CR_LITES0_DATA_MASK_0_0_0_MCHBAR)—Offset 6CB4h...................2257
5.25.153B-Unit Lites Group 1 Control (B_CR_LITES1_CTL_0_0_0_MCHBAR)—Offset
6CC0h ...............................................................................................2258
5.25.154B-Unit Lites Group 1 Opcode Match Filter
(B_CR_LITES1_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6CC4h.............2260
5.25.155B-Unit Lites Group 1 Agent Match Filter
(B_CR_LITES1_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6CC8h ...............2262
5.25.156B-Unit Lites Group 1 U2C IntData Match Filter
(B_CR_LITES1_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6CCCh ......2264
5.25.157B-Unit Lites Group 1 Address Match Filter LITES1_ADDR_MATCH
(B_CR_LITES1_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6CD0h ................2264
5.25.158B-Unit Lites Group 1 Address Mask Filter LITES1_ADDR_MASK
(B_CR_LITES1_ADDR_MASK_0_0_0_MCHBAR)—Offset 6CD8h ..................2265
5.25.159B-Unit Lites Group 1 Data Match Filter LITES1_DATA_MATCH
(B_CR_LITES1_DATA_MATCH_0_0_0_MCHBAR)—Offset 6CE0h .................2266
5.25.160B-Unit Lites Group 1 Data Mask Filter LITES1_DATA_MASK
(B_CR_LITES1_DATA_MASK_0_0_0_MCHBAR)—Offset 6CE4h ...................2266

334818 49
 5.25.161B-Unit Lites Group 2 Control (B_CR_LITES2_CTL_0_0_0_MCHBAR)—Offset
6CF0h ............................................................................................... 2267
5.25.162B-Unit Lites Group 2 Opcode Match Filter
(B_CR_LITES2_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6CF4h ............ 2269
5.25.163B-Unit Lites Group 2 Agent Match Filter
(B_CR_LITES2_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6CF8h............... 2271
5.25.164B-Unit Lites Group 2 U2C IntData Match Filter
(B_CR_LITES2_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6CFCh...... 2273
5.25.165B-Unit Lites Group 2 Address Match Filter LITES2_ADDR_MATCH
(B_CR_LITES2_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6D00h................ 2273
5.25.166B-Unit Lites Group 2 Address Mask Filter LITES2_ADDR_MASK
(B_CR_LITES2_ADDR_MASK_0_0_0_MCHBAR)—Offset 6D08h.................. 2274
5.25.167B-Unit Lites Group 2 Data Match Filter LITES2_DATA_MATCH
(B_CR_LITES2_DATA_MATCH_0_0_0_MCHBAR)—Offset 6D10h ................ 2275
5.25.168B-Unit Lites Group 2 Data Mask Filter LITES2_DATA_MASK
(B_CR_LITES2_DATA_MASK_0_0_0_MCHBAR)—Offset 6D14h .................. 2275
5.25.169B-Unit Lites Group 3 Control (B_CR_LITES3_CTL_0_0_0_MCHBAR)—Offset
6D20h............................................................................................... 2276
5.25.170B-Unit Lites Group 3 Opcode Match Filter
(B_CR_LITES3_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 6D24h ............ 2278
5.25.171B-Unit Lites Group 3 Agent Match Filter
(B_CR_LITES3_AGENT_MATCH_0_0_0_MCHBAR)—Offset 6D28h .............. 2280
5.25.172B-Unit Lites Group 3 U2C IntData Match Filter
(B_CR_LITES3_U2CINTDATA_MATCH_0_0_0_MCHBAR)—Offset 6D2Ch ..... 2282
5.25.173B-Unit Lites Group 3 Address Match Filter LITES3_ADDR_MATCH
(B_CR_LITES3_ADDR_MATCH_0_0_0_MCHBAR)—Offset 6D30h................ 2282
5.25.174B-Unit Lites Group 3 Address Mask Filter LITES3_ADDR_MASK
(B_CR_LITES3_ADDR_MASK_0_0_0_MCHBAR)—Offset 6D38h.................. 2283
5.25.175B-Unit Lites Group 3 Data Match Filter LITES3_DATA_MATCH
(B_CR_LITES3_DATA_MATCH_0_0_0_MCHBAR)—Offset 6D40h ................ 2284
5.25.176B-Unit Lites Group 3 Data Mask Filter LITES3_DATA_MASK
(B_CR_LITES3_DATA_MASK_0_0_0_MCHBAR)—Offset 6D44h .................. 2284
5.25.177B-Unit Lites and Emon Master Control LITESEMONCTL
(B_CR_LITESEMON_CTL_0_0_0_MCHBAR)—Offset 6D48h........................ 2285
5.25.178B-Unit Arbiter Control BARBCTRL0 (B_CR_BARBCTRL0)—Offset 6D4Ch..... 2287
5.25.179B-Unit Arbiter Control BARBCTRL1 (B_CR_BARBCTRL1)—Offset 6D50h ..... 2288
5.25.180B-Unit Scheduler Control (B_CR_BSCHWT0)—Offset 6D54h .................... 2289
5.25.181B-Unit Scheduler Control (B_CR_BSCHWT1)—Offset 6D58h .................... 2289
5.25.182B-Unit Scheduler Control (B_CR_BSCHWT2)—Offset 6D5Ch .................... 2290
5.25.183B-Unit Scheduler Control (B_CR_BSCHWT3)—Offset 6D60h .................... 2291
5.25.184B-Unit Flush Control (B_CR_BWFLUSH)—Offset 6D64h ........................... 2292
5.25.185B-Unit Flush Weights (B_CR_BFLWT)—Offset 6D68h .............................. 2293
5.25.186Weighted Scheduling Control of High Priority ISOC and Other Requests
(B_CR_BISOCWT)—Offset 6D6Ch ......................................................... 2294
5.25.187B-Unit Control (B_CR_BCTRL2)—Offset 6D70h ...................................... 2295
5.25.188Asset Classification Bits (B_CR_AC_RS0_0_0_0_MCHBAR)—Offset 6D74h . 2297
5.25.189IDI Real-Time Feature Configuration Bits (B_CR_RT_EN_0_0_0_MCHBAR)—
Offset 6D78h ..................................................................................... 2297
5.25.190B-Unit Control Register 3 (B_CR_BCTRL3)—Offset 6D7Ch ....................... 2298
5.25.191Asymmetric Memory Region 0 With No Interleaving Configuration
(B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR)—Offset 6E40h................. 2299
5.25.192Asymmetric Memory Region 1 With No Interleaving Configuration
(B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR)—Offset 6E44h................. 2300
5.25.193B-Unit Machine Check Mode Low (B_CR_BMCMODE_LOW)—Offset 6E48h . 2301
5.25.194B-Unit Machine Check Mode High (B_CR_BMCMODE_HIGH)—Offset 6E4Ch 2302
5.25.195Two-Way Asymmetric Memory Region Configuration
(B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR)—Offset 6E50h......... 2302

50 334818
 5.26 Registers Summary ........................................................................................2305
5.26.1 X2B_BARB_CTL1 (X2B_BARB_CTL1_MCHBAR)—Offset 7804h....................2306
5.26.2 Clock Gating Control (CLKGATE_CTL_MCHBAR)—Offset 7808h ..................2307
5.26.3 Miscellaneous Controls (MISC_CTL_MCHBAR)—Offset 780Ch .....................2309
5.26.4 CMiscellaneous T2A selector (T2A_SELECTOR_MISC_MCHBAR)—Offset 7818h ....
2311
5.26.5 VC Read Ordering CFG (VC_READ_ORDERING_CFG_MCHBAR)—Offset 781Ch.....
2312
5.26.6 VC Write Ordering CFG (VC_WRITE_ORDERING_CFG_MCHBAR)—Offset 7820h...
2314
5.26.7 IDI0 C2U Credit Control (IDI0_C2U_CREDIT_CTRL_MCHBAR)—Offset 7824h......
2317
5.26.8 IDI1 C2U Credit Control (IDI1_C2U_CREDIT_CTRL_MCHBAR)—Offset 7828h......
2318
5.26.9 IDI2 C2U Credit Control (IDI2_C2U_CREDIT_CTRL_MCHBAR)—Offset 782Ch......
2319
5.26.10IDI3 C2U Credit Control (IDI3_C2U_CREDIT_CTRL_MCHBAR)—Offset 7830h......
2321
5.26.11IDI4 C2U Credit Control (IDI4_C2U_CREDIT_CTRL_MCHBAR)—Offset 7834h......
2322
5.26.12IDI5 C2U Credit Control (IDI5_C2U_CREDIT_CTRL_MCHBAR)—Offset 7838h......
2323
5.26.13IDI6 C2U Credit Control (IDI6_C2U_CREDIT_CTRL_MCHBAR)—Offset 783Ch......
2324
5.26.14IDI7 C2U Credit Control (IDI7_C2U_CREDIT_CTRL_MCHBAR)—Offset 7840h......
2326
5.26.15PII2 A2T Credit Control (PII2_A2T_CREDIT_CTRL_MCHBAR)—Offset 7844h 2327
5.26.16BIOSWR Control Policy (T_CR_BIOSWR_CP_0_0_0_MCHBAR)—Offset 7848h .....
2328
5.26.17BIOSWR Read Access Control (T_CR_BIOSWR_RAC_0_0_0_MCHBAR)—Offset
7850h................................................................................................2329
5.26.18BIOSWR Write Access Control (T_CR_BIOSWR_WAC_0_0_0_MCHBAR)—Offset
7858h................................................................................................2329
5.26.19TUnit Pcode/Ucode Write, All Read Control Policy Register
(T_CR_P_U_CODEWR_ALLRD_CP_0_0_0_MCHBAR)—Offset 7860h ............2330
5.26.20TUnit Pcode/Ucode Read Access Control
(T_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCHBAR)—Offset 7868h ..........2330
5.26.21TUnit Pcode/Ucode Write Access Control
(T_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_MCHBAR)—Offset 7870h .........2331
6 Graphics and Displays ..........................................................................................2333
6.1 Registers Summary ........................................................................................2335
6.1.1 (CTXREG1)—Offset FF4h .....................................................................2335
6.1.2 (PAVP1)—Offset 31030h.......................................................................2335
6.1.3 (PAVP2)—Offset 323A4h .....................................................................2336
7 MDSI ....................................................................................................................2337
7.1 Registers Summary ........................................................................................2337
7.1.1 LJPLL_RW_CONTROL_1 (LJPLL_CR_RW_CONTROL_1)—Offset 10h .............2337
7.1.2 LJPLL_RW_CONTROL_2 (LJPLL_CR_RW_CONTROL_2)—Offset 14h .............2337
7.1.3 dsipll_cp (dsipll_cp)—Offset 20h............................................................2338
7.1.4 dsipll_rac (dsipll_rac)—Offset 28h .........................................................2339
7.1.5 dsipll_wac (dsipll_wac)—Offset 30h .......................................................2339
7.2 Registers Summary ........................................................................................2341
7.2.1 LJPLL_RW_CONTROL_1 (LJPLL_CR_RW_CONTROL_1)—Offset 10h .............2341
7.2.2 LJPLL_RW_CONTROL_2 (LJPLL_CR_RW_CONTROL_2)—Offset 14h .............2341
7.2.3 dsipll_cp (dsipll_cp)—Offset 20h............................................................2342

334818 51
 7.2.4 dsipll_rac (dsipll_rac)—Offset 28h ......................................................... 2342
7.2.5 dsipll_wac (dsipll_wac)—Offset 30h....................................................... 2343
8 System Agent....................................................................................................... 2345
8.1 Registers Summary........................................................................................ 2345
8.1.1 B-Unit Copy of the MCHBAR (B_CR_MCHBAR_LO_0_0_0_PCI)—Offset 48h . 2345
8.1.2 B-Unit Copy of the MCHBAR (B_CR_MCHBAR_HI_0_0_0_PCI)—Offset 4Ch . 2346
8.1.3 B-Unit Shadow of GGC (B_CR_GGC_0_0_0_PCI)—Offset 50h ................... 2347
8.1.4 B-Unit Shadow of the DEVEN Register (B_CR_DEVEN_0_0_0_PCI)—Offset 54h ..
2349
8.1.5 B-Unit PCI Express Enhanced Configuration Range Base Address Low
(B_CR_PCIEXBAR_LO_0_0_0_PCI)—Offset 60h ...................................... 2350
8.1.6 B-Unit PCI Express Enhanced Configuration Range Base Address High
(B_CR_PCIEXBAR_HI_0_0_0_PCI)—Offset 64h ....................................... 2351
8.1.7 Top of Upper Usable DRAM Low (B_CR_TOUUD_LO_0_0_0_PCI)—Offset A8h.....
2352
8.1.8 Top of Upper Usable DRAM High (B_CR_TOUUD_HI_0_0_0_PCI)—Offset ACh ....
2352
8.1.9 Base of Graphics Stolen Memory (B_CR_BGSM_0_0_0_PCI)—Offset B4h.... 2353
8.1.10 B-Unit Copy of the TSEG Memory Base (B_CR_TSEGMB_0_0_0_PCI)—Offset B8h
2354
8.1.11 Top of Lower Usable DRAM (B_CR_TOLUD_0_0_0_PCI)—Offset BCh .......... 2355
8.1.12 Capability ID0 A (B_CR_CAPID0_A_0_0_0_PCI)—Offset E4h .................... 2356
8.1.13 Capability ID0 B (B_CR_CAPID0_B_0_0_0_PCI)—Offset E8h .................... 2358
8.2 Registers Summary........................................................................................ 2359
8.2.1 B-Unit Copy of PCICMD for IGD (B_CR_PCICMD_0_2_0_PCI)—Offset 4h .... 2359
8.2.2 B-Unit Copy of GTTMMADR (B_CR_GTTMMADR_LO_0_2_0_PCI)—Offset 10h .....
2360
8.2.3 B-Unit Copy of GTTMMADR (B_CR_GTTMMADR_HI_0_2_0_PCI)—Offset 14h......
2361
8.2.4 B-Unit Copy of GMADR (B_CR_GMADR_LO_0_2_0_PCI)—Offset 18h.......... 2362
8.2.5 B-Unit Copy of GMADR (B_CR_GMADR_HI_0_2_0_PCI)—Offset 1Ch .......... 2363
8.2.6 B-Unit Copy of the IOBAR (B_CR_IOBAR_0_2_0_PCI)—Offset 20h ............ 2363
8.2.7 B-Unit Copy of Device 2 Control Register (B_CR_DEV2CTL_0_2_0_PCI)—Offset
58h................................................................................................... 2364
8.2.8 B-Unit Copy of MSAC (B_CR_MSAC_0_2_0_PCI)—Offset 62h .................... 2365
8.2.9 B-Unit Copy of Device 2 Control Register (B_CR_DEVICECTL_0_2_0_PCI)—Offset
78h................................................................................................... 2366
8.2.10 B-Unit Copy of PMCS for IGD (B_CR_PMCS_0_2_0_PCI)—Offset D4h......... 2367
8.3 Registers Summary........................................................................................ 2368
8.3.1 PCICMD for I-Unit in Device 3 Mode (B_CR_PCICMD_0_3_0_PCI)—Offset 4h .....
2369
8.3.2 B-Unit Copy of I-Unit BAR (B_CR_ISPMMADR_LO_0_3_0_PCI)—Offset 10h 2369
8.3.3 B-Unit Copy of I-Unit BAR (B_CR_ISPMMADR_HI_0_3_0_PCI)—Offset 14h . 2370
8.3.4 B-Unit Copy of Device 3 Control Register (B_CR_DEVICECTL_0_3_0_PCI)—Offset
78h................................................................................................... 2371
8.3.5 B-Unit Copy of PMCS for I-Unit Device 0/3/0 (B_CR_PMCS_0_3_0_PCI)—Offset
D4h .................................................................................................. 2372
8.4 Registers Summary........................................................................................ 2373
8.4.1 B-Unit Copy of the I/O Decode Ranges Register for LPC (B_CR_IOD_LPC)—Offset
80h................................................................................................... 2373
8.4.2 B-Unit Copy of the I/O Enables Register for LPC (B_CR_IOE_LPC)—Offset 82h ...
2375
8.4.3 B_LGIR1_LPC (B_CR_LGIR1_LPC)—Offset 84h........................................ 2375
8.4.4 B_LGIR2_LPC (B_CR_LGIR2_LPC)—Offset 88h........................................ 2376
8.4.5 B_LGIR3_LPC (B_CR_LGIR3_LPC)—Offset 8Ch ....................................... 2377

52 334818
 8.4.6 B_LGIR4_LPC (B_CR_LGIR4_LPC)—Offset 90h ........................................2378
8.4.7 B-Unit Copy of the LPC Generic Memory Range Register for LPC
(B_CR_LGMR_LPC)—Offset 98h.............................................................2379
8.4.8 B-Unit Copy of the BIOS Decode Enable Register for LPC (B_CR_BDE_LPC)—
Offset D8h .........................................................................................2379
8.5 Registers Summary ........................................................................................2381
8.5.1 B-Unit Copy of the TCO Base Address Register for Legacy SMBUS
(B_CR_TCOBASE_SMBUS)—Offset 50h...................................................2381
8.5.2 B-Unit Copy of the TCO Control Register for Legacy SMBUS
(B_CR_TCOCTL_SMBUS)—Offset 54h .....................................................2381
8.6 Registers Summary ........................................................................................2382
8.6.1 B-Unit Copy of the BIOS Decode Enable register for SPI (B_CR_BDE_SPI)—Offset
D8h...................................................................................................2382
8.7 Registers Summary ........................................................................................2383
8.7.1 B-Unit Copy of IOBAR MMIO INDEX (B_CR_INDEX_0_2_0_IOBAR)—Offset 0h ....
2384
8.8 Registers Summary ........................................................................................2384
8.8.1 B-Unit Shadow of Legacy VGA Decode GR and MSR Bits
(B_CR_VGADEC_0_2_0_VGABAR)—Offset 0h..........................................2384
8.9 Registers Summary ........................................................................................2385
8.9.1 B-Unit Copy of Default VTd BAR PMEN (B_CR_PMEN_REG_0_0_0_DEFVTDBAR)—
Offset 64h ..........................................................................................2386
8.9.2 B-Unit Copy of Default VTd BAR PLM Base Register
(B_CR_PLMBASE_REG_0_0_0_DEFVTDBAR)—Offset 68h ..........................2386
8.9.3 B-Unit Copy of Default VTd BAR PLM Limit Register
(B_CR_PLMLIMIT_REG_0_0_0_DEFVTDBAR)—Offset 6Ch .........................2387
8.9.4 B-Unit Copy of Default VTd BAR PHM Base Register
(B_CR_PHMBASE_REG_0_0_0_DEFVTDBAR)—Offset 70h .........................2388
8.9.5 B-Unit Copy of Default VTd BAR PHM Limit Register
(B_CR_PHMLIMIT_REG_0_0_0_DEFVTDBAR)—Offset 78h .........................2389
8.10 Registers Summary ........................................................................................2391
8.10.1 B-Unit Copy of the MCHBAR (B_CR_MCHBAR_LO_0_0_0_PCI)—Offset 48h..2391
8.10.2 B-Unit Copy of the MCHBAR (B_CR_MCHBAR_HI_0_0_0_PCI)—Offset 4Ch ..2392
8.10.3 B-Unit Shadow of GGC (B_CR_GGC_0_0_0_PCI)—Offset 50h ....................2393
8.10.4 B-Unit Shadow of the DEVEN Register (B_CR_DEVEN_0_0_0_PCI)—Offset 54h...
2395
8.10.5 B-Unit PCI Express Enhanced Configuration Range Base Address Low
(B_CR_PCIEXBAR_LO_0_0_0_PCI)—Offset 60h .......................................2396
8.10.6 B-Unit PCI Express Enhanced Configuration Range Base Address High
(B_CR_PCIEXBAR_HI_0_0_0_PCI)—Offset 64h .......................................2397
8.10.7 Top of Upper Usable DRAM Low (B_CR_TOUUD_LO_0_0_0_PCI)—Offset A8h .....
2398
8.10.8 Top of Upper Usable DRAM High (B_CR_TOUUD_HI_0_0_0_PCI)—Offset ACh.....
2398
8.10.9 Base of Graphics Stolen Memory (B_CR_BGSM_0_0_0_PCI)—Offset B4h ....2399
8.10.10B-Unit Copy of the TSEG Memory Base (B_CR_TSEGMB_0_0_0_PCI)—Offset B8h
2400
8.10.11Top of Lower Usable DRAM (B_CR_TOLUD_0_0_0_PCI)—Offset BCh ..........2401
8.10.12Capability ID0 A (B_CR_CAPID0_A_0_0_0_PCI)—Offset E4h .....................2402
8.10.13Capability ID0 B (B_CR_CAPID0_B_0_0_0_PCI)—Offset E8h .....................2404
8.11 Registers Summary ........................................................................................2407
8.11.1 B-Unit Copy of PCICMD for IGD (B_CR_PCICMD_0_2_0_PCI)—Offset 4h.....2407
8.11.2 B-Unit Copy of GTTMMADR (B_CR_GTTMMADR_LO_0_2_0_PCI)—Offset 10h......
2408
8.11.3 B-Unit Copy of GTTMMADR (B_CR_GTTMMADR_HI_0_2_0_PCI)—Offset 14h ......
2409

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 8.11.4 B-Unit Copy of GMADR (B_CR_GMADR_LO_0_2_0_PCI)—Offset 18h.......... 2410
8.11.5 B-Unit Copy of GMADR (B_CR_GMADR_HI_0_2_0_PCI)—Offset 1Ch .......... 2411
8.11.6 B-Unit Copy of the IOBAR (B_CR_IOBAR_0_2_0_PCI)—Offset 20h ............ 2411
8.11.7 B-Unit Copy of Device 2 Control Register (B_CR_DEV2CTL_0_2_0_PCI)—Offset
58h................................................................................................... 2412
8.11.8 B-Unit Copy of MSAC (B_CR_MSAC_0_2_0_PCI)—Offset 62h .................... 2412
8.11.9 B-Unit Copy of Device 2 Control Register (B_CR_DEVICECTL_0_2_0_PCI)—Offset
78h................................................................................................... 2413
8.11.10B-Unit Copy of PMCS for IGD (B_CR_PMCS_0_2_0_PCI)—Offset D4h......... 2415
8.12 Registers Summary........................................................................................ 2417
8.12.1 PCICMD for I-Unit in Device 3 Mode (B_CR_PCICMD_0_3_0_PCI)—Offset 4h .....
2417
8.12.2 B-Unit Copy of I-Unit BAR (B_CR_ISPMMADR_LO_0_3_0_PCI)—Offset 10h 2418
8.12.3 B-Unit Copy of I-Unit BAR (B_CR_ISPMMADR_HI_0_3_0_PCI)—Offset 14h . 2418
8.12.4 B-Unit Copy of Device 3 Control Register (B_CR_DEVICECTL_0_3_0_PCI)—Offset
78h................................................................................................... 2419
8.12.5 B-Unit Copy of PMCS for I-Unit Device 0/3/0 (B_CR_PMCS_0_3_0_PCI)—Offset
D4h .................................................................................................. 2420
8.13 Registers Summary........................................................................................ 2423
8.13.1 B-Unit Copy of the I/O Decode Ranges Register for LPC (B_CR_IOD_LPC)—Offset
80h................................................................................................... 2423
8.13.2 B-Unit Copy of the I/O Enables Register for LPC (B_CR_IOE_LPC)—Offset 82h ...
2424
8.13.3 B_LGIR1_LPC (B_CR_LGIR1_LPC)—Offset 84h........................................ 2425
8.13.4 B_LGIR2_LPC (B_CR_LGIR2_LPC)—Offset 88h........................................ 2426
8.13.5 B_LGIR3_LPC (B_CR_LGIR3_LPC)—Offset 8Ch ....................................... 2427
8.13.6 B_LGIR4_LPC (B_CR_LGIR4_LPC)—Offset 90h........................................ 2428
8.13.7 B-Unit Copy of the LPC Generic Memory Range Register for LPC
(B_CR_LGMR_LPC)—Offset 98h ............................................................ 2428
8.13.8 B-Unit Copy of the BIOS Decode Enable Register for LPC (B_CR_BDE_LPC)—
Offset D8h ......................................................................................... 2429
8.14 Registers Summary........................................................................................ 2431
8.14.1 B-Unit Copy of the TCO Base Address Register for Legacy SMBUS
(B_CR_TCOBASE_SMBUS)—Offset 50h .................................................. 2431
8.14.2 B-Unit Copy of the TCO Control Register for Legacy SMBUS
(B_CR_TCOCTL_SMBUS)—Offset 54h .................................................... 2431
8.15 Registers Summary........................................................................................ 2433
8.15.1 B-Unit Copy of the BIOS Decode Enable register for SPI (B_CR_BDE_SPI)—Offset
D8h .................................................................................................. 2433
8.16 Registers Summary........................................................................................ 2435
8.16.1 B-Unit Copy of IOBAR MMIO INDEX (B_CR_INDEX_0_2_0_IOBAR)—Offset 0h ...
2435
8.17 Registers Summary........................................................................................ 2437
8.17.1 B-Unit Shadow of Legacy VGA Decode GR and MSR Bits
(B_CR_VGADEC_0_2_0_VGABAR)—Offset 0h ......................................... 2437
8.18 Registers Summary........................................................................................ 2439
8.18.1 B-Unit Copy of Default VTd BAR PMEN (B_CR_PMEN_REG_0_0_0_DEFVTDBAR)—
Offset 64h ......................................................................................... 2439
8.18.2 B-Unit Copy of Default VTd BAR PLM Base Register
(B_CR_PLMBASE_REG_0_0_0_DEFVTDBAR)—Offset 68h ......................... 2440
8.18.3 B-Unit Copy of Default VTd BAR PLM Limit Register
(B_CR_PLMLIMIT_REG_0_0_0_DEFVTDBAR)—Offset 6Ch ......................... 2441
8.18.4 B-Unit Copy of Default VTd BAR PHM Base Register
(B_CR_PHMBASE_REG_0_0_0_DEFVTDBAR)—Offset 70h ......................... 2441
8.18.5 B-Unit Copy of Default VTd BAR PHM Limit Register
(B_CR_PHMLIMIT_REG_0_0_0_DEFVTDBAR)—Offset 78h ........................ 2442

54 334818
9 C-Unit ...................................................................................................................2445
9.1 Registers Summary ........................................................................................2445
9.1.1 Device ID and Vendor ID Register (DEVICE_ID_VENDOR_ID_0_0_0_PCI)—Offset
0h .....................................................................................................2446
9.1.2 PCI Status and PCI Command Register (PCI_STATUS_COMMAND_0_0_0_PCI)—
Offset 4h............................................................................................2446
9.1.3 PCI Revision ID and PCI Class Code Register
(REVISION_ID_CLASS_CODE_0_0_0_PCI)—Offset 8h ..............................2447
9.1.4 Master Latency Timer and Header Type Register
(MASTER_LATENCY_TIME_0_0_0_PCI)—Offset Ch ...................................2448
9.1.5 PCI Subsystem Vendor ID and PCI Subsystem ID (SVID_SID_0_0_0_PCI)—Offset
2Ch ...................................................................................................2449
9.1.6 Capability Register Pointer (CAPPTR_0_0_0_PCI)—Offset 34h ...................2449
9.1.7 Memory Controller Hub Base Address Register (MCHBAR_LO_0_0_0_PCI)—Offset
48h ...................................................................................................2450
9.1.8 Memory Controller Hub Base Address Register (MCHBAR_HI_0_0_0_PCI)—Offset
4Ch ...................................................................................................2451
9.1.9 Graphics and Memory Controller Hub Graphics Control Register
(GGC_0_0_0_PCI)—Offset 50h .............................................................2451
9.1.10 Device Enable Register (DEVEN_0_0_0_PCI)—Offset 54h .........................2453
9.1.11 Protected Audio Video Path Control (PAVPC_0_0_0_PCI)—Offset 58h .........2454
9.1.12 PCI Express Enhanced Configuration Range Base Address Low
(PCIEXBAR_LO_0_0_0_PCI)—Offset 60h ................................................2456
9.1.13 PCI Express Enhanced Configuration Range Base Address High
(PCIEXBAR_HI_0_0_0_PCI)—Offset 64h.................................................2457
9.1.14 Top of Upper Usable DRAM Low (TOUUD_LO_0_0_0_PCI)—Offset A8h .......2457
9.1.15 Top of Upper Usable DRAM High (TOUUD_HI_0_0_0_PCI)—Offset ACh .......2458
9.1.16 Base of Data Stolen Memory (BDSM_0_0_0_PCI)—Offset B0h ...................2459
9.1.17 Base of Graphics Stolen Memory (BGSM_0_0_0_PCI)—Offset B4h .............2460
9.1.18 Top Segment Memory Base (TSEGMB_0_0_0_PCI)—Offset B8h .................2461
9.1.19 Top of Lower Usable DRAM (TOLUD_0_0_0_PCI)—Offset BCh....................2461
9.1.20 Scratchpad (SKPD_0_0_0_PCI)—Offset DCh ...........................................2462
9.1.21 Capability ID0 Capability Control (CAPID0_CAPCTRL0_0_0_0_PCI)—Offset E0h ..
2463
9.1.22 Capability ID0 A (CAPID0_A_0_0_0_PCI)—Offset E4h ..............................2463
9.1.23 Capability ID0 B (CAPID0_B_0_0_0_PCI)—Offset E8h ..............................2465
9.1.24 Design and Engineering Backup Register 0 (DEBUP0_0_0_0_PCI)—Offset F8h ....
2466
9.1.25 Design and Engineering Backup Register 1 (DEBUP1_0_0_0_PCI)—Offset FCh....
2467
9.1.26 I/O Buffer Control (IOBCTL)—Offset 061Ch .............................................2467
9.1.27 Power Management Control And Status (PCS)—Offset 0054h ....................2469
9.1.28 LTRC_D013C_PCE—Offset 1048h ..........................................................2471
9.1.29 PID_PC—Offset 0050h .........................................................................2472
9.2 Registers Summary ........................................................................................2473
9.2.1 Thermal Management Base Address Register (TMBAR_LO_0_0_1_PCI)—Offset
10h ...................................................................................................2473
9.2.2 Thermal Management Base Address Register (TMBAR_HI_0_0_1_PCI)—Offset
14h ...................................................................................................2474
9.3 Registers Summary ........................................................................................2477
9.3.1 Device ID and Vendor ID Register (DEVICE_ID_VENDOR_ID_0_0_0_PCI)—Offset
0h .....................................................................................................2478
9.3.2 PCI Status and PCI Command Register (PCI_STATUS_COMMAND_0_0_0_PCI)—
Offset 4h............................................................................................2478
9.3.3 PCI Revision ID and PCI Class Code Register
(REVISION_ID_CLASS_CODE_0_0_0_PCI)—Offset 8h ..............................2479

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 9.3.4 Master Latency Timer and Header Type Register
(MASTER_LATENCY_TIME_0_0_0_PCI)—Offset Ch .................................. 2480
9.3.5 PCI Subsystem Vendor ID and PCI Subsystem ID (SVID_SID_0_0_0_PCI)—Offset
2Ch .................................................................................................. 2481
9.3.6 Capability Register Pointer (CAPPTR_0_0_0_PCI)—Offset 34h ................... 2481
9.3.7 Memory Controller Hub Base Address Register (MCHBAR_LO_0_0_0_PCI)—Offset
48h................................................................................................... 2482
9.3.8 Memory Controller Hub Base Address Register (MCHBAR_HI_0_0_0_PCI)—Offset
4Ch .................................................................................................. 2483
9.3.9 Graphics and Memory Controller Hub Graphics Control Register
(GGC_0_0_0_PCI)—Offset 50h ............................................................. 2483
9.3.10 Device Enable Register (DEVEN_0_0_0_PCI)—Offset 54h ......................... 2485
9.3.11 Protected Audio Video Path Control (PAVPC_0_0_0_PCI)—Offset 58h......... 2486
9.3.12 PCI Express Enhanced Configuration Range Base Address Low
(PCIEXBAR_LO_0_0_0_PCI)—Offset 60h................................................ 2488
9.3.13 PCI Express Enhanced Configuration Range Base Address High
(PCIEXBAR_HI_0_0_0_PCI)—Offset 64h ................................................ 2489
9.3.14 Top of Upper Usable DRAM Low (TOUUD_LO_0_0_0_PCI)—Offset A8h ....... 2489
9.3.15 Top of Upper Usable DRAM High (TOUUD_HI_0_0_0_PCI)—Offset ACh ...... 2490
9.3.16 Base of Data Stolen Memory (BDSM_0_0_0_PCI)—Offset B0h .................. 2491
9.3.17 Base of Graphics Stolen Memory (BGSM_0_0_0_PCI)—Offset B4h ............. 2492
9.3.18 Top Segment Memory Base (TSEGMB_0_0_0_PCI)—Offset B8h ................ 2493
9.3.19 Top of Lower Usable DRAM (TOLUD_0_0_0_PCI)—Offset BCh ................... 2493
9.3.20 Scratchpad (SKPD_0_0_0_PCI)—Offset DCh........................................... 2494
9.3.21 Capability ID0 Capability Control (CAPID0_CAPCTRL0_0_0_0_PCI)—Offset E0h..
2495
9.3.22 Capability ID0 A (CAPID0_A_0_0_0_PCI)—Offset E4h.............................. 2495
9.3.23 Capability ID0 B (CAPID0_B_0_0_0_PCI)—Offset E8h.............................. 2497
9.3.24 Design and Engineering Backup Register 0 (DEBUP0_0_0_0_PCI)—Offset F8h ...
2498
9.3.25 Design and Engineering Backup Register 1 (DEBUP1_0_0_0_PCI)—Offset FCh ...
2499
9.3.26 I/O Buffer Control (IOBCTL)—Offset 061Ch ............................................ 2499
9.3.27 Power Management Control And Status (PCS)—Offset 0054h .................... 2501
9.3.28 LTRC_D013C_PCE—Offset 1048h .......................................................... 2503
9.3.29 PID_PC—Offset 0050h ......................................................................... 2504
9.4 Registers Summary........................................................................................ 2507
9.4.1 Thermal Management Base Address Register (TMBAR_LO_0_0_1_PCI)—Offset
10h................................................................................................... 2507
9.4.2 Thermal Management Base Address Register (TMBAR_HI_0_0_1_PCI)—Offset
14h................................................................................................... 2508
10 Imaging Control................................................................................................... 2509
10.1 Registers Summary........................................................................................ 2509
10.1.1 (VID_DID)—Offset 0h......................................................................... 2509
10.1.2 (PCICMD_PCISTS)—Offset 4h .............................................................. 2510
10.1.3 (RID_CC)—Offset 8h .......................................................................... 2511
10.1.4 (CLS_MLT_HT_BIST)—Offset Ch .......................................................... 2512
10.1.5 (ISPMMADR_LOW)—Offset 10h............................................................ 2513
10.1.6 (ISPMMADR_HIGH)—Offset 14h........................................................... 2514
10.1.7 (SVID_SID)—Offset 2Ch ..................................................................... 2514
10.1.8 (CAPPOINT)—Offset 34h ..................................................................... 2515
10.1.9 (INTR)—Offset 3Ch ............................................................................ 2515
10.1.10 (PCIECAPHDR_PCIECAP)—Offset 70h ................................................... 2516
10.1.11 (DEVICECAP)—Offset 74h ................................................................... 2517
10.1.12 (DEVICECTL_DEVICESTS)—Offset 78h.................................................. 2518

56 334818
 10.1.13 (MSI_CAPID)—Offset ACh....................................................................2519
10.1.14 (MSI_ADDRESS_LO)—Offset B0h .........................................................2520
10.1.15 (MSI_ADDRESS_HI)—Offset B4h ..........................................................2520
10.1.16 (MSI_DATA)—Offset B8h .....................................................................2521
10.1.17 (PMCAP)—Offset D0h ..........................................................................2522
10.1.18(PMCS)—Offset D4h ............................................................................2522
10.1.19(SENSOR_FREQ_CTL)—Offset 16Ch .......................................................2523
10.1.20(SENSOR_CLK_CTL)—Offset 170h .........................................................2524
10.1.21NFC_CFG ...........................................................................................2525
10.1.22IUNIT_CFG .........................................................................................2526
10.2 Registers Summary ........................................................................................2529
10.2.1 (VID_DID)—Offset 0h .........................................................................2529
10.2.2 (PCICMD_PCISTS)—Offset 4h ..............................................................2530
10.2.3 (RID_CC)—Offset 8h...........................................................................2531
10.2.4 (CLS_MLT_HT_BIST)—Offset Ch...........................................................2532
10.2.5 (ISPMMADR_LOW)—Offset 10h ............................................................2533
10.2.6 (ISPMMADR_HIGH)—Offset 14h ...........................................................2534
10.2.7 (SVID_SID)—Offset 2Ch......................................................................2534
10.2.8 (CAPPOINT)—Offset 34h .....................................................................2535
10.2.9 (INTR)—Offset 3Ch.............................................................................2535
10.2.10 (PCIECAPHDR_PCIECAP)—Offset 70h ....................................................2536
10.2.11 (DEVICECAP)—Offset 74h....................................................................2537
10.2.12 (DEVICECTL_DEVICESTS)—Offset 78h ..................................................2538
10.2.13 (MSI_CAPID)—Offset ACh....................................................................2539
10.2.14 (MSI_ADDRESS_LO)—Offset B0h .........................................................2540
10.2.15 (MSI_ADDRESS_HI)—Offset B4h ..........................................................2540
10.2.16 (MSI_DATA)—Offset B8h .....................................................................2541
10.2.17 (PMCAP)—Offset D0h ..........................................................................2542
10.2.18(PMCS)—Offset D4h ............................................................................2542
10.2.19(SENSOR_FREQ_CTL)—Offset 16Ch .......................................................2543
10.2.20(SENSOR_CLK_CTL)—Offset 170h .........................................................2544
10.2.21NFC_CFG ...........................................................................................2545
10.2.22IUNIT_CFG .........................................................................................2546
11 Audio Controller ...................................................................................................2549
11.1 Registers Summary ........................................................................................2549
11.1.1 Vendor Identification (VID)—Offset 0h ...................................................2550
11.1.2 Device ID (DID)—Offset 2h...................................................................2551
11.1.3 Command (CMD)—Offset 4h .................................................................2551
11.1.4 Status (STS)—Offset 6h .......................................................................2552
11.1.5 Revision Identification (RID)—Offset 8h..................................................2553
11.1.6 Programming Interface (PI)—Offset 9h...................................................2554
11.1.7 Sub Class Code (SCC)—Offset Ah ..........................................................2554
11.1.8 Base Class Code (BCC)—Offset Bh .........................................................2555
11.1.9 Cache Line Size (CLS)—Offset Ch ..........................................................2555
11.1.10Latency Timer (LT)—Offset Dh ..............................................................2556
11.1.11Header Type (HTYPE)—Offset Eh ...........................................................2556
11.1.12Built-in Self Test (BIST)—Offset Fh ........................................................2557
11.1.13Intel HD Audio Base Lower Address (HDALBA)—Offset 10h .......................2557
11.1.14Intel HD Audio Base Upper Address (HDAUBA)—Offset 14h .......................2558
11.1.15Shadowed PCI Configuration Lower Base Address (SPCLBA)—Offset 18h.....2558
11.1.16Shadowed PCI Configuration Upper Base Address (SPCUBA)—Offset 1Ch ....2559
11.1.17Audio DSP Lower Base Address (ADSPLBA)—Offset 20h............................2559
11.1.18Audio DSP Upper Base Address (ADSPUBA)—Offset 24h ...........................2560
11.1.19Subsystem Vendor ID (SVID)—Offset 2Ch ..............................................2561

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 11.1.20Subsystem ID (SID)—Offset 2Eh........................................................... 2561
11.1.21Capability Pointer (CAPPTR)—Offset 34h ................................................ 2562
11.1.22Interrupt Line (INTLN)—Offset 3Ch ....................................................... 2562
11.1.23Interrupt Pin (INTPN)—Offset 3Dh......................................................... 2563
11.1.24Test Mode 1 register (TM1)—Offset 43h ................................................. 2563
11.1.25PCI Power Management Capability ID (PID)—Offset 50h .......................... 2564
11.1.26MSI Capability ID (MID)—Offset 60h ..................................................... 2565
11.1.27MSI Message Control (MMC)—Offset 62h ............................................... 2565
11.1.28MSI Message Lower Address (MMLA)—Offset 64h.................................... 2566
11.1.29MSI Message Upper Address (MMUA)—Offset 68h ................................... 2566
11.1.30MSI Message Data (MMD)—Offset 6Ch................................................... 2567
11.1.31PCI Express Capability ID (PXID)—Offset 70h ......................................... 2567
11.1.32PCI Express Capabilities (PXC)—Offset 72h ............................................ 2568
11.1.33Device Capabilities (DEVCAP)—Offset 74h .............................................. 2568
11.1.34Device Control (DEVC)—Offset 78h ....................................................... 2569
11.1.35Device Status (DEVS)—Offset 7Ah ........................................................ 2571
11.1.36Vendor Specific Capability Identifiers (VSCID)—Offset 80h ....................... 2571
11.1.37Vendor Specific Extended Capability (VSECID)—Offset 84h....................... 2572
11.1.38Device Idle Pointer (DEVIDLEPTR)—Offset 8Ch ....................................... 2573
11.1.39Device Idle Power On Latency (DEVIDLEPOL)—Offset 90h ........................ 2573
11.1.40Virtual Channel Enhanced Capability Header (VCCAP)—Offset 100h ........... 2574
11.1.41Port VC Capability Register 1 (PVCCAP1)—Offset 104h ............................. 2575
11.1.42Port VC Capability Register 2 (PVCCAP2)—Offset 108h ............................. 2576
11.1.43Port VC Control Register (PVCCTL)—Offset 10Ch ..................................... 2576
11.1.44Port VC Status Register (PVCSTS)—Offset 10Eh ...................................... 2577
11.1.45VC0 Resource Capability Register (VC0CAP)—Offset 110h ........................ 2577
11.1.46VC0 Resource Control Register (VC0CTL)—Offset 114h ............................ 2578
11.1.47VC0 Resource Status Register (VC0STS)—Offset 11Ah ............................. 2579
11.1.48VCi Resource Capability Register (VCiCAP)—Offset 11Ch .......................... 2580
11.1.49VCi Resource Control Register (VCiCTL)—Offset 120h .............................. 2580
11.1.50VCi Resource Status Register (VCiSTS)—Offset 126h ............................... 2581
11.1.51Root Complex Link Declaration Enhanced (RCCAP)—Offset 130h ............... 2582
11.1.52Element Self Description (ESD)—Offset 134h.......................................... 2582
11.1.53Link 1 Description (L1DESC)—Offset 140h.............................................. 2583
11.1.54Link 1 Lower Address (L1LADD)—Offset 148h ......................................... 2584
11.1.55Link 1 Upper Address (L1UADD)—Offset 14Ch ........................................ 2584
11.1.56I/O Buffer Control (IOBCTL)—Offset 061Ch ............................................ 2585
11.1.57Power Management Control And Status (PCS)—Offset 0054h .................... 2586
11.1.58LTRC_D013C_PCE—Offset 1048h .......................................................... 2588
11.1.59PID_PC—Offset 0050h ......................................................................... 2589
11.2 Registers Summary........................................................................................ 2590
11.2.1 Global Capabilities (GCAP)—Offset 0h .................................................... 2604
11.2.2 Minor Version (VMIN)—Offset 2h........................................................... 2604
11.2.3 Major Version (VMAJ)—Offset 3h........................................................... 2605
11.2.4 Output Payload Capability (OUTPAY)—Offset 4h ...................................... 2605
11.2.5 Input Payload Capability (INPAY)—Offset 6h........................................... 2606
11.2.6 Global Control (GCTL)—Offset 8h .......................................................... 2607
11.2.7 Wake Enable (WAKEEN)—Offset Ch ....................................................... 2609
11.2.8 Wake Status (WAKESTS)—Offset Eh...................................................... 2609
11.2.9 Global Status (GSTS)—Offset 10h ......................................................... 2610
11.2.10Global Capabilities 2 (GCAP2)—Offset 12h.............................................. 2610
11.2.11Linked List Capabilities Header (LLCH)—Offset 14h.................................. 2611
11.2.12Output Stream Payload Capability (OUTSTRMPAY)—Offset 18h ................. 2612
11.2.13Input Stream Payload Capability (INSTRMPAY)—Offset 1Ah ...................... 2612
11.2.14Interrupt Control (INTCTL)—Offset 20h.................................................. 2613

58 334818
 11.2.15Interrupt Status (INTSTS)—Offset 24h ...................................................2614
11.2.16Wall Clock Counter (WALCLK)—Offset 30h ..............................................2615
11.2.17Stream Synchronization (SSYNC)—Offset 38h .........................................2616
11.2.18CORB Lower Base Address (CORBLBASE)—Offset 40h ..............................2617
11.2.19CORB Upper Base Address (CORBUBASE)—Offset 44h ..............................2617
11.2.20CORB Write Pointer (CORBWP)—Offset 48h.............................................2618
11.2.21CORB Read Pointer (CORBRP)—Offset 4Ah..............................................2618
11.2.22CORB Control (CORBCTL)—Offset 4Ch....................................................2619
11.2.23CORB Status (CORBSTS)—Offset 4Dh ....................................................2620
11.2.24CORB Size (CORBSIZE)—Offset 4Eh.......................................................2620
11.2.25RIRB Lower Base Address (RIRBLBASE)—Offset 50h ................................2621
11.2.26RIRB Upper Base Address (RIRBUBASE)—Offset 54h ................................2622
11.2.27RIRB Write Pointer (RIRBWP)—Offset 58h...............................................2622
11.2.28Response Interrupt Count (RINTCNT)—Offset 5Ah ...................................2623
11.2.29RIRB Control (RIRBCTL)—Offset 5Ch......................................................2623
11.2.30RIRB Status (RIRBSTS)—Offset 5Dh ......................................................2624
11.2.31RIRB Size (RIRBSIZE)—Offset 5Eh.........................................................2625
11.2.32Immediate Command Status (ICS)—Offset 68h .......................................2625
11.2.33DMA Position Lower Base Address (DPLBASE)—Offset 70h ........................2626
11.2.34DMA Position Upper Base Address (DPUBASE)—Offset 74h........................2627
11.2.35Input/Output Stream Descriptor x Control (ISD0CTL)—Offset 80h..............2628
11.2.36Input/Output Stream Descriptor x Status (ISD0STS)—Offset 83h ..............2629
11.2.37Input/Output Stream Descriptor x Link Position in Buffer (ISD0LPIB)—Offset 84h
2631
11.2.38Input/Output Stream Descriptor x Cyclic Buffer Length (ISD0CBL)—Offset 88h ...
2631
11.2.39Input/Output Stream Descriptor x Last Valid Index (ISD0LVI)—Offset 8Ch ..2632
11.2.40Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW)—Offset
8Eh ...................................................................................................2633
11.2.41Input/Output Stream Descriptor x FIFO Size (ISD0FIFOS)—Offset 90h .......2633
11.2.42Input/Output Stream Descriptor x Format (ISD0FMT)—Offset 92h .............2634
11.2.43Input/Output Stream Descriptor x FIFO Limit (ISD0FIFOL)—Offset 94h.......2636
11.2.44Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD0BDLPLBA)—Offset 98h .....................................................2636
11.2.45Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD0BDLPUBA)—Offset 9Ch.....................................................2637
11.2.46Input/Output Stream Descriptor x Control (ISD1CTL)—Offset A0h..............2637
11.2.47Input/Output Stream Descriptor x Status (ISD1STS)—Offset A3h ..............2639
11.2.48Input/Output Stream Descriptor x Link Position in Buffer (ISD1LPIB)—Offset A4h
2641
11.2.49Input/Output Stream Descriptor x Cyclic Buffer Length (ISD1CBL)—Offset A8h...
2641
11.2.50Input/Output Stream Descriptor x Last Valid Index (ISD1LVI)—Offset ACh..2642
11.2.51Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD1FIFOW)—Offset
AEh ...................................................................................................2643
11.2.52Input/Output Stream Descriptor x FIFO Size (ISD1FIFOS)—Offset B0h .......2643
11.2.53Input/Output Stream Descriptor x Format (ISD1FMT)—Offset B2h .............2644
11.2.54Input/Output Stream Descriptor x FIFO Limit (ISD1FIFOL)—Offset B4h ......2646
11.2.55Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD1BDLPLBA)—Offset B8h .....................................................2646
11.2.56Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD1BDLPUBA)—Offset BCh.....................................................2647
11.2.57Input/Output Stream Descriptor x Control (ISD2CTL)—Offset C0h .............2647
11.2.58Input/Output Stream Descriptor x Status (ISD2STS)—Offset C3h ..............2649
11.2.59Input/Output Stream Descriptor x Link Position in Buffer (ISD2LPIB)—Offset C4h
2651

334818 59
 11.2.60Input/Output Stream Descriptor x Cyclic Buffer Length (ISD2CBL)—Offset C8h ..
2651
11.2.61Input/Output Stream Descriptor x Last Valid Index (ISD2LVI)—Offset CCh . 2652
11.2.62Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD2FIFOW)—Offset
CEh .................................................................................................. 2653
11.2.63Input/Output Stream Descriptor x FIFO Size (ISD2FIFOS)—Offset D0h ...... 2653
11.2.64Input/Output Stream Descriptor x Format (ISD2FMT)—Offset D2h ............ 2654
11.2.65Input/Output Stream Descriptor x FIFO Limit (ISD2FIFOL)—Offset D4h...... 2656
11.2.66Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD2BDLPLBA)—Offset D8h .................................................... 2656
11.2.67Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD2BDLPUBA)—Offset DCh.................................................... 2657
11.2.68Input/Output Stream Descriptor x Control (ISD3CTL)—Offset E0h ............. 2657
11.2.69Input/Output Stream Descriptor x Status (ISD3STS)—Offset E3h .............. 2659
11.2.70Input/Output Stream Descriptor x Link Position in Buffer (ISD3LPIB)—Offset E4h
2661
11.2.71Input/Output Stream Descriptor x Cyclic Buffer Length (ISD3CBL)—Offset E8h ..
2661
11.2.72Input/Output Stream Descriptor x Last Valid Index (ISD3LVI)—Offset ECh . 2662
11.2.73Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD3FIFOW)—Offset
EEh................................................................................................... 2663
11.2.74Input/Output Stream Descriptor x FIFO Size (ISD3FIFOS)—Offset F0h ....... 2663
11.2.75Input/Output Stream Descriptor x Format (ISD3FMT)—Offset F2h ............. 2664
11.2.76Input/Output Stream Descriptor x FIFO Limit (ISD3FIFOL)—Offset F4h ...... 2666
11.2.77Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD3BDLPLBA)—Offset F8h ..................................................... 2666
11.2.78Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD3BDLPUBA)—Offset FCh .................................................... 2667
11.2.79Input/Output Stream Descriptor x Control (ISD4CTL)—Offset 100h ........... 2667
11.2.80Input/Output Stream Descriptor x Status (ISD4STS)—Offset 103h ............ 2669
11.2.81Input/Output Stream Descriptor x Link Position in Buffer (ISD4LPIB)—Offset 104h
2671
11.2.82Input/Output Stream Descriptor x Cyclic Buffer Length (ISD4CBL)—Offset 108h.
2671
11.2.83Input/Output Stream Descriptor x Last Valid Index (ISD4LVI)—Offset 10Ch 2672
11.2.84Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD4FIFOW)—Offset
10Eh ................................................................................................. 2673
11.2.85Input/Output Stream Descriptor x FIFO Size (ISD4FIFOS)—Offset 110h ..... 2673
11.2.86Input/Output Stream Descriptor x Format (ISD4FMT)—Offset 112h ........... 2674
11.2.87Input/Output Stream Descriptor x FIFO Limit (ISD4FIFOL)—Offset 114h .... 2676
11.2.88Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD4BDLPLBA)—Offset 118h ................................................... 2676
11.2.89Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD4BDLPUBA)—Offset 11Ch .................................................. 2677
11.2.90Input/Output Stream Descriptor x Control (ISD5CTL)—Offset 120h ........... 2677
11.2.91Input/Output Stream Descriptor x Status (ISD5STS)—Offset 123h ............ 2679
11.2.92Input/Output Stream Descriptor x Link Position in Buffer (ISD5LPIB)—Offset 124h
2681
11.2.93Input/Output Stream Descriptor x Cyclic Buffer Length (ISD5CBL)—Offset 128h.
2681
11.2.94Input/Output Stream Descriptor x Last Valid Index (ISD5LVI)—Offset 12Ch 2682
11.2.95Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD5FIFOW)—Offset
12Eh ................................................................................................. 2683
11.2.96Input/Output Stream Descriptor x FIFO Size (ISD5FIFOS)—Offset 130h ..... 2683
11.2.97Input/Output Stream Descriptor x Format (ISD5FMT)—Offset 132h ........... 2684
11.2.98Input/Output Stream Descriptor x FIFO Limit (ISD5FIFOL)—Offset 134h .... 2686

60 334818
 11.2.99Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD5BDLPLBA)—Offset 138h....................................................2686
11.2.100Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD5BDLPUBA)—Offset 13Ch ...................................................2687
11.2.101Input/Output Stream Descriptor x Control (ISD6CTL)—Offset 140h ..........2687
11.2.102Input/Output Stream Descriptor x Status (ISD6STS)—Offset 143h ...........2689
11.2.103Input/Output Stream Descriptor x Link Position in Buffer (ISD6LPIB)—Offset
144h .................................................................................................2691
11.2.104Input/Output Stream Descriptor x Cyclic Buffer Length (ISD6CBL)—Offset 148h
2691
11.2.105Input/Output Stream Descriptor x Last Valid Index (ISD6LVI)—Offset 14Ch......
2692
11.2.106Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD6FIFOW)—
Offset 14Eh ........................................................................................2693
11.2.107Input/Output Stream Descriptor x FIFO Size (ISD6FIFOS)—Offset 150h ....2693
11.2.108Input/Output Stream Descriptor x Format (ISD6FMT)—Offset 152h ..........2694
11.2.109Input/Output Stream Descriptor x FIFO Limit (ISD6FIFOL)—Offset 154h ...2696
11.2.110Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD6BDLPLBA)—Offset 158h....................................................2696
11.2.111Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD6BDLPUBA)—Offset 15Ch ...................................................2697
11.2.112Input/Output Stream Descriptor x Control (OSD0CTL)—Offset 160h .........2697
11.2.113Input/Output Stream Descriptor x Status (OSD0STS)—Offset 163h ..........2699
11.2.114Input/Output Stream Descriptor x Link Position in Buffer (OSD0LPIB)—Offset
164h .................................................................................................2701
11.2.115Input/Output Stream Descriptor x Cyclic Buffer Length (OSD0CBL)—Offset 168h
2701
11.2.116Input/Output Stream Descriptor x Last Valid Index (OSD0LVI)—Offset 16Ch.....
2702
11.2.117Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD0FIFOW)—
Offset 16Eh ........................................................................................2703
11.2.118Input/Output Stream Descriptor x FIFO Size (OSD0FIFOS)—Offset 170h ...2703
11.2.119Input/Output Stream Descriptor x Format (OSD0FMT)—Offset 172h .........2704
11.2.120Input/Output Stream Descriptor x FIFO Limit (OSD0FIFOL)—Offset 174h ..2706
11.2.121Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD0BDLPLBA)—Offset 178h...................................................2706
11.2.122Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD0BDLPUBA)—Offset 17Ch ..................................................2707
11.2.123Input/Output Stream Descriptor x Control (OSD1CTL)—Offset 180h .........2708
11.2.124Input/Output Stream Descriptor x Status (OSD1STS)—Offset 183h ..........2709
11.2.125Input/Output Stream Descriptor x Link Position in Buffer (OSD1LPIB)—Offset
184h .................................................................................................2711
11.2.126Input/Output Stream Descriptor x Cyclic Buffer Length (OSD1CBL)—Offset 188h
2711
11.2.127Input/Output Stream Descriptor x Last Valid Index (OSD1LVI)—Offset 18Ch.....
2712
11.2.128Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD1FIFOW)—
Offset 18Eh ........................................................................................2713
11.2.129Input/Output Stream Descriptor x FIFO Size (OSD1FIFOS)—Offset 190h ...2713
11.2.130Input/Output Stream Descriptor x Format (OSD1FMT)—Offset 192h .........2714
11.2.131Input/Output Stream Descriptor x FIFO Limit (OSD1FIFOL)—Offset 194h ..2716
11.2.132Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD1BDLPLBA)—Offset 198h...................................................2716
11.2.133Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD1BDLPUBA)—Offset 19Ch ..................................................2717
11.2.134Input/Output Stream Descriptor x Control (OSD2CTL)—Offset 1A0h .........2718

334818 61
 11.2.135Input/Output Stream Descriptor x Status (OSD2STS)—Offset 1A3h.......... 2719
11.2.136Input/Output Stream Descriptor x Link Position in Buffer (OSD2LPIB)—Offset
1A4h................................................................................................. 2721
11.2.137Input/Output Stream Descriptor x Cyclic Buffer Length (OSD2CBL)—Offset 1A8h
2721
11.2.138Input/Output Stream Descriptor x Last Valid Index (OSD2LVI)—Offset 1ACh ....
2722
11.2.139Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD2FIFOW)—
Offset 1AEh ....................................................................................... 2723
11.2.140Input/Output Stream Descriptor x FIFO Size (OSD2FIFOS)—Offset 1B0h .. 2723
11.2.141Input/Output Stream Descriptor x Format (OSD2FMT)—Offset 1B2h ........ 2724
11.2.142Input/Output Stream Descriptor x FIFO Limit (OSD2FIFOL)—Offset 1B4h.. 2726
11.2.143Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD2BDLPLBA)—Offset 1B8h .................................................. 2726
11.2.144Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD2BDLPUBA)—Offset 1BCh ................................................. 2727
11.2.145Input/Output Stream Descriptor x Control (OSD3CTL)—Offset 1C0h......... 2728
11.2.146Input/Output Stream Descriptor x Status (OSD3STS)—Offset 1C3h.......... 2729
11.2.147Input/Output Stream Descriptor x Link Position in Buffer (OSD3LPIB)—Offset
1C4h................................................................................................. 2731
11.2.148Input/Output Stream Descriptor x Cyclic Buffer Length (OSD3CBL)—Offset 1C8h
2731
11.2.149Input/Output Stream Descriptor x Last Valid Index (OSD3LVI)—Offset 1CCh ....
2732
11.2.150Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD3FIFOW)—
Offset 1CEh ....................................................................................... 2733
11.2.151Input/Output Stream Descriptor x FIFO Size (OSD3FIFOS)—Offset 1D0h .. 2733
11.2.152Input/Output Stream Descriptor x Format (OSD3FMT)—Offset 1D2h ........ 2734
11.2.153Input/Output Stream Descriptor x FIFO Limit (OSD3FIFOL)—Offset 1D4h . 2736
11.2.154Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD3BDLPLBA)—Offset 1D8h.................................................. 2736
11.2.155Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD3BDLPUBA)—Offset 1DCh ................................................. 2737
11.2.156Input/Output Stream Descriptor x Control (OSD4CTL)—Offset 1E0h ......... 2738
11.2.157Input/Output Stream Descriptor x Status (OSD4STS)—Offset 1E3h.......... 2739
11.2.158Input/Output Stream Descriptor x Link Position in Buffer (OSD4LPIB)—Offset
1E4h ................................................................................................. 2741
11.2.159Input/Output Stream Descriptor x Cyclic Buffer Length (OSD4CBL)—Offset 1E8h
2741
11.2.160Input/Output Stream Descriptor x Last Valid Index (OSD4LVI)—Offset 1ECh ....
2742
11.2.161Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD4FIFOW)—
Offset 1EEh........................................................................................ 2743
11.2.162Input/Output Stream Descriptor x FIFO Size (OSD4FIFOS)—Offset 1F0h... 2743
11.2.163Input/Output Stream Descriptor x Format (OSD4FMT)—Offset 1F2h ......... 2744
11.2.164Input/Output Stream Descriptor x FIFO Limit (OSD4FIFOL)—Offset 1F4h .. 2746
11.2.165Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD4BDLPLBA)—Offset 1F8h .................................................. 2746
11.2.166Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD4BDLPUBA)—Offset 1FCh.................................................. 2747
11.2.167Input/Output Stream Descriptor x Control (OSD5CTL)—Offset 200h ......... 2747
11.2.168Input/Output Stream Descriptor x Status (OSD5STS)—Offset 203h.......... 2749
11.2.169Input/Output Stream Descriptor x Link Position in Buffer (OSD5LPIB)—Offset
204h ................................................................................................. 2751
11.2.170Input/Output Stream Descriptor x Cyclic Buffer Length (OSD5CBL)—Offset 208h
2751

62 334818
 11.2.171Input/Output Stream Descriptor x Last Valid Index (OSD5LVI)—Offset 20Ch.....
2752
11.2.172Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD5FIFOW)—
Offset 20Eh ........................................................................................2753
11.2.173Input/Output Stream Descriptor x FIFO Size (OSD5FIFOS)—Offset 210h ...2753
11.2.174Input/Output Stream Descriptor x Format (OSD5FMT)—Offset 212h .........2754
11.2.175Input/Output Stream Descriptor x FIFO Limit (OSD5FIFOL)—Offset 214h ..2756
11.2.176Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD5BDLPLBA)—Offset 218h...................................................2756
11.2.177Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD5BDLPUBA)—Offset 21Ch ..................................................2757
11.2.178Global Time Synchronization Capability Header (GTSCH)—Offset 500h ......2758
11.2.179Global Time Synchronization Controller Adjust Control (GTSCTLAC)—Offset 50Ch
2758
11.2.180Global Time Synchronization Capture Control (GTSCC0)—Offset 520h .......2759
11.2.181Wall Frame Counter Captured (WALFCC0)—Offset 524h ..........................2760
11.2.182Time Stamp Counter Captured Lower (TSCCL0)—Offset 528h ..................2761
11.2.183Time Stamp Counter Captured Upper (TSCCU0)—Offset 52Ch..................2761
11.2.184Linear Link Position Frame Offset Captured (LLPFOC0)—Offset 534h .........2762
11.2.185Linear Link Position Captured Lower (LLPCL0)—Offset 538h .....................2762
11.2.186Linear Link Position Captured Upper (LLPCU0)—Offset 53Ch ....................2763
11.2.187Global Time Synchronization Capture Control (GTSCC1)—Offset 540h .......2763
11.2.188Wall Frame Counter Captured (WALFCC1)—Offset 544h ..........................2764
11.2.189Time Stamp Counter Captured Lower (TSCCL1)—Offset 548h ..................2765
11.2.190Time Stamp Counter Captured Upper (TSCCU1)—Offset 54Ch..................2765
11.2.191Linear Link Position Frame Offset Captured (LLPFOC1)—Offset 554h .........2766
11.2.192Linear Link Position Captured Lower (LLPCL1)—Offset 558h .....................2766
11.2.193Linear Link Position Captured Upper (LLPCU1)—Offset 55Ch ....................2767
11.2.194Software Position Based FIFO Capability Header (SPBFCH)—Offset 700h ...2767
11.2.195Software Position Based FIFO Control (SPBFCTL)—Offset 704h.................2768
11.2.196Input/Output Stream Descriptor x Software Position in Buffer (ISD0SPIB)—
Offset 708h ........................................................................................2769
11.2.197Input/Output Stream Descriptor x Max FIFO Size (ISD0MAXFIFOS)—Offset 70Ch
2769
11.2.198Input/Output Stream Descriptor x Software Position in Buffer (ISD1SPIB)—
Offset 710h ........................................................................................2770
11.2.199Input/Output Stream Descriptor x Max FIFO Size (ISD1MAXFIFOS)—Offset 714h
2770
11.2.200Input/Output Stream Descriptor x Software Position in Buffer (ISD2SPIB)—
Offset 718h ........................................................................................2771
11.2.201Input/Output Stream Descriptor x Max FIFO Size (ISD2MAXFIFOS)—Offset 71Ch
2772
11.2.202Input/Output Stream Descriptor x Software Position in Buffer (ISD3SPIB)—
Offset 720h ........................................................................................2772
11.2.203Input/Output Stream Descriptor x Max FIFO Size (ISD3MAXFIFOS)—Offset 724h
2773
11.2.204Input/Output Stream Descriptor x Software Position in Buffer (ISD4SPIB)—
Offset 728h ........................................................................................2773
11.2.205Input/Output Stream Descriptor x Max FIFO Size (ISD4MAXFIFOS)—Offset 72Ch
2774
11.2.206Input/Output Stream Descriptor x Software Position in Buffer (ISD5SPIB)—
Offset 730h ........................................................................................2775
11.2.207Input/Output Stream Descriptor x Max FIFO Size (ISD5MAXFIFOS)—Offset 734h
2775
11.2.208Input/Output Stream Descriptor x Software Position in Buffer (ISD6SPIB)—
Offset 738h ........................................................................................2776

334818 63
 11.2.209Input/Output Stream Descriptor x Max FIFO Size (ISD6MAXFIFOS)—Offset 73Ch
2776
11.2.210Input/Output Stream Descriptor x Software Position in Buffer (OSD0SPIB)—
Offset 740h........................................................................................ 2777
11.2.211Input/Output Stream Descriptor x Max FIFO Size (OSD0MAXFIFOS)—Offset
744h ................................................................................................. 2778
11.2.212Input/Output Stream Descriptor x Software Position in Buffer (OSD1SPIB)—
Offset 748h........................................................................................ 2778
11.2.213Input/Output Stream Descriptor x Max FIFO Size (OSD1MAXFIFOS)—Offset
74Ch................................................................................................. 2779
11.2.214Input/Output Stream Descriptor x Software Position in Buffer (OSD2SPIB)—
Offset 750h........................................................................................ 2779
11.2.215Input/Output Stream Descriptor x Max FIFO Size (OSD2MAXFIFOS)—Offset
754h ................................................................................................. 2780
11.2.216Input/Output Stream Descriptor x Software Position in Buffer (OSD3SPIB)—
Offset 758h........................................................................................ 2780
11.2.217Input/Output Stream Descriptor x Max FIFO Size (OSD3MAXFIFOS)—Offset
75Ch................................................................................................. 2781
11.2.218Input/Output Stream Descriptor x Software Position in Buffer (OSD4SPIB)—
Offset 760h........................................................................................ 2782
11.2.219Input/Output Stream Descriptor x Max FIFO Size (OSD4MAXFIFOS)—Offset
764h ................................................................................................. 2782
11.2.220Input/Output Stream Descriptor x Software Position in Buffer (OSD5SPIB)—
Offset 768h........................................................................................ 2783
11.2.221Input/Output Stream Descriptor x Max FIFO Size (OSD5MAXFIFOS)—Offset
76Ch................................................................................................. 2783
11.2.222Processing Pipe Capability Header (PPCH)—Offset 800h .......................... 2784
11.2.223Processing Pipe Control (PPCTL)—Offset 804h ....................................... 2785
11.2.224Processing Pipe Status (PPSTS)—Offset 808h ........................................ 2786
11.2.225Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC0LLPL)—Offset 810h .................................................................. 2786
11.2.226Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC0LLPU)—Offset 814h ................................................................. 2787
11.2.227Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC0LDPL)—Offset 818h ................................................................. 2787
11.2.228Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC0LDPU)—Offset 81Ch................................................................. 2788
11.2.229Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC1LLPL)—Offset 820h .................................................................. 2789
11.2.230Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC1LLPU)—Offset 824h ................................................................. 2789
11.2.231Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC1LDPL)—Offset 828h ................................................................. 2790
11.2.232Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC1LDPU)—Offset 82Ch................................................................. 2790
11.2.233Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC2LLPL)—Offset 830h .................................................................. 2791
11.2.234Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC2LLPU)—Offset 834h ................................................................. 2791
11.2.235Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC2LDPL)—Offset 838h ................................................................. 2792
11.2.236Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC2LDPU)—Offset 83Ch................................................................. 2792
11.2.237Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC3LLPL)—Offset 840h .................................................................. 2793
11.2.238Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC3LLPU)—Offset 844h ................................................................. 2794

64 334818
 11.2.239Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC3LDPL)—Offset 848h ..................................................................2794
11.2.240Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC3LDPU)—Offset 84Ch .................................................................2795
11.2.241Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC4LLPL)—Offset 850h ..................................................................2795
11.2.242Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC4LLPU)—Offset 854h ..................................................................2796
11.2.243Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC4LDPL)—Offset 858h ..................................................................2796
11.2.244Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC4LDPU)—Offset 85Ch .................................................................2797
11.2.245Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC5LLPL)—Offset 860h ..................................................................2798
11.2.246Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC5LLPU)—Offset 864h ..................................................................2798
11.2.247Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC5LDPL)—Offset 868h ..................................................................2799
11.2.248Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC5LDPU)—Offset 86Ch .................................................................2799
11.2.249Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC6LLPL)—Offset 870h ..................................................................2800
11.2.250Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC6LLPU)—Offset 874h ..................................................................2801
11.2.251Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC6LDPL)—Offset 878h ..................................................................2801
11.2.252Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC6LDPU)—Offset 87Ch .................................................................2802
11.2.253Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC0LLPL)—Offset 880h .................................................................2802
11.2.254Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC0LLPU)—Offset 884h .................................................................2803
11.2.255Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC0LDPL)—Offset 888h .................................................................2803
11.2.256Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC0LDPU)—Offset 88Ch ................................................................2804
11.2.257Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC1LLPL)—Offset 890h .................................................................2805
11.2.258Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC1LLPU)—Offset 894h .................................................................2805
11.2.259Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC1LDPL)—Offset 898h .................................................................2806
11.2.260Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC1LDPU)—Offset 89Ch ................................................................2806
11.2.261Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC2LLPL)—Offset 8A0h .................................................................2807
11.2.262Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC2LLPU)—Offset 8A4h .................................................................2808
11.2.263Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC2LDPL)—Offset 8A8h.................................................................2808
11.2.264Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC2LDPU)—Offset 8ACh ................................................................2809
11.2.265Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC3LLPL)—Offset 8B0h .................................................................2809
11.2.266Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC3LLPU)—Offset 8B4h .................................................................2810

334818 65
 11.2.267Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC3LDPL)—Offset 8B8h ................................................................ 2810
11.2.268Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC3LDPU)—Offset 8BCh ............................................................... 2811
11.2.269Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC4LLPL)—Offset 8C0h................................................................. 2812
11.2.270Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC4LLPU)—Offset 8C4h ................................................................ 2812
11.2.271Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC4LDPL)—Offset 8C8h ................................................................ 2813
11.2.272Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC4LDPU)—Offset 8CCh ............................................................... 2813
11.2.273Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC5LLPL)—Offset 8D0h ................................................................ 2814
11.2.274Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC5LLPU)—Offset 8D4h ................................................................ 2815
11.2.275Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC5LDPL)—Offset 8D8h ................................................................ 2815
11.2.276Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC5LDPU)—Offset 8DCh ............................................................... 2816
11.2.277Input/Output Processing Pipe's Link Connection x Control (IPPLC0CTL)—Offset
8E0h ................................................................................................. 2816
11.2.278Input/Output Processing Pipe's Link Connection x Format (IPPLC0FMT)—Offset
8E4h ................................................................................................. 2818
11.2.279Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC0LLPL)—Offset 8E8h .................................................................. 2819
11.2.280Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC0LLPU)—Offset 8ECh .................................................................. 2820
11.2.281Input/Output Processing Pipe's Link Connection x Control (IPPLC1CTL)—Offset
8F0h ................................................................................................. 2820
11.2.282Input/Output Processing Pipe's Link Connection x Format (IPPLC1FMT)—Offset
8F4h ................................................................................................. 2821
11.2.283Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC1LLPL)—Offset 8F8h................................................................... 2823
11.2.284Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC1LLPU)—Offset 8FCh .................................................................. 2823
11.2.285Input/Output Processing Pipe's Link Connection x Control (IPPLC2CTL)—Offset
900h ................................................................................................. 2824
11.2.286Input/Output Processing Pipe's Link Connection x Format (IPPLC2FMT)—Offset
904h ................................................................................................. 2825
11.2.287Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC2LLPL)—Offset 908h .................................................................. 2826
11.2.288Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC2LLPU)—Offset 90Ch.................................................................. 2827
11.2.289Input/Output Processing Pipe's Link Connection x Control (IPPLC3CTL)—Offset
910h ................................................................................................. 2827
11.2.290Input/Output Processing Pipe's Link Connection x Format (IPPLC3FMT)—Offset
914h ................................................................................................. 2829
11.2.291Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC3LLPL)—Offset 918h .................................................................. 2830
11.2.292Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC3LLPU)—Offset 91Ch.................................................................. 2831
11.2.293Input/Output Processing Pipe's Link Connection x Control (IPPLC4CTL)—Offset
920h ................................................................................................. 2831
11.2.294Input/Output Processing Pipe's Link Connection x Format (IPPLC4FMT)—Offset
924h ................................................................................................. 2832

66 334818
 11.2.295Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC4LLPL)—Offset 928h ...................................................................2834
11.2.296Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC4LLPU)—Offset 92Ch ..................................................................2834
11.2.297Input/Output Processing Pipe's Link Connection x Control (IPPLC5CTL)—Offset
930h .................................................................................................2835
11.2.298Input/Output Processing Pipe's Link Connection x Format (IPPLC5FMT)—Offset
934h .................................................................................................2836
11.2.299Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC5LLPL)—Offset 938h ...................................................................2837
11.2.300Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC5LLPU)—Offset 93Ch ..................................................................2838
11.2.301Input/Output Processing Pipe's Link Connection x Control (IPPLC6CTL)—Offset
940h .................................................................................................2838
11.2.302Input/Output Processing Pipe's Link Connection x Format (IPPLC6FMT)—Offset
944h .................................................................................................2840
11.2.303Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC6LLPL)—Offset 948h ...................................................................2841
11.2.304Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC6LLPU)—Offset 94Ch ..................................................................2842
11.2.305Input/Output Processing Pipe's Link Connection x Control (OPPLC0CTL)—Offset
950h .................................................................................................2842
11.2.306Input/Output Processing Pipe's Link Connection x Format (OPPLC0FMT)—Offset
954h .................................................................................................2843
11.2.307Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC0LLPL)—Offset 958h ..................................................................2845
11.2.308Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC0LLPU)—Offset 95Ch .................................................................2845
11.2.309Input/Output Processing Pipe's Link Connection x Control (OPPLC1CTL)—Offset
960h .................................................................................................2846
11.2.310Input/Output Processing Pipe's Link Connection x Format (OPPLC1FMT)—Offset
964h .................................................................................................2847
11.2.311Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC1LLPL)—Offset 968h ..................................................................2848
11.2.312Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC1LLPU)—Offset 96Ch .................................................................2849
11.2.313Input/Output Processing Pipe's Link Connection x Control (OPPLC2CTL)—Offset
970h .................................................................................................2849
11.2.314Input/Output Processing Pipe's Link Connection x Format (OPPLC2FMT)—Offset
974h .................................................................................................2851
11.2.315Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC2LLPL)—Offset 978h ..................................................................2852
11.2.316Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC2LLPU)—Offset 97Ch .................................................................2853
11.2.317Input/Output Processing Pipe's Link Connection x Control (OPPLC3CTL)—Offset
980h .................................................................................................2853
11.2.318Input/Output Processing Pipe's Link Connection x Format (OPPLC3FMT)—Offset
984h .................................................................................................2854
11.2.319Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC3LLPL)—Offset 988h ..................................................................2856
11.2.320Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC3LLPU)—Offset 98Ch .................................................................2856
11.2.321Input/Output Processing Pipe's Link Connection x Control (OPPLC4CTL)—Offset
990h .................................................................................................2857
11.2.322Input/Output Processing Pipe's Link Connection x Format (OPPLC4FMT)—Offset
994h .................................................................................................2858

334818 67
 11.2.323Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC4LLPL)—Offset 998h ................................................................. 2859
11.2.324Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC4LLPU)—Offset 99Ch................................................................. 2860
11.2.325Input/Output Processing Pipe's Link Connection x Control (OPPLC5CTL)—Offset
9A0h................................................................................................. 2860
11.2.326Input/Output Processing Pipe's Link Connection x Format (OPPLC5FMT)—Offset
9A4h................................................................................................. 2862
11.2.327Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC5LLPL)—Offset 9A8h ................................................................. 2863
11.2.328Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC5LLPU)—Offset 9ACh................................................................. 2864
11.2.329Multiple Links Capability Header (MLCH)—Offset C00h............................ 2864
11.2.330Multiple Links Capability Declaration (MLCD)—Offset C04h ...................... 2865
11.2.331Link x Capabilities (LCAP0)—Offset C40h .............................................. 2865
11.2.332Link x Output Stream ID Mapping Valid (LOSIDV0)—Offset C48h ............. 2866
11.2.333Link x SDI Identifier (LSDIID0)—Offset C4Ch ........................................ 2868
11.2.334Link x Per Stream Output Overhead (LPSOO0)—Offset C50h ................... 2869
11.2.335Link x Per Stream Input Overhead (LPSIO0)—Offset C52h ...................... 2870
11.2.336Link x Wall Frame Counter (LWALFC0)—Offset C58h .............................. 2870
11.2.337Link x Output Payload Capability (LOUTPAY6M0)—Offset C60h ................ 2871
11.2.338Link x Output Payload Capability (LOUTPAY12M0)—Offset C62h............... 2872
11.2.339Link x Output Payload Capability (LOUTPAY24M0)—Offset C64h............... 2873
11.2.340Link x Output Payload Capability (LOUTPAY48M0)—Offset C66h............... 2874
11.2.341Link x Output Payload Capability (LOUTPAY96M0)—Offset C68h............... 2875
11.2.342Link x Output Payload Capability (LOUTPAY192M0)—Offset C6Ah............. 2876
11.2.343Link x Input Payload Capability (LINPAY6M0)—Offset C70h ..................... 2877
11.2.344Link x Input Payload Capability (LINPAY12M0)—Offset C72h ................... 2878
11.2.345Link x Input Payload Capability (LINPAY24M0)—Offset C74h ................... 2879
11.2.346Link x Input Payload Capability (LINPAY48M0)—Offset C76h ................... 2880
11.2.347Link x Input Payload Capability (LINPAY96M0)—Offset C78h ................... 2881
11.2.348Link x Input Payload Capability (LINPAY192M0)—Offset C7Ah ................. 2882
11.2.349Link x Capabilities (LCAP1)—Offset C80h .............................................. 2883
11.2.350Link x Output Stream ID Mapping Valid (LOSIDV1)—Offset C88h ............. 2884
11.2.351Link x SDI Identifier (LSDIID1)—Offset C8Ch ........................................ 2886
11.2.352Link x Per Stream Output Overhead (LPSOO1)—Offset C90h ................... 2887
11.2.353Link x Per Stream Input Overhead (LPSIO1)—Offset C92h ...................... 2887
11.2.354Link x Wall Frame Counter (LWALFC1)—Offset C98h .............................. 2888
11.2.355Link x Output Payload Capability (LOUTPAY6M1)—Offset CA0h ................ 2888
11.2.356Link x Output Payload Capability (LOUTPAY12M1)—Offset CA2h .............. 2889
11.2.357Link x Output Payload Capability (LOUTPAY24M1)—Offset CA4h .............. 2890
11.2.358Link x Output Payload Capability (LOUTPAY48M1)—Offset CA6h .............. 2891
11.2.359Link x Output Payload Capability (LOUTPAY96M1)—Offset CA8h .............. 2892
11.2.360Link x Output Payload Capability (LOUTPAY192M1)—Offset CAAh............. 2893
11.2.361Link x Input Payload Capability (LINPAY6M1)—Offset CB0h ..................... 2894
11.2.362Link x Input Payload Capability (LINPAY12M1)—Offset CB2h ................... 2895
11.2.363Link x Input Payload Capability (LINPAY24M1)—Offset CB4h ................... 2896
11.2.364Link x Input Payload Capability (LINPAY48M1)—Offset CB6h ................... 2897
11.2.365Link x Input Payload Capability (LINPAY96M1)—Offset CB8h ................... 2898
11.2.366Link x Input Payload Capability (LINPAY192M1)—Offset CBAh ................. 2899
11.2.367DMA Resume Capability Header (DRSMCH)—Offset 1F00h ...................... 2900
11.2.368DMA Resume Control (DRSMCTL)—Offset 1F04h.................................... 2901
11.2.369DMA Position in Buffer Resume (ISD0DPIBR)—Offset 1F08h .................... 2901
11.2.370DMA Position in Buffer Resume (ISD1DPIBR)—Offset 1F10h .................... 2902
11.2.371DMA Position in Buffer Resume (ISD2DPIBR)—Offset 1F18h .................... 2902

68 334818
 11.2.372DMA Position in Buffer Resume (ISD3DPIBR)—Offset 1F20h ....................2903
11.2.373DMA Position in Buffer Resume (ISD4DPIBR)—Offset 1F28h ....................2903
11.2.374DMA Position in Buffer Resume (ISD5DPIBR)—Offset 1F30h ....................2904
11.2.375DMA Position in Buffer Resume (ISD6DPIBR)—Offset 1F38h ....................2904
11.2.376DMA Position in Buffer Resume (OSD0DPIBR)—Offset 1F40h ...................2905
11.2.377DMA Position in Buffer Resume (OSD1DPIBR)—Offset 1F48h ...................2905
11.2.378DMA Position in Buffer Resume (OSD2DPIBR)—Offset 1F50h ...................2906
11.2.379DMA Position in Buffer Resume (OSD3DPIBR)—Offset 1F58h ...................2906
11.2.380DMA Position in Buffer Resume (OSD4DPIBR)—Offset 1F60h ...................2907
11.2.381DMA Position in Buffer Resume (OSD5DPIBR)—Offset 1F68h ...................2907
11.2.382Wall Clock Alias (WLCLKA)—Offset 2030h..............................................2908
11.2.383Input Stream Descriptor 0 Link Position in Buffer Alias (ISD0LPIBA)—Offset
2084h................................................................................................2908
11.2.384Input Stream Descriptor 0 Link Position in Buffer Alias (ISD1LPIBA)—Offset
20A4h ...............................................................................................2909
11.2.385Input Stream Descriptor 0 Link Position in Buffer Alias (ISD2LPIBA)—Offset
20C4h ...............................................................................................2910
11.2.386Input Stream Descriptor 0 Link Position in Buffer Alias (ISD3LPIBA)—Offset
20E4h................................................................................................2910
11.2.387Input Stream Descriptor 0 Link Position in Buffer Alias (ISD4LPIBA)—Offset
2104h................................................................................................2911
11.2.388Input Stream Descriptor 0 Link Position in Buffer Alias (ISD5LPIBA)—Offset
2124h................................................................................................2911
11.2.389Input Stream Descriptor 0 Link Position in Buffer Alias (ISD6LPIBA)—Offset
2144h................................................................................................2912
11.2.390Input Stream Descriptor 0 Link Position in Buffer Alias (OSD0LPIBA)—Offset
2164h................................................................................................2912
11.2.391Input Stream Descriptor 0 Link Position in Buffer Alias (OSD1LPIBA)—Offset
2184h................................................................................................2913
11.2.392Input Stream Descriptor 0 Link Position in Buffer Alias (OSD2LPIBA)—Offset
21A4h ...............................................................................................2914
11.2.393Input Stream Descriptor 0 Link Position in Buffer Alias (OSD3LPIBA)—Offset
21C4h ...............................................................................................2914
11.2.394Input Stream Descriptor 0 Link Position in Buffer Alias (OSD4LPIBA)—Offset
21E4h................................................................................................2915
11.2.395Input Stream Descriptor 0 Link Position in Buffer Alias (OSD5LPIBA)—Offset
2204h................................................................................................2915
11.3 Registers Summary ........................................................................................2917
11.3.1 Vendor Identification (VID)—Offset 0h ...................................................2918
11.3.2 Device ID (DID)—Offset 2h...................................................................2919
11.3.3 Command (CMD)—Offset 4h .................................................................2919
11.3.4 Status (STS)—Offset 6h .......................................................................2920
11.3.5 Revision Identification (RID)—Offset 8h..................................................2921
11.3.6 Programming Interface (PI)—Offset 9h...................................................2922
11.3.7 Sub Class Code (SCC)—Offset Ah ..........................................................2922
11.3.8 Base Class Code (BCC)—Offset Bh .........................................................2923
11.3.9 Cache Line Size (CLS)—Offset Ch ..........................................................2923
11.3.10Latency Timer (LT)—Offset Dh ..............................................................2923
11.3.11Header Type (HTYPE)—Offset Eh ...........................................................2924
11.3.12Built-in Self Test (BIST)—Offset Fh ........................................................2924
11.3.13Intel HD Audio Base Lower Address (HDALBA)—Offset 10h .......................2925
11.3.14Intel HD Audio Base Upper Address (HDAUBA)—Offset 14h .......................2926
11.3.15Shadowed PCI Configuration Lower Base Address (SPCLBA)—Offset 18h.....2926
11.3.16Shadowed PCI Configuration Upper Base Address (SPCUBA)—Offset 1Ch ....2927
11.3.17Audio DSP Lower Base Address (ADSPLBA)—Offset 20h............................2927
11.3.18Audio DSP Upper Base Address (ADSPUBA)—Offset 24h ...........................2928

334818 69
 11.3.19Subsystem Vendor ID (SVID)—Offset 2Ch.............................................. 2928
11.3.20Subsystem ID (SID)—Offset 2Eh........................................................... 2929
11.3.21Capability Pointer (CAPPTR)—Offset 34h ................................................ 2930
11.3.22Interrupt Line (INTLN)—Offset 3Ch ....................................................... 2930
11.3.23Interrupt Pin (INTPN)—Offset 3Dh......................................................... 2931
11.3.24Test Mode 1 register (TM1)—Offset 43h ................................................. 2931
11.3.25PCI Power Management Capability ID (PID)—Offset 50h .......................... 2932
11.3.26MSI Capability ID (MID)—Offset 60h ..................................................... 2932
11.3.27MSI Message Control (MMC)—Offset 62h ............................................... 2933
11.3.28MSI Message Lower Address (MMLA)—Offset 64h.................................... 2934
11.3.29MSI Message Upper Address (MMUA)—Offset 68h ................................... 2934
11.3.30MSI Message Data (MMD)—Offset 6Ch................................................... 2934
11.3.31PCI Express Capability ID (PXID)—Offset 70h ......................................... 2935
11.3.32PCI Express Capabilities (PXC)—Offset 72h ............................................ 2935
11.3.33Device Capabilities (DEVCAP)—Offset 74h .............................................. 2936
11.3.34Device Control (DEVC)—Offset 78h ....................................................... 2937
11.3.35Device Status (DEVS)—Offset 7Ah ........................................................ 2939
11.3.36Vendor Specific Capability Identifiers (VSCID)—Offset 80h ....................... 2939
11.3.37Vendor Specific Extended Capability (VSECID)—Offset 84h....................... 2940
11.3.38Device Idle Pointer (DEVIDLEPTR)—Offset 8Ch ....................................... 2941
11.3.39Device Idle Power On Latency (DEVIDLEPOL)—Offset 90h ........................ 2941
11.3.40Virtual Channel Enhanced Capability Header (VCCAP)—Offset 100h ........... 2942
11.3.41Port VC Capability Register 1 (PVCCAP1)—Offset 104h ............................. 2943
11.3.42Port VC Capability Register 2 (PVCCAP2)—Offset 108h ............................. 2944
11.3.43Port VC Control Register (PVCCTL)—Offset 10Ch ..................................... 2944
11.3.44Port VC Status Register (PVCSTS)—Offset 10Eh ...................................... 2945
11.3.45VC0 Resource Capability Register (VC0CAP)—Offset 110h ........................ 2945
11.3.46VC0 Resource Control Register (VC0CTL)—Offset 114h ............................ 2946
11.3.47VC0 Resource Status Register (VC0STS)—Offset 11Ah ............................. 2947
11.3.48VCi Resource Capability Register (VCiCAP)—Offset 11Ch .......................... 2948
11.3.49VCi Resource Control Register (VCiCTL)—Offset 120h .............................. 2948
11.3.50VCi Resource Status Register (VCiSTS)—Offset 126h ............................... 2949
11.3.51Root Complex Link Declaration Enhanced (RCCAP)—Offset 130h ............... 2950
11.3.52Element Self Description (ESD)—Offset 134h.......................................... 2950
11.3.53Link 1 Description (L1DESC)—Offset 140h.............................................. 2951
11.3.54Link 1 Lower Address (L1LADD)—Offset 148h ......................................... 2952
11.3.55Link 1 Upper Address (L1UADD)—Offset 14Ch ........................................ 2952
11.3.56I/O Buffer Control (IOBCTL)—Offset 061Ch ............................................ 2953
11.3.57Power Management Control And Status (PCS)—Offset 0054h .................... 2954
11.3.58LTRC_D013C_PCE—Offset 1048h .......................................................... 2956
11.3.59PID_PC—Offset 0050h ......................................................................... 2957
11.4 Registers Summary........................................................................................ 2959
11.4.1 Global Capabilities (GCAP)—Offset 0h .................................................... 2972
11.4.2 Minor Version (VMIN)—Offset 2h........................................................... 2973
11.4.3 Major Version (VMAJ)—Offset 3h........................................................... 2973
11.4.4 Output Payload Capability (OUTPAY)—Offset 4h ...................................... 2974
11.4.5 Input Payload Capability (INPAY)—Offset 6h........................................... 2974
11.4.6 Global Control (GCTL)—Offset 8h .......................................................... 2975
11.4.7 Wake Enable (WAKEEN)—Offset Ch ....................................................... 2977
11.4.8 Wake Status (WAKESTS)—Offset Eh...................................................... 2977
11.4.9 Global Status (GSTS)—Offset 10h ......................................................... 2978
11.4.10Global Capabilities 2 (GCAP2)—Offset 12h.............................................. 2978
11.4.11Linked List Capabilities Header (LLCH)—Offset 14h.................................. 2979
11.4.12Output Stream Payload Capability (OUTSTRMPAY)—Offset 18h ................. 2980
11.4.13Input Stream Payload Capability (INSTRMPAY)—Offset 1Ah ...................... 2980

70 334818
 11.4.14Interrupt Control (INTCTL)—Offset 20h ..................................................2981
11.4.15Interrupt Status (INTSTS)—Offset 24h ...................................................2982
11.4.16Wall Clock Counter (WALCLK)—Offset 30h ..............................................2983
11.4.17Stream Synchronization (SSYNC)—Offset 38h .........................................2984
11.4.18CORB Lower Base Address (CORBLBASE)—Offset 40h ..............................2985
11.4.19CORB Upper Base Address (CORBUBASE)—Offset 44h ..............................2985
11.4.20CORB Write Pointer (CORBWP)—Offset 48h.............................................2986
11.4.21CORB Read Pointer (CORBRP)—Offset 4Ah..............................................2986
11.4.22CORB Control (CORBCTL)—Offset 4Ch....................................................2987
11.4.23CORB Status (CORBSTS)—Offset 4Dh ....................................................2988
11.4.24CORB Size (CORBSIZE)—Offset 4Eh.......................................................2988
11.4.25RIRB Lower Base Address (RIRBLBASE)—Offset 50h ................................2989
11.4.26RIRB Upper Base Address (RIRBUBASE)—Offset 54h ................................2990
11.4.27RIRB Write Pointer (RIRBWP)—Offset 58h...............................................2990
11.4.28Response Interrupt Count (RINTCNT)—Offset 5Ah ...................................2991
11.4.29RIRB Control (RIRBCTL)—Offset 5Ch......................................................2991
11.4.30RIRB Status (RIRBSTS)—Offset 5Dh ......................................................2992
11.4.31RIRB Size (RIRBSIZE)—Offset 5Eh.........................................................2993
11.4.32Immediate Command Status (ICS)—Offset 68h .......................................2993
11.4.33DMA Position Lower Base Address (DPLBASE)—Offset 70h ........................2994
11.4.34DMA Position Upper Base Address (DPUBASE)—Offset 74h........................2995
11.4.35Input/Output Stream Descriptor x Control (ISD0CTL)—Offset 80h..............2996
11.4.36Input/Output Stream Descriptor x Status (ISD0STS)—Offset 83h ..............2997
11.4.37Input/Output Stream Descriptor x Link Position in Buffer (ISD0LPIB)—Offset 84h
2999
11.4.38Input/Output Stream Descriptor x Cyclic Buffer Length (ISD0CBL)—Offset 88h ...
2999
11.4.39Input/Output Stream Descriptor x Last Valid Index (ISD0LVI)—Offset 8Ch ..3000
11.4.40Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD0FIFOW)—Offset
8Eh ...................................................................................................3001
11.4.41Input/Output Stream Descriptor x FIFO Size (ISD0FIFOS)—Offset 90h .......3001
11.4.42Input/Output Stream Descriptor x Format (ISD0FMT)—Offset 92h .............3002
11.4.43Input/Output Stream Descriptor x FIFO Limit (ISD0FIFOL)—Offset 94h.......3004
11.4.44Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD0BDLPLBA)—Offset 98h .....................................................3004
11.4.45Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD0BDLPUBA)—Offset 9Ch.....................................................3005
11.4.46Input/Output Stream Descriptor x Control (ISD1CTL)—Offset A0h..............3005
11.4.47Input/Output Stream Descriptor x Status (ISD1STS)—Offset A3h ..............3007
11.4.48Input/Output Stream Descriptor x Link Position in Buffer (ISD1LPIB)—Offset A4h
3009
11.4.49Input/Output Stream Descriptor x Cyclic Buffer Length (ISD1CBL)—Offset A8h...
3009
11.4.50Input/Output Stream Descriptor x Last Valid Index (ISD1LVI)—Offset ACh..3010
11.4.51Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD1FIFOW)—Offset
AEh ...................................................................................................3011
11.4.52Input/Output Stream Descriptor x FIFO Size (ISD1FIFOS)—Offset B0h .......3011
11.4.53Input/Output Stream Descriptor x Format (ISD1FMT)—Offset B2h .............3012
11.4.54Input/Output Stream Descriptor x FIFO Limit (ISD1FIFOL)—Offset B4h ......3014
11.4.55Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD1BDLPLBA)—Offset B8h .....................................................3014
11.4.56Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD1BDLPUBA)—Offset BCh.....................................................3015
11.4.57Input/Output Stream Descriptor x Control (ISD2CTL)—Offset C0h .............3015
11.4.58Input/Output Stream Descriptor x Status (ISD2STS)—Offset C3h ..............3017

334818 71
 11.4.59Input/Output Stream Descriptor x Link Position in Buffer (ISD2LPIB)—Offset C4h
3019
11.4.60Input/Output Stream Descriptor x Cyclic Buffer Length (ISD2CBL)—Offset C8h ..
3019
11.4.61Input/Output Stream Descriptor x Last Valid Index (ISD2LVI)—Offset CCh . 3020
11.4.62Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD2FIFOW)—Offset
CEh .................................................................................................. 3021
11.4.63Input/Output Stream Descriptor x FIFO Size (ISD2FIFOS)—Offset D0h ...... 3021
11.4.64Input/Output Stream Descriptor x Format (ISD2FMT)—Offset D2h ............ 3022
11.4.65Input/Output Stream Descriptor x FIFO Limit (ISD2FIFOL)—Offset D4h...... 3024
11.4.66Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD2BDLPLBA)—Offset D8h .................................................... 3024
11.4.67Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD2BDLPUBA)—Offset DCh.................................................... 3025
11.4.68Input/Output Stream Descriptor x Control (ISD3CTL)—Offset E0h ............. 3025
11.4.69Input/Output Stream Descriptor x Status (ISD3STS)—Offset E3h .............. 3027
11.4.70Input/Output Stream Descriptor x Link Position in Buffer (ISD3LPIB)—Offset E4h
3029
11.4.71Input/Output Stream Descriptor x Cyclic Buffer Length (ISD3CBL)—Offset E8h ..
3029
11.4.72Input/Output Stream Descriptor x Last Valid Index (ISD3LVI)—Offset ECh . 3030
11.4.73Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD3FIFOW)—Offset
EEh................................................................................................... 3031
11.4.74Input/Output Stream Descriptor x FIFO Size (ISD3FIFOS)—Offset F0h ....... 3031
11.4.75Input/Output Stream Descriptor x Format (ISD3FMT)—Offset F2h ............. 3032
11.4.76Input/Output Stream Descriptor x FIFO Limit (ISD3FIFOL)—Offset F4h ...... 3034
11.4.77Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD3BDLPLBA)—Offset F8h ..................................................... 3034
11.4.78Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD3BDLPUBA)—Offset FCh .................................................... 3035
11.4.79Input/Output Stream Descriptor x Control (ISD4CTL)—Offset 100h ........... 3035
11.4.80Input/Output Stream Descriptor x Status (ISD4STS)—Offset 103h ............ 3037
11.4.81Input/Output Stream Descriptor x Link Position in Buffer (ISD4LPIB)—Offset 104h
3039
11.4.82Input/Output Stream Descriptor x Cyclic Buffer Length (ISD4CBL)—Offset 108h.
3039
11.4.83Input/Output Stream Descriptor x Last Valid Index (ISD4LVI)—Offset 10Ch 3040
11.4.84Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD4FIFOW)—Offset
10Eh ................................................................................................. 3041
11.4.85Input/Output Stream Descriptor x FIFO Size (ISD4FIFOS)—Offset 110h ..... 3041
11.4.86Input/Output Stream Descriptor x Format (ISD4FMT)—Offset 112h ........... 3042
11.4.87Input/Output Stream Descriptor x FIFO Limit (ISD4FIFOL)—Offset 114h .... 3044
11.4.88Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD4BDLPLBA)—Offset 118h ................................................... 3044
11.4.89Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD4BDLPUBA)—Offset 11Ch .................................................. 3045
11.4.90Input/Output Stream Descriptor x Control (ISD5CTL)—Offset 120h ........... 3045
11.4.91Input/Output Stream Descriptor x Status (ISD5STS)—Offset 123h ............ 3047
11.4.92Input/Output Stream Descriptor x Link Position in Buffer (ISD5LPIB)—Offset 124h
3049
11.4.93Input/Output Stream Descriptor x Cyclic Buffer Length (ISD5CBL)—Offset 128h.
3049
11.4.94Input/Output Stream Descriptor x Last Valid Index (ISD5LVI)—Offset 12Ch 3050
11.4.95Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD5FIFOW)—Offset
12Eh ................................................................................................. 3051
11.4.96Input/Output Stream Descriptor x FIFO Size (ISD5FIFOS)—Offset 130h ..... 3051

72 334818
 11.4.97Input/Output Stream Descriptor x Format (ISD5FMT)—Offset 132h............3052
11.4.98Input/Output Stream Descriptor x FIFO Limit (ISD5FIFOL)—Offset 134h .....3054
11.4.99Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD5BDLPLBA)—Offset 138h....................................................3054
11.4.100Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD5BDLPUBA)—Offset 13Ch ...................................................3055
11.4.101Input/Output Stream Descriptor x Control (ISD6CTL)—Offset 140h ..........3055
11.4.102Input/Output Stream Descriptor x Status (ISD6STS)—Offset 143h ...........3057
11.4.103Input/Output Stream Descriptor x Link Position in Buffer (ISD6LPIB)—Offset
144h .................................................................................................3059
11.4.104Input/Output Stream Descriptor x Cyclic Buffer Length (ISD6CBL)—Offset 148h
3059
11.4.105Input/Output Stream Descriptor x Last Valid Index (ISD6LVI)—Offset 14Ch......
3060
11.4.106Input/Output Stream Descriptor x FIFO Eviction Watermark (ISD6FIFOW)—
Offset 14Eh ........................................................................................3061
11.4.107Input/Output Stream Descriptor x FIFO Size (ISD6FIFOS)—Offset 150h ....3061
11.4.108Input/Output Stream Descriptor x Format (ISD6FMT)—Offset 152h ..........3062
11.4.109Input/Output Stream Descriptor x FIFO Limit (ISD6FIFOL)—Offset 154h ...3064
11.4.110Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (ISD6BDLPLBA)—Offset 158h....................................................3064
11.4.111Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (ISD6BDLPUBA)—Offset 15Ch ...................................................3065
11.4.112Input/Output Stream Descriptor x Control (OSD0CTL)—Offset 160h .........3065
11.4.113Input/Output Stream Descriptor x Status (OSD0STS)—Offset 163h ..........3067
11.4.114Input/Output Stream Descriptor x Link Position in Buffer (OSD0LPIB)—Offset
164h .................................................................................................3069
11.4.115Input/Output Stream Descriptor x Cyclic Buffer Length (OSD0CBL)—Offset 168h
3069
11.4.116Input/Output Stream Descriptor x Last Valid Index (OSD0LVI)—Offset 16Ch.....
3070
11.4.117Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD0FIFOW)—
Offset 16Eh ........................................................................................3071
11.4.118Input/Output Stream Descriptor x FIFO Size (OSD0FIFOS)—Offset 170h ...3071
11.4.119Input/Output Stream Descriptor x Format (OSD0FMT)—Offset 172h .........3072
11.4.120Input/Output Stream Descriptor x FIFO Limit (OSD0FIFOL)—Offset 174h ..3074
11.4.121Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD0BDLPLBA)—Offset 178h...................................................3074
11.4.122Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD0BDLPUBA)—Offset 17Ch ..................................................3075
11.4.123Input/Output Stream Descriptor x Control (OSD1CTL)—Offset 180h .........3076
11.4.124Input/Output Stream Descriptor x Status (OSD1STS)—Offset 183h ..........3077
11.4.125Input/Output Stream Descriptor x Link Position in Buffer (OSD1LPIB)—Offset
184h .................................................................................................3079
11.4.126Input/Output Stream Descriptor x Cyclic Buffer Length (OSD1CBL)—Offset 188h
3079
11.4.127Input/Output Stream Descriptor x Last Valid Index (OSD1LVI)—Offset 18Ch.....
3080
11.4.128Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD1FIFOW)—
Offset 18Eh ........................................................................................3081
11.4.129Input/Output Stream Descriptor x FIFO Size (OSD1FIFOS)—Offset 190h ...3081
11.4.130Input/Output Stream Descriptor x Format (OSD1FMT)—Offset 192h .........3082
11.4.131Input/Output Stream Descriptor x FIFO Limit (OSD1FIFOL)—Offset 194h ..3084
11.4.132Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD1BDLPLBA)—Offset 198h...................................................3084

334818 73
 11.4.133Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD1BDLPUBA)—Offset 19Ch ................................................. 3085
11.4.134Input/Output Stream Descriptor x Control (OSD2CTL)—Offset 1A0h......... 3086
11.4.135Input/Output Stream Descriptor x Status (OSD2STS)—Offset 1A3h.......... 3087
11.4.136Input/Output Stream Descriptor x Link Position in Buffer (OSD2LPIB)—Offset
1A4h................................................................................................. 3089
11.4.137Input/Output Stream Descriptor x Cyclic Buffer Length (OSD2CBL)—Offset 1A8h
3089
11.4.138Input/Output Stream Descriptor x Last Valid Index (OSD2LVI)—Offset 1ACh ....
3090
11.4.139Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD2FIFOW)—
Offset 1AEh ....................................................................................... 3091
11.4.140Input/Output Stream Descriptor x FIFO Size (OSD2FIFOS)—Offset 1B0h .. 3091
11.4.141Input/Output Stream Descriptor x Format (OSD2FMT)—Offset 1B2h ........ 3092
11.4.142Input/Output Stream Descriptor x FIFO Limit (OSD2FIFOL)—Offset 1B4h.. 3094
11.4.143Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD2BDLPLBA)—Offset 1B8h .................................................. 3094
11.4.144Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD2BDLPUBA)—Offset 1BCh ................................................. 3095
11.4.145Input/Output Stream Descriptor x Control (OSD3CTL)—Offset 1C0h......... 3096
11.4.146Input/Output Stream Descriptor x Status (OSD3STS)—Offset 1C3h.......... 3097
11.4.147Input/Output Stream Descriptor x Link Position in Buffer (OSD3LPIB)—Offset
1C4h................................................................................................. 3099
11.4.148Input/Output Stream Descriptor x Cyclic Buffer Length (OSD3CBL)—Offset 1C8h
3099
11.4.149Input/Output Stream Descriptor x Last Valid Index (OSD3LVI)—Offset 1CCh ....
3100
11.4.150Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD3FIFOW)—
Offset 1CEh ....................................................................................... 3101
11.4.151Input/Output Stream Descriptor x FIFO Size (OSD3FIFOS)—Offset 1D0h .. 3101
11.4.152Input/Output Stream Descriptor x Format (OSD3FMT)—Offset 1D2h ........ 3102
11.4.153Input/Output Stream Descriptor x FIFO Limit (OSD3FIFOL)—Offset 1D4h . 3104
11.4.154Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD3BDLPLBA)—Offset 1D8h.................................................. 3104
11.4.155Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD3BDLPUBA)—Offset 1DCh ................................................. 3105
11.4.156Input/Output Stream Descriptor x Control (OSD4CTL)—Offset 1E0h ......... 3106
11.4.157Input/Output Stream Descriptor x Status (OSD4STS)—Offset 1E3h.......... 3107
11.4.158Input/Output Stream Descriptor x Link Position in Buffer (OSD4LPIB)—Offset
1E4h ................................................................................................. 3109
11.4.159Input/Output Stream Descriptor x Cyclic Buffer Length (OSD4CBL)—Offset 1E8h
3109
11.4.160Input/Output Stream Descriptor x Last Valid Index (OSD4LVI)—Offset 1ECh ....
3110
11.4.161Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD4FIFOW)—
Offset 1EEh........................................................................................ 3111
11.4.162Input/Output Stream Descriptor x FIFO Size (OSD4FIFOS)—Offset 1F0h... 3111
11.4.163Input/Output Stream Descriptor x Format (OSD4FMT)—Offset 1F2h ......... 3112
11.4.164Input/Output Stream Descriptor x FIFO Limit (OSD4FIFOL)—Offset 1F4h .. 3114
11.4.165Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD4BDLPLBA)—Offset 1F8h .................................................. 3114
11.4.166Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD4BDLPUBA)—Offset 1FCh.................................................. 3115
11.4.167Input/Output Stream Descriptor x Control (OSD5CTL)—Offset 200h ......... 3115
11.4.168Input/Output Stream Descriptor x Status (OSD5STS)—Offset 203h.......... 3117

74 334818
 11.4.169Input/Output Stream Descriptor x Link Position in Buffer (OSD5LPIB)—Offset
204h .................................................................................................3119
11.4.170Input/Output Stream Descriptor x Cyclic Buffer Length (OSD5CBL)—Offset 208h
3119
11.4.171Input/Output Stream Descriptor x Last Valid Index (OSD5LVI)—Offset 20Ch.....
3120
11.4.172Input/Output Stream Descriptor x FIFO Eviction Watermark (OSD5FIFOW)—
Offset 20Eh ........................................................................................3121
11.4.173Input/Output Stream Descriptor x FIFO Size (OSD5FIFOS)—Offset 210h ...3121
11.4.174Input/Output Stream Descriptor x Format (OSD5FMT)—Offset 212h .........3122
11.4.175Input/Output Stream Descriptor x FIFO Limit (OSD5FIFOL)—Offset 214h ..3124
11.4.176Input/Output Stream Descriptor x Buffer Descriptor List Pointer Lower Base
Address (OSD5BDLPLBA)—Offset 218h...................................................3124
11.4.177Input/Output Stream Descriptor x Buffer Descriptor List Pointer Upper Base
Address (OSD5BDLPUBA)—Offset 21Ch ..................................................3125
11.4.178Global Time Synchronization Capability Header (GTSCH)—Offset 500h ......3126
11.4.179Global Time Synchronization Controller Adjust Control (GTSCTLAC)—Offset 50Ch
3126
11.4.180Global Time Synchronization Capture Control (GTSCC0)—Offset 520h .......3127
11.4.181Wall Frame Counter Captured (WALFCC0)—Offset 524h ..........................3128
11.4.182Time Stamp Counter Captured Lower (TSCCL0)—Offset 528h ..................3129
11.4.183Time Stamp Counter Captured Upper (TSCCU0)—Offset 52Ch..................3129
11.4.184Linear Link Position Frame Offset Captured (LLPFOC0)—Offset 534h .........3130
11.4.185Linear Link Position Captured Lower (LLPCL0)—Offset 538h .....................3130
11.4.186Linear Link Position Captured Upper (LLPCU0)—Offset 53Ch ....................3131
11.4.187Global Time Synchronization Capture Control (GTSCC1)—Offset 540h .......3131
11.4.188Wall Frame Counter Captured (WALFCC1)—Offset 544h ..........................3132
11.4.189Time Stamp Counter Captured Lower (TSCCL1)—Offset 548h ..................3133
11.4.190Time Stamp Counter Captured Upper (TSCCU1)—Offset 54Ch..................3133
11.4.191Linear Link Position Frame Offset Captured (LLPFOC1)—Offset 554h .........3134
11.4.192Linear Link Position Captured Lower (LLPCL1)—Offset 558h .....................3134
11.4.193Linear Link Position Captured Upper (LLPCU1)—Offset 55Ch ....................3135
11.4.194Software Position Based FIFO Capability Header (SPBFCH)—Offset 700h ...3135
11.4.195Software Position Based FIFO Control (SPBFCTL)—Offset 704h.................3136
11.4.196Input/Output Stream Descriptor x Software Position in Buffer (ISD0SPIB)—
Offset 708h ........................................................................................3137
11.4.197Input/Output Stream Descriptor x Max FIFO Size (ISD0MAXFIFOS)—Offset 70Ch
3137
11.4.198Input/Output Stream Descriptor x Software Position in Buffer (ISD1SPIB)—
Offset 710h ........................................................................................3138
11.4.199Input/Output Stream Descriptor x Max FIFO Size (ISD1MAXFIFOS)—Offset 714h
3138
11.4.200Input/Output Stream Descriptor x Software Position in Buffer (ISD2SPIB)—
Offset 718h ........................................................................................3139
11.4.201Input/Output Stream Descriptor x Max FIFO Size (ISD2MAXFIFOS)—Offset 71Ch
3140
11.4.202Input/Output Stream Descriptor x Software Position in Buffer (ISD3SPIB)—
Offset 720h ........................................................................................3140
11.4.203Input/Output Stream Descriptor x Max FIFO Size (ISD3MAXFIFOS)—Offset 724h
3141
11.4.204Input/Output Stream Descriptor x Software Position in Buffer (ISD4SPIB)—
Offset 728h ........................................................................................3141
11.4.205Input/Output Stream Descriptor x Max FIFO Size (ISD4MAXFIFOS)—Offset 72Ch
3142
11.4.206Input/Output Stream Descriptor x Software Position in Buffer (ISD5SPIB)—
Offset 730h ........................................................................................3143

334818 75
 11.4.207Input/Output Stream Descriptor x Max FIFO Size (ISD5MAXFIFOS)—Offset 734h
3143
11.4.208Input/Output Stream Descriptor x Software Position in Buffer (ISD6SPIB)—
Offset 738h........................................................................................ 3144
11.4.209Input/Output Stream Descriptor x Max FIFO Size (ISD6MAXFIFOS)—Offset 73Ch
3144
11.4.210Input/Output Stream Descriptor x Software Position in Buffer (OSD0SPIB)—
Offset 740h........................................................................................ 3145
11.4.211Input/Output Stream Descriptor x Max FIFO Size (OSD0MAXFIFOS)—Offset
744h ................................................................................................. 3146
11.4.212Input/Output Stream Descriptor x Software Position in Buffer (OSD1SPIB)—
Offset 748h........................................................................................ 3146
11.4.213Input/Output Stream Descriptor x Max FIFO Size (OSD1MAXFIFOS)—Offset
74Ch................................................................................................. 3147
11.4.214Input/Output Stream Descriptor x Software Position in Buffer (OSD2SPIB)—
Offset 750h........................................................................................ 3147
11.4.215Input/Output Stream Descriptor x Max FIFO Size (OSD2MAXFIFOS)—Offset
754h ................................................................................................. 3148
11.4.216Input/Output Stream Descriptor x Software Position in Buffer (OSD3SPIB)—
Offset 758h........................................................................................ 3148
11.4.217Input/Output Stream Descriptor x Max FIFO Size (OSD3MAXFIFOS)—Offset
75Ch................................................................................................. 3149
11.4.218Input/Output Stream Descriptor x Software Position in Buffer (OSD4SPIB)—
Offset 760h........................................................................................ 3150
11.4.219Input/Output Stream Descriptor x Max FIFO Size (OSD4MAXFIFOS)—Offset
764h ................................................................................................. 3150
11.4.220Input/Output Stream Descriptor x Software Position in Buffer (OSD5SPIB)—
Offset 768h........................................................................................ 3151
11.4.221Input/Output Stream Descriptor x Max FIFO Size (OSD5MAXFIFOS)—Offset
76Ch................................................................................................. 3151
11.4.222Processing Pipe Capability Header (PPCH)—Offset 800h .......................... 3152
11.4.223Processing Pipe Control (PPCTL)—Offset 804h ....................................... 3153
11.4.224Processing Pipe Status (PPSTS)—Offset 808h ........................................ 3154
11.4.225Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC0LLPL)—Offset 810h .................................................................. 3154
11.4.226Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC0LLPU)—Offset 814h ................................................................. 3155
11.4.227Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC0LDPL)—Offset 818h ................................................................. 3155
11.4.228Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC0LDPU)—Offset 81Ch................................................................. 3156
11.4.229Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC1LLPL)—Offset 820h .................................................................. 3157
11.4.230Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC1LLPU)—Offset 824h ................................................................. 3157
11.4.231Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC1LDPL)—Offset 828h ................................................................. 3158
11.4.232Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC1LDPU)—Offset 82Ch................................................................. 3158
11.4.233Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC2LLPL)—Offset 830h .................................................................. 3159
11.4.234Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC2LLPU)—Offset 834h ................................................................. 3159
11.4.235Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC2LDPL)—Offset 838h ................................................................. 3160
11.4.236Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC2LDPU)—Offset 83Ch................................................................. 3160

76 334818
 11.4.237Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC3LLPL)—Offset 840h ..................................................................3161
11.4.238Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC3LLPU)—Offset 844h ..................................................................3162
11.4.239Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC3LDPL)—Offset 848h ..................................................................3162
11.4.240Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC3LDPU)—Offset 84Ch .................................................................3163
11.4.241Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC4LLPL)—Offset 850h ..................................................................3163
11.4.242Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC4LLPU)—Offset 854h ..................................................................3164
11.4.243Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC4LDPL)—Offset 858h ..................................................................3164
11.4.244Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC4LDPU)—Offset 85Ch .................................................................3165
11.4.245Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC5LLPL)—Offset 860h ..................................................................3166
11.4.246Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC5LLPU)—Offset 864h ..................................................................3166
11.4.247Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC5LDPL)—Offset 868h ..................................................................3167
11.4.248Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC5LDPU)—Offset 86Ch .................................................................3167
11.4.249Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(IPPHC6LLPL)—Offset 870h ..................................................................3168
11.4.250Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(IPPHC6LLPU)—Offset 874h ..................................................................3169
11.4.251Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(IPPHC6LDPL)—Offset 878h ..................................................................3169
11.4.252Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(IPPHC6LDPU)—Offset 87Ch .................................................................3170
11.4.253Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC0LLPL)—Offset 880h .................................................................3170
11.4.254Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC0LLPU)—Offset 884h .................................................................3171
11.4.255Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC0LDPL)—Offset 888h .................................................................3171
11.4.256Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC0LDPU)—Offset 88Ch ................................................................3172
11.4.257Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC1LLPL)—Offset 890h .................................................................3173
11.4.258Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC1LLPU)—Offset 894h .................................................................3173
11.4.259Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC1LDPL)—Offset 898h .................................................................3174
11.4.260Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC1LDPU)—Offset 89Ch ................................................................3174
11.4.261Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC2LLPL)—Offset 8A0h .................................................................3175
11.4.262Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC2LLPU)—Offset 8A4h .................................................................3176
11.4.263Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC2LDPL)—Offset 8A8h.................................................................3176
11.4.264Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC2LDPU)—Offset 8ACh ................................................................3177

334818 77
 11.4.265Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC3LLPL)—Offset 8B0h................................................................. 3177
11.4.266Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC3LLPU)—Offset 8B4h ................................................................ 3178
11.4.267Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC3LDPL)—Offset 8B8h ................................................................ 3178
11.4.268Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC3LDPU)—Offset 8BCh ............................................................... 3179
11.4.269Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC4LLPL)—Offset 8C0h................................................................. 3180
11.4.270Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC4LLPU)—Offset 8C4h ................................................................ 3180
11.4.271Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC4LDPL)—Offset 8C8h ................................................................ 3181
11.4.272Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC4LDPU)—Offset 8CCh ............................................................... 3181
11.4.273Input/Output Processing Pipe's Host Connection x Linear Link Position Lower
(OPPHC5LLPL)—Offset 8D0h ................................................................ 3182
11.4.274Input/Output Processing Pipe's Host Connection x Linear Link Position Upper
(OPPHC5LLPU)—Offset 8D4h ................................................................ 3183
11.4.275Input/Output Processing Pipe's Host Connection x Linear DMA Position Lower
(OPPHC5LDPL)—Offset 8D8h ................................................................ 3183
11.4.276Input/Output Processing Pipe's Host Connection x Linear DMA Position Upper
(OPPHC5LDPU)—Offset 8DCh ............................................................... 3184
11.4.277Input/Output Processing Pipe's Link Connection x Control (IPPLC0CTL)—Offset
8E0h ................................................................................................. 3184
11.4.278Input/Output Processing Pipe's Link Connection x Format (IPPLC0FMT)—Offset
8E4h ................................................................................................. 3186
11.4.279Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC0LLPL)—Offset 8E8h .................................................................. 3187
11.4.280Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC0LLPU)—Offset 8ECh .................................................................. 3188
11.4.281Input/Output Processing Pipe's Link Connection x Control (IPPLC1CTL)—Offset
8F0h ................................................................................................. 3188
11.4.282Input/Output Processing Pipe's Link Connection x Format (IPPLC1FMT)—Offset
8F4h ................................................................................................. 3189
11.4.283Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC1LLPL)—Offset 8F8h................................................................... 3191
11.4.284Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC1LLPU)—Offset 8FCh .................................................................. 3191
11.4.285Input/Output Processing Pipe's Link Connection x Control (IPPLC2CTL)—Offset
900h ................................................................................................. 3192
11.4.286Input/Output Processing Pipe's Link Connection x Format (IPPLC2FMT)—Offset
904h ................................................................................................. 3193
11.4.287Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC2LLPL)—Offset 908h .................................................................. 3194
11.4.288Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC2LLPU)—Offset 90Ch.................................................................. 3195
11.4.289Input/Output Processing Pipe's Link Connection x Control (IPPLC3CTL)—Offset
910h ................................................................................................. 3195
11.4.290Input/Output Processing Pipe's Link Connection x Format (IPPLC3FMT)—Offset
914h ................................................................................................. 3197
11.4.291Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC3LLPL)—Offset 918h .................................................................. 3198
11.4.292Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC3LLPU)—Offset 91Ch.................................................................. 3199

78 334818
 11.4.293Input/Output Processing Pipe's Link Connection x Control (IPPLC4CTL)—Offset
920h .................................................................................................3199
11.4.294Input/Output Processing Pipe's Link Connection x Format (IPPLC4FMT)—Offset
924h .................................................................................................3200
11.4.295Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC4LLPL)—Offset 928h ...................................................................3202
11.4.296Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC4LLPU)—Offset 92Ch ..................................................................3202
11.4.297Input/Output Processing Pipe's Link Connection x Control (IPPLC5CTL)—Offset
930h .................................................................................................3203
11.4.298Input/Output Processing Pipe's Link Connection x Format (IPPLC5FMT)—Offset
934h .................................................................................................3204
11.4.299Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC5LLPL)—Offset 938h ...................................................................3205
11.4.300Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC5LLPU)—Offset 93Ch ..................................................................3206
11.4.301Input/Output Processing Pipe's Link Connection x Control (IPPLC6CTL)—Offset
940h .................................................................................................3206
11.4.302Input/Output Processing Pipe's Link Connection x Format (IPPLC6FMT)—Offset
944h .................................................................................................3208
11.4.303Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(IPPLC6LLPL)—Offset 948h ...................................................................3209
11.4.304Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(IPPLC6LLPU)—Offset 94Ch ..................................................................3210
11.4.305Input/Output Processing Pipe's Link Connection x Control (OPPLC0CTL)—Offset
950h .................................................................................................3210
11.4.306Input/Output Processing Pipe's Link Connection x Format (OPPLC0FMT)—Offset
954h .................................................................................................3211
11.4.307Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC0LLPL)—Offset 958h ..................................................................3213
11.4.308Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC0LLPU)—Offset 95Ch .................................................................3213
11.4.309Input/Output Processing Pipe's Link Connection x Control (OPPLC1CTL)—Offset
960h .................................................................................................3214
11.4.310Input/Output Processing Pipe's Link Connection x Format (OPPLC1FMT)—Offset
964h .................................................................................................3215
11.4.311Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC1LLPL)—Offset 968h ..................................................................3216
11.4.312Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC1LLPU)—Offset 96Ch .................................................................3217
11.4.313Input/Output Processing Pipe's Link Connection x Control (OPPLC2CTL)—Offset
970h .................................................................................................3217
11.4.314Input/Output Processing Pipe's Link Connection x Format (OPPLC2FMT)—Offset
974h .................................................................................................3219
11.4.315Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC2LLPL)—Offset 978h ..................................................................3220
11.4.316Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC2LLPU)—Offset 97Ch .................................................................3221
11.4.317Input/Output Processing Pipe's Link Connection x Control (OPPLC3CTL)—Offset
980h .................................................................................................3221
11.4.318Input/Output Processing Pipe's Link Connection x Format (OPPLC3FMT)—Offset
984h .................................................................................................3222
11.4.319Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC3LLPL)—Offset 988h ..................................................................3224
11.4.320Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC3LLPU)—Offset 98Ch .................................................................3224

334818 79
 11.4.321Input/Output Processing Pipe's Link Connection x Control (OPPLC4CTL)—Offset
990h ................................................................................................. 3225
11.4.322Input/Output Processing Pipe's Link Connection x Format (OPPLC4FMT)—Offset
994h ................................................................................................. 3226
11.4.323Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC4LLPL)—Offset 998h ................................................................. 3227
11.4.324Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC4LLPU)—Offset 99Ch................................................................. 3228
11.4.325Input/Output Processing Pipe's Link Connection x Control (OPPLC5CTL)—Offset
9A0h................................................................................................. 3228
11.4.326Input/Output Processing Pipe's Link Connection x Format (OPPLC5FMT)—Offset
9A4h................................................................................................. 3230
11.4.327Input/Output Processing Pipe's Link Connection x Linear Link Position Lower
(OPPLC5LLPL)—Offset 9A8h ................................................................. 3231
11.4.328Input/Output Processing Pipe's Link Connection x Linear Link Position Upper
(OPPLC5LLPU)—Offset 9ACh................................................................. 3232
11.4.329Multiple Links Capability Header (MLCH)—Offset C00h............................ 3232
11.4.330Multiple Links Capability Declaration (MLCD)—Offset C04h ...................... 3233
11.4.331Link x Capabilities (LCAP0)—Offset C40h .............................................. 3233
11.4.332Link x Output Stream ID Mapping Valid (LOSIDV0)—Offset C48h ............. 3234
11.4.333Link x SDI Identifier (LSDIID0)—Offset C4Ch ........................................ 3236
11.4.334Link x Per Stream Output Overhead (LPSOO0)—Offset C50h ................... 3237
11.4.335Link x Per Stream Input Overhead (LPSIO0)—Offset C52h ...................... 3238
11.4.336Link x Wall Frame Counter (LWALFC0)—Offset C58h .............................. 3238
11.4.337Link x Output Payload Capability (LOUTPAY6M0)—Offset C60h ................ 3239
11.4.338Link x Output Payload Capability (LOUTPAY12M0)—Offset C62h............... 3240
11.4.339Link x Output Payload Capability (LOUTPAY24M0)—Offset C64h............... 3241
11.4.340Link x Output Payload Capability (LOUTPAY48M0)—Offset C66h............... 3242
11.4.341Link x Output Payload Capability (LOUTPAY96M0)—Offset C68h............... 3243
11.4.342Link x Output Payload Capability (LOUTPAY192M0)—Offset C6Ah............. 3244
11.4.343Link x Input Payload Capability (LINPAY6M0)—Offset C70h ..................... 3245
11.4.344Link x Input Payload Capability (LINPAY12M0)—Offset C72h ................... 3246
11.4.345Link x Input Payload Capability (LINPAY24M0)—Offset C74h ................... 3247
11.4.346Link x Input Payload Capability (LINPAY48M0)—Offset C76h ................... 3248
11.4.347Link x Input Payload Capability (LINPAY96M0)—Offset C78h ................... 3249
11.4.348Link x Input Payload Capability (LINPAY192M0)—Offset C7Ah ................. 3250
11.4.349Link x Capabilities (LCAP1)—Offset C80h .............................................. 3251
11.4.350Link x Output Stream ID Mapping Valid (LOSIDV1)—Offset C88h ............. 3252
11.4.351Link x SDI Identifier (LSDIID1)—Offset C8Ch ........................................ 3254
11.4.352Link x Per Stream Output Overhead (LPSOO1)—Offset C90h ................... 3255
11.4.353Link x Per Stream Input Overhead (LPSIO1)—Offset C92h ...................... 3255
11.4.354Link x Wall Frame Counter (LWALFC1)—Offset C98h .............................. 3256
11.4.355Link x Output Payload Capability (LOUTPAY6M1)—Offset CA0h ................ 3256
11.4.356Link x Output Payload Capability (LOUTPAY12M1)—Offset CA2h .............. 3257
11.4.357Link x Output Payload Capability (LOUTPAY24M1)—Offset CA4h .............. 3258
11.4.358Link x Output Payload Capability (LOUTPAY48M1)—Offset CA6h .............. 3259
11.4.359Link x Output Payload Capability (LOUTPAY96M1)—Offset CA8h .............. 3260
11.4.360Link x Output Payload Capability (LOUTPAY192M1)—Offset CAAh............. 3261
11.4.361Link x Input Payload Capability (LINPAY6M1)—Offset CB0h ..................... 3262
11.4.362Link x Input Payload Capability (LINPAY12M1)—Offset CB2h ................... 3263
11.4.363Link x Input Payload Capability (LINPAY24M1)—Offset CB4h ................... 3264
11.4.364Link x Input Payload Capability (LINPAY48M1)—Offset CB6h ................... 3265
11.4.365Link x Input Payload Capability (LINPAY96M1)—Offset CB8h ................... 3266
11.4.366Link x Input Payload Capability (LINPAY192M1)—Offset CBAh ................. 3267
11.4.367DMA Resume Capability Header (DRSMCH)—Offset 1F00h ...................... 3268

80 334818
 11.4.368DMA Resume Control (DRSMCTL)—Offset 1F04h ....................................3269
11.4.369DMA Position in Buffer Resume (ISD0DPIBR)—Offset 1F08h ....................3269
11.4.370DMA Position in Buffer Resume (ISD1DPIBR)—Offset 1F10h ....................3270
11.4.371DMA Position in Buffer Resume (ISD2DPIBR)—Offset 1F18h ....................3270
11.4.372DMA Position in Buffer Resume (ISD3DPIBR)—Offset 1F20h ....................3271
11.4.373DMA Position in Buffer Resume (ISD4DPIBR)—Offset 1F28h ....................3271
11.4.374DMA Position in Buffer Resume (ISD5DPIBR)—Offset 1F30h ....................3272
11.4.375DMA Position in Buffer Resume (ISD6DPIBR)—Offset 1F38h ....................3272
11.4.376DMA Position in Buffer Resume (OSD0DPIBR)—Offset 1F40h ...................3273
11.4.377DMA Position in Buffer Resume (OSD1DPIBR)—Offset 1F48h ...................3273
11.4.378DMA Position in Buffer Resume (OSD2DPIBR)—Offset 1F50h ...................3274
11.4.379DMA Position in Buffer Resume (OSD3DPIBR)—Offset 1F58h ...................3274
11.4.380DMA Position in Buffer Resume (OSD4DPIBR)—Offset 1F60h ...................3275
11.4.381DMA Position in Buffer Resume (OSD5DPIBR)—Offset 1F68h ...................3275
11.4.382Wall Clock Alias (WLCLKA)—Offset 2030h..............................................3276
11.4.383Input Stream Descriptor 0 Link Position in Buffer Alias (ISD0LPIBA)—Offset
2084h................................................................................................3276
11.4.384Input Stream Descriptor 0 Link Position in Buffer Alias (ISD1LPIBA)—Offset
20A4h ...............................................................................................3277
11.4.385Input Stream Descriptor 0 Link Position in Buffer Alias (ISD2LPIBA)—Offset
20C4h ...............................................................................................3278
11.4.386Input Stream Descriptor 0 Link Position in Buffer Alias (ISD3LPIBA)—Offset
20E4h................................................................................................3278
11.4.387Input Stream Descriptor 0 Link Position in Buffer Alias (ISD4LPIBA)—Offset
2104h................................................................................................3279
11.4.388Input Stream Descriptor 0 Link Position in Buffer Alias (ISD5LPIBA)—Offset
2124h................................................................................................3279
11.4.389Input Stream Descriptor 0 Link Position in Buffer Alias (ISD6LPIBA)—Offset
2144h................................................................................................3280
11.4.390Input Stream Descriptor 0 Link Position in Buffer Alias (OSD0LPIBA)—Offset
2164h................................................................................................3280
11.4.391Input Stream Descriptor 0 Link Position in Buffer Alias (OSD1LPIBA)—Offset
2184h................................................................................................3281
11.4.392Input Stream Descriptor 0 Link Position in Buffer Alias (OSD2LPIBA)—Offset
21A4h ...............................................................................................3282
11.4.393Input Stream Descriptor 0 Link Position in Buffer Alias (OSD3LPIBA)—Offset
21C4h ...............................................................................................3282
11.4.394Input Stream Descriptor 0 Link Position in Buffer Alias (OSD4LPIBA)—Offset
21E4h................................................................................................3283
11.4.395Input Stream Descriptor 0 Link Position in Buffer Alias (OSD5LPIBA)—Offset
2204h................................................................................................3283
12 Power Management Controller (PMC) ...................................................................3285
12.1 Registers Summary ........................................................................................3285
12.1.1 Power Management 1 Status and Enable (PM1_STS_EN)—Offset 0h ...........3285
12.1.2 Power Management 1 Control (PM1_CNT)—Offset 4h ...............................3290
12.1.3 Power Management 1 Timer (PM1_TMR)—Offset 8h .................................3291
12.1.4 General Purpose Event 0 Status (GPE0a_STS)—Offset 20h........................3291
12.1.5 General Purpose Event 0 Status (GPE0b_STS)—Offset 24h .......................3295
12.1.6 General Purpose Event 0 Status (GPE0c_STS)—Offset 28h........................3295
12.1.7 General Purpose Event 0 Status (GPE0d_STS)—Offset 2Ch .......................3296
12.1.8 General Purpose Event 0 Enables (GPE0a_EN)—Offset 30h .......................3296
12.1.9 General Purpose Event 0 Enable (GPE0b_EN)—Offset 34h.........................3300
12.1.10General Purpose Event 0 Enable (GPE0c_EN)—Offset 38h .........................3300
12.1.11General Purpose Event 0 Enable (GPE0d_EN)—Offset 3Ch.........................3301
12.1.12SMI Control and Enable (SMI_EN)—Offset 40h ........................................3301

334818 81
 12.1.13SMI Status Register (SMI_STS)—Offset 44h ........................................... 3304
12.1.14Device Trap Status (DEVTRAP_STS)—Offset 4Ch..................................... 3308
12.1.15General Purpose Event Control (GPE_CTRL)—Offset 50h .......................... 3309
12.1.16TCO Reload Register (TCO_RLD)—Offset 60h.......................................... 3309
12.1.17TCO Timer Status (TCO_STS)—Offset 64h.............................................. 3310
12.1.18TCO Timer Control (TCO1_CNT)—Offset 68h........................................... 3311
12.1.19TCO Timer Register (TCO_TMR)—Offset 70h........................................... 3311
12.1.20Advanced Power Management Status (APM_STS)—Offset 74h................... 3312
12.1.21Advanced Power Management Control Port (APM_CNT)—Offset 78h ........... 3313
12.1.22Direct IRQ Enables (DIRECT_IRQ_EN)—Offset 7Ch .................................. 3313
12.1.23PCI Configuration Control 1 Register(PCICFGCTR1)—Offset 200h .............. 3315
12.1.24PCI Configuration Control 2 Register(PCICFGCTR2)—Offset 204h .............. 3316
12.1.25PCI Configuration Control 3 Register(PCICFGCTR3)—Offset 208h .............. 3317
12.2 Registers Summary........................................................................................ 3318
12.2.1 Power and Reset Status (PRSTS)—Offset 1000h...................................... 3319
12.2.2 PM CFG - Power Management Configuration (PMC_CFG)—Offset 1008h ...... 3319
12.2.3 Power Management Configuration (PMC_CFG2)—Offset 100Ch.................. 3322
12.2.4 SOC Power Management Status (SOC_PM_STS)—Offset 1010h ................. 3323
12.2.5 General PM Configuration 1 (GEN_PMCON1)—Offset 1020h ...................... 3324
12.2.6 General PM Configuration 2 (GEN_PMCON2)—Offset 1024h ...................... 3327
12.2.7 General PM Configuration 3 (GEN_PMCON3)—Offset 1028h ...................... 3329
12.2.8 Configured Revision ID (CRID)—Offset 1030h ......................................... 3331
12.2.9 Function Disable 0 (FUNC_DIS_0)—Offset 1034h .................................... 3332
12.2.10Function Disable 1 (FUNC_DIS_1)—Offset 1038h .................................... 3334
12.2.11Extended Test Mode Register (ETR)—Offset 1048h .................................. 3335
12.2.12GPIO Group to General Purpose Event Register Configuration (GPIO_GPE_CFG)—
Offset 1050h ...................................................................................... 3336
12.2.13IRQ Select 0 (IRQ_SEL_0)—Offset 1064h............................................... 3338
12.2.14IRQ Select 1 (IRQ_SEL_1)—Offset 1068h............................................... 3339
12.2.15IRQ Select 2 (IRQ_SEL_2)—Offset 106Ch .............................................. 3340
12.2.16Function ACPI Enumeration 0 (FUNC_ACPI_ENUM_0)—Offset 1070h.......... 3340
12.2.17Function ACPI Enumeration 1 (FUNC_ACPI_ENUM_1)—Offset 1074h.......... 3342
12.2.18Fixed Deep S0Ix Counter Lower 32 Bits (TELEM_DEEP_S0IX_LO_HOST)—Offset
1078h ............................................................................................... 3343
12.2.19Fixed Deep S0Ix Counter Upper 32 Bits (TELEM_DEEP_S0IX_HI_HOST)—Offset
107Ch ............................................................................................... 3344
12.2.20Fixed Shallow S0Ix Counter Lower 32 Bits (TELEM_SHALLOW_S0IX_LO_HOST)—
Offset 1080h ...................................................................................... 3344
12.2.21Fixed Shallow S0Ix Counter Upper 32 Bits (TELEM_SHALLOW_S0IX_HI_HOST)—
Offset 1084h ...................................................................................... 3345
12.2.22Reserved (TELEM_MISC_FIXED_LO_HOST)—Offset 1088h........................ 3345
12.2.23Reserved register for sharing data with software upper 32 bits
(TELEM_MISC_FIXED_HI_HOST)—Offset 108Ch...................................... 3346
12.2.24Scratchpad for sharing data between BIOS and PMC Firmware
(BIOS_SCRATCHPAD)—Offset 1090h ..................................................... 3347
12.2.25Display Hot Plug Detect Control (DISPLAY_HPD_CTL)—Offset 1094h.......... 3349
12.2.26OBFF Control and Status (OBFF_CTL_STS)—Offset 10C8h ........................ 3350
12.2.27Lock Register (LOCK)—Offset 10CCh ..................................................... 3352
12.3 Registers Summary........................................................................................ 3354
12.3.1 IPC Command (IPC_CMD)—Offset 0h .................................................... 3354
12.3.2 IPC Status (IPC_STS)—Offset 4h .......................................................... 3355
12.3.3 IPC Source Pointer (IPC_SPTR)—Offset 8h ............................................. 3356
12.3.4 IPC Destination Pointer (IPC_DPTR)—Offset Ch ....................................... 3357
12.3.5 IPC Write Buffer (IPC_WBUF0)—Offset 80h ............................................ 3357
12.3.6 IPC Write Buffer (IPC_WBUF1)—Offset 84h ............................................ 3358

82 334818
 12.3.7 IPC Write Buffer (IPC_WBUF2)—Offset 88h .............................................3358
12.3.8 IPC Write Buffer (IPC_WBUF3)—Offset 8Ch.............................................3359
12.3.9 IPC Read Buffer (IPC_RBUF0)—Offset 90h ..............................................3359
12.3.10IPC Read Buffer (IPC_RBUF1)—Offset 94h ..............................................3360
12.3.11IPC Read Buffer (IPC_RBUF2)—Offset 98h ..............................................3360
12.3.12IPC Read Buffer (IPC_RBUF3)—Offset 9Ch ..............................................3361
12.4 Registers Summary ........................................................................................3361
12.4.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3362
12.4.2 STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..3363
12.4.3 REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
3364
12.4.4 CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ...........................................................................................3364
12.4.5 BAR -Base Address Register (BAR)—Offset 10h .......................................3365
12.4.6 BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................3366
12.4.7 BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................3366
12.4.8 BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................3367
12.4.9 (BAR2)—Offset 20h ............................................................................3368
12.4.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................3368
12.4.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ......
3369
12.4.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h...........3369
12.4.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ............3370
12.4.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h.....
3371
12.4.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................3372
12.4.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset 90h
3372
12.4.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h 3373
12.4.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................3374
12.4.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................3374
12.4.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................3375
12.5 Registers Summary ........................................................................................3376
12.5.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3377
12.5.2 STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..3377
12.5.3 REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
3379
12.5.4 CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ...........................................................................................3379
12.5.5 BAR -Base Address Register (BAR)—Offset 10h .......................................3380
12.5.6 BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................3381
12.5.7 BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................3381
12.5.8 BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................3382
12.5.9 (BAR2)—Offset 20h ............................................................................3383
12.5.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................3383
12.5.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ......
3384
12.5.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h...........3384

334818 83
 12.5.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ............ 3385
12.5.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h ....
3386
12.5.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h ............................................................ 3387
12.5.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset 90h
3387
12.5.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h 3388
12.5.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 3389
12.5.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 3389
12.5.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 3390
12.6 Registers Summary........................................................................................ 3391
12.6.1 PWM Control Register (PWMCTRL_0)—Offset 0h...................................... 3391
12.6.2 PWM D0i3 Control Register (PWMD0i3C)—Offset 100h ............................. 3392
12.6.3 PWM Control Register (PWMCTRL_1)—Offset 400h .................................. 3393
12.6.4 PWM Control Register (PWMCTRL_2)—Offset 800h .................................. 3394
12.6.5 PWM Control Register (PWMCTRL_3)—Offset C00h .................................. 3395
12.7 Registers Summary........................................................................................ 3396
12.7.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3397
12.7.2 STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h . 3398
12.7.3 REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h......
3399
12.7.4 CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ........................................................................................... 3400
12.7.5 BAR -Base Address Register (BAR)—Offset 10h....................................... 3400
12.7.6 BAR -Base Address Register High (BAR_HIGH)—Offset 14h ...................... 3401
12.7.7 BAR1 -Base Address Register1 (BAR1)—Offset 18h ................................. 3402
12.7.8 BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ................. 3402
12.7.9 (BAR2)—Offset 20h............................................................................ 3403
12.7.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch .................................................................................................. 3403
12.7.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h .....
3404
12.7.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h .......... 3405
12.7.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ............ 3405
12.7.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h ....
3406
12.7.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h ............................................................ 3407
12.7.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset 90h
3408
12.7.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h 3408
12.7.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 3409
12.7.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 3410
12.7.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 3410
12.8 Registers Summary........................................................................................ 3411
12.8.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3412
12.8.2 STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h . 3413

84 334818
 12.8.3 REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
3414
12.8.4 CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ...........................................................................................3414
12.8.5 BAR -Base Address Register (BAR)—Offset 10h .......................................3415
12.8.6 BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................3416
12.8.7 BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................3416
12.8.8 BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................3417
12.8.9 (BAR2)—Offset 20h ............................................................................3418
12.8.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................3418
12.8.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ......
3419
12.8.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h...........3419
12.8.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ............3420
12.8.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h.....
3421
12.8.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................3422
12.8.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset 90h
3422
12.8.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h 3423
12.8.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................3424
12.8.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................3424
12.8.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................3425
12.9 Registers Summary ........................................................................................3426
12.9.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3427
12.9.2 STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..3427
12.9.3 REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
3429
12.9.4 CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ...........................................................................................3429
12.9.5 BAR -Base Address Register (BAR)—Offset 10h .......................................3430
12.9.6 BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................3431
12.9.7 BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................3431
12.9.8 BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................3432
12.9.9 (BAR2)—Offset 20h ............................................................................3433
12.9.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................3433
12.9.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ......
3434
12.9.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h...........3434
12.9.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ............3435
12.9.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h.....
3436
12.9.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................3437
12.9.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset 90h
3437
12.9.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h 3438
12.9.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................3439

334818 85
 12.9.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 3439
12.9.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 3440
12.10 Registers Summary........................................................................................ 3441
12.10.1DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3442
12.10.2STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h . 3442
12.10.3REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h......
3444
12.10.4CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ........................................................................................... 3444
12.10.5BAR -Base Address Register (BAR)—Offset 10h....................................... 3445
12.10.6BAR -Base Address Register High (BAR_HIGH)—Offset 14h ...................... 3446
12.10.7BAR1 -Base Address Register1 (BAR1)—Offset 18h ................................. 3446
12.10.8BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ................. 3447
12.10.9 (BAR2)—Offset 20h............................................................................ 3448
12.10.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch .................................................................................................. 3448
12.10.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ....
3449
12.10.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h......... 3449
12.10.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch .......... 3450
12.10.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h...
3451
12.10.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h ............................................................ 3452
12.10.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset
90h................................................................................................... 3452
12.10.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h .....
3453
12.10.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 3454
12.10.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 3454
12.10.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 3455
12.11 Registers Summary........................................................................................ 3457
12.11.1Power Management 1 Status and Enable (PM1_STS_EN)—Offset 0h .......... 3457
12.11.2Power Management 1 Control (PM1_CNT)—Offset 4h ............................... 3462
12.11.3Power Management 1 Timer (PM1_TMR)—Offset 8h................................. 3463
12.11.4General Purpose Event 0 Status (GPE0a_STS)—Offset 20h ....................... 3463
12.11.5General Purpose Event 0 Status (GPE0b_STS)—Offset 24h ....................... 3467
12.11.6General Purpose Event 0 Status (GPE0c_STS)—Offset 28h ....................... 3467
12.11.7General Purpose Event 0 Status (GPE0d_STS)—Offset 2Ch....................... 3468
12.11.8General Purpose Event 0 Enables (GPE0a_EN)—Offset 30h ....................... 3468
12.11.9General Purpose Event 0 Enable (GPE0b_EN)—Offset 34h ........................ 3472
12.11.10General Purpose Event 0 Enable (GPE0c_EN)—Offset 38h ....................... 3472
12.11.11General Purpose Event 0 Enable (GPE0d_EN)—Offset 3Ch....................... 3473
12.11.12SMI Control and Enable (SMI_EN)—Offset 40h ...................................... 3473
12.11.13SMI Status Register (SMI_STS)—Offset 44h.......................................... 3476
12.11.14Device Trap Status (DEVTRAP_STS)—Offset 4Ch ................................... 3480
12.11.15General Purpose Event Control (GPE_CTRL)—Offset 50h ......................... 3481
12.11.16TCO Reload Register (TCO_RLD)—Offset 60h ........................................ 3481
12.11.17TCO Timer Status (TCO_STS)—Offset 64h ............................................ 3482
12.11.18TCO Timer Control (TCO1_CNT)—Offset 68h ......................................... 3483

86 334818
 12.11.19TCO Timer Register (TCO_TMR)—Offset 70h ..........................................3483
12.11.20Advanced Power Management Status (APM_STS)—Offset 74h..................3484
12.11.21Advanced Power Management Control Port (APM_CNT)—Offset 78h ..........3485
12.11.22Direct IRQ Enables (DIRECT_IRQ_EN)—Offset 7Ch .................................3485
12.11.23PCI Configuration Control 1 Register(PCICFGCTR1)—Offset 200h..............3487
12.11.24PCI Configuration Control 2 Register(PCICFGCTR2)—Offset 204h..............3488
12.11.25PCI Configuration Control 3 Register(PCICFGCTR3)—Offset 208h..............3489
12.12 Registers Summary ........................................................................................3491
12.12.1Power and Reset Status (PRSTS)—Offset 1000h ......................................3491
12.12.2PM CFG - Power Management Configuration (PMC_CFG)—Offset 1008h ......3492
12.12.3Power Management Configuration (PMC_CFG2)—Offset 100Ch ..................3495
12.12.4SOC Power Management Status (SOC_PM_STS)—Offset 1010h .................3496
12.12.5General PM Configuration 1 (GEN_PMCON1)—Offset 1020h.......................3497
12.12.6General PM Configuration 2 (GEN_PMCON2)—Offset 1024h.......................3500
12.12.7General PM Configuration 3 (GEN_PMCON3)—Offset 1028h.......................3502
12.12.8Configured Revision ID (CRID)—Offset 1030h .........................................3504
12.12.9Function Disable 0 (FUNC_DIS_0)—Offset 1034h.....................................3505
12.12.10Function Disable 1 (FUNC_DIS_1)—Offset 1038h ...................................3507
12.12.11Extended Test Mode Register (ETR)—Offset 1048h .................................3508
12.12.12GPIO Group to General Purpose Event Register Configuration
(GPIO_GPE_CFG)—Offset 1050h ...........................................................3509
12.12.13IRQ Select 0 (IRQ_SEL_0)—Offset 1064h..............................................3511
12.12.14IRQ Select 1 (IRQ_SEL_1)—Offset 1068h..............................................3512
12.12.15IRQ Select 2 (IRQ_SEL_2)—Offset 106Ch..............................................3513
12.12.16Function ACPI Enumeration 0 (FUNC_ACPI_ENUM_0)—Offset 1070h .........3513
12.12.17Function ACPI Enumeration 1 (FUNC_ACPI_ENUM_1)—Offset 1074h .........3515
12.12.18Fixed Deep S0Ix Counter Lower 32 Bits (TELEM_DEEP_S0IX_LO_HOST)—Offset
1078h................................................................................................3516
12.12.19Fixed Deep S0Ix Counter Upper 32 Bits (TELEM_DEEP_S0IX_HI_HOST)—Offset
107Ch ...............................................................................................3517
12.12.20Fixed Shallow S0Ix Counter Lower 32 Bits
(TELEM_SHALLOW_S0IX_LO_HOST)—Offset 1080h .................................3517
12.12.21Fixed Shallow S0Ix Counter Upper 32 Bits (TELEM_SHALLOW_S0IX_HI_HOST)—
Offset 1084h ......................................................................................3518
12.12.22Reserved (TELEM_MISC_FIXED_LO_HOST)—Offset 1088h.......................3518
12.12.23Reserved register for sharing data with software upper 32 bits
(TELEM_MISC_FIXED_HI_HOST)—Offset 108Ch ......................................3519
12.12.24Scratchpad for sharing data between BIOS and PMC Firmware
(BIOS_SCRATCHPAD)—Offset 1090h .....................................................3520
12.12.25Display Hot Plug Detect Control (DISPLAY_HPD_CTL)—Offset 1094h.........3522
12.12.26OBFF Control and Status (OBFF_CTL_STS)—Offset 10C8h .......................3523
12.12.27Lock Register (LOCK)—Offset 10CCh ....................................................3525
12.13 Registers Summary ........................................................................................3529
12.13.1IPC Command (IPC_CMD)—Offset 0h .....................................................3529
12.13.2IPC Status (IPC_STS)—Offset 4h ...........................................................3530
12.13.3IPC Source Pointer (IPC_SPTR)—Offset 8h ..............................................3531
12.13.4IPC Destination Pointer (IPC_DPTR)—Offset Ch .......................................3532
12.13.5IPC Write Buffer (IPC_WBUF0)—Offset 80h .............................................3532
12.13.6IPC Write Buffer (IPC_WBUF1)—Offset 84h .............................................3533
12.13.7IPC Write Buffer (IPC_WBUF2)—Offset 88h .............................................3533
12.13.8IPC Write Buffer (IPC_WBUF3)—Offset 8Ch.............................................3534
12.13.9IPC Read Buffer (IPC_RBUF0)—Offset 90h ..............................................3534
12.13.10IPC Read Buffer (IPC_RBUF1)—Offset 94h.............................................3535
12.13.11IPC Read Buffer (IPC_RBUF2)—Offset 98h.............................................3535
12.13.12IPC Read Buffer (IPC_RBUF3)—Offset 9Ch ............................................3536

334818 87
 12.14 Registers Summary........................................................................................ 3537
12.14.1DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3537
12.14.2STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h . 3538
12.14.3REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h......
3539
12.14.4CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ........................................................................................... 3540
12.14.5BAR -Base Address Register (BAR)—Offset 10h....................................... 3540
12.14.6BAR -Base Address Register High (BAR_HIGH)—Offset 14h ...................... 3541
12.14.7BAR1 -Base Address Register1 (BAR1)—Offset 18h ................................. 3542
12.14.8BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ................. 3542
12.14.9 (BAR2)—Offset 20h............................................................................ 3543
12.14.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch .................................................................................................. 3543
12.14.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ....
3544
12.14.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h......... 3545
12.14.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch .......... 3545
12.14.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h...
3546
12.14.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h ............................................................ 3547
12.14.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset
90h................................................................................................... 3548
12.14.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h .....
3548
12.14.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 3549
12.14.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 3550
12.14.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 3550
12.15 Registers Summary........................................................................................ 3553
12.15.1DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3553
12.15.2STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h . 3554
12.15.3REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h......
3555
12.15.4CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ........................................................................................... 3556
12.15.5BAR -Base Address Register (BAR)—Offset 10h....................................... 3556
12.15.6BAR -Base Address Register High (BAR_HIGH)—Offset 14h ...................... 3557
12.15.7BAR1 -Base Address Register1 (BAR1)—Offset 18h ................................. 3558
12.15.8BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ................. 3558
12.15.9 (BAR2)—Offset 20h............................................................................ 3559
12.15.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch .................................................................................................. 3559
12.15.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ....
3560
12.15.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h......... 3561
12.15.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch .......... 3561
12.15.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h...
3562
12.15.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h ............................................................ 3563

88 334818
 12.15.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset
90h ...................................................................................................3564
12.15.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h ......
3564
12.15.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................3565
12.15.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................3566
12.15.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................3566
12.16 Registers Summary ........................................................................................3569
12.16.1PWM Control Register (PWMCTRL_0)—Offset 0h ......................................3569
12.16.2PWM D0i3 Control Register (PWMD0i3C)—Offset 100h..............................3570
12.16.3PWM Control Register (PWMCTRL_1)—Offset 400h...................................3571
12.16.4PWM Control Register (PWMCTRL_2)—Offset 800h...................................3572
12.16.5PWM Control Register (PWMCTRL_3)—Offset C00h...................................3573
12.17 Registers Summary ........................................................................................3575
12.17.1DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3575
12.17.2STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..3576
12.17.3REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
3577
12.17.4CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ...........................................................................................3578
12.17.5BAR -Base Address Register (BAR)—Offset 10h .......................................3578
12.17.6BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................3579
12.17.7BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................3580
12.17.8BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................3580
12.17.9 (BAR2)—Offset 20h ............................................................................3581
12.17.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................3581
12.17.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h.....
3582
12.17.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h .........3583
12.17.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ...........3583
12.17.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h ...
3584
12.17.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................3585
12.17.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset
90h ...................................................................................................3586
12.17.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h ......
3586
12.17.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................3587
12.17.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................3588
12.17.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................3588
12.18 Registers Summary ........................................................................................3591
12.18.1DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3591
12.18.2STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..3592
12.18.3REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
3593

334818 89
 12.18.4CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ........................................................................................... 3594
12.18.5BAR -Base Address Register (BAR)—Offset 10h....................................... 3594
12.18.6BAR -Base Address Register High (BAR_HIGH)—Offset 14h ...................... 3595
12.18.7BAR1 -Base Address Register1 (BAR1)—Offset 18h ................................. 3596
12.18.8BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ................. 3596
12.18.9 (BAR2)—Offset 20h............................................................................ 3597
12.18.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch .................................................................................................. 3597
12.18.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ....
3598
12.18.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h......... 3599
12.18.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch .......... 3599
12.18.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h...
3600
12.18.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h ............................................................ 3601
12.18.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset
90h................................................................................................... 3602
12.18.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h .....
3602
12.18.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 3603
12.18.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 3604
12.18.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 3604
12.19 Registers Summary........................................................................................ 3607
12.19.1DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3607
12.19.2STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h . 3608
12.19.3REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h......
3609
12.19.4CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ........................................................................................... 3610
12.19.5BAR -Base Address Register (BAR)—Offset 10h....................................... 3610
12.19.6BAR -Base Address Register High (BAR_HIGH)—Offset 14h ...................... 3611
12.19.7BAR1 -Base Address Register1 (BAR1)—Offset 18h ................................. 3612
12.19.8BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ................. 3612
12.19.9 (BAR2)—Offset 20h............................................................................ 3613
12.19.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch .................................................................................................. 3613
12.19.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ....
3614
12.19.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h......... 3615
12.19.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch .......... 3615
12.19.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h...
3616
12.19.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h ............................................................ 3617
12.19.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset
90h................................................................................................... 3618
12.19.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h .....
3618
12.19.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 3619

90 334818
 12.19.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................3620
12.19.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................3620
12.20 Registers Summary ........................................................................................3623
12.20.1DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
3623
12.20.2STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..3624
12.20.3REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
3625
12.20.4CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ...........................................................................................3626
12.20.5BAR -Base Address Register (BAR)—Offset 10h .......................................3626
12.20.6BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................3627
12.20.7BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................3628
12.20.8BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................3628
12.20.9 (BAR2)—Offset 20h ............................................................................3629
12.20.10SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................3629
12.20.11EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h.....
3630
12.20.12CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h .........3631
12.20.13INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ...........3631
12.20.14POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h ...
3632
12.20.15PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................3633
12.20.16PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset
90h ...................................................................................................3634
12.20.17DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h ......
3634
12.20.18D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................3635
12.20.19DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................3636
12.20.20D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................3636
13 Power Management Controller (P-Unit) ................................................................3639
13.1 Registers Summary ........................................................................................3639
13.1.1 Device Enable Register (P_CR_DEVEN_0_0_0_PCI)—Offset 54h.................3639
13.1.2 Capability ID0 A (P_CR_CAPID0_A_0_0_0_PCI)—Offset E4h .....................3640
13.1.3 Capability ID0 B (P_CR_CAPID0_B_0_0_0_PCI)—Offset E8h .....................3642
13.2 Registers Summary ........................................................................................3643
13.2.1 Device ID and Vendor ID Register (P_CR_DEVICE_ID_VENDOR_ID_0_0_1_PCI)—
Offset 0h............................................................................................3644
13.2.2 PCI_STATUS_COMMAND_0_0_1_PCI
(P_CR_PCI_STATUS_COMMAND_0_0_1_PCI)—Offset 4h ..........................3644
13.2.3 PCI Revision ID and PCI Class Code Register
(P_CR_REVISION_ID_CLASS_CODE_0_0_1_PCI)—Offset 8h .....................3646
13.2.4 Master Latency Timer and Header Type Register
(P_CR_MASTER_LATENCY_TIME_0_0_1_PCI)—Offset Ch ..........................3647
13.2.5 Thermal Management Base Address Register (P_CR_TMBAR_LO_0_0_1_PCI)—
Offset 10h ..........................................................................................3648
13.2.6 Thermal Management Base Address Register (P_CR_TMBAR_HI_0_0_1_PCI)—
Offset 14h ..........................................................................................3649

334818 91
 13.2.7 PCI Subsystem Vendor ID and PCI Subsystem ID
(P_CR_SVID_SID_0_0_1_PCI)—Offset 2Ch ............................................ 3649
13.2.8 CAPPTR_0_0_1_PCI (P_CR_CAPPTR_0_0_1_PCI)—Offset 34h ................... 3650
13.2.9 Interrupt and Latency Configuration (P_CR_INTR_LAT_0_0_1_PCI)—Offset 3Ch.
3651
13.2.10Device Enable Register (P_CR_DEVEN_0_0_1_PCI)—Offset 54h ................ 3651
13.2.11SCISTS_0_0_1_PCI (P_CR_SCISTS_0_0_1_PCI)—Offset 88h ................... 3652
13.2.12SCI Command (P_CR_SCICMD_0_0_1_PCI)—Offset CCh.......................... 3653
13.2.13Power Management Capabilities (P_CR_PMCAPID_0_0_1_PCI)—Offset D0h 3654
13.2.14Power Management Control and Status (P_CR_PMCS_0_0_1_PCI)—Offset D4h ..
3655
13.2.15Interrupt Status (P_CR_INTSTS_0_0_1_PCI)—Offset DCh ........................ 3656
13.2.16Capability ID0 Capability Control (P_CR_CAPID0_CAPCTRL0_0_0_1_PCI)—Offset
E0h................................................................................................... 3657
13.2.17Capability ID0 A (P_CR_CAPID0_A_0_0_1_PCI)—Offset E4h..................... 3657
13.2.18Capability ID0 B (P_CR_CAPID0_B_0_0_1_PCI)—Offset E8h..................... 3659
13.3 Registers Summary........................................................................................ 3660
13.3.1 GT_SLICE_INFO (P_CR_GT_SLICE_INFO_0_2_0_GTTMMADR)—Offset 8064h ....
3662
13.3.2 GT Hardware P-state Control Request
(P_CR_GT_HWP_REQ_0_2_0_GTTMMADR)—Offset 8068h........................ 3663
13.3.3 GT_MEM_BOUND_COUNTER_0_2_0_GTTMMADR
(P_CR_GT_MEM_BOUND_COUNTER_0_2_0_GTTMMADR)—Offset 8070h .... 3664
13.3.4 GT_SQ_OCCUPANCY_0_2_0_GTTMMADR
(P_CR_GT_SQ_OCCUPANCY_0_2_0_GTTMMADR)—Offset 8074h............... 3664
13.3.5 GT_RW_DRAM_0_2_0_GTTMMADR (P_CR_GT_RW_DRAM_0_2_0_GTTMMADR)—
Offset 8078h ...................................................................................... 3665
13.3.6 GT_P_REQ (P_CR_GT_THREAD_P_REQ_0_2_0_GTTMMADR)—Offset 807Ch 3665
13.3.7 GT_ARAT_TTT (P_CR_GT_ARAT_TTT_0_2_0_GTTMMADR)—Offset 8080h ... 3666
13.3.8 GTC6_PREWAKE_TIMER_0_2_0_GTTMMADR
(P_CR_GTC6_PREWAKE_TIMER_0_2_0_GTTMMADR)—Offset 8088h .......... 3667
13.3.9 GT_DISP_PWRON_0_2_0_GTTMMADR
(P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR)—Offset 8090h................... 3668
13.3.10GT_GFX_RC6_0_2_0_GTTMMADR (P_CR_GT_GFX_RC6_0_2_0_GTTMMADR)—
Offset 8108h ...................................................................................... 3668
13.3.11GTDRIVER_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_INTERFACE_0_2_0_GTTMMADR)—Offset 8124h ....
3669
13.3.12GTDRIVER_MAILBOX_DATA_LOW_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_DATA_LOW_0_2_0_GTTMMADR)—Offset 8128h....
3670
13.3.13GTDRIVER_MAILBOX_DATA_HIGH_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_DATA_HIGH_0_2_0_GTTMMADR)—Offset 812Ch...
3670
13.3.14P24C_PCODE_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_P24C_PCODE_MAILBOX_INTERFACE_0_2_0_GTTMMADR)—Offset 8130h
3671
13.3.15P24C_PCODE_MAILBOX_DATA_0_2_0_GTTMMADR
(P_CR_P24C_PCODE_MAILBOX_DATA_0_2_0_GTTMMADR)—Offset 8134h . 3672
13.3.16PCODE_P24C_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_PCODE_P24C_MAILBOX_INTERFACE_0_2_0_GTTMMADR)—Offset 8138h
3672
13.3.17PCODE_P24C_MAILBOX_DATA_0_2_0_GTTMMADR
(P_CR_PCODE_P24C_MAILBOX_DATA_0_2_0_GTTMMADR)—Offset 813Ch . 3673
13.3.18GT_PM_CONFIG_0_2_0_GTTMMADR
(P_CR_GT_PM_CONFIG_0_2_0_GTTMMADR)—Offset 8140h ..................... 3674

92 334818
 13.3.19Graphics Interrupt Response Latency Tolerance
(P_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_0_2_0_GTTMMADR)—Offset
8150h................................................................................................3674
13.3.20GTDRIVER_P2G_EVENTS_0_2_0_GTTMMADR
(P_CR_GTDRIVER_P2G_EVENTS_0_2_0_GTTMMADR)—Offset 8160h .........3675
13.3.21GTDRIVER_G2P_EVENTS_0_2_0_GTTMMADR
(P_CR_GTDRIVER_G2P_EVENTS_0_2_0_GTTMMADR)—Offset 8164h .........3676
13.3.22CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_CORE_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—Offset 816Ch ...
3677
13.3.23GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_GRAPHICS_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—Offset
8170h................................................................................................3678
13.3.24SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—
Offset 8174h ......................................................................................3679
13.3.25Memory Frequency Status
(P_CR_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—Offset
8178h................................................................................................3680
13.3.26GT_PERF_LIMIT_REASONS
(P_CR_GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR)—Offset 8184h.......3681
13.3.27GTDRIVER_HWP_REQUEST_0_2_0_GTTMMADR
(P_CR_GTDRIVER_HWP_REQUEST_0_2_0_GTTMMADR)—Offset 8190h ......3683
13.3.28ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR
(P_CR_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_2_0_GTTMMADR)—
Offset 8198h ......................................................................................3684
13.3.29GT_VIDEO_BUSYNESS_0_2_0_GTTMMADR
(P_CR_GT_VIDEO_BUSYNESS_0_2_0_GTTMMADR)—Offset 819Ch ............3685
13.4 Registers Summary ........................................................................................3686
13.4.1 ISPDRIVER_MAILBOX_INTERFACE_0_0_0_MCHBAR
(P_CR_ISPDRIVER_MAILBOX_INTERFACE_0_0_0_MCHBAR)—Offset 7480h.3687
13.4.2 ISPDRIVER_MAILBOX_DATA_LOW_0_0_0_MCHBAR
(P_CR_ISPDRIVER_MAILBOX_DATA_LOW_0_0_0_MCHBAR)—Offset 7484h.3688
13.4.3 ISPDRIVER_MAILBOX_DATA_HIGH_0_0_0_MCHBAR
(P_CR_ISPDRIVER_MAILBOX_DATA_HIGH_0_0_0_MCHBAR)—Offset 7488h3688
13.4.4 ISPDRIVER_P2I_EVENTS_0_0_0_MCHBAR
(P_CR_ISPDRIVER_P2I_EVENTS_0_0_0_MCHBAR)—Offset 748Ch .............3689
13.4.5 ISPDRIVER_I2P_EVENTS_0_0_0_MCHBAR
(P_CR_ISPDRIVER_I2P_EVENTS_0_0_0_MCHBAR)—Offset 7490h..............3690
13.4.6 ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBA
R)—Offset 7498h ................................................................................3691
13.4.7 ISPDRIVER_HWP_REQUEST_0_0_0_MCHBAR
(P_CR_ISPDRIVER_HWP_REQUEST_0_0_0_MCHBAR)—Offset 74A0h .........3692
13.4.8 ISPDRIVER_SPARE_RW_0_0_0_MCHBAR
(P_CR_ISPDRIVER_SPARE_RW_0_0_0_MCHBAR)—Offset 74A8h ...............3693
13.4.9 ISPDRIVER_SPARE_RO_0_0_0_MCHBAR
(P_CR_ISPDRIVER_SPARE_RO_0_0_0_MCHBAR)—Offset 74ACh................3693
13.4.10CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset
74B0h ...............................................................................................3694
13.4.11GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—
Offset 74B4h ......................................................................................3695
13.4.12SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHB
AR)—Offset 74B8h ..............................................................................3695

334818 93
 13.4.13Memory Frequency Status
(P_CR_ISPDRIVER_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
)—Offset 74BCh.................................................................................. 3696
13.4.14ISP_PERF_LIMIT_REASONS
(P_CR_ISPDRIVER_ISP_PERF_LIMIT_REASONS_0_0_0_MCHBAR)—Offset 74CCh
3697
13.4.15I-unit Processing System C0 Residency Counter
(P_CR_ISPDRIVER_TELEM_IUNIT_C0_RESIDENCY_0_0_0_MCHBAR)—Offset
74D0h............................................................................................... 3700
13.4.16I-unit Processing System C0 Residency Counter
(P_CR_ISPDRIVER_TELEM_IUNIT_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—
Offset 74D4h ..................................................................................... 3700
13.5 Registers Summary........................................................................................ 3703
13.5.1 Device Enable Register (P_CR_DEVEN_0_0_0_PCI)—Offset 54h ................ 3703
13.5.2 Capability ID0 A (P_CR_CAPID0_A_0_0_0_PCI)—Offset E4h..................... 3704
13.5.3 Capability ID0 B (P_CR_CAPID0_B_0_0_0_PCI)—Offset E8h..................... 3706
13.6 Registers Summary........................................................................................ 3707
13.6.1 Device ID and Vendor ID Register (P_CR_DEVICE_ID_VENDOR_ID_0_0_1_PCI)—
Offset 0h ........................................................................................... 3707
13.6.2 PCI_STATUS_COMMAND_0_0_1_PCI
(P_CR_PCI_STATUS_COMMAND_0_0_1_PCI)—Offset 4h .......................... 3708
13.6.3 PCI Revision ID and PCI Class Code Register
(P_CR_REVISION_ID_CLASS_CODE_0_0_1_PCI)—Offset 8h .................... 3710
13.6.4 Master Latency Timer and Header Type Register
(P_CR_MASTER_LATENCY_TIME_0_0_1_PCI)—Offset Ch ......................... 3711
13.6.5 Thermal Management Base Address Register (P_CR_TMBAR_LO_0_0_1_PCI)—
Offset 10h ......................................................................................... 3712
13.6.6 Thermal Management Base Address Register (P_CR_TMBAR_HI_0_0_1_PCI)—
Offset 14h ......................................................................................... 3712
13.6.7 PCI Subsystem Vendor ID and PCI Subsystem ID
(P_CR_SVID_SID_0_0_1_PCI)—Offset 2Ch ............................................ 3713
13.6.8 CAPPTR_0_0_1_PCI (P_CR_CAPPTR_0_0_1_PCI)—Offset 34h ................... 3714
13.6.9 Interrupt and Latency Configuration (P_CR_INTR_LAT_0_0_1_PCI)—Offset 3Ch.
3714
13.6.10Device Enable Register (P_CR_DEVEN_0_0_1_PCI)—Offset 54h ................ 3715
13.6.11SCISTS_0_0_1_PCI (P_CR_SCISTS_0_0_1_PCI)—Offset 88h ................... 3716
13.6.12SCI Command (P_CR_SCICMD_0_0_1_PCI)—Offset CCh.......................... 3717
13.6.13Power Management Capabilities (P_CR_PMCAPID_0_0_1_PCI)—Offset D0h 3717
13.6.14Power Management Control and Status (P_CR_PMCS_0_0_1_PCI)—Offset D4h ..
3718
13.6.15Interrupt Status (P_CR_INTSTS_0_0_1_PCI)—Offset DCh ........................ 3720
13.6.16Capability ID0 Capability Control (P_CR_CAPID0_CAPCTRL0_0_0_1_PCI)—Offset
E0h................................................................................................... 3721
13.6.17Capability ID0 A (P_CR_CAPID0_A_0_0_1_PCI)—Offset E4h..................... 3721
13.6.18Capability ID0 B (P_CR_CAPID0_B_0_0_1_PCI)—Offset E8h..................... 3723
13.7 Registers Summary........................................................................................ 3725
13.7.1 GT_SLICE_INFO (P_CR_GT_SLICE_INFO_0_2_0_GTTMMADR)—Offset 8064h ....
3726
13.7.2 GT Hardware P-state Control Request
(P_CR_GT_HWP_REQ_0_2_0_GTTMMADR)—Offset 8068h........................ 3727
13.7.3 GT_MEM_BOUND_COUNTER_0_2_0_GTTMMADR
(P_CR_GT_MEM_BOUND_COUNTER_0_2_0_GTTMMADR)—Offset 8070h .... 3728
13.7.4 GT_SQ_OCCUPANCY_0_2_0_GTTMMADR
(P_CR_GT_SQ_OCCUPANCY_0_2_0_GTTMMADR)—Offset 8074h............... 3728
13.7.5 GT_RW_DRAM_0_2_0_GTTMMADR (P_CR_GT_RW_DRAM_0_2_0_GTTMMADR)—
Offset 8078h ...................................................................................... 3729
13.7.6 GT_P_REQ (P_CR_GT_THREAD_P_REQ_0_2_0_GTTMMADR)—Offset 807Ch 3729

94 334818
 13.7.7 GT_ARAT_TTT (P_CR_GT_ARAT_TTT_0_2_0_GTTMMADR)—Offset 8080h ...3730
13.7.8 GTC6_PREWAKE_TIMER_0_2_0_GTTMMADR
(P_CR_GTC6_PREWAKE_TIMER_0_2_0_GTTMMADR)—Offset 8088h...........3731
13.7.9 GT_DISP_PWRON_0_2_0_GTTMMADR
(P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR)—Offset 8090h ...................3732
13.7.10GT_GFX_RC6_0_2_0_GTTMMADR (P_CR_GT_GFX_RC6_0_2_0_GTTMMADR)—
Offset 8108h ......................................................................................3732
13.7.11GTDRIVER_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_INTERFACE_0_2_0_GTTMMADR)—Offset 8124h ....
3733
13.7.12GTDRIVER_MAILBOX_DATA_LOW_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_DATA_LOW_0_2_0_GTTMMADR)—Offset 8128h ....
3734
13.7.13GTDRIVER_MAILBOX_DATA_HIGH_0_2_0_GTTMMADR
(P_CR_GTDRIVER_MAILBOX_DATA_HIGH_0_2_0_GTTMMADR)—Offset 812Ch ...
3734
13.7.14P24C_PCODE_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_P24C_PCODE_MAILBOX_INTERFACE_0_2_0_GTTMMADR)—Offset 8130h
3735
13.7.15P24C_PCODE_MAILBOX_DATA_0_2_0_GTTMMADR
(P_CR_P24C_PCODE_MAILBOX_DATA_0_2_0_GTTMMADR)—Offset 8134h..3736
13.7.16PCODE_P24C_MAILBOX_INTERFACE_0_2_0_GTTMMADR
(P_CR_PCODE_P24C_MAILBOX_INTERFACE_0_2_0_GTTMMADR)—Offset 8138h
3736
13.7.17PCODE_P24C_MAILBOX_DATA_0_2_0_GTTMMADR
(P_CR_PCODE_P24C_MAILBOX_DATA_0_2_0_GTTMMADR)—Offset 813Ch .3737
13.7.18GT_PM_CONFIG_0_2_0_GTTMMADR
(P_CR_GT_PM_CONFIG_0_2_0_GTTMMADR)—Offset 8140h......................3738
13.7.19Graphics Interrupt Response Latency Tolerance
(P_CR_GRAPHICS_INTERRUPT_RESPONSE_TIME_0_2_0_GTTMMADR)—Offset
8150h................................................................................................3738
13.7.20GTDRIVER_P2G_EVENTS_0_2_0_GTTMMADR
(P_CR_GTDRIVER_P2G_EVENTS_0_2_0_GTTMMADR)—Offset 8160h .........3739
13.7.21GTDRIVER_G2P_EVENTS_0_2_0_GTTMMADR
(P_CR_GTDRIVER_G2P_EVENTS_0_2_0_GTTMMADR)—Offset 8164h .........3740
13.7.22CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_CORE_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—Offset 816Ch ...
3741
13.7.23GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_GRAPHICS_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—Offset
8170h................................................................................................3742
13.7.24SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—
Offset 8174h ......................................................................................3743
13.7.25Memory Frequency Status
(P_CR_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_2_0_GTTMMADR)—Offset
8178h................................................................................................3744
13.7.26GT_PERF_LIMIT_REASONS
(P_CR_GT_PERF_LIMIT_REASONS_0_2_0_GTTMMADR)—Offset 8184h.......3745
13.7.27GTDRIVER_HWP_REQUEST_0_2_0_GTTMMADR
(P_CR_GTDRIVER_HWP_REQUEST_0_2_0_GTTMMADR)—Offset 8190h ......3747
13.7.28ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR
(P_CR_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_2_0_GTTMMADR)—
Offset 8198h ......................................................................................3748
13.7.29GT_VIDEO_BUSYNESS_0_2_0_GTTMMADR
(P_CR_GT_VIDEO_BUSYNESS_0_2_0_GTTMMADR)—Offset 819Ch ............3749
13.8 Registers Summary ........................................................................................3751

334818 95
 13.8.1 ISPDRIVER_MAILBOX_INTERFACE_0_0_0_MCHBAR
(P_CR_ISPDRIVER_MAILBOX_INTERFACE_0_0_0_MCHBAR)—Offset 7480h 3752
13.8.2 ISPDRIVER_MAILBOX_DATA_LOW_0_0_0_MCHBAR
(P_CR_ISPDRIVER_MAILBOX_DATA_LOW_0_0_0_MCHBAR)—Offset 7484h 3752
13.8.3 ISPDRIVER_MAILBOX_DATA_HIGH_0_0_0_MCHBAR
(P_CR_ISPDRIVER_MAILBOX_DATA_HIGH_0_0_0_MCHBAR)—Offset 7488h3753
13.8.4 ISPDRIVER_P2I_EVENTS_0_0_0_MCHBAR
(P_CR_ISPDRIVER_P2I_EVENTS_0_0_0_MCHBAR)—Offset 748Ch ............. 3754
13.8.5 ISPDRIVER_I2P_EVENTS_0_0_0_MCHBAR
(P_CR_ISPDRIVER_I2P_EVENTS_0_0_0_MCHBAR)—Offset 7490h ............. 3755
13.8.6 ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBA
R)—Offset 7498h ................................................................................ 3755
13.8.7 ISPDRIVER_HWP_REQUEST_0_0_0_MCHBAR
(P_CR_ISPDRIVER_HWP_REQUEST_0_0_0_MCHBAR)—Offset 74A0h ......... 3757
13.8.8 ISPDRIVER_SPARE_RW_0_0_0_MCHBAR
(P_CR_ISPDRIVER_SPARE_RW_0_0_0_MCHBAR)—Offset 74A8h............... 3758
13.8.9 ISPDRIVER_SPARE_RO_0_0_0_MCHBAR
(P_CR_ISPDRIVER_SPARE_RO_0_0_0_MCHBAR)—Offset 74ACh ............... 3758
13.8.10CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—Offset
74B0h ............................................................................................... 3759
13.8.11GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)—
Offset 74B4h...................................................................................... 3760
13.8.12SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_ISPDRIVER_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHB
AR)—Offset 74B8h .............................................................................. 3760
13.8.13Memory Frequency Status
(P_CR_ISPDRIVER_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
)—Offset 74BCh.................................................................................. 3761
13.8.14ISP_PERF_LIMIT_REASONS
(P_CR_ISPDRIVER_ISP_PERF_LIMIT_REASONS_0_0_0_MCHBAR)—Offset 74CCh
3762
13.8.15I-unit Processing System C0 Residency Counter
(P_CR_ISPDRIVER_TELEM_IUNIT_C0_RESIDENCY_0_0_0_MCHBAR)—Offset
74D0h............................................................................................... 3765
13.8.16I-unit Processing System C0 Residency Counter
(P_CR_ISPDRIVER_TELEM_IUNIT_FREQ_ACCUMULATOR_0_0_0_MCHBAR)—
Offset 74D4h ..................................................................................... 3765
14 ITSS..................................................................................................................... 3767
14.1 Registers Summary........................................................................................ 3767
14.1.1 Version (VS)—Offset 1h ....................................................................... 3770
14.1.2 Redirection Table Entry 0 (RTE0)—Offset 10h ......................................... 3771
14.1.3 Redirection Table Entry 1 (RTE1)—Offset 12h ......................................... 3772
14.1.4 Redirection Table Entry 2 (RTE2)—Offset 14h ......................................... 3773
14.1.5 Redirection Table Entry 3 (RTE3)—Offset 16h ......................................... 3775
14.1.6 Redirection Table Entry 4 (RTE4)—Offset 18h ......................................... 3776
14.1.7 Redirection Table Entry 5 (RTE5)—Offset 1Ah ......................................... 3777
14.1.8 Redirection Table Entry 6 (RTE6)—Offset 1Ch ......................................... 3778
14.1.9 Redirection Table Entry 7 (RTE7)—Offset 1Eh ......................................... 3779
14.1.10Redirection Table Entry 8 (RTE8)—Offset 20h ......................................... 3780
14.1.11Redirection Table Entry 9 (RTE9)—Offset 22h ......................................... 3782
14.1.12Redirection Table Entry 10 (RTE10)—Offset 24h...................................... 3783
14.1.13Redirection Table Entry 11 (RTE11)—Offset 26h...................................... 3784
14.1.14Redirection Table Entry 12 (RTE12)—Offset 28h...................................... 3785

96 334818
 14.1.15Redirection Table Entry 13 (RTE13)—Offset 2Ah ......................................3786
14.1.16Redirection Table Entry 14 (RTE14)—Offset 2Ch ......................................3787
14.1.17Redirection Table Entry 15 (RTE15)—Offset 2Eh ......................................3789
14.1.18Redirection Table Entry 16 (RTE16)—Offset 30h ......................................3790
14.1.19Redirection Table Entry 17 (RTE17)—Offset 32h ......................................3791
14.1.20Redirection Table Entry 18 (RTE18)—Offset 34h ......................................3792
14.1.21Redirection Table Entry 19 (RTE19)—Offset 36h ......................................3793
14.1.22Redirection Table Entry 20 (RTE20)—Offset 38h ......................................3794
14.1.23Redirection Table Entry 21 (RTE21)—Offset 3Ah ......................................3796
14.1.24Redirection Table Entry 22 (RTE22)—Offset 3Ch ......................................3797
14.1.25Redirection Table Entry 23 (RTE23)—Offset 3Eh ......................................3798
14.1.26Redirection Table Entry 24 (RTE24)—Offset 40h ......................................3799
14.1.27Redirection Table Entry 25 (RTE25)—Offset 42h ......................................3800
14.1.28Redirection Table Entry 26 (RTE26)—Offset 44h ......................................3801
14.1.29Redirection Table Entry 27 (RTE27)—Offset 46h ......................................3803
14.1.30Redirection Table Entry 28 (RTE28)—Offset 48h ......................................3804
14.1.31Redirection Table Entry 29 (RTE29)—Offset 4Ah ......................................3805
14.1.32Redirection Table Entry 30 (RTE30)—Offset 4Ch ......................................3806
14.1.33Redirection Table Entry 31 (RTE31)—Offset 4Eh ......................................3807
14.1.34Redirection Table Entry 32 (RTE32)—Offset 50h ......................................3808
14.1.35Redirection Table Entry 33 (RTE33)—Offset 52h ......................................3810
14.1.36Redirection Table Entry 34 (RTE34)—Offset 54h ......................................3811
14.1.37Redirection Table Entry 35 (RTE35)—Offset 56h ......................................3812
14.1.38Redirection Table Entry 36 (RTE36)—Offset 58h ......................................3813
14.1.39Redirection Table Entry 37 (RTE37)—Offset 5Ah ......................................3814
14.1.40Redirection Table Entry 38 (RTE38)—Offset 5Ch ......................................3815
14.1.41Redirection Table Entry 39 (RTE39)—Offset 5Eh ......................................3817
14.1.42Redirection Table Entry 40 (RTE40)—Offset 60h ......................................3818
14.1.43Redirection Table Entry 41 (RTE41)—Offset 62h ......................................3819
14.1.44Redirection Table Entry 42 (RTE42)—Offset 64h ......................................3820
14.1.45Redirection Table Entry 43 (RTE43)—Offset 66h ......................................3821
14.1.46Redirection Table Entry 44 (RTE44)—Offset 68h ......................................3822
14.1.47Redirection Table Entry 45 (RTE45)—Offset 6Ah ......................................3824
14.1.48Redirection Table Entry 46 (RTE46)—Offset 6Ch ......................................3825
14.1.49Redirection Table Entry 47 (RTE47)—Offset 6Eh ......................................3826
14.1.50Redirection Table Entry 48 (RTE48)—Offset 70h ......................................3827
14.1.51Redirection Table Entry 49 (RTE49)—Offset 72h ......................................3828
14.1.52Redirection Table Entry 50 (RTE50)—Offset 74h ......................................3829
14.1.53Redirection Table Entry 51 (RTE51)—Offset 76h ......................................3831
14.1.54Redirection Table Entry 52 (RTE52)—Offset 78h ......................................3832
14.1.55Redirection Table Entry 53 (RTE53)—Offset 7Ah ......................................3833
14.1.56Redirection Table Entry 54 (RTE54)—Offset 7Ch ......................................3834
14.1.57Redirection Table Entry 55 (RTE55)—Offset 7Eh ......................................3835
14.1.58Redirection Table Entry 56 (RTE56)—Offset 80h ......................................3836
14.1.59Redirection Table Entry 57 (RTE57)—Offset 82h ......................................3838
14.1.60Redirection Table Entry 58 (RTE58)—Offset 84h ......................................3839
14.1.61Redirection Table Entry 59 (RTE59)—Offset 86h ......................................3840
14.1.62Redirection Table Entry 60 (RTE60)—Offset 88h ......................................3841
14.1.63Redirection Table Entry 61 (RTE61)—Offset 8Ah ......................................3842
14.1.64Redirection Table Entry 62 (RTE62)—Offset 8Ch ......................................3843
14.1.65Redirection Table Entry 63 (RTE63)—Offset 8Eh ......................................3845
14.1.66Redirection Table Entry 64 (RTE64)—Offset 90h ......................................3846
14.1.67Redirection Table Entry 65 (RTE65)—Offset 92h ......................................3847
14.1.68Redirection Table Entry 66 (RTE66)—Offset 94h ......................................3848
14.1.69Redirection Table Entry 67 (RTE67)—Offset 96h ......................................3849

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 14.1.70Redirection Table Entry 68 (RTE68)—Offset 98h...................................... 3850
14.1.71Redirection Table Entry 69 (RTE69)—Offset 9Ah ..................................... 3852
14.1.72Redirection Table Entry 70 (RTE70)—Offset 9Ch ..................................... 3853
14.1.73Redirection Table Entry 71 (RTE71)—Offset 9Eh...................................... 3854
14.1.74Redirection Table Entry 72 (RTE72)—Offset A0h ..................................... 3855
14.1.75Redirection Table Entry 73 (RTE73)—Offset A2h ..................................... 3856
14.1.76Redirection Table Entry 74 (RTE74)—Offset A4h ..................................... 3857
14.1.77Redirection Table Entry 75 (RTE75)—Offset A6h ..................................... 3859
14.1.78Redirection Table Entry 76 (RTE76)—Offset A8h ..................................... 3860
14.1.79Redirection Table Entry 77 (RTE77)—Offset AAh ..................................... 3861
14.1.80Redirection Table Entry 78 (RTE78)—Offset ACh ..................................... 3862
14.1.81Redirection Table Entry 79 (RTE79)—Offset AEh ..................................... 3863
14.1.82Redirection Table Entry 80 (RTE80)—Offset B0h ..................................... 3864
14.1.83Redirection Table Entry 81 (RTE81)—Offset B2h ..................................... 3866
14.1.84Redirection Table Entry 82 (RTE82)—Offset B4h ..................................... 3867
14.1.85Redirection Table Entry 83 (RTE83)—Offset B6h ..................................... 3868
14.1.86Redirection Table Entry 84 (RTE84)—Offset B8h ..................................... 3869
14.1.87Redirection Table Entry 85 (RTE85)—Offset BAh ..................................... 3870
14.1.88Redirection Table Entry 86 (RTE86)—Offset BCh ..................................... 3871
14.1.89Redirection Table Entry 87 (RTE87)—Offset BEh ..................................... 3873
14.1.90Redirection Table Entry 88 (RTE88)—Offset C0h ..................................... 3874
14.1.91Redirection Table Entry 89 (RTE89)—Offset C2h ..................................... 3875
14.1.92Redirection Table Entry 90 (RTE90)—Offset C4h ..................................... 3876
14.1.93Redirection Table Entry 91 (RTE91)—Offset C6h ..................................... 3877
14.1.94Redirection Table Entry 92 (RTE92)—Offset C8h ..................................... 3878
14.1.95Redirection Table Entry 93 (RTE93)—Offset CAh ..................................... 3880
14.1.96Redirection Table Entry 94 (RTE94)—Offset CCh ..................................... 3881
14.1.97Redirection Table Entry 95 (RTE95)—Offset CEh ..................................... 3882
14.1.98Redirection Table Entry 96 (RTE96)—Offset D0h ..................................... 3883
14.1.99Redirection Table Entry 97 (RTE97)—Offset D2h ..................................... 3884
14.1.100Redirection Table Entry 98 (RTE98)—Offset D4h.................................... 3885
14.1.101Redirection Table Entry 99 (RTE99)—Offset D6h.................................... 3887
14.1.102Redirection Table Entry 100 (RTE100)—Offset D8h ................................ 3888
14.1.103Redirection Table Entry 101 (RTE101)—Offset DAh ................................ 3889
14.1.104Redirection Table Entry 102 (RTE102)—Offset DCh ................................ 3890
14.1.105Redirection Table Entry 103 (RTE103)—Offset DEh ................................ 3891
14.1.106Redirection Table Entry 104 (RTE104)—Offset E0h................................. 3892
14.1.107Redirection Table Entry 105 (RTE105)—Offset E2h................................. 3894
14.1.108Redirection Table Entry 106 (RTE106)—Offset E4h................................. 3895
14.1.109Redirection Table Entry 107 (RTE107)—Offset E6h................................. 3896
14.1.110Redirection Table Entry 108 (RTE108)—Offset E8h................................. 3897
14.1.111Redirection Table Entry 109 (RTE109)—Offset EAh ................................ 3898
14.1.112Redirection Table Entry 110 (RTE110)—Offset ECh ................................ 3899
14.1.113Redirection Table Entry 111 (RTE111)—Offset EEh................................. 3901
14.1.114Redirection Table Entry 112 (RTE112)—Offset F0h ................................. 3902
14.1.115Redirection Table Entry 113 (RTE113)—Offset F2h ................................. 3903
14.1.116Redirection Table Entry 114 (RTE114)—Offset F4h ................................. 3904
14.1.117Redirection Table Entry 115 (RTE115)—Offset F6h ................................. 3905
14.1.118Redirection Table Entry 116 (RTE116)—Offset F8h ................................. 3906
14.1.119Redirection Table Entry 117 (RTE117)—Offset FAh................................. 3908
14.1.120Redirection Table Entry 118 (RTE118)—Offset FCh................................. 3909
14.1.121Redirection Table Entry 119 (RTE119)—Offset FEh ................................. 3910
14.1.122PIRQA Routing Control (PARC)—Offset 3100h ....................................... 3911
14.1.123PIRQB Routing Control (PBRC)—Offset 3101h ....................................... 3912
14.1.124PIRQC Routing Control (PCRC)—Offset 3102h ....................................... 3912

98 334818
 14.1.125PIRQD Routing Control (PDRC)—Offset 3103h........................................3913
14.1.126PIRQE Routing Control (PERC)—Offset 3104h ........................................3914
14.1.127PIRQF Routing Control (PFRC)—Offset 3105h.........................................3914
14.1.128PIRQG Routing Control (PGRC)—Offset 3106h........................................3915
14.1.129PIRQH Routing Control (PHRC)—Offset 3107h........................................3916
14.1.130PCI Interrupt Route 0 (PIR0)—Offset 3140h ..........................................3916
14.1.131PCI Interrupt Route 1 (PIR1)—Offset 3142h ..........................................3917
14.1.132PCI Interrupt Route 2 (PIR2)—Offset 3144h ..........................................3918
14.1.133PCI Interrupt Route 3(PIR3)—Offset 3146h ...........................................3919
14.1.134PCI Interrupt Route 4 (PIR4)—Offset 3148h ..........................................3920
14.1.135PCI Interrupt Route 5 (PIR5)—Offset 314Ah ..........................................3921
14.1.136PCI Interrupt Route 6 (PIR6)—Offset 314Ch ..........................................3921
14.1.137PCI Interrupt Route 7 (PIR7)—Offset 314Eh ..........................................3922
14.1.138PCI Interrupt Route 8 (PIR8)—Offset 3150h ..........................................3923
14.1.139PCI Interrupt Route 9 (PIR9)—Offset 3152h ..........................................3924
14.1.140PCI Interrupt Route 10 (PIR10)—Offset 3154h .......................................3925
14.1.141PCI Interrupt Route 11 (PIR11)—Offset 3156h .......................................3926
14.1.142PCI Interrupt Route 12 (PIR12)—Offset 3158h .......................................3926
14.1.143Interrupt Polarity Control 0 (IPC0)—Offset 3200h...................................3927
14.1.144Interrupt Polarity Control 1 (IPC1)—Offset 3204h...................................3927
14.1.145Interrupt Polarity Control 2 (IPC2)—Offset 3208h...................................3928
14.1.146Interrupt Polarity Control 3 (IPC3)—Offset 320Ch...................................3928
14.1.147ITSS Power Reduction Control (ITSSPRC)—Offset 3300h .........................3929
14.1.148SIDE Clock Timing (SIDECT)—Offset 3304h...........................................3929
14.2 Registers Summary ........................................................................................3931
14.2.1 Index Register (IDX)—Offset FEC00000h ................................................3931
14.2.2 Window Register (WDW)—Offset FEC00010h...........................................3931
14.2.3 EOI Register (EOI)—Offset FEC00040h ...................................................3932
14.3 Registers Summary ........................................................................................3932
14.3.1 NMI Status and Control (NMI_STS_CNT)—Offset 61h ...............................3933
14.3.2 NMI Enable (and Real Time Clock Index) (NMI_EN)—Offset 70h ................3934
14.3.3 Init Register (PORT92)—Offset 92h........................................................3934
14.3.4 Reset Control Register (RST_CNT)—Offset CF9h ......................................3935
14.4 Registers Summary ........................................................................................3936
14.4.1 General Capabilities and ID Register (GEN_CAP_ID)—Offset FED00000h.....3937
14.4.2 General Config Register (GEN_CFG)—Offset FED00010h ...........................3938
14.4.3 Main Counter Value (MAIN_CNTR)—Offset FED000F0h .............................3939
14.4.4 Timer 0 Config and Capabilities (TMR0_CNF_CAP)—Offset FED00100h........3940
14.4.5 Timer 0 Comparator Value (TMR0_CMP_VAL)—Offset FED00108h ..............3943
14.4.6 Timer 0 FSB Interrupt Rout Register (TMR0_FSB_INT_ROUT)—Offset FED00110h
3944
14.4.7 Timer 1 Config and Capabilities (TMR1_CNF_CAP)—Offset FED00120h........3945
14.4.8 Timer 1 Comparator Value (TMR1_CMP_VAL)—Offset FED00128h ..............3948
14.4.9 Timer 1 FSB Interrupt Rout Register (TMR1_FSB_INT_ROUT)—Offset FED00130h
3949
14.4.10Timer 2 Config and Capabilities (TMR2_CNF_CAP)—Offset FED00140h........3950
14.4.11Timer 2 Comparator Value (TMR2_CMP_VAL)—Offset FED00148h ..............3953
14.4.12Timer 2 FSB Interrupt Rout Register (TMR2_FSB_INT_ROUT)—Offset FED00150h
3954
14.4.13Timer 3 Config and Capabilities (TMR3_CNF_CAP)—Offset FED00160h........3955
14.4.14Timer 3 Comparator Value (TMR3_CMP_VAL)—Offset FED00168h ..............3958
14.4.15Timer 3 FSB Interrupt Rout Register (TMR3_FSB_INT_ROUT)—Offset FED00170h
3959
14.4.16Timer 4 Config and Capabilities (TMR4_CNF_CAP)—Offset FED00180h........3960
14.4.17Timer 4 Comparator Value (TMR4_CMP_VAL)—Offset FED00188h ..............3963

334818 99
 14.4.18Timer 4 FSB Interrupt Rout Register (TMR4_FSB_INT_ROUT)—Offset FED00190h
3964
14.4.19Timer 5 Config and Capabilities (TMR5_CNF_CAP)—Offset FED001A0h ....... 3965
14.4.20Timer 5 Comparator Value (TMR5_CMP_VAL)—Offset FED001A8h ............. 3968
14.4.21Timer 5 FSB Interrupt Rout Register (TMR5_FSB_INT_ROUT)—Offset FED001B0h
3969
14.4.22Timer 6 Config and Capabilities (TMR6_CNF_CAP)—Offset FED001C0h ....... 3970
14.4.23Timer 6 Comparator Value (TMR6_CMP_VAL)—Offset FED001C8h ............. 3973
14.4.24Timer 6 FSB Interrupt Rout Register (TMR6_FSB_INT_ROUT)—Offset FED001D0h
3974
14.4.25Timer 7 Config and Capabilities (TMR7_CNF_CAP)—Offset FED001E0h ....... 3975
14.4.26Timer 7 Comparator Value (TMR7_CMP_VAL)—Offset FED001E8h.............. 3978
14.4.27Timer 7 FSB Interrupt Rout Register (TMR7_FSB_INT_ROUT)—Offset FED001F0h
3979
14.5 Registers Summary........................................................................................ 3980
14.5.1 Master Initialization Command Word 1 (MICW1)—Offset 20h .................... 3981
14.5.2 Master Operational Control Word 2 (MOCW2)—Offset 20h ........................ 3981
14.5.3 Master Operational Control Word 3 (MOCW3)—Offset 20h ........................ 3982
14.5.4 Master Initialization Command Word 2 (MICW2)—Offset 21h .................... 3983
14.5.5 Master Initialization Command Word 3 (MICW3)—Offset 21h .................... 3984
14.5.6 Master Initialization Command Word 4 (MICW4)—Offset 21h .................... 3985
14.5.7 Master Operational Control Word 1 (MOCW1)—Offset 21h ........................ 3985
14.5.8 Slave Operational Control Word 3 (SOCW3)—Offset A0h .......................... 3986
14.5.9 Slave Initialization Command Word 1 (SICW1)—Offset A0h ...................... 3987
14.5.10Slave Operational Control Word 2 (SOCW2)—Offset A0h .......................... 3988
14.5.11Slave Initialization Command Word 3 (SICW3)—Offset A1h ...................... 3989
14.5.12Slave Initialization Command Word 4 (SICW4)—Offset A1h ...................... 3989
14.5.13Slave Operational Control Word 1 (SOCW1)—Offset A1h .......................... 3990
14.5.14Slave Initialization Command Word 2 (SICW2)—Offset A1h ...................... 3991
14.5.15Master Edge/Level Control (ELCR1)—Offset 4D0h.................................... 3991
14.5.16Slave Edge/Level Control (ELCR2)—Offset 4D1h ..................................... 3992
14.6 Registers Summary........................................................................................ 3993
14.6.1 Counter 0 - Interval Timer Status Byte Format Register (C0_ITSBFR)—Offset 40h
3993
14.6.2 Counter 0 - Counter Access Ports Register (C0_CAPR)—Offset 40h ............ 3994
14.6.3 Counter 2 - Interval Timer Status Byte Format Register (C2_ITSBFR)—Offset 42h
3995
14.6.4 Counter 2 - Counter Access Ports Register (C2_CAPR)—Offset 42h ............ 3996
14.6.5 Timer Control Word Register (TCW)—Offset 43h ..................................... 3997
14.6.6 Read Back Command (RBC)—Offset 43h ................................................ 3998
14.6.7 Counter Latch Command (CLC)—Offset 43h ........................................... 3999
14.7 Registers Summary........................................................................................ 4001
14.7.1 Version (VS)—Offset 1h ....................................................................... 4004
14.7.2 Redirection Table Entry 0 (RTE0)—Offset 10h ......................................... 4005
14.7.3 Redirection Table Entry 1 (RTE1)—Offset 12h ......................................... 4006
14.7.4 Redirection Table Entry 2 (RTE2)—Offset 14h ......................................... 4007
14.7.5 Redirection Table Entry 3 (RTE3)—Offset 16h ......................................... 4008
14.7.6 Redirection Table Entry 4 (RTE4)—Offset 18h ......................................... 4010
14.7.7 Redirection Table Entry 5 (RTE5)—Offset 1Ah ......................................... 4011
14.7.8 Redirection Table Entry 6 (RTE6)—Offset 1Ch ......................................... 4012
14.7.9 Redirection Table Entry 7 (RTE7)—Offset 1Eh ......................................... 4013
14.7.10Redirection Table Entry 8 (RTE8)—Offset 20h ......................................... 4014
14.7.11Redirection Table Entry 9 (RTE9)—Offset 22h ......................................... 4016
14.7.12Redirection Table Entry 10 (RTE10)—Offset 24h...................................... 4017
14.7.13Redirection Table Entry 11 (RTE11)—Offset 26h...................................... 4018

100 334818
 14.7.14Redirection Table Entry 12 (RTE12)—Offset 28h ......................................4019
14.7.15Redirection Table Entry 13 (RTE13)—Offset 2Ah ......................................4020
14.7.16Redirection Table Entry 14 (RTE14)—Offset 2Ch ......................................4021
14.7.17Redirection Table Entry 15 (RTE15)—Offset 2Eh ......................................4023
14.7.18Redirection Table Entry 16 (RTE16)—Offset 30h ......................................4024
14.7.19Redirection Table Entry 17 (RTE17)—Offset 32h ......................................4025
14.7.20Redirection Table Entry 18 (RTE18)—Offset 34h ......................................4026
14.7.21Redirection Table Entry 19 (RTE19)—Offset 36h ......................................4027
14.7.22Redirection Table Entry 20 (RTE20)—Offset 38h ......................................4028
14.7.23Redirection Table Entry 21 (RTE21)—Offset 3Ah ......................................4030
14.7.24Redirection Table Entry 22 (RTE22)—Offset 3Ch ......................................4031
14.7.25Redirection Table Entry 23 (RTE23)—Offset 3Eh ......................................4032
14.7.26Redirection Table Entry 24 (RTE24)—Offset 40h ......................................4033
14.7.27Redirection Table Entry 25 (RTE25)—Offset 42h ......................................4034
14.7.28Redirection Table Entry 26 (RTE26)—Offset 44h ......................................4035
14.7.29Redirection Table Entry 27 (RTE27)—Offset 46h ......................................4037
14.7.30Redirection Table Entry 28 (RTE28)—Offset 48h ......................................4038
14.7.31Redirection Table Entry 29 (RTE29)—Offset 4Ah ......................................4039
14.7.32Redirection Table Entry 30 (RTE30)—Offset 4Ch ......................................4040
14.7.33Redirection Table Entry 31 (RTE31)—Offset 4Eh ......................................4041
14.7.34Redirection Table Entry 32 (RTE32)—Offset 50h ......................................4042
14.7.35Redirection Table Entry 33 (RTE33)—Offset 52h ......................................4044
14.7.36Redirection Table Entry 34 (RTE34)—Offset 54h ......................................4045
14.7.37Redirection Table Entry 35 (RTE35)—Offset 56h ......................................4046
14.7.38Redirection Table Entry 36 (RTE36)—Offset 58h ......................................4047
14.7.39Redirection Table Entry 37 (RTE37)—Offset 5Ah ......................................4048
14.7.40Redirection Table Entry 38 (RTE38)—Offset 5Ch ......................................4049
14.7.41Redirection Table Entry 39 (RTE39)—Offset 5Eh ......................................4051
14.7.42Redirection Table Entry 40 (RTE40)—Offset 60h ......................................4052
14.7.43Redirection Table Entry 41 (RTE41)—Offset 62h ......................................4053
14.7.44Redirection Table Entry 42 (RTE42)—Offset 64h ......................................4054
14.7.45Redirection Table Entry 43 (RTE43)—Offset 66h ......................................4055
14.7.46Redirection Table Entry 44 (RTE44)—Offset 68h ......................................4056
14.7.47Redirection Table Entry 45 (RTE45)—Offset 6Ah ......................................4058
14.7.48Redirection Table Entry 46 (RTE46)—Offset 6Ch ......................................4059
14.7.49Redirection Table Entry 47 (RTE47)—Offset 6Eh ......................................4060
14.7.50Redirection Table Entry 48 (RTE48)—Offset 70h ......................................4061
14.7.51Redirection Table Entry 49 (RTE49)—Offset 72h ......................................4062
14.7.52Redirection Table Entry 50 (RTE50)—Offset 74h ......................................4063
14.7.53Redirection Table Entry 51 (RTE51)—Offset 76h ......................................4065
14.7.54Redirection Table Entry 52 (RTE52)—Offset 78h ......................................4066
14.7.55Redirection Table Entry 53 (RTE53)—Offset 7Ah ......................................4067
14.7.56Redirection Table Entry 54 (RTE54)—Offset 7Ch ......................................4068
14.7.57Redirection Table Entry 55 (RTE55)—Offset 7Eh ......................................4069
14.7.58Redirection Table Entry 56 (RTE56)—Offset 80h ......................................4070
14.7.59Redirection Table Entry 57 (RTE57)—Offset 82h ......................................4072
14.7.60Redirection Table Entry 58 (RTE58)—Offset 84h ......................................4073
14.7.61Redirection Table Entry 59 (RTE59)—Offset 86h ......................................4074
14.7.62Redirection Table Entry 60 (RTE60)—Offset 88h ......................................4075
14.7.63Redirection Table Entry 61 (RTE61)—Offset 8Ah ......................................4076
14.7.64Redirection Table Entry 62 (RTE62)—Offset 8Ch ......................................4077
14.7.65Redirection Table Entry 63 (RTE63)—Offset 8Eh ......................................4079
14.7.66Redirection Table Entry 64 (RTE64)—Offset 90h ......................................4080
14.7.67Redirection Table Entry 65 (RTE65)—Offset 92h ......................................4081
14.7.68Redirection Table Entry 66 (RTE66)—Offset 94h ......................................4082

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 14.7.69Redirection Table Entry 67 (RTE67)—Offset 96h...................................... 4083
14.7.70Redirection Table Entry 68 (RTE68)—Offset 98h...................................... 4084
14.7.71Redirection Table Entry 69 (RTE69)—Offset 9Ah ..................................... 4086
14.7.72Redirection Table Entry 70 (RTE70)—Offset 9Ch ..................................... 4087
14.7.73Redirection Table Entry 71 (RTE71)—Offset 9Eh...................................... 4088
14.7.74Redirection Table Entry 72 (RTE72)—Offset A0h ..................................... 4089
14.7.75Redirection Table Entry 73 (RTE73)—Offset A2h ..................................... 4090
14.7.76Redirection Table Entry 74 (RTE74)—Offset A4h ..................................... 4091
14.7.77Redirection Table Entry 75 (RTE75)—Offset A6h ..................................... 4093
14.7.78Redirection Table Entry 76 (RTE76)—Offset A8h ..................................... 4094
14.7.79Redirection Table Entry 77 (RTE77)—Offset AAh ..................................... 4095
14.7.80Redirection Table Entry 78 (RTE78)—Offset ACh ..................................... 4096
14.7.81Redirection Table Entry 79 (RTE79)—Offset AEh ..................................... 4097
14.7.82Redirection Table Entry 80 (RTE80)—Offset B0h ..................................... 4098
14.7.83Redirection Table Entry 81 (RTE81)—Offset B2h ..................................... 4100
14.7.84Redirection Table Entry 82 (RTE82)—Offset B4h ..................................... 4101
14.7.85Redirection Table Entry 83 (RTE83)—Offset B6h ..................................... 4102
14.7.86Redirection Table Entry 84 (RTE84)—Offset B8h ..................................... 4103
14.7.87Redirection Table Entry 85 (RTE85)—Offset BAh ..................................... 4104
14.7.88Redirection Table Entry 86 (RTE86)—Offset BCh ..................................... 4105
14.7.89Redirection Table Entry 87 (RTE87)—Offset BEh ..................................... 4107
14.7.90Redirection Table Entry 88 (RTE88)—Offset C0h ..................................... 4108
14.7.91Redirection Table Entry 89 (RTE89)—Offset C2h ..................................... 4109
14.7.92Redirection Table Entry 90 (RTE90)—Offset C4h ..................................... 4110
14.7.93Redirection Table Entry 91 (RTE91)—Offset C6h ..................................... 4111
14.7.94Redirection Table Entry 92 (RTE92)—Offset C8h ..................................... 4112
14.7.95Redirection Table Entry 93 (RTE93)—Offset CAh ..................................... 4114
14.7.96Redirection Table Entry 94 (RTE94)—Offset CCh ..................................... 4115
14.7.97Redirection Table Entry 95 (RTE95)—Offset CEh ..................................... 4116
14.7.98Redirection Table Entry 96 (RTE96)—Offset D0h ..................................... 4117
14.7.99Redirection Table Entry 97 (RTE97)—Offset D2h ..................................... 4118
14.7.100Redirection Table Entry 98 (RTE98)—Offset D4h.................................... 4119
14.7.101Redirection Table Entry 99 (RTE99)—Offset D6h.................................... 4121
14.7.102Redirection Table Entry 100 (RTE100)—Offset D8h ................................ 4122
14.7.103Redirection Table Entry 101 (RTE101)—Offset DAh ................................ 4123
14.7.104Redirection Table Entry 102 (RTE102)—Offset DCh ................................ 4124
14.7.105Redirection Table Entry 103 (RTE103)—Offset DEh ................................ 4125
14.7.106Redirection Table Entry 104 (RTE104)—Offset E0h................................. 4126
14.7.107Redirection Table Entry 105 (RTE105)—Offset E2h................................. 4128
14.7.108Redirection Table Entry 106 (RTE106)—Offset E4h................................. 4129
14.7.109Redirection Table Entry 107 (RTE107)—Offset E6h................................. 4130
14.7.110Redirection Table Entry 108 (RTE108)—Offset E8h................................. 4131
14.7.111Redirection Table Entry 109 (RTE109)—Offset EAh ................................ 4132
14.7.112Redirection Table Entry 110 (RTE110)—Offset ECh ................................ 4133
14.7.113Redirection Table Entry 111 (RTE111)—Offset EEh................................. 4135
14.7.114Redirection Table Entry 112 (RTE112)—Offset F0h ................................. 4136
14.7.115Redirection Table Entry 113 (RTE113)—Offset F2h ................................. 4137
14.7.116Redirection Table Entry 114 (RTE114)—Offset F4h ................................. 4138
14.7.117Redirection Table Entry 115 (RTE115)—Offset F6h ................................. 4139
14.7.118Redirection Table Entry 116 (RTE116)—Offset F8h ................................. 4140
14.7.119Redirection Table Entry 117 (RTE117)—Offset FAh................................. 4142
14.7.120Redirection Table Entry 118 (RTE118)—Offset FCh................................. 4143
14.7.121Redirection Table Entry 119 (RTE119)—Offset FEh ................................. 4144
14.7.122PIRQA Routing Control (PARC)—Offset 3100h ....................................... 4145
14.7.123PIRQB Routing Control (PBRC)—Offset 3101h ....................................... 4146

102 334818
 14.7.124PIRQC Routing Control (PCRC)—Offset 3102h ........................................4146
14.7.125PIRQD Routing Control (PDRC)—Offset 3103h........................................4147
14.7.126PIRQE Routing Control (PERC)—Offset 3104h ........................................4148
14.7.127PIRQF Routing Control (PFRC)—Offset 3105h.........................................4148
14.7.128PIRQG Routing Control (PGRC)—Offset 3106h........................................4149
14.7.129PIRQH Routing Control (PHRC)—Offset 3107h........................................4150
14.7.130PCI Interrupt Route 0 (PIR0)—Offset 3140h ..........................................4150
14.7.131PCI Interrupt Route 1 (PIR1)—Offset 3142h ..........................................4151
14.7.132PCI Interrupt Route 2 (PIR2)—Offset 3144h ..........................................4152
14.7.133PCI Interrupt Route 3(PIR3)—Offset 3146h ...........................................4153
14.7.134PCI Interrupt Route 4 (PIR4)—Offset 3148h ..........................................4154
14.7.135PCI Interrupt Route 5 (PIR5)—Offset 314Ah ..........................................4155
14.7.136PCI Interrupt Route 6 (PIR6)—Offset 314Ch ..........................................4155
14.7.137PCI Interrupt Route 7 (PIR7)—Offset 314Eh ..........................................4156
14.7.138PCI Interrupt Route 8 (PIR8)—Offset 3150h ..........................................4157
14.7.139PCI Interrupt Route 9 (PIR9)—Offset 3152h ..........................................4158
14.7.140PCI Interrupt Route 10 (PIR10)—Offset 3154h .......................................4159
14.7.141PCI Interrupt Route 11 (PIR11)—Offset 3156h .......................................4160
14.7.142PCI Interrupt Route 12 (PIR12)—Offset 3158h .......................................4160
14.7.143Interrupt Polarity Control 0 (IPC0)—Offset 3200h...................................4161
14.7.144Interrupt Polarity Control 1 (IPC1)—Offset 3204h...................................4161
14.7.145Interrupt Polarity Control 2 (IPC2)—Offset 3208h...................................4162
14.7.146Interrupt Polarity Control 3 (IPC3)—Offset 320Ch...................................4162
14.7.147ITSS Power Reduction Control (ITSSPRC)—Offset 3300h .........................4163
14.7.148SIDE Clock Timing (SIDECT)—Offset 3304h...........................................4163
14.8 Registers Summary ........................................................................................4165
14.8.1 Index Register (IDX)—Offset FEC00000h ................................................4165
14.8.2 Window Register (WDW)—Offset FEC00010h...........................................4165
14.8.3 EOI Register (EOI)—Offset FEC00040h ...................................................4166
14.9 Registers Summary ........................................................................................4167
14.9.1 NMI Status and Control (NMI_STS_CNT)—Offset 61h ...............................4167
14.9.2 NMI Enable (and Real Time Clock Index) (NMI_EN)—Offset 70h ................4168
14.9.3 Init Register (PORT92)—Offset 92h........................................................4169
14.9.4 Reset Control Register (RST_CNT)—Offset CF9h ......................................4169
14.10 Registers Summary ........................................................................................4171
14.10.1General Capabilities and ID Register (GEN_CAP_ID)—Offset FED00000h.....4172
14.10.2General Config Register (GEN_CFG)—Offset FED00010h ...........................4173
14.10.3Main Counter Value (MAIN_CNTR)—Offset FED000F0h .............................4174
14.10.4Timer 0 Config and Capabilities (TMR0_CNF_CAP)—Offset FED00100h........4174
14.10.5Timer 0 Comparator Value (TMR0_CMP_VAL)—Offset FED00108h ..............4177
14.10.6Timer 0 FSB Interrupt Rout Register (TMR0_FSB_INT_ROUT)—Offset FED00110h
4178
14.10.7Timer 1 Config and Capabilities (TMR1_CNF_CAP)—Offset FED00120h........4179
14.10.8Timer 1 Comparator Value (TMR1_CMP_VAL)—Offset FED00128h ..............4182
14.10.9Timer 1 FSB Interrupt Rout Register (TMR1_FSB_INT_ROUT)—Offset FED00130h
4183
14.10.10Timer 2 Config and Capabilities (TMR2_CNF_CAP)—Offset FED00140h ......4184
14.10.11Timer 2 Comparator Value (TMR2_CMP_VAL)—Offset FED00148h.............4187
14.10.12Timer 2 FSB Interrupt Rout Register (TMR2_FSB_INT_ROUT)—Offset
FED00150h ........................................................................................4188
14.10.13Timer 3 Config and Capabilities (TMR3_CNF_CAP)—Offset FED00160h ......4189
14.10.14Timer 3 Comparator Value (TMR3_CMP_VAL)—Offset FED00168h.............4192
14.10.15Timer 3 FSB Interrupt Rout Register (TMR3_FSB_INT_ROUT)—Offset
FED00170h ........................................................................................4193
14.10.16Timer 4 Config and Capabilities (TMR4_CNF_CAP)—Offset FED00180h ......4194

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 14.10.17Timer 4 Comparator Value (TMR4_CMP_VAL)—Offset FED00188h ............ 4197
14.10.18Timer 4 FSB Interrupt Rout Register (TMR4_FSB_INT_ROUT)—Offset
FED00190h ........................................................................................ 4198
14.10.19Timer 5 Config and Capabilities (TMR5_CNF_CAP)—Offset FED001A0h ..... 4199
14.10.20Timer 5 Comparator Value (TMR5_CMP_VAL)—Offset FED001A8h ............ 4202
14.10.21Timer 5 FSB Interrupt Rout Register (TMR5_FSB_INT_ROUT)—Offset
FED001B0h........................................................................................ 4203
14.10.22Timer 6 Config and Capabilities (TMR6_CNF_CAP)—Offset FED001C0h ..... 4204
14.10.23Timer 6 Comparator Value (TMR6_CMP_VAL)—Offset FED001C8h ............ 4207
14.10.24Timer 6 FSB Interrupt Rout Register (TMR6_FSB_INT_ROUT)—Offset
FED001D0h ....................................................................................... 4208
14.10.25Timer 7 Config and Capabilities (TMR7_CNF_CAP)—Offset FED001E0h...... 4209
14.10.26Timer 7 Comparator Value (TMR7_CMP_VAL)—Offset FED001E8h ............ 4212
14.10.27Timer 7 FSB Interrupt Rout Register (TMR7_FSB_INT_ROUT)—Offset
FED001F0h ........................................................................................ 4213
14.11 Registers Summary........................................................................................ 4215
14.11.1Master Initialization Command Word 1 (MICW1)—Offset 20h .................... 4215
14.11.2Master Operational Control Word 2 (MOCW2)—Offset 20h ........................ 4216
14.11.3Master Operational Control Word 3 (MOCW3)—Offset 20h ........................ 4217
14.11.4Master Initialization Command Word 2 (MICW2)—Offset 21h .................... 4218
14.11.5Master Initialization Command Word 3 (MICW3)—Offset 21h .................... 4219
14.11.6Master Initialization Command Word 4 (MICW4)—Offset 21h .................... 4220
14.11.7Master Operational Control Word 1 (MOCW1)—Offset 21h ........................ 4220
14.11.8Slave Operational Control Word 3 (SOCW3)—Offset A0h .......................... 4221
14.11.9Slave Initialization Command Word 1 (SICW1)—Offset A0h ...................... 4222
14.11.10Slave Operational Control Word 2 (SOCW2)—Offset A0h......................... 4223
14.11.11Slave Initialization Command Word 3 (SICW3)—Offset A1h..................... 4224
14.11.12Slave Initialization Command Word 4 (SICW4)—Offset A1h..................... 4224
14.11.13Slave Operational Control Word 1 (SOCW1)—Offset A1h......................... 4225
14.11.14Slave Initialization Command Word 2 (SICW2)—Offset A1h..................... 4226
14.11.15Master Edge/Level Control (ELCR1)—Offset 4D0h .................................. 4226
14.11.16Slave Edge/Level Control (ELCR2)—Offset 4D1h .................................... 4227
14.12 Registers Summary........................................................................................ 4229
14.12.1Counter 0 - Interval Timer Status Byte Format Register (C0_ITSBFR)—Offset 40h
4229
14.12.2Counter 0 - Counter Access Ports Register (C0_CAPR)—Offset 40h ............ 4230
14.12.3Counter 2 - Interval Timer Status Byte Format Register (C2_ITSBFR)—Offset 42h
4231
14.12.4Counter 2 - Counter Access Ports Register (C2_CAPR)—Offset 42h ............ 4232
14.12.5Timer Control Word Register (TCW)—Offset 43h ..................................... 4233
14.12.6Read Back Command (RBC)—Offset 43h ................................................ 4234
14.12.7Counter Latch Command (CLC)—Offset 43h ........................................... 4235
15 IOSF2OCP ............................................................................................................ 4237
15.1 Registers Summary........................................................................................ 4237
15.1.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
4237
15.1.2 STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h . 4238
15.1.3 REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h......
4239
15.1.4 CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ........................................................................................... 4240
15.1.5 BAR -Base Address Register (BAR)—Offset 10h....................................... 4240
15.1.6 BAR -Base Address Register High (BAR_HIGH)—Offset 14h ...................... 4241
15.1.7 BAR1 -Base Address Register1 (BAR1)—Offset 18h ................................. 4242
15.1.8 BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ................. 4242

104 334818
 15.1.9 SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................4243
15.1.10EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ......
4244
15.1.11CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h...........4244
15.1.12INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ............4245
15.1.13POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h.....
4245
15.1.14PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................4246
15.1.15PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset 90h
4247
15.1.16DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h 4248
15.1.17D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................4248
15.1.18DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................4249
15.1.19D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................4250
15.2 Registers Summary ........................................................................................4253
15.2.1 DEVICEVENDORID - Device ID and Vendor ID Register (DEVVENDID)—Offset 0h
4253
15.2.2 STATUSCOMMAND- Status and Command (STATUSCOMMAND)—Offset 4h..4254
15.2.3 REVCLASSCODE - Revision ID and Class Code (REVCLASSCODE)—Offset 8h ......
4255
15.2.4 CLLATHEADERBIST - Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch ...........................................................................................4256
15.2.5 BAR -Base Address Register (BAR)—Offset 10h .......................................4256
15.2.6 BAR -Base Address Register High (BAR_HIGH)—Offset 14h .......................4257
15.2.7 BAR1 -Base Address Register1 (BAR1)—Offset 18h ..................................4258
15.2.8 BAR1 -Base Address Register1 High (BAR1_HIGH)—Offset 1Ch .................4258
15.2.9 SUBSYSTEMID -Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset
2Ch ...................................................................................................4259
15.2.10EXPANSION ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h ......
4260
15.2.11CAPABILITYPTR - Capabilities Pointer (CAPABILITYPTR)—Offset 34h...........4260
15.2.12INTERRUPTREG - Interrupt Register (INTERRUPTREG)—Offset 3Ch ............4261
15.2.13POWERCAPID - PowerManagement Capability ID (POWERCAPID)—Offset 80h.....
4261
15.2.14PMECTRLSTATUS_type Power Management Control and status register
(PMECTRLSTATUS)—Offset 84h .............................................................4262
15.2.15PCI DEVICE IDLE CAPABILITY RECORD (PCIDEVIDLE_CAP_RECORD)—Offset 90h
4263
15.2.16DEVID VENDOR SPECIFIC REG (DEVID_VEND_SPECIFIC_REG)—Offset 94h 4264
15.2.17D0I3_CONTROL_SW_LTR_MMIO_REG - SW LTR Update MMIO Location Register
(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................4264
15.2.18DEVICE_IDLE_POINTER_REG - Device IDLE pointer register
(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................4265
15.2.19D0I3_MAX_POW_LAT_PG_CONFIG - DEVICE PG CONFIG
(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................4266
16 PCIeRegisters Summary .......................................................................................4269
16.0.1 Device Command; Primary Status (CMD_PSPCLKD_L1TREF_CFG—Offset
1010hTS)—Offset 4h ...........................................................................4272
16.0.2 Revision ID;Class Code (RID_CC)—Offset 8h...........................................4274
16.0.3 Cache Line Size; Primary Latency Timer; Header Type (CLS_PLT_HTYPE)—Offset
Ch.....................................................................................................4275

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 16.0.4 Bus Numbers; Secondary Latency Timer (BNUM_SLT)—Offset 18h ............ 4276
16.0.5 I/O Base and Limit; Secondary Status (IOBL_SSTS)—Offset 1Ch............... 4276
16.0.6 Memory Base and Limit (MBL)—Offset 20h ............................................. 4278
16.0.7 Prefetchable Memory Base and Limit (PMBL)—Offset 24h ......................... 4278
16.0.8 Prefetchable Memory Base Upper 32 Bits (PMBU32)—Offset 28h ............... 4279
16.0.9 Prefetchable Memory Limit Upper 32 Bits (PMLU32)—Offset 2Ch ............... 4279
16.0.10Capabilities List Pointer (CAPP)—Offset 34h ............................................ 4280
16.0.11Interrupt Information; Bridge Control (INTR_BCTRL)—Offset 3Ch.............. 4281
16.0.12Capabilities List; PCI Express Capabilities (CLIST_XCAP)—Offset 40h ......... 4283
16.0.13Device Capabilities (DCAP)—Offset 44h.................................................. 4284
16.0.14Device Control; Device Status (DCTL_DSTS)—Offset 48h ......................... 4285
16.0.15Link Capabilities (LCAP)—Offset 4Ch...................................................... 4287
16.0.16Link Control; Link Status (LCTL_LSTS)—Offset 50h ................................. 4290
16.0.17Slot Capabilities (SLCAP)—Offset 54h .................................................... 4294
16.0.18Slot Control; Slot Status (SLCTL_SLSTS)—Offset 58h .............................. 4295
16.0.19Root Control (RCTL)—Offset 5Ch........................................................... 4296
16.0.20Root Status (RSTS)—Offset 60h............................................................ 4297
16.0.21Device Capabilities 2 (DCAP2)—Offset 64h ............................................. 4298
16.0.22Device Control 2; Device Status 2 (DCTL2_DSTS2)—Offset 68h ................ 4299
16.0.23Link Capabilities 2 (LCAP2)—Offset 6Ch ................................................. 4302
16.0.24Link Control 2; Link Status 2 (LCTL2_LSTS2)—Offset 70h ........................ 4304
16.0.25Slot Capabilities 2 (SLCAP2)—Offset 74h................................................ 4307
16.0.26Slot Control 2; Slot Status 2 (SLCTL2_SLSTS2)—Offset 78h ..................... 4308
16.0.27Message Signaled Interrupt Identifiers; Message Signaled Interrupt Message
Control (MID_MC)—Offset 80h.............................................................. 4308
16.0.28Message Signaled Interrupt Message Data (MD)—Offset 88h .................... 4309
16.0.29Subsystem Vendor Capability (SVCAP)—Offset 90h ................................. 4310
16.0.30Subsystem Vendor IDs (SVID)—Offset 94h ............................................ 4310
16.0.31Power Management Capability; PCI Power Management Capabilities
(PMCAP_PMC)—Offset A0h ................................................................... 4311
16.0.32PCI Power Management Control And Status (PMCS)—Offset A4h ............... 4312
16.0.33Advanced Error Extended Reporting Capability Header (AECH)—Offset 100h4313
16.0.34Uncorrectable Error Status (UES)—Offset 104h ....................................... 4314
16.0.35Uncorrectable Error Mask (UEM)—Offset 108h ........................................ 4315
16.0.36Uncorrectable Error Severity (UEV)—Offset 10Ch .................................... 4316
16.0.37Correctable Error Status (CES)—Offset 110h .......................................... 4317
16.0.38Correctable Error Mask (CEM)—Offset 114h............................................ 4318
16.0.39Advanced Error Capabilities and Control (AECC)—Offset 118h ................... 4319
16.0.40Header Log DW1 (HL_DW1)—Offset 11Ch .............................................. 4320
16.0.41Header Log DW2 (HL_DW2)—Offset 120h .............................................. 4320
16.0.42Header Log DW3 (HL_DW3)—Offset 124h .............................................. 4321
16.0.43Header Log DW4 (HL_DW4)—Offset 128h .............................................. 4321
16.0.44Root Error Command (REC)—Offset 12Ch .............................................. 4322
16.0.45Error Source Identification (ESID)—Offset 134h ...................................... 4322
16.0.46ACS Extended Capability Header (ACSECH)—Offset 140h ......................... 4323
16.0.47ACS Capability Register (ACSCAPR)—Offset 144h .................................... 4324
16.0.48ACS Control Register (ACSCTLR)—Offset 148h........................................ 4325
16.0.49PTM Extended Capability Header (PTMECH)—Offset 150h ......................... 4326
16.0.50PTM Capability Register (PTMCAPR)—Offset 154h .................................... 4327
16.0.51PTM Control Register (PTMCTLR)—Offset 158h........................................ 4328
16.0.52L1 Sub-States Extended Capability Header (L1SECH)—Offset 200h............ 4328
16.0.53L1 Sub-States Capabilities (L1SCAP)—Offset 204h .................................. 4329
16.0.54L1 Sub-States Control 1 (L1SCTL1)—Offset 208h .................................... 4331
16.0.55L1 Sub-States Control 2 (L1SCTL2)—Offset 20Ch .................................... 4332
16.0.56Secondary PCI Express Extended Capability Header (SPEECH)—Offset 220h 4333

106 334818
 16.0.57Link Control 3 (LCTL3)—Offset 224h ......................................................4334
16.0.58Lane Error Status (LES)—Offset 228h ....................................................4335
16.0.59Lane 0 and Lane 1 Equalization Control (L01EC)—Offset 22Ch ...................4336
16.0.60Lane 2 and Lane 3 Equalization Control (L23EC)—Offset 230h ...................4338
16.0.61PCI Express Replay Timer Policy 1 (PCIERTP1)—Offset 300h .....................4339
16.0.62PCI Express Replay Timer Policy 2 (PCIERTP2)—Offset 304h .....................4341
16.0.63PCI Express Status 1 (PCIESTS1)—Offset 328h .......................................4344
16.0.64PCI Express Status 2 (PCIESTS2)—Offset 32Ch .......................................4348
16.0.65PCI Express Compliance Measurement Mode (CMM) Port Control (PCIECMMPC)—
Offset 330h ........................................................................................4350
16.0.66PCI Express Compliance Measurement Mode Symbol Buffer (PCIECMMSB)—Offset
334h .................................................................................................4352
16.0.67PTM Propagation Delay (PTMPD)—Offset 390h.........................................4353
16.0.68PTM Lower Local Master Time (PTMLLMT)—Offset 394h ............................4353
16.0.69PTM Upper Local Master Time (PTMULMT)—Offset 398h ............................4354
16.0.70PTM Pipe Stage Delay Configuration 1 (PTMPSDC1)—Offset 39Ch ..............4354
16.0.71PTM Pipe Stage Delay Configuration 2 (PTMPSDC2)—Offset 3A0h...............4355
16.0.72PTM Pipe Stage Delay Configuration 3 (PTMPSDC3)—Offset 3A4h...............4356
16.0.73PTM Pipe Stage Delay Configuration 4 (PTMPSDC4)—Offset 3A8h...............4358
16.0.74PTM Pipe Stage Delay Configuration 5 (PTMPSDC5)—Offset 3ACh ..............4359
16.0.75PTM Extended Config (PTMECFG)—Offset 3B0h........................................4360
16.0.76PTM Lower T2 Time Stamp (PTMLT2TSTMP)—Offset 3B4h .........................4363
16.0.77PTM Upper T2 Time Stamp (PTMUT2TSTMP)—Offset 3B8h ........................4364
16.0.78Strap Configuration 2 (STRPFUSECFG2)—Offset 414h ..............................4364
16.0.79Thermal and Power Throttling (TNPT)—Offset 418h..................................4365
16.0.80Dynamic Lane Switch (DYNLNSW)—Offset 41Ch ......................................4369
16.0.81Power Control Enable (PCE)—Offset 428h ...............................................4370
16.0.82PGCB Control1 (PGCBCTL1)—Offset 42Ch ...............................................4371
16.0.83PGCB Control2 (PGCBCTL2)—Offset 430h ...............................................4374
16.0.84Equalization Configuration 1 (EQCFG1)—Offset 450h................................4375
16.0.85Remote Transmitter Preset Coefficient List 1 (RTPCL1)—Offset 454h ..........4381
16.0.86Remote Transmitter Preset Coefficient List 2 (RTPCL2)—Offset 458h ..........4384
16.0.87Remote Transmitter Preset Coefficient List 3 (RTPCL3)—Offset 45Ch ..........4387
16.0.88Remote Transmitter Preset Coefficient List 4 (RTPCL4)—Offset 460h ..........4390
16.0.89Figure Of Merit Status (FOMS)—Offset 464h............................................4393
16.0.90Hardware Autonomous Equalization Control (HAEQ)—Offset 468h ..............4394
16.0.91Local Transmitter Coefficient Override 1 (LTCO1)—Offset 470h..................4397
16.0.92Local Transmitter Coefficient Override 2 (LTCO2)—Offset 474h..................4399
16.0.93GEN3 L0s Control (G3L0SCTL)—Offset 478h ...........................................4401
16.0.94Equalization Configuration 2 (EQCFG2)—Offset 47Ch................................4403
16.0.95Monitor Mux (MM)—Offset 480h ............................................................4406
16.0.96Lane0 P0 and P1 Preset-Coefficient Mapping (L0P0P1PCM)—Offset 500h .....4407
16.0.97Lane0 P1, P2 and P3 Preset-Coefficient Mapping (L0P1P2P3PCM)—Offset 504h ...
4408
16.0.98Lane0 P3 and P4 Preset-Coefficient Mapping (L0P3P4PCM)—Offset 508h .....4409
16.0.99Lane0 P5 and P6 Preset-Coefficient Mapping (L0P5P6PCM)—Offset 50Ch.....4411
16.0.100Lane0 P6, P7 and P8 Preset-Coefficient Mapping (L0P6P7P8PCM)—Offset 510h..
4412
16.0.101Lane0 P8 and P9 Preset-Coefficient Mapping (L0P8P9PCM)—Offset 514h ...4413
16.0.102Lane0 P10 Preset-Coefficient Mapping (L0P10PCM)—Offset 518h..............4414
16.0.103Lane0 LF and FS (L0LFFS)—Offset 51Ch................................................4415
16.0.104Lane1 P0 and P1 Preset-Coefficient Mapping (L1P0P1PCM)—Offset 520h ...4417
16.0.105Lane1 P1, P2 and P3 Preset-Coefficient Mapping (L1P1P2P3PCM)—Offset 524h..
4418
16.0.106Lane1 P3 and P4 Preset-Coefficient Mapping (L1P3P4PCM)—Offset 528h ...4419

334818 107
 16.0.107Lane1 P5 and P6 Preset-Coefficient Mapping (L1P5P6PCM)—Offset 52Ch... 4420
16.0.108Lane1 P6, P7 and P8 Preset-Coefficient Mapping (L1P6P7P8PCM)—Offset 530h .
4422
16.0.109Lane1 P8 and P9 Preset-Coefficient Mapping (L1P8P9PCM)—Offset 534h ... 4423
16.0.110Lane1 P10 Preset-Coefficient Mapping (L1P10PCM)—Offset 538h ............. 4424
16.0.111Lane1 LF and FS (L1LFFS)—Offset 53Ch ............................................... 4425
16.0.112Lane2 P0 and P1 Preset-Coefficient Mapping (L2P0P1PCM)—Offset 540h ... 4426
16.0.113Lane2 P1, P2 and P3 Preset-Coefficient Mapping (L2P1P2P3PCM)—Offset 544h .
4427
16.0.114Lane2 P3 and P4 Preset-Coefficient Mapping (L2P3P4PCM)—Offset 548h ... 4428
16.0.115Lane2 P5 and P6 Preset-Coefficient Mapping (L2P5P6PCM)—Offset 54Ch... 4430
16.0.116Lane2 P6, P7 and P8 Preset-Coefficient Mapping (L2P6P7P8PCM)—Offset 550h .
4431
16.0.117Lane2 P8 and P9 Preset-Coefficient Mapping (L2P8P9PCM)—Offset 554h ... 4432
16.0.118Lane2 P10 Preset-Coefficient Mapping (L2P10PCM)—Offset 558h ............. 4433
16.0.119Lane2 LF and FS (L2LFFS)—Offset 55Ch ............................................... 4434
16.0.120Lane3 P0 and P1 Preset-Coefficient Mapping (L3P0P1PCM)—Offset 560h ... 4435
16.0.121Lane3 P1, P2 and P3 Preset-Coefficient Mapping (L3P1P2P3PCM)—Offset 564h .
4437
16.0.122Lane3 P3 and P4 Preset-Coefficient Mapping (L3P3P4PCM)—Offset 568h ... 4438
16.0.123Lane3 P5 and P6 Preset-Coefficient Mapping (L3P5P6PCM)—Offset 56Ch... 4439
16.0.124Lane3 P6, P7 and P8 Preset-Coefficient Mapping (L3P6P7P8PCM)—Offset 570h .
4440
16.0.125Lane3 P8 and P9 Preset-Coefficient Mapping (L3P8P9PCM)—Offset 574h ... 4441
16.0.126Lane3 P10 Preset-Coefficient Mapping (L3P10PCM)—Offset 578h ............. 4442
16.0.127Lane3 LF and FS (L3LFFS)—Offset 57Ch ............................................... 4443
16.0.128Lane3 LF and FS (L3LFFS)—Offset 57Ch ............................................... 4444
16.0.129PCLKD_L1TREF_CFG—Offset 1010h ..................................................... 4446
16.1 Registers Summary........................................................................................ 4449
16.1.1 Device Command; Primary Status (CMD_PSPCLKD_L1TREF_CFG—Offset
1010hTS)—Offset 4h........................................................................... 4452
16.1.2 Revision ID;Class Code (RID_CC)—Offset 8h .......................................... 4454
16.1.3 Cache Line Size; Primary Latency Timer; Header Type (CLS_PLT_HTYPE)—Offset
Ch .................................................................................................... 4455
16.1.4 Bus Numbers; Secondary Latency Timer (BNUM_SLT)—Offset 18h ............ 4456
16.1.5 I/O Base and Limit; Secondary Status (IOBL_SSTS)—Offset 1Ch............... 4456
16.1.6 Memory Base and Limit (MBL)—Offset 20h ............................................. 4458
16.1.7 Prefetchable Memory Base and Limit (PMBL)—Offset 24h ......................... 4458
16.1.8 Prefetchable Memory Base Upper 32 Bits (PMBU32)—Offset 28h ............... 4459
16.1.9 Prefetchable Memory Limit Upper 32 Bits (PMLU32)—Offset 2Ch ............... 4459
16.1.10Capabilities List Pointer (CAPP)—Offset 34h ............................................ 4460
16.1.11Interrupt Information; Bridge Control (INTR_BCTRL)—Offset 3Ch.............. 4461
16.1.12Capabilities List; PCI Express Capabilities (CLIST_XCAP)—Offset 40h ......... 4463
16.1.13Device Capabilities (DCAP)—Offset 44h.................................................. 4464
16.1.14Device Control; Device Status (DCTL_DSTS)—Offset 48h ......................... 4465
16.1.15Link Capabilities (LCAP)—Offset 4Ch...................................................... 4467
16.1.16Link Control; Link Status (LCTL_LSTS)—Offset 50h ................................. 4470
16.1.17Slot Capabilities (SLCAP)—Offset 54h .................................................... 4474
16.1.18Slot Control; Slot Status (SLCTL_SLSTS)—Offset 58h .............................. 4475
16.1.19Root Control (RCTL)—Offset 5Ch........................................................... 4476
16.1.20Root Status (RSTS)—Offset 60h............................................................ 4477
16.1.21Device Capabilities 2 (DCAP2)—Offset 64h ............................................. 4478
16.1.22Device Control 2; Device Status 2 (DCTL2_DSTS2)—Offset 68h ................ 4479
16.1.23Link Capabilities 2 (LCAP2)—Offset 6Ch ................................................. 4482
16.1.24Link Control 2; Link Status 2 (LCTL2_LSTS2)—Offset 70h ........................ 4484

108 334818
 16.1.25Slot Capabilities 2 (SLCAP2)—Offset 74h ................................................4487
16.1.26Slot Control 2; Slot Status 2 (SLCTL2_SLSTS2)—Offset 78h ......................4488
16.1.27Message Signaled Interrupt Identifiers; Message Signaled Interrupt Message
Control (MID_MC)—Offset 80h ..............................................................4488
16.1.28Message Signaled Interrupt Message Data (MD)—Offset 88h .....................4489
16.1.29Subsystem Vendor Capability (SVCAP)—Offset 90h ..................................4490
16.1.30Subsystem Vendor IDs (SVID)—Offset 94h .............................................4490
16.1.31Power Management Capability; PCI Power Management Capabilities
(PMCAP_PMC)—Offset A0h ...................................................................4491
16.1.32PCI Power Management Control And Status (PMCS)—Offset A4h ................4492
16.1.33Advanced Error Extended Reporting Capability Header (AECH)—Offset 100h4493
16.1.34Uncorrectable Error Status (UES)—Offset 104h .......................................4494
16.1.35Uncorrectable Error Mask (UEM)—Offset 108h .........................................4495
16.1.36Uncorrectable Error Severity (UEV)—Offset 10Ch.....................................4496
16.1.37Correctable Error Status (CES)—Offset 110h ...........................................4497
16.1.38Correctable Error Mask (CEM)—Offset 114h ............................................4498
16.1.39Advanced Error Capabilities and Control (AECC)—Offset 118h ...................4499
16.1.40Header Log DW1 (HL_DW1)—Offset 11Ch...............................................4500
16.1.41Header Log DW2 (HL_DW2)—Offset 120h...............................................4500
16.1.42Header Log DW3 (HL_DW3)—Offset 124h...............................................4501
16.1.43Header Log DW4 (HL_DW4)—Offset 128h...............................................4501
16.1.44Root Error Command (REC)—Offset 12Ch ...............................................4502
16.1.45Error Source Identification (ESID)—Offset 134h.......................................4502
16.1.46ACS Extended Capability Header (ACSECH)—Offset 140h..........................4503
16.1.47ACS Capability Register (ACSCAPR)—Offset 144h ....................................4504
16.1.48ACS Control Register (ACSCTLR)—Offset 148h ........................................4505
16.1.49PTM Extended Capability Header (PTMECH)—Offset 150h..........................4506
16.1.50PTM Capability Register (PTMCAPR)—Offset 154h ....................................4507
16.1.51PTM Control Register (PTMCTLR)—Offset 158h ........................................4508
16.1.52L1 Sub-States Extended Capability Header (L1SECH)—Offset 200h ............4508
16.1.53L1 Sub-States Capabilities (L1SCAP)—Offset 204h ...................................4509
16.1.54L1 Sub-States Control 1 (L1SCTL1)—Offset 208h.....................................4511
16.1.55L1 Sub-States Control 2 (L1SCTL2)—Offset 20Ch ....................................4512
16.1.56Secondary PCI Express Extended Capability Header (SPEECH)—Offset 220h 4513
16.1.57Link Control 3 (LCTL3)—Offset 224h ......................................................4514
16.1.58Lane Error Status (LES)—Offset 228h ....................................................4515
16.1.59Lane 0 and Lane 1 Equalization Control (L01EC)—Offset 22Ch ...................4516
16.1.60Lane 2 and Lane 3 Equalization Control (L23EC)—Offset 230h ...................4518
16.1.61PCI Express Replay Timer Policy 1 (PCIERTP1)—Offset 300h .....................4519
16.1.62PCI Express Replay Timer Policy 2 (PCIERTP2)—Offset 304h .....................4521
16.1.63PCI Express Status 1 (PCIESTS1)—Offset 328h .......................................4524
16.1.64PCI Express Status 2 (PCIESTS2)—Offset 32Ch .......................................4528
16.1.65PCI Express Compliance Measurement Mode (CMM) Port Control (PCIECMMPC)—
Offset 330h ........................................................................................4530
16.1.66PCI Express Compliance Measurement Mode Symbol Buffer (PCIECMMSB)—Offset
334h .................................................................................................4532
16.1.67PTM Propagation Delay (PTMPD)—Offset 390h.........................................4533
16.1.68PTM Lower Local Master Time (PTMLLMT)—Offset 394h ............................4533
16.1.69PTM Upper Local Master Time (PTMULMT)—Offset 398h ............................4534
16.1.70PTM Pipe Stage Delay Configuration 1 (PTMPSDC1)—Offset 39Ch ..............4534
16.1.71PTM Pipe Stage Delay Configuration 2 (PTMPSDC2)—Offset 3A0h...............4535
16.1.72PTM Pipe Stage Delay Configuration 3 (PTMPSDC3)—Offset 3A4h...............4536
16.1.73PTM Pipe Stage Delay Configuration 4 (PTMPSDC4)—Offset 3A8h...............4538
16.1.74PTM Pipe Stage Delay Configuration 5 (PTMPSDC5)—Offset 3ACh ..............4539
16.1.75PTM Extended Config (PTMECFG)—Offset 3B0h........................................4540

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 16.1.76PTM Lower T2 Time Stamp (PTMLT2TSTMP)—Offset 3B4h ........................ 4543
16.1.77PTM Upper T2 Time Stamp (PTMUT2TSTMP)—Offset 3B8h ........................ 4544
16.1.78Strap Configuration 2 (STRPFUSECFG2)—Offset 414h .............................. 4544
16.1.79Thermal and Power Throttling (TNPT)—Offset 418h ................................. 4545
16.1.80Dynamic Lane Switch (DYNLNSW)—Offset 41Ch...................................... 4549
16.1.81Power Control Enable (PCE)—Offset 428h............................................... 4550
16.1.82PGCB Control1 (PGCBCTL1)—Offset 42Ch .............................................. 4551
16.1.83PGCB Control2 (PGCBCTL2)—Offset 430h............................................... 4554
16.1.84Equalization Configuration 1 (EQCFG1)—Offset 450h ............................... 4555
16.1.85Remote Transmitter Preset Coefficient List 1 (RTPCL1)—Offset 454h.......... 4561
16.1.86Remote Transmitter Preset Coefficient List 2 (RTPCL2)—Offset 458h.......... 4564
16.1.87Remote Transmitter Preset Coefficient List 3 (RTPCL3)—Offset 45Ch.......... 4567
16.1.88Remote Transmitter Preset Coefficient List 4 (RTPCL4)—Offset 460h.......... 4570
16.1.89Figure Of Merit Status (FOMS)—Offset 464h ........................................... 4573
16.1.90Hardware Autonomous Equalization Control (HAEQ)—Offset 468h ............. 4574
16.1.91Local Transmitter Coefficient Override 1 (LTCO1)—Offset 470h ................. 4577
16.1.92Local Transmitter Coefficient Override 2 (LTCO2)—Offset 474h ................. 4579
16.1.93GEN3 L0s Control (G3L0SCTL)—Offset 478h ........................................... 4581
16.1.94Equalization Configuration 2 (EQCFG2)—Offset 47Ch ............................... 4583
16.1.95Monitor Mux (MM)—Offset 480h............................................................ 4586
16.1.96Lane0 P0 and P1 Preset-Coefficient Mapping (L0P0P1PCM)—Offset 500h .... 4587
16.1.97Lane0 P1, P2 and P3 Preset-Coefficient Mapping (L0P1P2P3PCM)—Offset 504h...
4588
16.1.98Lane0 P3 and P4 Preset-Coefficient Mapping (L0P3P4PCM)—Offset 508h .... 4589
16.1.99Lane0 P5 and P6 Preset-Coefficient Mapping (L0P5P6PCM)—Offset 50Ch .... 4591
16.1.100Lane0 P6, P7 and P8 Preset-Coefficient Mapping (L0P6P7P8PCM)—Offset 510h .
4592
16.1.101Lane0 P8 and P9 Preset-Coefficient Mapping (L0P8P9PCM)—Offset 514h ... 4593
16.1.102Lane0 P10 Preset-Coefficient Mapping (L0P10PCM)—Offset 518h ............. 4594
16.1.103Lane0 LF and FS (L0LFFS)—Offset 51Ch ............................................... 4595
16.1.104Lane1 P0 and P1 Preset-Coefficient Mapping (L1P0P1PCM)—Offset 520h ... 4597
16.1.105Lane1 P1, P2 and P3 Preset-Coefficient Mapping (L1P1P2P3PCM)—Offset 524h .
4598
16.1.106Lane1 P3 and P4 Preset-Coefficient Mapping (L1P3P4PCM)—Offset 528h ... 4599
16.1.107Lane1 P5 and P6 Preset-Coefficient Mapping (L1P5P6PCM)—Offset 52Ch... 4600
16.1.108Lane1 P6, P7 and P8 Preset-Coefficient Mapping (L1P6P7P8PCM)—Offset 530h .
4602
16.1.109Lane1 P8 and P9 Preset-Coefficient Mapping (L1P8P9PCM)—Offset 534h ... 4603
16.1.110Lane1 P10 Preset-Coefficient Mapping (L1P10PCM)—Offset 538h ............. 4604
16.1.111Lane1 LF and FS (L1LFFS)—Offset 53Ch ............................................... 4605
16.1.112Lane2 P0 and P1 Preset-Coefficient Mapping (L2P0P1PCM)—Offset 540h ... 4606
16.1.113Lane2 P1, P2 and P3 Preset-Coefficient Mapping (L2P1P2P3PCM)—Offset 544h .
4607
16.1.114Lane2 P3 and P4 Preset-Coefficient Mapping (L2P3P4PCM)—Offset 548h ... 4608
16.1.115Lane2 P5 and P6 Preset-Coefficient Mapping (L2P5P6PCM)—Offset 54Ch... 4610
16.1.116Lane2 P6, P7 and P8 Preset-Coefficient Mapping (L2P6P7P8PCM)—Offset 550h .
4611
16.1.117Lane2 P8 and P9 Preset-Coefficient Mapping (L2P8P9PCM)—Offset 554h ... 4612
16.1.118Lane2 P10 Preset-Coefficient Mapping (L2P10PCM)—Offset 558h ............. 4613
16.1.119Lane2 LF and FS (L2LFFS)—Offset 55Ch ............................................... 4614
16.1.120Lane3 P0 and P1 Preset-Coefficient Mapping (L3P0P1PCM)—Offset 560h ... 4615
16.1.121Lane3 P1, P2 and P3 Preset-Coefficient Mapping (L3P1P2P3PCM)—Offset 564h .
4617
16.1.122Lane3 P3 and P4 Preset-Coefficient Mapping (L3P3P4PCM)—Offset 568h ... 4618
16.1.123Lane3 P5 and P6 Preset-Coefficient Mapping (L3P5P6PCM)—Offset 56Ch... 4619

110 334818
 16.1.124Lane3 P6, P7 and P8 Preset-Coefficient Mapping (L3P6P7P8PCM)—Offset 570h..
4620
16.1.125Lane3 P8 and P9 Preset-Coefficient Mapping (L3P8P9PCM)—Offset 574h ...4621
16.1.126Lane3 P10 Preset-Coefficient Mapping (L3P10PCM)—Offset 578h..............4622
16.1.127Lane3 LF and FS (L3LFFS)—Offset 57Ch................................................4623
16.1.128Lane3 LF and FS (L3LFFS)—Offset 57Ch................................................4624
16.1.129PCLKD_L1TREF_CFG—Offset 1010h......................................................4626
17 SATA ....................................................................................................................4629
17.1 Registers Summary ........................................................................................4629
17.1.1 Command (CMD)—Offset 4h .................................................................4630
17.1.2 Device Status (STS)—Offset 6h .............................................................4631
17.1.3 Revision ID (RID)—Offset 8h ................................................................4632
17.1.4 Programming Interface (PI)—Offset 9h...................................................4632
17.1.5 Cache Line Size (CLS)—Offset Ch ..........................................................4633
17.1.6 Master Latency Timer (MLT)—Offset Dh..................................................4633
17.1.7 Header Type (HTYPE)—Offset Eh ...........................................................4634
17.1.8 MSI-X Table Base Address (MXTBA)—Offset 10h......................................4634
17.1.9 MXP Base Address (MXPBA)—Offset 14h.................................................4635
17.1.10SCMDBA (SCMDBA)—Offset 18h............................................................4636
17.1.11SCTLBA (SCTLBA)—Offset 1Ch ..............................................................4636
17.1.12AHCI Index Data Pair Base Address (AIDPBA)—Offset 20h ........................4637
17.1.13AHCI Base Address (ABAR)—Offset 24h..................................................4637
17.1.14Sub System Identifiers (SS)—Offset 2Ch ................................................4639
17.1.15Capabilities Pointer (CAP)—Offset 34h....................................................4639
17.1.16Interrupt Information (INTR)—Offset 3Ch ...............................................4640
17.1.17PCI Power Management Capability ID (PID)—Offset 70h ...........................4640
17.1.18PCI Power Management Control and Status (PMCS)—Offset 74h ................4641
17.1.19Message Signalled Interrupt Identifier (MID)—Offset 80h..........................4642
17.1.20Message Signalled Interrupt Message Control (MC)—Offset 82h .................4643
17.1.21Message Signalled Interrupt Message Data (MD)—Offset 88h ....................4643
17.1.22Port Mapping Register (MAP)—Offset 90h ...............................................4644
17.1.23SATA General Configuration (SATAGC)—Offset 9Ch..................................4645
17.1.24SATA Initialization Register Index (SIRI)—Offset A0h ...............................4648
17.1.25SATA Initialization Register Data (SIRD)—Offset A4h ...............................4649
17.1.26Serial ATA Capability Register 0 (SATACR0)—Offset A8h ...........................4649
17.1.27Serial ATA Capability Register 1 (SATACR1)—Offset ACh...........................4650
17.1.28FLR Capability ID (FLRCID)—Offset B0h .................................................4651
17.1.29FLR Capability Length and Version (FLRCAP)—Offset B2h..........................4651
17.1.30FLR Control (FLRCTL)—Offset B4h .........................................................4652
17.1.31Scratch Pad (SP)—Offset C0h................................................................4653
17.1.32MSI-X Identifiers (MXID)—Offset D0h ....................................................4653
17.1.33MSI-X Message Control (MXC)—Offset D2h .............................................4654
17.1.34MSI-X Table Offset / Table BIR (MXT)—Offset D4h...................................4654
17.1.35MSI-X PBA Offset / PBA BIR (MXP)—Offset D8h .......................................4655
17.1.36BIST FIS Control/Status (BFCS)—Offset E0h ...........................................4656
17.1.37BIST FIS Transmit Data 1 (BFTD1)—Offset E4h .......................................4658
17.1.38BIST FIS Transmit Data 2 (BFTD2)—Offset E8h .......................................4659
17.1.39Manufacturing ID (MFID)—Offset F8h.....................................................4659
17.2 Registers Summary ........................................................................................4660
17.2.1 AHCI Data Register (DATA)—Offset 14h .................................................4660
17.3 Registers Summary ........................................................................................4661
17.3.1 HBA Capabilities (GHC_CAP)—Offset 0h..................................................4662
17.3.2 Global HBA Control (GHC)—Offset 4h .....................................................4665
17.3.3 Ports Implemented (GHC_PI)—Offset Ch ................................................4666

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 17.3.4 AHCI Version (VS)—Offset 10h ............................................................. 4667
17.3.5 Enclosure Management Location (EM_LOC)—Offset 1Ch ........................... 4668
17.3.6 Enclosure Management Control (EM_CTL)—Offset 20h ............................. 4669
17.3.7 HBA Capabilities Extended (GHC_CAP2)—Offset 24h................................ 4670
17.3.8 Vendor Specific (VSP)—Offset A0h ........................................................ 4671
17.3.9 Vendor-Specific Capabilities Register (VS_CAP)—Offset A4h ..................... 4672
17.3.10Remapping Under NVMe (RUN)—Offset A8h ........................................... 4673
17.3.11RAID Platform ID (RPID)—Offset C0h .................................................... 4674
17.3.12Premium Feature Block (PFB)—Offset C4h.............................................. 4675
17.3.13SW Feature Mask (SFM)—Offset C8h ..................................................... 4675
17.3.14Port [0-7] Command List Base Address (PxCLB0)—Offset 100h ................. 4677
17.3.15Port [0-7] Command List Base Address Upper 32-bits (PxCLBU0)—Offset 104h ..
4677
17.3.16Port [0-7] FIS Base Address (PxFB0)—Offset 108h .................................. 4678
17.3.17Port [0-7] FIS Base Address Upper 32-bits (PxFBU0)—Offset 10Ch ............ 4678
17.3.18Port [0-7] Interrupt Status (PxIS0)—Offset 110h .................................... 4679
17.3.19Port [0-7] Interrupt Enable (PxIE0)—Offset 114h .................................... 4681
17.3.20Port [0-7] Command (PxCMD0)—Offset 118h ......................................... 4682
17.3.21Port [0-7] Task File Data (PxTFD0)—Offset 120h..................................... 4685
17.3.22Port [0-7] Signature (PxSIG0)—Offset 124h ........................................... 4686
17.3.23Port [0-7] Serial ATA Status (PxSSTS0)—Offset 128h .............................. 4686
17.3.24Port [0-7] Serial ATA Control (PxSCTL0)—Offset 12Ch ............................. 4687
17.3.25Port [0-7] Serial ATA Error (PxSERR0)—Offset 130h ................................ 4687
17.3.26Port [0-7] Serial ATA Active (PxSACT0)—Offset 134h............................... 4688
17.3.27Port [0-7] Commands Issued (PxCI0)—Offset 138h ................................. 4688
17.3.28Port [0-7] SNotification (PxSNTF0)—Offset 13Ch..................................... 4689
17.3.29Port [0-7] Device Sleep (PxDEVSLP0)—Offset 144h ................................. 4690
17.3.30Port [0-7] Command List Base Address (PxCLB1)—Offset 180h ................. 4691
17.3.31Port [0-7] Command List Base Address Upper 32-bits (PxCLBU1)—Offset 184h ..
4692
17.3.32Port [0-7] FIS Base Address (PxFB1)—Offset 188h .................................. 4692
17.3.33Port [0-7] FIS Base Address Upper 32-bits (PxFBU1)—Offset 18Ch ............ 4693
17.3.34Port [0-7] Interrupt Status (PxIS1)—Offset 190h .................................... 4693
17.3.35Port [0-7] Interrupt Enable (PxIE1)—Offset 194h .................................... 4695
17.3.36Port [0-7] Command (PxCMD1)—Offset 198h ......................................... 4697
17.3.37Port [0-7] Task File Data (PxTFD1)—Offset 1A0h..................................... 4699
17.3.38Port [0-7] Signature (PxSIG1)—Offset 1A4h ........................................... 4700
17.3.39Port [0-7] Serial ATA Status (PxSSTS1)—Offset 1A8h .............................. 4701
17.3.40Port [0-7] Serial ATA Control (PxSCTL1)—Offset 1ACh ............................. 4701
17.3.41Port [0-7] Serial ATA Error (PxSERR1)—Offset 1B0h ................................ 4702
17.3.42Port [0-7] Serial ATA Active (PxSACT1)—Offset 1B4h .............................. 4702
17.3.43Port [0-7] Commands Issued (PxCI1)—Offset 1B8h ................................. 4703
17.3.44Port [0-7] SNotification (PxSNTF1)—Offset 1BCh..................................... 4703
17.3.45Port [0-7] Device Sleep (PxDEVSLP1)—Offset 1C4h ................................. 4704
17.3.46Enclosure Management Message Format (EM_MF)—Offset 580h ................ 4706
17.3.47Enclosure Management LED (EM_LED)—Offset 584h................................ 4706
17.4 Registers Summary........................................................................................ 4707
17.4.1 MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)—Offset 0h ...................... 4708
17.4.2 MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)—Offset 4h ...................... 4708
17.5 Registers Summary........................................................................................ 4709
17.5.1 MSI-X Table Entries 0 Message Lower Address (MXTE0MLA)—Offset 0h...... 4709
17.5.2 MSI-X Table Entries 0 Message Upper Address (MXTE0MUA)—Offset 4h ..... 4710
17.5.3 MSI-X Table Entries 0 Message Data (MXTE0MD)—Offset 8h..................... 4710
17.5.4 MSI-X Table Entries 0 Vector Control (MXTE0VC)—Offset Ch..................... 4711
17.6 Registers Summary........................................................................................ 4713

112 334818
 17.6.1 Command (CMD)—Offset 4h .................................................................4714
17.6.2 Device Status (STS)—Offset 6h .............................................................4715
17.6.3 Revision ID (RID)—Offset 8h ................................................................4716
17.6.4 Programming Interface (PI)—Offset 9h...................................................4716
17.6.5 Cache Line Size (CLS)—Offset Ch ..........................................................4717
17.6.6 Master Latency Timer (MLT)—Offset Dh..................................................4717
17.6.7 Header Type (HTYPE)—Offset Eh ...........................................................4718
17.6.8 MSI-X Table Base Address (MXTBA)—Offset 10h......................................4718
17.6.9 MXP Base Address (MXPBA)—Offset 14h.................................................4719
17.6.10SCMDBA (SCMDBA)—Offset 18h............................................................4719
17.6.11SCTLBA (SCTLBA)—Offset 1Ch ..............................................................4720
17.6.12AHCI Index Data Pair Base Address (AIDPBA)—Offset 20h ........................4721
17.6.13AHCI Base Address (ABAR)—Offset 24h..................................................4721
17.6.14Sub System Identifiers (SS)—Offset 2Ch ................................................4722
17.6.15Capabilities Pointer (CAP)—Offset 34h....................................................4723
17.6.16Interrupt Information (INTR)—Offset 3Ch ...............................................4723
17.6.17PCI Power Management Capability ID (PID)—Offset 70h ...........................4724
17.6.18PCI Power Management Control and Status (PMCS)—Offset 74h ................4724
17.6.19Message Signalled Interrupt Identifier (MID)—Offset 80h..........................4725
17.6.20Message Signalled Interrupt Message Control (MC)—Offset 82h .................4726
17.6.21Message Signalled Interrupt Message Data (MD)—Offset 88h ....................4727
17.6.22Port Mapping Register (MAP)—Offset 90h ...............................................4727
17.6.23SATA General Configuration (SATAGC)—Offset 9Ch..................................4729
17.6.24SATA Initialization Register Index (SIRI)—Offset A0h ...............................4732
17.6.25SATA Initialization Register Data (SIRD)—Offset A4h ...............................4732
17.6.26Serial ATA Capability Register 0 (SATACR0)—Offset A8h ...........................4733
17.6.27Serial ATA Capability Register 1 (SATACR1)—Offset ACh...........................4734
17.6.28FLR Capability ID (FLRCID)—Offset B0h .................................................4734
17.6.29FLR Capability Length and Version (FLRCAP)—Offset B2h..........................4735
17.6.30FLR Control (FLRCTL)—Offset B4h .........................................................4736
17.6.31Scratch Pad (SP)—Offset C0h................................................................4736
17.6.32MSI-X Identifiers (MXID)—Offset D0h ....................................................4737
17.6.33MSI-X Message Control (MXC)—Offset D2h .............................................4737
17.6.34MSI-X Table Offset / Table BIR (MXT)—Offset D4h...................................4738
17.6.35MSI-X PBA Offset / PBA BIR (MXP)—Offset D8h .......................................4739
17.6.36BIST FIS Control/Status (BFCS)—Offset E0h ...........................................4739
17.6.37BIST FIS Transmit Data 1 (BFTD1)—Offset E4h .......................................4742
17.6.38BIST FIS Transmit Data 2 (BFTD2)—Offset E8h .......................................4743
17.6.39Manufacturing ID (MFID)—Offset F8h.....................................................4743
17.7 Registers Summary ........................................................................................4745
17.7.1 AHCI Data Register (DATA)—Offset 14h .................................................4745
17.8 Registers Summary ........................................................................................4747
17.8.1 HBA Capabilities (GHC_CAP)—Offset 0h..................................................4748
17.8.2 Global HBA Control (GHC)—Offset 4h .....................................................4750
17.8.3 Ports Implemented (GHC_PI)—Offset Ch ................................................4752
17.8.4 AHCI Version (VS)—Offset 10h..............................................................4753
17.8.5 Enclosure Management Location (EM_LOC)—Offset 1Ch ...........................4754
17.8.6 Enclosure Management Control (EM_CTL)—Offset 20h..............................4754
17.8.7 HBA Capabilities Extended (GHC_CAP2)—Offset 24h ................................4756
17.8.8 Vendor Specific (VSP)—Offset A0h .........................................................4757
17.8.9 Vendor-Specific Capabilities Register (VS_CAP)—Offset A4h ......................4758
17.8.10Remapping Under NVMe (RUN)—Offset A8h ............................................4759
17.8.11RAID Platform ID (RPID)—Offset C0h.....................................................4760
17.8.12Premium Feature Block (PFB)—Offset C4h ..............................................4760
17.8.13SW Feature Mask (SFM)—Offset C8h......................................................4761

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 17.8.14Port [0-7] Command List Base Address (PxCLB0)—Offset 100h ................. 4762
17.8.15Port [0-7] Command List Base Address Upper 32-bits (PxCLBU0)—Offset 104h ..
4763
17.8.16Port [0-7] FIS Base Address (PxFB0)—Offset 108h .................................. 4763
17.8.17Port [0-7] FIS Base Address Upper 32-bits (PxFBU0)—Offset 10Ch ............ 4764
17.8.18Port [0-7] Interrupt Status (PxIS0)—Offset 110h .................................... 4764
17.8.19Port [0-7] Interrupt Enable (PxIE0)—Offset 114h .................................... 4766
17.8.20Port [0-7] Command (PxCMD0)—Offset 118h ......................................... 4768
17.8.21Port [0-7] Task File Data (PxTFD0)—Offset 120h..................................... 4770
17.8.22Port [0-7] Signature (PxSIG0)—Offset 124h ........................................... 4771
17.8.23Port [0-7] Serial ATA Status (PxSSTS0)—Offset 128h .............................. 4772
17.8.24Port [0-7] Serial ATA Control (PxSCTL0)—Offset 12Ch ............................. 4772
17.8.25Port [0-7] Serial ATA Error (PxSERR0)—Offset 130h ................................ 4773
17.8.26Port [0-7] Serial ATA Active (PxSACT0)—Offset 134h............................... 4773
17.8.27Port [0-7] Commands Issued (PxCI0)—Offset 138h ................................. 4774
17.8.28Port [0-7] SNotification (PxSNTF0)—Offset 13Ch..................................... 4774
17.8.29Port [0-7] Device Sleep (PxDEVSLP0)—Offset 144h ................................. 4775
17.8.30Port [0-7] Command List Base Address (PxCLB1)—Offset 180h ................. 4777
17.8.31Port [0-7] Command List Base Address Upper 32-bits (PxCLBU1)—Offset 184h ..
4777
17.8.32Port [0-7] FIS Base Address (PxFB1)—Offset 188h .................................. 4778
17.8.33Port [0-7] FIS Base Address Upper 32-bits (PxFBU1)—Offset 18Ch ............ 4778
17.8.34Port [0-7] Interrupt Status (PxIS1)—Offset 190h .................................... 4779
17.8.35Port [0-7] Interrupt Enable (PxIE1)—Offset 194h .................................... 4781
17.8.36Port [0-7] Command (PxCMD1)—Offset 198h ......................................... 4782
17.8.37Port [0-7] Task File Data (PxTFD1)—Offset 1A0h..................................... 4785
17.8.38Port [0-7] Signature (PxSIG1)—Offset 1A4h ........................................... 4786
17.8.39Port [0-7] Serial ATA Status (PxSSTS1)—Offset 1A8h .............................. 4786
17.8.40Port [0-7] Serial ATA Control (PxSCTL1)—Offset 1ACh ............................. 4787
17.8.41Port [0-7] Serial ATA Error (PxSERR1)—Offset 1B0h ................................ 4787
17.8.42Port [0-7] Serial ATA Active (PxSACT1)—Offset 1B4h .............................. 4788
17.8.43Port [0-7] Commands Issued (PxCI1)—Offset 1B8h ................................. 4788
17.8.44Port [0-7] SNotification (PxSNTF1)—Offset 1BCh..................................... 4789
17.8.45Port [0-7] Device Sleep (PxDEVSLP1)—Offset 1C4h ................................. 4790
17.8.46Enclosure Management Message Format (EM_MF)—Offset 580h ................ 4791
17.8.47Enclosure Management LED (EM_LED)—Offset 584h................................ 4792
17.9 Registers Summary........................................................................................ 4795
17.9.1 MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)—Offset 0h ...................... 4795
17.9.2 MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)—Offset 4h ...................... 4795
17.10 Registers Summary........................................................................................ 4797
17.10.1MSI-X Table Entries 0 Message Lower Address (MXTE0MLA)—Offset 0h...... 4797
17.10.2MSI-X Table Entries 0 Message Upper Address (MXTE0MUA)—Offset 4h ..... 4797
17.10.3MSI-X Table Entries 0 Message Data (MXTE0MD)—Offset 8h..................... 4798
17.10.4MSI-X Table Entries 0 Vector Control (MXTE0VC)—Offset Ch..................... 4798
18 USB...................................................................................................................... 4801
18.1 Registers Summary........................................................................................ 4801
18.1.1 Capability Registers Length (CAPLENGTH)—Offset 0h .............................. 4814
18.1.2 Host Controller Interface Version Number (HCIVERSION)—Offset 2h.......... 4814
18.1.3 Structural Parameters 1 (HCSPARAMS1)—Offset 4h................................. 4815
18.1.4 Structural Parameters 2 (HCSPARAMS2)—Offset 8h................................. 4815
18.1.5 Structural Parameters 3 (HCSPARAMS3)—Offset Ch ................................ 4816
18.1.6 Capability Parameters (HCCPARAMS)—Offset 10h ................................... 4817
18.1.7 Doorbell Offset (DBOFF)—Offset 14h ..................................................... 4818
18.1.8 Runtime Register Space Offset (RTSOFF)—Offset 18h .............................. 4818

114 334818
 18.1.9 USB Command (USBCMD)—Offset 80h...................................................4818
18.1.10USB Status (USBSTS)—Offset 84h .........................................................4819
18.1.11Page Size (PAGESIZE)—Offset 88h ........................................................4820
18.1.12Device Notification Control (DNCTRL)—Offset 94h....................................4821
18.1.13Command Ring Low (CRCR_LO)—Offset 98h ...........................................4821
18.1.14Command Ring High (CRCR_HI)—Offset 9Ch...........................................4822
18.1.15Device Context Base Address Array Pointer Low (DCBAAP_LO)—Offset B0h.4822
18.1.16Device Context Base Address Array Pointer High (DCBAAP_HI)—Offset B4h 4823
18.1.17Configure (CONFIG)—Offset B8h ...........................................................4823
18.1.18Port Status and Control USB2 (PORTSC1)—Offset 480h ............................4823
18.1.19Port Power Management Status and Control USB2 (PORTPMSC1)—Offset 484h ...
4825
18.1.20Port X Hardware LPM Control Register (PORTHLPMC1)—Offset 48Ch...........4826
18.1.21Port Status and Control USB2 (PORTSC2)—Offset 490h ............................4826
18.1.22Port Power Management Status and Control USB2 (PORTPMSC2)—Offset 494h ...
4828
18.1.23Port X Hardware LPM Control Register (PORTHLPMC2)—Offset 49Ch...........4829
18.1.24Port Status and Control USB2 (PORTSC3)—Offset 4A0h ............................4829
18.1.25Port Power Management Status and Control USB2 (PORTPMSC3)—Offset 4A4h...
4831
18.1.26Port X Hardware LPM Control Register (PORTHLPMC3)—Offset 4ACh...........4832
18.1.27Port Status and Control USB2 (PORTSC4)—Offset 4B0h ............................4832
18.1.28Port Power Management Status and Control USB2 (PORTPMSC4)—Offset 4B4h...
4834
18.1.29Port X Hardware LPM Control Register (PORTHLPMC4)—Offset 4BCh...........4835
18.1.30Port Status and Control USB2 (PORTSC5)—Offset 4C0h ............................4835
18.1.31Port Power Management Status and Control USB2 (PORTPMSC5)—Offset 4C4h...
4837
18.1.32Port X Hardware LPM Control Register (PORTHLPMC5)—Offset 4CCh ..........4838
18.1.33Port Status and Control USB2 (PORTSC6)—Offset 4D0h............................4838
18.1.34Port Power Management Status and Control USB2 (PORTPMSC6)—Offset 4D4h...
4840
18.1.35Port X Hardware LPM Control Register (PORTHLPMC6)—Offset 4DCh ..........4841
18.1.36Port Status and Control USB2 (PORTSC7)—Offset 4E0h ............................4841
18.1.37Port Power Management Status and Control USB2 (PORTPMSC7)—Offset 4E4h ...
4843
18.1.38Port X Hardware LPM Control Register (PORTHLPMC7)—Offset 4ECh...........4844
18.1.39Port Status and Control USB2 (PORTSC8)—Offset 4F0h ............................4844
18.1.40Port Power Management Status and Control USB2 (PORTPMSC8)—Offset 4F4h ...
4846
18.1.41Port X Hardware LPM Control Register (PORTHLPMC8)—Offset 4FCh ...........4847
18.1.42Port Status and Control USB3 (PORTSC9)—Offset 500h ............................4847
18.1.43Port Power Management Status and Control USB3 (PORTPMSC9)—Offset 504h ...
4849
18.1.44USB3 Port Link Info (PORTLI9)—Offset 508h ...........................................4849
18.1.45Port Status and Control USB3 (PORTSC10)—Offset 510h ..........................4850
18.1.46Port Power Management Status and Control USB3 (PORTPMSC10)—Offset 514h .
4851
18.1.47USB3 Port Link Info (PORTLI10)—Offset 518h .........................................4852
18.1.48Port Status and Control USB3 (PORTSC11)—Offset 520h ..........................4852
18.1.49Port Power Management Status and Control USB3 (PORTPMSC11)—Offset 524h .
4854
18.1.50USB3 Port Link Info (PORTLI11)—Offset 528h .........................................4854
18.1.51Port Status and Control USB3 (PORTSC12)—Offset 530h ..........................4855
18.1.52Port Power Management Status and Control USB3 (PORTPMSC12)—Offset 534h .
4856

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 18.1.53USB3 Port Link Info (PORTLI12)—Offset 538h......................................... 4857
18.1.54Port Status and Control USB3 (PORTSC13)—Offset 540h.......................... 4857
18.1.55Port Power Management Status and Control USB3 (PORTPMSC13)—Offset 544h.
4859
18.1.56USB3 Port Link Info (PORTLI13)—Offset 548h......................................... 4859
18.1.57Port Status and Control USB3 (PORTSC14)—Offset 550h.......................... 4860
18.1.58Port Power Management Status and Control USB3 (PORTPMSC14)—Offset 554h.
4861
18.1.59USB3 Port Link Info (PORTLI14)—Offset 558h......................................... 4862
18.1.60Port Status and Control USB3 (PORTSC15)—Offset 560h.......................... 4862
18.1.61Port Power Management Status and Control USB3 (PORTPMSC15)—Offset 564h.
4864
18.1.62USB3 Port Link Info (PORTLI15)—Offset 568h......................................... 4864
18.1.63Microframe Index (RTMFINDEX)—Offset 2000h ....................................... 4865
18.1.64Interrupter 1 Management (IMAN0)—Offset 2020h.................................. 4865
18.1.65Interrupter 1 Moderation (IMOD0)—Offset 2024h.................................... 4866
18.1.66Event Ring Segment Table Size 1 (ERSTSZ0)—Offset 2028h ..................... 4866
18.1.67Event Ring Segment Table Base Address Low 1 (ERSTBA_LO0)—Offset 2030h ...
4867
18.1.68Event Ring Segment Table Base Address High 1 (ERSTBA_HI0)—Offset 2034h ...
4867
18.1.69Event Ring Dequeue Pointer Low 1 (ERDP_LO0)—Offset 2038h ................. 4868
18.1.70Event Ring Dequeue Pointer High 1 (ERDP_HI0)—Offset 203Ch................. 4868
18.1.71Interrupter 2 Management (IMAN1)—Offset 2040h.................................. 4869
18.1.72Interrupter 2 Moderation (IMOD1)—Offset 2044h.................................... 4869
18.1.73Event Ring Segment Table Size 2 (ERSTSZ1)—Offset 2048h ..................... 4870
18.1.74Event Ring Segment Table Base Address Low 2 (ERSTBA_LO1)—Offset 2050h ...
4870
18.1.75Event Ring Segment Table Base Address High 2 (ERSTBA_HI1)—Offset 2054h ...
4871
18.1.76Event Ring Dequeue Pointer Low 2 (ERDP_LO1)—Offset 2058h ................. 4871
18.1.77Event Ring Dequeue Pointer High 2 (ERDP_HI1)—Offset 205Ch................. 4872
18.1.78Interrupter 3 Management (IMAN2)—Offset 2060h.................................. 4872
18.1.79Interrupter 3 Moderation (IMOD2)—Offset 2064h.................................... 4873
18.1.80Event Ring Segment Table Size 3 (ERSTSZ2)—Offset 2068h ..................... 4873
18.1.81Event Ring Segment Table Base Address Low 3 (ERSTBA_LO2)—Offset 2070h ...
4874
18.1.82Event Ring Segment Table Base Address High 3 (ERSTBA_HI2)—Offset 2074h ...
4874
18.1.83Event Ring Dequeue Pointer Low 3 (ERDP_LO2)—Offset 2078h ................. 4875
18.1.84Event Ring Dequeue Pointer High 3 (ERDP_HI2)—Offset 207Ch................. 4875
18.1.85Interrupter 4 Management (IMAN3)—Offset 2080h.................................. 4876
18.1.86Interrupter 4 Moderation (IMOD3)—Offset 2084h.................................... 4876
18.1.87Event Ring Segment Table Size 4 (ERSTSZ3)—Offset 2088h ..................... 4877
18.1.88Event Ring Segment Table Base Address Low 4 (ERSTBA_LO3)—Offset 2090h ...
4877
18.1.89Event Ring Segment Table Base Address High 4 (ERSTBA_HI3)—Offset 2094h ...
4878
18.1.90Event Ring Dequeue Pointer Low 4 (ERDP_LO3)—Offset 2098h ................. 4878
18.1.91Event Ring Dequeue Pointer High 4 (ERDP_HI3)—Offset 209Ch................. 4879
18.1.92Interrupter 5 Management (IMAN4)—Offset 20A0h ................................. 4879
18.1.93Interrupter 5 Moderation (IMOD4)—Offset 20A4h.................................... 4880
18.1.94Event Ring Segment Table Size 5 (ERSTSZ4)—Offset 20A8h..................... 4880
18.1.95Event Ring Segment Table Base Address Low 5 (ERSTBA_LO4)—Offset 20B0h ...
4881

116 334818
 18.1.96Event Ring Segment Table Base Address High 5 (ERSTBA_HI4)—Offset 20B4h ...
4881
18.1.97Event Ring Dequeue Pointer Low 5 (ERDP_LO4)—Offset 20B8h..................4882
18.1.98Event Ring Dequeue Pointer High 5 (ERDP_HI4)—Offset 20BCh .................4882
18.1.99Interrupter 6 Management (IMAN5)—Offset 20C0h ..................................4883
18.1.100Interrupter 6 Moderation (IMOD5)—Offset 20C4h...................................4883
18.1.101Event Ring Segment Table Size 6 (ERSTSZ5)—Offset 20C8h....................4884
18.1.102Event Ring Segment Table Base Address Low 6 (ERSTBA_LO5)—Offset 20D0h ..
4884
18.1.103Event Ring Segment Table Base Address High 6 (ERSTBA_HI5)—Offset 20D4h..
4885
18.1.104Event Ring Dequeue Pointer Low 6 (ERDP_LO5)—Offset 20D8h ................4885
18.1.105Event Ring Dequeue Pointer High 6 (ERDP_HI5)—Offset 20DCh ...............4886
18.1.106Interrupter 7 Management (IMAN6)—Offset 20E0h.................................4886
18.1.107Interrupter 7 Moderation (IMOD6)—Offset 20E4h ...................................4887
18.1.108Event Ring Segment Table Size 7 (ERSTSZ6)—Offset 20E8h ....................4887
18.1.109Event Ring Segment Table Base Address Low 7 (ERSTBA_LO6)—Offset 20F0h ..
4888
18.1.110Event Ring Segment Table Base Address High 7 (ERSTBA_HI6)—Offset 20F4h ..
4888
18.1.111Event Ring Dequeue Pointer Low 7 (ERDP_LO6)—Offset 20F8h ................4889
18.1.112Event Ring Dequeue Pointer High 7 (ERDP_HI6)—Offset 20FCh ................4889
18.1.113Interrupter 8 Management (IMAN7)—Offset 2100h.................................4890
18.1.114Interrupter 8 Moderation (IMOD7)—Offset 2104h ...................................4890
18.1.115Event Ring Segment Table Size 8 (ERSTSZ7)—Offset 2108h ....................4891
18.1.116Event Ring Segment Table Base Address Low 8 (ERSTBA_LO7)—Offset 2110h ..
4891
18.1.117Event Ring Segment Table Base Address High 8 (ERSTBA_HI7)—Offset 2114h ..
4892
18.1.118Event Ring Dequeue Pointer Low 8 (ERDP_LO7)—Offset 2118h ................4892
18.1.119Event Ring Dequeue Pointer High 8 (ERDP_HI7)—Offset 211Ch................4893
18.1.120Door Bell 1 (DB0)—Offset 3000h..........................................................4893
18.1.121Door Bell 2 (DB1)—Offset 3004h..........................................................4894
18.1.122Door Bell 3 (DB2)—Offset 3008h..........................................................4894
18.1.123Door Bell 4 (DB3)—Offset 300Ch .........................................................4895
18.1.124Door Bell 5 (DB4)—Offset 3010h..........................................................4895
18.1.125Door Bell 6 (DB5)—Offset 3014h..........................................................4896
18.1.126Door Bell 7 (DB6)—Offset 3018h..........................................................4896
18.1.127Door Bell 8 (DB7)—Offset 301Ch .........................................................4897
18.1.128Door Bell 9 (DB8)—Offset 3020h..........................................................4897
18.1.129Door Bell 10 (DB9)—Offset 3024h ........................................................4898
18.1.130Door Bell 11 (DB10)—Offset 3028h ......................................................4898
18.1.131Door Bell 12 (DB11)—Offset 302Ch ......................................................4899
18.1.132Door Bell 13 (DB12)—Offset 3030h ......................................................4900
18.1.133Door Bell 14 (DB13)—Offset 3034h ......................................................4900
18.1.134Door Bell 15 (DB14)—Offset 3038h ......................................................4901
18.1.135Door Bell 16 (DB15)—Offset 303Ch ......................................................4901
18.1.136Door Bell 17 (DB16)—Offset 3040h ......................................................4902
18.1.137Door Bell 18 (DB17)—Offset 3044h ......................................................4902
18.1.138Door Bell 19 (DB18)—Offset 3048h ......................................................4903
18.1.139Door Bell 20 (DB19)—Offset 304Ch ......................................................4903
18.1.140Door Bell 21 (DB20)—Offset 3050h ......................................................4904
18.1.141Door Bell 22 (DB21)—Offset 3054h ......................................................4904
18.1.142Door Bell 23 (DB22)—Offset 3058h ......................................................4905
18.1.143Door Bell 24 (DB23)—Offset 305Ch ......................................................4906

334818 117
 18.1.144Door Bell 25 (DB24)—Offset 3060h...................................................... 4906
18.1.145Door Bell 26 (DB25)—Offset 3064h...................................................... 4907
18.1.146Door Bell 27 (DB26)—Offset 3068h...................................................... 4907
18.1.147Door Bell 28 (DB27)—Offset 306Ch ..................................................... 4908
18.1.148Door Bell 29 (DB28)—Offset 3070h...................................................... 4908
18.1.149Door Bell 30 (DB29)—Offset 3074h...................................................... 4909
18.1.150Door Bell 31 (DB30)—Offset 3078h...................................................... 4909
18.1.151Door Bell 32 (DB31)—Offset 307Ch ..................................................... 4910
18.1.152Door Bell 32 (DB32)—Offset 3080h...................................................... 4910
18.1.153XECP_SUPP_USB2_0 (XECP_SUPP_USB2_0)—Offset 8000h .................... 4911
18.1.154XECP_SUPP_USB2_1 (XECP_SUPP_USB2_1)—Offset 8004h .................... 4912
18.1.155XECP_SUPP_USB2_2 (XECP_SUPP_USB2_2)—Offset 8008h .................... 4912
18.1.156XECP_SUPP_USB2_3 (Full Speed) (XECP_SUPP_USB2_3)—Offset 8010h .. 4913
18.1.157XECP_SUPP_USB2_4 (Low Speed) (XECP_SUPP_USB2_4)—Offset 8014h .. 4914
18.1.158XECP_SUPP_USB2_5 (High Speed) (XECP_SUPP_USB2_5)—Offset 8018h . 4914
18.1.159XECP_SUPP_USB3_0 (XECP_SUPP_USB3_0)—Offset 8020h .................... 4915
18.1.160XECP_SUPP_USB3_1 (XECP_SUPP_USB3_1)—Offset 8024h .................... 4916
18.1.161XECP_SUPP_USB3_2 (XECP_SUPP_USB3_2)—Offset 8028h .................... 4916
18.1.162XECP_SUPP_USB3_3 (XECP_SUPP_USB3_3)—Offset 8030h .................... 4917
18.1.163XECP_SUPP_USB3_4 (XECP_SUPP_USB3_4)—Offset 8034h .................... 4917
18.1.164XECP_SUPP_USB3_5 (XECP_SUPP_USB3_5)—Offset 8038h .................... 4918
18.1.165XECP_SUPP_USB3_6 (XECP_SUPP_USB3_6)—Offset 803Ch .................... 4919
18.1.166XECP_SUPP_USB3_7 (XECP_SUPP_USB3_7)—Offset 8040h .................... 4919
18.1.167XECP_SUPP_USB3_8 (XECP_SUPP_USB3_8)—Offset 8044h .................... 4920
18.1.168XECP_SUPP_USB3_9 (XECP_SUPP_USB3_9)—Offset 8048h .................... 4921
18.1.169Host Controller Capability (HOST_CTRL_CAP_REG)—Offset 8070h ........... 4921
18.1.170Override EP Flow Control (HOST_CLR_MASK_REG)—Offset 8078h............ 4922
18.1.171Clear Active IN EP ID Control (HOST_CLR_IN_EP_VALID_REG)—Offset 807Ch ..
4923
18.1.172Clear Poll Mask Control (HOST_CLR_PMASK_REG)—Offset 8080h ............ 4923
18.1.173Host Control Scheduler (HOST_CTRL_SCH_REG)—Offset 8094h............... 4924
18.1.174Global Port Control (HOST_CTRL_PORT_CTRL)—Offset 80A0h ................. 4925
18.1.175PGCB Control (PGCBCTRL_REG)—Offset 80A8h ..................................... 4926
18.1.176D0I3 Control (DOI3CTRL_REG)—Offset 80ACh ...................................... 4929
18.1.177HOST_CTRL_MISC_REG (HOST_CTRL_MISC_REG)—Offset 80B0h............ 4930
18.1.178HOST_CTRL_MISC_REG2 (HOST_CTRL_MISC_REG2)—Offset 80B4h ........ 4932
18.1.179SSPE_REG (SSPE_REG)—Offset 80B8h................................................. 4934
18.1.180(SSPITPE)—Offset 80BCh ................................................................... 4934
18.1.181AUX Reset Control (AUX_CTRL_REG)—Offset 80C0h .............................. 4935
18.1.182Super Speed Bandwidth Overload (HOST_BW_OV_SS_REG)—Offset 80C4h .....
4937
18.1.183High Speed TT Bandwidth Overload (HOST_BW_OV_HS_REG)—Offset 80C8h ...
4938
18.1.184Bandwidth Overload Full Low Speed (HOST_BW_OV_FS_LS_REG)—Offset
80CCh............................................................................................... 4939
18.1.185System Bandwidth Overload (HOST_BW_OV_SYS_REG)—Offset 80D0h .... 4939
18.1.186Scheduler Async Delay (HOST_CTRL_SCH_ASYNC_DELAY_REG)—Offset 80D4h
4940
18.1.187DEVICE MODE CONTROL REG 0 (DUAL_ROLE_CFG_REG0)—Offset 80D8h . 4941
18.1.188DEVICE MODE CONTROL REG 1 (DUAL_ROLE_CFG_REG1)—Offset 80DCh. 4943
18.1.189AUX Power Management Control (AUX_CTRL_REG1)—Offset 80E0h ......... 4944
18.1.190Battery Charge (BATTERY_CHARGE_REG)—Offset 80E4h ........................ 4946
18.1.191Port Watermark (HOST_CTRL_WATERMARK_REG)—Offset 80E8h ............ 4947
18.1.192SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG)—Offset 80ECh ..
4947

118 334818
 18.1.193USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1)—Offset 80F0h ..4949
18.1.194USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2)—Offset 80F4h ..4951
18.1.195USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3)—Offset 80F8h ..4952
18.1.196USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4)—Offset 80FCh ..4952
18.1.197Bandwidth Calc Control (HOST_CTRL_BW_CTRL_REG)—Offset 8100h .......4953
18.1.198Host Interface Control (HOST_IF_CTRL_REG)—Offset 8108h ...................4953
18.1.199Bandwidth Overload Burst (HOST_BW_OV_BURST_REG)—Offset 810Ch ....4954
18.1.200USB Max Bandwidth Control 4 (HOST_CTRL_BW_MAX_REG)—Offset 8128h ......
4955
18.1.201USB2 Linestate Debug (LINESTATE_DEBUG_REG)—Offset 8130h .............4955
18.1.202USB2 Protocol Gap Timer (USB2_PROTOCOL_GAP_TIMER_REG)—Offset 8134h .
4956
18.1.203USB2 Protocol Bus Timeout Timer (USB2_PROTOCOL_BTO_TIMER_REG)—Offset
813Ch ...............................................................................................4957
18.1.204Power Scheduler Control-0 (PWR_SCHED_CTRL0)—Offset 8140h .............4958
18.1.205Power Scheduler Control-2 (PWR_SCHED_CTRL2)—Offset 8144h .............4958
18.1.206AUX Power Management Control (AUX_CTRL_REG2)—Offset 8154h ..........4959
18.1.207USB2 PHY Power Management Control (USB2_PHY_PMC)—Offset 8164h ...4962
18.1.208USB Power Gating Control (USB_PGC)—Offset 8168h .............................4963
18.1.209xHCI Aux Clock Control Register (XHCI_AUX_CCR)—Offset 816Ch ............4964
18.1.210USB LPM Parameters (USB_LPM_PARAM)—Offset 8170h .........................4966
18.1.211xHC Latency Tolerance Parameters - LTV Control (XLTP_LTV1)—Offset 8174h...
4967
18.1.212xHC Latency Tolerance Parameters LTV Control 2 (XLTP_LTV2)—Offset 8178h ..
4968
18.1.213xHC Latency Tolerance Parameters - High Idle Time Control (XLTP_HITC)—Offset
817Ch ...............................................................................................4969
18.1.214xHC Latency Tolerance Parameters - Medium Idle Time Control (XLTP_MITC)—
Offset 8180h ......................................................................................4970
18.1.215xHC Latency Tolerance Parameters Low Idle Time Control (XLTP_LITC)—Offset
8184h................................................................................................4971
18.1.216HOST_CTRL_BW_MAX3_REG (HOST_CTRL_BW_MAX3_REG)—Offset 8188h......
4971
18.1.217PDDIS_REG (PDDIS_REG)—Offset 8198h ..............................................4972
18.1.218LFPS_PM_CTRL_REG (LFPS_PM_CTRL_REG)—Offset 81A0h .....................4972
18.1.219U2PDM (U2PDM)—Offset 81A4h ...........................................................4973
18.1.220U2PCM (U2PCM)—Offset 81A8h ...........................................................4973
18.1.221U3PDM (U3PDM)—Offset 81ACh...........................................................4974
18.1.222U3PCM (U3PCM)—Offset 81B0h ...........................................................4974
18.1.223THRM_HOST_CTRL_REG2 (THRM_HOST_CTRL_REG2)—Offset 81B4h .......4975
18.1.224(D0i2_CTRL_REG)—Offset 81BCh.........................................................4975
18.1.225 (D0i2_SCH_ALARM_CTRL_REG)—Offset 81C0h .....................................4977
18.1.226 (USB2PMCTRL_REG)—Offset 81C4h ....................................................4978
18.1.227ECC_PARITY_ERROR_LOG_REG (ECC_PARITY_ERROR_LOG_REG)—Offset
83F8h................................................................................................4980
18.1.228ECC_POISONING_CTRL_REG (ECC_POISONING_CTRL_REG)—Offset 83FCh......
4982
18.1.229USB2_PORT_STATE_REG (USB2_PORT_STATE_REG)—Offset 8400h .........4983
18.1.230USB3_PORT_STATE_REG (USB3_PORT_STATE_REG)—Offset 8408h .........4984
18.1.231FUS1_REG (FUS1_REG)—Offset 8410h .................................................4984
18.1.232FUS2_REG (FUS2_REG)—Offset 8414h .................................................4985
18.1.233FUS3_REG (FUS3_REG)—Offset 8418h .................................................4986
18.1.234STRAP1_REG (STRAP1_REG)—Offset 841Ch ..........................................4986
18.1.235STRAP3_REG (STRAP3_REG)—Offset 8424h ..........................................4987
18.1.236XECP_CMDM_STS0 (XECP_CMDM_STS0)—Offset 8448h..........................4988
18.1.237XECP_CMDM_STS1 (XECP_CMDM_STS1)—Offset 844Ch .........................4989

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 18.1.238XECP_CMDM_STS2 (XECP_CMDM_STS2)—Offset 8450h ......................... 4990
18.1.239XECP_CMDM_STS3 (XECP_CMDM_STS3)—Offset 8454h ......................... 4990
18.1.240XECP_CMDM_STS4 (XECP_CMDM_STS4)—Offset 8458h ......................... 4991
18.1.241XECP_CMDM_STS5 (XECP_CMDM_STS5)—Offset 845Ch ......................... 4991
18.1.242AUX Power PHY Reset (UPORTS_PON_RST_REG)—Offset 8460h .............. 4992
18.1.243Latency Tolerance Control 0 (HOST_IF_LAT_TOL_CTRL_REG0)—Offset 8464h ..
4992
18.1.244USB Legacy Support Capability (USBLEGSUP)—Offset 846Ch .................. 4993
18.1.245USB Legacy Support Control Status (USBLEGCTLSTS)—Offset 8470h ....... 4994
18.1.246Port Disable Override capability register (PDO_CAPABILITY)—Offset 84F4h4995
18.1.247USB2 Port Disable Override (USB2PDO)—Offset 84F8h ........................... 4995
18.1.248USB3 Port Disable Override (USB3PDO)—Offset 84FCh........................... 4996
18.1.249HW state capability register (HW_STATE_CAPABILITY)—Offset 8500h ...... 4996
18.1.250HW state register 1 (HW_STATE_REG1)—Offset 8504h........................... 4997
18.1.251HW state register 2 (HW_STATE_REG2)—Offset 8508h........................... 4997
18.1.252HW state register 3 (HW_STATE_REG3)—Offset 850Ch .......................... 4998
18.1.253HW state register 4 (HW_STATE_REG4)—Offset 8510h........................... 4998
18.1.254CONFIG mirror capability register (CONFIG_MIRROR_CAPABILITY)—Offset
8600h ............................................................................................... 4999
18.1.255Command (CMD_MMIO)—Offset 8604h ................................................ 4999
18.1.256Device Status (STS_MMIO)—Offset 8606h ............................................ 5001
18.1.257Revision ID (RID_MMIO)—Offset 8608h ............................................... 5002
18.1.258Programming Interface (PI_MMIO)—Offset 8609h.................................. 5002
18.1.259Sub Class Code (SCC_MMIO)—Offset 860Ah ......................................... 5003
18.1.260Base Class Code (BCC_MMIO)—Offset 860Bh ........................................ 5003
18.1.261Master Latency Timer (MLT_MMIO)—Offset 860Dh................................. 5003
18.1.262Header Type (HT_MMIO)—Offset 860Eh ............................................... 5004
18.1.263Memory Base Address (MBAR_MMIO)—Offset 8610h .............................. 5004
18.1.264USB Subsystem Vendor ID (SSVID_MMIO)—Offset 862Ch ...................... 5005
18.1.265USB Subsystem ID (SSID_MMIO)—Offset 862Eh ................................... 5005
18.1.266Capabilities Pointer (CAP_PTR_MMIO)—Offset 8634h.............................. 5006
18.1.267Interrupt Line (ILINE_MMIO)—Offset 863Ch.......................................... 5006
18.1.268Interrupt Pin (IPIN_MMIO)—Offset 863Dh ............................................ 5007
18.1.269XHC System Bus Configuration 1 (XHCC1_MMIO)—Offset 8640h ............. 5007
18.1.270Clock Gating (XHCLKGTEN_MMIO)—Offset 8650h .................................. 5009
18.1.271Audio Time Synchronization (AUDSYNC_MMIO)—Offset 8658h ................ 5012
18.1.272Serial Bus Release Number (SBRN_MMIO)—Offset 8660h ....................... 5013
18.1.273Frame Length Adjustment (FLADJ_MMIO)—Offset 8661h ........................ 5013
18.1.274Best Effort Service Latency (BESL_MMIO)—Offset 8662h ........................ 5014
18.1.275PCI Power Management Capability ID (PM_CID_MMIO)—Offset 8670h ...... 5015
18.1.276Next Item Pointer #1 (PM_NEXT_MMIO)—Offset 8671h .......................... 5015
18.1.277Power Management Capabilities (PM_CAP_MMIO)—Offset 8672h ............. 5016
18.1.278Power Management Control/Status (PM_CS_MMIO)—Offset 8674h........... 5017
18.1.279Message Signaled Interrupt CID (MSI_CID_MMIO)—Offset 8680h ............ 5018
18.1.280Next item pointer (MSI_NEXT_MMIO)—Offset 8681h.............................. 5019
18.1.281Message Signaled Interrupt Message Control (MSI_MCTL_MMIO)—Offset 8682h
5019
18.1.282Message Signaled Interrupt Message Address (MSI_MAD_MMIO)—Offset 8684h
5020
18.1.283Message Signaled Interrupt Upper Address (MSI_MUAD_MMIO)—Offset 8688h .
5021
18.1.284Message Signaled Interrupt Message Data (MSI_MD_MMIO)—Offset 868Ch .....
5021
18.1.285Device Idle Capability (DEVIDLE_MMIO)—Offset 8690h .......................... 5022
18.1.286Vendor Specific Header (VSHDR_MMIO)—Offset 8694h .......................... 5022

120 334818
 18.1.287SW LTR POINTER (SWLTRPTR_MMIO)—Offset 8698h ..............................5023
18.1.288Device Idle Pointer Register (DEVIDLEPTR_MMIO)—Offset 869Ch .............5024
18.1.289Device Idle Power ON Latency (DEVIDLEPOL_MMIO)—Offset 86A0h..........5025
18.1.290High Speed Configuration 2 (HSCFG2_MMIO)—Offset 86A4h....................5026
18.1.291XHCI USB2 Overcurrent Pin Mapping 1 (U2OCM1_MMIO)—Offset 86B0h....5027
18.1.292XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM2_MMIO)—Offset 86B4h....5028
18.1.293XHCI USB3 Overcurrent Pin Mapping 1 (U3OCM1_MMIO)—Offset 86D0h ...5028
18.1.294XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM2_MMIO)—Offset 86D4h ...5029
18.1.295XHCC3 (XHCC3_MMIO)—Offset 86FCh ..................................................5029
18.1.296Debug Capability ID Register (DCID)—Offset 8700h ...............................5030
18.1.297Debug Capability Doorbell Register (DCDB)—Offset 8704h ......................5031
18.1.298Debug Capability Event Ring Segment Table Size Register (DCERSTSZ)—Offset
8708h................................................................................................5031
18.1.299Debug Capability Event Ring Segment Table Base Address Register
(DCERSTBA)—Offset 8710h ..................................................................5032
18.1.300Debug Capability Event Ring Dequeue Pointer Register (DCERDP)—Offset 8718h
5032
18.1.301Debug Capability Control Register (DCCTRL)—Offset 8720h .....................5033
18.1.302Debug Capability Status Register (DCST)—Offset 8724h .........................5034
18.1.303Debug Capability Port Status and Control Register (DCPORTSC)—Offset 8728h .
5035
18.1.304Debug Capability Context Pointer Register (DCCP)—Offset 8730h .............5037
18.1.305Debug Capability Device Descriptor Info Register 1 (DCDDI1)—Offset 8738h ....
5037
18.1.306Debug Capability Device Descriptor Info Register 2 (DCDDI2)—Offset 873Ch ....
5038
18.1.307Debug Capability Descriptor Parameters (DCDP)—Offset 8740h................5038
18.1.308 .......................................................................................................5039
18.1.309Debug Device Control ODMA (DBGDEV_CTRL_ODMA_REG)—Offset 8748h .5039
18.1.310DBC Control Register 1 (DBCCTL_REG)—Offset 8760h ............................5040
18.1.311(PORT1_PROFILE_ATTRIBUTES_REG0)—Offset 890Ch ............................5041
18.1.312(PORT1_PROFILE_ATTRIBUTES_REG1)—Offset 8910h ............................5041
18.1.313(PORT1_PROFILE_ATTRIBUTES_REG2)—Offset 8914h ............................5042
18.1.314(PORT1_PROFILE_ATTRIBUTES_REG3)—Offset 8918h ............................5043
18.1.315(PORT1_PROFILE_ATTRIBUTES_REG4)—Offset 891Ch ............................5043
18.1.316(PORT1_PROFILE_ATTRIBUTES_REG5)—Offset 8920h ............................5044
18.1.317(PORT1_PROFILE_ATTRIBUTES_REG6)—Offset 8924h ............................5045
18.1.318(PORT1_PROFILE_ATTRIBUTES_REG7)—Offset 8928h ............................5045
18.1.319(PORT1_PROFILE_ATTRIBUTES_REG8)—Offset 892Ch ............................5046
18.1.320(PORT1_PROFILE_ATTRIBUTES_REG9)—Offset 8930h ............................5047
18.1.321(PORT1_PROFILE_ATTRIBUTES_REG10)—Offset 8934h...........................5047
18.1.322(PORT1_PROFILE_ATTRIBUTES_REG11)—Offset 8938h...........................5048
18.1.323(PORT1_PROFILE_ATTRIBUTES_REG12)—Offset 893Ch...........................5049
18.1.324(PORT1_PROFILE_ATTRIBUTES_REG13)—Offset 8940h...........................5049
18.1.325(PORT1_PROFILE_ATTRIBUTES_REG14)—Offset 8944h...........................5050
18.1.326(PORT1_PROFILE_ATTRIBUTES_REG15)—Offset 8948h...........................5051
18.1.327(PORT1_PROFILE_ATTRIBUTES_REG16)—Offset 894Ch...........................5051
18.1.328(PORT1_PROFILE_ATTRIBUTES_REG17)—Offset 8950h...........................5052
18.1.329(PORT1_PROFILE_ATTRIBUTES_REG18)—Offset 8954h...........................5053
18.1.330(PORT1_PROFILE_ATTRIBUTES_REG19)—Offset 8958h...........................5053
18.1.331(PORT1_PROFILE_ATTRIBUTES_REG20)—Offset 895Ch...........................5054
18.1.332(PORT1_PROFILE_ATTRIBUTES_REG21)—Offset 8960h...........................5055
18.1.333(PORT1_PROFILE_ATTRIBUTES_REG22)—Offset 8964h...........................5055
18.1.334(PORT1_PROFILE_ATTRIBUTES_REG23)—Offset 8968h...........................5056
18.1.335(PORT1_PROFILE_ATTRIBUTES_REG24)—Offset 896Ch...........................5057

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 18.1.336(PORT1_PROFILE_ATTRIBUTES_REG25)—Offset 8970h .......................... 5057
18.1.337(PORT1_PROFILE_ATTRIBUTES_REG26)—Offset 8974h .......................... 5058
18.1.338(PORT1_PROFILE_ATTRIBUTES_REG27)—Offset 8978h .......................... 5059
18.1.339(PORT1_PROFILE_ATTRIBUTES_REG28)—Offset 897Ch .......................... 5059
18.1.340(PORT1_PROFILE_ATTRIBUTES_REG29)—Offset 8980h .......................... 5060
18.1.341(PORT1_PROFILE_ATTRIBUTES_REG30)—Offset 8984h .......................... 5061
18.1.342(PORT1_PROFILE_ATTRIBUTES_REG31)—Offset 8988h .......................... 5061
18.1.343(PORT1_PROFILE_ATTRIBUTES_REG32)—Offset 898Ch .......................... 5062
18.1.344(PORT1_PROFILE_ATTRIBUTES_REG33)—Offset 8990h .......................... 5063
18.1.345(PORT1_PROFILE_ATTRIBUTES_REG34)—Offset 8994h .......................... 5063
18.1.346(PORT1_PROFILE_ATTRIBUTES_REG35)—Offset 8998h .......................... 5064
18.1.347(PORT1_PROFILE_ATTRIBUTES_REG36)—Offset 899Ch .......................... 5065
18.1.348(PORT1_PROFILE_ATTRIBUTES_REG37)—Offset 89A0h .......................... 5065
18.1.349(PORT1_PROFILE_ATTRIBUTES_REG38)—Offset 89A4h .......................... 5066
18.1.350(PORT1_PROFILE_ATTRIBUTES_REG39)—Offset 89A8h .......................... 5067
18.1.351(PORT1_PROFILE_ATTRIBUTES_REG40)—Offset 89ACh .......................... 5067
18.1.352(PORT1_PROFILE_ATTRIBUTES_REG41)—Offset 89B0h .......................... 5068
18.1.353(PORT1_PROFILE_ATTRIBUTES_REG42)—Offset 89B4h .......................... 5069
18.1.354(PORT1_PROFILE_ATTRIBUTES_REG43)—Offset 89B8h .......................... 5069
18.1.355(PORT1_PROFILE_ATTRIBUTES_REG44)—Offset 89BCh .......................... 5070
18.1.356(PORT1_PROFILE_ATTRIBUTES_REG45)—Offset 89C0h .......................... 5071
18.1.357(PORT1_PROFILE_ATTRIBUTES_REG46)—Offset 89C4h .......................... 5071
18.1.358(PORT1_PROFILE_ATTRIBUTES_REG47)—Offset 89C8h .......................... 5072
18.1.359(PORT1_PROFILE_ATTRIBUTES_REG48)—Offset 89CCh .......................... 5073
18.1.360(PORT1_PROFILE_ATTRIBUTES_REG49)—Offset 89D0h .......................... 5073
18.1.361(PORT1_PROFILE_ATTRIBUTES_REG50)—Offset 89D4h .......................... 5074
18.1.362(PORT1_PROFILE_ATTRIBUTES_REG51)—Offset 89D8h .......................... 5075
18.1.363(PORT1_PROFILE_ATTRIBUTES_REG52)—Offset 89DCh.......................... 5075
18.1.364(PORT1_PROFILE_ATTRIBUTES_REG53)—Offset 89E0h .......................... 5076
18.1.365(PORT1_PROFILE_ATTRIBUTES_REG54)—Offset 89E4h .......................... 5077
18.1.366(PORT1_PROFILE_ATTRIBUTES_REG55)—Offset 89E8h .......................... 5077
18.1.367(PORT1_PROFILE_ATTRIBUTES_REG56)—Offset 89ECh .......................... 5078
18.1.368(PORT1_PROFILE_ATTRIBUTES_REG57)—Offset 89F0h .......................... 5079
18.1.369(PORT1_PROFILE_ATTRIBUTES_REG58)—Offset 89F4h .......................... 5079
18.1.370(PORT1_PROFILE_ATTRIBUTES_REG59)—Offset 89F8h .......................... 5080
18.1.371(PORT1_PROFILE_ATTRIBUTES_REG60)—Offset 89FCh .......................... 5081
18.1.372(PORT1_PROFILE_ATTRIBUTES_REG61)—Offset 8A00h .......................... 5081
18.1.373(PORT1_PROFILE_ATTRIBUTES_REG62)—Offset 8A04h .......................... 5082
18.1.374(PORT1_PROFILE_ATTRIBUTES_REG63)—Offset 8A08h .......................... 5083
18.1.375GLOBAL_TIME_SYNC_CAP_REG (GLOBAL_TIME_SYNC_CAP_REG)—Offset
8E10h ............................................................................................... 5083
18.1.376GLOBAL_TIME_SYNC_CTRL_REG (GLOBAL_TIME_SYNC_CTRL_REG)—Offset
8E14h ............................................................................................... 5084
18.1.377MICROFRAME_TIME_REG (MICROFRAME_TIME_REG)—Offset 8E18h ........ 5085
18.1.378GLOBAL_TIME_LOW_REG (GLOBAL_TIME_LOW_REG)—Offset 8E20h ....... 5085
18.1.379GLOBAL_TIME_HI_REG (GLOBAL_TIME_HI_REG)—Offset 8E24h.............. 5086
18.1.380Debug Status Capability Register (DEBUG_STATUS_CAPABILITY_REG)—Offset
8E58h ............................................................................................... 5087
18.1.381Host Ctrl USB3 Soft Error Count Register 1
(HOST_CTRL_USB3_ERR_COUNT_REG1)—Offset 8E5Ch .......................... 5087
18.1.382Host Ctrl USB3 Soft Error Count Register 2
(HOST_CTRL_USB3_ERR_COUNT_REG2)—Offset 8E60h........................... 5088
18.1.383Host Ctrl USB3 Soft Error Count Register 3
(HOST_CTRL_USB3_ERR_COUNT_REG3)—Offset 8E64h........................... 5088

122 334818
 18.1.384Host Ctrl USB3 Soft Error Count Register 4
(HOST_CTRL_USB3_ERR_COUNT_REG4)—Offset 8E68h ...........................5089
18.1.385Host Ctrl USB3 Soft Error Count Register 5
(HOST_CTRL_USB3_ERR_COUNT_REG5)—Offset 8E6Ch ...........................5090
18.1.386Host Ctrl USB3 Soft Error Count Register 6
(HOST_CTRL_USB3_ERR_COUNT_REG6)—Offset 8E70h ...........................5090
18.1.387Host Ctrl USB3 Soft Error Count Register 7
(HOST_CTRL_USB3_ERR_COUNT_REG7)—Offset 8E74h ...........................5091
18.1.388IOSFCTL - Control Register (IOSFCTL)—Offset 0h...................................5091
18.1.389Power Management Control Register (PMCTL)—Offset 1D0h.....................5092
18.1.390PCI Configuration Control 1 Register (PCICFGCTR1)—Offset 200h.............5093
18.1.391c73usb280_USB2 PER PORT (USB2_PER_PORT_PP0)—Offset 4100h .........5094
18.1.392GLB ADP VBUS COMP REG (GLB_ADP_VBUS_COMP_REG)—Offset 402Bh ..5097
18.1.393c73usb280_USB2 COMPBG (USB2_COMPBG)—Offset 7F04h ....................5099
18.1.394CONFIG_3—Offset 7014h....................................................................5103
18.1.395DBC_GP2_IN_PAYLOAD_BP_LOW—Offset 1Ch .......................................5104
18.1.396DBC_GP2_IN_PAYLOAD_BP_HI—Offset 20h...........................................5104
18.1.397DBC_GP2_IN_PAYLOAD_QUALIFIERS—Offset 24h ..................................5104
18.1.398DBC_GP2_IN_STATUS_QUALIFIERS—Offset 34h ....................................5105
18.1.399DBC_GP2_IN_STATUS_BP_LOW—Offset 2Ch .........................................5105
18.1.400DBC_GP2_IN_STATUS_BP_HI—Offset 30h ............................................5106
18.1.401Host Control IDMA (HOST_CTRL_IDMA_REG)—Offset 809Ch....................5106
18.1.402Host Control Transfer Manager (HOST_CTRL_TRM_REG2) —Offset 8110h..5108
18.1.403Command Manager Control 1 (XECP_CMDM_CTRL_REG1) —Offset 818Ch .5111
18.1.404Command Manager Control 2 (XECP_CMDM_CTRL_REG2) —Offset 8190h .5113
18.1.405Command Manager Control 3 (XECP_CMDM_CTRL_REG3) —Offset 8194h .5115
18.1.406Power Control Enable (PCE_REG) —Offset 00A2h ...................................5116
18.1.407GEN_REGRW4 —Offset 00BCh .............................................................5116
18.2 Registers Summary ........................................................................................5117
18.2.1 Vendor ID (VID)—Offset 0h ..................................................................5118
18.2.2 Device ID (DID)—Offset 2h...................................................................5119
18.2.3 Command (CMD)—Offset 4h .................................................................5119
18.2.4 Device Status (STS)—Offset 6h .............................................................5120
18.2.5 Revision ID (RID)—Offset 8h ................................................................5122
18.2.6 Programming Interface (PI)—Offset 9h...................................................5122
18.2.7 Sub Class Code (SCC)—Offset Ah ..........................................................5122
18.2.8 Base Class Code (BCC)—Offset Bh .........................................................5123
18.2.9 Master Latency Timer (MLT)—Offset Dh..................................................5123
18.2.10Header Type (HT)—Offset Eh ................................................................5123
18.2.11Memory Base Address (MBAR)—Offset 10h .............................................5124
18.2.12USB Subsystem Vendor ID (SSVID)—Offset 2Ch......................................5125
18.2.13USB Subsystem ID (SSID)—Offset 2Eh ..................................................5125
18.2.14Capabilities Pointer (CAP_PTR)—Offset 34h.............................................5125
18.2.15Interrupt Line (ILINE)—Offset 3Ch.........................................................5126
18.2.16Interrupt Pin (IPIN)—Offset 3Dh............................................................5126
18.2.17XHC System Bus Configuration 1 (XHCC1)—Offset 40h.............................5127
18.2.18Clock Gating (XHCLKGTEN)—Offset 50h .................................................5128
18.2.19Audio Time Synchronization (AUDSYNC)—Offset 58h................................5131
18.2.20Serial Bus Release Number (SBRN)—Offset 60h ......................................5132
18.2.21Frame Length Adjustment (FLADJ)—Offset 61h .......................................5133
18.2.22Best Effort Service Latency (BESL)—Offset 62h .......................................5134
18.2.23PCI Power Management Capability ID (PM_CID)—Offset 70h .....................5134
18.2.24Next Item Pointer #1 (PM_NEXT)—Offset 71h .........................................5135
18.2.25Power Management Capabilities (PM_CAP)—Offset 72h.............................5135
18.2.26Power Management Control/Status (PM_CS)—Offset 74h ..........................5136

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 18.2.27Message Signaled Interrupt CID (MSI_CID)—Offset 80h........................... 5137
18.2.28Next item pointer (MSI_NEXT)—Offset 81h ............................................ 5138
18.2.29Message Signaled Interrupt Message Control (MSI_MCTL)—Offset 82h....... 5138
18.2.30Message Signaled Interrupt Message Address (MSI_MAD)—Offset 84h ....... 5139
18.2.31Message Signaled Interrupt Upper Address (MSI_MUAD)—Offset 88h ........ 5139
18.2.32Message Signaled Interrupt Message Data (MSI_MD)—Offset 8Ch ............. 5140
18.2.33Device Idle Capability (DEVIDLE)—Offset 90h ......................................... 5140
18.2.34Vendor Specific Header (VSHDR)—Offset 94h ......................................... 5141
18.2.35SW LTR POINTER (SWLTRPTR)—Offset 98h ............................................ 5142
18.2.36Device Idle Pointer Register (DEVIDLEPTR)—Offset 9Ch ........................... 5143
18.2.37Device Idle Power ON Latency (DEVIDLEPOL)—Offset A0h........................ 5143
18.2.38High Speed Configuration 2 (HSCFG2)—Offset A4h.................................. 5144
18.2.39XHCI USB2 Overcurrent Pin Mapping 1 (U2OCM1)—Offset B0h.................. 5146
18.2.40XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM2)—Offset B4h.................. 5146
18.2.41XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM3)—Offset B8h.................. 5147
18.2.42XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM4)—Offset BCh ................. 5147
18.2.43XHCI USB3 Overcurrent Pin Mapping 1 (U3OCM1)—Offset D0h ................. 5148
18.2.44XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM2)—Offset D4h ................. 5148
18.2.45XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM3)—Offset D8h ................. 5149
18.2.46XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM4)—Offset DCh ................. 5149
18.2.47XHCC3 (XHCC3)—Offset FCh ................................................................ 5149
18.3 Registers Summary........................................................................................ 5150
18.3.1 DBC_GP2_OUT_PAYLOAD_BP_LOW (DBC_GP2_OUT_PAYLOAD_BP_LOW)—
Offset 0h ........................................................................................... 5158
18.3.2 DBC_GP2_OUT_PAYLOAD_BP_HI (DBC_GP2_OUT_PAYLOAD_BP_HI)—Offset 4h
5159
18.3.3 DBC_GP2_OUT_PAYLOAD_QUALIFIERS
(DBC_GP2_OUT_PAYLOAD_QUALIFIERS)—Offset 8h................................ 5159
18.3.4 DBC_GP2_OUT_PAYLOAD_TRANSFER_LENGTH
(DBC_GP2_OUT_PAYLOAD_TRANSFER_LENGTH)—Offset Ch ..................... 5160
18.3.5 DBC_GP2_OUT_STATUS_BP_LOW (DBC_GP2_OUT_STATUS_BP_LOW)—Offset
10h................................................................................................... 5161
18.3.6 DBC_GP2_OUT_STATUS_BP_HI (DBC_GP2_OUT_STATUS_BP_HI)—Offset 14h ..
5161
18.3.7 DBC_GP2_OUT_STATUS_QUALIFIERS (DBC_GP2_OUT_STATUS_QUALIFIERS)—
Offset 18h ......................................................................................... 5162
18.3.8 DBC_GP2_IN_PAYLOAD_BP_LOW (DBC_GP2_IN_PAYLOAD_BP_LOW)—Offset
1Ch .................................................................................................. 5163
18.3.9 DBC_GP2_IN_PAYLOAD_BP_HI (DBC_GP2_IN_PAYLOAD_BP_HI)—Offset 20h ....
5163
18.3.10DBC_GP2_IN_PAYLOAD_QUALIFIERS (DBC_GP2_IN_PAYLOAD_QUALIFIERS)—
Offset 24h ......................................................................................... 5164
18.3.11DBC_GP2_IN_PAYLOAD_TRANSFER_LENGTH
(DBC_GP2_IN_PAYLOAD_TRANSFER_LENGTH)—Offset 28h ...................... 5165
18.3.12DBC_GP2_IN_STATUS_BP_LOW (DBC_GP2_IN_STATUS_BP_LOW)—Offset 2Ch .
5165
18.3.13DBC_GP2_IN_STATUS_BP_HI (DBC_GP2_IN_STATUS_BP_HI)—Offset 30h. 5166
18.3.14DBC_GP2_IN_STATUS_QUALIFIERS (DBC_GP2_IN_STATUS_QUALIFIERS)—
Offset 34h ......................................................................................... 5167
18.3.15DBC_TRACE_IN_PAYLOAD_BP_LOW (DBC_TRACE_IN_PAYLOAD_BP_LOW)—
Offset 50h ......................................................................................... 5167
18.3.16DBC_TRACE_IN_PAYLOAD_BP_HI (DBC_TRACE_IN_PAYLOAD_BP_HI)—Offset
54h................................................................................................... 5168
18.3.17DBC_TRACE_IN_PAYLOAD_QUALIFIERS
(DBC_TRACE_IN_PAYLOAD_QUALIFIERS)—Offset 58h ............................. 5169

124 334818
 18.3.18DBC_TRACE_IN_PAYLOAD_TRASNFER_DOORBELL
(DBC_TRACE_IN_PAYLOAD_TRANSFER_DOORBELL)—Offset 5Ch ...............5169
18.3.19DBC_TRACE_IN_STATUS_BP_LOW (DBC_TRACE_IN_STATUS_BP_LOW)—Offset
60h ...................................................................................................5170
18.3.20DBC_TRACE_IN_STATUS_BP_HI (DBC_TRACE_IN_STATUS_BP_HI)—Offset 64h .
5171
18.3.21DBC_TRACE_IN_STATUS_QUALIFIERS
(DBC_TRACE_IN_STATUS_QUALIFIERS)—Offset 68h ...............................5171
18.3.22DBConEXI Capability Port Status and Control Register (DBC_EXI_DCPORTSC)—
Offset 88h ..........................................................................................5172
18.3.23DEBUG_SW_CONTROL_STATUS_REG (DEBUG_SW_CONTROL_STATUS_REG)—
Offset 100h ........................................................................................5174
18.3.24DEBUG_REQUEST_INFO_AND_STATUS_REG
(DEBUG_REQUEST_INFO_AND_STATUS_REG)—Offset 104h .....................5175
18.3.25DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_0)—Offset 108h ......
5177
18.3.26DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_1)—Offset 10Ch ......
5177
18.3.27DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_2)—Offset 110h ......
5178
18.3.28DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_3)—Offset 114h ......
5179
18.3.29DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_4)—Offset 118h ......
5179
18.3.30DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_5)—Offset 11Ch ......
5180
18.3.31DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_6)—Offset 120h ......
5181
18.3.32DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_7)—Offset 124h ......
5181
18.3.33DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_8)—Offset 128h ......
5182
18.3.34DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_9)—Offset 12Ch ......
5183
18.3.35DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_10)—Offset 130h.....
5183
18.3.36DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_11)—Offset 134h.....
5184
18.3.37DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_12)—Offset 138h.....
5185
18.3.38DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_13)—Offset 13Ch ....
5185
18.3.39DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_14)—Offset 140h.....
5186
18.3.40DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_15)—Offset 144h.....
5187
18.3.41DEBUG_RESPONSE_INFO_AND_STATUS_REG
(DEBUG_RESPONSE_INFO_AND_STATUS_REG)—Offset 148h ...................5187
18.3.42DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_0)—
Offset 180h ........................................................................................5188
18.3.43DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_1)—
Offset 184h ........................................................................................5189
18.3.44DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_2)—
Offset 188h ........................................................................................5189
18.3.45DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_3)—
Offset 18Ch ........................................................................................5190

334818 125
 18.3.46DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_4)—
Offset 190h........................................................................................ 5190
18.3.47DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_5)—
Offset 194h........................................................................................ 5191
18.3.48DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_6)—
Offset 198h........................................................................................ 5191
18.3.49DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_7)—
Offset 19Ch ....................................................................................... 5192
18.3.50DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_8)—
Offset 1A0h ....................................................................................... 5193
18.3.51DEBUG_RESPONSE_DATA_STACK (DEBUG_RESPONSE_DATA_STACK_REG_9)—
Offset 1A4h ....................................................................................... 5193
18.3.52DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_10)—Offset 1A8h ...................... 5194
18.3.53DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_11)—Offset 1ACh ...................... 5194
18.3.54DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_12)—Offset 1B0h ...................... 5195
18.3.55DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_13)—Offset 1B4h ...................... 5196
18.3.56DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_14)—Offset 1B8h ...................... 5196
18.3.57DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_15)—Offset 1BCh ...................... 5197
18.3.58DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_16)—Offset 1C0h ...................... 5197
18.3.59DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_17)—Offset 1C4h ...................... 5198
18.3.60DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_18)—Offset 1C8h ...................... 5199
18.3.61DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_19)—Offset 1CCh ...................... 5199
18.3.62DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_20)—Offset 1D0h ...................... 5200
18.3.63DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_21)—Offset 1D4h ...................... 5200
18.3.64DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_22)—Offset 1D8h ...................... 5201
18.3.65DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_23)—Offset 1DCh ...................... 5202
18.3.66DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_24)—Offset 1E0h....................... 5202
18.3.67DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_25)—Offset 1E4h....................... 5203
18.3.68DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_26)—Offset 1E8h....................... 5203
18.3.69DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_27)—Offset 1ECh ...................... 5204
18.3.70DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_28)—Offset 1F0h....................... 5205
18.3.71DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_29)—Offset 1F4h....................... 5205
18.3.72DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_30)—Offset 1F8h....................... 5206
18.3.73DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_31)—Offset 1FCh....................... 5206

126 334818
 18.3.74DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_32)—Offset 200h .......................5207
18.3.75DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_33)—Offset 204h .......................5208
18.3.76DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_34)—Offset 208h .......................5208
18.3.77DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_35)—Offset 20Ch .......................5209
18.3.78DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_36)—Offset 210h .......................5209
18.3.79DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_37)—Offset 214h .......................5210
18.3.80DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_38)—Offset 218h .......................5211
18.3.81DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_39)—Offset 21Ch .......................5211
18.3.82DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_40)—Offset 220h .......................5212
18.3.83DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_41)—Offset 224h .......................5212
18.3.84DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_42)—Offset 228h .......................5213
18.3.85DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_43)—Offset 22Ch .......................5214
18.3.86DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_44)—Offset 230h .......................5214
18.3.87DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_45)—Offset 234h .......................5215
18.3.88DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_46)—Offset 238h .......................5215
18.3.89DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_47)—Offset 23Ch .......................5216
18.3.90DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_48)—Offset 240h .......................5217
18.3.91DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_49)—Offset 244h .......................5217
18.3.92DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_50)—Offset 248h .......................5218
18.3.93DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_51)—Offset 24Ch .......................5218
18.3.94DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_52)—Offset 250h .......................5219
18.3.95DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_53)—Offset 254h .......................5220
18.3.96DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_54)—Offset 258h .......................5220
18.3.97DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_55)—Offset 25Ch .......................5221
18.3.98DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_56)—Offset 260h .......................5221
18.3.99DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_57)—Offset 264h .......................5222
18.3.100DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_58)—Offset 268h .......................5223
18.3.101DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_59)—Offset 26Ch .......................5223

334818 127
 18.3.102DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_60)—Offset 270h....................... 5224
18.3.103DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_61)—Offset 274h....................... 5224
18.3.104DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_62)—Offset 278h....................... 5225
18.3.105DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_63)—Offset 27Ch ...................... 5226
18.3.106DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_64)—Offset 280h....................... 5226
18.3.107DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_65)—Offset 284h....................... 5227
18.3.108DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_66)—Offset 288h....................... 5227
18.3.109DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_67)—Offset 28Ch ...................... 5228
18.3.110DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_68)—Offset 290h....................... 5229
18.3.111DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_69)—Offset 294h....................... 5229
18.3.112DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_70)—Offset 298h....................... 5230
18.3.113DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_71)—Offset 29Ch ...................... 5230
18.3.114DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_72)—Offset 2A0h ...................... 5231
18.3.115DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_73)—Offset 2A4h ...................... 5232
18.3.116DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_74)—Offset 2A8h ...................... 5232
18.3.117DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_75)—Offset 2ACh ...................... 5233
18.3.118DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_76)—Offset 2B0h ...................... 5233
18.3.119DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_77)—Offset 2B4h ...................... 5234
18.3.120DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_78)—Offset 2B8h ...................... 5235
18.3.121DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_79)—Offset 2BCh ...................... 5235
18.3.122DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_80)—Offset 2C0h ...................... 5236
18.3.123DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_81)—Offset 2C4h ...................... 5236
18.3.124DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_82)—Offset 2C8h ...................... 5237
18.3.125DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_83)—Offset 2CCh ...................... 5238
18.3.126DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_84)—Offset 2D0h ...................... 5238
18.3.127DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_85)—Offset 2D4h ...................... 5239
18.3.128DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_86)—Offset 2D8h ...................... 5239
18.3.129DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_87)—Offset 2DCh ...................... 5240

128 334818
 18.3.130DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_88)—Offset 2E0h .......................5241
18.3.131DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_89)—Offset 2E4h .......................5241
18.3.132DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_90)—Offset 2E8h .......................5242
18.3.133DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_91)—Offset 2ECh .......................5242
18.3.134DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_92)—Offset 2F0h .......................5243
18.3.135DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_93)—Offset 2F4h .......................5244
18.3.136DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_94)—Offset 2F8h .......................5244
18.3.137DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_95)—Offset 2FCh .......................5245
18.3.138DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_96)—Offset 300h .......................5245
18.3.139DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_97)—Offset 304h .......................5246
18.3.140DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_98)—Offset 308h .......................5247
18.3.141DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_99)—Offset 30Ch .......................5247
18.3.142DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_100)—Offset 310h .....................5248
18.3.143DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_101)—Offset 314h .....................5249
18.3.144DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_102)—Offset 318h .....................5249
18.3.145DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_103)—Offset 31Ch .....................5250
18.3.146DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_104)—Offset 320h .....................5251
18.3.147DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_105)—Offset 324h .....................5251
18.3.148DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_106)—Offset 328h .....................5252
18.3.149DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_107)—Offset 32Ch .....................5253
18.3.150DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_108)—Offset 330h .....................5253
18.3.151DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_109)—Offset 334h .....................5254
18.3.152DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_110)—Offset 338h .....................5255
18.3.153DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_111)—Offset 33Ch .....................5255
18.3.154DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_112)—Offset 340h .....................5256
18.3.155DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_113)—Offset 344h .....................5257
18.3.156DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_114)—Offset 348h .....................5257
18.3.157DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_115)—Offset 34Ch .....................5258

334818 129
 18.3.158DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_116)—Offset 350h ..................... 5259
18.3.159DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_117)—Offset 354h ..................... 5259
18.3.160DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_118)—Offset 358h ..................... 5260
18.3.161DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_119)—Offset 35Ch..................... 5261
18.3.162DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_120)—Offset 360h ..................... 5261
18.3.163DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_121)—Offset 364h ..................... 5262
18.3.164DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_122)—Offset 368h ..................... 5263
18.3.165DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_123)—Offset 36Ch..................... 5263
18.3.166DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_124)—Offset 370h ..................... 5264
18.3.167DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_125)—Offset 374h ..................... 5265
18.3.168DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_126)—Offset 378h ..................... 5265
18.3.169DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_127)—Offset 37Ch..................... 5266
18.3.170DEBUG_RESPONSE_HEADER_STACK_REG
(DEBUG_RESPONSE_HEADER_STACK_REG_0)—Offset 380h .................... 5267
18.3.171DEBUG_RESPONSE_HEADER_STACK_REG
(DEBUG_RESPONSE_HEADER_STACK_REG_1)—Offset 384h .................... 5267
18.3.172DEBUG_RESPONSE_HEADER_STACK_REG
(DEBUG_RESPONSE_HEADER_STACK_REG_2)—Offset 388h .................... 5268
18.4 Registers Summary........................................................................................ 5269
18.4.1 DCFG (DCFG)—Offset C700h ................................................................ 5272
18.4.2 DCTL (DCTL)—Offset C704h ................................................................. 5273
18.4.3 DEVTEN (DEVTEN)—Offset C708h ......................................................... 5274
18.4.4 DSTS (DSTS)—Offset C70Ch ................................................................ 5275
18.4.5 DGCMDPAR (DGCMDPAR)—Offset C710h ............................................... 5276
18.4.6 DGCMD (DGCMD)—Offset C714h .......................................................... 5277
18.4.7 DALEPENA (DALEPENA)—Offset C720h .................................................. 5277
18.4.8 DEPCMDPAR2_0 (DEPCMDPAR2_0)—Offset C800h .................................. 5278
18.4.9 DEPCMDPAR1_0 (DEPCMDPAR1_0)—Offset C804h .................................. 5278
18.4.10DEPCMDPAR0_0 (DEPCMDPAR0_0)—Offset C808h .................................. 5279
18.4.11DEPCMD_0 (DEPCMD_0)—Offset C80Ch................................................. 5279
18.4.12DEPCMDPAR2_1 (DEPCMDPAR2_1)—Offset C810h .................................. 5280
18.4.13DEPCMDPAR1_1 (DEPCMDPAR1_1)—Offset C814h .................................. 5281
18.4.14DEPCMDPAR0_1 (DEPCMDPAR0_1)—Offset C818h .................................. 5281
18.4.15DEPCMD_1 (DEPCMD_1)—Offset C81Ch................................................. 5282
18.4.16DEPCMDPAR2_2 (DEPCMDPAR2_2)—Offset C820h .................................. 5282
18.4.17DEPCMDPAR1_2 (DEPCMDPAR1_2)—Offset C824h .................................. 5283
18.4.18DEPCMDPAR0_2 (DEPCMDPAR0_2)—Offset C828h .................................. 5283
18.4.19DEPCMD_2 (DEPCMD_2)—Offset C82Ch................................................. 5284
18.4.20DEPCMDPAR2_3 (DEPCMDPAR2_3)—Offset C830h .................................. 5285
18.4.21DEPCMDPAR1_3 (DEPCMDPAR1_3)—Offset C834h .................................. 5285
18.4.22DEPCMDPAR0_3 (DEPCMDPAR0_3)—Offset C838h .................................. 5286
18.4.23DEPCMD_3 (DEPCMD_3)—Offset C83Ch................................................. 5286
18.4.24DEPCMDPAR2_4 (DEPCMDPAR2_4)—Offset C840h .................................. 5287
18.4.25DEPCMDPAR1_4 (DEPCMDPAR1_4)—Offset C844h .................................. 5287

130 334818
 18.4.26DEPCMDPAR0_4 (DEPCMDPAR0_4)—Offset C848h ...................................5288
18.4.27DEPCMD_4 (DEPCMD_4)—Offset C84Ch .................................................5288
18.4.28DEPCMDPAR2_5 (DEPCMDPAR2_5)—Offset C850h ...................................5289
18.4.29DEPCMDPAR1_5 (DEPCMDPAR1_5)—Offset C854h ...................................5290
18.4.30DEPCMDPAR0_5 (DEPCMDPAR0_5)—Offset C858h ...................................5290
18.4.31DEPCMD_5 (DEPCMD_5)—Offset C85Ch .................................................5291
18.4.32DEPCMDPAR2_6 (DEPCMDPAR2_6)—Offset C860h ...................................5291
18.4.33DEPCMDPAR1_6 (DEPCMDPAR1_6)—Offset C864h ...................................5292
18.4.34DEPCMDPAR0_6 (DEPCMDPAR0_6)—Offset C868h ...................................5292
18.4.35DEPCMD_6 (DEPCMD_6)—Offset C86Ch .................................................5293
18.4.36DEPCMDPAR2_7 (DEPCMDPAR2_7)—Offset C870h ...................................5294
18.4.37DEPCMDPAR1_7 (DEPCMDPAR1_7)—Offset C874h ...................................5294
18.4.38DEPCMDPAR0_7 (DEPCMDPAR0_7)—Offset C878h ...................................5295
18.4.39DEPCMD_7 (DEPCMD_7)—Offset C87Ch .................................................5295
18.4.40DEPCMDPAR2_8 (DEPCMDPAR2_8)—Offset C880h ...................................5296
18.4.41DEPCMDPAR1_8 (DEPCMDPAR1_8)—Offset C884h ...................................5296
18.4.42DEPCMDPAR0_8 (DEPCMDPAR0_8)—Offset C888h ...................................5297
18.4.43DEPCMD_8 (DEPCMD_8)—Offset C88Ch .................................................5297
18.4.44DEPCMDPAR2_9 (DEPCMDPAR2_9)—Offset C890h ...................................5298
18.4.45DEPCMDPAR1_9 (DEPCMDPAR1_9)—Offset C894h ...................................5299
18.4.46DEPCMDPAR0_9 (DEPCMDPAR0_9)—Offset C898h ...................................5299
18.4.47DEPCMD_9 (DEPCMD_9)—Offset C89Ch .................................................5300
18.4.48DEPCMDPAR2_10 (DEPCMDPAR2_10)—Offset C8A0h ...............................5300
18.4.49DEPCMDPAR1_10 (DEPCMDPAR1_10)—Offset C8A4h ...............................5301
18.4.50DEPCMDPAR0_10 (DEPCMDPAR0_10)—Offset C8A8h ...............................5301
18.4.51DEPCMD_10 (DEPCMD_10)—Offset C8ACh .............................................5302
18.4.52DEPCMDPAR2_11 (DEPCMDPAR2_11)—Offset C8B0h ...............................5303
18.4.53DEPCMDPAR1_11 (DEPCMDPAR1_11)—Offset C8B4h ...............................5303
18.4.54DEPCMDPAR0_11 (DEPCMDPAR0_11)—Offset C8B8h ...............................5304
18.4.55DEPCMD_11 (DEPCMD_11)—Offset C8BCh .............................................5304
18.4.56DEPCMDPAR2_12 (DEPCMDPAR2_12)—Offset C8C0h ...............................5305
18.4.57DEPCMDPAR1_12 (DEPCMDPAR1_12)—Offset C8C4h ...............................5305
18.4.58DEPCMDPAR0_12 (DEPCMDPAR0_12)—Offset C8C8h ...............................5306
18.4.59DEPCMD_12 (DEPCMD_12)—Offset C8CCh .............................................5306
18.4.60DEPCMDPAR2_13 (DEPCMDPAR2_13)—Offset C8D0h ...............................5307
18.4.61DEPCMDPAR1_13 (DEPCMDPAR1_13)—Offset C8D4h ...............................5308
18.4.62DEPCMDPAR0_13 (DEPCMDPAR0_13)—Offset C8D8h ...............................5308
18.4.63DEPCMD_13 (DEPCMD_13)—Offset C8DCh .............................................5309
18.4.64DEPCMDPAR2_14 (DEPCMDPAR2_14)—Offset C8E0h ...............................5309
18.4.65DEPCMDPAR1_14 (DEPCMDPAR1_14)—Offset C8E4h ...............................5310
18.4.66DEPCMDPAR0_14 (DEPCMDPAR0_14)—Offset C8E8h ...............................5310
18.4.67DEPCMD_14 (DEPCMD_14)—Offset C8ECh..............................................5311
18.4.68DEPCMDPAR2_15 (DEPCMDPAR2_15)—Offset C8F0h................................5312
18.4.69DEPCMDPAR1_15 (DEPCMDPAR1_15)—Offset C8F4h................................5312
18.4.70DEPCMDPAR0_15 (DEPCMDPAR0_15)—Offset C8F8h................................5313
18.4.71DEPCMD_15 (DEPCMD_15)—Offset C8FCh ..............................................5313
18.4.72DEPCMDPAR2_16 (DEPCMDPAR2_16)—Offset C900h ...............................5314
18.4.73DEPCMDPAR1_16 (DEPCMDPAR1_16)—Offset C904h ...............................5314
18.4.74DEPCMDPAR0_16 (DEPCMDPAR0_16)—Offset C908h ...............................5315
18.4.75DEPCMD_16 (DEPCMD_16)—Offset C90Ch..............................................5315
18.4.76DEPCMDPAR2_17 (DEPCMDPAR2_17)—Offset C910h ...............................5316
18.4.77DEPCMDPAR1_17 (DEPCMDPAR1_17)—Offset C914h ...............................5317
18.4.78DEPCMDPAR0_17 (DEPCMDPAR0_17)—Offset C918h ...............................5317
18.4.79DEPCMD_17 (DEPCMD_17)—Offset C91Ch..............................................5318
18.4.80DEPCMDPAR2_18 (DEPCMDPAR2_18)—Offset C920h ...............................5318

334818 131
 18.4.81DEPCMDPAR1_18 (DEPCMDPAR1_18)—Offset C924h ............................... 5319
18.4.82DEPCMDPAR0_18 (DEPCMDPAR0_18)—Offset C928h ............................... 5319
18.4.83DEPCMD_18 (DEPCMD_18)—Offset C92Ch ............................................. 5320
18.4.84DEPCMDPAR2_19 (DEPCMDPAR2_19)—Offset C930h ............................... 5321
18.4.85DEPCMDPAR1_19 (DEPCMDPAR1_19)—Offset C934h ............................... 5321
18.4.86DEPCMDPAR0_19 (DEPCMDPAR0_19)—Offset C938h ............................... 5322
18.4.87DEPCMD_19 (DEPCMD_19)—Offset C93Ch ............................................. 5322
18.4.88DEPCMDPAR2_20 (DEPCMDPAR2_20)—Offset C940h ............................... 5323
18.4.89DEPCMDPAR1_20 (DEPCMDPAR1_20)—Offset C944h ............................... 5323
18.4.90DEPCMDPAR0_20 (DEPCMDPAR0_20)—Offset C948h ............................... 5324
18.4.91DEPCMD_20 (DEPCMD_20)—Offset C94Ch ............................................. 5324
18.4.92DEPCMDPAR2_21 (DEPCMDPAR2_21)—Offset C950h ............................... 5325
18.4.93DEPCMDPAR1_21 (DEPCMDPAR1_21)—Offset C954h ............................... 5326
18.4.94DEPCMDPAR0_21 (DEPCMDPAR0_21)—Offset C958h ............................... 5326
18.4.95DEPCMD_21 (DEPCMD_21)—Offset C95Ch ............................................. 5327
18.4.96DEPCMDPAR2_22 (DEPCMDPAR2_22)—Offset C960h ............................... 5327
18.4.97DEPCMDPAR1_22 (DEPCMDPAR1_22)—Offset C964h ............................... 5328
18.4.98DEPCMDPAR0_22 (DEPCMDPAR0_22)—Offset C968h ............................... 5328
18.4.99DEPCMD_22 (DEPCMD_22)—Offset C96Ch ............................................. 5329
18.4.100DEPCMDPAR2_23 (DEPCMDPAR2_23)—Offset C970h ............................. 5330
18.4.101DEPCMDPAR1_23 (DEPCMDPAR1_23)—Offset C974h ............................. 5330
18.4.102DEPCMDPAR0_23 (DEPCMDPAR0_23)—Offset C978h ............................. 5331
18.4.103DEPCMD_23 (DEPCMD_23)—Offset C97Ch............................................ 5331
18.4.104DEPCMDPAR2_24 (DEPCMDPAR2_24)—Offset C980h ............................. 5332
18.4.105DEPCMDPAR1_24 (DEPCMDPAR1_24)—Offset C984h ............................. 5332
18.4.106DEPCMDPAR0_24 (DEPCMDPAR0_24)—Offset C988h ............................. 5333
18.4.107DEPCMD_24 (DEPCMD_24)—Offset C98Ch............................................ 5333
18.4.108DEPCMDPAR2_25 (DEPCMDPAR2_25)—Offset C990h ............................. 5334
18.4.109DEPCMDPAR1_25 (DEPCMDPAR1_25)—Offset C994h ............................. 5335
18.4.110DEPCMDPAR0_25 (DEPCMDPAR0_25)—Offset C998h ............................. 5335
18.4.111DEPCMD_25 (DEPCMD_25)—Offset C99Ch............................................ 5336
18.4.112DEPCMDPAR2_26 (DEPCMDPAR2_26)—Offset C9A0h ............................. 5336
18.4.113DEPCMDPAR1_26 (DEPCMDPAR1_26)—Offset C9A4h ............................. 5337
18.4.114DEPCMDPAR0_26 (DEPCMDPAR0_26)—Offset C9A8h ............................. 5337
18.4.115DEPCMD_26 (DEPCMD_26)—Offset C9ACh ........................................... 5338
18.4.116DEPCMDPAR2_27 (DEPCMDPAR2_27)—Offset C9B0h ............................. 5339
18.4.117DEPCMDPAR1_27 (DEPCMDPAR1_27)—Offset C9B4h ............................. 5339
18.4.118DEPCMDPAR0_27 (DEPCMDPAR0_27)—Offset C9B8h ............................. 5340
18.4.119DEPCMD_27 (DEPCMD_27)—Offset C9BCh ........................................... 5340
18.4.120DEPCMDPAR2_28 (DEPCMDPAR2_28)—Offset C9C0h ............................. 5341
18.4.121DEPCMDPAR1_28 (DEPCMDPAR1_28)—Offset C9C4h ............................. 5341
18.4.122DEPCMDPAR0_28 (DEPCMDPAR0_28)—Offset C9C8h ............................. 5342
18.4.123DEPCMD_28 (DEPCMD_28)—Offset C9CCh ........................................... 5342
18.4.124DEPCMDPAR2_29 (DEPCMDPAR2_29)—Offset C9D0h ............................. 5343
18.4.125DEPCMDPAR1_29 (DEPCMDPAR1_29)—Offset C9D4h ............................. 5344
18.4.126DEPCMDPAR0_29 (DEPCMDPAR0_29)—Offset C9D8h ............................. 5344
18.4.127DEPCMD_29 (DEPCMD_29)—Offset C9DCh ........................................... 5345
18.4.128DEPCMDPAR2_30 (DEPCMDPAR2_30)—Offset C9E0h ............................. 5345
18.4.129DEPCMDPAR1_30 (DEPCMDPAR1_30)—Offset C9E4h ............................. 5346
18.4.130DEPCMDPAR0_30 (DEPCMDPAR0_30)—Offset C9E8h ............................. 5346
18.4.131DEPCMD_30 (DEPCMD_30)—Offset C9ECh............................................ 5347
18.4.132DEPCMDPAR2_31 (DEPCMDPAR2_31)—Offset C9F0h.............................. 5348
18.4.133DEPCMDPAR1_31 (DEPCMDPAR1_31)—Offset C9F4h.............................. 5348
18.4.134DEPCMDPAR0_31 (DEPCMDPAR0_31)—Offset C9F8h.............................. 5349
18.4.135DEPCMD_31 (DEPCMD_31)—Offset C9FCh............................................ 5349

132 334818
 18.5 Registers Summary ........................................................................................5350
18.5.1 GSBUSCFG0 (GSBUSCFG0)—Offset C100h..............................................5352
18.5.2 GSBUSCFG1 (GSBUSCFG1)—Offset C104h..............................................5353
18.5.3 GTXTHRCFG (GTXTHRCFG)—Offset C108h ..............................................5354
18.5.4 GRXTHRCFG (GRXTHRCFG)—Offset C10Ch .............................................5354
18.5.5 GCTL (GCTL)—Offset C110h .................................................................5355
18.5.6 GPMSTS (GPMSTS)—Offset C114h .........................................................5356
18.5.7 GSTS (GSTS)—Offset C118h .................................................................5357
18.5.8 GUCTL1 (GUCTL1)—Offset C11Ch..........................................................5358
18.5.9 GSNPSID (GSNPSID)—Offset C120h ......................................................5359
18.5.10GGPIO (GGPIO)—Offset C124h..............................................................5359
18.5.11GUID (GUID)—Offset C128h .................................................................5360
18.5.12GUCTL (GUCTL)—Offset C12Ch .............................................................5360
18.5.13GBUSERRADDRLO (GBUSERRADDRLO)—Offset C130h..............................5361
18.5.14GBUSERRADDRHI (GBUSERRADDRHI)—Offset C134h...............................5362
18.5.15GPRTBIMAPLO (GPRTBIMAPLO)—Offset C138h ........................................5362
18.5.16GPRTBIMAPHI (GPRTBIMAPHI)—Offset C13Ch .........................................5363
18.5.17GHWPARAMS0 (GHWPARAMS0)—Offset C140h........................................5364
18.5.18GHWPARAMS1 (GHWPARAMS1)—Offset C144h........................................5365
18.5.19GHWPARAMS2 (GHWPARAMS2)—Offset C148h........................................5366
18.5.20GHWPARAMS3 (GHWPARAMS3)—Offset C14Ch .......................................5367
18.5.21GHWPARAMS4 (GHWPARAMS4)—Offset C150h........................................5368
18.5.22GHWPARAMS5 (GHWPARAMS5)—Offset C154h........................................5369
18.5.23GHWPARAMS6 (GHWPARAMS6)—Offset C158h........................................5370
18.5.24GHWPARAMS7 (GHWPARAMS7)—Offset C15Ch .......................................5371
18.5.25GDBGFIFOSPACE (GDBGFIFOSPACE)—Offset C160h ................................5372
18.5.26GDBGLTSSM (GDBGLTSSM)—Offset C164h .............................................5372
18.5.27GDBGLNMCC (GDBGLNMCC)—Offset C168h ............................................5374
18.5.28GDBGBMU (GDBGBMU)—Offset C16Ch ...................................................5374
18.5.29GDBGLSPMUX_DEV (GDBGLSPMUX_DEV)—Offset C170h ..........................5375
18.5.30GDBGLSP (GDBGLSP)—Offset C174h .....................................................5375
18.5.31GDBGEPINFO0 (GDBGEPINFO0)—Offset C178h .......................................5376
18.5.32GDBGEPINFO1 (GDBGEPINFO1)—Offset C17Ch .......................................5376
18.5.33GPRTBIMAP_HSLO (GPRTBIMAP_HSLO)—Offset C180h.............................5377
18.5.34GPRTBIMAP_HSHI (GPRTBIMAP_HSHI)—Offset C184h..............................5378
18.5.35GPRTBIMAP_FSLO (GPRTBIMAP_FSLO)—Offset C188h..............................5378
18.5.36GPRTBIMAP_FSHI (GPRTBIMAP_FSHI)—Offset C18Ch ..............................5379
18.5.37GUSB2PHYCFG_0 (GUSB2PHYCFG_0)—Offset C200h................................5380
18.5.38GUSB2I2CCTL_0 (GUSB2I2CCTL_0)—Offset C240h ..................................5381
18.5.39GUSB2PHYACC_ULPI_0 (GUSB2PHYACC_ULPI_0)—Offset C280h ...............5382
18.5.40GUSB3PIPECTL_0 (GUSB3PIPECTL_0)—Offset C2C0h ...............................5383
18.5.41GTXFIFOSIZ0_0 (GTXFIFOSIZ0_0)—Offset C300h ...................................5384
18.5.42GTXFIFOSIZ1_0 (GTXFIFOSIZ1_0)—Offset C304h ...................................5385
18.5.43GTXFIFOSIZ2_0 (GTXFIFOSIZ2_0)—Offset C308h ...................................5385
18.5.44GTXFIFOSIZ3_0 (GTXFIFOSIZ3_0)—Offset C30Ch ...................................5386
18.5.45GTXFIFOSIZ4_0 (GTXFIFOSIZ4_0)—Offset C310h ...................................5387
18.5.46GTXFIFOSIZ5_0 (GTXFIFOSIZ5_0)—Offset C314h ...................................5387
18.5.47GTXFIFOSIZ6_0 (GTXFIFOSIZ6_0)—Offset C318h ...................................5388
18.5.48GTXFIFOSIZ7_0 (GTXFIFOSIZ7_0)—Offset C31Ch ...................................5388
18.5.49GTXFIFOSIZ8_0 (GTXFIFOSIZ8_0)—Offset C320h ...................................5389
18.5.50GTXFIFOSIZ9_0 (GTXFIFOSIZ9_0)—Offset C324h ...................................5389
18.5.51GTXFIFOSIZ10_0 (GTXFIFOSIZ10_0)—Offset C328h ................................5390
18.5.52GTXFIFOSIZ11_0 (GTXFIFOSIZ11_0)—Offset C32Ch................................5390
18.5.53GTXFIFOSIZ12_0 (GTXFIFOSIZ12_0)—Offset C330h ................................5391
18.5.54GTXFIFOSIZ13_0 (GTXFIFOSIZ13_0)—Offset C334h ................................5391

334818 133
 18.5.55GTXFIFOSIZ14_0 (GTXFIFOSIZ14_0)—Offset C338h ............................... 5392
18.5.56GTXFIFOSIZ15_0 (GTXFIFOSIZ15_0)—Offset C33Ch ............................... 5392
18.5.57GRXFIFOSIZ0_0 (GRXFIFOSIZ0_0)—Offset C380h .................................. 5393
18.5.58GEVNTADRLO_0 (GEVNTADRLO_0)—Offset C400h .................................. 5393
18.5.59GEVNTADRHI_0 (GEVNTADRHI_0)—Offset C404h ................................... 5394
18.5.60GEVNTSIZ_0 (GEVNTSIZ_0)—Offset C408h............................................ 5394
18.5.61GEVNTCOUNT_0 (GEVNTCOUNT_0)—Offset C40Ch.................................. 5395
18.5.62GHWPARAMS8 (GHWPARAMS8)—Offset C600h ....................................... 5396
18.5.63GTXFIFOPRIDEV (GTXFIFOPRIDEV)—Offset C610h .................................. 5396
18.5.64GFLADJ (GFLADJ)—Offset C630h .......................................................... 5397
18.6 Registers Summary........................................................................................ 5398
18.6.1 APBFC_U3PMU_CFG0 (APBFC_U3PMU_CFG0)—Offset 10F808h ................. 5398
18.6.2 APBFC_U3PMU_CFG1 (APBFC_U3PMU_CFG1)—Offset 10F80Ch ................. 5399
18.6.3 APBFC_U3PMU_CFG2 (APBFC_U3PMU_CFG2)—Offset 10F810h ................. 5401
18.6.4 APBFC_U3PMU_CFG3 (APBFC_U3PMU_CFG3)—Offset 10F814h ................. 5402
18.6.5 APBFC_U3PMU_CFG4 (APBFC_U3PMU_CFG4)—Offset 10F818h ................. 5403
18.6.6 APBFC_U3PMU_CFG5 (APBFC_U3PMU_CFG5)—Offset 10F81Ch ................. 5404
18.6.7 APBFC_U3PMU_CFG6 (APBFC_U3PMU_CFG6)—Offset 10F820h ................. 5405
18.6.8 APBFC_D0I3C (APBFC_D0I3C)—Offset 10F830h...................................... 5406
18.7 Registers Summary........................................................................................ 5407
18.7.1 (GEN_REGRW1)—Offset B0h ............................................................... 5407
18.7.2 (GEN_REGRW2)—Offset B4h ................................................................ 5407
18.7.3 (GEN_REGRW3)—Offset B8h ................................................................ 5408
18.7.4 (GEN_REGRW4)—Offset BCh ................................................................ 5408
18.7.5 (GEN_INPUT_REGRW)—Offset C0h....................................................... 5409
18.8 Registers Summary........................................................................................ 5411
18.8.1 (GEN_REGRW1)—Offset B0h ............................................................... 5411
18.8.2 (GEN_REGRW2)—Offset B4h ................................................................ 5411
18.8.3 (GEN_REGRW3)—Offset B8h ................................................................ 5412
18.8.4 (GEN_REGRW4)—Offset BCh ................................................................ 5412
18.8.5 (GEN_INPUT_REGRW)—Offset C0h....................................................... 5413
18.9 Registers Summary........................................................................................ 5415
18.9.1 (DEVVENDID)—Offset 0h .................................................................... 5415
18.9.2 (STATUSCOMMAND)—Offset 4h ............................................................ 5416
18.9.3 (REVCLASSCODE)—Offset 8h ............................................................... 5417
18.9.4 (CLLATHEADERBIST)—Offset Ch ........................................................... 5417
18.9.5 (BAR)—Offset 10h .............................................................................. 5418
18.9.6 (BAR1)—Offset 18h............................................................................. 5419
18.9.7 (SUBSYSTEMID)—Offset 2Ch................................................................ 5419
18.9.8 (EXPANSION_ROM_BASEADDR)—Offset 30h .......................................... 5420
18.9.9 (CAPABILITYPTR)—Offset 34h .............................................................. 5421
18.9.10(INTERRUPTREG)—Offset 3Ch .............................................................. 5421
18.9.11(POWERCAPID)—Offset 80h ................................................................. 5422
18.9.12(PMECTRLSTATUS)—Offset 84h ............................................................ 5422
18.9.13(PCIDEVIDLE_CAP_RECORD)—Offset 90h .............................................. 5423
18.9.14(DEVID_VEND_SPECIFIC_REG)—Offset 94h ........................................... 5424
18.9.15(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 5424
18.9.16(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 5425
18.9.17(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 5426
18.10 Registers Summary........................................................................................ 5427
18.10.1 (DEVVENDID)—Offset 0h .................................................................... 5427
18.10.2(STATUSCOMMAND)—Offset 4h ............................................................ 5428
18.10.3(REVCLASSCODE)—Offset 8h ............................................................... 5429
18.10.4(CLLATHEADERBIST)—Offset Ch ........................................................... 5429
18.10.5(BAR)—Offset 10h .............................................................................. 5430

134 334818
 18.10.6(BAR1)—Offset 18h .............................................................................5431
18.10.7(SUBSYSTEMID)—Offset 2Ch ................................................................5431
18.10.8(EXPANSION_ROM_BASEADDR)—Offset 30h ...........................................5432
18.10.9(CAPABILITYPTR)—Offset 34h ...............................................................5433
18.10.10(INTERRUPTREG)—Offset 3Ch .............................................................5433
18.10.11(POWERCAPID)—Offset 80h ................................................................5434
18.10.12(PMECTRLSTATUS)—Offset 84h ...........................................................5434
18.10.13(PCIDEVIDLE_CAP_RECORD)—Offset 90h .............................................5435
18.10.14(DEVID_VEND_SPECIFIC_REG)—Offset 94h ..........................................5436
18.10.15(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h...............................5436
18.10.16(DEVICE_IDLE_POINTER_REG)—Offset 9Ch...........................................5437
18.10.17(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ...................................5438
18.11 Registers Summary ........................................................................................5439
18.11.1Capability Registers Length (CAPLENGTH)—Offset 0h ...............................5452
18.11.2Host Controller Interface Version Number (HCIVERSION)—Offset 2h ..........5452
18.11.3Structural Parameters 1 (HCSPARAMS1)—Offset 4h .................................5452
18.11.4Structural Parameters 2 (HCSPARAMS2)—Offset 8h .................................5453
18.11.5Structural Parameters 3 (HCSPARAMS3)—Offset Ch .................................5454
18.11.6Capability Parameters (HCCPARAMS)—Offset 10h ....................................5454
18.11.7Doorbell Offset (DBOFF)—Offset 14h......................................................5455
18.11.8Runtime Register Space Offset (RTSOFF)—Offset 18h...............................5456
18.11.9USB Command (USBCMD)—Offset 80h...................................................5456
18.11.10USB Status (USBSTS)—Offset 84h .......................................................5457
18.11.11Page Size (PAGESIZE)—Offset 88h .......................................................5458
18.11.12Device Notification Control (DNCTRL)—Offset 94h ..................................5458
18.11.13Command Ring Low (CRCR_LO)—Offset 98h..........................................5459
18.11.14Command Ring High (CRCR_HI)—Offset 9Ch .........................................5459
18.11.15Device Context Base Address Array Pointer Low (DCBAAP_LO)—Offset B0h ......
5460
18.11.16Device Context Base Address Array Pointer High (DCBAAP_HI)—Offset B4h ......
5460
18.11.17Configure (CONFIG)—Offset B8h..........................................................5461
18.11.18Port Status and Control USB2 (PORTSC1)—Offset 480h...........................5461
18.11.19Port Power Management Status and Control USB2 (PORTPMSC1)—Offset 484h .
5463
18.11.20Port X Hardware LPM Control Register (PORTHLPMC1)—Offset 48Ch .........5463
18.11.21Port Status and Control USB2 (PORTSC2)—Offset 490h...........................5464
18.11.22Port Power Management Status and Control USB2 (PORTPMSC2)—Offset 494h .
5466
18.11.23Port X Hardware LPM Control Register (PORTHLPMC2)—Offset 49Ch .........5466
18.11.24Port Status and Control USB2 (PORTSC3)—Offset 4A0h ..........................5467
18.11.25Port Power Management Status and Control USB2 (PORTPMSC3)—Offset 4A4h .
5469
18.11.26Port X Hardware LPM Control Register (PORTHLPMC3)—Offset 4ACh .........5469
18.11.27Port Status and Control USB2 (PORTSC4)—Offset 4B0h ..........................5470
18.11.28Port Power Management Status and Control USB2 (PORTPMSC4)—Offset 4B4h .
5472
18.11.29Port X Hardware LPM Control Register (PORTHLPMC4)—Offset 4BCh .........5472
18.11.30Port Status and Control USB2 (PORTSC5)—Offset 4C0h ..........................5473
18.11.31Port Power Management Status and Control USB2 (PORTPMSC5)—Offset 4C4h .
5475
18.11.32Port X Hardware LPM Control Register (PORTHLPMC5)—Offset 4CCh .........5475
18.11.33Port Status and Control USB2 (PORTSC6)—Offset 4D0h ..........................5476
18.11.34Port Power Management Status and Control USB2 (PORTPMSC6)—Offset 4D4h .
5478

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 18.11.35Port X Hardware LPM Control Register (PORTHLPMC6)—Offset 4DCh ........ 5478
18.11.36Port Status and Control USB2 (PORTSC7)—Offset 4E0h .......................... 5479
18.11.37Port Power Management Status and Control USB2 (PORTPMSC7)—Offset 4E4h .
5481
18.11.38Port X Hardware LPM Control Register (PORTHLPMC7)—Offset 4ECh......... 5481
18.11.39Port Status and Control USB2 (PORTSC8)—Offset 4F0h .......................... 5482
18.11.40Port Power Management Status and Control USB2 (PORTPMSC8)—Offset 4F4h .
5484
18.11.41Port X Hardware LPM Control Register (PORTHLPMC8)—Offset 4FCh ......... 5484
18.11.42Port Status and Control USB3 (PORTSC9)—Offset 500h .......................... 5485
18.11.43Port Power Management Status and Control USB3 (PORTPMSC9)—Offset 504h .
5487
18.11.44USB3 Port Link Info (PORTLI9)—Offset 508h ......................................... 5487
18.11.45Port Status and Control USB3 (PORTSC10)—Offset 510h ........................ 5488
18.11.46Port Power Management Status and Control USB3 (PORTPMSC10)—Offset 514h
5489
18.11.47USB3 Port Link Info (PORTLI10)—Offset 518h ....................................... 5490
18.11.48Port Status and Control USB3 (PORTSC11)—Offset 520h ........................ 5490
18.11.49Port Power Management Status and Control USB3 (PORTPMSC11)—Offset 524h
5492
18.11.50USB3 Port Link Info (PORTLI11)—Offset 528h ....................................... 5492
18.11.51Port Status and Control USB3 (PORTSC12)—Offset 530h ........................ 5493
18.11.52Port Power Management Status and Control USB3 (PORTPMSC12)—Offset 534h
5494
18.11.53USB3 Port Link Info (PORTLI12)—Offset 538h ....................................... 5495
18.11.54Port Status and Control USB3 (PORTSC13)—Offset 540h ........................ 5495
18.11.55Port Power Management Status and Control USB3 (PORTPMSC13)—Offset 544h
5497
18.11.56USB3 Port Link Info (PORTLI13)—Offset 548h ....................................... 5497
18.11.57Port Status and Control USB3 (PORTSC14)—Offset 550h ........................ 5498
18.11.58Port Power Management Status and Control USB3 (PORTPMSC14)—Offset 554h
5499
18.11.59USB3 Port Link Info (PORTLI14)—Offset 558h ....................................... 5500
18.11.60Port Status and Control USB3 (PORTSC15)—Offset 560h ........................ 5500
18.11.61Port Power Management Status and Control USB3 (PORTPMSC15)—Offset 564h
5501
18.11.62USB3 Port Link Info (PORTLI15)—Offset 568h ....................................... 5502
18.11.63Microframe Index (RTMFINDEX)—Offset 2000h ..................................... 5502
18.11.64Interrupter 1 Management (IMAN0)—Offset 2020h ................................ 5503
18.11.65Interrupter 1 Moderation (IMOD0)—Offset 2024h .................................. 5503
18.11.66Event Ring Segment Table Size 1 (ERSTSZ0)—Offset 2028h ................... 5504
18.11.67Event Ring Segment Table Base Address Low 1 (ERSTBA_LO0)—Offset 2030h..
5504
18.11.68Event Ring Segment Table Base Address High 1 (ERSTBA_HI0)—Offset 2034h .
5505
18.11.69Event Ring Dequeue Pointer Low 1 (ERDP_LO0)—Offset 2038h................ 5505
18.11.70Event Ring Dequeue Pointer High 1 (ERDP_HI0)—Offset 203Ch ............... 5506
18.11.71Interrupter 2 Management (IMAN1)—Offset 2040h ................................ 5506
18.11.72Interrupter 2 Moderation (IMOD1)—Offset 2044h .................................. 5507
18.11.73Event Ring Segment Table Size 2 (ERSTSZ1)—Offset 2048h ................... 5507
18.11.74Event Ring Segment Table Base Address Low 2 (ERSTBA_LO1)—Offset 2050h..
5508
18.11.75Event Ring Segment Table Base Address High 2 (ERSTBA_HI1)—Offset 2054h .
5508
18.11.76Event Ring Dequeue Pointer Low 2 (ERDP_LO1)—Offset 2058h................ 5509
18.11.77Event Ring Dequeue Pointer High 2 (ERDP_HI1)—Offset 205Ch ............... 5509

136 334818
 18.11.78Interrupter 3 Management (IMAN2)—Offset 2060h.................................5510
18.11.79Interrupter 3 Moderation (IMOD2)—Offset 2064h ...................................5510
18.11.80Event Ring Segment Table Size 3 (ERSTSZ2)—Offset 2068h ....................5511
18.11.81Event Ring Segment Table Base Address Low 3 (ERSTBA_LO2)—Offset 2070h ..
5511
18.11.82Event Ring Segment Table Base Address High 3 (ERSTBA_HI2)—Offset 2074h ..
5512
18.11.83Event Ring Dequeue Pointer Low 3 (ERDP_LO2)—Offset 2078h ................5512
18.11.84Event Ring Dequeue Pointer High 3 (ERDP_HI2)—Offset 207Ch................5513
18.11.85Interrupter 4 Management (IMAN3)—Offset 2080h.................................5513
18.11.86Interrupter 4 Moderation (IMOD3)—Offset 2084h ...................................5514
18.11.87Event Ring Segment Table Size 4 (ERSTSZ3)—Offset 2088h ....................5514
18.11.88Event Ring Segment Table Base Address Low 4 (ERSTBA_LO3)—Offset 2090h ..
5515
18.11.89Event Ring Segment Table Base Address High 4 (ERSTBA_HI3)—Offset 2094h ..
5515
18.11.90Event Ring Dequeue Pointer Low 4 (ERDP_LO3)—Offset 2098h ................5516
18.11.91Event Ring Dequeue Pointer High 4 (ERDP_HI3)—Offset 209Ch................5516
18.11.92Interrupter 5 Management (IMAN4)—Offset 20A0h.................................5517
18.11.93Interrupter 5 Moderation (IMOD4)—Offset 20A4h...................................5517
18.11.94Event Ring Segment Table Size 5 (ERSTSZ4)—Offset 20A8h ....................5518
18.11.95Event Ring Segment Table Base Address Low 5 (ERSTBA_LO4)—Offset 20B0h ..
5518
18.11.96Event Ring Segment Table Base Address High 5 (ERSTBA_HI4)—Offset 20B4h ..
5519
18.11.97Event Ring Dequeue Pointer Low 5 (ERDP_LO4)—Offset 20B8h ................5519
18.11.98Event Ring Dequeue Pointer High 5 (ERDP_HI4)—Offset 20BCh................5520
18.11.99Interrupter 6 Management (IMAN5)—Offset 20C0h.................................5520
18.11.100Interrupter 6 Moderation (IMOD5)—Offset 20C4h .................................5521
18.11.101Event Ring Segment Table Size 6 (ERSTSZ5)—Offset 20C8h ..................5521
18.11.102Event Ring Segment Table Base Address Low 6 (ERSTBA_LO5)—Offset 20D0h
5522
18.11.103Event Ring Segment Table Base Address High 6 (ERSTBA_HI5)—Offset 20D4h
5522
18.11.104Event Ring Dequeue Pointer Low 6 (ERDP_LO5)—Offset 20D8h ..............5523
18.11.105Event Ring Dequeue Pointer High 6 (ERDP_HI5)—Offset 20DCh..............5523
18.11.106Interrupter 7 Management (IMAN6)—Offset 20E0h ...............................5524
18.11.107Interrupter 7 Moderation (IMOD6)—Offset 20E4h .................................5524
18.11.108Event Ring Segment Table Size 7 (ERSTSZ6)—Offset 20E8h ..................5525
18.11.109Event Ring Segment Table Base Address Low 7 (ERSTBA_LO6)—Offset 20F0h.
5525
18.11.110Event Ring Segment Table Base Address High 7 (ERSTBA_HI6)—Offset 20F4h
5526
18.11.111Event Ring Dequeue Pointer Low 7 (ERDP_LO6)—Offset 20F8h...............5526
18.11.112Event Ring Dequeue Pointer High 7 (ERDP_HI6)—Offset 20FCh ..............5527
18.11.113Interrupter 8 Management (IMAN7)—Offset 2100h ...............................5527
18.11.114Interrupter 8 Moderation (IMOD7)—Offset 2104h .................................5528
18.11.115Event Ring Segment Table Size 8 (ERSTSZ7)—Offset 2108h ..................5528
18.11.116Event Ring Segment Table Base Address Low 8 (ERSTBA_LO7)—Offset 2110h
5529
18.11.117Event Ring Segment Table Base Address High 8 (ERSTBA_HI7)—Offset 2114h
5529
18.11.118Event Ring Dequeue Pointer Low 8 (ERDP_LO7)—Offset 2118h ..............5530
18.11.119Event Ring Dequeue Pointer High 8 (ERDP_HI7)—Offset 211Ch ..............5530
18.11.120Door Bell 1 (DB0)—Offset 3000h ........................................................5531
18.11.121Door Bell 2 (DB1)—Offset 3004h ........................................................5531

334818 137
 18.11.122Door Bell 3 (DB2)—Offset 3008h ....................................................... 5532
18.11.123Door Bell 4 (DB3)—Offset 300Ch ....................................................... 5532
18.11.124Door Bell 5 (DB4)—Offset 3010h ....................................................... 5533
18.11.125Door Bell 6 (DB5)—Offset 3014h ....................................................... 5533
18.11.126Door Bell 7 (DB6)—Offset 3018h ....................................................... 5534
18.11.127Door Bell 8 (DB7)—Offset 301Ch ....................................................... 5534
18.11.128Door Bell 9 (DB8)—Offset 3020h ....................................................... 5535
18.11.129Door Bell 10 (DB9)—Offset 3024h...................................................... 5536
18.11.130Door Bell 11 (DB10)—Offset 3028h .................................................... 5536
18.11.131Door Bell 12 (DB11)—Offset 302Ch.................................................... 5537
18.11.132Door Bell 13 (DB12)—Offset 3030h .................................................... 5537
18.11.133Door Bell 14 (DB13)—Offset 3034h .................................................... 5538
18.11.134Door Bell 15 (DB14)—Offset 3038h .................................................... 5538
18.11.135Door Bell 16 (DB15)—Offset 303Ch.................................................... 5539
18.11.136Door Bell 17 (DB16)—Offset 3040h .................................................... 5539
18.11.137Door Bell 18 (DB17)—Offset 3044h .................................................... 5540
18.11.138Door Bell 19 (DB18)—Offset 3048h .................................................... 5540
18.11.139Door Bell 20 (DB19)—Offset 304Ch.................................................... 5541
18.11.140Door Bell 21 (DB20)—Offset 3050h .................................................... 5542
18.11.141Door Bell 22 (DB21)—Offset 3054h .................................................... 5542
18.11.142Door Bell 23 (DB22)—Offset 3058h .................................................... 5543
18.11.143Door Bell 24 (DB23)—Offset 305Ch.................................................... 5543
18.11.144Door Bell 25 (DB24)—Offset 3060h .................................................... 5544
18.11.145Door Bell 26 (DB25)—Offset 3064h .................................................... 5544
18.11.146Door Bell 27 (DB26)—Offset 3068h .................................................... 5545
18.11.147Door Bell 28 (DB27)—Offset 306Ch.................................................... 5545
18.11.148Door Bell 29 (DB28)—Offset 3070h .................................................... 5546
18.11.149Door Bell 30 (DB29)—Offset 3074h .................................................... 5546
18.11.150Door Bell 31 (DB30)—Offset 3078h .................................................... 5547
18.11.151Door Bell 32 (DB31)—Offset 307Ch.................................................... 5548
18.11.152Door Bell 32 (DB32)—Offset 3080h .................................................... 5548
18.11.153XECP_SUPP_USB2_0 (XECP_SUPP_USB2_0)—Offset 8000h................... 5549
18.11.154XECP_SUPP_USB2_1 (XECP_SUPP_USB2_1)—Offset 8004h................... 5549
18.11.155XECP_SUPP_USB2_2 (XECP_SUPP_USB2_2)—Offset 8008h................... 5550
18.11.156XECP_SUPP_USB2_3 (Full Speed) (XECP_SUPP_USB2_3)—Offset 8010h. 5551
18.11.157XECP_SUPP_USB2_4 (Low Speed) (XECP_SUPP_USB2_4)—Offset 8014h 5551
18.11.158XECP_SUPP_USB2_5 (High Speed) (XECP_SUPP_USB2_5)—Offset 8018h 5552
18.11.159XECP_SUPP_USB3_0 (XECP_SUPP_USB3_0)—Offset 8020h................... 5553
18.11.160XECP_SUPP_USB3_1 (XECP_SUPP_USB3_1)—Offset 8024h................... 5553
18.11.161XECP_SUPP_USB3_2 (XECP_SUPP_USB3_2)—Offset 8028h................... 5554
18.11.162XECP_SUPP_USB3_3 (XECP_SUPP_USB3_3)—Offset 8030h................... 5554
18.11.163XECP_SUPP_USB3_4 (XECP_SUPP_USB3_4)—Offset 8034h................... 5555
18.11.164XECP_SUPP_USB3_5 (XECP_SUPP_USB3_5)—Offset 8038h................... 5556
18.11.165XECP_SUPP_USB3_6 (XECP_SUPP_USB3_6)—Offset 803Ch .................. 5556
18.11.166XECP_SUPP_USB3_7 (XECP_SUPP_USB3_7)—Offset 8040h................... 5557
18.11.167XECP_SUPP_USB3_8 (XECP_SUPP_USB3_8)—Offset 8044h................... 5558
18.11.168XECP_SUPP_USB3_9 (XECP_SUPP_USB3_9)—Offset 8048h................... 5558
18.11.169Host Controller Capability (HOST_CTRL_CAP_REG)—Offset 8070h.......... 5559
18.11.170Override EP Flow Control (HOST_CLR_MASK_REG)—Offset 8078h .......... 5560
18.11.171Clear Active IN EP ID Control (HOST_CLR_IN_EP_VALID_REG)—Offset 807Ch
5560
18.11.172Clear Poll Mask Control (HOST_CLR_PMASK_REG)—Offset 8080h........... 5561
18.11.173Host Control Scheduler (HOST_CTRL_SCH_REG)—Offset 8094h ............. 5562
18.11.174Global Port Control (HOST_CTRL_PORT_CTRL)—Offset 80A0h................ 5563
18.11.175PGCB Control (PGCBCTRL_REG)—Offset 80A8h.................................... 5564

138 334818
 18.11.176D0I3 Control (DOI3CTRL_REG)—Offset 80ACh .....................................5567
18.11.177HOST_CTRL_MISC_REG (HOST_CTRL_MISC_REG)—Offset 80B0h...........5568
18.11.178HOST_CTRL_MISC_REG2 (HOST_CTRL_MISC_REG2)—Offset 80B4h .......5570
18.11.179SSPE_REG (SSPE_REG)—Offset 80B8h ...............................................5571
18.11.180(SSPITPE)—Offset 80BCh ..................................................................5572
18.11.181AUX Reset Control (AUX_CTRL_REG)—Offset 80C0h .............................5572
18.11.182Super Speed Bandwidth Overload (HOST_BW_OV_SS_REG)—Offset 80C4h ....
5575
18.11.183High Speed TT Bandwidth Overload (HOST_BW_OV_HS_REG)—Offset 80C8h..
5575
18.11.184Bandwidth Overload Full Low Speed (HOST_BW_OV_FS_LS_REG)—Offset
80CCh ...............................................................................................5576
18.11.185System Bandwidth Overload (HOST_BW_OV_SYS_REG)—Offset 80D0h...5577
18.11.186Scheduler Async Delay (HOST_CTRL_SCH_ASYNC_DELAY_REG)—Offset
80D4h ...............................................................................................5577
18.11.187DEVICE MODE CONTROL REG 0 (DUAL_ROLE_CFG_REG0)—Offset 80D8h5578
18.11.188DEVICE MODE CONTROL REG 1 (DUAL_ROLE_CFG_REG1)—Offset 80DCh5580
18.11.189AUX Power Management Control (AUX_CTRL_REG1)—Offset 80E0h ........5581
18.11.190Battery Charge (BATTERY_CHARGE_REG)—Offset 80E4h.......................5583
18.11.191Port Watermark (HOST_CTRL_WATERMARK_REG)—Offset 80E8h ...........5584
18.11.192SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG)—Offset 80ECh .
5585
18.11.193USB2 Port Link Control 1 (USB2_LINK_MGR_CTRL_REG1)—Offset 80F0h.5586
18.11.194USB2 Port Link Control 2 (USB2_LINK_MGR_CTRL_REG2)—Offset 80F4h.5588
18.11.195USB2 Port Link Control 3 (USB2_LINK_MGR_CTRL_REG3)—Offset 80F8h.5589
18.11.196USB2 Port Link Control 4 (USB2_LINK_MGR_CTRL_REG4)—Offset 80FCh 5590
18.11.197Bandwidth Calc Control (HOST_CTRL_BW_CTRL_REG)—Offset 8100h .....5591
18.11.198Host Interface Control (HOST_IF_CTRL_REG)—Offset 8108h..................5591
18.11.199Bandwidth Overload Burst (HOST_BW_OV_BURST_REG)—Offset 810Ch ..5592
18.11.200USB Max Bandwidth Control 4 (HOST_CTRL_BW_MAX_REG)—Offset 8128h ....
5592
18.11.201USB2 Linestate Debug (LINESTATE_DEBUG_REG)—Offset 8130h............5593
18.11.202USB2 Protocol Gap Timer (USB2_PROTOCOL_GAP_TIMER_REG)—Offset 8134h
5594
18.11.203USB2 Protocol Bus Timeout Timer (USB2_PROTOCOL_BTO_TIMER_REG)—
Offset 813Ch ......................................................................................5595
18.11.204Power Scheduler Control-0 (PWR_SCHED_CTRL0)—Offset 8140h............5595
18.11.205Power Scheduler Control-2 (PWR_SCHED_CTRL2)—Offset 8144h............5596
18.11.206AUX Power Management Control (AUX_CTRL_REG2)—Offset 8154h ........5597
18.11.207USB2 PHY Power Management Control (USB2_PHY_PMC)—Offset 8164h..5600
18.11.208USB Power Gating Control (USB_PGC)—Offset 8168h............................5601
18.11.209xHCI Aux Clock Control Register (XHCI_AUX_CCR)—Offset 816Ch ..........5602
18.11.210USB LPM Parameters (USB_LPM_PARAM)—Offset 8170h........................5604
18.11.211xHC Latency Tolerance Parameters - LTV Control (XLTP_LTV1)—Offset 8174h .
5605
18.11.212xHC Latency Tolerance Parameters LTV Control 2 (XLTP_LTV2)—Offset 8178h
5606
18.11.213xHC Latency Tolerance Parameters - High Idle Time Control (XLTP_HITC)—
Offset 817Ch ......................................................................................5607
18.11.214xHC Latency Tolerance Parameters - Medium Idle Time Control (XLTP_MITC)—
Offset 8180h ......................................................................................5608
18.11.215xHC Latency Tolerance Parameters Low Idle Time Control (XLTP_LITC)—Offset
8184h................................................................................................5609
18.11.216HOST_CTRL_BW_MAX3_REG (HOST_CTRL_BW_MAX3_REG)—Offset 8188h ....
5609
18.11.217PDDIS_REG (PDDIS_REG)—Offset 8198h ............................................5610

334818 139
 18.11.218LFPS_PM_CTRL_REG (LFPS_PM_CTRL_REG)—Offset 81A0h ................... 5610
18.11.219U2PDM (U2PDM)—Offset 81A4h......................................................... 5611
18.11.220U2PCM (U2PCM)—Offset 81A8h ......................................................... 5611
18.11.221U3PDM (U3PDM)—Offset 81ACh ........................................................ 5612
18.11.222U3PCM (U3PCM)—Offset 81B0h ......................................................... 5612
18.11.223THRM_HOST_CTRL_REG2 (THRM_HOST_CTRL_REG2)—Offset 81B4h ..... 5613
18.11.224(D0i2_CTRL_REG)—Offset 81BCh ...................................................... 5613
18.11.225 (D0i2_SCH_ALARM_CTRL_REG)—Offset 81C0h................................... 5615
18.11.226 (USB2PMCTRL_REG)—Offset 81C4h .................................................. 5616
18.11.227ECC_PARITY_ERROR_LOG_REG (ECC_PARITY_ERROR_LOG_REG)—Offset
83F8h ............................................................................................... 5618
18.11.228ECC_POISONING_CTRL_REG (ECC_POISONING_CTRL_REG)—Offset 83FCh ...
5620
18.11.229USB2_PORT_STATE_REG (USB2_PORT_STATE_REG)—Offset 8400h....... 5621
18.11.230USB3_PORT_STATE_REG (USB3_PORT_STATE_REG)—Offset 8408h....... 5622
18.11.231FUS1_REG (FUS1_REG)—Offset 8410h ............................................... 5622
18.11.232FUS2_REG (FUS2_REG)—Offset 8414h ............................................... 5623
18.11.233FUS3_REG (FUS3_REG)—Offset 8418h ............................................... 5624
18.11.234STRAP1_REG (STRAP1_REG)—Offset 841Ch........................................ 5624
18.11.235STRAP3_REG (STRAP3_REG)—Offset 8424h ........................................ 5625
18.11.236XECP_CMDM_STS0 (XECP_CMDM_STS0)—Offset 8448h ....................... 5626
18.11.237XECP_CMDM_STS1 (XECP_CMDM_STS1)—Offset 844Ch ....................... 5627
18.11.238XECP_CMDM_STS2 (XECP_CMDM_STS2)—Offset 8450h ....................... 5628
18.11.239XECP_CMDM_STS3 (XECP_CMDM_STS3)—Offset 8454h ....................... 5628
18.11.240XECP_CMDM_STS4 (XECP_CMDM_STS4)—Offset 8458h ....................... 5629
18.11.241XECP_CMDM_STS5 (XECP_CMDM_STS5)—Offset 845Ch ....................... 5629
18.11.242AUX Power PHY Reset (UPORTS_PON_RST_REG)—Offset 8460h............. 5630
18.11.243Latency Tolerance Control 0 (HOST_IF_LAT_TOL_CTRL_REG0)—Offset 8464h
5630
18.11.244USB Legacy Support Capability (USBLEGSUP)—Offset 846Ch................. 5631
18.11.245USB Legacy Support Control Status (USBLEGCTLSTS)—Offset 8470h...... 5632
18.11.246Port Disable Override capability register (PDO_CAPABILITY)—Offset 84F4h ....
5633
18.11.247USB2 Port Disable Override (USB2PDO)—Offset 84F8h ......................... 5633
18.11.248USB3 Port Disable Override (USB3PDO)—Offset 84FCh ......................... 5634
18.11.249HW state capability register (HW_STATE_CAPABILITY)—Offset 8500h..... 5634
18.11.250HW state register 1 (HW_STATE_REG1)—Offset 8504h ......................... 5635
18.11.251HW state register 2 (HW_STATE_REG2)—Offset 8508h ......................... 5635
18.11.252HW state register 3 (HW_STATE_REG3)—Offset 850Ch......................... 5636
18.11.253HW state register 4 (HW_STATE_REG4)—Offset 8510h ......................... 5636
18.11.254CONFIG mirror capability register (CONFIG_MIRROR_CAPABILITY)—Offset
8600h ............................................................................................... 5637
18.11.255Command (CMD_MMIO)—Offset 8604h .............................................. 5637
18.11.256Device Status (STS_MMIO)—Offset 8606h .......................................... 5639
18.11.257Revision ID (RID_MMIO)—Offset 8608h.............................................. 5640
18.11.258Programming Interface (PI_MMIO)—Offset 8609h ................................ 5640
18.11.259Sub Class Code (SCC_MMIO)—Offset 860Ah ....................................... 5641
18.11.260Base Class Code (BCC_MMIO)—Offset 860Bh ...................................... 5641
18.11.261Master Latency Timer (MLT_MMIO)—Offset 860Dh ............................... 5641
18.11.262Header Type (HT_MMIO)—Offset 860Eh ............................................. 5642
18.11.263Memory Base Address (MBAR_MMIO)—Offset 8610h ............................ 5642
18.11.264USB Subsystem Vendor ID (SSVID_MMIO)—Offset 862Ch..................... 5643
18.11.265USB Subsystem ID (SSID_MMIO)—Offset 862Eh ................................. 5643
18.11.266Capabilities Pointer (CAP_PTR_MMIO)—Offset 8634h ............................ 5644
18.11.267Interrupt Line (ILINE_MMIO)—Offset 863Ch........................................ 5644

140 334818
 18.11.268Interrupt Pin (IPIN_MMIO)—Offset 863Dh ...........................................5645
18.11.269XHC System Bus Configuration 1 (XHCC1_MMIO)—Offset 8640h ............5645
18.11.270Clock Gating (XHCLKGTEN_MMIO)—Offset 8650h .................................5647
18.11.271Audio Time Synchronization (AUDSYNC_MMIO)—Offset 8658h ...............5650
18.11.272Serial Bus Release Number (SBRN_MMIO)—Offset 8660h ......................5651
18.11.273Frame Length Adjustment (FLADJ_MMIO)—Offset 8661h .......................5651
18.11.274Best Effort Service Latency (BESL_MMIO)—Offset 8662h .......................5652
18.11.275PCI Power Management Capability ID (PM_CID_MMIO)—Offset 8670h.....5653
18.11.276Next Item Pointer #1 (PM_NEXT_MMIO)—Offset 8671h.........................5653
18.11.277Power Management Capabilities (PM_CAP_MMIO)—Offset 8672h ............5654
18.11.278Power Management Control/Status (PM_CS_MMIO)—Offset 8674h .........5655
18.11.279Message Signaled Interrupt CID (MSI_CID_MMIO)—Offset 8680h...........5656
18.11.280Next item pointer (MSI_NEXT_MMIO)—Offset 8681h.............................5657
18.11.281Message Signaled Interrupt Message Control (MSI_MCTL_MMIO)—Offset
8682h................................................................................................5657
18.11.282Message Signaled Interrupt Message Address (MSI_MAD_MMIO)—Offset 8684h
5658
18.11.283Message Signaled Interrupt Upper Address (MSI_MUAD_MMIO)—Offset 8688h
5659
18.11.284Message Signaled Interrupt Message Data (MSI_MD_MMIO)—Offset 868Ch ....
5659
18.11.285Device Idle Capability (DEVIDLE_MMIO)—Offset 8690h .........................5660
18.11.286Vendor Specific Header (VSHDR_MMIO)—Offset 8694h .........................5660
18.11.287SW LTR POINTER (SWLTRPTR_MMIO)—Offset 8698h ............................5661
18.11.288Device Idle Pointer Register (DEVIDLEPTR_MMIO)—Offset 869Ch ...........5662
18.11.289Device Idle Power ON Latency (DEVIDLEPOL_MMIO)—Offset 86A0h ........5663
18.11.290High Speed Configuration 2 (HSCFG2_MMIO)—Offset 86A4h..................5664
18.11.291XHCI USB2 Overcurrent Pin Mapping 1 (U2OCM1_MMIO)—Offset 86B0h ..5665
18.11.292XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM2_MMIO)—Offset 86B4h ..5666
18.11.293XHCI USB3 Overcurrent Pin Mapping 1 (U3OCM1_MMIO)—Offset 86D0h..5666
18.11.294XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM2_MMIO)—Offset 86D4h..5667
18.11.295XHCC3 (XHCC3_MMIO)—Offset 86FCh ................................................5667
18.11.296Debug Capability ID Register (DCID)—Offset 8700h..............................5668
18.11.297Debug Capability Doorbell Register (DCDB)—Offset 8704h.....................5669
18.11.298Debug Capability Event Ring Segment Table Size Register (DCERSTSZ)—Offset
8708h................................................................................................5669
18.11.299Debug Capability Event Ring Segment Table Base Address Register
(DCERSTBA)—Offset 8710h ..................................................................5670
18.11.300Debug Capability Event Ring Dequeue Pointer Register (DCERDP)—Offset
8718h................................................................................................5670
18.11.301Debug Capability Control Register (DCCTRL)—Offset 8720h ...................5671
18.11.302Debug Capability Status Register (DCST)—Offset 8724h........................5672
18.11.303Debug Capability Port Status and Control Register (DCPORTSC)—Offset 8728h
5673
18.11.304Debug Capability Context Pointer Register (DCCP)—Offset 8730h ...........5675
18.11.305Debug Capability Device Descriptor Info Register 1 (DCDDI1)—Offset 8738h ..
5675
18.11.306Debug Capability Device Descriptor Info Register 2 (DCDDI2)—Offset 873Ch ..
5676
18.11.307Debug Capability Descriptor Parameters (DCDP)—Offset 8740h ..............5676
18.11.308 .....................................................................................................5677
18.11.309Debug Device Control ODMA (DBGDEV_CTRL_ODMA_REG)—Offset 8748h ......
5677
18.11.310DBC Control Register 1 (DBCCTL_REG)—Offset 8760h ..........................5678
18.11.311(PORT1_PROFILE_ATTRIBUTES_REG0)—Offset 890Ch...........................5679
18.11.312(PORT1_PROFILE_ATTRIBUTES_REG1)—Offset 8910h...........................5679

334818 141
 18.11.313(PORT1_PROFILE_ATTRIBUTES_REG2)—Offset 8914h .......................... 5680
18.11.314(PORT1_PROFILE_ATTRIBUTES_REG3)—Offset 8918h .......................... 5681
18.11.315(PORT1_PROFILE_ATTRIBUTES_REG4)—Offset 891Ch .......................... 5681
18.11.316(PORT1_PROFILE_ATTRIBUTES_REG5)—Offset 8920h .......................... 5682
18.11.317(PORT1_PROFILE_ATTRIBUTES_REG6)—Offset 8924h .......................... 5683
18.11.318(PORT1_PROFILE_ATTRIBUTES_REG7)—Offset 8928h .......................... 5683
18.11.319(PORT1_PROFILE_ATTRIBUTES_REG8)—Offset 892Ch .......................... 5684
18.11.320(PORT1_PROFILE_ATTRIBUTES_REG9)—Offset 8930h .......................... 5685
18.11.321(PORT1_PROFILE_ATTRIBUTES_REG10)—Offset 8934h ........................ 5685
18.11.322(PORT1_PROFILE_ATTRIBUTES_REG11)—Offset 8938h ........................ 5686
18.11.323(PORT1_PROFILE_ATTRIBUTES_REG12)—Offset 893Ch ........................ 5687
18.11.324(PORT1_PROFILE_ATTRIBUTES_REG13)—Offset 8940h ........................ 5687
18.11.325(PORT1_PROFILE_ATTRIBUTES_REG14)—Offset 8944h ........................ 5688
18.11.326(PORT1_PROFILE_ATTRIBUTES_REG15)—Offset 8948h ........................ 5689
18.11.327(PORT1_PROFILE_ATTRIBUTES_REG16)—Offset 894Ch ........................ 5689
18.11.328(PORT1_PROFILE_ATTRIBUTES_REG17)—Offset 8950h ........................ 5690
18.11.329(PORT1_PROFILE_ATTRIBUTES_REG18)—Offset 8954h ........................ 5691
18.11.330(PORT1_PROFILE_ATTRIBUTES_REG19)—Offset 8958h ........................ 5691
18.11.331(PORT1_PROFILE_ATTRIBUTES_REG20)—Offset 895Ch ........................ 5692
18.11.332(PORT1_PROFILE_ATTRIBUTES_REG21)—Offset 8960h ........................ 5693
18.11.333(PORT1_PROFILE_ATTRIBUTES_REG22)—Offset 8964h ........................ 5693
18.11.334(PORT1_PROFILE_ATTRIBUTES_REG23)—Offset 8968h ........................ 5694
18.11.335(PORT1_PROFILE_ATTRIBUTES_REG24)—Offset 896Ch ........................ 5695
18.11.336(PORT1_PROFILE_ATTRIBUTES_REG25)—Offset 8970h ........................ 5695
18.11.337(PORT1_PROFILE_ATTRIBUTES_REG26)—Offset 8974h ........................ 5696
18.11.338(PORT1_PROFILE_ATTRIBUTES_REG27)—Offset 8978h ........................ 5697
18.11.339(PORT1_PROFILE_ATTRIBUTES_REG28)—Offset 897Ch ........................ 5697
18.11.340(PORT1_PROFILE_ATTRIBUTES_REG29)—Offset 8980h ........................ 5698
18.11.341(PORT1_PROFILE_ATTRIBUTES_REG30)—Offset 8984h ........................ 5699
18.11.342(PORT1_PROFILE_ATTRIBUTES_REG31)—Offset 8988h ........................ 5699
18.11.343(PORT1_PROFILE_ATTRIBUTES_REG32)—Offset 898Ch ........................ 5700
18.11.344(PORT1_PROFILE_ATTRIBUTES_REG33)—Offset 8990h ........................ 5701
18.11.345(PORT1_PROFILE_ATTRIBUTES_REG34)—Offset 8994h ........................ 5701
18.11.346(PORT1_PROFILE_ATTRIBUTES_REG35)—Offset 8998h ........................ 5702
18.11.347(PORT1_PROFILE_ATTRIBUTES_REG36)—Offset 899Ch ........................ 5703
18.11.348(PORT1_PROFILE_ATTRIBUTES_REG37)—Offset 89A0h ........................ 5703
18.11.349(PORT1_PROFILE_ATTRIBUTES_REG38)—Offset 89A4h ........................ 5704
18.11.350(PORT1_PROFILE_ATTRIBUTES_REG39)—Offset 89A8h ........................ 5705
18.11.351(PORT1_PROFILE_ATTRIBUTES_REG40)—Offset 89ACh ........................ 5705
18.11.352(PORT1_PROFILE_ATTRIBUTES_REG41)—Offset 89B0h ........................ 5706
18.11.353(PORT1_PROFILE_ATTRIBUTES_REG42)—Offset 89B4h ........................ 5707
18.11.354(PORT1_PROFILE_ATTRIBUTES_REG43)—Offset 89B8h ........................ 5707
18.11.355(PORT1_PROFILE_ATTRIBUTES_REG44)—Offset 89BCh ........................ 5708
18.11.356(PORT1_PROFILE_ATTRIBUTES_REG45)—Offset 89C0h ........................ 5709
18.11.357(PORT1_PROFILE_ATTRIBUTES_REG46)—Offset 89C4h ........................ 5709
18.11.358(PORT1_PROFILE_ATTRIBUTES_REG47)—Offset 89C8h ........................ 5710
18.11.359(PORT1_PROFILE_ATTRIBUTES_REG48)—Offset 89CCh ........................ 5711
18.11.360(PORT1_PROFILE_ATTRIBUTES_REG49)—Offset 89D0h ........................ 5711
18.11.361(PORT1_PROFILE_ATTRIBUTES_REG50)—Offset 89D4h ........................ 5712
18.11.362(PORT1_PROFILE_ATTRIBUTES_REG51)—Offset 89D8h ........................ 5713
18.11.363(PORT1_PROFILE_ATTRIBUTES_REG52)—Offset 89DCh ........................ 5713
18.11.364(PORT1_PROFILE_ATTRIBUTES_REG53)—Offset 89E0h ........................ 5714
18.11.365(PORT1_PROFILE_ATTRIBUTES_REG54)—Offset 89E4h ........................ 5715
18.11.366(PORT1_PROFILE_ATTRIBUTES_REG55)—Offset 89E8h ........................ 5715
18.11.367(PORT1_PROFILE_ATTRIBUTES_REG56)—Offset 89ECh ........................ 5716

142 334818
 18.11.368(PORT1_PROFILE_ATTRIBUTES_REG57)—Offset 89F0h .........................5717
18.11.369(PORT1_PROFILE_ATTRIBUTES_REG58)—Offset 89F4h .........................5717
18.11.370(PORT1_PROFILE_ATTRIBUTES_REG59)—Offset 89F8h .........................5718
18.11.371(PORT1_PROFILE_ATTRIBUTES_REG60)—Offset 89FCh .........................5719
18.11.372(PORT1_PROFILE_ATTRIBUTES_REG61)—Offset 8A00h .........................5719
18.11.373(PORT1_PROFILE_ATTRIBUTES_REG62)—Offset 8A04h .........................5720
18.11.374(PORT1_PROFILE_ATTRIBUTES_REG63)—Offset 8A08h .........................5721
18.11.375GLOBAL_TIME_SYNC_CAP_REG (GLOBAL_TIME_SYNC_CAP_REG)—Offset
8E10h................................................................................................5721
18.11.376GLOBAL_TIME_SYNC_CTRL_REG (GLOBAL_TIME_SYNC_CTRL_REG)—Offset
8E14h................................................................................................5722
18.11.377MICROFRAME_TIME_REG (MICROFRAME_TIME_REG)—Offset 8E18h .......5723
18.11.378GLOBAL_TIME_LOW_REG (GLOBAL_TIME_LOW_REG)—Offset 8E20h ......5723
18.11.379GLOBAL_TIME_HI_REG (GLOBAL_TIME_HI_REG)—Offset 8E24h ............5724
18.11.380Debug Status Capability Register (DEBUG_STATUS_CAPABILITY_REG)—Offset
8E58h................................................................................................5725
18.11.381Host Ctrl USB3 Soft Error Count Register 1
(HOST_CTRL_USB3_ERR_COUNT_REG1)—Offset 8E5Ch ...........................5725
18.11.382Host Ctrl USB3 Soft Error Count Register 2
(HOST_CTRL_USB3_ERR_COUNT_REG2)—Offset 8E60h ...........................5726
18.11.383Host Ctrl USB3 Soft Error Count Register 3
(HOST_CTRL_USB3_ERR_COUNT_REG3)—Offset 8E64h ...........................5726
18.11.384Host Ctrl USB3 Soft Error Count Register 4
(HOST_CTRL_USB3_ERR_COUNT_REG4)—Offset 8E68h ...........................5727
18.11.385Host Ctrl USB3 Soft Error Count Register 5
(HOST_CTRL_USB3_ERR_COUNT_REG5)—Offset 8E6Ch ...........................5728
18.11.386Host Ctrl USB3 Soft Error Count Register 6
(HOST_CTRL_USB3_ERR_COUNT_REG6)—Offset 8E70h ...........................5728
18.11.387Host Ctrl USB3 Soft Error Count Register 7
(HOST_CTRL_USB3_ERR_COUNT_REG7)—Offset 8E74h ...........................5729
18.11.388IOSFCTL - Control Register (IOSFCTL)—Offset 0h .................................5729
18.11.389Power Management Control Register (PMCTL)—Offset 1D0h...................5730
18.11.390PCI Configuration Control 1 Register (PCICFGCTR1)—Offset 200h ...........5731
18.11.391c73usb280_USB2 PER PORT (USB2_PER_PORT_PP0)—Offset 4100h .......5731
18.11.392GLB ADP VBUS COMP REG (GLB_ADP_VBUS_COMP_REG)—Offset 402Bh.5735
18.11.393c73usb280_USB2 COMPBG (USB2_COMPBG)—Offset 7F04h ..................5737
18.11.394CONFIG_3—Offset 7014h ..................................................................5740
18.11.395DBC_GP2_IN_PAYLOAD_BP_LOW—Offset 1Ch .....................................5741
18.11.396DBC_GP2_IN_PAYLOAD_BP_HI—Offset 20h .........................................5741
18.11.397DBC_GP2_IN_PAYLOAD_QUALIFIERS—Offset 24h ................................5741
18.11.398DBC_GP2_IN_STATUS_QUALIFIERS—Offset 34h ..................................5742
18.11.399DBC_GP2_IN_STATUS_BP_LOW—Offset 2Ch .......................................5742
18.11.400DBC_GP2_IN_STATUS_BP_HI—Offset 30h...........................................5743
18.11.401Host Control IDMA (HOST_CTRL_IDMA_REG)—Offset 809Ch ..................5743
18.11.402Host Control Transfer Manager (HOST_CTRL_TRM_REG2) —Offset 8110h 5746
18.11.403Command Manager Control 1 (XECP_CMDM_CTRL_REG1) —Offset 818Ch5749
18.11.404Command Manager Control 2 (XECP_CMDM_CTRL_REG2) —Offset 8190h 5751
18.11.405Command Manager Control 3 (XECP_CMDM_CTRL_REG3) —Offset 8194h 5753
18.11.406Power Control Enable (PCE_REG) —Offset 00A2h .................................5754
18.11.407GEN_REGRW4 —Offset 00BCh ...........................................................5754
18.12 Registers Summary ........................................................................................5757
18.12.1Vendor ID (VID)—Offset 0h ..................................................................5758
18.12.2Device ID (DID)—Offset 2h...................................................................5758
18.12.3Command (CMD)—Offset 4h .................................................................5759
18.12.4Device Status (STS)—Offset 6h .............................................................5760
18.12.5Revision ID (RID)—Offset 8h ................................................................5761

334818 143
 18.12.6Programming Interface (PI)—Offset 9h .................................................. 5761
18.12.7Sub Class Code (SCC)—Offset Ah.......................................................... 5762
18.12.8Base Class Code (BCC)—Offset Bh ........................................................ 5762
18.12.9Master Latency Timer (MLT)—Offset Dh ................................................. 5763
18.12.10Header Type (HT)—Offset Eh .............................................................. 5763
18.12.11Memory Base Address (MBAR)—Offset 10h ........................................... 5763
18.12.12USB Subsystem Vendor ID (SSVID)—Offset 2Ch.................................... 5764
18.12.13USB Subsystem ID (SSID)—Offset 2Eh ................................................ 5765
18.12.14Capabilities Pointer (CAP_PTR)—Offset 34h........................................... 5765
18.12.15Interrupt Line (ILINE)—Offset 3Ch....................................................... 5766
18.12.16Interrupt Pin (IPIN)—Offset 3Dh.......................................................... 5766
18.12.17XHC System Bus Configuration 1 (XHCC1)—Offset 40h........................... 5766
18.12.18Clock Gating (XHCLKGTEN)—Offset 50h ............................................... 5768
18.12.19Audio Time Synchronization (AUDSYNC)—Offset 58h.............................. 5771
18.12.20Serial Bus Release Number (SBRN)—Offset 60h .................................... 5772
18.12.21Frame Length Adjustment (FLADJ)—Offset 61h ..................................... 5772
18.12.22Best Effort Service Latency (BESL)—Offset 62h ..................................... 5773
18.12.23PCI Power Management Capability ID (PM_CID)—Offset 70h ................... 5774
18.12.24Next Item Pointer #1 (PM_NEXT)—Offset 71h ....................................... 5774
18.12.25Power Management Capabilities (PM_CAP)—Offset 72h........................... 5775
18.12.26Power Management Control/Status (PM_CS)—Offset 74h ........................ 5776
18.12.27Message Signaled Interrupt CID (MSI_CID)—Offset 80h ......................... 5777
18.12.28Next item pointer (MSI_NEXT)—Offset 81h ........................................... 5778
18.12.29Message Signaled Interrupt Message Control (MSI_MCTL)—Offset 82h ..... 5778
18.12.30Message Signaled Interrupt Message Address (MSI_MAD)—Offset 84h ..... 5779
18.12.31Message Signaled Interrupt Upper Address (MSI_MUAD)—Offset 88h ....... 5779
18.12.32Message Signaled Interrupt Message Data (MSI_MD)—Offset 8Ch............ 5780
18.12.33Device Idle Capability (DEVIDLE)—Offset 90h ....................................... 5780
18.12.34Vendor Specific Header (VSHDR)—Offset 94h........................................ 5781
18.12.35SW LTR POINTER (SWLTRPTR)—Offset 98h........................................... 5782
18.12.36Device Idle Pointer Register (DEVIDLEPTR)—Offset 9Ch.......................... 5783
18.12.37Device Idle Power ON Latency (DEVIDLEPOL)—Offset A0h ...................... 5783
18.12.38High Speed Configuration 2 (HSCFG2)—Offset A4h ................................ 5784
18.12.39XHCI USB2 Overcurrent Pin Mapping 1 (U2OCM1)—Offset B0h ................ 5785
18.12.40XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM2)—Offset B4h ................ 5786
18.12.41XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM3)—Offset B8h ................ 5786
18.12.42XHCI USB2 Overcurrent Pin Mapping 2 (U2OCM4)—Offset BCh ................ 5787
18.12.43XHCI USB3 Overcurrent Pin Mapping 1 (U3OCM1)—Offset D0h ................ 5787
18.12.44XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM2)—Offset D4h ................ 5788
18.12.45XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM3)—Offset D8h ................ 5788
18.12.46XHCI USB3 Overcurrent Pin Mapping 2 (U3OCM4)—Offset DCh................ 5789
18.12.47XHCC3 (XHCC3)—Offset FCh............................................................... 5789
18.13 Registers Summary........................................................................................ 5791
18.13.1DBC_GP2_OUT_PAYLOAD_BP_LOW (DBC_GP2_OUT_PAYLOAD_BP_LOW)—
Offset 0h ........................................................................................... 5798
18.13.2DBC_GP2_OUT_PAYLOAD_BP_HI (DBC_GP2_OUT_PAYLOAD_BP_HI)—Offset 4h
5799
18.13.3DBC_GP2_OUT_PAYLOAD_QUALIFIERS
(DBC_GP2_OUT_PAYLOAD_QUALIFIERS)—Offset 8h................................ 5799
18.13.4DBC_GP2_OUT_PAYLOAD_TRANSFER_LENGTH
(DBC_GP2_OUT_PAYLOAD_TRANSFER_LENGTH)—Offset Ch ..................... 5800
18.13.5DBC_GP2_OUT_STATUS_BP_LOW (DBC_GP2_OUT_STATUS_BP_LOW)—Offset
10h................................................................................................... 5801
18.13.6DBC_GP2_OUT_STATUS_BP_HI (DBC_GP2_OUT_STATUS_BP_HI)—Offset 14h ..
5801

144 334818
 18.13.7DBC_GP2_OUT_STATUS_QUALIFIERS (DBC_GP2_OUT_STATUS_QUALIFIERS)—
Offset 18h ..........................................................................................5802
18.13.8DBC_GP2_IN_PAYLOAD_BP_LOW (DBC_GP2_IN_PAYLOAD_BP_LOW)—Offset
1Ch ...................................................................................................5803
18.13.9DBC_GP2_IN_PAYLOAD_BP_HI (DBC_GP2_IN_PAYLOAD_BP_HI)—Offset 20h.....
5803
18.13.10DBC_GP2_IN_PAYLOAD_QUALIFIERS (DBC_GP2_IN_PAYLOAD_QUALIFIERS)—
Offset 24h ..........................................................................................5804
18.13.11DBC_GP2_IN_PAYLOAD_TRANSFER_LENGTH
(DBC_GP2_IN_PAYLOAD_TRANSFER_LENGTH)—Offset 28h ......................5805
18.13.12DBC_GP2_IN_STATUS_BP_LOW (DBC_GP2_IN_STATUS_BP_LOW)—Offset 2Ch
5805
18.13.13DBC_GP2_IN_STATUS_BP_HI (DBC_GP2_IN_STATUS_BP_HI)—Offset 30h 5806
18.13.14DBC_GP2_IN_STATUS_QUALIFIERS (DBC_GP2_IN_STATUS_QUALIFIERS)—
Offset 34h ..........................................................................................5807
18.13.15DBC_TRACE_IN_PAYLOAD_BP_LOW (DBC_TRACE_IN_PAYLOAD_BP_LOW)—
Offset 50h ..........................................................................................5807
18.13.16DBC_TRACE_IN_PAYLOAD_BP_HI (DBC_TRACE_IN_PAYLOAD_BP_HI)—Offset
54h ...................................................................................................5808
18.13.17DBC_TRACE_IN_PAYLOAD_QUALIFIERS
(DBC_TRACE_IN_PAYLOAD_QUALIFIERS)—Offset 58h .............................5809
18.13.18DBC_TRACE_IN_PAYLOAD_TRASNFER_DOORBELL
(DBC_TRACE_IN_PAYLOAD_TRANSFER_DOORBELL)—Offset 5Ch ...............5809
18.13.19DBC_TRACE_IN_STATUS_BP_LOW (DBC_TRACE_IN_STATUS_BP_LOW)—Offset
60h ...................................................................................................5810
18.13.20DBC_TRACE_IN_STATUS_BP_HI (DBC_TRACE_IN_STATUS_BP_HI)—Offset 64h
5811
18.13.21DBC_TRACE_IN_STATUS_QUALIFIERS
(DBC_TRACE_IN_STATUS_QUALIFIERS)—Offset 68h ...............................5811
18.13.22DBConEXI Capability Port Status and Control Register (DBC_EXI_DCPORTSC)—
Offset 88h ..........................................................................................5812
18.13.23DEBUG_SW_CONTROL_STATUS_REG (DEBUG_SW_CONTROL_STATUS_REG)—
Offset 100h ........................................................................................5814
18.13.24DEBUG_REQUEST_INFO_AND_STATUS_REG
(DEBUG_REQUEST_INFO_AND_STATUS_REG)—Offset 104h .....................5815
18.13.25DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_0)—Offset 108h .....
5817
18.13.26DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_1)—Offset 10Ch.....
5817
18.13.27DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_2)—Offset 110h .....
5818
18.13.28DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_3)—Offset 114h .....
5819
18.13.29DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_4)—Offset 118h .....
5819
18.13.30DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_5)—Offset 11Ch.....
5820
18.13.31DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_6)—Offset 120h .....
5821
18.13.32DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_7)—Offset 124h .....
5821
18.13.33DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_8)—Offset 128h .....
5822
18.13.34DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_9)—Offset 12Ch.....
5823
18.13.35DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_10)—Offset 130h ...
5823

334818 145
 18.13.36DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_11)—Offset 134h...
5824
18.13.37DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_12)—Offset 138h...
5825
18.13.38DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_13)—Offset 13Ch ..
5825
18.13.39DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_14)—Offset 140h...
5826
18.13.40DEBUG_REQUEST_STACK (DEBUG_REQUEST_STACK_REG_15)—Offset 144h...
5827
18.13.41DEBUG_RESPONSE_INFO_AND_STATUS_REG
(DEBUG_RESPONSE_INFO_AND_STATUS_REG)—Offset 148h ................... 5827
18.13.42DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_0)—Offset 180h ........................ 5828
18.13.43DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_1)—Offset 184h ........................ 5829
18.13.44DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_2)—Offset 188h ........................ 5829
18.13.45DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_3)—Offset 18Ch ........................ 5830
18.13.46DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_4)—Offset 190h ........................ 5830
18.13.47DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_5)—Offset 194h ........................ 5831
18.13.48DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_6)—Offset 198h ........................ 5831
18.13.49DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_7)—Offset 19Ch ........................ 5832
18.13.50DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_8)—Offset 1A0h ........................ 5833
18.13.51DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_9)—Offset 1A4h ........................ 5833
18.13.52DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_10)—Offset 1A8h ...................... 5834
18.13.53DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_11)—Offset 1ACh ...................... 5834
18.13.54DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_12)—Offset 1B0h ...................... 5835
18.13.55DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_13)—Offset 1B4h ...................... 5836
18.13.56DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_14)—Offset 1B8h ...................... 5836
18.13.57DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_15)—Offset 1BCh ...................... 5837
18.13.58DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_16)—Offset 1C0h ...................... 5837
18.13.59DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_17)—Offset 1C4h ...................... 5838
18.13.60DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_18)—Offset 1C8h ...................... 5839
18.13.61DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_19)—Offset 1CCh ...................... 5839
18.13.62DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_20)—Offset 1D0h ...................... 5840
18.13.63DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_21)—Offset 1D4h ...................... 5840

146 334818
 18.13.64DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_22)—Offset 1D8h .......................5841
18.13.65DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_23)—Offset 1DCh.......................5842
18.13.66DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_24)—Offset 1E0h .......................5842
18.13.67DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_25)—Offset 1E4h .......................5843
18.13.68DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_26)—Offset 1E8h .......................5843
18.13.69DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_27)—Offset 1ECh .......................5844
18.13.70DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_28)—Offset 1F0h .......................5845
18.13.71DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_29)—Offset 1F4h .......................5845
18.13.72DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_30)—Offset 1F8h .......................5846
18.13.73DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_31)—Offset 1FCh .......................5846
18.13.74DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_32)—Offset 200h .......................5847
18.13.75DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_33)—Offset 204h .......................5848
18.13.76DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_34)—Offset 208h .......................5848
18.13.77DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_35)—Offset 20Ch .......................5849
18.13.78DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_36)—Offset 210h .......................5849
18.13.79DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_37)—Offset 214h .......................5850
18.13.80DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_38)—Offset 218h .......................5851
18.13.81DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_39)—Offset 21Ch .......................5851
18.13.82DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_40)—Offset 220h .......................5852
18.13.83DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_41)—Offset 224h .......................5852
18.13.84DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_42)—Offset 228h .......................5853
18.13.85DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_43)—Offset 22Ch .......................5854
18.13.86DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_44)—Offset 230h .......................5854
18.13.87DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_45)—Offset 234h .......................5855
18.13.88DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_46)—Offset 238h .......................5855
18.13.89DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_47)—Offset 23Ch .......................5856
18.13.90DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_48)—Offset 240h .......................5857
18.13.91DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_49)—Offset 244h .......................5857

334818 147
 18.13.92DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_50)—Offset 248h....................... 5858
18.13.93DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_51)—Offset 24Ch ...................... 5858
18.13.94DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_52)—Offset 250h....................... 5859
18.13.95DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_53)—Offset 254h....................... 5860
18.13.96DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_54)—Offset 258h....................... 5860
18.13.97DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_55)—Offset 25Ch ...................... 5861
18.13.98DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_56)—Offset 260h....................... 5861
18.13.99DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_57)—Offset 264h....................... 5862
18.13.100DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_58)—Offset 268h....................... 5863
18.13.101DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_59)—Offset 26Ch ...................... 5863
18.13.102DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_60)—Offset 270h....................... 5864
18.13.103DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_61)—Offset 274h....................... 5864
18.13.104DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_62)—Offset 278h....................... 5865
18.13.105DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_63)—Offset 27Ch ...................... 5866
18.13.106DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_64)—Offset 280h....................... 5866
18.13.107DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_65)—Offset 284h....................... 5867
18.13.108DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_66)—Offset 288h....................... 5867
18.13.109DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_67)—Offset 28Ch ...................... 5868
18.13.110DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_68)—Offset 290h....................... 5869
18.13.111DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_69)—Offset 294h....................... 5869
18.13.112DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_70)—Offset 298h....................... 5870
18.13.113DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_71)—Offset 29Ch ...................... 5870
18.13.114DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_72)—Offset 2A0h ...................... 5871
18.13.115DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_73)—Offset 2A4h ...................... 5872
18.13.116DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_74)—Offset 2A8h ...................... 5872
18.13.117DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_75)—Offset 2ACh ...................... 5873
18.13.118DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_76)—Offset 2B0h ...................... 5873
18.13.119DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_77)—Offset 2B4h ...................... 5874

148 334818
 18.13.120DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_78)—Offset 2B8h .......................5875
18.13.121DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_79)—Offset 2BCh .......................5875
18.13.122DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_80)—Offset 2C0h .......................5876
18.13.123DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_81)—Offset 2C4h .......................5876
18.13.124DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_82)—Offset 2C8h .......................5877
18.13.125DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_83)—Offset 2CCh .......................5878
18.13.126DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_84)—Offset 2D0h .......................5878
18.13.127DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_85)—Offset 2D4h .......................5879
18.13.128DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_86)—Offset 2D8h .......................5879
18.13.129DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_87)—Offset 2DCh.......................5880
18.13.130DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_88)—Offset 2E0h .......................5881
18.13.131DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_89)—Offset 2E4h .......................5881
18.13.132DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_90)—Offset 2E8h .......................5882
18.13.133DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_91)—Offset 2ECh .......................5882
18.13.134DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_92)—Offset 2F0h .......................5883
18.13.135DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_93)—Offset 2F4h .......................5884
18.13.136DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_94)—Offset 2F8h .......................5884
18.13.137DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_95)—Offset 2FCh .......................5885
18.13.138DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_96)—Offset 300h .......................5885
18.13.139DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_97)—Offset 304h .......................5886
18.13.140DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_98)—Offset 308h .......................5887
18.13.141DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_99)—Offset 30Ch .......................5887
18.13.142DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_100)—Offset 310h .....................5888
18.13.143DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_101)—Offset 314h .....................5889
18.13.144DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_102)—Offset 318h .....................5889
18.13.145DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_103)—Offset 31Ch .....................5890
18.13.146DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_104)—Offset 320h .....................5891
18.13.147DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_105)—Offset 324h .....................5891

334818 149
 18.13.148DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_106)—Offset 328h ..................... 5892
18.13.149DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_107)—Offset 32Ch..................... 5893
18.13.150DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_108)—Offset 330h ..................... 5893
18.13.151DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_109)—Offset 334h ..................... 5894
18.13.152DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_110)—Offset 338h ..................... 5895
18.13.153DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_111)—Offset 33Ch..................... 5895
18.13.154DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_112)—Offset 340h ..................... 5896
18.13.155DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_113)—Offset 344h ..................... 5897
18.13.156DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_114)—Offset 348h ..................... 5897
18.13.157DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_115)—Offset 34Ch..................... 5898
18.13.158DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_116)—Offset 350h ..................... 5899
18.13.159DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_117)—Offset 354h ..................... 5899
18.13.160DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_118)—Offset 358h ..................... 5900
18.13.161DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_119)—Offset 35Ch..................... 5901
18.13.162DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_120)—Offset 360h ..................... 5901
18.13.163DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_121)—Offset 364h ..................... 5902
18.13.164DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_122)—Offset 368h ..................... 5903
18.13.165DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_123)—Offset 36Ch..................... 5903
18.13.166DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_124)—Offset 370h ..................... 5904
18.13.167DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_125)—Offset 374h ..................... 5905
18.13.168DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_126)—Offset 378h ..................... 5905
18.13.169DEBUG_RESPONSE_DATA_STACK
(DEBUG_RESPONSE_DATA_STACK_REG_127)—Offset 37Ch..................... 5906
18.13.170DEBUG_RESPONSE_HEADER_STACK_REG
(DEBUG_RESPONSE_HEADER_STACK_REG_0)—Offset 380h .................... 5907
18.13.171DEBUG_RESPONSE_HEADER_STACK_REG
(DEBUG_RESPONSE_HEADER_STACK_REG_1)—Offset 384h .................... 5907
18.13.172DEBUG_RESPONSE_HEADER_STACK_REG
(DEBUG_RESPONSE_HEADER_STACK_REG_2)—Offset 388h .................... 5908
18.14 Registers Summary........................................................................................ 5909
18.14.1DCFG (DCFG)—Offset C700h ................................................................ 5912
18.14.2DCTL (DCTL)—Offset C704h ................................................................. 5913
18.14.3DEVTEN (DEVTEN)—Offset C708h ......................................................... 5914
18.14.4DSTS (DSTS)—Offset C70Ch ................................................................ 5915
18.14.5DGCMDPAR (DGCMDPAR)—Offset C710h ............................................... 5916
18.14.6DGCMD (DGCMD)—Offset C714h .......................................................... 5917

150 334818
 18.14.7DALEPENA (DALEPENA)—Offset C720h ...................................................5917
18.14.8DEPCMDPAR2_0 (DEPCMDPAR2_0)—Offset C800h ...................................5918
18.14.9DEPCMDPAR1_0 (DEPCMDPAR1_0)—Offset C804h ...................................5918
18.14.10DEPCMDPAR0_0 (DEPCMDPAR0_0)—Offset C808h .................................5919
18.14.11DEPCMD_0 (DEPCMD_0)—Offset C80Ch................................................5919
18.14.12DEPCMDPAR2_1 (DEPCMDPAR2_1)—Offset C810h .................................5920
18.14.13DEPCMDPAR1_1 (DEPCMDPAR1_1)—Offset C814h .................................5921
18.14.14DEPCMDPAR0_1 (DEPCMDPAR0_1)—Offset C818h .................................5921
18.14.15DEPCMD_1 (DEPCMD_1)—Offset C81Ch................................................5922
18.14.16DEPCMDPAR2_2 (DEPCMDPAR2_2)—Offset C820h .................................5922
18.14.17DEPCMDPAR1_2 (DEPCMDPAR1_2)—Offset C824h .................................5923
18.14.18DEPCMDPAR0_2 (DEPCMDPAR0_2)—Offset C828h .................................5923
18.14.19DEPCMD_2 (DEPCMD_2)—Offset C82Ch................................................5924
18.14.20DEPCMDPAR2_3 (DEPCMDPAR2_3)—Offset C830h .................................5925
18.14.21DEPCMDPAR1_3 (DEPCMDPAR1_3)—Offset C834h .................................5925
18.14.22DEPCMDPAR0_3 (DEPCMDPAR0_3)—Offset C838h .................................5926
18.14.23DEPCMD_3 (DEPCMD_3)—Offset C83Ch................................................5926
18.14.24DEPCMDPAR2_4 (DEPCMDPAR2_4)—Offset C840h .................................5927
18.14.25DEPCMDPAR1_4 (DEPCMDPAR1_4)—Offset C844h .................................5927
18.14.26DEPCMDPAR0_4 (DEPCMDPAR0_4)—Offset C848h .................................5928
18.14.27DEPCMD_4 (DEPCMD_4)—Offset C84Ch................................................5928
18.14.28DEPCMDPAR2_5 (DEPCMDPAR2_5)—Offset C850h .................................5929
18.14.29DEPCMDPAR1_5 (DEPCMDPAR1_5)—Offset C854h .................................5930
18.14.30DEPCMDPAR0_5 (DEPCMDPAR0_5)—Offset C858h .................................5930
18.14.31DEPCMD_5 (DEPCMD_5)—Offset C85Ch................................................5931
18.14.32DEPCMDPAR2_6 (DEPCMDPAR2_6)—Offset C860h .................................5931
18.14.33DEPCMDPAR1_6 (DEPCMDPAR1_6)—Offset C864h .................................5932
18.14.34DEPCMDPAR0_6 (DEPCMDPAR0_6)—Offset C868h .................................5932
18.14.35DEPCMD_6 (DEPCMD_6)—Offset C86Ch................................................5933
18.14.36DEPCMDPAR2_7 (DEPCMDPAR2_7)—Offset C870h .................................5934
18.14.37DEPCMDPAR1_7 (DEPCMDPAR1_7)—Offset C874h .................................5934
18.14.38DEPCMDPAR0_7 (DEPCMDPAR0_7)—Offset C878h .................................5935
18.14.39DEPCMD_7 (DEPCMD_7)—Offset C87Ch................................................5935
18.14.40DEPCMDPAR2_8 (DEPCMDPAR2_8)—Offset C880h .................................5936
18.14.41DEPCMDPAR1_8 (DEPCMDPAR1_8)—Offset C884h .................................5936
18.14.42DEPCMDPAR0_8 (DEPCMDPAR0_8)—Offset C888h .................................5937
18.14.43DEPCMD_8 (DEPCMD_8)—Offset C88Ch................................................5937
18.14.44DEPCMDPAR2_9 (DEPCMDPAR2_9)—Offset C890h .................................5938
18.14.45DEPCMDPAR1_9 (DEPCMDPAR1_9)—Offset C894h .................................5939
18.14.46DEPCMDPAR0_9 (DEPCMDPAR0_9)—Offset C898h .................................5939
18.14.47DEPCMD_9 (DEPCMD_9)—Offset C89Ch................................................5940
18.14.48DEPCMDPAR2_10 (DEPCMDPAR2_10)—Offset C8A0h ..............................5940
18.14.49DEPCMDPAR1_10 (DEPCMDPAR1_10)—Offset C8A4h ..............................5941
18.14.50DEPCMDPAR0_10 (DEPCMDPAR0_10)—Offset C8A8h ..............................5941
18.14.51DEPCMD_10 (DEPCMD_10)—Offset C8ACh ............................................5942
18.14.52DEPCMDPAR2_11 (DEPCMDPAR2_11)—Offset C8B0h ..............................5943
18.14.53DEPCMDPAR1_11 (DEPCMDPAR1_11)—Offset C8B4h ..............................5943
18.14.54DEPCMDPAR0_11 (DEPCMDPAR0_11)—Offset C8B8h ..............................5944
18.14.55DEPCMD_11 (DEPCMD_11)—Offset C8BCh ............................................5944
18.14.56DEPCMDPAR2_12 (DEPCMDPAR2_12)—Offset C8C0h..............................5945
18.14.57DEPCMDPAR1_12 (DEPCMDPAR1_12)—Offset C8C4h..............................5945
18.14.58DEPCMDPAR0_12 (DEPCMDPAR0_12)—Offset C8C8h..............................5946
18.14.59DEPCMD_12 (DEPCMD_12)—Offset C8CCh ............................................5946
18.14.60DEPCMDPAR2_13 (DEPCMDPAR2_13)—Offset C8D0h..............................5947
18.14.61DEPCMDPAR1_13 (DEPCMDPAR1_13)—Offset C8D4h..............................5948

334818 151
 18.14.62DEPCMDPAR0_13 (DEPCMDPAR0_13)—Offset C8D8h ............................. 5948
18.14.63DEPCMD_13 (DEPCMD_13)—Offset C8DCh ........................................... 5949
18.14.64DEPCMDPAR2_14 (DEPCMDPAR2_14)—Offset C8E0h ............................. 5949
18.14.65DEPCMDPAR1_14 (DEPCMDPAR1_14)—Offset C8E4h ............................. 5950
18.14.66DEPCMDPAR0_14 (DEPCMDPAR0_14)—Offset C8E8h ............................. 5950
18.14.67DEPCMD_14 (DEPCMD_14)—Offset C8ECh............................................ 5951
18.14.68DEPCMDPAR2_15 (DEPCMDPAR2_15)—Offset C8F0h.............................. 5952
18.14.69DEPCMDPAR1_15 (DEPCMDPAR1_15)—Offset C8F4h.............................. 5952
18.14.70DEPCMDPAR0_15 (DEPCMDPAR0_15)—Offset C8F8h.............................. 5953
18.14.71DEPCMD_15 (DEPCMD_15)—Offset C8FCh............................................ 5953
18.14.72DEPCMDPAR2_16 (DEPCMDPAR2_16)—Offset C900h ............................. 5954
18.14.73DEPCMDPAR1_16 (DEPCMDPAR1_16)—Offset C904h ............................. 5954
18.14.74DEPCMDPAR0_16 (DEPCMDPAR0_16)—Offset C908h ............................. 5955
18.14.75DEPCMD_16 (DEPCMD_16)—Offset C90Ch............................................ 5955
18.14.76DEPCMDPAR2_17 (DEPCMDPAR2_17)—Offset C910h ............................. 5956
18.14.77DEPCMDPAR1_17 (DEPCMDPAR1_17)—Offset C914h ............................. 5957
18.14.78DEPCMDPAR0_17 (DEPCMDPAR0_17)—Offset C918h ............................. 5957
18.14.79DEPCMD_17 (DEPCMD_17)—Offset C91Ch............................................ 5958
18.14.80DEPCMDPAR2_18 (DEPCMDPAR2_18)—Offset C920h ............................. 5958
18.14.81DEPCMDPAR1_18 (DEPCMDPAR1_18)—Offset C924h ............................. 5959
18.14.82DEPCMDPAR0_18 (DEPCMDPAR0_18)—Offset C928h ............................. 5959
18.14.83DEPCMD_18 (DEPCMD_18)—Offset C92Ch............................................ 5960
18.14.84DEPCMDPAR2_19 (DEPCMDPAR2_19)—Offset C930h ............................. 5961
18.14.85DEPCMDPAR1_19 (DEPCMDPAR1_19)—Offset C934h ............................. 5961
18.14.86DEPCMDPAR0_19 (DEPCMDPAR0_19)—Offset C938h ............................. 5962
18.14.87DEPCMD_19 (DEPCMD_19)—Offset C93Ch............................................ 5962
18.14.88DEPCMDPAR2_20 (DEPCMDPAR2_20)—Offset C940h ............................. 5963
18.14.89DEPCMDPAR1_20 (DEPCMDPAR1_20)—Offset C944h ............................. 5963
18.14.90DEPCMDPAR0_20 (DEPCMDPAR0_20)—Offset C948h ............................. 5964
18.14.91DEPCMD_20 (DEPCMD_20)—Offset C94Ch............................................ 5964
18.14.92DEPCMDPAR2_21 (DEPCMDPAR2_21)—Offset C950h ............................. 5965
18.14.93DEPCMDPAR1_21 (DEPCMDPAR1_21)—Offset C954h ............................. 5966
18.14.94DEPCMDPAR0_21 (DEPCMDPAR0_21)—Offset C958h ............................. 5966
18.14.95DEPCMD_21 (DEPCMD_21)—Offset C95Ch............................................ 5967
18.14.96DEPCMDPAR2_22 (DEPCMDPAR2_22)—Offset C960h ............................. 5967
18.14.97DEPCMDPAR1_22 (DEPCMDPAR1_22)—Offset C964h ............................. 5968
18.14.98DEPCMDPAR0_22 (DEPCMDPAR0_22)—Offset C968h ............................. 5968
18.14.99DEPCMD_22 (DEPCMD_22)—Offset C96Ch............................................ 5969
18.14.100DEPCMDPAR2_23 (DEPCMDPAR2_23)—Offset C970h............................ 5970
18.14.101DEPCMDPAR1_23 (DEPCMDPAR1_23)—Offset C974h............................ 5970
18.14.102DEPCMDPAR0_23 (DEPCMDPAR0_23)—Offset C978h............................ 5971
18.14.103DEPCMD_23 (DEPCMD_23)—Offset C97Ch .......................................... 5971
18.14.104DEPCMDPAR2_24 (DEPCMDPAR2_24)—Offset C980h............................ 5972
18.14.105DEPCMDPAR1_24 (DEPCMDPAR1_24)—Offset C984h............................ 5972
18.14.106DEPCMDPAR0_24 (DEPCMDPAR0_24)—Offset C988h............................ 5973
18.14.107DEPCMD_24 (DEPCMD_24)—Offset C98Ch .......................................... 5973
18.14.108DEPCMDPAR2_25 (DEPCMDPAR2_25)—Offset C990h............................ 5974
18.14.109DEPCMDPAR1_25 (DEPCMDPAR1_25)—Offset C994h............................ 5975
18.14.110DEPCMDPAR0_25 (DEPCMDPAR0_25)—Offset C998h............................ 5975
18.14.111DEPCMD_25 (DEPCMD_25)—Offset C99Ch .......................................... 5976
18.14.112DEPCMDPAR2_26 (DEPCMDPAR2_26)—Offset C9A0h ........................... 5976
18.14.113DEPCMDPAR1_26 (DEPCMDPAR1_26)—Offset C9A4h ........................... 5977
18.14.114DEPCMDPAR0_26 (DEPCMDPAR0_26)—Offset C9A8h ........................... 5977
18.14.115DEPCMD_26 (DEPCMD_26)—Offset C9ACh.......................................... 5978
18.14.116DEPCMDPAR2_27 (DEPCMDPAR2_27)—Offset C9B0h ........................... 5979

152 334818
 18.14.117DEPCMDPAR1_27 (DEPCMDPAR1_27)—Offset C9B4h ............................5979
18.14.118DEPCMDPAR0_27 (DEPCMDPAR0_27)—Offset C9B8h ............................5980
18.14.119DEPCMD_27 (DEPCMD_27)—Offset C9BCh ..........................................5980
18.14.120DEPCMDPAR2_28 (DEPCMDPAR2_28)—Offset C9C0h ............................5981
18.14.121DEPCMDPAR1_28 (DEPCMDPAR1_28)—Offset C9C4h ............................5981
18.14.122DEPCMDPAR0_28 (DEPCMDPAR0_28)—Offset C9C8h ............................5982
18.14.123DEPCMD_28 (DEPCMD_28)—Offset C9CCh ..........................................5982
18.14.124DEPCMDPAR2_29 (DEPCMDPAR2_29)—Offset C9D0h ............................5983
18.14.125DEPCMDPAR1_29 (DEPCMDPAR1_29)—Offset C9D4h ............................5984
18.14.126DEPCMDPAR0_29 (DEPCMDPAR0_29)—Offset C9D8h ............................5984
18.14.127DEPCMD_29 (DEPCMD_29)—Offset C9DCh ..........................................5985
18.14.128DEPCMDPAR2_30 (DEPCMDPAR2_30)—Offset C9E0h ............................5985
18.14.129DEPCMDPAR1_30 (DEPCMDPAR1_30)—Offset C9E4h ............................5986
18.14.130DEPCMDPAR0_30 (DEPCMDPAR0_30)—Offset C9E8h ............................5986
18.14.131DEPCMD_30 (DEPCMD_30)—Offset C9ECh ..........................................5987
18.14.132DEPCMDPAR2_31 (DEPCMDPAR2_31)—Offset C9F0h ............................5988
18.14.133DEPCMDPAR1_31 (DEPCMDPAR1_31)—Offset C9F4h ............................5988
18.14.134DEPCMDPAR0_31 (DEPCMDPAR0_31)—Offset C9F8h ............................5989
18.14.135DEPCMD_31 (DEPCMD_31)—Offset C9FCh...........................................5989
18.15 Registers Summary ........................................................................................5991
18.15.1GSBUSCFG0 (GSBUSCFG0)—Offset C100h..............................................5992
18.15.2GSBUSCFG1 (GSBUSCFG1)—Offset C104h..............................................5993
18.15.3GTXTHRCFG (GTXTHRCFG)—Offset C108h ..............................................5994
18.15.4GRXTHRCFG (GRXTHRCFG)—Offset C10Ch .............................................5995
18.15.5GCTL (GCTL)—Offset C110h .................................................................5996
18.15.6GPMSTS (GPMSTS)—Offset C114h .........................................................5997
18.15.7GSTS (GSTS)—Offset C118h .................................................................5998
18.15.8GUCTL1 (GUCTL1)—Offset C11Ch..........................................................5999
18.15.9GSNPSID (GSNPSID)—Offset C120h ......................................................6000
18.15.10GGPIO (GGPIO)—Offset C124h ............................................................6000
18.15.11GUID (GUID)—Offset C128h................................................................6001
18.15.12GUCTL (GUCTL)—Offset C12Ch ............................................................6001
18.15.13GBUSERRADDRLO (GBUSERRADDRLO)—Offset C130h ............................6002
18.15.14GBUSERRADDRHI (GBUSERRADDRHI)—Offset C134h .............................6003
18.15.15GPRTBIMAPLO (GPRTBIMAPLO)—Offset C138h.......................................6003
18.15.16GPRTBIMAPHI (GPRTBIMAPHI)—Offset C13Ch .......................................6004
18.15.17GHWPARAMS0 (GHWPARAMS0)—Offset C140h ......................................6005
18.15.18GHWPARAMS1 (GHWPARAMS1)—Offset C144h ......................................6006
18.15.19GHWPARAMS2 (GHWPARAMS2)—Offset C148h ......................................6007
18.15.20GHWPARAMS3 (GHWPARAMS3)—Offset C14Ch ......................................6008
18.15.21GHWPARAMS4 (GHWPARAMS4)—Offset C150h ......................................6009
18.15.22GHWPARAMS5 (GHWPARAMS5)—Offset C154h ......................................6010
18.15.23GHWPARAMS6 (GHWPARAMS6)—Offset C158h ......................................6011
18.15.24GHWPARAMS7 (GHWPARAMS7)—Offset C15Ch ......................................6012
18.15.25GDBGFIFOSPACE (GDBGFIFOSPACE)—Offset C160h ...............................6013
18.15.26GDBGLTSSM (GDBGLTSSM)—Offset C164h ...........................................6013
18.15.27GDBGLNMCC (GDBGLNMCC)—Offset C168h...........................................6015
18.15.28GDBGBMU (GDBGBMU)—Offset C16Ch .................................................6015
18.15.29GDBGLSPMUX_DEV (GDBGLSPMUX_DEV)—Offset C170h ........................6016
18.15.30GDBGLSP (GDBGLSP)—Offset C174h ....................................................6016
18.15.31GDBGEPINFO0 (GDBGEPINFO0)—Offset C178h ......................................6017
18.15.32GDBGEPINFO1 (GDBGEPINFO1)—Offset C17Ch......................................6017
18.15.33GPRTBIMAP_HSLO (GPRTBIMAP_HSLO)—Offset C180h ...........................6018
18.15.34GPRTBIMAP_HSHI (GPRTBIMAP_HSHI)—Offset C184h ............................6019
18.15.35GPRTBIMAP_FSLO (GPRTBIMAP_FSLO)—Offset C188h ............................6019

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 18.15.36GPRTBIMAP_FSHI (GPRTBIMAP_FSHI)—Offset C18Ch ............................ 6020
18.15.37GUSB2PHYCFG_0 (GUSB2PHYCFG_0)—Offset C200h.............................. 6021
18.15.38GUSB2I2CCTL_0 (GUSB2I2CCTL_0)—Offset C240h................................ 6022
18.15.39GUSB2PHYACC_ULPI_0 (GUSB2PHYACC_ULPI_0)—Offset C280h ............. 6023
18.15.40GUSB3PIPECTL_0 (GUSB3PIPECTL_0)—Offset C2C0h ............................. 6024
18.15.41GTXFIFOSIZ0_0 (GTXFIFOSIZ0_0)—Offset C300h ................................. 6025
18.15.42GTXFIFOSIZ1_0 (GTXFIFOSIZ1_0)—Offset C304h ................................. 6026
18.15.43GTXFIFOSIZ2_0 (GTXFIFOSIZ2_0)—Offset C308h ................................. 6026
18.15.44GTXFIFOSIZ3_0 (GTXFIFOSIZ3_0)—Offset C30Ch ................................. 6027
18.15.45GTXFIFOSIZ4_0 (GTXFIFOSIZ4_0)—Offset C310h ................................. 6028
18.15.46GTXFIFOSIZ5_0 (GTXFIFOSIZ5_0)—Offset C314h ................................. 6028
18.15.47GTXFIFOSIZ6_0 (GTXFIFOSIZ6_0)—Offset C318h ................................. 6029
18.15.48GTXFIFOSIZ7_0 (GTXFIFOSIZ7_0)—Offset C31Ch ................................. 6029
18.15.49GTXFIFOSIZ8_0 (GTXFIFOSIZ8_0)—Offset C320h ................................. 6030
18.15.50GTXFIFOSIZ9_0 (GTXFIFOSIZ9_0)—Offset C324h ................................. 6030
18.15.51GTXFIFOSIZ10_0 (GTXFIFOSIZ10_0)—Offset C328h .............................. 6031
18.15.52GTXFIFOSIZ11_0 (GTXFIFOSIZ11_0)—Offset C32Ch.............................. 6031
18.15.53GTXFIFOSIZ12_0 (GTXFIFOSIZ12_0)—Offset C330h .............................. 6032
18.15.54GTXFIFOSIZ13_0 (GTXFIFOSIZ13_0)—Offset C334h .............................. 6032
18.15.55GTXFIFOSIZ14_0 (GTXFIFOSIZ14_0)—Offset C338h .............................. 6033
18.15.56GTXFIFOSIZ15_0 (GTXFIFOSIZ15_0)—Offset C33Ch.............................. 6033
18.15.57GRXFIFOSIZ0_0 (GRXFIFOSIZ0_0)—Offset C380h ................................. 6034
18.15.58GEVNTADRLO_0 (GEVNTADRLO_0)—Offset C400h ................................. 6034
18.15.59GEVNTADRHI_0 (GEVNTADRHI_0)—Offset C404h.................................. 6035
18.15.60GEVNTSIZ_0 (GEVNTSIZ_0)—Offset C408h .......................................... 6035
18.15.61GEVNTCOUNT_0 (GEVNTCOUNT_0)—Offset C40Ch ................................ 6036
18.15.62GHWPARAMS8 (GHWPARAMS8)—Offset C600h...................................... 6037
18.15.63GTXFIFOPRIDEV (GTXFIFOPRIDEV)—Offset C610h................................. 6037
18.15.64GFLADJ (GFLADJ)—Offset C630h ......................................................... 6038
18.16 Registers Summary........................................................................................ 6041
18.16.1APBFC_U3PMU_CFG0 (APBFC_U3PMU_CFG0)—Offset 10F808h ................. 6041
18.16.2APBFC_U3PMU_CFG1 (APBFC_U3PMU_CFG1)—Offset 10F80Ch ................. 6042
18.16.3APBFC_U3PMU_CFG2 (APBFC_U3PMU_CFG2)—Offset 10F810h ................. 6043
18.16.4APBFC_U3PMU_CFG3 (APBFC_U3PMU_CFG3)—Offset 10F814h ................. 6044
18.16.5APBFC_U3PMU_CFG4 (APBFC_U3PMU_CFG4)—Offset 10F818h ................. 6045
18.16.6APBFC_U3PMU_CFG5 (APBFC_U3PMU_CFG5)—Offset 10F81Ch ................. 6046
18.16.7APBFC_U3PMU_CFG6 (APBFC_U3PMU_CFG6)—Offset 10F820h ................. 6047
18.16.8APBFC_D0I3C (APBFC_D0I3C)—Offset 10F830h...................................... 6048
18.17 Registers Summary........................................................................................ 6051
18.17.1 (GEN_REGRW1)—Offset B0h ............................................................... 6051
18.17.2(GEN_REGRW2)—Offset B4h ................................................................ 6051
18.17.3(GEN_REGRW3)—Offset B8h ................................................................ 6052
18.17.4(GEN_REGRW4)—Offset BCh ................................................................ 6052
18.17.5 (GEN_INPUT_REGRW)—Offset C0h....................................................... 6053
18.18 Registers Summary........................................................................................ 6055
18.18.1 (GEN_REGRW1)—Offset B0h ............................................................... 6055
18.18.2(GEN_REGRW2)—Offset B4h ................................................................ 6055
18.18.3(GEN_REGRW3)—Offset B8h ................................................................ 6056
18.18.4(GEN_REGRW4)—Offset BCh ................................................................ 6056
18.18.5 (GEN_INPUT_REGRW)—Offset C0h....................................................... 6057
18.19 Registers Summary........................................................................................ 6059
18.19.1 (DEVVENDID)—Offset 0h .................................................................... 6059
18.19.2(STATUSCOMMAND)—Offset 4h ............................................................ 6060
18.19.3(REVCLASSCODE)—Offset 8h ............................................................... 6061
18.19.4(CLLATHEADERBIST)—Offset Ch ........................................................... 6061

154 334818
 18.19.5(BAR)—Offset 10h ...............................................................................6062
18.19.6(BAR1)—Offset 18h .............................................................................6063
18.19.7(SUBSYSTEMID)—Offset 2Ch ................................................................6063
18.19.8(EXPANSION_ROM_BASEADDR)—Offset 30h ...........................................6064
18.19.9(CAPABILITYPTR)—Offset 34h ...............................................................6065
18.19.10(INTERRUPTREG)—Offset 3Ch .............................................................6065
18.19.11(POWERCAPID)—Offset 80h ................................................................6066
18.19.12(PMECTRLSTATUS)—Offset 84h ...........................................................6066
18.19.13(PCIDEVIDLE_CAP_RECORD)—Offset 90h .............................................6067
18.19.14(DEVID_VEND_SPECIFIC_REG)—Offset 94h ..........................................6068
18.19.15(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h...............................6068
18.19.16(DEVICE_IDLE_POINTER_REG)—Offset 9Ch...........................................6069
18.19.17(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ...................................6070
18.20 Registers Summary ........................................................................................6071
18.20.1 (DEVVENDID)—Offset 0h.....................................................................6071
18.20.2(STATUSCOMMAND)—Offset 4h.............................................................6072
18.20.3(REVCLASSCODE)—Offset 8h ................................................................6073
18.20.4(CLLATHEADERBIST)—Offset Ch............................................................6073
18.20.5(BAR)—Offset 10h ...............................................................................6074
18.20.6(BAR1)—Offset 18h .............................................................................6075
18.20.7(SUBSYSTEMID)—Offset 2Ch ................................................................6075
18.20.8(EXPANSION_ROM_BASEADDR)—Offset 30h ...........................................6076
18.20.9(CAPABILITYPTR)—Offset 34h ...............................................................6077
18.20.10(INTERRUPTREG)—Offset 3Ch .............................................................6077
18.20.11(POWERCAPID)—Offset 80h ................................................................6078
18.20.12(PMECTRLSTATUS)—Offset 84h ...........................................................6078
18.20.13(PCIDEVIDLE_CAP_RECORD)—Offset 90h .............................................6079
18.20.14(DEVID_VEND_SPECIFIC_REG)—Offset 94h ..........................................6080
18.20.15(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h...............................6080
18.20.16(DEVICE_IDLE_POINTER_REG)—Offset 9Ch...........................................6081
18.20.17(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ...................................6082
19 Storage ................................................................................................................6083
19.1 eMMC Registers Summary ...............................................................................6083
19.1.1 (SW_LTR_val)—Offset 804h.................................................................6083
19.1.2 (Auto_LTR_val)—Offset 808h ...............................................................6084
19.1.3 (Cap_byps)—Offset 810h ....................................................................6085
19.1.4 (Cap_byps_reg1)—Offset 814h ............................................................6085
19.1.5 (Cap_byps_reg2)—Offset 818h ............................................................6087
19.1.6 (reg_D0i3)—Offset 81Ch .....................................................................6088
19.1.7 (Tx_CMD_dly)—Offset 820h.................................................................6089
19.1.8 (Tx_DATA_dly_1)—Offset 824h ............................................................6090
19.1.9 (Tx_DATA_dly_2)—Offset 828h ............................................................6090
19.1.10 (Rx_CMD_Data_dly_1)—Offset 82Ch.....................................................6091
19.1.11 (Rx_Strobe_Ctrl_Path)—Offset 830h .....................................................6092
19.1.12 (Rx_CMD_Data_dly_2)—Offset 834h.....................................................6093
19.1.13 (Master_Dll)—Offset 838h ...................................................................6094
19.1.14 (Auto_tuning)—Offset 840h .................................................................6095
19.1.15(emmc_Root_Space)—Offset 900h ........................................................6095
19.2 SD Card Registers Summary ............................................................................6096
19.2.1 (SW_LTR_val)—Offset 804h.................................................................6096
19.2.2 (Auto_LTR_val)—Offset 808h ...............................................................6097
19.2.3 (Cap_byps)—Offset 810h ....................................................................6098
19.2.4 (Cap_byps_reg1)—Offset 814h ............................................................6098
19.2.5 (Cap_byps_reg2)—Offset 818h ............................................................6100

334818 155
 19.2.6 (reg_D0i3)—Offset 81Ch..................................................................... 6101
19.2.7 (Tx_CMD_dly)—Offset 820h ................................................................ 6102
19.2.8 (Tx_DATA_dly_1)—Offset 824h ........................................................... 6103
19.2.9 (Tx_DATA_dly_2)—Offset 828h ........................................................... 6103
19.2.10 (Rx_CMD_Data_dly_1)—Offset 82Ch .................................................... 6104
19.2.11 (Rx_Strobe_Ctrl_Path)—Offset 830h .................................................... 6105
19.2.12 (Rx_CMD_Data_dly_2)—Offset 834h .................................................... 6106
19.2.13 (Master_Dll)—Offset 838h................................................................... 6107
19.2.14 (Auto_tuning)—Offset 840h ................................................................ 6108
19.3 SDIO Registers Summary ............................................................................... 6108
19.3.1 (SW_LTR_val)—Offset 804h ................................................................ 6109
19.3.2 (Auto_LTR_val)—Offset 808h .............................................................. 6110
19.3.3 (Cap_byps)—Offset 810h .................................................................... 6110
19.3.4 (Cap_byps_reg1)—Offset 814h ............................................................ 6111
19.3.5 (Cap_byps_reg2)—Offset 818h ............................................................ 6113
19.3.6 (reg_D0i3)—Offset 81Ch..................................................................... 6114
19.3.7 (Tx_CMD_dly)—Offset 820h ................................................................ 6115
19.3.8 (Tx_DATA_dly_1)—Offset 824h ........................................................... 6115
19.3.9 (Tx_DATA_dly_2)—Offset 828h ........................................................... 6116
19.3.10 (Rx_CMD_Data_dly_1)—Offset 82Ch .................................................... 6117
19.3.11 (Rx_Strobe_Ctrl_Path)—Offset 830h .................................................... 6118
19.3.12 (Rx_CMD_Data_dly_2)—Offset 834h .................................................... 6118
19.3.13 (Master_Dll)—Offset 838h................................................................... 6119
19.3.14 (Auto_tuning)—Offset 840h ................................................................ 6120
19.4 Registers Summary........................................................................................ 6121
19.4.1 (DEVVENDID)—Offset 0h .................................................................... 6121
19.4.2 (STATUSCOMMAND)—Offset 4h ............................................................ 6122
19.4.3 (REVCLASSCODE)—Offset 8h ............................................................... 6123
19.4.4 (CLLATHEADERBIST)—Offset Ch ........................................................... 6124
19.4.5 (BAR)—Offset 10h .............................................................................. 6124
19.4.6 (BAR_HIGH)—Offset 14h ..................................................................... 6125
19.4.7 (BAR1)—Offset 18h............................................................................. 6126
19.4.8 (BAR1_HIGH)—Offset 1Ch ................................................................... 6126
19.4.9 (SUBSYSTEMID)—Offset 2Ch................................................................ 6127
19.4.10(EXPANSION_ROM_BASEADDR)—Offset 30h .......................................... 6127
19.4.11(CAPABILITYPTR)—Offset 34h .............................................................. 6128
19.4.12(INTERRUPTREG)—Offset 3Ch .............................................................. 6128
19.4.13(POWERCAPID)—Offset 80h ................................................................. 6129
19.4.14(PMECTRLSTATUS)—Offset 84h ............................................................ 6130
19.4.15(PCIDEVIDLE_CAP_RECORD)—Offset 90h .............................................. 6131
19.4.16(DEVID_VEND_SPECIFIC_REG)—Offset 94h ........................................... 6131
19.4.17(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h................................ 6132
19.4.18(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ........................................... 6132
19.4.19(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................... 6133
19.5 Registers Summary........................................................................................ 6134
19.5.1 SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h .
6135
19.5.2 BlockSize Register (blocksize)—Offset 4h ............................................... 6136
19.5.3 BlockCount Register (blockcount)—Offset 6h .......................................... 6136
19.5.4 Argument1 Register (argument1)—Offset 8h .......................................... 6137
19.5.5 TransferMode Register (transfermode)—Offset Ch ................................... 6137
19.5.6 Command Register (command)—Offset Eh ............................................. 6138
19.5.7 Response Register (response01)—Offset 10h.......................................... 6139
19.5.8 Response Register (response2)—Offset 14h ........................................... 6140
19.5.9 Response Register (response3)—Offset 16h ........................................... 6140

156 334818
 19.5.10Response Register (response4)—Offset 18h ............................................6141
19.5.11Response Register (response5)—Offset 1Ah ............................................6141
19.5.12Response Register (response6)—Offset 1Ch ............................................6142
19.5.13Response Register (response7)—Offset 1Eh ............................................6142
19.5.14Buffer DataPort Register (dataport)—Offset 20h ......................................6143
19.5.15eMMC Presentstate Register (presentstate)—Offset 24h............................6143
19.5.16HostControl1 Register (hostcontrol1)—Offset 28h ....................................6145
19.5.17PowerControl Register (powercontrol)—Offset 29h ...................................6146
19.5.18BlockGapControl Register (blockgapcontrol)—Offset 2Ah...........................6147
19.5.19Wakeup Control Register (wakeupcontrol)—Offset 2Bh .............................6148
19.5.20Clock Control Register (clockcontrol)—Offset 2Ch ....................................6149
19.5.21Timeout Control Register (timeoutcontrol)—Offset 2Eh .............................6150
19.5.22Software Reset Register (softwarereset)—Offset 2Fh................................6150
19.5.23Normal Interrupt Status Register (normalintrsts)—Offset 30h....................6151
19.5.24ErrorInterruptStatus_Register (errorintrsts)—Offset 32h ...........................6152
19.5.25Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h.....6154
19.5.26Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h ..........6156
19.5.27Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h .....6157
19.5.28Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah...........6158
19.5.29Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch ................6160
19.5.30Host Control2 Register (hostcontrol2)—Offset 3Eh ...................................6161
19.5.31Capabilities Register (capabilities)—Offset 40h ........................................6162
19.5.32Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h .........6164
19.5.33Force Event REGISTER for AUTO CMD Error Status
(ForceEventforAUTOCMDErrorStatus)—Offset 50h....................................6165
19.5.34Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset
52h ...................................................................................................6166
19.5.35ADMA Error Status Register (admaerrsts)—Offset 54h ..............................6167
19.5.36ADMA System Address Register0&1 (admasysaddr01)—Offset 58h.............6168
19.5.37ADMA System Address Register1 (admasysaddr2)—Offset 5Ch ..................6168
19.5.38ADMA System Address Register1 (admasysaddr3)—Offset 5Eh ..................6169
19.5.39Boot Timeout Control Register (boottimeoutcnt)—Offset 70h .....................6169
19.5.40Slot Interrupt Status Register (slotintrsts)—Offset FCh .............................6170
19.5.41Host Controller Version Register (hostcontrollerver)—Offset FEh ................6171
19.6 Registers Summary ........................................................................................6171
19.6.1 (DEVVENDID)—Offset 0h.....................................................................6172
19.6.2 (STATUSCOMMAND)—Offset 4h.............................................................6172
19.6.3 (REVCLASSCODE)—Offset 8h ................................................................6173
19.6.4 (CLLATHEADERBIST)—Offset Ch............................................................6174
19.6.5 (BAR)—Offset 10h ...............................................................................6175
19.6.6 (BAR_HIGH)—Offset 14h ......................................................................6175
19.6.7 (BAR1)—Offset 18h .............................................................................6176
19.6.8 (BAR1_HIGH)—Offset 1Ch ....................................................................6176
19.6.9 (SUBSYSTEMID)—Offset 2Ch ................................................................6177
19.6.10(EXPANSION_ROM_BASEADDR)—Offset 30h ...........................................6178
19.6.11(CAPABILITYPTR)—Offset 34h ...............................................................6178
19.6.12(INTERRUPTREG)—Offset 3Ch ...............................................................6179
19.6.13(POWERCAPID)—Offset 80h..................................................................6179
19.6.14(PMECTRLSTATUS)—Offset 84h .............................................................6180
19.6.15(PCIDEVIDLE_CAP_RECORD)—Offset 90h ...............................................6181
19.6.16(DEVID_VEND_SPECIFIC_REG)—Offset 94h ............................................6181
19.6.17(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................6182
19.6.18(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................6183
19.6.19(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................6183
19.7 Registers Summary ........................................................................................6184

334818 157
 19.7.1 SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h .
6185
19.7.2 BlockSize Register (blocksize)—Offset 4h ............................................... 6186
19.7.3 BlockCount Register (blockcount)—Offset 6h .......................................... 6187
19.7.4 Argument1 Register (argument1)—Offset 8h .......................................... 6187
19.7.5 TransferMode Register (transfermode)—Offset Ch ................................... 6188
19.7.6 Command Register (command)—Offset Eh ............................................. 6188
19.7.7 Response Register (response01)—Offset 10h.......................................... 6189
19.7.8 Response Register (response2)—Offset 14h ........................................... 6190
19.7.9 Response Register (response3)—Offset 16h ........................................... 6190
19.7.10Response Register (response4)—Offset 18h ........................................... 6191
19.7.11Response Register (response5)—Offset 1Ah ........................................... 6191
19.7.12Response Register (response6)—Offset 1Ch ........................................... 6192
19.7.13Response Register (response7)—Offset 1Eh ........................................... 6192
19.7.14Buffer DataPort Register (dataport)—Offset 20h...................................... 6193
19.7.15SDIO PresentState Register (presentstate)—Offset 24h............................ 6194
19.7.16HostControl1 Register (hostcontrol1)—Offset 28h.................................... 6196
19.7.17PowerControl Register (powercontrol)—Offset 29h .................................. 6197
19.7.18BlockGapControl Register (blockgapcontrol)—Offset 2Ah .......................... 6197
19.7.19Wakeup Control Register (wakeupcontrol)—Offset 2Bh............................. 6198
19.7.20Clock Control Register (clockcontrol)—Offset 2Ch .................................... 6199
19.7.21Timeout Control Register (timeoutcontrol)—Offset 2Eh ............................ 6200
19.7.22Software Reset Register (softwarereset)—Offset 2Fh ............................... 6201
19.7.23Normal Interrupt Status Register (normalintrsts)—Offset 30h ................... 6201
19.7.24ErrorInterruptStatus_Register (errorintrsts)—Offset 32h .......................... 6203
19.7.25Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h .... 6204
19.7.26Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h .......... 6206
19.7.27Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h .... 6207
19.7.28Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah .......... 6209
19.7.29Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch ................ 6210
19.7.30Host Control2 Register (hostcontrol2)—Offset 3Eh................................... 6211
19.7.31Capabilities Register (capabilities)—Offset 40h........................................ 6212
19.7.32Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h ........ 6215
19.7.33Force Event REGISTER for AUTO CMD Error Status
(ForceEventforAUTOCMDErrorStatus)—Offset 50h ................................... 6215
19.7.34Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset
52h................................................................................................... 6216
19.7.35ADMA Error Status Register (admaerrsts)—Offset 54h ............................. 6217
19.7.36ADMA System Address Register0&1 (admasysaddr01)—Offset 58h ............ 6218
19.7.37ADMA System Address Register1 (admasysaddr2)—Offset 5Ch ................. 6219
19.7.38ADMA System Address Register1 (admasysaddr3)—Offset 5Eh ................. 6219
19.7.39Boot Timeout Control Register (boottimeoutcnt)—Offset 70h .................... 6220
19.7.40Slot Interrupt Status Register (slotintrsts)—Offset FCh............................. 6220
19.7.41Host Controller Version Register (hostcontrollerver)—Offset FEh................ 6221
19.8 Registers Summary........................................................................................ 6222
19.8.1 (DEVVENDID)—Offset 0h .................................................................... 6222
19.8.2 (STATUSCOMMAND)—Offset 4h ............................................................ 6223
19.8.3 (REVCLASSCODE)—Offset 8h ............................................................... 6224
19.8.4 (CLLATHEADERBIST)—Offset Ch ........................................................... 6224
19.8.5 (BAR)—Offset 10h .............................................................................. 6225
19.8.6 (BAR_HIGH)—Offset 14h ..................................................................... 6226
19.8.7 (BAR1)—Offset 18h............................................................................. 6226
19.8.8 (BAR1_HIGH)—Offset 1Ch ................................................................... 6227
19.8.9 (SUBSYSTEMID)—Offset 2Ch................................................................ 6227
19.8.10(EXPANSION_ROM_BASEADDR)—Offset 30h .......................................... 6228

158 334818
 19.8.11(CAPABILITYPTR)—Offset 34h ...............................................................6229
19.8.12(INTERRUPTREG)—Offset 3Ch ...............................................................6229
19.8.13(POWERCAPID)—Offset 80h..................................................................6230
19.8.14(PMECTRLSTATUS)—Offset 84h .............................................................6230
19.8.15(PCIDEVIDLE_CAP_RECORD)—Offset 90h ...............................................6231
19.8.16(DEVID_VEND_SPECIFIC_REG)—Offset 94h ............................................6232
19.8.17(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ................................6232
19.8.18(DEVICE_IDLE_POINTER_REG)—Offset 9Ch ............................................6233
19.8.19(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ....................................6234
19.9 Registers Summary ........................................................................................6235
19.9.1 SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h..
6236
19.9.2 BlockSize Register (blocksize)—Offset 4h................................................6236
19.9.3 BlockCount Register (blockcount)—Offset 6h...........................................6237
19.9.4 Argument1 Register (argument1)—Offset 8h...........................................6237
19.9.5 TransferMode Register (transfermode)—Offset Ch....................................6238
19.9.6 Command Register (command)—Offset Eh..............................................6239
19.9.7 Response Register (response01)—Offset 10h ..........................................6240
19.9.8 Response Register (response2)—Offset 14h ............................................6240
19.9.9 Response Register (response3)—Offset 16h ............................................6241
19.9.10Response Register (response4)—Offset 18h ............................................6241
19.9.11Response Register (response5)—Offset 1Ah ............................................6242
19.9.12Response Register (response6)—Offset 1Ch ............................................6242
19.9.13Response Register (response7)—Offset 1Eh ............................................6243
19.9.14Buffer DataPort Register (dataport)—Offset 20h ......................................6243
19.9.15SD Card PresentState Register (presentstate)—Offset 24h ........................6244
19.9.16HostControl1 Register (hostcontrol1)—Offset 28h ....................................6246
19.9.17PowerControl Register (powercontrol)—Offset 29h ...................................6247
19.9.18BlockGapControl Register (blockgapcontrol)—Offset 2Ah...........................6248
19.9.19Wakeup Control Register (wakeupcontrol)—Offset 2Bh .............................6249
19.9.20Clock Control Register (clockcontrol)—Offset 2Ch ....................................6250
19.9.21Timeout Control Register (timeoutcontrol)—Offset 2Eh .............................6250
19.9.22Software Reset Register (softwarereset)—Offset 2Fh................................6251
19.9.23Normal Interrupt Status Register (normalintrsts)—Offset 30h....................6252
19.9.24ErrorInterruptStatus_Register (errorintrsts)—Offset 32h ...........................6253
19.9.25Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h.....6255
19.9.26Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h ..........6256
19.9.27Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h .....6258
19.9.28Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah...........6259
19.9.29Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch ................6260
19.9.30Host Control2 Register (hostcontrol2)—Offset 3Eh ...................................6261
19.9.31Capabilities Register (capabilities)—Offset 40h ........................................6263
19.9.32Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h .........6265
19.9.33Force Event REGISTER for AUTO CMD Error Status
(ForceEventforAUTOCMDErrorStatus)—Offset 50h....................................6266
19.9.34Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset
52h ...................................................................................................6267
19.9.35ADMA Error Status Register (admaerrsts)—Offset 54h ..............................6268
19.9.36ADMA System Address Register0&1 (admasysaddr01)—Offset 58h.............6268
19.9.37ADMA System Address Register1 (admasysaddr2)—Offset 5Ch ..................6269
19.9.38ADMA System Address Register1 (admasysaddr3)—Offset 5Eh ..................6270
19.9.39Boot Timeout Control Register (boottimeoutcnt)—Offset 70h .....................6270
19.9.40Slot Interrupt Status Register (slotintrsts)—Offset FCh .............................6271
19.9.41Host Controller Version Register (hostcontrollerver)—Offset FEh ................6271
19.10 eMMC, SD Card & SDIO Idle Clock Gating Register..............................................6272

334818 159
 19.11 eMMC Registers Summary .............................................................................. 6275
19.11.1 (SW_LTR_val)—Offset 804h ................................................................ 6275
19.11.2 (Auto_LTR_val)—Offset 808h .............................................................. 6276
19.11.3 (Cap_byps)—Offset 810h .................................................................... 6277
19.11.4 (Cap_byps_reg1)—Offset 814h ............................................................ 6277
19.11.5 (Cap_byps_reg2)—Offset 818h ............................................................ 6279
19.11.6 (reg_D0i3)—Offset 81Ch..................................................................... 6280
19.11.7 (Tx_CMD_dly)—Offset 820h ................................................................ 6281
19.11.8 (Tx_DATA_dly_1)—Offset 824h ........................................................... 6281
19.11.9 (Tx_DATA_dly_2)—Offset 828h ........................................................... 6282
19.11.10 (Rx_CMD_Data_dly_1)—Offset 82Ch .................................................. 6283
19.11.11 (Rx_Strobe_Ctrl_Path)—Offset 830h ................................................... 6284
19.11.12 (Rx_CMD_Data_dly_2)—Offset 834h................................................... 6285
19.11.13 (Master_Dll)—Offset 838h ................................................................. 6286
19.11.14 (Auto_tuning)—Offset 840h ............................................................... 6286
19.11.15(emmc_Root_Space)—Offset 900h ...................................................... 6287
19.12 SD Card Registers Summary ........................................................................... 6289
19.12.1 (SW_LTR_val)—Offset 804h ................................................................ 6289
19.12.2 (Auto_LTR_val)—Offset 808h .............................................................. 6290
19.12.3 (Cap_byps)—Offset 810h .................................................................... 6291
19.12.4 (Cap_byps_reg1)—Offset 814h ............................................................ 6291
19.12.5 (Cap_byps_reg2)—Offset 818h ............................................................ 6293
19.12.6 (reg_D0i3)—Offset 81Ch..................................................................... 6294
19.12.7 (Tx_CMD_dly)—Offset 820h ................................................................ 6295
19.12.8 (Tx_DATA_dly_1)—Offset 824h ........................................................... 6295
19.12.9 (Tx_DATA_dly_2)—Offset 828h ........................................................... 6296
19.12.10 (Rx_CMD_Data_dly_1)—Offset 82Ch .................................................. 6297
19.12.11 (Rx_Strobe_Ctrl_Path)—Offset 830h ................................................... 6298
19.12.12 (Rx_CMD_Data_dly_2)—Offset 834h................................................... 6299
19.12.13 (Master_Dll)—Offset 838h ................................................................. 6300
19.12.14 (Auto_tuning)—Offset 840h ............................................................... 6300
19.13 SDIO Registers Summary ............................................................................... 6303
19.13.1 (SW_LTR_val)—Offset 804h ................................................................ 6303
19.13.2 (Auto_LTR_val)—Offset 808h .............................................................. 6304
19.13.3 (Cap_byps)—Offset 810h .................................................................... 6305
19.13.4 (Cap_byps_reg1)—Offset 814h ............................................................ 6305
19.13.5 (Cap_byps_reg2)—Offset 818h ............................................................ 6307
19.13.6 (reg_D0i3)—Offset 81Ch..................................................................... 6308
19.13.7 (Tx_CMD_dly)—Offset 820h ................................................................ 6309
19.13.8 (Tx_DATA_dly_1)—Offset 824h ........................................................... 6309
19.13.9 (Tx_DATA_dly_2)—Offset 828h ........................................................... 6310
19.13.10 (Rx_CMD_Data_dly_1)—Offset 82Ch .................................................. 6311
19.13.11 (Rx_Strobe_Ctrl_Path)—Offset 830h ................................................... 6312
19.13.12 (Rx_CMD_Data_dly_2)—Offset 834h................................................... 6313
19.13.13 (Master_Dll)—Offset 838h ................................................................. 6314
19.13.14 (Auto_tuning)—Offset 840h ............................................................... 6314
19.14 Registers Summary........................................................................................ 6317
19.14.1 (DEVVENDID)—Offset 0h .................................................................... 6317
19.14.2(STATUSCOMMAND)—Offset 4h ............................................................ 6318
19.14.3(REVCLASSCODE)—Offset 8h ............................................................... 6319
19.14.4(CLLATHEADERBIST)—Offset Ch ........................................................... 6319
19.14.5(BAR)—Offset 10h .............................................................................. 6320
19.14.6(BAR_HIGH)—Offset 14h ..................................................................... 6321
19.14.7(BAR1)—Offset 18h............................................................................. 6321
19.14.8(BAR1_HIGH)—Offset 1Ch ................................................................... 6322

160 334818
 19.14.9(SUBSYSTEMID)—Offset 2Ch ................................................................6322
19.14.10(EXPANSION_ROM_BASEADDR)—Offset 30h .........................................6323
19.14.11(CAPABILITYPTR)—Offset 34h .............................................................6324
19.14.12(INTERRUPTREG)—Offset 3Ch .............................................................6324
19.14.13(POWERCAPID)—Offset 80h ................................................................6325
19.14.14(PMECTRLSTATUS)—Offset 84h ...........................................................6325
19.14.15(PCIDEVIDLE_CAP_RECORD)—Offset 90h .............................................6326
19.14.16(DEVID_VEND_SPECIFIC_REG)—Offset 94h ..........................................6327
19.14.17(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h...............................6327
19.14.18(DEVICE_IDLE_POINTER_REG)—Offset 9Ch...........................................6328
19.14.19(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ...................................6329
19.15 Registers Summary ........................................................................................6331
19.15.1SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h..
6332
19.15.2BlockSize Register (blocksize)—Offset 4h................................................6332
19.15.3BlockCount Register (blockcount)—Offset 6h...........................................6333
19.15.4Argument1 Register (argument1)—Offset 8h...........................................6333
19.15.5TransferMode Register (transfermode)—Offset Ch....................................6334
19.15.6Command Register (command)—Offset Eh..............................................6335
19.15.7Response Register (response01)—Offset 10h ..........................................6336
19.15.8Response Register (response2)—Offset 14h ............................................6336
19.15.9Response Register (response3)—Offset 16h ............................................6337
19.15.10Response Register (response4)—Offset 18h...........................................6337
19.15.11Response Register (response5)—Offset 1Ah ..........................................6338
19.15.12Response Register (response6)—Offset 1Ch ..........................................6338
19.15.13Response Register (response7)—Offset 1Eh...........................................6339
19.15.14Buffer DataPort Register (dataport)—Offset 20h.....................................6339
19.15.15eMMC Presentstate Register (presentstate)—Offset 24h ..........................6340
19.15.16HostControl1 Register (hostcontrol1)—Offset 28h...................................6342
19.15.17PowerControl Register (powercontrol)—Offset 29h..................................6343
19.15.18BlockGapControl Register (blockgapcontrol)—Offset 2Ah .........................6344
19.15.19Wakeup Control Register (wakeupcontrol)—Offset 2Bh............................6345
19.15.20Clock Control Register (clockcontrol)—Offset 2Ch ...................................6345
19.15.21Timeout Control Register (timeoutcontrol)—Offset 2Eh............................6346
19.15.22Software Reset Register (softwarereset)—Offset 2Fh ..............................6347
19.15.23Normal Interrupt Status Register (normalintrsts)—Offset 30h ..................6347
19.15.24ErrorInterruptStatus_Register (errorintrsts)—Offset 32h .........................6349
19.15.25Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h ...6350
19.15.26Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h .........6352
19.15.27Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h....6353
19.15.28Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah .........6355
19.15.29Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch ...............6356
19.15.30Host Control2 Register (hostcontrol2)—Offset 3Eh..................................6357
19.15.31Capabilities Register (capabilities)—Offset 40h .......................................6358
19.15.32Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h........6361
19.15.33Force Event REGISTER for AUTO CMD Error Status
(ForceEventforAUTOCMDErrorStatus)—Offset 50h....................................6362
19.15.34Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset
52h ...................................................................................................6363
19.15.35ADMA Error Status Register (admaerrsts)—Offset 54h ............................6364
19.15.36ADMA System Address Register0&1 (admasysaddr01)—Offset 58h ...........6364
19.15.37ADMA System Address Register1 (admasysaddr2)—Offset 5Ch ................6365
19.15.38ADMA System Address Register1 (admasysaddr3)—Offset 5Eh.................6366
19.15.39Boot Timeout Control Register (boottimeoutcnt)—Offset 70h ...................6366
19.15.40Slot Interrupt Status Register (slotintrsts)—Offset FCh............................6367

334818 161
 19.15.41Host Controller Version Register (hostcontrollerver)—Offset FEh .............. 6367
19.16 Registers Summary........................................................................................ 6369
19.16.1 (DEVVENDID)—Offset 0h .................................................................... 6369
19.16.2(STATUSCOMMAND)—Offset 4h ............................................................ 6370
19.16.3(REVCLASSCODE)—Offset 8h ............................................................... 6371
19.16.4(CLLATHEADERBIST)—Offset Ch ........................................................... 6371
19.16.5(BAR)—Offset 10h .............................................................................. 6372
19.16.6(BAR_HIGH)—Offset 14h ..................................................................... 6373
19.16.7(BAR1)—Offset 18h............................................................................. 6373
19.16.8(BAR1_HIGH)—Offset 1Ch ................................................................... 6374
19.16.9(SUBSYSTEMID)—Offset 2Ch................................................................ 6374
19.16.10(EXPANSION_ROM_BASEADDR)—Offset 30h ......................................... 6375
19.16.11(CAPABILITYPTR)—Offset 34h ............................................................. 6376
19.16.12(INTERRUPTREG)—Offset 3Ch ............................................................. 6376
19.16.13(POWERCAPID)—Offset 80h................................................................ 6377
19.16.14(PMECTRLSTATUS)—Offset 84h ........................................................... 6377
19.16.15(PCIDEVIDLE_CAP_RECORD)—Offset 90h ............................................. 6378
19.16.16(DEVID_VEND_SPECIFIC_REG)—Offset 94h .......................................... 6379
19.16.17(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h .............................. 6379
19.16.18(DEVICE_IDLE_POINTER_REG)—Offset 9Ch .......................................... 6380
19.16.19(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h .................................. 6381
19.17 Registers Summary........................................................................................ 6383
19.17.1SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h .
6384
19.17.2BlockSize Register (blocksize)—Offset 4h ............................................... 6384
19.17.3BlockCount Register (blockcount)—Offset 6h .......................................... 6385
19.17.4Argument1 Register (argument1)—Offset 8h .......................................... 6385
19.17.5TransferMode Register (transfermode)—Offset Ch ................................... 6386
19.17.6Command Register (command)—Offset Eh ............................................. 6387
19.17.7Response Register (response01)—Offset 10h.......................................... 6388
19.17.8Response Register (response2)—Offset 14h ........................................... 6388
19.17.9Response Register (response3)—Offset 16h ........................................... 6389
19.17.10Response Register (response4)—Offset 18h .......................................... 6389
19.17.11Response Register (response5)—Offset 1Ah .......................................... 6390
19.17.12Response Register (response6)—Offset 1Ch .......................................... 6390
19.17.13Response Register (response7)—Offset 1Eh .......................................... 6391
19.17.14Buffer DataPort Register (dataport)—Offset 20h .................................... 6391
19.17.15SDIO PresentState Register (presentstate)—Offset 24h .......................... 6392
19.17.16HostControl1 Register (hostcontrol1)—Offset 28h .................................. 6394
19.17.17PowerControl Register (powercontrol)—Offset 29h ................................. 6395
19.17.18BlockGapControl Register (blockgapcontrol)—Offset 2Ah......................... 6396
19.17.19Wakeup Control Register (wakeupcontrol)—Offset 2Bh ........................... 6396
19.17.20Clock Control Register (clockcontrol)—Offset 2Ch .................................. 6397
19.17.21Timeout Control Register (timeoutcontrol)—Offset 2Eh ........................... 6398
19.17.22Software Reset Register (softwarereset)—Offset 2Fh.............................. 6399
19.17.23Normal Interrupt Status Register (normalintrsts)—Offset 30h.................. 6399
19.17.24ErrorInterruptStatus_Register (errorintrsts)—Offset 32h......................... 6401
19.17.25Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h... 6402
19.17.26Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h ........ 6404
19.17.27Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h ... 6405
19.17.28Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah......... 6407
19.17.29Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch .............. 6408
19.17.30Host Control2 Register (hostcontrol2)—Offset 3Eh ................................. 6409
19.17.31Capabilities Register (capabilities)—Offset 40h ...................................... 6410
19.17.32Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h ....... 6413

162 334818
 19.17.33Force Event REGISTER for AUTO CMD Error Status
(ForceEventforAUTOCMDErrorStatus)—Offset 50h....................................6413
19.17.34Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset
52h ...................................................................................................6414
19.17.35ADMA Error Status Register (admaerrsts)—Offset 54h ............................6415
19.17.36ADMA System Address Register0&1 (admasysaddr01)—Offset 58h ...........6416
19.17.37ADMA System Address Register1 (admasysaddr2)—Offset 5Ch ................6417
19.17.38ADMA System Address Register1 (admasysaddr3)—Offset 5Eh.................6417
19.17.39Boot Timeout Control Register (boottimeoutcnt)—Offset 70h ...................6418
19.17.40Slot Interrupt Status Register (slotintrsts)—Offset FCh............................6418
19.17.41Host Controller Version Register (hostcontrollerver)—Offset FEh...............6419
19.18 Registers Summary ........................................................................................6421
19.18.1 (DEVVENDID)—Offset 0h.....................................................................6421
19.18.2(STATUSCOMMAND)—Offset 4h.............................................................6422
19.18.3(REVCLASSCODE)—Offset 8h ................................................................6423
19.18.4(CLLATHEADERBIST)—Offset Ch............................................................6423
19.18.5(BAR)—Offset 10h ...............................................................................6424
19.18.6(BAR_HIGH)—Offset 14h ......................................................................6425
19.18.7(BAR1)—Offset 18h .............................................................................6425
19.18.8(BAR1_HIGH)—Offset 1Ch ....................................................................6426
19.18.9(SUBSYSTEMID)—Offset 2Ch ................................................................6426
19.18.10(EXPANSION_ROM_BASEADDR)—Offset 30h .........................................6427
19.18.11(CAPABILITYPTR)—Offset 34h .............................................................6428
19.18.12(INTERRUPTREG)—Offset 3Ch .............................................................6428
19.18.13(POWERCAPID)—Offset 80h ................................................................6429
19.18.14(PMECTRLSTATUS)—Offset 84h ...........................................................6429
19.18.15(PCIDEVIDLE_CAP_RECORD)—Offset 90h .............................................6430
19.18.16(DEVID_VEND_SPECIFIC_REG)—Offset 94h ..........................................6431
19.18.17(D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h...............................6431
19.18.18(DEVICE_IDLE_POINTER_REG)—Offset 9Ch...........................................6432
19.18.19(D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h ...................................6433
19.19 Registers Summary ........................................................................................6435
19.19.1SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h..
6436
19.19.2BlockSize Register (blocksize)—Offset 4h................................................6436
19.19.3BlockCount Register (blockcount)—Offset 6h...........................................6437
19.19.4Argument1 Register (argument1)—Offset 8h...........................................6437
19.19.5TransferMode Register (transfermode)—Offset Ch....................................6438
19.19.6Command Register (command)—Offset Eh..............................................6439
19.19.7Response Register (response01)—Offset 10h ..........................................6440
19.19.8Response Register (response2)—Offset 14h ............................................6440
19.19.9Response Register (response3)—Offset 16h ............................................6441
19.19.10Response Register (response4)—Offset 18h...........................................6441
19.19.11Response Register (response5)—Offset 1Ah ..........................................6442
19.19.12Response Register (response6)—Offset 1Ch ..........................................6442
19.19.13Response Register (response7)—Offset 1Eh...........................................6443
19.19.14Buffer DataPort Register (dataport)—Offset 20h.....................................6443
19.19.15SD Card PresentState Register (presentstate)—Offset 24h.......................6444
19.19.16HostControl1 Register (hostcontrol1)—Offset 28h...................................6446
19.19.17PowerControl Register (powercontrol)—Offset 29h..................................6447
19.19.18BlockGapControl Register (blockgapcontrol)—Offset 2Ah .........................6448
19.19.19Wakeup Control Register (wakeupcontrol)—Offset 2Bh............................6449
19.19.20Clock Control Register (clockcontrol)—Offset 2Ch ...................................6450
19.19.21Timeout Control Register (timeoutcontrol)—Offset 2Eh............................6450
19.19.22Software Reset Register (softwarereset)—Offset 2Fh ..............................6451

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 19.19.23Normal Interrupt Status Register (normalintrsts)—Offset 30h.................. 6452
19.19.24ErrorInterruptStatus_Register (errorintrsts)—Offset 32h......................... 6453
19.19.25Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h... 6455
19.19.26Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h ........ 6456
19.19.27Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h ... 6458
19.19.28Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah......... 6459
19.19.29Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch .............. 6460
19.19.30Host Control2 Register (hostcontrol2)—Offset 3Eh ................................. 6461
19.19.31Capabilities Register (capabilities)—Offset 40h ...................................... 6463
19.19.32Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h ....... 6465
19.19.33Force Event REGISTER for AUTO CMD Error Status
(ForceEventforAUTOCMDErrorStatus)—Offset 50h ................................... 6466
19.19.34Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset
52h................................................................................................... 6467
19.19.35ADMA Error Status Register (admaerrsts)—Offset 54h ............................ 6468
19.19.36ADMA System Address Register0&1 (admasysaddr01)—Offset 58h .......... 6468
19.19.37ADMA System Address Register1 (admasysaddr2)—Offset 5Ch ................ 6469
19.19.38ADMA System Address Register1 (admasysaddr3)—Offset 5Eh ................ 6470
19.19.39Boot Timeout Control Register (boottimeoutcnt)—Offset 70h ................... 6470
19.19.40Slot Interrupt Status Register (slotintrsts)—Offset FCh ........................... 6471
19.19.41Host Controller Version Register (hostcontrollerver)—Offset FEh .............. 6471
20 I2S....................................................................................................................... 6473
20.1 Register Summary ......................................................................................... 6473
20.1.1 SSP Control 0 (SSC0) - Offset 00h ........................................................ 6473
20.1.2 SSP Control 1 (SSC1) - Offset 04h ........................................................ 6475
20.1.3 SSP Status (SSS) - Offset 08h .............................................................. 6477
20.1.4 SSP Data (SSD) - Offset 10h ................................................................ 6479
20.1.5 SSP Time Out (SSTO) - Offset 28h ........................................................ 6480
20.1.6 SSP Programmable Serial Protocol (SSPSP) - Offset 2Ch .......................... 6480
20.1.7 SSP TX Time Slot Active (SSTSA) - Offset 30h ........................................ 6482
20.1.8 SSP RX Time Slot Active (SSRSA) - Offset 34h........................................ 6483
20.1.9 SSP Time Slot Status (SSTSS) - Offset 38h ............................................ 6483
20.1.10SSP Command/Status 2 (SSC2) - Offset 40h .......................................... 6484
20.1.11SSP Programmable Serial Protocol 2 (SSPSP2) - Offset 44h ...................... 6486
20.1.12SSP Command/Status 3 (SSC3) - Offset 48h .......................................... 6486
20.1.13SSP IO Control (SSIOC) - Offset 4Ch ..................................................... 6487
20.2 M/N Clock Synthesizer Registers ...................................................................... 6488
20.2.1 Register Summary .............................................................................. 6488
20.3 MCLK and BCLK Calculation: ........................................................................... 6489
20.3.1 Offset 000h: MDIVCTRL - MCLK Divider Control Register .......................... 6489
20.3.2 Offset 080h: MDIV0R – MCLK Divider 0 Ratio Register ............................. 6490
20.3.3 Offset 084h: MDIV1R – MCLK Divider 1 Ratio Register ............................. 6490
20.3.4 Offset 100h: I2S1_MDIVMVAL – I2S1 M/N Divider M Value Register .......... 6491
20.3.5 Offset 104h: I2S1_MDIVNVAL – I2S1 M/N Divider N Value Register ........... 6491
20.3.6 Offset 108h: I2S2_MDIVMVAL – I2S2 M/N Divider M Value Register .......... 6492
20.3.7 Offset 10Ch: I2S2_MDIVNVAL – I2S2 M/N Divider N Value Register........... 6492
20.3.8 Offset 110h: I2S3_MDIVMVAL – I2S3 M/N Divider M Value Register .......... 6493
20.3.9 Offset 114h: I2S3_MDIVNVAL – I2S3 M/N Divider N Value Register ........... 6493
20.3.10Offset 118h: I2S4_MDIVMVAL – I2S4 M/N Divider M Value Register .......... 6493
20.3.11Offset 11Ch: I2S4_MDIVNVAL – I2S4 M/N Divider N Value Register........... 6494
20.3.12Offset 120h: I2S5_MDIVMVAL – I2S5 M/N Divider M Value Register .......... 6494
20.3.13Offset 124h: I2S5_MDIVNVAL – I2S5 M/N Divider N Value Register ........... 6495
20.3.14Offset 128h: I2S6_MDIVMVAL – I2S6 M/N Divider M Value Register .......... 6495
20.3.15Offset 12Ch: I2S6_MDIVNVAL – I2S6 M/N Divider N Value Register........... 6495

164 334818
 2-1 Memory Map Configuration Registers ............................................................................ 8
2-2 Low DRAM Default Address Decode Rule ....................................................................... 9
2-3 Legacy VGA A.......................................................................................................... 10
2-4 Legacy MDA ............................................................................................................ 10
2-5 Legacy VGA B.......................................................................................................... 11
2-6 PMR-L .................................................................................................................... 11
2-7 TSEG...................................................................................................................... 12
2-8 GSM....................................................................................................................... 12
2-9 Low MMIO Address Range ......................................................................................... 13
2-10PCIe MMCFG ........................................................................................................... 14
2-11MCHBAR ................................................................................................................. 14
2-12Default VTd BAR ...................................................................................................... 15
2-13Graphics VTd BAR .................................................................................................... 15
2-14GTTMMADR ............................................................................................................. 16
2-15GMADR................................................................................................................... 16
2-16I-Unit BAR .............................................................................................................. 17
2-17LPC Generic Memory Range....................................................................................... 17
2-18CRAB_ABORT .......................................................................................................... 17
2-19IOAPIC ................................................................................................................... 18
2-20HPET ...................................................................................................................... 18
2-21TPM locality 0 .......................................................................................................... 18
2-22TPM Locality 1-3 ...................................................................................................... 19
2-23TPM Locality 1-3 ...................................................................................................... 19
2-24xHCI.DBC ............................................................................................................... 19
2-25IOAPIC ................................................................................................................... 20
2-26BIOS1 .................................................................................................................... 20
2-27BIOS2 .................................................................................................................... 21
2-28BIOS3 .................................................................................................................... 21
2-29BIOS4 .................................................................................................................... 21
2-30High DRAM.............................................................................................................. 22
2-31PMR-H.................................................................................................................... 23
2-32High MMIO Address Range ........................................................................................ 23
2-33Fixed I/O Address Map Positive Decode ....................................................................... 27
2-34Fixed I/O Address Map Subtractive Decode.................................................................. 28
2-35Legacy Variable I/O Address Map ............................................................................... 30
2-36Display IOBAR ......................................................................................................... 30
2-37PCI Config PORT CF8 Mapping ................................................................................... 31
2-38PCI Config Memory Bar Mapping ................................................................................ 32
2-39Funny I/O Address Ranges and Routing ...................................................................... 35
2-40P2SB MMIO Register Interface ................................................................................... 35
3-1 PCI Configuration Matrix: (Snapshot effective 10/12/2014 12:38 PM) ............................. 40
4-1 Fixed I/O Register Access Method Example (P80 Register) ............................................. 43
4-2 Referenced I/O Register Access Method Example (HSTS Register) .................................. 44
4-3 PCI Register Access Method Example (VID Register) ..................................................... 44
4-4 PCI CONFIG_ADDRESS Register (I/O PORT CF8h) Mapping ............................................ 44
4-5 Fixed Memory-Mapped Register Access Method Example (IDX Register) .......................... 46
4-6 Memory-Mapped Register Access Method Example (_MBAR Register) .............................. 46
4-7 P2SB MMIO Register Interface ................................................................................... 47
4-8 Access Type Explanations.......................................................................................... 48
4-9 Attributes/Modifiers are Applied to Base Access Types to Describe HW Interaction or Other
Details.................................................................................................................... 48
5-1 Summary of pcs_regs_wrapper Registers .................................................................... 51
5-2 Summary of pcs_regs_wrapper Registers .................................................................... 52
5-3 Summary of pcs_regs_wrapper Registers .................................................................... 96
5-4 Summary of pcs_regs_wrapper Registers .................................................................. 140

334818 1
 5-5 Summary of pcs_regs_wrapper Registers .................................................................. 184
5-6 Summary of memss_regs Registers .......................................................................... 228
5-7 Summary of pcs_regs_wrapper Registers .................................................................. 273
5-8 Summary of pcs_regs_wrapper Registers .................................................................. 329
5-9 Summary of pcs_regs_wrapper Registers .................................................................. 374
5-10Summary of pcs_regs_wrapper Registers .................................................................. 742
5-11Summary of cpgc_t_submap Registers ...................................................................... 771
5-12Summary of cpgc_c_submap Registers.................................................................... 1031
5-13Summary of cpgc_t_submap Registers .................................................................... 1061
5-14Summary of cpgc_c_submap Registers.................................................................... 1321
5-15Summary of cpgc_t_submap Registers .................................................................... 1351
5-16Summary of pcs_regs_wrapper Registers ................................................................ 1611
5-17Summary of pcs_regs_wrapper Registers ................................................................ 1613
5-18Summary of pcs_regs_wrapper Registers ................................................................ 1657
5-19Summary of pcs_regs_wrapper Registers ................................................................ 1701
5-20Summary of pcs_regs_wrapper Registers ................................................................ 1745
5-21Summary of memss_regs Registers ........................................................................ 1789
5-22Summary of pcs_regs_wrapper Registers ................................................................ 1833
5-23Summary of pcs_regs_wrapper Registers ................................................................ 1891
5-24Summary of pcs_regs_wrapper Registers ................................................................ 1937
5-25Summary of pcs_regs_wrapper Registers ................................................................ 2305
6-1 Summary of pcs_regs Registers.............................................................................. 2335
7-1 Summary of pcs_regs Registers.............................................................................. 2337
7-2 Summary of pcs_regs Registers.............................................................................. 2341
8-1 Summary of pcs_regs_wrapper Registers ................................................................ 2345
8-2 Summary of pcs_regs_wrapper Registers ................................................................ 2359
8-3 Summary of pcs_regs_wrapper Registers ................................................................ 2368
8-4 Summary of pcs_regs_wrapper Registers ................................................................ 2373
8-5 Summary of pcs_regs_wrapper Registers ................................................................ 2381
8-6 Summary of pcs_regs_wrapper Registers ................................................................ 2382
8-7 Summary of pcs_regs_wrapper Registers ................................................................ 2383
8-8 Summary of pcs_regs_wrapper Registers ................................................................ 2384
8-9 Summary of pcs_regs_wrapper Registers ................................................................ 2385
8-10Summary of pcs_regs_wrapper Registers ................................................................ 2391
8-11Summary of pcs_regs_wrapper Registers ................................................................ 2407
8-12Summary of pcs_regs_wrapper Registers ................................................................ 2417
8-13Summary of pcs_regs_wrapper Registers ................................................................ 2423
8-14Summary of pcs_regs_wrapper Registers ................................................................ 2431
8-15Summary of pcs_regs_wrapper Registers ................................................................ 2433
8-16Summary of pcs_regs_wrapper Registers ................................................................ 2435
8-17Summary of pcs_regs_wrapper Registers ................................................................ 2437
8-18Summary of pcs_regs_wrapper Registers ................................................................ 2439
9-1 Summary of pcs_regs_wrapper Registers ................................................................ 2445
9-2 Summary of pcs_regs_wrapper Registers ................................................................ 2473
9-3 Summary of pcs_regs_wrapper Registers ................................................................ 2477
9-4 Summary of pcs_regs_wrapper Registers ................................................................ 2507
10-1Summary of IUNIT_CFG Registers .......................................................................... 2509
10-2Summary of IUNIT_CFG Registers .......................................................................... 2529
11-1Summary of HDAHC_CFGREG Registers................................................................... 2549
11-2Summary of HDAHC_MMREG Registers.................................................................... 2590
11-3Summary of HDAHC_CFGREG Registers................................................................... 2917
11-4Summary of HDAHC_MMREG Registers.................................................................... 2959
12-1Summary of ACPI CR Registers .............................................................................. 3285
12-2Summary of GCR CR Registers ............................................................................... 3318
12-3Summary of IPC Registers Registers ....................................................................... 3354

2 334818
 12-4Summary of soc_regs_wrapper Registers .................................................................3361
12-5Summary of soc_regs_wrapper Registers .................................................................3376
12-6Summary of Pulse Width Modulator Controller Registers .............................................3391
12-7Summary of soc_regs_wrapper Registers .................................................................3396
12-8Summary of soc_regs_wrapper Registers .................................................................3411
12-9Summary of soc_regs_wrapper Registers .................................................................3426
12-10Summary of soc_regs_wrapper Registers ...............................................................3441
12-11Summary of ACPI CR Registers .............................................................................3457
12-12Summary of GCR CR Registers..............................................................................3491
12-13Summary of IPC Registers Registers ......................................................................3529
12-14Summary of soc_regs_wrapper Registers ...............................................................3537
12-15Summary of soc_regs_wrapper Registers ...............................................................3553
12-16Summary of Pulse Width Modulator Controller Registers ...........................................3569
12-17Summary of soc_regs_wrapper Registers ...............................................................3575
12-18Summary of soc_regs_wrapper Registers ...............................................................3591
12-19Summary of soc_regs_wrapper Registers ...............................................................3607
12-20Summary of soc_regs_wrapper Registers ...............................................................3623
13-1Summary of pcs_regs_wrapper Registers .................................................................3639
13-2Summary of pcs_regs_wrapper Registers .................................................................3643
13-3Summary of pcs_regs_wrapper Registers .................................................................3660
13-4Summary of pcs_regs_wrapper Registers .................................................................3686
13-5Summary of pcs_regs_wrapper Registers .................................................................3703
13-6Summary of pcs_regs_wrapper Registers .................................................................3707
13-7Summary of pcs_regs_wrapper Registers .................................................................3725
13-8Summary of pcs_regs_wrapper Registers .................................................................3751
14-1Summary of 0_31_0_APIC MEM Registers ................................................................3767
14-2Summary of 0_31_0_APIC MEM REG Registers .........................................................3931
14-3Summary of 0_31_0_CPU IO Registers ....................................................................3932
14-4Summary of 0_31_0_HPET MEM SPT Registers .........................................................3936
14-5Summary of 0_31_0_INTR IO Registers ...................................................................3980
14-6Summary of 0_31_0_LEG_8254_TIMER IO Registers .................................................3993
14-7Summary of 0_31_0_APIC MEM Registers ................................................................4001
14-8Summary of 0_31_0_APIC MEM REG Registers .........................................................4165
14-9Summary of 0_31_0_CPU IO Registers ....................................................................4167
14-10Summary of 0_31_0_HPET MEM SPT Registers........................................................4171
14-11Summary of 0_31_0_INTR IO Registers .................................................................4215
14-12Summary of 0_31_0_LEG_8254_TIMER IO Registers ...............................................4229
15-1Summary of map_iosf2ocp_pci_configreg Registers ...................................................4237
15-2Summary of map_iosf2ocp_pci_configreg Registers ...................................................4253
16-1Summary of pcie_cfg Registers ...............................................................................4269
16-2Summary of pcie_cfg Registers ...............................................................................4449
17-1Summary of sata_configreg_top Registers................................................................4629
17-2Summary of sata_configreg_top Registers................................................................4660
17-3Summary of sata_configreg_top Registers................................................................4661
17-4Summary of sata_configreg_top Registers................................................................4707
17-5Summary of sata_configreg_top Registers................................................................4709
17-6Summary of sata_configreg_top Registers................................................................4713
17-7Summary of sata_configreg_top Registers................................................................4745
17-8Summary of sata_configreg_top Registers................................................................4747
17-9Summary of sata_configreg_top Registers................................................................4795
17-10Summary of sata_configreg_top Registers ..............................................................4797
18-1Summary of 0_20_0_USBx MMIO Registers Registers ................................................4801
18-2Summary of 0_20_0_USBx PCI Config Registers Registers .........................................5117
18-3Summary of 0_20_0_usbx_exi_on_dbc_registers Registers ........................................5150
18-4Summary of USBX device top Registers ...................................................................5269

334818 3
 18-5Summary of USBX device top Registers ................................................................... 5350
18-6Summary of USBX device top Registers ................................................................... 5398
18-7Summary of USBX device top Registers ................................................................... 5407
18-8Summary of USBX device top Registers ................................................................... 5411
18-9Summary of USBX device top Registers ................................................................... 5415
18-10Summary of USBX device top Registers ................................................................. 5427
18-11Summary of 0_20_0_USBx MMIO Registers Registers.............................................. 5439
18-12Summary of 0_20_0_USBx PCI Config Registers Registers ....................................... 5757
18-13Summary of 0_20_0_usbx_exi_on_dbc_registers Registers ...................................... 5791
18-14Summary of USBX device top Registers ................................................................. 5909
18-15Summary of USBX device top Registers ................................................................. 5991
18-16Summary of USBX device top Registers ................................................................. 6041
18-17Summary of USBX device top Registers ................................................................. 6051
18-18Summary of USBX device top Registers ................................................................. 6055
18-19Summary of USBX device top Registers ................................................................. 6059
18-20Summary of USBX device top Registers ................................................................. 6071
19-1Summary of CONVERGE_LAYER Registers................................................................ 6083
19-2Summary of CONVERGE_LAYER Registers................................................................ 6096
19-3Summary of CONVERGE_LAYER Registers................................................................ 6108
19-4Summary of soc_regs_wrapper Registers ................................................................ 6121
19-5Summary of SDHOST_OCP Registers ...................................................................... 6134
19-6Summary of soc_regs_wrapper Registers ................................................................ 6171
19-7Summary of SDHOST_OCP Registers ...................................................................... 6184
19-8Summary of soc_regs_wrapper Registers ................................................................ 6222
19-9Summary of SDHOST_OCP Registers ...................................................................... 6235
19-10Summary of CONVERGE_LAYER Registers .............................................................. 6275
19-11Summary of CONVERGE_LAYER Registers .............................................................. 6289
19-12Summary of CONVERGE_LAYER Registers .............................................................. 6303
19-13Summary of soc_regs_wrapper Registers............................................................... 6317
19-14Summary of SDHOST_OCP Registers..................................................................... 6331
19-15Summary of soc_regs_wrapper Registers............................................................... 6369
19-16Summary of SDHOST_OCP Registers..................................................................... 6383
19-17Summary of soc_regs_wrapper Registers............................................................... 6421
19-18Summary of SDHOST_OCP Registers..................................................................... 6435

4 334818
1 SoC Address Map

1.1 Root Spaces sup

The SoC supports two root spaces: Host and CSE. Each root space contains an
orthogonal address map. The Host address space is associated with the Atom CPUs.
The CSE root space is associated with the CSE minute IA CPU.

Each root space supports an independent IA system. Within a given IA system (Host or
CSE), the IA architecture defines several distinct address spaces that are accessible
through different mechanisms. Some of these spaces have clean architectural
definitions and others are less clean and overlap. It is not uncommon for a window in
one address space to allow access to resources in another space. This is true both for
address spaces within one root space (e.g., a Host Memory Address Space window to
Host PCI config space) and between Root spaces (e.g., a CSE Memory Address Space
window to DRAM that is also accessible from the Host Memory Space).

1.2 Super Set Architecture Definition

This Address MAP covers a super set of possible SoC configurations. Specifically, it
refers to various address ranges that can be mapped to LPC or SPI. However, not all
SoC instances will allow all of these configurations.

Note: The term “IAFW” is used throughout this document as a generic term for platform
specific code that runs on the IA cores before the OS is loaded, often referred to as
“BIOS”. The term “BIOS” is typically used for PC platforms, whereas mobile and
Android based platforms typically refer to IAFW.

334818 Intel Top Secret 5

2 Host Root Space

The following address spaces are available within the Host Root space:
• Memory
• I/O
• PCI Configuration
• Funny I/O
• IOSF SB Private CR space

2.1 Host Memory Address Space

The SoC implements 39 address bits providing 512 GB of addressable memory space
for use by the CPU and devices. This is the address space accessible by memory reads
and writes and is the set of addresses as presented to the System Controllers or
devices from either the CPU or devices. For PCI compliance the devices and IOSF fabric
implement a full 64 b address space. Addresses greater than 512 GB never address a
physical resource in the SoC and are always terminated with an error.

6 Intel Top Secret 334818

Figure 2-1. Host Memory Address Map

Host Memory Address Space

32
2
39 2 01_0000_0000
80_0000 _0000

BIOS
0xFF00_0000
DRAM

Local APIC (MSI)

0xFEE 0_0000
MMIO xHCI.DBC 0xFED6_0000
TPM 0xFED4_0000
HPET 0xFED0_0000

MMIO-hi IO APIC
PCIe MMCFG 0xFEC0_0000
Relocatable Based on BAR
CRAB Abort
0xFEB0_0000

TOLUD
DSM

BDSM GSM

BGSM
TSEG
TOUUD TSEG BASE
PAM
0x000 E_0000

0x000C_0000
DRAM-Low
PRMRR PRMRR
PRMRR (relocatable ) Legacy VGA
PMR-H PMR-L 0x000 A_0000
PHMR PLMR
DRAM-High

DOS
Range
32
2 0x01_0000_0000
TOLUD MMIO-low 0x00_0010 _0000 Compatibility
1M
DRAM-Low Area
0
Uncore 39 bit
Lower 32 bits
Address Space
(4 GB)
(512 GB)

System DRAM memory is split into multiple independent architectural physical memory
segments. In order to enable System DRAM to be addressed contiguously at the
memory controller, “System DRAM address space” was defined. A transformation is
applied to the physical address to obtain the System DRAM address. Section 2.2,
"System DRAM Address Space" provides details on Physical to System DRAM
transformation. The SoC memory protection, security and coherency checks are
performed on the Physical memory address before transformation.

VT-d adds the concept of Guest Physical Address or GPA and Host Physical address
space or HPA. The Physical Address Space defined in this section corresponds to the
HPA. A GPA is an un-translated address.

2.1.1 Host Memory Space Address Decode and Routing

Transactions in the Host Memory Space originate from two classes of sources: IDI
attached and IOSF attached. These transactions must be routed, by address, to the
appropriate resources. Address decode responsibilities are divided between the System

334818 Intel Top Secret 7

 Agent and the IOSF fabric. This section will cover the details of System Agent address
decode logic. The System Agent address decode logic is implemented in two parts. The
B-Unit implements the majority of the address decode logic, with the A-Unit also
implementing a first level address decode for upstream requests from IOSF.

The B-Unit system address decode logic will positively decode transactions to the
following locations:

DRAM
• C-unit (Host Bridge functionality: Dev0 Fun0)
• SPI (BIOS, dTPM)
• LPC (BIOS, dTPM, misc non-standard ranges)
• CSE (BIOS and fTPM)
• Display
• I-Unit

Any transaction that arrives at the B-Unit from the A-Unit and is decoded to return to
the A-Unit will be aborted. Transactions that are not positively decoded will be routed to
PSF1.

The A-Unit system decode logic will positively decode upstream requests from IOSF
agents as follows:
• Within MSI address range (0xFEEx_xxxx)  route to Tunit
• Within DRAM memory aperture  route to Bunit
• Otherwise  abort
The Host memory address space is configurable. This document does not provide the
detailed register definitions. This following table provides the names and a description
of the primary registers used to control the memory configuration.

Table 2-1. Memory Map Configuration Registers

Register Name Definition

TOUUD Top of Upper Usable DRAM. Address above TOUUD target High MMIO. Address from 4 GB up to TOUUD
target DRAM.

TOLUD Top of Low Usable DRAM. As a rule addresses below TOLUD target DRAM target DRAM and addresses
between TOLUD and 4 GB target devices in MMIO space. There are exceptions to the rule.

BDSM Base of graphics Data Stolen Memory. A region used by the Integrated Graphics Device (IGD). BDSM
specifies the base and TOLUD specifies the DSM region.

BGSM Base of Graphics Stolen Memory. A region used by the IGD. BGSM specifies the base, and BDMS specifies
the limit of the GSM region.

TSEGMB T segment Memory Base. The region used for SMM protected DRAM. TSEGMB specifies the base, and
BGSM specifies the limit.

BMISC Contains fields for enabling various legacy regions including VGA and the BIOS PAM regions.

2.1.2 Abort Handling

The term “abort” is used in this document to handle a few different error handling
mechanisms.

8 Intel Top Secret 334818

2.1.2.1 B-Unit Abort Handling
Non-posted Transactions that are aborted in the B-Unit will have a completion
returned: to the IDI originator with bogus data (all ‘1’s), to IOSF agents the completion
is a UR with no data. Posted transactions that are aborted in the B-Unit are dropped
without altering the contents of system memory. Depending on the reason for the
abort, the B-Unit will follow different error logging behaviors.

2.1.2.2 IOSF Abort Handling

Transactions routed to IOSF will be aborted in the fabric or in the P2SB. Non-posted
transactions are completed with a UR completion. The A-Unit converts the zero-length
UR completion into a completion with all ‘1’s. Posted transactions that are aborted are
dropped. Error handling in the IOSF fabric follows the rules of the IOSF fabric and if
errors are detected in the fabric the error message is sent to the ITSS error collector
logic over sideband.

2.1.3 Low DRAM Address Range (0 to (TOLUD - 1)

As a rule all addresses from 0 to Top of Low Usable DRAM (TOLUD - 1) are routed to
DRAM. There are exceptions to this rule. The following sub sections describe the
exceptions to the rule.

Table 2-2. Low DRAM Default Address Decode Rule

Name Low DRAM

Range 0 to (TOLUD – 1)

From IDI DRAM, unless a specific rule supersedes this rule.

From IOSF DRAM, unless a specific rule supersedes this rule.

Security IMR ranges are SAI protected.

2.1.3.1 Legacy Video Area (A_0000h to B_FFFFh)

The legacy 128 KB VGA memory range, (000A_0000h to 000B_FFFFh, also known as
ASEG and BSEG) can be mapped to IGD or to a PCIe root port; the mapping is
configured in the B-Unit BMISC register. The appropriate mapping depends on which
devices are enabled and the programming of the VGA steering bits. If the VGA region is
enabled and the transactions are not targeting the IGD, then they will be routed to the
PCIe root port with the VGA enable bit of the bridge control register set.

The VGA range can be divided into three sub-ranges. Each range is either routed to the
IGD or a PCIe root port based on the steering bits.

The following conditions are used to determine where to route addresses within this
range:
• ABSegInDRAM:
BMISC.ABSegInDRAM = 1
• IGDEnabled:
(0.0.0.PCI.DEVEN.D2F0EN = 1)
AND (0.2.0.PCI.PMCSR.PSRSTAT = 2’b00)
AND (0.2.0.PCI.PCICMD2.MAE = 1)

334818 Intel Top Secret 9

 • VGAAtoIGD:
((VGAAtoIGD1 = 1) OR (VGAAtoIGD2 = 1))
• VGAAtoIGD1:
(GGC.GGMS ≠ 5’b00000 )
AND (GGC.IVD = 0)
AND (VGADEC.VGAMSR1 = 1)
AND (VGADEC.VGAGR10 = 1)
• VGAAtoIGD2:
(!VGAAtoIGD1)
AND ((VGADEC.VGAGR6 = 2’b00) OR (VGADEC.VGAGR6 = 2’b01))
• MDAtoIGD:
(!VGAAtoIGD1)
AND (VGADEC.VGAGR6 = 2’b10)
• VGABtoIGD:
(!VGAAtoIGD1)
AND (VGADEC.VGAGR6 = 2’b11)

Table 2-3. Legacy VGA A

Name VGA A

Range 0xA_0000 to 0xA_FFFF

From IDI IF (ABSegInDRAM)

Route to DRAM
ELSE IF (IGDEnabled and VGAAtoIGD)
Route to Display
ELSE
Route to PSF1

From IOSF IF (ABSegInDRAM)

Route to DRAM
ELSE
Abort: Send to System Agent.

Note: no A-Unit decode is required for this range.

Security No restrictions

10 Intel Top Secret 334818

Table 2-4. Legacy MDA
Name MDA (Monochrome Display Adaptor)

Range 0xB_0000 to 0xB_7FFF

From IDI IF (ABSegInDRAM)

Route to DRAM
ELSE IF (IGDEnabled and MDAtoIGD)
Route to Display
ELSE
Route to PSF1

From IOSF IF (ABSegInDRAM)

Route to DRAM
ELSE
Abort: Send to System agent.

Note: no A-Unit decode is required for this range.

Security No restrictions

Table 2-5. Legacy VGA B

Name VGA B

Range 0xB_8000 to 0xB_FFFF

From IDI IF (ABSegInDRAM)

Route to DRAM
ELSE IF (IGDEnabled and VGABtoIGD)
Route to Display
ELSE
Route to PSF1

From IOSF IF (ABSegInDRAM)

Route to DRAM
ELSE
Abort: Send to System agent.

Note: no A-Unit decode is required for this range.

Security No restrictions

2.1.3.1.1 Legacy VGA and Compatible Mode SMM

The SoC does not support legacy SMM usage of the VGA range.

2.1.3.2 Expansion Area (C_0000h to D_FFFFh)

The SoC does not Support the ISA Expansion region. This area always maps to system
DRAM.

2.1.3.3 PAM Memory Area (E_0000h to F_FFFFh)

The SoC does NOT support the PAM regions. The PAM Memory Area has historically
been used for accessing IAFW code from flash.

ISA Hole (15 MB to 16 MB)

The SoC Does NOT support the ISA Hole Feature. This range is always mapped to
DRAM.

334818 Intel Top Secret 11

2.1.3.4 Protected Memory Range (PMR-L: programmable)
VT-d defines a protected memory range. This range is re-locatable. This range must be
protected by IMRs to ensure only the IA core has access to this range before VT-d
translation is enabled.

There is one range per VT-d engine. So the SoC has two PMR-L ranges.

In addition to PMR-L (below 4 GB) there is a PMR-H above 4 GB with the same access
restrictions.

Table 2-6. PMR-L

Name PMR-L

Range 0.0.0.DefVTdBAR.PMRLBASE to 0.0.0DefVTdBAR.PMRLLIMIT

and 0.0.0.GfxVTdBAR.PMRLBASE to 0.0.0GfxVTdBAR.PMRLLIMIT

From IDI DRAM

From IOSF DRAM or ABORT (based on security)

Security GT has a copy of GfxVTd PMR. It will make sure that only VT-d walks are allowed to touch PMR and hence
get onto IDI. Other tnx that hit PMR are killed before they get onto IDI.
Display will add GfxVTd PMR. It will make sure that only VTd walks are allowed to go to PMR range and all
other tnx will be killed before they get onto IOSF primary.
DefVTd PMR will be implemented in Bunit.

2.1.3.5 DMA Protected Range (DPR: Programmable)

The SoC Address map does not support DPR. This range is used in big core systems as
part of the TXT security model.

2.1.3.6 TSEG SMM Range (Programmable)

This range is set up by IAFW and must match the range specified for SMM in the core
MSRs. TSEGMB is the base of the range, and the limit is defined by BGSM (Bottom of
Graphics Stolen Memory). This range is SAI protected and only transactions originating
in SMM mode from the IA cores are allowed access.

Table 2-7. TSEG

Name TSEG

Range 0.0.0.TSEGMB to (0.0.0.BGSM - 1)

From IDI DRAM or ABORT

From IOSF DRAM or ABORT (Abort if enabled by SAI check)

Security SAI protected.

2.1.3.7 Graphics Stolen Memory (Programmable)

The base of graphics stolen memory is defined by BGSM (Base of Graphics Stolen
Memory). The limit is defined by TOLUD. This region is SAI protected and only Display
and GT are allowed access.

12 Intel Top Secret 334818

 The IGD further subdivides this range, however outside of the IGD the access
protections are the same and the system is not aware of the further sub-division. These
divisions include a Data segment and a PCM segment. The enforcement of access
restrictions within GSM to the data segment or the PCM segment is the responsibility of
the GT logic and Display.

Table 2-8. GSM

Name GSM

Range 0.0.0.MCHBAR.BGSM to (0.0.0.MCHBAR.TOLUD - 1)

From IDI DRAM or ABORT

From IOSF DRAM or ABORT

Security SAI protected.

2.1.4 Low MMIO Address Range (TOLUD to 4 GB)

This address range, from BUNIT.BMBOUND to 4 GB is primarily used for devices in
MMIO space. Section 2.1.6, "High MMIO Address Range (TOUUD to 0x7F_FFFF_FFFF)"
provides a summary of all legacy fixed and programmable MMIO address ranges in the
SoC.

Root complex integrated PCI devices have memory space BARs that can be configured
to claim memory within this region. Root Ports (PCIe or Mobile Express) have Base and
limit range registers that can be configured to claim memory within this region. IAFW
and the OS ensure that the PCI BARs are not programmed to overlap with any of the
legacy address ranges.

Table 2-9. Low MMIO Address Range

Name Low MMIO

Range 0.0.0.MCHBAR.TOLUD to 0xFFFF_FFFF

From IDI PSF1 on VC0b, unless a specific rule supersedes this rule.

From IOSF IF (VC0a)

PSF1 on VC0b, unless a specific rule supersedes this rule.
ELSE IF (VC0b)
Abort, Send to system agent, unless a specific rule supersedes this rule.
ELSE

Security No restrictions, unless a specific rule supersedes this rule.

2.1.4.1 PCIe Memory Mapped Config Range (Programmable)

A 256 MB range used to access PCI configuration registers.

Note: A fixed PCI config MM space of 256 MB is overkill and would waste DRAM space on a
32 b (4 GB) system. Ideally the MM window would be configurable to match the needs
of the system and minimize DRAM waste. This needs to be investigated for future
derivatives.

334818 Intel Top Secret 13

 The System Agent is responsible for converting the transactions to PCI config
transactions. The B-Unit does some address decode of PCI config space, but most
transactions are forwarded subtractively to PSF1 and the IOSF fabric is responsible for
decode.

Note: When I-Unit is configured as a “child of graphics”, the I-Unit PCI config space will be
disabled and configuration transactions to B/D/F 0/3/0 will be routed to the IOSF fabric
and aborted.

Table 2-10. PCIe MMCFG

Name PCIeMMCFG

Range BAR: 0.0.0.MCHBAR.PCIEXBAR (size 256 MB)

From IDI IF (0.0.0.MCHBAR.PCIEXBAR.ECEnable = 1)

Convert to PCI configuration cycle

IF (B/D/F = 0/0/0)
C-unit on VC0b
ELSE IF ((B/D/F = 0/2/0) AND (DEVEN.D2F0EN))
Display on VC0a
ELSE IF ((B/D/F = 0/3/0) AND (DEVEN.D3F0EN))
I-Unit on VC0a
ELSE
PSF1

From IOSF Default (see Low MMIO range)

Security GT is not allowed to access this range. If GT does attempt access the transaction is forwarded to IOSF as a
Memory transaction.

2.1.4.2 Host Bridge

The host bridge located at Bus0, Dev0, Fn0 contains three non-standard BARs.
MCHBAR is defined in a PCI configuration register. The Two VTd BARs are MMIO
registers in the MCHBAR range. Each of these BARs has an enable bit. If the BAR is not
enabled, the address decoder should ignore the value programmed in the upper bits of
the BAR.

MCHBAR is the BAR for all System Agent memory mapped registers. Transactions are
routed on IOSF primary to the C-unit and from the C-unit they are distributed as
needed on IOSF SB.

The A-Unit TAD should not decode for MCHBAR, DefVTDBAR or GFxVTdBAR. This will
prevent P2P transactions from VC0a targeting the C-unit. These 3 BARs are source
decoded by B-Unit.

Table 2-11. MCHBAR (Sheet 1 of 2)

Name MCHBAR

Range BAR: 0.0.0.PCI.MCHBAR size (32 KB)

14 Intel Top Secret 334818

Table 2-11. MCHBAR (Sheet 2 of 2)
Name MCHBAR

From IDI IF (0.0.0.PCI.MCHBAR.MCHBAREnable = 1)

C-unit
ELSE

From IOSF Default (see Low MMIO range)

Security B-Unit

The Default VTd BAR is the BAR for the Default IOMMU memory mapped registers.
Transactions are routed on IOSF primary to the C-unit. The C-unit forwards the
transaction to the Default IOMMU on IOSF SB.

Table 2-12. Default VTd BAR

Name DefVTdBAR

Range BAR: 0.0.0.MCHBAR.DefVTdBAR (4 KB)

From IDI IF (0.0.0.PCI.DefVTdBAR.DefVtdBAREnable = 1)

C-unit
ELSE

From IOSF Default (see Low MMIO range)

Security No restrictions.

The Graphics VTd BAR is the BAR for the Graphics IOMMU memory mapped registers.
Transactions are routed on IOSF primary to Display.

Although this is a dev0 owned memory BAR, the registers live in dev2 and dev2 must
be enabled to access this memory range.
• IGDEnabled:
(0.0.0.PCI.DEVEN.D2F0EN = 1)
AND (0.2.0.PCI.PMCSR.PSRSTAT = 2’b00)
AND (0.2.0.PCI.PCICMD2.MAE = 1)

Table 2-13. Graphics VTd BAR

Name GfxVTdBAR

Range BAR: 0.0.0.MCHBAR.GfxVTdBAR (4 KB)

From IDI IF (0.0.0.MCHBAR.GFxVTdBAR.VtdBAREnable = 1) && IGDEnabled

Display
ELSE

From IOSF Default (see Low MMIO range)

Security No restrictions.

334818 Intel Top Secret 15

2.1.4.3 Integrated Graphics Device (IGD)

Note: The IGD BARs are not restricted to Low MMIO space and could be programmed in High
MMIO space.

Note: The Integrated graphics device has two Host Memory Space BARs. These are standard
PCI BARs.

Note: Address decode to these BARs are valid if the Integrated Graphics device is enabled
and system software has enabled the Memory Access to the device:
• IGDEnabled:
(0.0.0.PCI.DEVEN.D2F0EN = 1)
AND (0.2.0.PCI.PMCSR.PSRSTAT = 2’b00)
AND (0.2.0.PCI.PCICMD2.MAE = 1)
• MCHBARAlias:
offsets 0x14_0000 to 0x14_7FFF from GTTMADDR BASE

The registers in the IGD that live behind the GTTMMADR BAR are accessible in three
ways:
• By IA or peer transactions through the MMIO BAR described in this section
Section 2.4.2.1, "Integrated Graphics Device (IGD)")
• By GT using Funny I/O transactions
• By IA using an I/O BAR.

Table 2-14. GTTMMADR

Name GTTMMADR

Range BAR: 0.2.0.PCI.GTTMMADR (16 MB)

From IDI IF (IGDEnabled)

IF (MCHBARAlias and Read)
Cunit
ELSE IF (MCHBARAlias and Write)
Abort
ELSE
Display
ELSE

From IOSF IF (VC0a)

PSF1
ELSE IF (VC0b and IGDEnabled)
Display
ELSE

Security No Restrictions.

16 Intel Top Secret 334818

Table 2-15. GMADR
Name GMADR

Range BAR: 0.2.0.PCI.GMADR (re-sizeable by 0.2.0.PCI.MSAC 128 MB to 4 GB)

From IDI IF (IGDEnabled)

Display
ELSE

From IOSF Default (see Low MMIO range)

Security No restrictions.

2.1.4.4 I-Unit
The I-Unit contains one standard PCI BAR.

Note: The I-Unit BARs are not restricted to Low MMIO space and could be programmed in
High MMIO space.

Table 2-16. I-Unit BAR

Name IBAR

Range BAR: 0.3.0.PCI.IBAR (16 MB)

From IDI IF ( (0.0.0.PCI.DEVEN.D3F0EN = 1)

AND (0.3.0.PCI.PMCSR.PSRSTAT = 2’b00)
AND (0.3.0.PCI.PCICMD2.MAE = 1))
I-Unit
ELSE
Default (See Low MMIO Range)

From IOSF Default (see Low MMIO range)

Security No restrictions.

2.1.4.5 LPC Generic Memory Range

The LPC logic has a non-standard memory range. The system agent performs source
decoding on this range. The destination is LPC. If the SoC has no LPC, then these
ranges are n/a.

LPC Generic Memory Range. Enable via setting bit[0] of the LPC Generic Memory Range
register (D31:F0:offset 98h).

334818 Intel Top Secret 17

Table 2-17. LPC Generic Memory Range
Name LPC Generic Memory Range

Range BAR: 0.31.0.PCI.LGMR (offset 98h)

From IDI IF (0.31.0.PCI.LGMR.bit0 = 1)

IF (LPC enabled)
LPC
ELSE
Default (See Low MMIO Range)
ELSE

From IOSF Default (see Low MMIO range)

Security No restrictions.

2.1.4.6 CRAB_ABORT (0xFEB0_0000 to 0xFEBF_FFFF)

The CPU will re-map various access violations to target the CRAB_ABORT page.

Table 2-18. CRAB_ABORT

Name CRAB ABORT

Range 0xFEB0_0000 to 0xFEBF_FFFF

From IDI Abort

From IOSF Abort—Route to B-Unit no decode required in A-Unit

Security No restrictions.

2.1.4.7 IOAPIC (0xFEC0_0000 to 0xFECF_FFFF)

The IOAPIC has a small MMIO window that is located at 0xFECX_X000-FECX_X040.
IAFW configures the exact location using the APIC Range Select (ASEL) field and APIC
Enable (AEN) bit. For the SoC only ASEL programming placing the range at
0xFEC0_0000 to 0xFEC0_0040 will be validated.

Table 2-19. IOAPIC

Name IOAPIC

Range 0xFECX_X000 to 0xFECX_X040

From IDI Subtractive to PSF1

From IOSF Default (see Low MMIO range)

Security No restrictions.

2.1.4.8 HPET (0xFED0_0000 – 0xFED0_33FF)

IAFW can configure the HPET timers to be located at one of four locations:
0xFED0_X000 to 0xFED0_X3FF where X = {0, 1, 2, or 3}. For the SoC, will only
validate with X = 0.

18 Intel Top Secret 334818

Table 2-20. HPET
Name HPET

Range 0xFFD0_X000 to 0xFED0_X3FF (X = {0, 1, 2, or 3})

From IDI PSF1

From IOSF Default (see Low MMIO range)

Security No restrictions.

2.1.4.9 TPM (0xFED4_0000 to 0xFED4_0FFF)

The range from 0xFED4_0000 to 0xFED4_0FFF is reserved for use by the TPM. The
location of the TPM is determined by a strap and transactions to this address are routed
towards the TPM (CSE, SPI or LPC).

Table 2-21. TPM locality 0

Name TPM

Range 0xFED4_0000 to 0xFED4_0FFF

From IDI IF (TPM at CSE)

CSE
ELSE IF (TPM_at_LPC)
LPC
ELSE
PSF error handler.

From IOSF Default (see Low MMIO range)

Security No restrictions.

2.1.4.10 TXT (0xFED2_0000 to 0xFED3_FFFF)

The range from 0xFED2_0000 to 0xFED3_FFFF is the TXT public and private ranges.
This range is not used on the SoC and is aborted in the system agent.

Table 2-22. TPM Locality 1-3

Name TPM

Range 0xFED2_0000 to 0xFED3_FFFF

From IDI Abort

From IOSF Default (see Low MMIO range)

Security Always aborted

2.1.4.11 TPM (0xFED4_1000 to 0xFED4_3FFF)

The range from 0xFED4_1000 to 0xFED4_3FFF is the TPM locality 1 to 3 range. These
are not used on the SoC and are aborted in the system agent.

334818 Intel Top Secret 19

Table 2-23. TPM Locality 1-3
Name TPM

Range 0xFED4_1000 to 0xFED4_3FFF

From IDI Abort

From IOSF Default (see Low MMIO range)

Security Always aborted

2.1.4.12 xHCI.DBC (0xFED6_0000 to 0xFED6_0FFF)

The range from 0xFED6_0000 to 0xFED6_0FFF is reserved for P2P traffic targeting the
xHCI DBC endpoint. The OS must be informed that this address range is reserved, and
no other MMIO address should overlap with this range. There is not address decode
awareness of this address range. Addresses in this range must use source decode on
the PSF fabric. A transaction in this range without source decode will be subtractively
aborted.

Table 2-24. xHCI.DBC

Name TPM

Range 0xFED6_0000 to 0xFED6_0FFF

From IDI Default (see Low MMIO range)

From IOSF Default (see Low MMIO range)

Security Always aborted

2.1.4.13 Local APIC (0xFEE0_0000 to 0xFEEF_FFFF)

The range from 0xFEE0_0000 to 0xFEEF_FFFF is reserved signaling interrupts to the
local APICs inside the CPU cores. Accesses to this range from I/O devices are routed
upstream to the cores.

Table 2-25. IOAPIC

Name Local APIC

Range 0xFEE0_0000 to 0xFEEF_FFFF

From IDI Subtractive to PSF1

From IOSF T-Unit

Security No requirements

2.1.4.14 IAFW (BIOS) (0xFFXX_0000 to 0xFFFF_FFFF)

The range of memory at the top of Low MMIO is used to access IAFW (aka BIOS) during
boot. The size of this range is configurable from 256 KB to 16 MB. The range is always
aligned to end at 4 GB - 1. The first instruction fetch after reset targets address
0xFFFF_FFF0.

20 Intel Top Secret 334818

 The on die SRAM size is limited to 256 KB. When booting from LPC or SPI, the controls
to configure the size of the region are in either the BIOS Decode Register in LPC or SPI
(depending on which is enabled).

The IAFW region can be mapped to one of three physical locations: CSE SRAM, LPC, or
SPI flash.
• BIOSinSRAM
• BIOSinLPC
• BIOSinSPI
The IAFW range is broken into four sub-ranges. BIOS1 always is used for BIOS. BIOS2,
BIOS3 and BIOS4 may be used for BIOS or may be used as default MMIO addresses.

The BIOS3 and BIOS4 range is controlled by the BDE (BIOS Decode Enable) register.
When LPC is enabled the system agent should use the LPC BDE register. When SPI is
enabled the LPC should use the SPI BDE register.

Table 2-26. BIOS1

Name BIOS

Range 0xFFFC_0000 to 0xFFFF_FFFF

From IDI IF (BIOSinLPC)

LPC
ELSE IF (BIOSinSPI)
SPI
ELSE
CSE SRAM (note use IOSF DestID for CSE)

From IOSF Default (see Low MMIO range)

Security Perform SAI Completion check in system agent.

Perform SAI check at CSE SRAM.

Table 2-27. BIOS2

Name BIOS2

Range 0xFFF8_0000 to 0xFFFB_FFFF

From IDI IF (BIOSinLPC)

LPC
ELSE IF (BIOSinSPI)
SPI
ELSE
PSF1

From IOSF Default (see Low MMIO range)

Security No Requirements

334818 Intel Top Secret 21

Table 2-28. BIOS3
Name BIOS3

Range 0xFF80_0000 to 0xFFF7_FFFF

From IDI IF (BIOSinLPC AND (BDE[14:8] = 7’b111_1111))

LPC
ELSE IF (BIOSinSPI AND (BDE[14:8] = 7’b111_1111))
SPI
ELSE
PSF1

From IOSF Default (see Low MMIO range)

Security No requirements.

Table 2-29. BIOS4

Name BIOS4

Range 0xFF00_0000 to 0xFF7F_FFFF

From IDI IF (BIOSinLPC AND (BDE[3:0] = 4’b1111))

LPC
ELSE IF (BIOSinSPI AND (BDE[3:0] = 4’b1111))
SPI
ELSE
PSF1

From IOSF Default (see Low MMIO range)

Security No requirements.

2.1.4.14.1 BIOS Decode Enable Register Restrictions

To simplify the decoder in the B-Unit the legal programming of BDE need to be
restricted.

BDE[14:8] must be set or cleared together. This creates one region from 0xFF80_0000
to 0xFFF7_FFFF (7.5 MB in size).
• BDE[3:0] must be set or cleared together. This creates one 8 MB range from
0xFF00_0000 to 0xFF7F_FFFF.

Base Limit Enable

0xFFF8_0000 0xFFFB_FFFF

0xFFF0_0000 0xFFF7_FFFF bde[14]

0xFFE8_0000 0xFFEF_FFFF bde[13]

0xFFE0_0000 0xFFE7_FFFF bde[12]

0xFFD8_0000 0xFFDF_FFFF bde[11]

0xFFD0_0000 0xFFD7_FFFF bde[10]

0xFFC8_0000 0xFFCF_FFFF bde[9]

0xFFC0_0000 0xFFC7_FFFF bde[8]

0xFFB8_0000 0xFFBF_FFFF

0xFFB0_0000 0xFFB7_FFFF bde[14]

22 Intel Top Secret 334818

 Base Limit Enable

0xFFA8_0000 0xFFAF_FFFF bde[13]

0xFFA0_0000 0xFFA7_FFFF bde[12]

0xFF98_0000 0xFF9F_FFFF bde[11]

0xFF90_0000 0xFF97_FFFF bde[10]

0xFF88_0000 0xFF8F_FFFF bde[9]

0xFF80_0000 0xFF87_FFFF bde[8]

0xFF70_0000 0xFF7F_FFFF bde[3]

0xFF60_0000 0xFF6F_FFFF bde[2]

0xFF50_0000 0xFF5F_FFFF bde[1]

0xFF40_0000 0xFF4F_FFFF bde[0]

0xFF30_0000 0xFF3F_FFFF bde[3]

0xFF20_0000 0xFF2F_FFFF bde[2]

0xFF10_0000 0xFF1F_FFFF bde[1]

0xFF00_0000 0xFF0F_FFFF bde[0]

2.1.5 High DRAM (0x1_0000_0000 to (TOUUD - 1))

The range from 4 GB (1_0000_0000h) to (TOUUD - 1) is mapped to DRAM. When there
is no DRAM above 4 GB, TOUUD may be programmed to a value below 4 GB. In that
case this range is effectively disabled.

Table 2-30. High DRAM

Name

Range 0x1_0000_0000 to (TOUUD - 1)

From IDI DRAM

From IOSF DRAM

Security IMR ranges are SAI protected.

2.1.5.1 Protected Memory Range (PMR-H: Programmable)

VT-d defines a high (greater than 4 GB) protected memory range. This range is re-
locatable. This range must be protected by IMRs to ensure only the IA core has access
to this range before VT-d translation is enabled.

There is one range per VT-d engine. So the SoC has two PMR-H ranges.

In addition to PMR-H (above 4 GB) there is a PMR-L below 4 GB with the same access
restrictions.

334818 Intel Top Secret 23

Table 2-31. PMR-H
Name PMR-H

Range 0.0.0.DefVTdBAR.PMRHBASE to 0.0.0DefVTdBAR.PMRHLIMIT

and 0.0.0.GfxVTdBAR.PMRHBASE to 0.0.0GfxVTdBAR.PMRHLIMIT

From IDI DRAM

From IOSF DRAM

Security GT has a copy of GfxVTd PMR. It will make sure that only VT-d walks are allowed to touch PMR and hence
get onto IDI. Other tnx that hit PMR are killed before they get onto IDI.
Display will add GfxVTd PMR. It will make sure that only VTd walks are allowed to go to PMR range and all
other tnx will be killed before they get onto IOSF primary.
DefVTd PMR will be implemented in Bunit.
https://hsdes-stable.intel.com/home/default.html#article?id=101147810

2.1.6 High MMIO Address Range (TOUUD to 0x7F_FFFF_FFFF)

The range from TOUUD to 512 GB (7F_FFFF_FFFFh) is used for devices in MMIO space.
There are no legacy fixed or programmable MMIO address ranges in High MMIO space.

Root complex integrated PCI devices have memory space BARs that can be configured
to claim memory within this region. Root Ports (PCIe or Mobile Express) have Base and
limit range registers that can be configured to claim memory within this region.

Table 2-32. High MMIO Address Range

Name High MMIO

Range 0.0.0.MCHBAR.TOUUD to 0x7F_FFFF_FFFF

From IDI PSF1, unless a specific rule supersedes this rule.

From IOSF PSF1, unless a specific rule supersedes this rule.

Security No restrictions.

2.1.6.1 Other Ranges in High MMIO Address Ranges

Many of the programmable ranges defined in the Low MMIO Address Range can be
configured to be in either Low or High MMIO Address space. The following list of ranges
in Low MMIO space may be configured into High MMIO space:
• MCHBAR
• Default VTd BAR
• Graphics VTd BAR
• GTTMMADR
• GTMADR
• IBAR

2.2 System DRAM Address Space

This is the range of addresses presented to the memory controller after all security
checks and reclaiming has been done. The memory controller is aware of the total
amount of populated DRAM and addresses above this range are considered invalid –
writes will be dropped and reads will return all ‘1’s.

24 Intel Top Secret 334818

 In truth, memory controllers have options to swizzle which System DRAM Address
Space address bits map to banks, rows, columns to increase performance. For
purposes of this discussion, this mapping is assumed to 1-to-1.

2.2.1 Physical to System DRAM Address Mapping

Inside the system agent the Physical Address is converted to a System DRAM Address.
This is done to “reclaim” all addressable DRAM that would otherwise be lost because
the addresses conflict with the Low MMIO range.

Figure 2-2. Physical to System DRAM Address Map

SystemDRAMSpace Physical Address Space

512GB: 0x7F_FFFF_FFFF

High MMIO
TOUUD

High DRAMWindow

BIOSBoot
IO-APIC
4GB: 0x01_0000_0000
LPC/TPM
HPET
Low MMIO IO-APIC
TOLUD ABORT
OSVisible DRAM
ExtendedConfig

Low DRAMWindow

PROM“F” Range 0x00_000F_0000 to 0x00_000F_FFFF

PROM“E” Range 0x00_000E_0000 to 0x00_000E_FFFF
1MB: 0x00_0010_0000

DOSDRAM DOSDRAM

VGA 0x00_000A_0000 to 0x00_000B_FFFF

2.2.2 Case 1: 2 GB DRAM. Minimum 1 GB PCI MMIO

BUNIT.TOLUD needs to be no greater than 3 GB to make room for 1 GB of Low MMIO
between TOLUD and 4 GB.

TOLUD could be set to 3 GB, but any Physical Address Space request from 2 GB to 3 GB
will exceed available DRAM and this range will need to be marked as unavailable by the
IAFW to the OS (“bad”). Instead, it is better to leave the 2 GB to 3 GB Physical Address
Space range available for MMIO devices. Setting TOLUD to 2 GB makes all 2 GB of
DRAM available and provides 2 GB of Low MMIO space.

Because available DRAM is less than 4 GB, BUNIT.TOUUD should be set to 4 GB,
allowing all of the 4 GB to 64 GB address space to be used for 64 b PCI MMIO.

334818 Intel Top Secret 25

2.2.3 Case 2: 8 GB DRAM. Minimum 1 GB PCI MMIO
BUNIT.TOLUD needs to be no greater than 3 GB to make room for 1 GB of Low MMIO
between TOLUD and 4 GB.

Setting TOLUD to 3 GB gives the required range for Low MMIO and makes the
maximum amount of Physical Address Range below 4 GB available to access DRAM.

To make use of the remaining DRAM Address Space (3 GB to 8 GB), the Physical
Address Space range 4 GB to 9 GB will automatically be mapped downwards by 1 GB
(subtract 4 GB and add TOLUD) to 3 GB to 8 GB in DRAM Address Space before the
request make it to the memory controller. This mapping happens for all DRAM request
from CPUs or devices.

TOUUD would be set to 9 GB and the full remaining Physical Address Space range from
9 GB to 512 GB is available for HIGH MMIO.

2.3 System Management Mode (SMM)

System Management Mode uses main memory for System Management RAM (SMM
RAM). System Management RAM space provides a memory area that is available for
the SMI handlers and code and data storage. This memory resource is normally hidden
from the system OS so that the processor has immediate access to this memory space
upon entry to SMM.

2.3.1 IAFW Programming Restrictions

If any of the following conditions are violated the results of SMM accesses are
unpredictable and may cause the system to hang:
• The upper bound of the SMM region is controlled by BGSM. The lower bound is
controlled by TSEGMB.
• IAFW should program the upper and lower bounds with the upper > lower and
ensuring that the address space must not overlap address space assigned to
system DRAM, or to any MMIO range. This is an IAFW responsibility.
• The SMM region must not be reported to the OS as available DRAM. This is an IAFW
responsibility.
• Any address translated through the GMADR TLB must not target the SMM Range.
• IAFW should initially leave the SMM region open to allow writing of SMM code in
DRAM.
• Must setup the SMMR register in each CPU to prevent cache based attacks.
• The System Management Mode Range Register (SMRR) is an enhancement to the
IA-32 Intel architecture that constrains SMM cache-ability controls to SMM code.
• After the microcode update has been loaded and during the SMM relocation phase
of the POST, IAFW must detect if the processor supports SMRR by examining the
SMRR_CAP bit (IA32_MTRR_CAP[11]). If the SMRR_CAP bit is set (‘1’) the
processor supports the SMRR feature. If the SMRR_CAP bit is clear (‘0’) the
processor does not support the SMRR feature. If the SMRR is supported, it must be
enabled by setting bit 3 in the IA32_FEATURE_CONTROL MSR[3] (MSR 3Ah)
together with the lock bit (bit 0) of the same MSR. In addition, It must set the
SMRR_PHYS_BASE and SMRR_PHYS_MASK to match the BUNIT.BSMMRRL/
BUNIT.BSMMRRH defined region.

26 Intel Top Secret 334818

 • South Cluster devices are never allowed to access SMM space. ABIMR must be
used for this.

See the BIOS Writer’s Guide for more details.

2.3.2 SoC Internal Enforcement of SMM Protection

Note: SoC will automatically filter CPU request from threads that are not in SMM mode that
hit the SMM range. Writes will be dropped and reads will return all ‘1’s.

Note: Access to the SMM area of physical address space from agents other than the CPU
should be prevented. It is the responsibility of IAFW to use a SMM policy registers for
this functionality.

2.3.2.1 CPU WB Transaction to an Enabled SMM Address Space

CPU Writeback transactions to enabled SMM Address Space must be written to the
associated SMM DRAM even though BUNIT.BSMMRRL/BUNIT.BSMMRRH
[ALLOW_NON_SMM_WRITES_TO_SMM_SPACE_SMMWRITESOPEN] = 0 and the
transaction is not performed in SMM mode. This ensures SMM space cache coherency
when cacheable extended SMM space is used. It is the responsibility of IAFW to ensure
that the SMM physical address range is not exposed to the operating system or used for
any other function.

IAFW must also program the SMRR register in the CPU(s) to prevent a cache based
security risk.

2.4 I/O Space

The SoC implements a 64 KB + 3 B I/O address space. The I/O Space is accessed by
the CPU using the IN/OUT instructions. This address space is separate from both the
Host Memory Address Space described in Section 2.1, "Host Memory Address Space"
and the PCI config space described in Section 2.1, "Host Memory Address Space".
These requests never map to system DRAM. These requests are always NP and the CPU
waits for a completion before proceeding to the next instruction.

The CPU micro-code is responsible for ensuring that I/O transactions issued on IDI do
not cross a 4 B boundary. When an instruction would results in an un-aligned I/O
transaction micro-code will issue two I/O transactions. When an instruction targets the
upper three bytes of the 64 KB I/O space (FFFDh-FFFFh) and the transaction is split,
the second half of the transaction will access some or all of the “+ 3” bytes of I/O space
(1_0000h to 1_00002h). For example a 4 B read to FFFEh results in a 2 B transaction
to FFFEh, and a 2 B transaction to 1_0000h.

Note: There are no actual resources located at 1_0000 to 1_0003.

Note: Funny I/O is treated as a separate address space. Eight byte Funny I/O transactions
are allowed but micro-code will ensure they are always naturally aligned.

Some root complex integrated PCI devices have I/O space BARs that can be configured
to claim memory within this region. Root Ports (PCIe or Mobile Express) have Base and
limit range registers that can be configured to claim I/O addresses within this region.
IAFW and the OS ensure that the PCI BARs are not programmed to overlap with any of
the legacy address ranges.

334818 Intel Top Secret 27

2.4.1 Fixed I/O Ranges: Decode and Routing
These Fixed address ranges are either positively decoded in the System Agent or
subtractively routed to the Primary to Sideband Bridge (P2SB).

The following table defines the Fixed I/O address ranges that are positively decoded in
the system agent. If any of these ranges are not enabled, a transaction to that range
will subtractively decode to the P2SB.

The System Agent must shadow a copy of several LPC registers (IOE and IOD). Only
one of LPC registers will be enabled at a time and they always have the same device
and function number (specifically device 31, function 0).

The B-Unit implements the GCS register.

Table 2-33. Fixed I/O Address Map Positive Decode

IOSF Primary
I/O Address Register control
Target

080h LPC or PCIe GCS.RPR = 1

084h–086h LPC or PCIe GCS.RPR = 1

088h LPC or PCIe GCS.RPR = 1

08Ch–08Eh LPC or PCIe GCS.RPR = 1

200h–207h LPC IOE.LGE = 1

208h–20Fh LPC IOE.HGE = 1

220h–227h LPC ((IOE.CAE & IOD.CA) = 3’b010) OR ((IOE.CBE & IOD.CB) = 03’b10)

228h–22Fh LPC ((IOE.CAE & IOD.CA) = 3’b011) OR ((IOE.CBE & IOD.CB) = 3’b011)

238h–23Fh LPC (9IOE.CAE & IOD.CA) = 3’b100) OR (IOE.CBE & IOD.CB = 3’b100)

278h–27Fh LPC (IOE.PPE & IOD.LPT) = 2’b01

2E8h–2EFh LPC ((IOE.CAE & IOD.CA) = 3’b101) OR ((IOE.CBE & IOD.CB) = 3’b101)

2F8h–2FFh LPC ((IOE.CAE & IOD.CA) = 3’b001) OR ((IOE.CBE & IOD.CB) = 3’b001)

338h–33Fh LPC ((IOE.CAE & IOD.CA) = 3’b110) OR ((IOE.CBE & IOD.CB) = 3’b110)

370h–375h LPC (IOE.FDE & IOD.FDD) = 1

377h LPC (IOE.FDE & IOD.FDD) = 1

378h–37Fh LPC (IOE.PPE & IOD.LPT) = 2’b00

3BCh–3BEh LPC (IOE.PPE & IOD.LPT) = 2’b10

3E8h–3EFh LPC ((IOE.CAE & IOD.CA) = 3’b111) OR ((IOE.CBE & IOD.CB) = 3’b111)

3F0h–3F5h LPC (IOE.FDE & IOD.FDD) = 0

3F7h–3F7h LPC (IOE.FDE & IOD.FDD) = 0

3F8h–3FFh LPC ((IOE.CAE & IOD.CA) = 3’b000) OR ((IOE.CBE & IOD.CB) = 3’b000)

4D0h–4D1h LPC N/A

678h–67Fh LPC (IOE.PPE & IOD.LPT) = 2’b01

778h–77Fh LPC (IOE.PPE & IOD.LPT) = 2’b00

7BCh–7BEh LPC (IOE.PPE & IOD.LPT) = 2’b10

28 Intel Top Secret 334818

 The following table defines the Fixed I/O address ranges that are subtractively routed
to the P2SB. Transactions that reach the P2SB are either terminated or forwarded on
IOSF SB to the final destination. A hard strap informs the P2SB if LPC is enabled.

Table 2-34. Fixed I/O Address Map Subtractive Decode (Sheet 1 of 2)

IOSF Primary
I/O Address IOSF SB Target
Target

000h–01Fh P2SB Terminate

020h–021h P2SB ITSS (interrupt)

024h–025h P2SB ITSS (interrupt)

028h–029h P2SB ITSS (interrupt)

02Ch–02Dh P2SB ITSS (interrupt)

02Eh–02Fh P2SB LPC

030h–031h P2SB ITSS (interrupt)

034h–035h P2SB ITSS (interrupt)

038h–039h P2SB ITSS (interrupt)

03Ch–03Dh P2SB ITSS (interrupt)

040h P2SB ITSS (Timer 0 Register)

041h P2SB Terminate

042h P2SB ITSS (Timer 2 Register)

043h P2SB ITSS (Timer Control Word Register)

04Eh–04Fh LPC LPC

050h P2SB ITSS (alias of 040h)

051h P2SB Terminate

052h P2SB ITSS (alias of 042h)

053h P2SB ITSS (alias of 043h)

060h P2SB LPC

061h P2SB ITSS (CPU I/F)

062h P2SB LPC

063h P2SB ITSS (CPU I/F)

064h P2SB LPC

065h P2SB ITSS (CPU I/F)

066h P2SB LPC

067h P2SB ITSS (CPU I/F)

070h P2SB ITSS (CPU I/F), RTC, PMC

071h P2SB RTC, PMC

072h–073h P2SB RTC, PMC

073h P2SB RTC, PMC

074h P2SB RTC, PMC

075h P2SB RTC, PMC

076h–077h P2SB RTC, PMC

080h P2SB LPC or PMC

081h–083h P2SB Terminate

084h–086h P2SB LPC or PMC

334818 Intel Top Secret 29

Table 2-34. Fixed I/O Address Map Subtractive Decode (Sheet 2 of 2)
IOSF Primary
I/O Address IOSF SB Target
Target

087h P2SB Terminate

088h P2SB LPC or PMC

089h–08Bh P2SB Terminate

08Ch–08Eh P2SB LPC or PMC

08Fh P2SB Terminate

090h P2SB LPC

091h P2SB Terminate

092h P2SB ITSS (CPU I/F)

093h P2SB Terminate

094h–096h P2SB LPC or PMC

097h P2SB Terminate

098h P2SB LPC or PMC

099h–09Bh P2SB Terminate

09Ch–09Eh P2SB LPC or PMC

09Fh P2SB Terminate

0A0h–0A1h P2SB ITSS (interrupt)

0A4h–0A5h P2SB ITSS (interrupt)

0A8h–0A9h P2SB ITSS (interrupt)

0ACh–0ADh P2SB ITSS (interrupt)

0B0h–0B1h P2SB ITSS (interrupt)

0B2h–0B3h P2SB PMC

0B4h–0B5h P2SB ITSS (interrupt)

0B8h–0B9h P2SB ITSS (interrupt)

0BCh–0BDh P2SB ITSS (interrupt)

0C0h–0DFh P2SB Terminate

0F0h P2SB Terminate

170h–177h P2SB Terminate

1F0h–1F7h P2SB Terminate

376h P2SB Terminate

3F6h P2SB Terminate

4D0h–4D1h P2SB ITSS (interrupt)

CF9h P2SB ITSS (CPU I/F)

2.4.2 Variable I/O Ranges: Decode and Routing

Several PCI functions have I/O BARs (See Table 2-39, Funny I/O Address Ranges and
Routing). The PCIe root ports have I/O Base and Limit ranges. Address decode for the
standard PCI bars and bridge Base/Limit registers occurs in the IOSF fabric, except for
VC0a agents on PSF0.

30 Intel Top Secret 334818

 The Following table lists all of the non-standard legacy variable I/O address ranges
along with the agent they target. These ranges are source decoded in the System
Agent.

Table 2-35. Legacy Variable I/O Address Map

Range Name Size (Bytes) Target Enable Bar

LPC Generic 1 4 to 256 LPC LGIR1[0] LGIR1

LPC Generic 2 4 to 256 LPC LGIR2[0] LGIR2

LPC Generic 3 4 to 256 LPC LGIR3[0] LGIR3

LPC Generic 4 4 to 256 LPC LGIR4[0] LGIR4

2.4.2.1 Integrated Graphics Device (IGD)

Note: the IGD BARs are not restricted to Low MMIO space and could be programmed in High
MMIO space.

Note: The Integrated graphics device has two Host Memory Space BARs. These are standard
PCI BARs.
• Address decode to the IGD I/O BARs are valid if the Integrated Graphics device is
enabled and system software has enabled the I/O Access to the device:
• IGDEnabled:
(0.0.0.PCI.DEVEN.D2F0EN = 1)
AND (0.2.0.PCI.PMCSR.PSRSTAT = 2’b00)
AND (0.2.0.PCI.PCICMD2.IOE = 1)

Table 2-36. Display IOBAR

Name GTTMMADR

Range BAR: 0.2.0.PCI.IOBAR (8 B)

From IDI IF (IGDEnabled)

Display
ELSE
PSF1

From IOSF I/OA-Unit

Security No Restrictions.

2.5 PCI Config Space

PCI Config space is used to access both PCI devices inside the SoC and PCI/PCIe
devices outside the SoC connected to the PCIe hierarchy. This space is only accessible
from the CPU. Software has two mechanisms for accessing this space: (1) standard
CF8/CFC “I/O” ports; (2) PCI Enhanced Configuration. The CPU traps CF8/CFC accesses
in uCode and converts them to Funny I/O transactions. PCI Enhanced Configuration
accesses appear within the Extended Configuration range as defined by the PCIEXBAR
register. The system agent converts both of these types of transactions into IOSF
transactions that target the PCI config space.

334818 Intel Top Secret 31

 All SoC internal devices are on PCI bus #0. The list of all integrated PCI functions is in
section Section 2.8, "PCI Devices". For more information on the PCI configuration space
refer to the PCI 3.0 specification and the PCIe 3.0 specification.

2.5.1 Configuration Mechanisms

The CPU is the originator of configuration cycles. The configuration cycles will be
translated to PCI Config cycles before being sent on PSF fabric to configure different
PCI devices or a transaction on IOSF-SB fabric to update the register.

Note: All configuration registers are expected to be mapped on IOSF-SB fabric.

2.5.1.1 Standard PCI Configuration Mechanism

The following is the mechanism for software to generate configuration cycles using a
Address/Data pair in I/O space: CF8h (CONFIG_ADDRESS) and CFCh (CONFIG_DATA).

A 4 B (DW) I/O write cycle places a value into CONFIG_ADDRESS that specifies the PCI
bus, the Device on that bus, the Function within the Device, and a offset to the
configuration register of the Function being accessed. CONFIG_ADDRESS[31] must be
‘1’ to enable a configuration cycle. CONFIG_DATA then becomes a window into the four
bytes of configuration space specified by the contents of CONFIG_ADDRESS. Any read
or write to CONFIG_DATA will result in a Funny I/O transaction that is converted by the
system agent into a PCI configuration transaction.

Note: This mechanism is limited to accessing the first 256 B of configuration space.

The format of the address is as follows:

Table 2-37. PCI Config PORT CF8 Mapping

I/O CF8h
IDI Funny I/O bit
Field CONFIG_ADDRESS IOSF CMD Header Bits
location
Bits

Bus Number 23:16 27:20 Byte 8 [7:0]

Device Number 15:11 19:15 Byte 9 [7:3]

Function Number 10:08 14:12 Byte 9 [2:0]

Register Number 07:02 07:02 Byte 11 [7:2]

Bit 31 of offset CF8h must be set for a configuration cycle to be generated.

2.5.1.2 PCI Express Enhanced Configuration Mechanism

PCI Express extends the configuration space to 4096 B per device/function as
compared to 256 B allowed by PCI Specification Revision 3.0. PCI Express configuration
space is divided into a PCI 3.0 compatible region, which consists of the first 256 B of a
logical device’s configuration space and a PCI Express extended region which consists
of the remaining configuration space.

The PCI-compatible region can be accessed using either the Standard PCI Configuration
Mechanism or using the PCI Express Enhanced Configuration Mechanism described in
this section. The extended configuration registers may only be accessed using the PCI
Express Enhanced Configuration Mechanism. To maintain compatibility with PCI
configuration addressing mechanisms, system software must access the extended

32 Intel Top Secret 334818

 configuration space using 32 b data operations (32 b aligned) only. These 32 b
operations include byte enables allowing only appropriate bytes within the DWORD to
be accessed. Locked transactions to the PCI Express memory mapped configuration
address space are not supported. All changes made using either access mechanism are
equivalent.

The PCI Express Enhanced Configuration Mechanism utilizes a flat memory-mapped

address space to access device configuration registers. This address space is reported
by the system firmware to the operating system.

The PCI Express Configuration Transaction Header includes an additional 4 b

(ExtendedRegisterAddress[3:0]) between the Function Number and Register Address
fields to provide indexing into the 4 KB of configuration space allocated to each
potential device. For PCI Compatible Configuration Requests, the Extended Register
Address field must be all ‘0’s.

Figure 2-3. Memory Map to PCI Express Device Configuration Space

0xFFFFFFF 0xFFFFF 0x7FFF 0xFFF

Bus 255 Device 31 Function 7

PCI Express
Extended
Conf iguration
Space

0xFF
0x1FFFFF 0xFFFF 0x1FFF PCI Compatible
Conf iguration
Bus 1 Device 1 Function 1 Space
0x3F
0xFFFFF 0x7FFF 0xFFF PCI Compatible
Bus 0 Device 0 Function 0 Conf iguration
Space Header
0
Located by
PCI Express Base
Address

Just the same as with PCI devices, each device is selected based on decoded address
information that is provided as a part of the address portion of Configuration Request
packets. A PCI Express device will decode all address information fields (bus, device,
function and extended address numbers) to provide access to the correct register.

A flat 256 MB Host Memory Address Space window into Enhanced Configuration Space
is defined using the BUNIT.PCIEXBAR. This registers contains a 12 b base address
which is compared against bits 39:28 of the incoming memory address. If these 12 b
match the cycle is turned into a configuration cycle with the following fields:

Table 2-38. PCI Config Memory Bar Mapping

Host Memory IDI Memory Cycle
Field IOSF CMD Header Bits
Space address Bit location

Bus Number [7:0] 27:20 27:20 Byte 8 [7:0]

Device Number [4:0] 19:15 19:15 Byte 9 [7:3]

Function Number [2:0] 14:12 14:12 Byte 9 [2:0]

Register Number [9:0] 11:2 11:2 Reg[9:6]  Byte 10 [3:0]

Reg[5:0]  Byte 11 [7:2]

334818 Intel Top Secret 33

 To access this space (steps 1, 2, and 3 are done only once by IAFW),
1. Use the PCI compatible configuration mechanism to enable the PCI Express
enhanced configuration mechanism by writing ‘1’ to bit 0 of BUNIT.PCIEXBAR
registers.
2. Use the PCI compatible configuration mechanism to write an appropriate PCI
Express base address into BUNIT.PCIEXBAR registers
3. Calculate the host address of the register you wish to set using

host address=( PCI Express base

+ (1 MB× bus number)
+ (32 KB× device number)
+ (4 KB× function number)
+ (1 B× offset within the function))
4. Use a memory write or memory read cycle to the calculated host address to write
or read that register.

2.5.1.3 Type 0/Type 1 Configuration

If the Bus Number is zero, the SoC will generate a Type 0 Configuration Cycle on IOSF.
If the Bus Number is non-zero, the SoC will generate a Type 1 Configuration Cycle on
IOSF.

2.5.2 ACPI Mode

Some devices/functions are not intended to be enumerated/configurable by the OS—
they consume memory space, but this is not under the control of the OS. This may be
for security reasons, if there is no driver for the function, or if the function is specifically
for IAFW. For normal PCI functions, the PSF implements a PCI Configuration Object,
which is the set of PCI Config registers that it shadows so that it can perform fabric
decode and routing of transactions. For ACPI functions, the PSF implements either a
Hybrid or Fixed ACPI Configuration Object. A summary is given below.

2.5.2.1 Hybrid ACPI Configuration Object

Each Hybrid ACPI configuration object has a config header disable bit associated with it.
When this bit is set the PCI configuration object becomes a hybrid ACPI configuration
object. The PSF fabric stops routing PCI configuration cycles to the associated function,
and stops updating the shadow registers of the configuration object. The hybrid ACPI
shadow registers will be compared to for Fabric decode. The configuration object
remains accessible and updateable via IOSF SB.
To use a device as an ACPI device, IAFW would first configure the device and then set
the cfgDis bit. IAFW then informs the OS via the ACPI tables about the system
resources (e.g. memory range) that have been assigned to the function.
Functions that are switchable between host and CSE root spaces use hybrid ACPI
objects to allow their configuration space to be hidden while set to CSE root space, for
security.

34 Intel Top Secret 334818

2.5.2.2 Fixed ACPI Configuration Object

A Fixed (or Native) ACPI configuration object has the same structure as a PCI
configuration object, except almost all the values are set as compile-time constants.
The funDis, barDis, and ROMbarDis bits are the only control fields implemented, to
disable the function or BARs. The BAR and other PCI configuration settings are
immutable.
Native ACPI objects are used for security (no configuration cycles accepted) and for
completion routing-by-ID without BARs (also known as a ghost BDF).

2.5.2.3 IOSF2OCP Bridge ACPI Mode

The IOSF2OCP Bridge allows the PCI functions that it implements to be put into an
ACPI mode. In this mode of operation, PCI config accesses to the function return a UR
completion. A control bit in the private configuration space
(PCICFGCTRL[{1 to 32}].PCI_CFG_DIS) disables PCI configuration accesses in the
Bridge. The values programmed in the PCI Configuration registers are still valid. The
Bridge uses these registers (for example BAR, MSE, D3, and BME) to determine how to
handle memory accesses.
An additional BAR1 register is present in the PCI configuration space of the Bridge, for
each function, specifically to provide access to the PCI Config registers when the
function is in ACPI mode. Memory accesses to BAR1 access the PCI configuration space
of the corresponding function; that is BAR1 is an alias to the PCI configuration space.
The address decode for BAR1 ignores the MSE and D3 device states in the PCI
configuration space.

Note: MMIO transaction are posted and PCI configuration accesses are non-posted. A read
must always be performed following BAR1 access to ensure the Bridge observes the
BAR1 write access. Only 4 B (1 DW) BAR1 downstream accesses are supported. BAR1
memory accesses, which fall outside the standard PCI configuration registers, are
treated as accesses to reserved registers.

Refer to the latest version of the IOSF2OCP Bridge EAD for further details.

2.6 Funny I/O Space

Both uCode and the IGD can issue transactions on IDI targeting the Funny I/O space.
Any I/O transaction with an address beyond 64 KB + 3 is a Funny I/O transaction.

The IGD uses Funny I/O to communicate internally between the GT logic on IDI and the
Display logic on IOSF. In addition there is a 32 KB window within the GT Funny I/O
range that aliases to MCHBAR providing read only access for GT to MCHBAR registers.
(Read only access is enforced by SAI checks in the B-Unit).

2.6.1 RAVDMs
GT to CSE VDM flow is as follows:
1. GT issues Funny I/O transaction
2. B-Unit routes to A-Unit
3. A-Unit converts to RAVDM and sends to PSF1 for decode
4. PSF1 routes by ID to CSE

334818 Intel Top Secret 35

 5. VDM "Target ID" should use the HECI1 B/D/F

GT will target the PAVP VDM range of the GTTMMADR. GT will only send posted RAVDM
writes with RSP = 0 for the PAVP flow. GT RAVDMs that are writes are forwarded to
CSE. Reads to the PAVP region get routed normally to display.

There are no display fi CSE RAVDMs.

2.6.2 FunnyIO Address Ranges

Table 2-39, Funny I/O Address Ranges and Routing below provides the address ranges
and how they are routed in the system.

Table 2-39. Funny I/O Address Ranges and Routing

Range Usage Routing

0x2000_0000 to 0x2013_FFFF GT Funny I/O Route to Display: NOTE writes to 0x2012_8000

to 0x2012_FFFFh are routed to display as
RAVDMs.

0x2014_0000 to 0x2014_7FFF GT Funny I/O: MCH BAR alias (Read Route to C-unit
only)

0x2014_8000 to 0x201F_FFFF GT Funny I/O Route to Display

0x4000_0000 to 0x40FF_FFFF CR access Route to C-unit

0x8000_0000 to 0x8FFF_FFFF PCI Config Space access Convert to IOSF CFG transaction in SA and
route by B/D/F

0xFED0_0000 to 0xFEDF_FFFF LT Doorbells IDI to SA to IDI—doesn’t travel to A-Unit

2.7 IOSF-SB Private CR Space

IOSF-SB message space is used to access registers mapped on IOSF-SB. These
registers include uncore CRs, and chipset specific registers. The Private CR space is
accessed on IOSF SB using the CRRd and CRWr opcodes. Each Destination ID can have
up to 48 b of Byte addressable private register space.

An uncore CR is a configuration register that is accessible either by uCode or by IA code

through the MSR read/write instruction. Uncore CRs are accessed through Funny I/O
and mapped onto IOSF SB in the C-unit.

Chipset specific registers are accessed through a memory BAR in the P2S Bridge
function. Many I/O controllers and most of the Analog PHYs contain Chipset specific
registers for IAFW configuration. Historically these were mapped behind the PCH
“RCBA” or Root Complex Base Address register.

Access to IOSF-SB by the Host or System Agent is possible over PSF via the Primary to
Sideband Bridge (P2SB). P2SB will forward properly formatted register access requests
as CRRd and CRWr requests via IOSF-SB. The P2SB also provides a mask that can be
used to restrict access to certain endpoints.

P2SB offers two access methods for Primary to Sideband message generation:
• Sideband register access via MMIO (SBREG_BAR interface); limited to 16-bit
addressing
• Sideband Message Interface (required for 48 b addressing beyond 64 KB)

36 Intel Top Secret 334818

 PSF CR space can be accessed using the simpler MMIO BAR interface. A single MRd64/
MWr64 to the P2SB BAR causes a CRRd/Wr message to be sent via IOSF-SB.

Table 2-40. P2SB MMIO Register Interface

Addr[63:24] Addr[23:16] Addr[15:2] Addr[1:0]

BAR Target Port ID Register offset 2’b00

As seen in Table 2-40, P2SB MMIO Register Interface, the memory address contains the
BAR, destination port ID, and register offset. Using MMIO, all Sideband messages sent
are non-posted and will back pressure on PSF. Writes are pipelined; whereas reads are
serialized.

The Funny I/O access mechanism and the MMIO access mechanism both provide paths
to the same registers on IOSF SB. However, Uncore CRs and MSRs must be protected
from access by un-privileged code. SAI enforcement at the target is used for this.

2.8 PCI Devices

The PCI Configuration Matrix tables (linked) provide the Device and Function number
assignment for all internal devices. In addition it specifies the number and size of the
BARs for each Function. Address decoding for devices 0 (function 0 only), 2, and 3 are
performed by B-Unit. All other device functions are address decoded by PSF.

Note: Functions that are implemented in an IOSF2OCP Bridge have a 4 KB 64 b BAR1 that
aliases to PCI Config space for the corresponding function. This is to provide access to
the PCI Config registers when the function is in ACPI mode. Refer to the latest version
of the IOSF2OCP Bridge EAD for details.

2.9 System Memory Protection

The SoC security mechanism is designed to provide access control for data stored in
DRAM. Security checks happen in the Host Memory Address Space, but only for request
on the way to DRAM rather than devices/MMIO.

It is important for both security and coherency checking that there are no aliasing
cases in either Host Memory Address Space or System DRAM Address Space for
request targeting DRAM. This means that SoC must not allow accesses to two different
addresses to retrieve data from the same location in DRAM.

To ensure no aliasing, certain rules must be followed.

2.9.1 PMR-L and PMR-H

Bunit will implement PMR protection for the default VTd engine.
Display (and GT) will implement PMR protection for the Gfx VTd engine:
• GT has a copy of GfxVTd PMR. It will make sure that only VT-d walks are allowed to
touch PMR and hence get onto IDI. Other transactions that hit PMR are killed before
they get onto IDI.

334818 Intel Top Secret 37

 • Display will add GfxVTd PMR. It will make sure that only VTd walks are allowed to
go to PMR range and all other transactions will be killed before they get onto IOSF
primary.

Software is required to program PMR_def and PMR_gfx as the same but they may be
different during the initial setup period.

2.9.2 B-Unit Isolated Memory Regions (IMRs)

Isolated memory regions provide a mechanism to add SAI checks to certain regions of
memory.

38 Intel Top Secret 334818

3 CSE Root Space

3.1 CSE Memory Address Space

The SoC implements a 64 b CSE Memory Address space. Internal to the CSE the
minute IA subsystem uses a 32 b physical address. At the CSE Gasket a set of
programmable Address Translation Tables (ATT) allow the CSE minute IA and internal
DMA engines to access the full 64 b CSE Memory space of the SoC. This section
describes the address space and routing outside of the CSE.

Some portion of the CSE Memory Address Space references System DRAM. IMR regions
are used to divide the DRAM between the Host Memory Space and the CSE Memory
Space.

VT-d does not apply in the CSE Memory Address space.

CSE Memory Address Space Decode and Routing

Transactions that originate inside the CSE are positively decoded against several
possible ranges in the IOSF fabric. The downstream subtractive decode path from the
CSE leads to System DRAM.

Transactions that originate outside of the CSE in the CSE root space are positively
decoded against several possible ranges in the IOSF fabric. The upstream subtractive
decode path from agents outside the CSE leads to the CSE. Transactions from devices
outside the CSE that access System DRAM in the CSE Memory Address Space are
considered Peer to Peer transactions and must be positively decoded.

3.1.1 SoC System Agent Decode and Routing

Any transaction in the CSE root space that arrives at the A-Unit and does not positively
decode to a Peer target will be forwarded to the B-Unit. Within the B-Unit the Address
is checked against the IMRs and stolen memory ranges (TSEG SMM and Graphics
Stolen Memory). If the IMRs allow access the transaction is converted to a System
DRAM Address Space and sent to DRAM. Otherwise the transaction is aborted.

IMRs in the system agent are applied to both Host Memory address space and CSE
Memory Address space. Depending on how the IMRs are programmed the Host Memory
Space and the CSE Memory Space may be completely non-overlapping, or there may
be IMR regions that create an alias where both Host Memory Space and CSE Memory
Space reference the same System DRAM Address.

3.1.2 Abort Handling

The term abort is used in this document to handle a few different error handling
mechanisms.

334818 Intel Top Secret 39

3.1.2.1 B-Unit Abort Handling
Non-posted Transactions that are aborted in the B-Unit will have a completion returned
to the originator with bogus data. Posted transactions that are aborted in the B-Unit are
dropped without altering the contents of system memory. Depending on the reason for
the abort, the B-Unit will follow different error logging behaviors.

3.1.2.2 IOSF Abort Handling

Transactions routed to IOSF will either positively decode or be routed to the B-Unit.
There are no cases where the IOSF fabric will abort a CSE memory space transaction.

The IOSF fabric will perform error handling for CSE space configuration cycles.

3.1.3 Fixed Positive Decode Ranges

The following table defines the fixed address ranges in the CSE Memory Address Space.
The IOSF fabric is configured to route these ranges to the correct destination.

IOSF target Range Notes

PMC (Shared SRAM) 0x8000_0000_FF06_C000 to Writes and reads to this range.

0x8000_0000_FF06_FFFF

LPSS (secure I/O) 0x8000_0000_FF00_6000 to Writes and reads to this range.

0x8000_0000_FF00_6FFF

LPSS (secure I/O) 0x8000_0000_FF00_7000 to Writes and reads to this range.

0x8000_0000_FF00_7FFF

3.1.4 Programmable Positive Decode Ranges

3.1.4.1 Dedicated PCI Functions.
A PCI function that is always present in the CSE root space is a dedicated function.
There are two dedicated functions in the SoC: Audio and the SPI controller. The CSE
Programs the BARs of the dedicated function using PCI configuration cycles.

3.1.4.2 Switchable PCI Functions.

Several of the PCI functions in the SoC are configurable to be in either the Host Root
Space or the CSE Root Space. These functions are never in both spaces at the same
time. These functions include the USB-Device controller, the PMC, the 15 functions in
the LPSS, and the four functions in the SCS.

When the device is switched into the CSE Root Space, the CSE programs the BARs of
the device to set the address range the device will respond to in the CSE Memory
Address Space.

Switchable functions will have the same Device and Function number in both CSE Root
Space and the Host Root Space.

40 Intel Top Secret 334818

3.1.4.3 DRAM as Peer Address Ranges
To enable routing of transactions from outside the CSE to System DRAM the IOSF fabric
implements a hybrid ACPI configuration object. This is a set of registers inside the IOSF
fabric that match the definition of a standard PCI type0 header. They are programmed
over IOSF SB by the CSE. The BARs must be programmed by the system to route
transactions to the IMR regions that are accessed in the CSE root space by peer agents.

To simplify IMR region sizing in the fabric, two large 256 MB sized BARs are created in
one hybrid ACPI object associated with ISH in PSF3. The actual IMRs will be assigned
by CSE within the 256 MB BAR region (or 512 MB if combined). Upstream requests to
the IMRs will be within the region covered by the BARs.

The following is the list of peer agents that require access to System DRAM in the CSE
root space. The decode mode, either address (italicized to differentiate) or source, is
listed for requests and completions. Address decoding is provided by the IOSF fabric
and indicated by italics, whereas source decoding is provided by either B-Unit or the IP.
• I-Unit — Requests: source decode, Completions: source decode
• Audio — Requests: source decode, Completions: address decode
• ISH — Requests: address decode, Completions: address decode
• PMC — Requests: address decode, Completions: address decode

The IMR completions are routed back downstream to the requester by ID (BDF). A
hybrid ACPI object in the IOSF fabric is associated with Audio, PMC, and ISH to route
completions. Note that the ISH hybrid ACPI object serves dual purpose by providing the
IMR region BARs and the ISH BDF for ISH IMR completions.

3.2 System DRAM Address Space

The physical CSE Memory Address is converted to a System DRAM address in the exact
same way as a Host Memory Address.

3.3 I/O Space

There are no resources mapped into I/O Space in the CSE root space outside of the
CSE.

3.4 PCI Config Space

The CSE only accesses root complex integrated functions. By convention devices 0 to 8
will be inside the CSE itself, and devices 9 to 31 are available for use outside of the
CSE. All CSE functions are on PCI bus #0.

It is possible for the CSE subsystem to generate type1 configuration transactions onto
the IOSF fabric. There is no use case for this in the SoC, but it could occur. These will
subtractively decode to the A-Unit and should be properly aborted.

It is possible for the CSE subsystem to generate Type 0 configuration transactions onto
the IOSF fabric that will not positively decode. There is no use case for this in the SoC,
bit it could occur. These will subtractively decode to the A-Unit and should be properly
aborted.

334818 Intel Top Secret 41

3.5 IOSF-SB Private CR Space
The CSE can access IOSF-SB Private CR space from an SB ATT window in the Gasket.
The IOSF-SB Private CR space is the same in CSE root space and Host root space. SAI
protections are used where necessary to restrict access.

3.6 PCI Devices

The following PCI Devices are always available in the CSE root space.

Please note that some unnecessary device address resources exist in the PSF
configuration because removal was not possible with schedule constraints. Specifically,
PSF SPI defines an extra 16 MB BAR for Huffman decompression, which will not be used
and doesn’t affect the address map.

PCI Configuration Matrix:

Table 3-1. PCI Configuration Matrix: (Snapshot effective 10/12/2014 12:38 PM) (Sheet
1 of 2)
Logical Function PSF Agent Type DID Device Function

SoC Base device ID 5A80

Host Bridge C-unit PCI 0x5AF0 0 0

DPTF (Camarillo) C-unit PCI 0x5A8C 0 1

GMM GMM PCI 0x5A90 0 3

Gen Display PCI 0x5A84 2 0

Iunit Iunit PCIe 0x5A88 3 0

Reserved (CSE) CSE 7 0

P2SB P2SB PCI 0x5A92 13 0

PMC PMC ACPI 0x5A94 13 1

SPI SPI ACPI 0x5A96 13 2

Shared SRAM PMC ACPI 0x5AEC 13 3

Audio Audio PCIe 0x5A98 14 0

CSE-HECI1 CSE PCI 0x5A9A 15 0

CSE-HECI2 CSE PCI 0x5A9C 15 1

CSE-HECI3 CSE PCI 0x5A9E 15 2

CSE-fTPM (PSF ghost) CSE ACPI 15 7

CSE-HOFFL HOFFL PCI 0x5AA0 16 0

ISH ISH PCI 0x5AA2 17 0

SATA SATA SATA 0x5AE0 18 0

PCIe-A 0 PCIe-A PCIe 0x5AD8 19 0

PCIe-A 1 PCIe-A PCIe 0x5AD9 19 1

PCIe-A 2 PCIe-A PCIe 0x5ADA 19 2

PCIe-A 3 PCIe-A PCIe 0x5ADB 19 3

PCIe-B 0 PCIe-B PCIe 0x5AD6 20 0

PCIe-B 1 PCIe-B PCIe 0x5AD7 20 1

42 Intel Top Secret 334818

Table 3-1. PCI Configuration Matrix: (Snapshot effective 10/12/2014 12:38 PM) (Sheet
2 of 2)
Logical Function PSF Agent Type DID Device Function

USB-Host (xHCI) USB-H PCI 0x5AA8 21 0

USB-Device (xDCI) USB-D PCI 0x5AAA 21 1

I2C 0 LPSS PCI 0x5AAC 22 0

I2C 1 LPSS PCI 0x5AAE 22 1

I2C 2 LPSS PCI 0x5AB0 22 2

I2C 3 LPSS PCI 0x5AB2 22 3

I2C 6 LPSS PCI 0x5AB8 23 2

I2C 7 LPSS PCI 0x5ABA 23 3

UART 0 LPSS PCI 0x5ABC 24 0

UART 1 LPSS PCI 0x5ABE 24 1

UART 2 LPSS PCI 0x5AC0 24 2

UART 3 LPSS PCI 0x5AEE 24 3

SPI 0 LPSS PCI 0x5AC2 25 0

SPI 1 LPSS PCI 0x5AC4 25 1

SPI 2 LPSS PCI 0x5AC6 25 2

PWM PMC PCI 0x5AC8 26 0

SD Card SCS PCI 0x5ACA 27 0

eMMC SCS PCI 0x5ACC 28 0

UFS SCS PCI 0x5ACE 29 0

SDIO SCS PCI 0x5AD0 30 0

LPC LPC PCI 0x5AE8 31 0

SMBUS SMBUS PCI 0x5AD4 31 1

For the switchable PCI devices refer Section 2.8, "PCI Devices" for device/function
assignments and BAR information. The following PCI devices are switchable: USB-
Device, I2C0 to I2C7, UART0 to UART2, SPI0 to SPI2, SD Card, eMMC, UFS, and SDIO.

§§

334818 Intel Top Secret 43

44 Intel Top Secret 334818
4 Register Access Methods

There are five common register access methods :

• I/O-Space Register Access Methods
1.Fixed I/O Register Access (both Regular I/O and Funny I/O accesses)
2.Variable I/O (I/O-Referenced) Register Access
3.PCI Configuration Register Access (Indirect—via Memory or I/O Registers)
• Memory-Space (Memory Mapped I/O, MMIO) Register Access Methods
4.Fixed Memory-Mapped Register Access
5.Variable Memory (Memory-Referenced) Register Access
For details on the address ranges supported by these register access methods, see the
Address Map chapter.

Note: MCHBAR MMIO space has been adopted to replace the Message Bus Register Access
functionality provided in previous devices. This change has been made to improve
convergence between client and SoC devices as well as to resolve outstanding issues
relating to interrupts, security, and VT-d support.

4.1 I/O-Space Register Access Methods

4.1.1 Fixed I/O Register Access
Fixed I/O registers are accessed by specifying their address in a PORT IN or PORT OUT
transaction from the CPU core. This allows direct manipulation of the registers. Fixed I/
O registers are unmovable register in I/O space. There are two categories of Fixed I/
O registers:

Regular I/O registers—registers whose addresses fit within 16 b (0x0000 to 0xFFFF)

Funny I/O registers—registers whose addresses are above 2^16 + 3 (0x10004 and up)

Regular I/O registers are visible to all agents capable of making I/O accesses; Funny I/
O registers are limited to Goldmont IA core uCode and the GEN9 Display (IGD) for
internal communications within the SoC. See for more details on Funny I/O accesses
and address map.

Table 4-1. Fixed I/O Register Access Method Example (P80 Register)
Type: I/O Register P80: 80h
(Size: 32 b)

Note: Funny I/O register accesses may be 64 b.

4.1.2 Variable I/O (I/O-Referenced) Register Access

Variable I/O (I/O-referenced) registers use programmable base address registers
(BARs) to select the base I/O address for a range of I/O addresses. The I/O BARs act
as pointers to blocks of actual I/O registers; other than the variable starting address for

Intel Top Secret 43

 Variable I/O registers, accessing these registers is the same as for Fixed I/O registers.
To access an I/O-referenced register for a specific I/O base address, start with that
base address and add the register’s offset. Example pseudo code for an I/O-referenced
register read is as follows:

Register_Snapshot= IOREAD([IO_BAR] + Register_Offset)

Base-address registers are often located in the PCI configuration space and are
programmable by the BIOS/OS. Other base-address register types may include fixed
memory registers, fixed I/O registers or message-bus registers.

Table 4-2. Referenced I/O Register Access Method Example (HSTS Register)
Type: I/O Register HSTS: [_IOBAR] + 0h
(Size: 8 b) _IOBAR Type: PCI Configuration Register (Size: 32 b)
_IOBAR Reference: [B:0, D:31, F:3] + 20h

4.1.3 PCI Configuration Register Access

Access to PCI configuration space registers is performed through one of two different
configuration access methods (CAMs):
• I/O-indexed—PCI CAM
• Memory-mapped—PCI Enhanced CAM (ECAM)

Each PCI function has a standard PCI header consisting of 256 B for the I/O-access
scheme (CAM), or 4096 B for the enhanced memory-access method (ECAM). Invalid
read accesses return binary strings with all bits set to ‘1’.

Table 4-3. PCI Register Access Method Example (VID Register)

Type: PCI Configuration Register VID: [B:0, D:31, F:3] + 0h
(Size: 16 b)

4.1.3.1 PCI Configuration Access—CAM: I/O Indexed Scheme

Accesses to configuration space using the I/O method relies on two 32 b I/O registers:
• CONFIG_ADDRESS—I/O Port CF8h
• CONFIG_DATA—I/O Port CFCh

These two registers are both 32 b registers in I/O space. Using this indirect access
mode, software uses CONFIG_ADDRESS (CF8h) as an index register, indicating which
configuration-space register to access, and CONFIG_DATA (CFCh) acts as a window to
the register pointed to in CONFIG_ADDRESS. Accesses to CONFIG_ADDRESS (CF8h)
are internally captured. Upon a read or write access to CONFIG_DATA (CFCh),
configuration cycles will be generated to the PCI function specified by the address
captured in CONFIG_ADDRESS. The format of the address is shown in Table 4-1, Fixed
I/O Register Access Method Example (P80 Register).

Table 4-4. PCI CONFIG_ADDRESS Register (I/O PORT CF8h) Mapping

Field CONFIG_ADDRESS Bits
Enable PCI Configuration Space Mapping 31

Reserved 30:24

Bus Number 23:16

Device Number 15:11

44 Intel Top Secret

Table 4-4. PCI CONFIG_ADDRESS Register (I/O PORT CF8h) Mapping
Field CONFIG_ADDRESS Bits
Function Number 10:08

Register/Offset Number 07:02

Note: Bit 31 of CONFIG_ADDRESS must be set for a configuration cycle to be generated.

Pseudo code for a PCI register read is as follows:

Register_Snapshot= MEMREAD([Mem_BAR] + Register_Offset)

MyCfgAddr[23:16]= bus

MyCfgAddr[15:11]= device

MyCfgAddr[10:8]= funct

MyCfgAddr[7:2]= dWordMask(offset)

MyCfgAddr[31]= 1

IOWRITE(0xCF8, MyCfgAddr)

Register_Snapshot= IOREAD(0xCFC)

4.1.3.2 PCI Configuration Access—ECAM: Memory Mapped Scheme

A flat, 256 MB memory space may also be allocated to perform configuration
transactions. This is enabled through the BUNIT.BECREG message bus register
(Port: 3h, Register: 27h) found in the SoC Transaction Router. BUNIT.BECREG allows
remapping this 256 MB region anywhere in physical memory space. Memory accesses
within the programmed MMIO range result in configuration cycles to the appropriate
PCI devices specified by the memory address as shown in Table 4-4, PCI
CONFIG_ADDRESS Register (I/O PORT CF8h) Mapping.

ECAM Memory Address Field ECAM Memory Address Bits

Use from BAR: BUNIT.BECREG[31:28] 31:28

Bus Number 27:20

Device Number 19:15

Function Number 14:12

Register Number 11:02

ECAM Memory Address Field ECAM Memory Address Bits

Use from BAR: BUNIT.BECREG[31:28] 31:28

Bus Number 27:20

Device Number 19:15

Function Number 14:12

Register Number 11:02

Note: ECAM accesses are only possible when BUNIT.BECREG.ECENABLE (bit 0) is set.

Pseudo code for an enhanced PCI configuration register read is as follows:

MyCfgAddr[27:20]= bus

Intel Top Secret 45

 MyCfgAddr[19:15]= device

MyCfgAddr[14:12]= funct

MyCfgAddr[11:2]= dw_offset

MyCfgAddr[31:28]= BECREG[31:28]

Register_Snapshot= MEMREAD(MyCfgAddr)

4.2 Memory-Space Register Access Methods

4.2.1 Fixed Memory-Mapped Register Access
Fixed Memory-Mapped I/O (MMIO) registers are accessed by specifying their 32 b/39 b
address in a memory transaction from the CPU core. This allows direct manipulation of
the registers. Fixed MMIO registers are unmovable registers in memory space.

Table 4-5. Fixed Memory-Mapped Register Access Method Example (IDX Register)
Type: Memory-Mapped I/O Register IDX: FEC00000h
(Size: 32 b)

4.2.2 Variable Memory (Memory-Referenced) Register Access

The SoC uses programmable base address registers (BARs) to set a range of physical
address (memory) locations that it will use to decode memory reads and writes from
the CPU to directly access a register. These BARs act as pointers to blocks of actual
memory-mapped I/O (MMIO) registers. To access a memory-referenced register for a
specific base address, start with that base address and add the register’s offset.
Example pseudo code for a read is shown below:

Register_Snapshot= MEMREAD([Mem_BAR] + Register_Offset)

Base-address registers are often located in the PCI configuration space and are
programmable by the BIOS/OS. Other common base address register types include
fixed memory registers and I/O registers that point to MMIO register blocks.

Table 4-6. Memory-Mapped Register Access Method Example (_MBAR Register)

Type: Memory-Mapped I/O Register _MBAR Type: PCI Configuration Register (Size: 32 b)
(Size: 8 b) _MBAR Reference: [B:0, D:31, F:3] + 10h

4.3 Apollo Lake SoC IOSF-SB Bus Access

Apollo Lake SoC contains a Message Network called IOSF Sideband (IOSF-SB, SB, or
sideband) as an internal communication medium for simple, low bandwidth, sideband
communication. Host software (IA FW) can access the message network via
configuration registers in device 13 to access private (i.e. non host-mapped) registers
and to initiate messages (for example, interrupts, or power management events).

Access to this network by the CPU is needed for only a handful of SoC operations
including but not limited to:

• Configuring system DRAM and Uncore Units.

46 Intel Top Secret

 • Setting CPU configuration and causing a CPU-Only reset.

• SoC Performance Monitoring (PMON).

• Thermal management setup.

• Display IO and PLL configuration.

• GPIO configuration.

Note: Some SoC registers are ONLY accessible to software via this method.

4.3.1 IOSF-SB Register Addressability

Access to the message bus space is through the SoC Transaction Router’s PCI
configuration registers. This unit relies on three 32-bit PCI configuration registers to
generate messages:

IOSF-SB MMIO ADDR: PCI[B:0,D:13,F:0] | 0x10

4.3.2 IOSF-SB Access Mechanisms

Table 4-7. P2SB MMIO Register Interface

Addr[63:24] Addr[23:16] Addr[15:2] Addr[1:0]

BAR Target Port ID Register offset 2’b00

4.4 Register Field Access Types

Access Type Comments

RO Read-Only

RO/C Read-Only Clear on Read, loaded by HW

RO/Strap Read-Only Strap

RO/V Read-Only Variable

RO/V/P Read-Only Variable Sticky

RW Read-Write

RW/L Read-Write Lock

RW/1C Read-Write 1 to Clear (set by hardware, cleared by FW)

RW/1C/HC Read-Write 1 to Clear with Hardware Clear (set by hardware, cleared by FW or HW)

RW/1C/HC/L Read-Write 1 to Clear with Hardware clear Lock

RW/1C/L Read-Write 1 to Clear Lock

RW/1C/P Read-Write 1 to Clear Sticky (set by hardware, cleared by FW)

RW/1C/P/L Read-Write 1 to Clear Sticky Lock

RW/1S Read-Write 1 to Set, cannot be cleared

RW/1S/HC Read-Write 1 to Set with Hardware clear (set by FW, cleared by HW)

Intel Top Secret 47

 Access Type Comments

RW/1S/HC/L Read-Write 1 to Set with Hardware Clear, Lock

RW/1S/1C/HC Read-Write 1 to Set, write 1 to clear with hardware clear

RW/1S/1C/HC/L Read-Write 1 to Set, write 1 to clear with hardware clear, Lock

RW/HC Read-Write with Hardware Clear

RW/O Read-Write Once

RW/O/L Read-Write Once Lock

RW/O/P Read-Write Once Sticky

RW/P Read-Write Sticky

RW/P/L Read-Write Sticky Lock

RW/P/Strap Read-Write Sticky Strap

RW/Strap Read-Write Strap

RW/V Read-Write Variable

RW/V/L Read-Write Variable Lock

WO Write-Only

WO/L Write-Only Lock

Table 4-8. Access Type Explanations

Base Access Type Description

RO Read Only: Writes to this register do not affect the register value. Reads return either a constant or
variable device state.

RW Read Write: Writes to this register setting alter the register value with the value written. Reads return
the value of the register.

WO Write Only: Writes to this register alters the register value. Original—Reads always return 0; revised—
RTL will read reset, Saola mask read value, later Saola may change to check

Table 4-9. Attributes/Modifiers are Applied to Base Access Types to Describe HW

Interaction or Other Details
Applicable
Attribute Base Access Description
Type

/C RO Clear on Read: A read to the register will clear on a read to the register. Implies that HW modifies
the register value.

/V RO, RW Variable: The read status is variable (not constant), and if the register is writable, reads do not
return the write value, but return values that are dependant on other device or component state
or other registers.

/P RO, RW PWROK: Reset only by loss of power (!PWROK). Also referred to as Sticky. The actual PWROK
signal that is used as a reset depends on the power well the register is implemented in.

/L RW, WO Lock: Prior to the Lock bit being set (in a separate register), writes to the register load the
register with the value written. Reads return the value of the register. This register is not writable
once the lock bit is set. Reads to a locked register return the contents of the register. The Lock
Bit itself typically has a /L attribute modifier and in some (rare) cases the Lock Bit could also
have a /P modifier.

/1C RW Read Write 1 to Clear: Register that is set to ‘1’ by hardware, and cleared to ‘0’ by software
writing a ‘1’ to the register. Software writes of 0 have no effect.

48 Intel Top Secret

Table 4-9. Attributes/Modifiers are Applied to Base Access Types to Describe HW
Interaction or Other Details
/1S RW Read Write 1 to Set: Register that is set to ‘1’ by software writing a ‘1’ to the register. Software
writes to 0 have no effect.

/HC RW Hardware Clear: Register that is cleared to ‘0’ by hardware.

/O RW Write Once: This register may be written to any value once. After that, the register is Read Only.

Base
Attribute HW Access SW Access Other
Access

Type

RO none readable, constant value

RO /C loadable readable, cleared on a read

RO /V loadable readable

RO /V/P loadable readable reset by PWROK

RW none readable

writeable

RW /1C settable readable intended to be single-bit field

writeable (1 to clear, 0 has no effect)

RW /1C/HC settable readable intended to be single-bit field

clearable writeable (1 to clear, 0 has no effect)

RW /1C/HC/L settable readable intended to be single-bit field

clearable writeable when not locked (1 to clear,

0 has no effect)

RW /1C/L settable readable intended to be single-bit field

writeable when not locked (1 to clear,

0 has no effect)

RW /1C/P settable readable intended to be single-bit field

writeable (1 to clear, 0 has no effect) reset by PWROK

RW /1C/P/L settable readable intended to be single-bit field

writeable when not locked (1 to clear, reset by PWROK

0 has no effect)

RW /1S none readable intended to be single-bit field

writeable (1 to set, 0 has no effect)

RW /1S/1C/HC settable readable intended to be single-bit field

clearable writeable (1 to toggle, 0 has no effect)

RW /1S/1C/HC/L settable readable intended to be single-bit field

clearable writeable when not locked (1 to toggle,

0 has no effect)

RW /1S/HC clearable readable intended to be single-bit field

writeable (1 to set, 0 has no effect)

RW /1S/HC/L clearable readable intended to be single-bit field

writeable when not locked (1 to set,

0 has no effect)

Intel Top Secret 49

 Base
Attribute HW Access SW Access Other
Access

RW /L none readable

writeable when not locked

RW /O none readable

writeable once (any value)

RW /O/L none readable

writeable once when not locked (any

value)

RW /O/P none readable reset by PWROK

writeable once when not locked (any

value)

RW /P none readable reset by PWROK

writeable

RW /V loadable readable

writeable

RW /V/L loadable readable For /V/L, Saola will have to behave the
same as /V and will not lock since the
value cannot be predicted

writeable when not locked

WO none reads return 0

writeable

WO /L none reads return 0

writeable when not locked

4.5 Alternate Access Mode

Although not a specific I/O register access mode, the ITSS implements a special
Alternate Access mode to enable saving write-only (WO) registers during the state-
save process. In this mode, subsequent reads to a fixed I/O register returns all of the
ITSS WO-register values in sequence during state save; these values can then be
written back to the appropriate registers during state restore.

§§

50 Intel Top Secret

MCHBAR

5 MCHBAR

5.1 Registers Summary

Table 5-1. Summary of pcs_regs_wrapper Registers
Offset Offset
Register Name (ID)—Offset Default Value
Start End

Noncached Region Control

6000h 6007h 0h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6008h 600Fh C0061210202h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6010h 6017h C0061210202h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6018h 601Fh C0061010202h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6020h 6027h 80000C0063210217h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6028h 602Fh C00610C0212h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6030h 6037h 40001000202h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6038h 603Fh FFFFFFFFFFFFFFFFh
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6040h 6047h 40001000202h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6050h 6057h C0061210202h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6058h 605Fh 80000C0063210217h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6060h 6067h C00612C0212h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6070h 6077h 40001200202h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6078h 607Fh FFFFFFFFFFFFFFFFh
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6080h 6087h 40001200202h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6C80h 6C87h 0h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6C88h 6C8Fh 0h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

Noncached Region Control

6B60h 0h
(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h

5.1.1 Noncached Region Control

(B_CR_BNOCACHECTL_0_0_0_MCHBAR)—Offset 6B60h
Access Method

334818 51
 MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

Bit Default &

Field Name (ID): Description
Range Access

31:1 0h RESERVED_0 (Reserved): Reserved.

RO

0:0 0h ENABLE_NO_SNOOP (Enable No Snoop): When set, B-Unit compares bits 35:20
RW incoming addresses to Upper and Lower NoSnoop Bounds to see if the transaction
should be prevented from issuing a processor snoop operation.

5.2 Registers Summary

Table 5-2. Summary of pcs_regs_wrapper Registers
Offset Offset Default
Register Name (ID)—Offset
Start End Value

1000h 1003h DRAM Rank Population 0 (D_CR_DRP0)—Offset 1000h 10000000h

1008h 100Bh DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1008h 210702CBh

100Ch 100Fh DRAM Timing Register 1A (D_CR_DTR1A)—Offset 100Ch 30481218h

1010h 1013h DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1010h 8C080C30h

1014h 1017h DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1014h 3002EA28h

1018h 101Bh DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1018h 30209149h

101Ch 101Fh DRAM Timing Register 5A (D_CR_DTR5A)—Offset 101Ch 304200C2h

1020h 1023h DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1020h 20100000h

1024h 1027h DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1024h D060C06h

1028h 102Bh DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1028h CC50A18h

102Ch 102Fh D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 102Ch 0h

1030h 1033h D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1030h 0h

1034h 1037h D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1034h 10000028h

1038h 103Bh DRAM Refresh Control (D_CR_DRFC)—Offset 1038h 1750h

103Ch 103Fh D-Unit Scheduler (D_CR_DSCH)—Offset 103Ch 3901C08h

1040h 1043h DRAM Calibration Control (D_CR_DCAL)—Offset 1040h 1057h

1044h 1047h VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 104Ch 20000h

104Ch 104Fh VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 104Ch 0h

Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset

1050h 1053h 6C000008h
1050h

1054h 1057h TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1054h 0h

1058h 105Bh Data Scrambler (D_CR_SCRAMCTRL)—Offset 10A4h 0h

10A4h 10A7h Data Scrambler (D_CR_SCRAMCTRL)—Offset 10A4h 0h

10ACh 10AFh Error Injection Address Register (D_CR_ERR_INJ)—Offset 10ACh 0h

10B0h 10B3h Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 10B0h 0h

10B4h 10B7h Error Log Register (D_CR_ERR_ECC_LOG)—Offset 10B4h 0h

10BCh 10BFh D-Unit Status (D_CR_DFUSESTAT)—Offset 10BCh 0h

52 334818
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Table 5-2. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset Default
Register Name (ID)—Offset
Start End Value

1124h 1127h Major Mode Control (D_CR_MMC)—Offset 1124h 2B01E518h

Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset

1128h 112Bh 1F207C8h
1128h

Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—

112Ch 112Fh 1F207C8h
Offset 112Ch

1130h 1133h Access Class Initial Priority (D_CR_ACCIP)—Offset 1130h 17C2h

Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset

1134h 1137h 1F52940h
1134h

Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset

1138h 113Bh 14000000h
1138h

Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset

113Ch 113Fh 0h
113Ch

Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset

1140h 1143h 1F29400h
1140h

Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset

1144h 1147h 1F5294Ah
1144h

1148h 114Bh Deadline Threshold (D_CR_DL_THRS)—Offset 1148h 6h

114Ch 114Fh Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 114Ch 1800h

1154h 1157h DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1154h 0h

1180h 1183h DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1180h 0h

1184h 1187h MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1184h 0h

5.2.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1000h

Rank configuration register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10000000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DRAMDEVICE_PR

BLMODE

DWID
CASWIZZLE
ADDRDEC

DRAMTYPE

RSVD3
RSVD18_16

DDMEN
BAHEN

RSVD13_9

DDEN

RKEN1
RKEN0
ECCEN

RSIEN

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Bit Default &

Field Name (ID): Description
Range Access

DRAM Device Per Rank (DRAMDEVICE_PR): Specifies the number of DRAM

devices that are ganged together to form a single rank.
• 00: 1 DRAM device in each rank.
0h • 01: 2 DRAM devices in each rank.
31:30
RW
• 10: 4 DRAM devices in each rank.
• 11: 8 DRAM devices in each rank.
Note: The actual number of devices is one more than the value programmed when
ECC is enabled.

Address Decode (ADDRDEC): Specifies the address mapping to be used:

• 00: 1KB (A).
1h
29:28 • 01: 2KB (B).
RW
• 10: 4KB (C).
• 11: Reserved.
Burst Length Mode (BLMODE):
• 000: Fixed BL8.
• 001: Onthefly BL8.

0h
• 010: Fixed BL16.
27:25
RW • 011: Onthefly BL16.
• 100: Fixed BL32.
• 101: Onthefly BL32.
• 110-111: Reserved.
DRAM Type (DRAMTYPE):
• 000: DDR3L.
• 001: LPDDR3.
0h • 010: LPDDR4.
24:22
RW
• 011: Reserved.
• 100: Reserved.
• 101-111: Reserved.

ECC Enable (ECCEN):

• 0: ECC is disabled.
0h
21
RW • 1: ECC is enabled.
This bit determines if the D-Unit treats the PMI BE_ECC bits as ECC bits or Byte
Enables. This should only be used in configurations that support ECC (DDR3L).

CA Swizzle Type (CASWIZZLE):

• 00: uniDIMM/SODIMM.
0h
20:19 • 01: BGA.
RW
• 10: BGA mirrored (LPDDR3 Only).
• 11: UDIMM (DDR3L Only).

18:16
0h Reserved (RSVD18_16): Reserved.
RO

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Bit Default &

Field Name (ID): Description
Range Access

Bank Address Hashing Enable (BAHEN): See Address Mapping section for full
description.
0h
15 • 0: Bank Address Hashing disabled.
RW
• 1: Bank Address Hashing enabled.
Rank Select Interleave Enable (RSIEN): See Address Mapping section for full
description.
0h
14 • 0: Rank Select Interleaving disabled.
RW
• 1: Rank Select Interleaving enabled.

13:9
0h Reserved (RSVD13_9): Reserved.
RO

DRAM Device Density (DDEN): Density of the DRAM devices populated on Ranks 0
and 1.
• 000: 4 Gb.
• 001: 6 Gb.
0h • 010: 8 Gb.
8:6
RW
• 011: 12 Gb.
• 100: 16 Gb.
• 101-111: Reserved.
Note: For LPDDR4 this value is the die density.

DRAM Device Data Width (DWID): Data width of the DRAM device populated on
Ranks 0 and 1.
• 00: x8.
0h
5:4 • 01: x16.
RW
• 10: x32.
• 11: x64.

3
0h Reserved (RSVD3): Reserved.
RO

Dual Data Mode Enable (DDMEN):

• 0: PMI Dual Data Mode is disabled in D-Unit, full cacheline
0h
2 read and writes go through a single D-Unit.
RW
• 1: PMI Dual Data Mode is enabled, only half cacheline read/
writes go through a single D-Unit.
0h Rank Enable 1 (RKEN1): Enable Rank 1: Must be set to 1 to
1
RW enable use of this rank.
Rank Enable 0 (RKEN0): Enable Rank 0: Must be set to 1 to
0h
0 enable use of this rank.
RW
Note: Setting this bit to 0 is not a functional mode.

5.2.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1008h

Specifies DRAM timing parameters.

Access Method

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Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 210702CBh

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 1
TCKCKEH

TXSDLL

TXSR

TRPPB
TRCD
Bit Default &
Field Name (ID): Description
Range Access

Valid Clocks Before CKE High [tCKCKEH/tCSCKEH/tCKSRX] (TCKCKEH):

Number of valid clocks before CKE high (in DRAM clocks).
• LPDDR4: The value in this register covers both tCKCKEH and
tCSCKEH.
• DDR3L/LPDDR3: The value covers tCKSRX which is defined as
the number of valid DRAM clocks that have to toggle before
10h
31:25 the issuing of the Self Refresh Exit SRX. This value is also used
RW
if the clock frequency is changed or the clock is stopped or
tristated during Power Down i.e. the number valid DRAM
clocks that have to toggle before the issuing of the Power
Down Exit PDX command.
tCKCKEH can be used to compensate for clock stabilization delays in the
motherboard. Note: D-unit hardware enforces minimum of two SPID clock before
CKEH, any value in this register is the additional time.

Exit Self-Refresh to Valid Commands Requiring a Locked

DLL Delay [tXSDLL] (TXSDLL): D-Unit waits max(tXSR+tZQCL/
tZQCS, tXSDLL) before allowing traffic to DRAM (in 64 x DRAM
8h Clocks).
24:21
RW LPDDR3/LPDDR4: tXSDLL = 0.
DDR3L: tXSDLL = tDLLK = 512 Clocks = 8 x 64 DRAM Clocks.
Note: In the equation above, tZQCL/tZQCS = 0 if no ZQ is
performed on SR exit.
Exit Self-Refresh to Valid Command Delay [tXS/tXSR]
(TXSR): DDR3L: tXS - Delay between Self Refresh Exit SRX to
70h
20:12 any DRAM Command not requiring DLL Lock.
RW
LPDDR/: tXSR - Delay between Self Refresh Exit SRX to any DRAM
Command. (in DRAM clocks).
Activate RAS to CAS Command Delay [tRCD] (TRCD):
Specifies the delay between a DRAM Activate command and a
Bh
11:6 DRAM Read or Write command to the same bank (in DRAM
RW
clocks).
Note: Derating adds 1.875ns to this timing.

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Bit Default &

Field Name (ID): Description
Range Access

Precharge to Activate Command Delay of a Single Bank

[tRPpb] (TRPPB): Specifies the delay between a DRAM
Precharge command and a DRAM Activate command to the same
Bh
5:0 bank (in DRAM Clocks).
RW
Note : this CR should be constrained to a minimum of 4 in LPDDR3
and minimum of 8 in LPDDR4.
Note: Derating adds 1.875ns to this timing.

5.2.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 100Ch

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 30481218h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0
RSVD26

TZQCL

TZQLAT
TZQCS
TXP

Bit Default &

Field Name (ID): Description
Range Access

Exit Power Down to Next Command Delay [tXP] (TXP):

Specifies the delay from the DRAM Power Down Exit (PDX)
6h
31:27 command to any valid command (in DRAM clocks).
RW
Note: The value in this field must be programmed to tXPDLL when
Slow Exit Mode Power-down is enabled for DDR3L.

26
0h Reserved (RSVD26): Reserved.
RO

ZQ (long) Calibration Time [tZQCL/tZQCAL] (TZQCL):

• LPDDR3/DDR3L: tZQCL/tZQoper: Specifies the delay between
the DRAM ZQ Calibration Long (ZQCL) command and any
DRAM command during normal operation.
120h
25:14 • LPDDR4: tZQCAL: ZQ Calibration time (in DRAM clocks).
RW
Note: This field defines the ZQ Calibration Long delay during normal operation. It is
not the same as tZQinit which uses the same ZQCL command but the delay is longer.
tZQinit applies only during poweron initialization of the DRAM devices and tZQoper
applies during normal operation. BIOS executes the DRAM initialization sequence so
it has to ensure tZQinit is met and not the D-Unit.

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Bit Default &

Field Name (ID): Description
Range Access

ZQ Short Calibration Time [tZQCS] (TZQCS): ZQCS to any

DRAM Command Delay: Specifies the delay between the DRAM ZQ
48h Calibration Short (ZQCS) command and any DRAM command (in
13:6
RW DRAM clocks).
DDR3L and LPDDR3 only. LPDDR4 does not support ZQCS
command
ZQ Latch Time [tZQLAT] (TZQLAT): Specifies the delay
18h between the DRAM ZQ Calibration Latch command and any DRAM
5:0
RW command (in DRAM clocks).
LPDDR4 only.Not used in DDR3L/LPDDR3/.

5.2.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1010h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 8C080C30h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0
TCKE
RSVD22_21

RSVD16

NREFI
NRFCAB

Bit Default &

Field Name (ID): Description
Range Access

All Bank Refresh Cycle Time [tRFCab] (NRFCAB): Specifies

118h
31:23 the delay between the REFab command to the next valid
RW
command. (in DRAM clocks)

22:21
0h Reserved (RSVD22_21): Reserved.
RO

4h CKE Minimum Pulse Width [tCKE] (TCKE): Specifies the

20:17
RW minimum time from CKEL to CKEH (in DRAM clocks).

16
0h Reserved (RSVD16): Reserved.
RO

Refresh Interval Time [tREFI] (NREFI): Specifies the average

C30h time between refresh commands. JEDEC Base Refresh Interval
15:0
RW time (in DRAM clocks).
Note: D-Unit will ignore the 2 LSBs of this field.

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5.2.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1014h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 3002EA28h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 1 0 1 0 0 0
TRTP

TCCD_INC

TWTP

TCWL

TWMWSB
TCMD
Bit Default &
Field Name (ID): Description
Range Access

Read to Precharge Delay [tRDPRE] (TRTP): Specifies the minimum delay

between the DRAM Read and Precharge commands to the same bank (in DRAM
clocks).
6h
31:27 • LPDDR3 Equation: = BL/2 + tRTP - 4.
RW
• LPDDR4 Equation: = BL/2 + Max (8, tRTP) - 8.
• DDR3L Equation: = tRTP.
CAS to CAS Command Delay Adder (TCCD_INC): Specifies
0h the number of clocks to be added to turnaround times (for Stretch
26:20
RW Mode). It increases delay between Read to Read or Read to Write
commands (in 4 x DRAM clocks).
Write to Precharge Command Delay [tWRPRE] (TWTP): Specifies the minimum
delay between the DRAM Write command and the Precharge command to the same
17h bank (in DRAM clocks).
19:13
RW • LPDDR3/LPDDR4 Equation: tWTP = BL/2 + WL + tWR + 1.
• DDR3L Equation: tWTP = BL/2 + CWL + tWR.
DRAM Command Valid Duration (TCMD): Specifies the number of DRAM clocks a
command is held valid on the DRAM Address and Control buses. 1N is the DDR3 basic
requirement. 2N is the extended mode for board signal integrity.
• 0h: Reserved.
1h
12:11
RW • 1h: 1 DRAM Clock (1N).
• 2h: 2 DRAM Clocks (2N).
• 3h: Reserved.
Note: DDR3L only. tCMD must be set to 1N for LPDDR3/LPDDR4.

Write Latency [WL/CWL] (TCWL): The delay between the

8h
10:6 internal write command and the availability of the first word of
RW
DRAM input data (in DRAM clocks).

334818 59
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Bit Default &

Field Name (ID): Description
Range Access

Write CAS to Masked Write CAS Delay Same Bank (TWMWSB): Specifies the
minimum delay between DRAM Write command to Masked Write command to same
bank (in DRAM clocks).
28h
5:0 • LPDDR4 Equation: tWMWSB = tCCDMW (BL16) or tCCDMW +
RW
8 (BL32).
Note: Masked Write operation in LPDDR4 is always BL16. D-Unit applies this timing
for same rank as well as same bank.

5.2.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1018h

Specifies DRAM timings parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 30209149h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1
TFAW

TWRDR

TRWDR

TWWDR

TRRDR
Bit Default &
Field Name (ID): Description
Range Access

Four Bank Activate Window [tFAW] (TFAW): A rolling

30h timeframe in which a maximum of four Activate commands can be
31:24
RW issued to the same rank. This is to limit the peak current draw
from the DRAM devices (in DRAM clocks).
Write to Read DQ Delay Different Ranks (TWRDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Read data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tWRDR = WL + tDQSSmax + BL/2 +
tWPST - (RL + tDQSCKmin - tRPRE).
8h
23:18
RW • LPDDR4 Equation: tWRDR = WL - RL + BL/2 + 4 -
tDQSCKmin.
• DDR3L Equation: tWRDR = CWL + tDQSSmax + BL/2 +
tWPST - (CL + tDQSCKmin - tRPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.

60 334818
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Bit Default &

Field Name (ID): Description
Range Access

Read to Write DQ Delay Different Ranks (TRWDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Write data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tRWDR = RL + tDQSCKmax + BL/2 +
tRPST - (WL + tDQSSmin - tWPRE).
9h
17:12 • LPDDR4 Equation: tRWDR = RL + tDQSCKmax + BL/2 - (WL -
RW
2).
• DDR3L Equation: tRWDR = CL + tDQSCKmax + BL/2 + tRPST
- (CWL + tDQSSmin - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be adjusted by tODTon.
Note: For DDR3L using ODT, this latency may need to be increased by one clock.

Write to Write DQ Delay Different Ranks (TWWDR): Specifies the delay from
the start of a Write data burst of one rank to the start of a Write data burst of a
different rank (in DRAM clocks).
• LPDDR3 Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin
5h + tWPRE.
11:6
RW
• LPDDR4 Equation: tWWDR = BL/2 + 4 - tDQSSmin.
• DDR3L Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin +
tWPRE.
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.

Read to Read DQ Delay Different Ranks (TRRDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Read data burst of a different
rank (in DRAM clocks).

5:0
9h • LPDDR3/4 Equation: tRRDR = BL/2 + tDQSCKmax -
RW tDQSCKmin + tRPRE.
• DDR3L Equation: tRRDR = BL/2 + tRPST + tDQSCKmax -
tDQSCKmin + tRPRE + 1.

5.2.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 101Ch

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 304200C2h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0
TDERATE_INC
RSVD26

TWWSR

TRRSR

TWRSR

TRWSR
TRRD

334818 61
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Bit Default &

Field Name (ID): Description
Range Access

Row Activation to Row Activation Delay [tRRD] (TRRD):

Specifies the minimum delay in DRAM clocks between two DRAM
6h
31:27 Activate commands to the same rank but different banks (tRC is
RW
the minimum delay between activations of the same bank).
Note: Derating adds 1.875ns to this timing.

26
0h Reserved (RSVD26): Reserved.
RO

Derate Increment (TDERATE_INC): Specifies the additional

delay that is added to DRAM timing when indicated by MR4 status.
0h (in DRAM clocks)
25:23
RW LPDDR3/LPDDR4: Value is 1.875ns.
Note: The value in this register is only added to these timing
parameters: tRCD, tRAS, tRP and tRRD.
Write to Write DQ Delay Same Rank (TWWSR): Specifies the
10h delay from a DRAM Write to another Write command of the same
22:18
RW rank (in DRAM clocks).
LPDDR3/LPDDR4/DDR3L Equation: tRRSR = tCCD.
Read to Read DQ Delay Same Rank (TRRSR): Specifies the
10h delay from a DRAM Read to another Read command of the same
17:13
RW rank (in DRAM clocks).
LPDDR3/LPDDR4/DDR3L Equation: tRRSR = tCCD.
Write to Read DQ Delay Same Rank (TWRSR): Specifies the delay from a DRAM
Read to Write command of the same rank (in DRAM clocks).

3h • LPDDR3/LPDDR4 Equation: tWRSR = WL + tDQSSmax + BL/2

12:6 + tWTR.
RW
• DDR3L Equation: tWRSR = CWL + tDQSSmax + BL/2 +
tWPST + tWTR.
Read to Write DQ Delay Same Rank (TRWSR): Specifies the delay from a DRAM
Read to a Write command of the same rank (in DRAM clocks).
• LPDDR3/LPDDR4 Equation: tRWSR = RL + tDQSCKmax + BL/
2h 2 - WL + tWPRE.
5:0
RW
• DDR3L Equation: tRWSR = CL + tDQSCKmax + BL/2 + tRPST
- (CWL +tDQSSmin - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Note: For DDR3L using ODT, this latency may need to be increased by one clock.

5.2.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1020h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 20100000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

62 334818
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0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD7
OREFDLY

TCKCKEL

MNTDLY

TPSTMRRBLK

TPREMRBLK
Bit Default &
Field Name (ID): Description
Range Access

20h Opportunistic Refresh Idle Timer (OREFDLY): Rank idle

31:24
RW period that defines an opportunity for refresh (in DRAM clocks).
Valid Clocks After CKE Low [tCKELCK/tCKELCS/tCPDED/tCKSRE]
(TCKCKEL): Specifies the amount of time that DRAM clocks need to toggle after CKE
goes low (in DRAM Clocks).
• For /LPDDR3, this covers tCPDED.
2h
23:19
RW • For LPDDR4, this covers both tCKELCK and tCKELCS.
• For DDR3L, this is tCKSRE.
Note: D-Unit hardware enforces minimum of one SPID clocks after CKEL, any value in
this register is the additional time.

Maintenance Operation Delay (MNTDLY): When a critical read

request is pending in RPQ and a maintenance operation (MRR,
0h ZQCal, Ref, etc, panic refresh is an exception to this delay.) needs
18:15
RW to be performed, D-Unit waits this amount of time before
performing the maintenance operation to allow for some high
priority requests to be issued (in 4x SPID clocks).
Mode Register Read to Any Command Delay
(TPSTMRRBLK): Specifies the quiet time after issuing MRR
command (in DRAM Clocks).
0h
14:8 Note: D-Unit treats MRR as a read and always applies relevant
RW
turnaround times, any value programmed in this CR must be
greater than those turnaround times for D-Unit to enforce any
additional time from MRR to the next read/write.

7
0h Reserved (RSVD7): Reserved.
RO

Any Command to Mode Register Read/Write Delay

(TPREMRBLK): Specifies the quiet time before issuing MRR/MRW
command. (in DRAM clocks).
0h
6:0 Note: D-Unit treats MRR as a read and always applies relevant
RW
turnaround times, any value programmed in this CR must be
greater than those turnaround times for D-Unit to enforce any
additional time from previous read/writes.

5.2.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1024h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

334818 63
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Default: D060C06h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0

TWRPDEN

TRDPDEN
TRPAB

RSVD8_7
TPSTMRWBLK

TRAS
Bit Default &
Field Name (ID): Description
Range Access

All Bank Precharge to Activate Command Delay [tRPab] (TRPAB): Specifies

the delay between a DRAM Precharge All Bank command and a DRAM Activate
command (in DRAM Clocks). Note: This CR should be constrained to a minimum of 4
3h in LP3 and minimum of 8 in LP4. Note: Derating adds 1.875ns to this timing.
31:26
RW
• For LPDDR, tRPpb = tRP, tRPab = tRP + 3ns.
• For DDR3L 8ch tRPpb = tRPab = tRP.
Mode Register Write to any Command Delay [tMRD/tMRW]
2h (TPSTMRWBLK): Specifies the quiet time after issuing MRW
25:23
RW command (in 8 x DRAM clocks).
Note: This time covers for both tMRD and tMRW.
Write Command to Power Down Delay [tWRPDEN]
6h (TWRPDEN): Specifies the minimum time between a write
22:16
RW command to PowerDown command (in DRAM clocks).
Must be at least equal to tWR + tCCD + tWL + 2.
Read Command to Power Down Delay [tRDPDEN]
6h (TRDPDEN): Specifies the minimum time between a read
15:9
RW command to PowerDown command (in DRAM clocks).
Must be at least equal to CL/RL + tDQSCKmax + tCCD + tRPST.

8:7
0h Reserved (RSVD8_7): Reserved.
RO

Row Activation Period [tRAS] (TRAS): Specifies the minimum

6h delay between the DRAM Activate and Precharge commands to
6:0
RW the same bank (in DRAM clocks).
Note: Derating adds 1.875ns to this timing.

5.2.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1028h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: CC50A18h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

64 334818
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0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0

TCKESR

LPMDTOCKEDLY
LPMDRES

CKETOLPMDDLY

PWDDLY
Bit Default &
Field Name (ID): Description
Range Access

Minimum Self-Refresh Time [tSR/tCKESR] (TCKESR):

3h
31:26 Specifies the minimum time that DRAM should remain in SR (in
RW
DRAM clocks).
Minimum Low Power Mode Residency (LPMDRES): Specifies
6h
25:21 the minimum time that PHY should remain in LPMode (in DRAM
RW
clocks).
Low Power Mode Exit to Clock Enable Delay
(LPMDTOCKEDLY): Specifies the minimum time between the LP
Ah
20:15 Mode exit to the CK stop/tristate deassertion and powerdown exit
RW
(in DRAM clocks).
Note: Must be equal to t_idle_latency and less than 0x3C.
Clock Stop to Low Power Mode Delay (CKETOLPMDDLY):
Specifies the time between CK stop/tristate to the Low Power
Ah Mode entry. This timing parameter is used to delay Low Power
14:8
RW Mode entry (in DRAM clocks).
Note: Must be at least equal to t_idle_length parameter and less
than 0x7C.
Power Down Idle Timer (PWDDLY): This is a non-JEDEC
18h
7:0 timing parameter used to delay powerdown entry (in DRAM
RW
clocks).

5.2.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset

102Ch
Specifies the parameters to control DRAM ODT.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD31_30

RSVD23_18

RDODTSTOP

WRODTSTOP
R1RDODTCTL
R0RDODTCTL

R1WRODTCTL

R0WRODTCTL

RSVD13

RSVD4
RDODTSTART

WRODTSTART

334818 65
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Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

Rank 1 Read ODT Control (R1RDODTCTL): Specifies the

behavior of ODT signals when a Read command is issued to Rank
0h 1.
29
RW 0 - Read ODT is disabled for Rank 1
1 - Assert ODT to for Rank 0 (non-targeted Rank)
Note: This register should be set to 0 for LPDDR3 devices
Rank 0 Read ODT Control (R0RDODTCTL): Specifies the
behavior of ODT signals when a Read command is issued to Rank
0h 0.
28
RW 0 - Read ODT is disabled for Rank 0
1 - Assert ODT to for Rank 1 (non-targeted Rank)
Note: This register is reserved for LPDDR3 devices
Rank 1 Write ODT Control (R1WRODTCTL): Specifies the
behavior of ODT signals when a Write command is issued to Rank
1.
0h 00 - Write ODT is disabled
27:26
RW 01 - Assert ODT to Rank 0 (non-targeted Rank)
10 - Assert ODT to Rank 1 (targeted Rank)
11 - Assert ODT to Rank 0 and Rank 1
Note: 10 and 11 are reserved values for LPDDR3
Rank 0 Write ODT Control (R0WRODTCTL): Specifies the
behavior of ODT signals when a Write command is issued to Rank
0.
0h 00 - Write ODT is disabled
25:24
RW 01 - Assert ODT to Rank 0 (targeted Rank)
10 - Assert ODT to Rank 1 (non-targeted Rank)
11 - Assert ODT to Rank 0 and Rank 1
Note: 10 and 11 are reserved values for LPDDR3

23:18
0h Reserved (RSVD23_18): Reserved.
RO

Read ODT assertion to de-assertion delay (DDR3L Only)

(RDODTSTOP): Specifies Read ODT assertion to ODT de-assert
0h
17:14 delay (in DRAM clocks).
RW
DDR3L Equation: RDODTSTOP = DOCRx.WRODTSTOP (subtract 1
if DOCRx.WRODTSTART = 1 in 2N mode).

13
0h Reserved (RSVD13): Reserved.
RO

Read command to ODT assertion delay (DDR3L Only)

(RDODTSTART): Specifies Read ODT assertion delay after Read
0h Command (in DRAM clocks).
12:9
RW DDR3L Equation: RDODTSTART = CL CWL (add 1 if
DOCRx.WRODTSTART = 0 in 2N mode).
The max value for this CR is 0xE

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Bit Default &

Field Name (ID): Description
Range Access

Write ODT Assertion to De-assertion Delay (WRODTSTOP):

Specifies number of clocks after ODT assertion that D-Unit
0h deasserts ODT signal (in DRAM clocks).
8:5
RW LPDDR3 Equation: WRODTSTOP = RU(tODTon(max)/tCK) +
RU((tDQSSmax+tWPST)/tCK) + BL/2 - RD(tODToffmin/tCK)
DDR3L Equation: WRODTSTOP >= 6

4
0h Reserved (RSVD4): Reserved.
RO

Write command to ODT assertion delay (WRODTSTART):

Specifies number of clocks after Write command that D-Unit
asserts ODT signal (in DRAM clocks).
LPDDR3 Equation: WRODTSTART = WL - RU(tODTon(max)/tCK)
0h DDR3L Equation: WRODTSTART = 0 Note: DDR3 spec requires
3:0
RW ODT to be asserted high when the DRAM Write command is
issued. In DDR3L 2N mode the value can be set to 0 to assert ODT
one DRAM clock earlier than the Write Command (WR) or set to 1
to assert at the same clock as command (CS assertion).
The max value for this CR is 0xE

5.2.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—

Offset 1030h
Specifies the parameters to control D-Unit power management features.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD23
RSVD31_29

SREDLY
SUSPMOP

SRPMCLKW

DYNPMOP

DYNSREN

Bit Default &

Field Name (ID): Description
Range Access

31:29
0h Reserved (RSVD31_29): Reserved.
RO

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 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

SUSPEND/SUSPENDP Power Management Message Opcode

(SUSPMOP): DDRIO PHY Power Mode Opcode: After the D-Unit
has placed the DRAM devices in Self Refresh/PASR mode as the
result of a SUSPEND/SUSPENDP message, it sends this 5-bit value
0h
28:24 to the DDRIO PHY to tell it which power saving mode it should
RW
enter.
Changing this register value while in SUSPEND will have no effect.
Note: This opcode cannot be a PM state where it disables PHY PLLs
i.e PM7 in LPDDR PHY.

23
0h Reserved (RSVD23): Reserved.
RO

PM Message Wait for Clock Gate Enable (SRPMCLKW): Specifies when it is safe
to send PM message to the PHY. When enabled, D-Unit waits for SPID Clock to
deassert before sending a PM message on SR entry.

0h • 0: D-Unit will not wait for SPID_clk to deassert before sending

22
RW the PM message to PHY.
• 1: D-Unit will wait for SPID_clk to deassert before sending PM
message to the PHY.
Note: The value must be 1 when DYNPMOP = 7h.

Dynamic Self-Refresh Power Management Message Opcode

(DYNPMOP): DDRIO PHY Power Mode Opcode: After the D-Unit
has placed the DRAM devices in Self Refresh mode as the result of
0h
21:17 a Dynamic Self-Refresh, it sends this 5bit value to the DDRIO PHY
RW
to tell it which power saving mode it should enter.
Changing this register value while in self-refresh will only change
the PM state for the next entry in DynSR.
Dynamic Self-Refresh Enable (DYNSREN): When set to 1, the
D-Unit will automatically control DRAM Self Refresh entry and exit
based on interface state and requests in pending queues. When
0h
16 there is no pending request in the queues and PMI is idle, then the
RW
D-Unit will place the DRAM devices in Self Refresh mode. The
DRAM devices will be brought out of Self-Refresh when idle
conditions don't hold.
Self-Refresh Entry Delay (SREDLY): Specifies the minimum
0h
15:0 time the D-Unit will wait before it enters Dynamic Self-Refresh
RW
mode when idle (in 16x DRAM Clocks).

5.2.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—

Offset 1034h
Specifies the parameters to control D-Unit power management features.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10000028h

68 334818
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3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0

RSVD31_30

PASR

ENCKSTP

LPMODEOP

DISPWRDN
RPTCLKGTDIS

CLKGTDIS
CSTRIST

RSVD6
ODTTRIST
PCLSTODIS
CMDTRIST
SBEPCLKGTDIS

PCLSTO
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

D-Unit Repeaters Clock Gate Disable (RPTCLKGTDIS):

Setting this bit to 0 allows majority of the repeaters between D-
Unit and PHY to clock gate when there is no activity in order to
save power.
0h 0 - Enable Repeaters clock gating, 1 - Disable Repeaters clock
29
RW gating.
Note: This is a de-feature bit and should be set to 0 for normal
operation.
Note: The value should only change after DRAM Timing Registers
(DTR) are programmed.
IOSF-SB End Point Clock Gate Disable (SBEPCLKGTDIS):
Setting this bit to 0 enables the clock gating of IOSF-SB End
Points in D-Unit and CPGC when there is no IOSF-SB activity in
order to save power.
1h 0 - Enable IOSF-SB EP clock gating, 1 - Disable IOSF-SB clock
28
RW gating.
Note: This is a de-feature bit and should be set to 0 for normal
operation.
Note: The value should only change after DRAM Timing Registers
(DTR) are programmed.
Local Clock Gate Disable (CLKGTDIS): Setting this bit to 0 allows the majority of
the D-Unit clocks to be gated off when there is no activity in order to save power.
When set to 1, D-Unit clockgating is disabled.
0h • 0: Enable.
27
RW
• 1: Disable.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.

Chip Select Tristate Enable (CSTRIST):

• 0: The DRAM CS pins associated with the enabled ranks are
0h never tristated.
26
RW
• 1: The DRAM CS pins are tristated when DRAM clock is
stopped or tristated.
Note: CS is not tristated when global tristate flow is disabled (DCBR.TRISTDIS = 1).

334818 69
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Bit Default &

Field Name (ID): Description
Range Access

Command/Address Tristate (CMDTRIST):

• 00: The DRAM CA pins are never tristated.
• 01: The DRAM CA pins are only tristated when all enabled CKE
0h
25:24 pins are low.
RW
• 10: The DRAM CA pins are tristated when not driving a valid
command.
• 11: Reserved
Partial Array Self-Refresh Segment Mask (PASR): This is the
0h
23:16 Segment Mask used for the MRW to enable PASR during
RW
SUSPENDP (Partial Array Self Refresh entry).
Page Close Timeout Period (PCLSTO): Specifies the time from
0h the last access of a DRAM page until that page is scheduled to
15:8
RW close by sending a Precharge command to DRAM (in 16 x DRAM
clocks).
Page Close Timeout Disable (PCLSTODIS): When disabled, D-Unit will not close
the DRAM page when idle.
0h • 0: Enable page close timer.
7
RW
• 1: Disable page close timer (Used during DRAM init and
DDRIO training).

6
0h Reserved (RSVD6): Reserved.
RO

ODT Tristate Enable (ODTTRIST):

• 0: The DRAM ODT pins associated with the enabled ranks are
1h never tristated.
5
RW
• 1: DRAMs ODT pins are tristated when DRAM clock is stopped
or tristated.
Note: ODT is not tristated when global tristate flow is disabled (DCBR.TRISTDIS = 1)

Clock Stop/Tristate Enable (ENCKSTP): Enable/Disable CK Stop/Tristate During

Power down.
• 00: Disable CK Stop/Tristate During Power down.
1h • 01: Enable CK Stop During Power down.
4:3
RW
• 10: Enable CK Tristate During Power down.
• 11: Reserved
Note: CK is not stopped or tristated when global tristate flow is disabled
(DCBR.TRISTDIS = 1).

Low Power Mode Opcode (LPMODEOP): D-Unit will send the

value in this register after it has entered Powerdown Mode and has
0h stopped/tristated the clock.
2:1
RW 00: Disable LPMode.
Note: LPMODE entry is not possible when global tristate flow is
disabled (DCBR.TRISTDIS = 1).

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Bit Default &

Field Name (ID): Description
Range Access

Disable Power Down (DISPWRDN): Setting this bit to 1 disables dynamic control
of DRAM Power-Down entry and exit by keeping the CKE pins driven high. BIOS may
set it to 1 during DRAM initialization and DDRIO training. This bit should be set to 0
for normal operation.
• 0: The D-Unit dynamically controls the CKE pins to place the
0h DRAM devices in Power Down mode and bring them out of
0
RW Power Down mode.
• 1: The D-Unit constantly drives the CKE pins high to keep the
DRAM devices from entering Power Down mode when ranks
are idle.
Note: This bit is overridden if CKEMODE = 1. This bit does not control CKE behavior
on SR entry/exit.

5.2.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1038h

Specifies the parameters to control scheduling of refresh commands.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1750h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 0
RSVD31_22

DISREFDBTCLR

RSVD19_18

RSVD17_16

REFWMPNC

REFWMHI

RSVD3_1
REFSKWDIS

EXTRAREFDBT

MINREFRATE

OREFDIS
Bit Default &
Field Name (ID): Description
Range Access

31:22
0h Reserved (RSVD31_22): Reserved.
RO

Disable Refresh Debt Clear (DISREFDBTCLR): When set, D-Unit will not clear
refresh debt before Self Refresh SR Entry:

0h • 0: D-Unit sends all postponed REF commands to DRAM before

21 it enters Self Refresh.
RW
• 1: D-Unit enters SR without clearing the Refresh Debt (for
Debug only).

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Bit Default &

Field Name (ID): Description
Range Access

Refresh Skew Disable (REFSKWDIS): Disables Skewing of Refresh Counting

between Ranks. Each rank has its own refresh counter. By default incrementing these
refresh counters are skewed by 1/2 the tREFI period. Setting this bit to a 1 disables
this feature and all refresh counters will increment at the same time per tREFI period.
Skewing the tREFI counters can improve performance since traffic to all ranks does
not have to be blocked to perform refresh.
0h
20
RW • 0: Incrementing the refresh counters are skewed by 1/2 tREFI
period.
• 1: All refresh counters will increment at the same time per
tREFI period.

19:18
0h Reserved (RSVD19_18): Reserved.
RO

17:16
0h Reserved (RSVD17_16): Reserved.
RO

Extra Refresh Debit (EXTRAREFDBT): When set to 1, D-Unit

0h
15 adds one extra refresh debit (for a total of two) on Self-refresh
RW
exit.
Minimum Refresh Rate (MINREFRATE): Ensures that refresh rate never drops
below a certain limit regardless of TQ polling.
• 000: Disable tREFI counter and stop issuing refresh
commands.
• 001: 0.25x refresh rate (i.e. 4x tREFI same as no limit).
1h • 010: 0.5x refresh rate (i.e. 2x tREFI).
14:12
RW • 011: 1x refresh rate (i.e. 1x tREFI).
• 100: 2x refresh rate (i.e. 0.5x tREFI).
• 101: 4x refresh rate (i.e. 0.25x tREFI).
• 110: 4x refresh rate with derating forced on i.e. 0.25x tREFI.
• 111: Reserved.
Refresh Panic Watermark (REFWMPNC): When the Refresh
counter per rank is greater than this value, the D-Unit will send a
7h REF command to the rank regardless of pending requests.
11:8
RW Note: REFWMPNC must be greater than or equal to REFWMHI and
greater than 2, Max Value must be less than 8 to not violate
9xtREFI JEDEC requirement.
Refresh High Watermark (REFWMHI): When the Refresh
counter per rank is greater than this value, the D-Unit will send a
5h REF command to the rank if there is no critical priority requests in
7:4
RW the pending queues.
Note: Value must be greater or equal to 1 and less than or equal
to REFWMPNC.

3:1
0h Reserved (RSVD3_1): Reserved.
RO

72 334818
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Bit Default &

Field Name (ID): Description
Range Access

Opportunistic Refresh Disable (OREFDIS): Disable opportunistic scheduling of

refresh.
• 0: D-Unit will send a REF command only if there is no pending
0h request to that rank.
0
RW • 1: D-Unit will not send any opportunistic refreshes. Refresh
commands are only sent when the refresh counter is greater
than REFWMHI.
Note: When set, DISREFDBTCLR must also be set to be able to enter SR.

5.2.15 D-Unit Scheduler (D_CR_DSCH)—Offset 103Ch

Specifies parameters to control scheduling of commands to DRAM.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 3901C08h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0
BLKRDBF_ADD_RDDATA_CR
SPID_EARLY_RDDATA_VALID

RSVD15_14

BYPASSEN
BLKRDBF
RSVD31

BGF_EARLY_RDDATA_VALID

INORDERMODE

TMWR_TA_DELTA
WPQCOUNT

RPQCOUNT

STRETCHMODE

Bit Default &

Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

BGF Early Read Data Valid (BGF_EARLY_RDDATA_VALID): Specifies the

number of clocks the D-Unit sends the read data valid through the BGF earlier as
compared to the data.

0h • 00: Always write read valid in same SPID clock as data.

30:29
RW • 01: Always write read valid one SPID clock before data.
• 10: Write read valid up to 2 SPID clocks before data.
• 11: Reserved
SPID Early Read Data Valid
0h (SPID_EARLY_RDDATA_VALID): Specifies the delay in SPID
28:27
RW clocks from RDDATA_VALID assertion to actual data on SPID. The
value should match what is programmed in DDRIO (PHY).

334818 73
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Write Pending Queue Count (WPQCOUNT): Used to limit the

1Ch number of available slots in Write Pending Queue/ Write Data
26:21
RW Buffer. WPQCOUNT will only recognize changes when PMI ISM is
not active.
Read Pending Queue Count (RPQCOUNT): Used to limit the
10h
20:16 number of entries in Read Pending Queue. RPQCOUNT will only
RW
recognize changes when PMI ISM is not active.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

Read Return Data Additional Credits

(BLKRDBF_ADD_RDDATA_CR): Number of additional full
7h cacheline (64B) read data return credits exposed to D-Unit when
13:10
RW BLKRDBF is set.
Note: The value in this field has no effect on Read return credits
when BLKRDBF is not set.
In-Order Mode (INORDERMODE):
• 0h: In order mode disabled: Commands are sent out of order.
• 1h: Partial in order mode: Read and Write CAS commands are
sent in the order they were recieved. ACT and PRE can go out
of order.
0h
9:8
RW • 2h: Full in order mode serialized test: All DRAM commands
CAS ACT PRE associated with a PMI request are issued to DDR
before any DRAM commands for a subsequent PMI request.
• 3h: Reserved.
In order modes should be enabled during init/training/CPGC testing. Should never be
changed while the D-Unit queues are nonempty.

7
0h Idle Bypass Mode Enable (BYPASSEN): Reserved
RW

Block When RDB Full (BLKRDBF): When set D-Unit stops

0h
6 scheduling new read commands to DRAM when the read data
RW
buffer (RDB) is full.
Stretch Mode (STRETCHMODE): When stretch mode is enabled, commands are
initiated only on Phase 0 of SPIDClk.
• 00: Stretch mode is disabled.
0h
5:4 • 01: Commands are initiated on Phase 0 of every SPID clocks.
RW
• 10: Commands are initiated on Phase 0 of even SPID clocks.
• 11: Commands are initiated on Phase 0 of odd SPID clocks.
Masked Write Turnaround Delta (TMWR_TA_DELTA): The value in this register
8h is subtracted from Masked Write to Read, Masked Write to Write and Masked Write to
3:0 Masked Write turnaround times to account for half BL MWr commands in LPDDR4.
RW
• LPDDR4: = MWr tCCD = MWr BL/2 = 8.

5.2.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1040h

Specifies parameters to control ZQ Calibration.

Access Method

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Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1057h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1

ZQCLMODE
ZQCALTYPE
ZQCALSTRTR1
ZQCALSTRTR0

RSVD28_23

SRXZQC

RSVD20_18

RSVD15_14

ZQINT
ZQCDIS
Bit Default &
Field Name (ID): Description
Range Access

ZQ Calibration Type (ZQCALTYPE): Determines whether the

ZQ Calibration is a long or short calibration command (due to
0h
31 ZQCALSTRT).
RW
0: Short calibration (ZQCS).
1: Long calibration (ZQCL).
ZQ Calibration Start Rank 1 (ZQCALSTRTR1): Set this bit to 1
to start the ZQ calibration sequence on Rank 1. This bit will remain
0h a 1 until the ZQ calibration is complete for rank 1, then it will
30
RW/V return to 0.
0: ZQ calibration is done.
1: ZQ calibration has started and is in progress.
ZQ Calibration Start Rank 0 (ZQCALSTRTR0): Set this bit to 1
to start the ZQ calibration sequence on Rank 0. This bit will remain
0h a 1 until the ZQ calibration is complete for rank 0, then it will
29
RW/V return to 0.
0: ZQ calibration is done.
1: ZQ calibration has started and is in progress.

28:23
0h Reserved (RSVD28_23): Reserved.
RO

Self-Refresh Exit ZQ Calibration Control (SRXZQC):

• 00: On DynSR exit ZQ timer determines the ZQ type. When
the state is lost (i.e due to AutoPG/S0ix) ZQCL is always
performed.
0h • 01: Always perform ZQCL after self refresh exit, in LPDDR4,
22:21
RW ZQ with traffic blocked.
• 10: Always perform ZQCS on SR exit. For LPDDR4, ZQ while
traffic is allowed.
• 11: No ZQCL commands are sent (it disables ZQCAL
commands on SR exit).

20:18
0h Reserved (RSVD20_18): Reserved.
RO

334818 75
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Bit Default &

Field Name (ID): Description
Range Access

ZQ Calibration Mode (ZQCLMODE): Specifies how ZQCal commands are sent to

different ranks.
0h
17 • 0: ZQCal commands are sent in parallel to all ranks.
RW
• 1: ZQCal commands are sent serially to each rank.
Periodic ZQ Calibration Disable (ZQCDIS):
0h
16 • 0: Periodic ZQ Calibration is Enabled.
RW
• 1: Disable periodic ZQ Calibration.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

ZQ Calibration Interval (ZQINT): Specifies the time interval

1057h
13:0 between two ZQCS (LPDDR3) or ZQ Start (LPDDR4) commands to
RW
a DRAM device. (in RTC 32.8KHz clocks)

5.2.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset

104Ch
Specifies parameters for VNN Scaling Timer in D-Unit. The values in this register will be
set by P-code during VNN scaling period.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VNN_TIMER_TIME
RSVD30_12
VNN_TIMER_EN

Bit Default &

Field Name (ID): Description
Range Access

VNN Scaling Timer Enable (VNN_TIMER_EN):

0h
31 • 0: The D-Unit VNN Scaling Timer is disabled.
RW
• 1: The D-Unit VNN Scaling Timer is enabled.

30:12
0h Reserved (RSVD30_12): Reserved.
RO

0h VNN Timer Time (VNN_TIMER_TIME): The final timer value

11:0
RW (in 16 x DRAM clocks).

76 334818
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5.2.18 Periodic DRAM Temperature Polling Control (TQ)

(D_CR_TQCTL)—Offset 1050h
Specifies the control for periodic temperature monitoring and control of DRAM device.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 6C000008h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

ENDERATE
TQDATAR1

TQDATAR0

RSVD25_22

RSVD7_5

SRTEN

TQDATAPUSHEN
TQPOLLPER

TQPOLLSREN
TQPOLLEN
Bit Default &
Field Name (ID): Description
Range Access

TQ Data Rank 1 (TQDATAR1): If Rank 1 is disabled, this value

3h will remain zero.
31:29
RW/V This field contains the data of the last DRAM Mode Register Read
to MR4 MRR issued. It is overwritten with each command.
TQ Data Rank 0 (TQDATAR0): This field contains the data of
3h
28:26 the last DRAM Mode Register Read to MR4 MRR issued. It is
RW/V
overwritten with each command.

25:22
0h Reserved (RSVD25_22): Reserved.
RO

TQ Poll Period (TQPOLLPER): This sets the frequency by which

0h
21:8 the D-Unit polls the DRAM mode register MR4 to determine
RW
required refresh rate (in 4x tREFI units).

7:5
0h Reserved (RSVD7_5): Reserved.
RO

Self Refresh Temperature Range Enable (DDR3 Only)

(SRTEN): When set, before every Self refresh entry, D-Unit
0h writes a 1 to bit 7 of TQOFFSET.MR_VALUE when TQDATA for that
4
RW rank indicates a value higher then 0x3, and writes a 0 to that bit
otherwise. The new MR_VALUE is then written into MR2 of DDR3
for each enabled rank.
Enable Dynamic Timing Derating (ENDERATE): When set to
1, the Dynamic Timing Derating is enabled. When the D-Unit
1h
3 determines (via TQ polling) that the DRAM requires timing
RW
derating in addition to refresh interval adjustment, the D-Unit will
automatically adjust the relevant timing parameters.

334818 77
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Bit Default &

Field Name (ID): Description
Range Access

0h Enable TQ Data Push (TQDATAPUSHEN): When set to 1, D-

2
RW Unit pushes the data form the last MR4 read to a punit register.
Enable TQ Poll on Self-Refresh Exit (TQPOLLSREN): This bit
0h
1 enables MR4 read on Self Refresh Exit. If disabled, D-Unit will not
RW
read MR4 value on Self-Refresh exit.
Enable Periodic TQ Poll (TQPOLLEN): This bit enables periodic
0h
0 TQ Poll. If disabled, D-Unit will not read MR4 value periodically.
RW
Note: Will be enabled only if refreshes are enabled.

5.2.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset

1054h
Specifies temperature offset and refresh rate adjustments requested by software.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MR4_ADDER
RSVD31_26

RSVD15_11

RSVD7_3

MR3_OFFSET_UPDATE
MR_VALUE

Bit Default &

Field Name (ID): Description MR3_THERM_OFFSET
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

MR Value (MR_VALUE): MR2 Shadow Register (DDR3L Only):

0h BIOS writes the correct value of MR2 register in DDR3L into this
25:16
RW field at boot time. D-Unit modifies one bit and rewrites the MR2
into DDR3L DRAM before SR entry.

15:11
0h Reserved (RSVD15_11): Reserved
RO

MR4 Adder (MR4_ADDER): D-Unit adds the value of this field to

0h
10:8 TQDATA read from MR4 the resulting value is used to control
RW
refresh rate and AC timing derating.

7:3
0h Reserved (RSVD7_3): Reserved.
RO

78 334818
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Bit Default &

Field Name (ID): Description
Range Access

MR3 Offset Update (MR3_OFFSET_UPDATE): When set, D-

0h Unit writes the merged value of MR3_VALUE and
2
RW/V MR3_THERM_OFFSET into MR3 of DRAM. D-Unit clears this bit
once the value is written.

1:0
0h MR3 Thermal Offset (MR3_THERM_OFFSET): Reserved
RW

5.2.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 10A4h

Specifies parameters to control data scrambling in D-Unit.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCRM_EN
RSVD30

RSVD27_16
CLOCKGATE

Bit Default &

Field Name (ID): Description KEY
Range Access

Enable Data Scrambler (SCRM_EN): When set to 1, data

0h
31 scrambling is enabled. When set to 0, data scrambling is disabled.
RW
Should be set before D_CR_BGF_CTL_BGF_RUN is set to 1.

30
0h Reserved (RSVD30): Reserved.
RO

Scrambler Clock Gate Select (CLOCKGATE): This field controls how the scrambler
output code is clock gated to reduce power.
• 00: Clock gate disabled.
0h
29:28 • 01: Clock Gate every 2 cycle.
RW
• 10: Clock Gate every 3 cycle.
• 11: Clock Gate every 4 cycle.

27:16
0h Reserved (RSVD27_16): Reserved.
RO

0h Scrambling Key (KEY): Sets the key for the scrambler. The key
15:0
RW should be a random value that is set following each cold boot.

334818 79
 MCHBAR

5.2.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset

10ACh
Contains the target address for ECC error injection.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADDRESS

RSVD0
RSVD31

Bit Default &

Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

Error Injection Target Address (ADDRESS): Specifies the PMI

0h address of the write transaction to be injected with the error. Only
30:1
RW applicable to Write transactions. Read/under-fill read of the partial
write operation is not affected.

0
0h Reserved (RSVD0): Reserved.
RO

5.2.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—

Offset 10B0h
Controls injecting correctable or uncorrectable errors into the write requests specified
by target address.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SEL_HI
RSVD31_4

EN_HI
SEL_LO
EN_LO

80 334818
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Bit Default &

Field Name (ID): Description
Range Access

31:4
0h Reserved (RSVD31_4): Reserved
RO

Error Injection Type Higher 32B (SEL_HI): If enabled, the error injection is
continuously armed for ERR_INJ.ADDR 32B write address matching until it is cleared.
• 00: No error injection.
• 01: Uncorrectable Error (UE) is armed for write address
matching to inject UE by using the same poisoning scheme,
0h i.e. inverting corresponding write ECC[6:0] on QW0 of the 32B
3
RW data.
• 10: Correctable Error (CE) is armed for write address
matching to inject CE by inverting corresponding write ECC[0]
on QW0 of the 32B data.
• 11: Reserved.
Error Injection Enable Higher 32B (EN_HI): When set the
0h
2 error injection is continuously armed for higher 32B of
RW
D_CR_ERR_INJ_ADDR write address matching until it is cleared.
Error Injection Type Lower 32B (SEL_LO): 0 - Uncorrectable
Error (UE) is armed for write address matching to inject UE by
using the same poisoning scheme, i.e. inverting corresponding
0h
1 write ECC[6:0] on every QW of the 32B data.
RW
1 - Correctable Error (CE) is armed for write address matching to
inject CE by inverting corresponding write ECC[0] on every QW of
the 32B data.
Error Injection Enable Lower 32B (EN_LO): When set, the
0h
0 error injection is continuously armed for lower 32B of
RW
D_CR_ERR_INJ_ADDR write address matching until it is cleared.

5.2.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 10B4h

Detected ECC errors are captured in this register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CLEAR

CERR
MERR
ECC_VISA

ERR_BURST

ERR_CHUNK

SYNDROME_QW

TAG

334818 81
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Bit Default &

Field Name (ID): Description
Range Access

0h Clear (CLEAR): Setting this bit to one clears all fields in this
31
RW/V register, including itself.
PMI VISA Byte Select (ECC_VISA): Select ECC or PMI byte on VISA :
• 00: ECC byte,
0h
30:29 • 01: PMI Data Byte [7:0],
RW
• 10: PMI Data Byte [63:56],
• 11: PMI Data Byte [255:248]
Correctable Single-bit Error (CERR): This bit is set when a
correctable single-bit error occurs on a memory read data
transfer. When this bit is set, the address that caused the error
0h
28 and the error syndrome are also logged and they are locked to
RW/V
further single bit errors, until this bit is cleared. A multiple bit
error that occurs after this bit is set will override the address/error
syndrome information.
Uncorrectable Multiple-bit Error (MERR): This bit is set when
an uncorrectable multiple-bit error occurs on a memory read data
0h
27 transfer. When this bit is set, the address that caused the error
RW/V
and the error syndrome are also logged and they are locked until
this bit is cleared.
0h Error Burst Number (ERR_BURST): Burst number (in BL8) of
26:25
RW/V the error within a chunk.
Error Chunk Number (ERR_CHUNK): Chunk number of the
0h error.
24
RW/V 0 - lower 32B chunk has error if MERR/CERR is set
1 - higher 32B chunk has the error if MERR/CERR is set
0h Quad Word ECC Syndrome (SYNDROME_QW): ECC Syndrome
23:16
RW/V for a QW (64 bit) within 32B Address
0h Request Tag (TAG): Read Return Tag matches with the PMI
15:0
RW/V Request Tag which triggered the error log.

5.2.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 10BCh

Contains the values read from D-Unit

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

82 334818
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RSVD31_16

FUSESTAT
Bit Default &
Field Name (ID): Description
Range Access

31:16
0h Reserved (RSVD31_16): Reserved.
RO

D-Unit Status (FUSESTAT): D-Unit bits are captured into this register and are
available to be read.
• [0]: fus_dun_ecc_dis.
• [3:1]: fus_dun_max_supported_device_size[2:0].
0h • [4:4]: fus_dun_lpddr3_dis.
15:0
RO/V
• [5:5]: fus_dun_lpddr4_dis.
• [6:6]: reserved.
• [7:7]: fus_dun_ddr3l_dis.
• [15:8]: reserved.

5.2.25 Major Mode Control (D_CR_MMC)—Offset 1124h

Specifies parameters to control read/write major mode operation and transitions.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 2B01E518h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0
RSVD26
RSVD31_30

RSVD22_18

WMMEXIT
RIMPRIO

WIMTHRS

WMMENTRY
RAW_WMM

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

RAW Conflict Read Priority for WMM Transition

(RAW_WMM): If a conflict read reaches this priority (or greater
depending on access class occupancy), WMM will be triggered to
5h
29:27 unblock the corresponding write. D-Unit will stay in WMM until
RW
corresponding write is issued.
Note: The value in this bit must not be higher than lowest terminal
priority level of each access class.

334818 83
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Bit Default &

Field Name (ID): Description
Range Access

26
0h Reserved (RSVD26): Reserved.
RO

6h Read Isoch Trigger Priority (RIMPRIO): If any read in the

25:23
RW RPQ is at this programmable priority, RIM is triggered.

22:18
0h Reserved (RSVD22_18): Reserved.
RO

Write Isoch Threshold (WIMTHRS): When the number of

1Eh entries in WPQ is greater than or equal to this value (higher than
17:12
RW WMM entry watermark, less than WPQ size), it triggers write isoch
mode (WIM).
Write Major Mode Exit Watermark (WMMEXIT): When the
14h
11:6 number of entries in WPQ is less than this value, the D-Unit will
RW
switch back to read major mode.
Write Major Mode Entry Watermark (WMMENTRY): When
18h the number of entries in WPQ is greater than or equal to this
5:0
RW value, the D-Unit will switch to write major mode (WMM).
Note: the value must not be set to 0.

5.2.26 Major Mode RD/WR Counter (Set A and B)

(D_CR_MMRDWR_AB)—Offset 1128h
Minimum read and maximum write counter control. This register defines the minimum
number of reads in RMM and maximum number of writes in WMM before a mode
transition happens.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F207C8h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0
MAXWRA

MINRDA
RSVD31_26

RSVD13_12
MAXWRB

MINRDB

Bit Default &

Field Name (ID): Description
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

1Fh Max Writes B (MAXWRB): Maximum number of writes D-Unit

25:20
RW can send in WMM mode before returning to RMM (set B).

84 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

8h Min Reads B (MINRDB): Minimum number of reads that has to

19:14
RW be serviced before a switch to WMM is allowed (set B).

13:12
0h Reserved (RSVD13_12): Reserved.
RO

1Fh Max Writes A (MAXWRA): Maximum number of writes D-Unit

11:6
RW can send in WMM mode before returning to RMM (set A).
8h Min Reads A (MINRDA): Minimum number of reads that has to
5:0
RW be serviced before a switch to WMM is allowed (set A).

5.2.27 Major Mode RD/WR Counter (Set C and D)

(D_CR_MMRDWR_CD)—Offset 112Ch
Minimum read and maximum write counter control. This register defines the minumum
number of reads in RMM and maximum number of writes in WMM before a mode
transition happens (sets C and D).

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F207C8h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0

MINRDC
RSVD31_26

MAXWRC
MINRDD

RSVD13_12
MAXWRD

Bit Default &

Field Name (ID): Description
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

1Fh Max Writes D (MAXWRD): Maximum number of writes D-Unit

25:20
RW can send in WMM mode before returning to RMM (set D).
8h Min Reads D (MINRDD): Minimum number of reads that has to
19:14
RW be serviced before a switch to WMM is allowed (set D).

13:12
0h Reserved (RSVD13_12): Reserved.
RO

1Fh Max Writes C (MAXWRC): Maximum number of writes D-Unit

11:6
RW can send in WMM mode before returning to RMM (set C).
8h Min Reads C (MINRDC): Minimum number of reads that has to
5:0
RW be serviced before a switch to WMM is allowed (set C).

334818 85
 MCHBAR

5.2.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1130h

Each field of this register defines the initial priority of one access class.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 17C2h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 1 0
RSVD31_15

AC4IP

AC3IP

AC2IP

AC1IP

AC0IP
Bit Default &
Field Name (ID): Description
Range Access

31:15
0h Reserved (RSVD31_15): Reserved.
RO

1h Access Class 4 Initial Priority (AC4IP): Initial priority level of

14:12
RW read requests coming with access class 4.
3h Access Class 3 Initial Priority (AC3IP): Initial priority level of
11:9
RW read requests coming with access class 3.
7h Access Class 2 Initial Priority (AC2IP): Initial priority level of
8:6
RW read requests coming with access class 2.
0h Access Class 1 Initial Priority (AC1IP): Initial priority level of
5:3
RW read requests coming with access class 1.
2h Access Class 0 Initial Priority (AC0IP): Initial priority level of
2:0
RW read requests coming with access class 0.

5.2.29 Access Class 0 Priority Promotion Control

(D_CR_RD_PROM0)—Offset 1134h
This register defines the priority promotion policy for access class 0. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
next level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F52940h

86 334818
MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0

RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.2.30 Access Class 1 Priority Promotion Control

(D_CR_RD_PROM1)—Offset 1138h
This register defines the priority promotion policy for access class 1. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
associated level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 14000000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES

334818 87
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

Ah Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.2.31 Access Class 2 Priority Promotion Control

(D_CR_RD_PROM2)—Offset 113Ch
This register defines the priority promotion policy for access class 2. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
next level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
RSVD31_30

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.

88 334818
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Bit Default &

Field Name (ID): Description
Range Access

0h Priority 4 Residency (P4RES): Number of CASes that pass

19:15
RW before a request in this priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.2.32 Access Class 3 Priority Promotion Control

(D_CR_RD_PROM3)—Offset 1140h
This register defines the aging policy for access class 3. Each field of this register
defines the number of CASes that pass before the request is promoted to the next
priority level. A value of 31 indicates the request should never be promoted to the next
level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F29400h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
5h Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
5h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.

334818 89
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h Priority 1 Residency (P1RES): Number of CASes that pass

4:0
RW before a request in this priority promotes to the next priority level.

5.2.33 Access Class 4 Priority Promotion Control

(D_CR_RD_PROM4)—Offset 1144h
This register defines the aging policy for access class 3. Each field of this register
defines the number of CASes that pass before the request is promoted to the next
priority level. A value of 31 indicates the request should never be promoted to the next
level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F5294Ah

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
Ah Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.2.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1148h

Specifies when the request with initial priority 0 get promoted to a higher priority level.

90 334818
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Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 6h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

RSVD31_11

DEADLINE_THRS
Bit Default &
Field Name (ID): Description
Range Access

31:11
0h Reserved (RSVD31_11): Reserved.
RO

Deadline Threshold (DEADLINE_THRS): A requests with initial

priority of 0 will exit priority 0 when its deadline is equal or less
6h
10:0 than this value plus current time. This field does not affect the
RW
priority of any requests in access classes with initial priority bigger
than 0.

5.2.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—

Offset 114Ch
This register controls blocking rules enforced in RMM and WMM.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1800h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
RSVD31_25

RSVD23_20
WMM_REG_R1

WMM_PRIO_R4
WMM_PRIO_R3
WMM_PRIO_R2
WMM_PRIO_R1

RSVD15_14

RMM_REG_R6
RMM_REG_R5
RMM_REG_R4
RMM_REG_R3
RMM_REG_R2
RMM_REG_R1

RSVD7_4

RMM_PRIO_R4
RMM_PRIO_R3
RMM_PRIO_R2
RMM_PRIO_R1

334818 91
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Bit Default &

Field Name (ID): Description
Range Access

31:25
0h Reserved (RSVD31_25): Reserved.
RO

0h WMM Regular Rule 1 (WMM_REG_R1): Disable WMM unsafe

24
RW write page hits block safe write page misses same bank.

23:20
0h Reserved (RSVD23_20): Reserved.
RO

WMM Priority Rule 4 (WMM_PRIO_R4): Disable WMM unsafe

priority 1 read miss block write hit to same bank.
0h
19 Note: This rule does not block the bank that is being blocked by
RW
WMM_PRIO_R3.
Priority rules 1, 3 and 4 should be enabled/disabled together.
WMM Priority Rule 3 (WMM_PRIO_R3): Disable WMM unsafe
priority 1 write hit block write miss to same bank.
0h
18 Note: This rule does not block the bank that is being blocked by
RW
WMM_PRIO_R1.
Priority rules 1,3 and 4 should be enabled/disabled together.
0h WMM Priority Rule 2 (WMM_PRIO_R2): Disable WMM CAS
17
RW block rule.
WMM Priority Rule 1 (WMM_PRIO_R1): Disable WMM unsafe
0h
16 top priority 1 write miss block write hit same bank.
RW
Priority rules 1, 3 and 4 should be enabled/disabled together.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

0h RMM Regular Rule 6 (RMM_REG_R6): Disable RMM unsafe

13
RW write page hits block safe write page misses same bank.
RMM Regular Rule 5 (RMM_REG_R5): Disable RMM unsafe
read page miss block all safe and unsafe write page hit to the
1h
12 same bank.
RW
Note: This field must not be set to 0 (enabled) if RMM_REG_R4 is
also 0.
RMM Regular Rule 4 (RMM_REG_R4): Disable RMM unsafe
1h write page hit block safe read page miss same bank.
11
RW Note: This field must not be set to 0 (enabled) if RMM_REG_R5 is
also 0.
RMM Regular Rule 3 (RMM_REG_R3): Disable RMM unsafe
0h read page hit block safe read and write page miss same bank.
10
RW Note: This rule does not block the bank that is being blocked by
RMM_PRIO_R3 and RMM_PRIO_R1.
0h RMM Regular Rule 2 (RMM_REG_R2): Disable RMM unsafe
9
RW read page empty block safe write page empty same rank.
0h RMM Regular Rule 1 (RMM_REG_R1): Disable RMM unsafe
8
RW read page hit block safe write page hit same rank.

7:4
0h Reserved (RSVD7_4): Reserved.
RO

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Bit Default &

Field Name (ID): Description
Range Access

RMM Priority Rule 4 (RMM_PRIO_R4): Disable RMM unsafe

critical read miss block read and write hit to same bank.
0h
3 Note: This rule does not block the bank that is being blocked by
RW
RMM_PRIO_R3.
Priority rules 1, 3 and 4 should be enabled/disabled together.
RMM Priority Rule 3 (RMM_PRIO_R3): Disable RMM unsafe
critical read hit block read and write miss to same bank.
0h
2 Note: This rule does not block the bank that is being blocked by
RW
RMM_PRIO_R1.
Priority rules 1, 3 and 4 should be enabled/disabled together.
0h RMM Priority Rule 2 (RMM_PRIO_R2): Disable RMM CAS block
1
RW rule.
RMM Priority Rule 1 (RMM_PRIO_R1): Disable RMM unsafe
0h top critical read miss block read and write hit same bank.
0
RW Note: Priority rules 1, 3 and 4 should be enabled/disabled
together.

5.2.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—

Offset 1154h
Self refresh command register to allow sending WAKE and SUSPEND messages to D-
Unit. (Only one bit can be set at a time). Posted writes to this register are not
completed until hardware clears the field.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WAKE
RSVD31_4

SUSPENDP

RSVD1
SUSPEND

Bit Default &

Field Name (ID): Description
Range Access

31:4
0h Reserved (RSVD31_4): Reserved.
RO

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Bit Default &

Field Name (ID): Description
Range Access

SUSPENDP (SUSPENDP): A SUSPENDP message will put the

DRAM into self-refresh mode. The D-Unit will complete servicing
outstanding memory requests and flush all queued Refresh
commands to DRAM before putting the DRAM in self refresh mode.
0h Finally, a PM message will be sent to the PHY. The bit is cleared by
3
RW/V hardware after the PHY indicates the transition requested in the
PM message has been completed. D-Unit will perform an MRW to
MR17 with an opcode as defined by DPMC0.PASR before it places
the DRAM into Self-Refresh.

SUSPEND (SUSPEND): A SUSPEND message will put the DRAM

into self-refresh mode. The D-Unit will complete servicing
outstanding memory requests and flush all queued Refresh
commands to DRAM before putting the DRAM in Self Refresh
0h
2 mode. Finally, a PM message will be sent to the PHY. The bit is
RW/V
cleared by hardware only after the PHY indicates the transition
requested in the PM message has been completed.
Note: When COLDWAKE is set prior of setting this bit the DRAM
will not be placed in SR.

1
0h Reserved (RSVD1): Reserved.
RO

WAKE (WAKE): Take PHY out of PM states and wakes the DRAM
out of self refresh mode. The bit is cleared by hardware only when
0h
0 the DRAM has exited out of self refresh mode and is accessible.
RW/V
Note: When COLDWAKE is set prior of setting this bit the D-Unit
will not send SR exit command and will not set the DCO.IC bit.

5.2.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—

Offset 1180h
LPDDR4 DQS Retraining control register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

94 334818
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DQS_RETRAIN_INT

RSVD15_14

RSVD3_2
DQS_OSC_RT

DQS_RETRAIN_SRX_EN
DQS_RETRAIN_EN
Bit Default &
Field Name (ID): Description
Range Access

DQS Periodic Retraining Interval (DQS_RETRAIN_INT):

0h
31:16 This sets the frequency by which the D-Unit initiates periodic
RW
retraining (in 1x NREFI).

15:14
0h Reserved (RSVD15_14): Reserved.
RO

DQS Oscillator Runtime (DQS_OSC_RT): After D-Unit starts

DQS oscillator, it must wait this amount of time before being able
0h
13:4 to read the value in MR18 and MR19 (in 16x DRAM clocks).
RW
Value in this register must be at least equal to DRAM's MR23
value. + tOSCO.

3:2
0h Reserved (RSVD3_2): Reserved.
RO

DQS Retrain SRX Exit (DQS_RETRAIN_SRX_EN): Enable

0h retraining on SR exit.
1
RW This bit enables LPDDR4 DQS retraining on Self Refresh Exit. If
disabled, D-Unit will not perform retraining on SR exit.
DQS Retrain Enable (DQS_RETRAIN_EN): Periodic retraining
enable:
0h This bit enables periodic DQS retraining. If disabled, D-Unit will
0
RW not perform retraining periodically.
Note: Will be enabled only if DCO.IC is set and refreshes are
enabled in DRF.MINREFRATE.

5.2.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset

1184h
Controls the data bits swizzling crossbar for MR4.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

334818 95
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MR4_BYTE_SEL2
MR4_BIT2_SEL2

MR4_BIT1_SEL2

MR4_BIT0_SEL2

MR4_BYTE_SEL
RSVD31

RSVD27

RSVD23

RSVD19_18

RSVD15

MR4_BIT2_SEL

RSVD11

MR4_BIT1_SEL

RSVD7

MR4_BIT0_SEL

RSVD3_2
Bit Default &
Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

0h MR4 Bit 2 Select 2nd Byte (MR4_BIT2_SEL2): Selects bit 2 of

30:28
RW MR4 data.

27
0h Reserved (RSVD27): Reserved
RO

0h MR4 Bit 1 Select 2nd Byte (MR4_BIT1_SEL2): Selects bit 1 of

26:24
RW MR4 data

23
0h Reserved (RSVD23): Reserved
RO

0h MR4 Bit 0 Select 2nd Byte (MR4_BIT0_SEL2): Selects bit 0 of

22:20
RW MR4 data.

19:18
0h Reserved (RSVD19_18): Reserved
RO

0h MR4 Byte 2 Select (MR4_BYTE_SEL2): Selects byte position of

17:16
RW the MR4 data for second device.

15
0h Reserved (RSVD15): Reserved
RO

14:12
0h MR4 Bit 2 Select (MR4_BIT2_SEL): Selects bit 2 of MR4 data.
RW

11
0h Reserved (RSVD11): Reserved.
RO

10:8
0h MR4 Bit 1 Select (MR4_BIT1_SEL): Selects bit 1 of MR4 data.
RW

7
0h Reserved (RSVD7): Reserved.
RO

6:4
0h MR4 Bit 0 Select (MR4_BIT0_SEL): Selects bit 0 of MR4 data.
RW

3:2
0h Reserved (RSVD3_2): Reserved.
RO

0h MR4 Byte Select (MR4_BYTE_SEL): Selects byte position of

1:0
RW the MR4 data first device.

5.3 Registers Summary

Table 5-3. Summary of pcs_regs_wrapper Registers
Offset Offset Default
Register Name (ID)—Offset
Start End Value

1200h 1203h DRAM Rank Population 0 (D_CR_DRP0)—Offset 1200h 10000000h

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Table 5-3. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset Default
Register Name (ID)—Offset
Start End Value

1208h 120Bh DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1208h 210702CBh

120Ch 120Fh DRAM Timing Register 1A (D_CR_DTR1A)—Offset 120Ch 30481218h

1210h 1213h DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1210h 8C080C30h

1214h 1217h DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1214h 3002EA28h

1218h 121Bh DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1218h 30209149h

121Ch 121Fh DRAM Timing Register 5A (D_CR_DTR5A)—Offset 121Ch 304200C2h

1220h 1223h DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1220h 20100000h

1224h 1227h DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1224h D060C06h

1228h 122Bh DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1228h CC50A18h

122Ch 122Fh D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 122Ch 0h

1230h 1233h D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1230h 0h

1234h 1237h D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1234h 10000028h

1238h 123Bh DRAM Refresh Control (D_CR_DRFC)—Offset 1238h 1750h

123Ch 123Fh D-Unit Scheduler (D_CR_DSCH)—Offset 123Ch 3901C08h

1240h 1243h DRAM Calibration Control (D_CR_DCAL)—Offset 1240h 1057h

1244h 1247h VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 124Ch 20000h

124Ch 124Fh VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 124Ch 0h

Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset

1250h 1253h 6C000008h
1250h

1254h 1257h TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1254h 0h

1258h 125Bh Data Scrambler (D_CR_SCRAMCTRL)—Offset 12A4h 0h

12A4h 12A7h Data Scrambler (D_CR_SCRAMCTRL)—Offset 12A4h 0h

12ACh 12AFh Error Injection Address Register (D_CR_ERR_INJ)—Offset 12ACh 0h

12B0h 12B3h Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 12B0h 0h

12B4h 12B7h Error Log Register (D_CR_ERR_ECC_LOG)—Offset 12B4h 0h

12BCh 12BFh D-Unit Status (D_CR_DFUSESTAT)—Offset 12BCh 0h

1324h 1327h Major Mode Control (D_CR_MMC)—Offset 1324h 2B01E518h

Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset

1328h 132Bh 1F207C8h
1328h

Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—

132Ch 132Fh 1F207C8h
Offset 132Ch

1330h 1333h Access Class Initial Priority (D_CR_ACCIP)—Offset 1330h 17C2h

Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset

1334h 1337h 1F52940h
1334h

Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset

1338h 133Bh 14000000h
1338h

Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset

133Ch 133Fh 0h
133Ch

Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset

1340h 1343h 1F29400h
1340h

Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset

1344h 1347h 1F5294Ah
1344h

1348h 134Bh Deadline Threshold (D_CR_DL_THRS)—Offset 1348h 6h

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Table 5-3. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset Default
Register Name (ID)—Offset
Start End Value

134Ch 134Fh Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 134Ch 1800h

1354h 1357h DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1354h 0h

1380h 1383h DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1380h 0h

1384h 1387h MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1384h 0h

5.3.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1200h

Rank configuration register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10000000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BLMODE

DWID
ADDRDEC

CASWIZZLE
DRAMDEVICE_PR

DRAMTYPE

RSVD18_16

RSVD3
DDMEN
RKEN1
RKEN0
ECCEN

BAHEN

RSVD13_9

DDEN
RSIEN

Bit Default &

Field Name (ID): Description
Range Access

DRAM Device Per Rank (DRAMDEVICE_PR): Specifies the number of DRAM

devices that are ganged together to form a single rank.
• 00: 1 DRAM device in each rank.
0h • 01: 2 DRAM devices in each rank.
31:30
RW
• 10: 4 DRAM devices in each rank.
• 11: 8 DRAM devices in each rank.
Note: The actual number of devices is one more than the value programmed when
ECC is enabled.

Address Decode (ADDRDEC): Specifies the address mapping to be used:

• 00: 1KB (A).
1h
29:28 • 01: 2KB (B).
RW
• 10: 4KB (C).
• 11: Reserved.

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Bit Default &

Field Name (ID): Description
Range Access

Burst Length Mode (BLMODE):

• 000: Fixed BL8.
• 001: Onthefly BL8.

0h
• 010: Fixed BL16.
27:25
RW • 011: Onthefly BL16.
• 100: Fixed BL32.
• 101: Onthefly BL32.
• 110-111: Reserved.
DRAM Type (DRAMTYPE):
• 000: DDR3L.
• 001: LPDDR3.
0h • 010: LPDDR4.
24:22
RW
• 011: Reserved.
• 100: Reserved.
• 101-111: Reserved.

ECC Enable (ECCEN):

• 0: ECC is disabled.
0h
21
RW • 1: ECC is enabled.
This bit determines if the D-Unit treats the PMI BE_ECC bits as ECC bits or Byte
Enables. This should only be used in configurations that support ECC (DDR3L).

CA Swizzle Type (CASWIZZLE):

• 00: uniDIMM/SODIMM.
0h
20:19 • 01: BGA.
RW
• 10: BGA mirrored (LPDDR3 Only).
• 11: UDIMM (DDR3L Only).

18:16
0h Reserved (RSVD18_16): Reserved.
RO

Bank Address Hashing Enable (BAHEN): See Address Mapping section for full
description.
0h
15 • 0: Bank Address Hashing disabled.
RW
• 1: Bank Address Hashing enabled.
Rank Select Interleave Enable (RSIEN): See Address Mapping section for full
description.
0h
14 • 0: Rank Select Interleaving disabled.
RW
• 1: Rank Select Interleaving enabled.

13:9
0h Reserved (RSVD13_9): Reserved.
RO

334818 99
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

DRAM Device Density (DDEN): Density of the DRAM devices populated on Ranks 0
and 1.
• 000: 4 Gb.
• 001: 6 Gb.
0h • 010: 8 Gb.
8:6
RW
• 011: 12 Gb.
• 100: 16 Gb.
• 101-111: Reserved.
Note: For LPDDR4 this value is the die density.

DRAM Device Data Width (DWID): Data width of the DRAM device populated on
Ranks 0 and 1.
• 00: x8.
0h
5:4 • 01: x16.
RW
• 10: x32.
• 11: x64.

3
0h Reserved (RSVD3): Reserved.
RO

Dual Data Mode Enable (DDMEN):

• 0: PMI Dual Data Mode is disabled in D-Unit, full cacheline
0h
2 read and writes go through a single D-Unit.
RW
• 1: PMI Dual Data Mode is enabled, only half cacheline read/
writes go through a single D-Unit.
0h Rank Enable 1 (RKEN1): Enable Rank 1: Must be set to 1 to
1
RW enable use of this rank.
Rank Enable 0 (RKEN0): Enable Rank 0: Must be set to 1 to
0h
0 enable use of this rank.
RW
Note: Setting this bit to 0 is not a functional mode.

5.3.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1208h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 210702CBh

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 1
TCKCKEH

TXSDLL

TXSR

TRPPB
TRCD

100 334818
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Bit Default &

Field Name (ID): Description
Range Access

Valid Clocks Before CKE High [tCKCKEH/tCSCKEH/tCKSRX] (TCKCKEH):

Number of valid clocks before CKE high (in DRAM clocks).
• LPDDR4: The value in this register covers both tCKCKEH and
tCSCKEH.
• DDR3L/LPDDR3/: The value covers tCKSRX which is defined
as the number of valid DRAM clocks that have to toggle before
10h
31:25 the issuing of the Self Refresh Exit SRX. This value is also used
RW
if the clock frequency is changed or the clock is stopped or
tristated during Power Down i.e. the number valid DRAM
clocks that have to toggle before the issuing of the Power
Down Exit PDX command.
tCKCKEH can be used to compensate for clock stabilization delays in the
motherboard. Note: D-unit hardware enforces minimum of two SPID clock before
CKEH, any value in this register is the additional time.

Exit Self-Refresh to Valid Commands Requiring a Locked

DLL Delay [tXSDLL] (TXSDLL): D-Unit waits max(tXSR+tZQCL/
tZQCS, tXSDLL) before allowing traffic to DRAM (in 64 x DRAM
8h Clocks).
24:21
RW LPDDR3/LPDDR4: tXSDLL = 0.
DDR3L: tXSDLL = tDLLK = 512 Clocks = 8 x 64 DRAM Clocks.
Note: In the equation above, tZQCL/tZQCS = 0 if no ZQ is
performed on SR exit.
Exit Self-Refresh to Valid Command Delay [tXS/tXSR]
(TXSR): DDR3L: tXS - Delay between Self Refresh Exit SRX to
70h
20:12 any DRAM Command not requiring DLL Lock.
RW
LPDDR/: tXSR - Delay between Self Refresh Exit SRX to any DRAM
Command. (in DRAM clocks).
Activate RAS to CAS Command Delay [tRCD] (TRCD):
Specifies the delay between a DRAM Activate command and a
Bh
11:6 DRAM Read or Write command to the same bank (in DRAM
RW
clocks).
Note: Derating adds 1.875ns to this timing.
Precharge to Activate Command Delay of a Single Bank
[tRPpb] (TRPPB): Specifies the delay between a DRAM
Precharge command and a DRAM Activate command to the same
Bh
5:0 bank (in DRAM Clocks).
RW
Note : this CR should be constrained to a minimum of 4 in LPDDR3
and minimum of 8 in LPDDR4.
Note: Derating adds 1.875ns to this timing.

5.3.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 120Ch

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 30481218h

334818 101
 MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0

TXP

RSVD26

TZQCL

TZQLAT
TZQCS
Bit Default &
Field Name (ID): Description
Range Access

Exit Power Down to Next Command Delay [tXP] (TXP):

Specifies the delay from the DRAM Power Down Exit (PDX)
6h
31:27 command to any valid command (in DRAM clocks).
RW
Note: The value in this field must be programmed to tXPDLL when
Slow Exit Mode Power-down is enabled for DDR3L.

26
0h Reserved (RSVD26): Reserved.
RO

ZQ (long) Calibration Time [tZQCL/tZQCAL] (TZQCL):

• LPDDR3/DDR3L: tZQCL/tZQoper: Specifies the delay between
the DRAM ZQ Calibration Long (ZQCL) command and any
DRAM command during normal operation.
120h
25:14 • LPDDR4: tZQCAL: ZQ Calibration time (in DRAM clocks).
RW
Note: This field defines the ZQ Calibration Long delay during normal operation. It is
not the same as tZQinit which uses the same ZQCL command but the delay is longer.
tZQinit applies only during poweron initialization of the DRAM devices and tZQoper
applies during normal operation. BIOS executes the DRAM initialization sequence so
it has to ensure tZQinit is met and not the D-Unit.

ZQ Short Calibration Time [tZQCS] (TZQCS): ZQCS to any

DRAM Command Delay: Specifies the delay between the DRAM ZQ
48h Calibration Short (ZQCS) command and any DRAM command (in
13:6
RW DRAM clocks).
DDR3L and LPDDR3 only. LPDDR4 does not support ZQCS
command
ZQ Latch Time [tZQLAT] (TZQLAT): Specifies the delay
18h between the DRAM ZQ Calibration Latch command and any DRAM
5:0
RW command (in DRAM clocks).
LPDDR4 only.Not used in DDR3L/LPDDR3/.

5.3.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1210h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 8C080C30h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0

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TCKE
RSVD22_21

RSVD16

NREFI
NRFCAB
Bit Default &
Field Name (ID): Description
Range Access

All Bank Refresh Cycle Time [tRFCab] (NRFCAB): Specifies

118h
31:23 the delay between the REFab command to the next valid
RW
command. (in DRAM clocks)

22:21
0h Reserved (RSVD22_21): Reserved.
RO

4h CKE Minimum Pulse Width [tCKE] (TCKE): Specifies the

20:17
RW minimum time from CKEL to CKEH (in DRAM clocks).

16
0h Reserved (RSVD16): Reserved.
RO

Refresh Interval Time [tREFI] (NREFI): Specifies the average

C30h time between refresh commands. JEDEC Base Refresh Interval
15:0
RW time (in DRAM clocks).
Note: D-Unit will ignore the 2 LSBs of this field.

5.3.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1214h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 3002EA28h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 1 0 1 0 0 0
TCWL

TWMWSB
TCMD
TRTP

TCCD_INC

TWTP

Bit Default &

Field Name (ID): Description
Range Access

Read to Precharge Delay [tRDPRE] (TRTP): Specifies the minimum delay

between the DRAM Read and Precharge commands to the same bank (in DRAM
clocks).
6h
31:27 • LPDDR3 Equation: = BL/2 + tRTP - 4.
RW
• LPDDR4 Equation: = BL/2 + Max (8, tRTP) - 8.
• DDR3L Equation: = tRTP.

334818 103
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

CAS to CAS Command Delay Adder (TCCD_INC): Specifies

0h the number of clocks to be added to turnaround times (for Stretch
26:20
RW Mode). It increases delay between Read to Read or Read to Write
commands (in 4 x DRAM clocks).
Write to Precharge Command Delay [tWRPRE] (TWTP): Specifies the minimum
delay between the DRAM Write command and the Precharge command to the same
17h bank (in DRAM clocks).
19:13
RW • LPDDR3/LPDDR4 Equation: tWTP = BL/2 + WL + tWR + 1.
• DDR3L Equation: tWTP = BL/2 + CWL + tWR.
DRAM Command Valid Duration (TCMD): Specifies the number of DRAM clocks a
command is held valid on the DRAM Address and Control buses. 1N is the DDR3 basic
requirement. 2N is the extended mode for board signal integrity.
• 0h: Reserved.
1h
12:11
RW • 1h: 1 DRAM Clock (1N).
• 2h: 2 DRAM Clocks (2N).
• 3h: Reserved.
Note: DDR3L only. tCMD must be set to 1N for LPDDR3/LPDDR4.

Write Latency [WL/CWL] (TCWL): The delay between the

8h
10:6 internal write command and the availability of the first word of
RW
DRAM input data (in DRAM clocks).
Write CAS to Masked Write CAS Delay Same Bank (TWMWSB): Specifies the
minimum delay between DRAM Write command to Masked Write command to same
bank (in DRAM clocks).
28h
5:0 • LPDDR4 Equation: tWMWSB = tCCDMW (BL16) or tCCDMW +
RW
8 (BL32).
Note: Masked Write operation in LPDDR4 is always BL16. D-Unit applies this timing
for same rank as well as same bank.

5.3.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1218h

Specifies DRAM timings parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 30209149h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1
TFAW

TWRDR

TRWDR

TWWDR

TRRDR

104 334818
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Bit Default &

Field Name (ID): Description
Range Access

Four Bank Activate Window [tFAW] (TFAW): A rolling

30h timeframe in which a maximum of four Activate commands can be
31:24
RW issued to the same rank. This is to limit the peak current draw
from the DRAM devices (in DRAM clocks).
Write to Read DQ Delay Different Ranks (TWRDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Read data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tWRDR = WL + tDQSSmax + BL/2 +
tWPST - (RL + tDQSCKmin - tRPRE).
8h
23:18
RW • LPDDR4 Equation: tWRDR = WL - RL + BL/2 + 4 -
tDQSCKmin.
• DDR3L Equation: tWRDR = CWL + tDQSSmax + BL/2 +
tWPST - (CL + tDQSCKmin - tRPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.

Read to Write DQ Delay Different Ranks (TRWDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Write data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tRWDR = RL + tDQSCKmax + BL/2 +
tRPST - (WL + tDQSSmin - tWPRE).
9h
17:12 • LPDDR4 Equation: tRWDR = RL + tDQSCKmax + BL/2 - (WL -
RW
2).
• DDR3L Equation: tRWDR = CL + tDQSCKmax + BL/2 + tRPST
- (CWL + tDQSSmin - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be adjusted by tODTon.
Note: For DDR3L using ODT, this latency may need to be increased by one clock.

Write to Write DQ Delay Different Ranks (TWWDR): Specifies the delay from
the start of a Write data burst of one rank to the start of a Write data burst of a
different rank (in DRAM clocks).
• LPDDR3 Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin
5h + tWPRE.
11:6
RW
• LPDDR4 Equation: tWWDR = BL/2 + 4 - tDQSSmin.
• DDR3L Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin +
tWPRE.
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.

Read to Read DQ Delay Different Ranks (TRRDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Read data burst of a different
rank (in DRAM clocks).

5:0
9h • LPDDR3/4 Equation: tRRDR = BL/2 + tDQSCKmax -
RW tDQSCKmin + tRPRE.
• DDR3L Equation: tRRDR = BL/2 + tRPST + tDQSCKmax -
tDQSCKmin + tRPRE + 1.

5.3.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 121Ch

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

334818 105
 MCHBAR

Default: 304200C2h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0

TDERATE_INC
RSVD26

TWWSR

TRRSR

TWRSR

TRWSR
TRRD

Bit Default &

Field Name (ID): Description
Range Access

Row Activation to Row Activation Delay [tRRD] (TRRD):

Specifies the minimum delay in DRAM clocks between two DRAM
6h
31:27 Activate commands to the same rank but different banks (tRC is
RW
the minimum delay between activations of the same bank).
Note: Derating adds 1.875ns to this timing.

26
0h Reserved (RSVD26): Reserved.
RO

Derate Increment (TDERATE_INC): Specifies the additional

delay that is added to DRAM timing when indicated by MR4 status.
0h (in DRAM clocks)
25:23
RW LPDDR3/LPDDR4: Value is 1.875ns.
Note: The value in this register is only added to these timing
parameters: tRCD, tRAS, tRP and tRRD.
Write to Write DQ Delay Same Rank (TWWSR): Specifies the
10h delay from a DRAM Write to another Write command of the same
22:18
RW rank (in DRAM clocks).
LPDDR3/LPDDR4/DDR3L Equation: tRRSR = tCCD.
Read to Read DQ Delay Same Rank (TRRSR): Specifies the
10h delay from a DRAM Read to another Read command of the same
17:13
RW rank (in DRAM clocks).
LPDDR3/LPDDR4/DDR3L Equation: tRRSR = tCCD.
Write to Read DQ Delay Same Rank (TWRSR): Specifies the delay from a DRAM
Read to Write command of the same rank (in DRAM clocks).

3h • LPDDR3/LPDDR4 Equation: tWRSR = WL + tDQSSmax + BL/2

12:6 + tWTR.
RW
• DDR3L Equation: tWRSR = CWL + tDQSSmax + BL/2 +
tWPST + tWTR.
Read to Write DQ Delay Same Rank (TRWSR): Specifies the delay from a DRAM
Read to a Write command of the same rank (in DRAM clocks).
• LPDDR3/LPDDR4 Equation: tRWSR = RL + tDQSCKmax + BL/
2h 2 - WL + tWPRE.
5:0
RW
• DDR3L Equation: tRWSR = CL + tDQSCKmax + BL/2 + tRPST
- (CWL +tDQSSmin - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Note: For DDR3L using ODT, this latency may need to be increased by one clock.

106 334818
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5.3.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1220h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 20100000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD7
TPSTMRRBLK
OREFDLY

TCKCKEL

MNTDLY

TPREMRBLK
Bit Default &
Field Name (ID): Description
Range Access

20h Opportunistic Refresh Idle Timer (OREFDLY): Rank idle

31:24
RW period that defines an opportunity for refresh (in DRAM clocks).
Valid Clocks After CKE Low [tCKELCK/tCKELCS/tCPDED/tCKSRE]
(TCKCKEL): Specifies the amount of time that DRAM clocks need to toggle after CKE
goes low (in DRAM Clocks).
• For LPDDR3, this covers tCPDED.
2h
23:19
RW • For LPDDR4, this covers both tCKELCK and tCKELCS.
• For DDR3L, this is tCKSRE.
Note: D-Unit hardware enforces minimum of one SPID clocks after CKEL, any value in
this register is the additional time.

Maintenance Operation Delay (MNTDLY): When a critical read

request is pending in RPQ and a maintenance operation (MRR,
0h ZQCal, Ref, etc, panic refresh is an exception to this delay.) needs
18:15
RW to be performed, D-Unit waits this amount of time before
performing the maintenance operation to allow for some high
priority requests to be issued (in 4x SPID clocks).
Mode Register Read to Any Command Delay
(TPSTMRRBLK): Specifies the quiet time after issuing MRR
command (in DRAM Clocks).
0h
14:8 Note: D-Unit treats MRR as a read and always applies relevant
RW
turnaround times, any value programmed in this CR must be
greater than those turnaround times for D-Unit to enforce any
additional time from MRR to the next read/write.

7
0h Reserved (RSVD7): Reserved.
RO

334818 107
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Any Command to Mode Register Read/Write Delay

(TPREMRBLK): Specifies the quiet time before issuing MRR/MRW
command. (in DRAM clocks).
0h
6:0 Note: D-Unit treats MRR as a read and always applies relevant
RW
turnaround times, any value programmed in this CR must be
greater than those turnaround times for D-Unit to enforce any
additional time from previous read/writes.

5.3.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1224h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: D060C06h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0

RSVD8_7
TRDPDEN
TWRPDEN
TRPAB

TPSTMRWBLK

TRAS
Bit Default &
Field Name (ID): Description
Range Access

All Bank Precharge to Activate Command Delay [tRPab] (TRPAB): Specifies

the delay between a DRAM Precharge All Bank command and a DRAM Activate
command (in DRAM Clocks). Note: This CR should be constrained to a minimum of 4
3h in LP3 and minimum of 8 in LP4. Note: Derating adds 1.875ns to this timing.
31:26
RW
• For LPDDR, tRPpb = tRP, tRPab = tRP + 3ns.
• For DDR3L 8ch tRPpb = tRPab = tRP.
Mode Register Write to any Command Delay [tMRD/tMRW]
2h (TPSTMRWBLK): Specifies the quiet time after issuing MRW
25:23
RW command (in 8 x DRAM clocks).
Note: This time covers for both tMRD and tMRW.
Write Command to Power Down Delay [tWRPDEN]
6h (TWRPDEN): Specifies the minimum time between a write
22:16
RW command to PowerDown command (in DRAM clocks).
Must be at least equal to tWR + tCCD + tWL + 2.
Read Command to Power Down Delay [tRDPDEN]
6h (TRDPDEN): Specifies the minimum time between a read
15:9
RW command to PowerDown command (in DRAM clocks).
Must be at least equal to CL/RL + tDQSCKmax + tCCD + tRPST.

108 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

8:7
0h Reserved (RSVD8_7): Reserved.
RO

Row Activation Period [tRAS] (TRAS): Specifies the minimum

6h delay between the DRAM Activate and Precharge commands to
6:0
RW the same bank (in DRAM clocks).
Note: Derating adds 1.875ns to this timing.

5.3.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1228h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: CC50A18h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0
TCKESR

LPMDRES

LPMDTOCKEDLY

PWDDLY
CKETOLPMDDLY

Bit Default &

Field Name (ID): Description
Range Access

Minimum Self-Refresh Time [tSR/tCKESR] (TCKESR):

3h
31:26 Specifies the minimum time that DRAM should remain in SR (in
RW
DRAM clocks).
Minimum Low Power Mode Residency (LPMDRES): Specifies
6h
25:21 the minimum time that PHY should remain in LPMode (in DRAM
RW
clocks).
Low Power Mode Exit to Clock Enable Delay
(LPMDTOCKEDLY): Specifies the minimum time between the LP
Ah
20:15 Mode exit to the CK stop/tristate deassertion and powerdown exit
RW
(in DRAM clocks).
Note: Must be equal to t_idle_latency and less than 0x3C.
Clock Stop to Low Power Mode Delay (CKETOLPMDDLY):
Specifies the time between CK stop/tristate to the Low Power
Ah Mode entry. This timing parameter is used to delay Low Power
14:8
RW Mode entry (in DRAM clocks).
Note: Must be at least equal to t_idle_length parameter and less
than 0x7C.

334818 109
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Power Down Idle Timer (PWDDLY): This is a non-JEDEC

18h
7:0 timing parameter used to delay powerdown entry (in DRAM
RW
clocks).

5.3.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset

122Ch
Specifies the parameters to control DRAM ODT.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDODTSTART

WRODTSTART
RDODTSTOP

WRODTSTOP

RSVD4
RSVD31_30

R1WRODTCTL

R0WRODTCTL

RSVD23_18

RSVD13
R1RDODTCTL
R0RDODTCTL

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

Rank 1 Read ODT Control (R1RDODTCTL): Specifies the

behavior of ODT signals when a Read command is issued to Rank
0h 1.
29
RW 0 - Read ODT is disabled for Rank 1
1 - Assert ODT to for Rank 0 (non-targeted Rank)
Note: This register should be set to 0 for LPDDR3 devices
Rank 0 Read ODT Control (R0RDODTCTL): Specifies the
behavior of ODT signals when a Read command is issued to Rank
0h 0.
28
RW 0 - Read ODT is disabled for Rank 0
1 - Assert ODT to for Rank 1 (non-targeted Rank)
Note: This register is reserved for LPDDR3 devices
Rank 1 Write ODT Control (R1WRODTCTL): Specifies the
behavior of ODT signals when a Write command is issued to Rank
1.
0h 00 - Write ODT is disabled
27:26
RW 01 - Assert ODT to Rank 0 (non-targeted Rank)
10 - Assert ODT to Rank 1 (targeted Rank)
11 - Assert ODT to Rank 0 and Rank 1
Note: 10 and 11 are reserved values for LPDDR3

110 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Rank 0 Write ODT Control (R0WRODTCTL): Specifies the

behavior of ODT signals when a Write command is issued to Rank
0.
0h 00 - Write ODT is disabled
25:24
RW 01 - Assert ODT to Rank 0 (targeted Rank)
10 - Assert ODT to Rank 1 (non-targeted Rank)
11 - Assert ODT to Rank 0 and Rank 1
Note: 10 and 11 are reserved values for LPDDR3

23:18
0h Reserved (RSVD23_18): Reserved.
RO

Read ODT assertion to de-assertion delay (DDR3L Only)

(RDODTSTOP): Specifies Read ODT assertion to ODT de-assert
0h
17:14 delay (in DRAM clocks).
RW
DDR3L Equation: RDODTSTOP = DOCRx.WRODTSTOP (subtract 1
if DOCRx.WRODTSTART = 1 in 2N mode).

13
0h Reserved (RSVD13): Reserved.
RO

Read command to ODT assertion delay (DDR3L Only)

(RDODTSTART): Specifies Read ODT assertion delay after Read
0h Command (in DRAM clocks).
12:9
RW DDR3L Equation: RDODTSTART = CL CWL (add 1 if
DOCRx.WRODTSTART = 0 in 2N mode).
The max value for this CR is 0xE
Write ODT Assertion to De-assertion Delay (WRODTSTOP):
Specifies number of clocks after ODT assertion that D-Unit
0h deasserts ODT signal (in DRAM clocks).
8:5
RW LPDDR3 Equation: WRODTSTOP = RU(tODTon(max)/tCK) +
RU((tDQSSmax+tWPST)/tCK) + BL/2 - RD(tODToffmin/tCK)
DDR3L Equation: WRODTSTOP >= 6

4
0h Reserved (RSVD4): Reserved.
RO

Write command to ODT assertion delay (WRODTSTART):

Specifies number of clocks after Write command that D-Unit
asserts ODT signal (in DRAM clocks).
LPDDR3 Equation: WRODTSTART = WL - RU(tODTon(max)/tCK)
0h DDR3L Equation: WRODTSTART = 0 Note: DDR3 spec requires
3:0
RW ODT to be asserted high when the DRAM Write command is
issued. In DDR3L 2N mode the value can be set to 0 to assert ODT
one DRAM clock earlier than the Write Command (WR) or set to 1
to assert at the same clock as command (CS assertion).
The max value for this CR is 0xE

5.3.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—

Offset 1230h
Specifies the parameters to control D-Unit power management features.

Access Method

334818 111
 MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SREDLY
SUSPMOP
RSVD31_29

DYNPMOP
RSVD23
SRPMCLKW

DYNSREN
Bit Default &
Field Name (ID): Description
Range Access

31:29
0h Reserved (RSVD31_29): Reserved.
RO

SUSPEND/SUSPENDP Power Management Message Opcode

(SUSPMOP): DDRIO PHY Power Mode Opcode: After the D-Unit
has placed the DRAM devices in Self Refresh/PASR mode as the
result of a SUSPEND/SUSPENDP message, it sends this 5-bit value
0h
28:24 to the DDRIO PHY to tell it which power saving mode it should
RW
enter.
Changing this register value while in SUSPEND will have no effect.
Note: This opcode cannot be a PM state where it disables PHY PLLs
i.e PM7 in LPDDR PHY.

23
0h Reserved (RSVD23): Reserved.
RO

PM Message Wait for Clock Gate Enable (SRPMCLKW): Specifies when it is safe
to send PM message to the PHY. When enabled, D-Unit waits for SPID Clock to
deassert before sending a PM message on SR entry.

0h • 0: D-Unit will not wait for SPID_clk to deassert before sending

22
RW the PM message to PHY.
• 1: D-Unit will wait for SPID_clk to deassert before sending PM
message to the PHY.
Note: The value must be 1 when DYNPMOP = 7h.

Dynamic Self-Refresh Power Management Message Opcode

(DYNPMOP): DDRIO PHY Power Mode Opcode: After the D-Unit
has placed the DRAM devices in Self Refresh mode as the result of
0h
21:17 a Dynamic Self-Refresh, it sends this 5bit value to the DDRIO PHY
RW
to tell it which power saving mode it should enter.
Changing this register value while in self-refresh will only change
the PM state for the next entry in DynSR.
Dynamic Self-Refresh Enable (DYNSREN): When set to 1, the
D-Unit will automatically control DRAM Self Refresh entry and exit
based on interface state and requests in pending queues. When
0h
16 there is no pending request in the queues and PMI is idle, then the
RW
D-Unit will place the DRAM devices in Self Refresh mode. The
DRAM devices will be brought out of Self-Refresh when idle
conditions don't hold.

112 334818
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Bit Default &

Field Name (ID): Description
Range Access

Self-Refresh Entry Delay (SREDLY): Specifies the minimum

0h
15:0 time the D-Unit will wait before it enters Dynamic Self-Refresh
RW
mode when idle (in 16x DRAM Clocks).

5.3.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—

Offset 1234h
Specifies the parameters to control D-Unit power management features.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10000028h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
CSTRIST

CMDTRIST

PCLSTO

ODTTRIST
RPTCLKGTDIS

CLKGTDIS

PCLSTODIS
SBEPCLKGTDIS

LPMODEOP
RSVD31_30

RSVD6

ENCKSTP

DISPWRDN
PASR

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

D-Unit Repeaters Clock Gate Disable (RPTCLKGTDIS):

Setting this bit to 0 allows majority of the repeaters between D-
Unit and PHY to clock gate when there is no activity in order to
save power.
0h 0 - Enable Repeaters clock gating, 1 - Disable Repeaters clock
29
RW gating.
Note: This is a de-feature bit and should be set to 0 for normal
operation.
Note: The value should only change after DRAM Timing Registers
(DTR) are programmed.
IOSF-SB End Point Clock Gate Disable (SBEPCLKGTDIS):
Setting this bit to 0 enables the clock gating of IOSF-SB End
Points in D-Unit and CPGC when there is no IOSF-SB activity in
order to save power.
1h 0 - Enable IOSF-SB EP clock gating, 1 - Disable IOSF-SB clock
28
RW gating.
Note: This is a de-feature bit and should be set to 0 for normal
operation.
Note: The value should only change after DRAM Timing Registers
(DTR) are programmed.

334818 113
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Local Clock Gate Disable (CLKGTDIS): Setting this bit to 0 allows the majority of
the D-Unit clocks to be gated off when there is no activity in order to save power.
When set to 1, D-Unit clockgating is disabled.
0h • 0: Enable.
27
RW
• 1: Disable.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.

Chip Select Tristate Enable (CSTRIST):

• 0: The DRAM CS pins associated with the enabled ranks are
0h never tristated.
26
RW
• 1: The DRAM CS pins are tristated when DRAM clock is
stopped or tristated.
Note: CS is not tristated when global tristate flow is disabled (DCBR.TRISTDIS = 1).

Command/Address Tristate (CMDTRIST):

• 00: The DRAM CA pins are never tristated.
• 01: The DRAM CA pins are only tristated when all enabled CKE
0h
25:24 pins are low.
RW
• 10: The DRAM CA pins are tristated when not driving a valid
command.
• 11: Reserved
Partial Array Self-Refresh Segment Mask (PASR): This is the
0h
23:16 Segment Mask used for the MRW to enable PASR during
RW
SUSPENDP (Partial Array Self Refresh entry).
Page Close Timeout Period (PCLSTO): Specifies the time from
0h the last access of a DRAM page until that page is scheduled to
15:8
RW close by sending a Precharge command to DRAM (in 16 x DRAM
clocks).
Page Close Timeout Disable (PCLSTODIS): When disabled, D-Unit will not close
the DRAM page when idle.
0h • 0: Enable page close timer.
7
RW
• 1: Disable page close timer (Used during DRAM init and
DDRIO training).

6
0h Reserved (RSVD6): Reserved.
RO

ODT Tristate Enable (ODTTRIST):

• 0: The DRAM ODT pins associated with the enabled ranks are
1h never tristated.
5
RW
• 1: DRAMs ODT pins are tristated when DRAM clock is stopped
or tristated.
Note: ODT is not tristated when global tristate flow is disabled (DCBR.TRISTDIS = 1)

114 334818
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Bit Default &

Field Name (ID): Description
Range Access

Clock Stop/Tristate Enable (ENCKSTP): Enable/Disable CK Stop/Tristate During

Power down.
• 00: Disable CK Stop/Tristate During Power down.
1h • 01: Enable CK Stop During Power down.
4:3
RW
• 10: Enable CK Tristate During Power down.
• 11: Reserved
Note: CK is not stopped or tristated when global tristate flow is disabled
(DCBR.TRISTDIS = 1).

Low Power Mode Opcode (LPMODEOP): D-Unit will send the

value in this register after it has entered Powerdown Mode and has
0h stopped/tristated the clock.
2:1
RW 00: Disable LPMode.
Note: LPMODE entry is not possible when global tristate flow is
disabled (DCBR.TRISTDIS = 1).
Disable Power Down (DISPWRDN): Setting this bit to 1 disables dynamic control
of DRAM Power-Down entry and exit by keeping the CKE pins driven high. BIOS may
set it to 1 during DRAM initialization and DDRIO training. This bit should be set to 0
for normal operation.
• 0: The D-Unit dynamically controls the CKE pins to place the
0h DRAM devices in Power Down mode and bring them out of
0
RW Power Down mode.
• 1: The D-Unit constantly drives the CKE pins high to keep the
DRAM devices from entering Power Down mode when ranks
are idle.
Note: This bit is overridden if CKEMODE = 1. This bit does not control CKE behavior
on SR entry/exit.

5.3.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1238h

Specifies the parameters to control scheduling of refresh commands.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1750h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 0
DISREFDBTCLR
REFSKWDIS

EXTRAREFDBT

MINREFRATE

OREFDIS
RSVD31_22

RSVD19_18

RSVD17_16

REFWMPNC

REFWMHI

RSVD3_1

334818 115
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

31:22
0h Reserved (RSVD31_22): Reserved.
RO

Disable Refresh Debt Clear (DISREFDBTCLR): When set, D-Unit will not clear
refresh debt before Self Refresh SR Entry:

0h • 0: D-Unit sends all postponed REF commands to DRAM before

21 it enters Self Refresh.
RW
• 1: D-Unit enters SR without clearing the Refresh Debt (for
Debug only).
Refresh Skew Disable (REFSKWDIS): Disables Skewing of Refresh Counting
between Ranks. Each rank has its own refresh counter. By default incrementing these
refresh counters are skewed by 1/2 the tREFI period. Setting this bit to a 1 disables
this feature and all refresh counters will increment at the same time per tREFI period.
Skewing the tREFI counters can improve performance since traffic to all ranks does
not have to be blocked to perform refresh.
0h
20
RW • 0: Incrementing the refresh counters are skewed by 1/2 tREFI
period.
• 1: All refresh counters will increment at the same time per
tREFI period.

19:18
0h Reserved (RSVD19_18): Reserved.
RO

17:16
0h Reserved (RSVD17_16): Reserved.
RO

Extra Refresh Debit (EXTRAREFDBT): When set to 1, D-Unit

0h
15 adds one extra refresh debit (for a total of two) on Self-refresh
RW
exit.
Minimum Refresh Rate (MINREFRATE): Ensures that refresh rate never drops
below a certain limit regardless of TQ polling.
• 000: Disable tREFI counter and stop issuing refresh
commands.
• 001: 0.25x refresh rate (i.e. 4x tREFI same as no limit).
1h • 010: 0.5x refresh rate (i.e. 2x tREFI).
14:12
RW • 011: 1x refresh rate (i.e. 1x tREFI).
• 100: 2x refresh rate (i.e. 0.5x tREFI).
• 101: 4x refresh rate (i.e. 0.25x tREFI).
• 110: 4x refresh rate with derating forced on i.e. 0.25x tREFI.
• 111: Reserved.
Refresh Panic Watermark (REFWMPNC): When the Refresh
counter per rank is greater than this value, the D-Unit will send a
7h REF command to the rank regardless of pending requests.
11:8
RW Note: REFWMPNC must be greater than or equal to REFWMHI and
greater than 2, Max Value must be less than 8 to not violate
9xtREFI JEDEC requirement.

116 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Refresh High Watermark (REFWMHI): When the Refresh

counter per rank is greater than this value, the D-Unit will send a
5h REF command to the rank if there is no critical priority requests in
7:4
RW the pending queues.
Note: Value must be greater or equal to 1 and less than or equal
to REFWMPNC.

3:1
0h Reserved (RSVD3_1): Reserved.
RO

Opportunistic Refresh Disable (OREFDIS): Disable opportunistic scheduling of

refresh.
• 0: D-Unit will send a REF command only if there is no pending
0h request to that rank.
0
RW • 1: D-Unit will not send any opportunistic refreshes. Refresh
commands are only sent when the refresh counter is greater
than REFWMHI.
Note: When set, DISREFDBTCLR must also be set to be able to enter SR.

5.3.15 D-Unit Scheduler (D_CR_DSCH)—Offset 123Ch

Specifies parameters to control scheduling of commands to DRAM.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 3901C08h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0
WPQCOUNT

RPQCOUNT

BLKRDBF_ADD_RDDATA_CR

INORDERMODE

TMWR_TA_DELTA
BGF_EARLY_RDDATA_VALID

SPID_EARLY_RDDATA_VALID

RSVD15_14
RSVD31

BYPASSEN
BLKRDBF

STRETCHMODE

Bit Default &

Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

334818 117
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

BGF Early Read Data Valid (BGF_EARLY_RDDATA_VALID): Specifies the

number of clocks the D-Unit sends the read data valid through the BGF earlier as
compared to the data.

0h • 00: Always write read valid in same SPID clock as data.

30:29
RW • 01: Always write read valid one SPID clock before data.
• 10: Write read valid up to 2 SPID clocks before data.
• 11: Reserved
SPID Early Read Data Valid
0h (SPID_EARLY_RDDATA_VALID): Specifies the delay in SPID
28:27
RW clocks from RDDATA_VALID assertion to actual data on SPID. The
value should match what is programmed in DDRIO (PHY).
Write Pending Queue Count (WPQCOUNT): Used to limit the
1Ch number of available slots in Write Pending Queue/ Write Data
26:21
RW Buffer. WPQCOUNT will only recognize changes when PMI ISM is
not active.
Read Pending Queue Count (RPQCOUNT): Used to limit the
10h
20:16 number of entries in Read Pending Queue. RPQCOUNT will only
RW
recognize changes when PMI ISM is not active.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

Read Return Data Additional Credits

(BLKRDBF_ADD_RDDATA_CR): Number of additional full
7h cacheline (64B) read data return credits exposed to D-Unit when
13:10
RW BLKRDBF is set.
Note: The value in this field has no effect on Read return credits
when BLKRDBF is not set.
In-Order Mode (INORDERMODE):
• 0h: In order mode disabled: Commands are sent out of order.
• 1h: Partial in order mode: Read and Write CAS commands are
sent in the order they were recieved. ACT and PRE can go out
of order.
0h
9:8
RW • 2h: Full in order mode serialized test: All DRAM commands
CAS ACT PRE associated with a PMI request are issued to DDR
before any DRAM commands for a subsequent PMI request.
• 3h: Reserved.
In order modes should be enabled during init/training/CPGC testing. Should never be
changed while the D-Unit queues are nonempty.

7
0h Idle Bypass Mode Enable (BYPASSEN): Reserved.
RW

Block When RDB Full (BLKRDBF): When set D-Unit stops

0h
6 scheduling new read commands to DRAM when the read data
RW
buffer (RDB) is full.

118 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Stretch Mode (STRETCHMODE): When stretch mode is enabled, commands are

initiated only on Phase 0 of SPIDClk.
• 00: Stretch mode is disabled.
0h
5:4 • 01: Commands are initiated on Phase 0 of every SPID clocks.
RW
• 10: Commands are initiated on Phase 0 of even SPID clocks.
• 11: Commands are initiated on Phase 0 of odd SPID clocks.
Masked Write Turnaround Delta (TMWR_TA_DELTA): The value in this register
8h is subtracted from Masked Write to Read, Masked Write to Write and Masked Write to
3:0 Masked Write turnaround times to account for half BL MWr commands in LPDDR4.
RW
• LPDDR4: = MWr tCCD = MWr BL/2 = 8.

5.3.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1240h

Specifies parameters to control ZQ Calibration.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1057h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1
ZQCALSTRTR1
ZQCALSTRTR0

RSVD28_23

SRXZQC

RSVD20_18

RSVD15_14
ZQCALTYPE

ZQCLMODE
ZQCDIS

ZQINT

Bit Default &

Field Name (ID): Description
Range Access

ZQ Calibration Type (ZQCALTYPE): Determines whether the

ZQ Calibration is a long or short calibration command (due to
0h
31 ZQCALSTRT).
RW
0: Short calibration (ZQCS).
1: Long calibration (ZQCL).
ZQ Calibration Start Rank 1 (ZQCALSTRTR1): Set this bit to 1
to start the ZQ calibration sequence on Rank 1. This bit will remain
0h a 1 until the ZQ calibration is complete for rank 1, then it will
30
RW/V return to 0.
0: ZQ calibration is done.
1: ZQ calibration has started and is in progress.

334818 119
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

ZQ Calibration Start Rank 0 (ZQCALSTRTR0): Set this bit to 1

to start the ZQ calibration sequence on Rank 0. This bit will remain
0h a 1 until the ZQ calibration is complete for rank 0, then it will
29
RW/V return to 0.
0: ZQ calibration is done.
1: ZQ calibration has started and is in progress.

28:23
0h Reserved (RSVD28_23): Reserved.
RO

Self-Refresh Exit ZQ Calibration Control (SRXZQC):

• 00: On DynSR exit ZQ timer determines the ZQ type. When
the state is lost (i.e due to AutoPG/S0ix) ZQCL is always
performed.
0h • 01: Always perform ZQCL after self refresh exit, in LPDDR4,
22:21
RW ZQ with traffic blocked.
• 10: Always perform ZQCS on SR exit. For LPDDR4, ZQ while
traffic is allowed.
• 11: No ZQCL commands are sent (it disables ZQCAL
commands on SR exit).

20:18
0h Reserved (RSVD20_18): Reserved.
RO

ZQ Calibration Mode (ZQCLMODE): Specifies how ZQCal commands are sent to

different ranks.
0h
17 • 0: ZQCal commands are sent in parallel to all ranks.
RW
• 1: ZQCal commands are sent serially to each rank.
Periodic ZQ Calibration Disable (ZQCDIS):
0h
16 • 0: Periodic ZQ Calibration is Enabled.
RW
• 1: Disable periodic ZQ Calibration.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

ZQ Calibration Interval (ZQINT): Specifies the time interval

1057h
13:0 between two ZQCS (LPDDR3) or ZQ Start (LPDDR4) commands to
RW
a DRAM device. (in RTC 32.8KHz clocks)

5.3.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset

124Ch
Specifies parameters for VNN Scaling Timer in D-Unit. The values in this register will be
set by P-code during VNN scaling period.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

120 334818
MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD30_12
VNN_TIMER_EN

VNN_TIMER_TIME
Bit Default &
Field Name (ID): Description
Range Access

VNN Scaling Timer Enable (VNN_TIMER_EN):

0h
31 • 0: The D-Unit VNN Scaling Timer is disabled.
RW
• 1: The D-Unit VNN Scaling Timer is enabled.

30:12
0h Reserved (RSVD30_12): Reserved.
RO

0h VNN Timer Time (VNN_TIMER_TIME): The final timer value

11:0
RW (in 16 x DRAM clocks).

5.3.18 Periodic DRAM Temperature Polling Control (TQ)

(D_CR_TQCTL)—Offset 1250h
Specifies the control for periodic temperature monitoring and control of DRAM device.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 6C000008h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
TQDATAR1

TQDATAR0

RSVD25_22

RSVD7_5
TQPOLLPER

ENDERATE
SRTEN

TQDATAPUSHEN

TQPOLLEN
TQPOLLSREN

Bit Default &

Field Name (ID): Description
Range Access

TQ Data Rank 1 (TQDATAR1): If Rank 1 is disabled, this value

3h will remain zero.
31:29
RW/V This field contains the data of the last DRAM Mode Register Read
to MR4 MRR issued. It is overwritten with each command.

334818 121
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

TQ Data Rank 0 (TQDATAR0): This field contains the data of

3h
28:26 the last DRAM Mode Register Read to MR4 MRR issued. It is
RW/V
overwritten with each command.

25:22
0h Reserved (RSVD25_22): Reserved.
RO

TQ Poll Period (TQPOLLPER): This sets the frequency by which

0h
21:8 the D-Unit polls the DRAM mode register MR4 to determine
RW
required refresh rate (in 4x tREFI units).

7:5
0h Reserved (RSVD7_5): Reserved.
RO

Self Refresh Temperature Range Enable (DDR3 Only)

(SRTEN): When set, before every Self refresh entry, D-Unit
0h writes a 1 to bit 7 of TQOFFSET.MR_VALUE when TQDATA for that
4
RW rank indicates a value higher then 0x3, and writes a 0 to that bit
otherwise. The new MR_VALUE is then written into MR2 of DDR3
for each enabled rank.
Enable Dynamic Timing Derating (ENDERATE): When set to
1, the Dynamic Timing Derating is enabled. When the D-Unit
1h
3 determines (via TQ polling) that the DRAM requires timing
RW
derating in addition to refresh interval adjustment, the D-Unit will
automatically adjust the relevant timing parameters.
0h Enable TQ Data Push (TQDATAPUSHEN): When set to 1, D-
2
RW Unit pushes the data form the last MR4 read to a punit register.
Enable TQ Poll on Self-Refresh Exit (TQPOLLSREN): This bit
0h
1 enables MR4 read on Self Refresh Exit. If disabled, D-Unit will not
RW
read MR4 value on Self-Refresh exit.
Enable Periodic TQ Poll (TQPOLLEN): This bit enables periodic
0h
0 TQ Poll. If disabled, D-Unit will not read MR4 value periodically.
RW
Note: Will be enabled only if refreshes are enabled.

5.3.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset

1254h
Specifies temperature offset and refresh rate adjustments requested by software.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

122 334818
MCHBAR

MR_VALUE

MR3_OFFSET_UPDATE
RSVD31_26

RSVD15_11

MR4_ADDER

RSVD7_3

MR3_THERM_OFFSET
Bit Default &
Field Name (ID): Description
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

MR Value (MR_VALUE):
MR2 Shadow Register (DDR3L Only):
0h
25:16 BIOS writes the correct value of MR2 register in DDR3L into this
RW
field at boot time. D-Unit modifies one bit and rewrites the MR2
into DDR3L DRAM before SR entry.

15:11
0h Reserved (RSVD15_11): Reserved
RO

MR4 Adder (MR4_ADDER): D-Unit adds the value of this field to

0h
10:8 TQDATA read from MR4 the resulting value is used to control
RW
refresh rate and AC timing derating.

7:3
0h Reserved (RSVD7_3): Reserved.
RO

MR3 Offset Update (MR3_OFFSET_UPDATE): When set, D-

0h Unit writes the merged value of MR3_VALUE and
2
RW/V MR3_THERM_OFFSET into MR3 of DRAM. D-Unit clears this bit
once the value is written.

1:0
0h MR3 Thermal Offset (MR3_THERM_OFFSET): Reserved
RW

5.3.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 12A4h

Specifies parameters to control data scrambling in D-Unit.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CLOCKGATE

KEY
RSVD30

RSVD27_16
SCRM_EN

334818 123
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Enable Data Scrambler (SCRM_EN): When set to 1, data

0h
31 scrambling is enabled. When set to 0, data scrambling is disabled.
RW
Should be set before D_CR_BGF_CTL_BGF_RUN is set to 1.

30
0h Reserved (RSVD30): Reserved.
RO

Scrambler Clock Gate Select (CLOCKGATE): This field controls how the scrambler
output code is clock gated to reduce power.
• 00: Clock gate disabled.
0h
29:28 • 01: Clock Gate every 2 cycle.
RW
• 10: Clock Gate every 3 cycle.
• 11: Clock Gate every 4 cycle.

27:16
0h Reserved (RSVD27_16): Reserved.
RO

0h Scrambling Key (KEY): Sets the key for the scrambler. The key
15:0
RW should be a random value that is set following each cold boot.

5.3.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset

12ACh
Contains the target address for ECC error injection.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADDRESS
RSVD31

RSVD0

Bit Default &

Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

Error Injection Target Address (ADDRESS): Specifies the PMI

0h address of the write transaction to be injected with the error. Only
30:1
RW applicable to Write transactions. Read/under-fill read of the partial
write operation is not affected.

0
0h Reserved (RSVD0): Reserved.
RO

124 334818
MCHBAR

5.3.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—

Offset 12B0h
Controls injecting correctable or uncorrectable errors into the write requests specified
by target address.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD31_4

SEL_HI
EN_HI
SEL_LO
EN_LO
Bit Default &
Field Name (ID): Description
Range Access

31:4
0h Reserved (RSVD31_4): Reserved
RO

Error Injection Type Higher 32B (SEL_HI): If enabled, the error injection is
continuously armed for ERR_INJ.ADDR 32B write address matching until it is cleared.
• 00: No error injection.
• 01: Uncorrectable Error (UE) is armed for write address
matching to inject UE by using the same poisoning scheme,
0h i.e. inverting corresponding write ECC[6:0] on QW0 of the 32B
3
RW data.
• 10: Correctable Error (CE) is armed for write address
matching to inject CE by inverting corresponding write ECC[0]
on QW0 of the 32B data.
• 11: Reserved.
Error Injection Enable Higher 32B (EN_HI): When set the
0h
2 error injection is continuously armed for higher 32B of
RW
D_CR_ERR_INJ_ADDR write address matching until it is cleared.
Error Injection Type Lower 32B (SEL_LO): 0 - Uncorrectable
Error (UE) is armed for write address matching to inject UE by
using the same poisoning scheme, i.e. inverting corresponding
0h
1 write ECC[6:0] on every QW of the 32B data.
RW
1 - Correctable Error (CE) is armed for write address matching to
inject CE by inverting corresponding write ECC[0] on every QW of
the 32B data.
Error Injection Enable Lower 32B (EN_LO): When set, the
0h
0 error injection is continuously armed for lower 32B of
RW
D_CR_ERR_INJ_ADDR write address matching until it is cleared.

334818 125
 MCHBAR

5.3.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 12B4h

Detected ECC errors are captured in this register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYNDROME_QW

TAG
CLEAR

CERR
MERR
ECC_VISA

ERR_BURST

ERR_CHUNK

Bit Default &

Field Name (ID): Description
Range Access

0h Clear (CLEAR): Setting this bit to one clears all fields in this
31
RW/V register, including itself.
PMI VISA Byte Select (ECC_VISA): Select ECC or PMI byte on VISA :
• 00: ECC byte,
0h
30:29 • 01: PMI Data Byte [7:0],
RW
• 10: PMI Data Byte [63:56],
• 11: PMI Data Byte [255:248]
Correctable Single-bit Error (CERR): This bit is set when a
correctable single-bit error occurs on a memory read data
transfer. When this bit is set, the address that caused the error
0h
28 and the error syndrome are also logged and they are locked to
RW/V
further single bit errors, until this bit is cleared. A multiple bit
error that occurs after this bit is set will override the address/error
syndrome information.
Uncorrectable Multiple-bit Error (MERR): This bit is set when
an uncorrectable multiple-bit error occurs on a memory read data
0h
27 transfer. When this bit is set, the address that caused the error
RW/V
and the error syndrome are also logged and they are locked until
this bit is cleared.
0h Error Burst Number (ERR_BURST): Burst number (in BL8) of
26:25
RW/V the error within a chunk.
Error Chunk Number (ERR_CHUNK): Chunk number of the
0h error.
24
RW/V 0 - lower 32B chunk has error if MERR/CERR is set
1 - higher 32B chunk has the error if MERR/CERR is set

126 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h Quad Word ECC Syndrome (SYNDROME_QW): ECC Syndrome

23:16
RW/V for a QW (64 bit) within 32B Address
0h Request Tag (TAG): Read Return Tag matches with the PMI
15:0
RW/V Request Tag which triggered the error log.

5.3.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 12BCh

Contains the values read from D-Unit

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FUSESTAT
RSVD31_16

Bit Default &

Field Name (ID): Description
Range Access

31:16
0h Reserved (RSVD31_16): Reserved.
RO

D-Unit Status (FUSESTAT): D-Unit bits are captured into this register and are
available to be read.
• [0]: fus_dun_ecc_dis.
• [3:1]: fus_dun_max_supported_device_size[2:0].
0h • [4:4]: fus_dun_lpddr3_dis.
15:0
RO/V
• [5:5]: fus_dun_lpddr4_dis.
• [6:6]: reserved.
• [7:7]: fus_dun_ddr3l_dis.
• [15:8]: reserved.

5.3.25 Major Mode Control (D_CR_MMC)—Offset 1324h

Specifies parameters to control read/write major mode operation and transitions.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

334818 127
 MCHBAR

Default: 2B01E518h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0RSVD31_30 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0

RSVD22_18
RAW_WMM

RSVD26

WMMEXIT
RIMPRIO

WIMTHRS

WMMENTRY
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

RAW Conflict Read Priority for WMM Transition

(RAW_WMM): If a conflict read reaches this priority (or greater
depending on access class occupancy), WMM will be triggered to
5h
29:27 unblock the corresponding write. D-Unit will stay in WMM until
RW
corresponding write is issued.
Note: The value in this bit must not be higher than lowest terminal
priority level of each access class.

26
0h Reserved (RSVD26): Reserved.
RO

6h Read Isoch Trigger Priority (RIMPRIO): If any read in the

25:23
RW RPQ is at this programmable priority, RIM is triggered.

22:18
0h Reserved (RSVD22_18): Reserved.
RO

Write Isoch Threshold (WIMTHRS): When the number of

1Eh entries in WPQ is greater than or equal to this value (higher than
17:12
RW WMM entry watermark, less than WPQ size), it triggers write isoch
mode (WIM).
Write Major Mode Exit Watermark (WMMEXIT): When the
14h
11:6 number of entries in WPQ is less than this value, the D-Unit will
RW
switch back to read major mode.
Write Major Mode Entry Watermark (WMMENTRY): When
18h the number of entries in WPQ is greater than or equal to this
5:0
RW value, the D-Unit will switch to write major mode (WMM).
Note: the value must not be set to 0.

5.3.26 Major Mode RD/WR Counter (Set A and B)

(D_CR_MMRDWR_AB)—Offset 1328h
Minimum read and maximum write counter control. This register defines the minimum
number of reads in RMM and maximum number of writes in WMM before a mode
transition happens.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

128 334818
MCHBAR

Default: 1F207C8h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0

RSVD31_26

RSVD13_12
MINRDB
MAXWRB

MINRDA
MAXWRA
Bit Default &
Field Name (ID): Description
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

1Fh Max Writes B (MAXWRB): Maximum number of writes D-Unit

25:20
RW can send in WMM mode before returning to RMM (set B).
8h Min Reads B (MINRDB): Minimum number of reads that has to
19:14
RW be serviced before a switch to WMM is allowed (set B).

13:12
0h Reserved (RSVD13_12): Reserved.
RO

1Fh Max Writes A (MAXWRA): Maximum number of writes D-Unit

11:6
RW can send in WMM mode before returning to RMM (set A).
8h Min Reads A (MINRDA): Minimum number of reads that has to
5:0
RW be serviced before a switch to WMM is allowed (set A).

5.3.27 Major Mode RD/WR Counter (Set C and D)

(D_CR_MMRDWR_CD)—Offset 132Ch
Minimum read and maximum write counter control. This register defines the minumum
number of reads in RMM and maximum number of writes in WMM before a mode
transition happens (sets C and D).

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F207C8h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0
MINRDC
RSVD31_26

RSVD13_12

MAXWRC
MAXWRD

MINRDD

334818 129
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

1Fh Max Writes D (MAXWRD): Maximum number of writes D-Unit

25:20
RW can send in WMM mode before returning to RMM (set D).
8h Min Reads D (MINRDD): Minimum number of reads that has to
19:14
RW be serviced before a switch to WMM is allowed (set D).

13:12
0h Reserved (RSVD13_12): Reserved.
RO

1Fh Max Writes C (MAXWRC): Maximum number of writes D-Unit

11:6
RW can send in WMM mode before returning to RMM (set C).
8h Min Reads C (MINRDC): Minimum number of reads that has to
5:0
RW be serviced before a switch to WMM is allowed (set C).

5.3.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1330h

Each field of this register defines the initial priority of one access class.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 17C2h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 1 0
AC4IP

AC3IP

AC2IP

AC1IP

AC0IP
RSVD31_15

Bit Default &

Field Name (ID): Description
Range Access

31:15
0h Reserved (RSVD31_15): Reserved.
RO

1h Access Class 4 Initial Priority (AC4IP): Initial priority level of

14:12
RW read requests coming with access class 4.
3h Access Class 3 Initial Priority (AC3IP): Initial priority level of
11:9
RW read requests coming with access class 3.
7h Access Class 2 Initial Priority (AC2IP): Initial priority level of
8:6
RW read requests coming with access class 2.
0h Access Class 1 Initial Priority (AC1IP): Initial priority level of
5:3
RW read requests coming with access class 1.
2h Access Class 0 Initial Priority (AC0IP): Initial priority level of
2:0
RW read requests coming with access class 0.

130 334818
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5.3.29 Access Class 0 Priority Promotion Control

(D_CR_RD_PROM0)—Offset 1334h
This register defines the priority promotion policy for access class 0. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
next level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F52940h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0
P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
RSVD31_30

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.3.30 Access Class 1 Priority Promotion Control

(D_CR_RD_PROM1)—Offset 1338h
This register defines the priority promotion policy for access class 1. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
associated level and the request has reached its maximum priority.

Access Method

334818 131
 MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 14000000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

Ah Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.3.31 Access Class 2 Priority Promotion Control

(D_CR_RD_PROM2)—Offset 133Ch
This register defines the priority promotion policy for access class 2. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
next level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

132 334818
MCHBAR

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
RSVD31_30
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.3.32 Access Class 3 Priority Promotion Control

(D_CR_RD_PROM3)—Offset 1340h
This register defines the aging policy for access class 3. Each field of this register
defines the number of CASes that pass before the request is promoted to the next
priority level. A value of 31 indicates the request should never be promoted to the next
level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F29400h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

334818 133
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Bit Default &

Field Name (ID): Description
Range Access

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
5h Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
5h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.3.33 Access Class 4 Priority Promotion Control

(D_CR_RD_PROM4)—Offset 1344h
This register defines the aging policy for access class 3. Each field of this register
defines the number of CASes that pass before the request is promoted to the next
priority level. A value of 31 indicates the request should never be promoted to the next
level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F5294Ah

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.

134 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Ah Priority 3 Residency (P3RES): Number of CASes that pass

14:10
RW before a request in this priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
Ah Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.3.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1348h

Specifies when the request with initial priority 0 get promoted to a higher priority level.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 6h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

DEADLINE_THRS
RSVD31_11

Bit Default &

Field Name (ID): Description
Range Access

31:11
0h Reserved (RSVD31_11): Reserved.
RO

Deadline Threshold (DEADLINE_THRS): A requests with initial

priority of 0 will exit priority 0 when its deadline is equal or less
6h
10:0 than this value plus current time. This field does not affect the
RW
priority of any requests in access classes with initial priority bigger
than 0.

5.3.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—

Offset 134Ch
This register controls blocking rules enforced in RMM and WMM.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1800h

334818 135
 MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0

RSVD31_25

RSVD23_20

RSVD15_14
WMM_REG_R1

WMM_PRIO_R4
WMM_PRIO_R3
WMM_PRIO_R2
WMM_PRIO_R1

RMM_REG_R6
RMM_REG_R5
RMM_REG_R4
RMM_REG_R3
RMM_REG_R2
RMM_REG_R1

RSVD7_4

RMM_PRIO_R4
RMM_PRIO_R3
RMM_PRIO_R2
RMM_PRIO_R1
Bit Default &
Field Name (ID): Description
Range Access

31:25
0h Reserved (RSVD31_25): Reserved.
RO

0h WMM Regular Rule 1 (WMM_REG_R1): Disable WMM unsafe

24
RW write page hits block safe write page misses same bank.

23:20
0h Reserved (RSVD23_20): Reserved.
RO

WMM Priority Rule 4 (WMM_PRIO_R4): Disable WMM unsafe

priority 1 read miss block write hit to same bank.
0h
19 Note: This rule does not block the bank that is being blocked by
RW
WMM_PRIO_R3.
Priority rules 1, 3 and 4 should be enabled/disabled together.
WMM Priority Rule 3 (WMM_PRIO_R3): Disable WMM unsafe
priority 1 write hit block write miss to same bank.
0h
18 Note: This rule does not block the bank that is being blocked by
RW
WMM_PRIO_R1.
Priority rules 1,3 and 4 should be enabled/disabled together.
0h WMM Priority Rule 2 (WMM_PRIO_R2): Disable WMM CAS
17
RW block rule.
WMM Priority Rule 1 (WMM_PRIO_R1): Disable WMM unsafe
0h
16 top priority 1 write miss block write hit same bank.
RW
Priority rules 1, 3 and 4 should be enabled/disabled together.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

0h RMM Regular Rule 6 (RMM_REG_R6): Disable RMM unsafe

13
RW write page hits block safe write page misses same bank.
RMM Regular Rule 5 (RMM_REG_R5): Disable RMM unsafe
read page miss block all safe and unsafe write page hit to the
1h
12 same bank.
RW
Note: This field must not be set to 0 (enabled) if RMM_REG_R4 is
also 0.
RMM Regular Rule 4 (RMM_REG_R4): Disable RMM unsafe
1h write page hit block safe read page miss same bank.
11
RW Note: This field must not be set to 0 (enabled) if RMM_REG_R5 is
also 0.

136 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

RMM Regular Rule 3 (RMM_REG_R3): Disable RMM unsafe

0h read page hit block safe read and write page miss same bank.
10
RW Note: This rule does not block the bank that is being blocked by
RMM_PRIO_R3 and RMM_PRIO_R1.
0h RMM Regular Rule 2 (RMM_REG_R2): Disable RMM unsafe
9
RW read page empty block safe write page empty same rank.
0h RMM Regular Rule 1 (RMM_REG_R1): Disable RMM unsafe
8
RW read page hit block safe write page hit same rank.

7:4
0h Reserved (RSVD7_4): Reserved.
RO

RMM Priority Rule 4 (RMM_PRIO_R4): Disable RMM unsafe

critical read miss block read and write hit to same bank.
0h
3 Note: This rule does not block the bank that is being blocked by
RW
RMM_PRIO_R3.
Priority rules 1, 3 and 4 should be enabled/disabled together.
RMM Priority Rule 3 (RMM_PRIO_R3): Disable RMM unsafe
critical read hit block read and write miss to same bank.
0h
2 Note: This rule does not block the bank that is being blocked by
RW
RMM_PRIO_R1.
Priority rules 1, 3 and 4 should be enabled/disabled together.
0h RMM Priority Rule 2 (RMM_PRIO_R2): Disable RMM CAS block
1
RW rule.
RMM Priority Rule 1 (RMM_PRIO_R1): Disable RMM unsafe
0h top critical read miss block read and write hit same bank.
0
RW Note: Priority rules 1, 3 and 4 should be enabled/disabled
together.

5.3.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—

Offset 1354h
Self refresh command register to allow sending WAKE and SUSPEND messages to D-
Unit. (Only one bit can be set at a time). Posted writes to this register are not
completed until hardware clears the field.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SUSPEND

WAKE
RSVD31_4

SUSPENDP

RSVD1

334818 137
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

31:4
0h Reserved (RSVD31_4): Reserved.
RO

SUSPENDP (SUSPENDP): A SUSPENDP message will put the

DRAM into self-refresh mode. The D-Unit will complete servicing
outstanding memory requests and flush all queued Refresh
commands to DRAM before putting the DRAM in self refresh mode.
0h Finally, a PM message will be sent to the PHY. The bit is cleared by
3
RW/V hardware after the PHY indicates the transition requested in the
PM message has been completed. D-Unit will perform an MRW to
MR17 with an opcode as defined by DPMC0.PASR before it places
the DRAM into Self-Refresh.

SUSPEND (SUSPEND): A SUSPEND message will put the DRAM

into self-refresh mode. The D-Unit will complete servicing
outstanding memory requests and flush all queued Refresh
commands to DRAM before putting the DRAM in Self Refresh
0h
2 mode. Finally, a PM message will be sent to the PHY. The bit is
RW/V
cleared by hardware only after the PHY indicates the transition
requested in the PM message has been completed.
Note: When COLDWAKE is set prior of setting this bit the DRAM
will not be placed in SR.

1
0h Reserved (RSVD1): Reserved.
RO

WAKE (WAKE): Take PHY out of PM states and wakes the DRAM
out of self refresh mode. The bit is cleared by hardware only when
0h
0 the DRAM has exited out of self refresh mode and is accessible.
RW/V
Note: When COLDWAKE is set prior of setting this bit the D-Unit
will not send SR exit command and will not set the DCO.IC bit.

5.3.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—

Offset 1380h
LPDDR4 DQS Retraining control register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

138 334818
MCHBAR

DQS_RETRAIN_INT

RSVD15_14

RSVD3_2
DQS_OSC_RT

DQS_RETRAIN_SRX_EN
DQS_RETRAIN_EN
Bit Default &
Field Name (ID): Description
Range Access

DQS Periodic Retraining Interval (DQS_RETRAIN_INT):

0h
31:16 This sets the frequency by which the D-Unit initiates periodic
RW
retraining (in 1x NREFI).

15:14
0h Reserved (RSVD15_14): Reserved.
RO

DQS Oscillator Runtime (DQS_OSC_RT): After D-Unit starts

DQS oscillator, it must wait this amount of time before being able
0h
13:4 to read the value in MR18 and MR19 (in 16x DRAM clocks).
RW
Value in this register must be at least equal to DRAM's MR23
value. + tOSCO.

3:2
0h Reserved (RSVD3_2): Reserved.
RO

DQS Retrain SRX Exit (DQS_RETRAIN_SRX_EN): Enable

0h retraining on SR exit.
1
RW This bit enables LPDDR4 DQS retraining on Self Refresh Exit. If
disabled, D-Unit will not perform retraining on SR exit.
DQS Retrain Enable (DQS_RETRAIN_EN): Periodic retraining
enable:
0h This bit enables periodic DQS retraining. If disabled, D-Unit will
0
RW not perform retraining periodically.
Note: Will be enabled only if DCO.IC is set and refreshes are
enabled in DRF.MINREFRATE.

5.3.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset

1384h
Controls the data bits swizzling crossbar for MR4.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

334818 139
 MCHBAR

MR4_BYTE_SEL2
MR4_BIT2_SEL2

MR4_BIT1_SEL2

MR4_BIT0_SEL2

MR4_BYTE_SEL
RSVD31

RSVD27

RSVD23

RSVD19_18

RSVD15

MR4_BIT2_SEL

RSVD11

MR4_BIT1_SEL

RSVD7

MR4_BIT0_SEL

RSVD3_2
Bit Default &
Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

0h MR4 Bit 2 Select 2nd Byte (MR4_BIT2_SEL2): Selects bit 2 of

30:28
RW MR4 data.

27
0h Reserved (RSVD27): Reserved
RO

0h MR4 Bit 1 Select 2nd Byte (MR4_BIT1_SEL2): Selects bit 1 of

26:24
RW MR4 data

23
0h Reserved (RSVD23): Reserved
RO

0h MR4 Bit 0 Select 2nd Byte (MR4_BIT0_SEL2): Selects bit 0 of

22:20
RW MR4 data.

19:18
0h Reserved (RSVD19_18): Reserved
RO

0h MR4 Byte 2 Select (MR4_BYTE_SEL2): Selects byte position of

17:16
RW the MR4 data for second device.

15
0h Reserved (RSVD15): Reserved
RO

14:12
0h MR4 Bit 2 Select (MR4_BIT2_SEL): Selects bit 2 of MR4 data.
RW

11
0h Reserved (RSVD11): Reserved.
RO

10:8
0h MR4 Bit 1 Select (MR4_BIT1_SEL): Selects bit 1 of MR4 data.
RW

7
0h Reserved (RSVD7): Reserved.
RO

6:4
0h MR4 Bit 0 Select (MR4_BIT0_SEL): Selects bit 0 of MR4 data.
RW

3:2
0h Reserved (RSVD3_2): Reserved.
RO

0h MR4 Byte Select (MR4_BYTE_SEL): Selects byte position of

1:0
RW the MR4 data first device.

5.4 Registers Summary

Table 5-4. Summary of pcs_regs_wrapper Registers
Offset Offset Default
Register Name (ID)—Offset
Start End Value

1400h 1403h DRAM Rank Population 0 (D_CR_DRP0)—Offset 1400h 10000000h

140 334818
MCHBAR

Table 5-4. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset Default
Register Name (ID)—Offset
Start End Value

1408h 140Bh DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1408h 210702CBh

140Ch 140Fh DRAM Timing Register 1A (D_CR_DTR1A)—Offset 140Ch 30481218h

1410h 1413h DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1410h 8C080C30h

1414h 1417h DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1414h 3002EA28h

1418h 141Bh DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1418h 30209149h

141Ch 141Fh DRAM Timing Register 5A (D_CR_DTR5A)—Offset 141Ch 304200C2h

1420h 1423h DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1420h 20100000h

1424h 1427h DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1424h D060C06h

1428h 142Bh DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1428h CC50A18h

142Ch 142Fh D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 142Ch 0h

1430h 1433h D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1430h 0h

1434h 1437h D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1434h 10000028h

1438h 143Bh DRAM Refresh Control (D_CR_DRFC)—Offset 1438h 1750h

143Ch 143Fh D-Unit Scheduler (D_CR_DSCH)—Offset 143Ch 3901C08h

1440h 1443h DRAM Calibration Control (D_CR_DCAL)—Offset 1440h 1057h

1444h 1447h VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 144Ch 20000h

144Ch 144Fh VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 144Ch 0h

Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset

1450h 1453h 6C000008h
1450h

1454h 1457h TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1454h 0h

1458h 145Bh Data Scrambler (D_CR_SCRAMCTRL)—Offset 14A4h 0h

14A4h 14A7h Data Scrambler (D_CR_SCRAMCTRL)—Offset 14A4h 0h

14ACh 14AFh Error Injection Address Register (D_CR_ERR_INJ)—Offset 14ACh 0h

14B0h 14B3h Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 14B0h 0h

14B4h 14B7h Error Log Register (D_CR_ERR_ECC_LOG)—Offset 14B4h 0h

14BCh 14BFh D-Unit Status (D_CR_DFUSESTAT)—Offset 14BCh 0h

1524h 1527h Major Mode Control (D_CR_MMC)—Offset 1524h 2B01E518h

Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset

1528h 152Bh 1F207C8h
1528h

Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—

152Ch 152Fh 1F207C8h
Offset 152Ch

1530h 1533h Access Class Initial Priority (D_CR_ACCIP)—Offset 1530h 17C2h

Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset

1534h 1537h 1F52940h
1534h

Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset

1538h 153Bh 14000000h
1538h

Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset

153Ch 153Fh 0h
153Ch

Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset

1540h 1543h 1F29400h
1540h

Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset

1544h 1547h 1F5294Ah
1544h

1548h 154Bh Deadline Threshold (D_CR_DL_THRS)—Offset 1548h 6h

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Table 5-4. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset Default
Register Name (ID)—Offset
Start End Value

154Ch 154Fh Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 154Ch 1800h

1554h 1557h DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1554h 0h

1580h 1583h DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1580h 0h

1584h 1587h MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1584h 0h

5.4.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1400h

Rank configuration register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10000000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BLMODE

DWID
ADDRDEC

CASWIZZLE
DRAMDEVICE_PR

DRAMTYPE

RSVD18_16

RSVD3
DDMEN
RKEN1
RKEN0
ECCEN

BAHEN

RSVD13_9

DDEN
RSIEN

Bit Default &

Field Name (ID): Description
Range Access

DRAM Device Per Rank (DRAMDEVICE_PR): Specifies the number of DRAM

devices that are ganged together to form a single rank.
• 00: 1 DRAM device in each rank.
0h • 01: 2 DRAM devices in each rank.
31:30
RW
• 10: 4 DRAM devices in each rank.
• 11: 8 DRAM devices in each rank.
Note: The actual number of devices is one more than the value programmed when
ECC is enabled.

Address Decode (ADDRDEC): Specifies the address mapping to be used:

• 00: 1KB (A).
1h
29:28 • 01: 2KB (B).
RW
• 10: 4KB (C).
• 11: Reserved.

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Bit Default &

Field Name (ID): Description
Range Access

Burst Length Mode (BLMODE):

• 000: Fixed BL8.
• 001: Onthefly BL8.

0h
• 010: Fixed BL16.
27:25
RW • 011: Onthefly BL16.
• 100: Fixed BL32.
• 101: Onthefly BL32.
• 110-111: Reserved.
DRAM Type (DRAMTYPE):
• 000: DDR3L.
• 001: LPDDR3.
0h • 010: LPDDR4.
24:22
RW
• 011: Reserved.
• 100: Reserved.
• 101-111: Reserved.

ECC Enable (ECCEN):

• 0: ECC is disabled.
0h
21
RW • 1: ECC is enabled.
This bit determines if the D-Unit treats the PMI BE_ECC bits as ECC bits or Byte
Enables. This should only be used in configurations that support ECC (DDR3L).

CA Swizzle Type (CASWIZZLE):

• 00: uniDIMM/SODIMM.
0h
20:19 • 01: BGA.
RW
• 10: BGA mirrored (LPDDR3 Only).
• 11: UDIMM (DDR3L Only).

18:16
0h Reserved (RSVD18_16): Reserved.
RO

Bank Address Hashing Enable (BAHEN): See Address Mapping section for full
description.
0h
15 • 0: Bank Address Hashing disabled.
RW
• 1: Bank Address Hashing enabled.
Rank Select Interleave Enable (RSIEN): See Address Mapping section for full
description.
0h
14 • 0: Rank Select Interleaving disabled.
RW
• 1: Rank Select Interleaving enabled.

13:9
0h Reserved (RSVD13_9): Reserved.
RO

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Bit Default &

Field Name (ID): Description
Range Access

DRAM Device Density (DDEN): Density of the DRAM devices populated on Ranks 0
and 1.
• 000: 4 Gb.
• 001: 6 Gb.
0h • 010: 8 Gb.
8:6
RW
• 011: 12 Gb.
• 100: 16 Gb.
• 101-111: Reserved.
Note: For LPDDR4 this value is the die density.

DRAM Device Data Width (DWID): Data width of the DRAM device populated on
Ranks 0 and 1.
• 00: x8.
0h
5:4 • 01: x16.
RW
• 10: x32.
• 11: x64.

3
0h Reserved (RSVD3): Reserved.
RO

Dual Data Mode Enable (DDMEN):

• 0: PMI Dual Data Mode is disabled in D-Unit, full cacheline
0h
2 read and writes go through a single D-Unit.
RW
• 1: PMI Dual Data Mode is enabled, only half cacheline read/
writes go through a single D-Unit.
0h Rank Enable 1 (RKEN1): Enable Rank 1: Must be set to 1 to
1
RW enable use of this rank.
Rank Enable 0 (RKEN0): Enable Rank 0: Must be set to 1 to
0h
0 enable use of this rank.
RW
Note: Setting this bit to 0 is not a functional mode.

5.4.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1408h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 210702CBh

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 1
TCKCKEH

TXSDLL

TXSR

TRPPB
TRCD

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Bit Default &

Field Name (ID): Description
Range Access

Valid Clocks Before CKE High [tCKCKEH/tCSCKEH/tCKSRX] (TCKCKEH):

Number of valid clocks before CKE high (in DRAM clocks).
• LPDDR4: The value in this register covers both tCKCKEH and
tCSCKEH.
• DDR3L/LPDDR3: The value covers tCKSRX which is defined as
the number of valid DRAM clocks that have to toggle before
10h
31:25 the issuing of the Self Refresh Exit SRX. This value is also used
RW
if the clock frequency is changed or the clock is stopped or
tristated during Power Down i.e. the number valid DRAM
clocks that have to toggle before the issuing of the Power
Down Exit PDX command.
tCKCKEH can be used to compensate for clock stabilization delays in the
motherboard. Note: D-unit hardware enforces minimum of two SPID clock before
CKEH, any value in this register is the additional time.

Exit Self-Refresh to Valid Commands Requiring a Locked

DLL Delay [tXSDLL] (TXSDLL): D-Unit waits max(tXSR+tZQCL/
tZQCS, tXSDLL) before allowing traffic to DRAM (in 64 x DRAM
8h Clocks).
24:21
RW LPDDR3/LPDDR4: tXSDLL = 0.
DDR3L: tXSDLL = tDLLK = 512 Clocks = 8 x 64 DRAM Clocks.
Note: In the equation above, tZQCL/tZQCS = 0 if no ZQ is
performed on SR exit.
Exit Self-Refresh to Valid Command Delay [tXS/tXSR]
(TXSR): DDR3L: tXS - Delay between Self Refresh Exit SRX to
70h
20:12 any DRAM Command not requiring DLL Lock.
RW
LPDDR/: tXSR - Delay between Self Refresh Exit SRX to any DRAM
Command. (in DRAM clocks).
Activate RAS to CAS Command Delay [tRCD] (TRCD):
Specifies the delay between a DRAM Activate command and a
Bh
11:6 DRAM Read or Write command to the same bank (in DRAM
RW
clocks).
Note: Derating adds 1.875ns to this timing.
Precharge to Activate Command Delay of a Single Bank
[tRPpb] (TRPPB): Specifies the delay between a DRAM
Precharge command and a DRAM Activate command to the same
Bh
5:0 bank (in DRAM Clocks).
RW
Note : this CR should be constrained to a minimum of 4 in LPDDR3
and minimum of 8 in LPDDR4.
Note: Derating adds 1.875ns to this timing.

5.4.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 140Ch

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 30481218h

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3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0

TXP

RSVD26

TZQCL

TZQLAT
TZQCS
Bit Default &
Field Name (ID): Description
Range Access

Exit Power Down to Next Command Delay [tXP] (TXP):

Specifies the delay from the DRAM Power Down Exit (PDX)
6h
31:27 command to any valid command (in DRAM clocks).
RW
Note: The value in this field must be programmed to tXPDLL when
Slow Exit Mode Power-down is enabled for DDR3L.

26
0h Reserved (RSVD26): Reserved.
RO

ZQ (long) Calibration Time [tZQCL/tZQCAL] (TZQCL):

• LPDDR3/DDR3L: tZQCL/tZQoper: Specifies the delay between
the DRAM ZQ Calibration Long (ZQCL) command and any
DRAM command during normal operation.
120h
25:14 • LPDDR4: tZQCAL: ZQ Calibration time (in DRAM clocks).
RW
Note: This field defines the ZQ Calibration Long delay during normal operation. It is
not the same as tZQinit which uses the same ZQCL command but the delay is longer.
tZQinit applies only during poweron initialization of the DRAM devices and tZQoper
applies during normal operation. BIOS executes the DRAM initialization sequence so
it has to ensure tZQinit is met and not the D-Unit.

ZQ Short Calibration Time [tZQCS] (TZQCS): ZQCS to any

DRAM Command Delay: Specifies the delay between the DRAM ZQ
48h Calibration Short (ZQCS) command and any DRAM command (in
13:6
RW DRAM clocks).
DDR3L and LPDDR3 only. LPDDR4 does not support ZQCS
command
ZQ Latch Time [tZQLAT] (TZQLAT): Specifies the delay
18h between the DRAM ZQ Calibration Latch command and any DRAM
5:0
RW command (in DRAM clocks).
LPDDR4 only.Not used in DDR3L/LPDDR3.

5.4.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1410h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 8C080C30h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0

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TCKE
RSVD22_21

RSVD16

NREFI
NRFCAB
Bit Default &
Field Name (ID): Description
Range Access

All Bank Refresh Cycle Time [tRFCab] (NRFCAB): Specifies

118h
31:23 the delay between the REFab command to the next valid
RW
command. (in DRAM clocks)

22:21
0h Reserved (RSVD22_21): Reserved.
RO

4h CKE Minimum Pulse Width [tCKE] (TCKE): Specifies the

20:17
RW minimum time from CKEL to CKEH (in DRAM clocks).

16
0h Reserved (RSVD16): Reserved.
RO

Refresh Interval Time [tREFI] (NREFI): Specifies the average

C30h time between refresh commands. JEDEC Base Refresh Interval
15:0
RW time (in DRAM clocks).
Note: D-Unit will ignore the 2 LSBs of this field.

5.4.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1414h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 3002EA28h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 1 0 1 0 0 0
TCWL

TWMWSB
TCMD
TRTP

TCCD_INC

TWTP

Bit Default &

Field Name (ID): Description
Range Access

Read to Precharge Delay [tRDPRE] (TRTP): Specifies the minimum delay

between the DRAM Read and Precharge commands to the same bank (in DRAM
clocks).
6h
31:27 • LPDDR3 Equation: = BL/2 + tRTP - 4.
RW
• LPDDR4 Equation: = BL/2 + Max (8, tRTP) - 8.
• DDR3L Equation: = tRTP.

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Bit Default &

Field Name (ID): Description
Range Access

CAS to CAS Command Delay Adder (TCCD_INC): Specifies

0h the number of clocks to be added to turnaround times (for Stretch
26:20
RW Mode). It increases delay between Read to Read or Read to Write
commands (in 4 x DRAM clocks).
Write to Precharge Command Delay [tWRPRE] (TWTP): Specifies the minimum
delay between the DRAM Write command and the Precharge command to the same
17h bank (in DRAM clocks).
19:13
RW • LPDDR3/LPDDR4 Equation: tWTP = BL/2 + WL + tWR + 1.
• DDR3L Equation: tWTP = BL/2 + CWL + tWR.
DRAM Command Valid Duration (TCMD): Specifies the number of DRAM clocks a
command is held valid on the DRAM Address and Control buses. 1N is the DDR3 basic
requirement. 2N is the extended mode for board signal integrity.
• 0h: Reserved.
1h
12:11
RW • 1h: 1 DRAM Clock (1N).
• 2h: 2 DRAM Clocks (2N).
• 3h: Reserved.
Note: DDR3L only. tCMD must be set to 1N for LPDDR3/LPDDR4.

Write Latency [WL/CWL] (TCWL): The delay between the

8h
10:6 internal write command and the availability of the first word of
RW
DRAM input data (in DRAM clocks).
Write CAS to Masked Write CAS Delay Same Bank (TWMWSB): Specifies the
minimum delay between DRAM Write command to Masked Write command to same
bank (in DRAM clocks).
28h
5:0 • LPDDR4 Equation: tWMWSB = tCCDMW (BL16) or tCCDMW +
RW
8 (BL32).
Note: Masked Write operation in LPDDR4 is always BL16. D-Unit applies this timing
for same rank as well as same bank.

5.4.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1418h

Specifies DRAM timings parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 30209149h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1
TFAW

TWRDR

TRWDR

TWWDR

TRRDR

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Bit Default &

Field Name (ID): Description
Range Access

Four Bank Activate Window [tFAW] (TFAW): A rolling

30h timeframe in which a maximum of four Activate commands can be
31:24
RW issued to the same rank. This is to limit the peak current draw
from the DRAM devices (in DRAM clocks).
Write to Read DQ Delay Different Ranks (TWRDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Read data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tWRDR = WL + tDQSSmax + BL/2 +
tWPST - (RL + tDQSCKmin - tRPRE).
8h
23:18
RW • LPDDR4 Equation: tWRDR = WL - RL + BL/2 + 4 -
tDQSCKmin.
• DDR3L Equation: tWRDR = CWL + tDQSSmax + BL/2 +
tWPST - (CL + tDQSCKmin - tRPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.

Read to Write DQ Delay Different Ranks (TRWDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Write data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tRWDR = RL + tDQSCKmax + BL/2 +
tRPST - (WL + tDQSSmin - tWPRE).
9h
17:12 • LPDDR4 Equation: tRWDR = RL + tDQSCKmax + BL/2 - (WL -
RW
2).
• DDR3L Equation: tRWDR = CL + tDQSCKmax + BL/2 + tRPST
- (CWL + tDQSSmin - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be adjusted by tODTon.
Note: For DDR3L using ODT, this latency may need to be increased by one clock.

Write to Write DQ Delay Different Ranks (TWWDR): Specifies the delay from
the start of a Write data burst of one rank to the start of a Write data burst of a
different rank (in DRAM clocks).
• LPDDR3 Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin
5h + tWPRE.
11:6
RW
• LPDDR4 Equation: tWWDR = BL/2 + 4 - tDQSSmin.
• DDR3L Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin +
tWPRE.
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.

Read to Read DQ Delay Different Ranks (TRRDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Read data burst of a different
rank (in DRAM clocks).

5:0
9h • LPDDR3/4 Equation: tRRDR = BL/2 + tDQSCKmax -
RW tDQSCKmin + tRPRE.
• DDR3L Equation: tRRDR = BL/2 + tRPST + tDQSCKmax -
tDQSCKmin + tRPRE + 1.

5.4.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 141Ch

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

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Default: 304200C2h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0

TDERATE_INC
RSVD26

TWWSR

TRRSR

TWRSR

TRWSR
TRRD

Bit Default &

Field Name (ID): Description
Range Access

Row Activation to Row Activation Delay [tRRD] (TRRD):

Specifies the minimum delay in DRAM clocks between two DRAM
6h
31:27 Activate commands to the same rank but different banks (tRC is
RW
the minimum delay between activations of the same bank).
Note: Derating adds 1.875ns to this timing.

26
0h Reserved (RSVD26): Reserved.
RO

Derate Increment (TDERATE_INC): Specifies the additional

delay that is added to DRAM timing when indicated by MR4 status.
0h (in DRAM clocks)
25:23
RW LPDDR3/LPDDR4: Value is 1.875ns.
Note: The value in this register is only added to these timing
parameters: tRCD, tRAS, tRP and tRRD.
Write to Write DQ Delay Same Rank (TWWSR): Specifies the
10h delay from a DRAM Write to another Write command of the same
22:18
RW rank (in DRAM clocks).
LPDDR3/LPDDR4/DDR3L Equation: tRRSR = tCCD.
Read to Read DQ Delay Same Rank (TRRSR): Specifies the
10h delay from a DRAM Read to another Read command of the same
17:13
RW rank (in DRAM clocks).
LPDDR3/LPDDR4/DDR3L Equation: tRRSR = tCCD.
Write to Read DQ Delay Same Rank (TWRSR): Specifies the delay from a DRAM
Read to Write command of the same rank (in DRAM clocks).

3h • LPDDR3/LPDDR4 Equation: tWRSR = WL + tDQSSmax + BL/2

12:6 + tWTR.
RW
• DDR3L Equation: tWRSR = CWL + tDQSSmax + BL/2 +
tWPST + tWTR.
Read to Write DQ Delay Same Rank (TRWSR): Specifies the delay from a DRAM
Read to a Write command of the same rank (in DRAM clocks).
• LPDDR3/LPDDR4 Equation: tRWSR = RL + tDQSCKmax + BL/
2h 2 - WL + tWPRE.
5:0
RW
• DDR3L Equation: tRWSR = CL + tDQSCKmax + BL/2 + tRPST
- (CWL +tDQSSmin - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Note: For DDR3L using ODT, this latency may need to be increased by one clock.

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5.4.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1420h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 20100000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD7
TPSTMRRBLK
OREFDLY

TCKCKEL

MNTDLY

TPREMRBLK
Bit Default &
Field Name (ID): Description
Range Access

20h Opportunistic Refresh Idle Timer (OREFDLY): Rank idle

31:24
RW period that defines an opportunity for refresh (in DRAM clocks).
Valid Clocks After CKE Low [tCKELCK/tCKELCS/tCPDED/tCKSRE]
(TCKCKEL): Specifies the amount of time that DRAM clocks need to toggle after CKE
goes low (in DRAM Clocks).
• For LPDDR3, this covers tCPDED.
2h
23:19
RW • For LPDDR4, this covers both tCKELCK and tCKELCS.
• For DDR3L, this is tCKSRE.
Note: D-Unit hardware enforces minimum of one SPID clocks after CKEL, any value in
this register is the additional time.

Maintenance Operation Delay (MNTDLY): When a critical read

request is pending in RPQ and a maintenance operation (MRR,
0h ZQCal, Ref, etc, panic refresh is an exception to this delay.) needs
18:15
RW to be performed, D-Unit waits this amount of time before
performing the maintenance operation to allow for some high
priority requests to be issued (in 4x SPID clocks).
Mode Register Read to Any Command Delay
(TPSTMRRBLK): Specifies the quiet time after issuing MRR
command (in DRAM Clocks).
0h
14:8 Note: D-Unit treats MRR as a read and always applies relevant
RW
turnaround times, any value programmed in this CR must be
greater than those turnaround times for D-Unit to enforce any
additional time from MRR to the next read/write.

7
0h Reserved (RSVD7): Reserved.
RO

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Bit Default &

Field Name (ID): Description
Range Access

Any Command to Mode Register Read/Write Delay

(TPREMRBLK): Specifies the quiet time before issuing MRR/MRW
command. (in DRAM clocks).
0h
6:0 Note: D-Unit treats MRR as a read and always applies relevant
RW
turnaround times, any value programmed in this CR must be
greater than those turnaround times for D-Unit to enforce any
additional time from previous read/writes.

5.4.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1424h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: D060C06h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0

RSVD8_7
TRDPDEN
TWRPDEN
TRPAB

TPSTMRWBLK

TRAS
Bit Default &
Field Name (ID): Description
Range Access

All Bank Precharge to Activate Command Delay [tRPab] (TRPAB): Specifies

the delay between a DRAM Precharge All Bank command and a DRAM Activate
command (in DRAM Clocks). Note: This CR should be constrained to a minimum of 4
3h in LP3 and minimum of 8 in LP4. Note: Derating adds 1.875ns to this timing.
31:26
RW
• For LPDDR, tRPpb = tRP, tRPab = tRP + 3ns.
• For DDR3L 8ch tRPpb = tRPab = tRP.
Mode Register Write to any Command Delay [tMRD/tMRW]
2h (TPSTMRWBLK): Specifies the quiet time after issuing MRW
25:23
RW command (in 8 x DRAM clocks).
Note: This time covers for both tMRD and tMRW.
Write Command to Power Down Delay [tWRPDEN]
6h (TWRPDEN): Specifies the minimum time between a write
22:16
RW command to PowerDown command (in DRAM clocks).
Must be at least equal to tWR + tCCD + tWL + 2.
Read Command to Power Down Delay [tRDPDEN]
6h (TRDPDEN): Specifies the minimum time between a read
15:9
RW command to PowerDown command (in DRAM clocks).
Must be at least equal to CL/RL + tDQSCKmax + tCCD + tRPST.

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Bit Default &

Field Name (ID): Description
Range Access

8:7
0h Reserved (RSVD8_7): Reserved.
RO

Row Activation Period [tRAS] (TRAS): Specifies the minimum

6h delay between the DRAM Activate and Precharge commands to
6:0
RW the same bank (in DRAM clocks).
Note: Derating adds 1.875ns to this timing.

5.4.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1428h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: CC50A18h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0
TCKESR

LPMDRES

LPMDTOCKEDLY

PWDDLY
CKETOLPMDDLY

Bit Default &

Field Name (ID): Description
Range Access

Minimum Self-Refresh Time [tSR/tCKESR] (TCKESR):

3h
31:26 Specifies the minimum time that DRAM should remain in SR (in
RW
DRAM clocks).
Minimum Low Power Mode Residency (LPMDRES): Specifies
6h
25:21 the minimum time that PHY should remain in LPMode (in DRAM
RW
clocks).
Low Power Mode Exit to Clock Enable Delay
(LPMDTOCKEDLY): Specifies the minimum time between the LP
Ah
20:15 Mode exit to the CK stop/tristate deassertion and powerdown exit
RW
(in DRAM clocks).
Note: Must be equal to t_idle_latency and less than 0x3C.
Clock Stop to Low Power Mode Delay (CKETOLPMDDLY):
Specifies the time between CK stop/tristate to the Low Power
Ah Mode entry. This timing parameter is used to delay Low Power
14:8
RW Mode entry (in DRAM clocks).
Note: Must be at least equal to t_idle_length parameter and less
than 0x7C.

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Bit Default &

Field Name (ID): Description
Range Access

Power Down Idle Timer (PWDDLY): This is a non-JEDEC

18h
7:0 timing parameter used to delay powerdown entry (in DRAM
RW
clocks).

5.4.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset

142Ch
Specifies the parameters to control DRAM ODT.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDODTSTART

WRODTSTART
RDODTSTOP

WRODTSTOP

RSVD4
RSVD31_30

R1WRODTCTL

R0WRODTCTL

RSVD23_18

RSVD13
R1RDODTCTL
R0RDODTCTL

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

Rank 1 Read ODT Control (R1RDODTCTL): Specifies the

behavior of ODT signals when a Read command is issued to Rank
0h 1.
29
RW 0 - Read ODT is disabled for Rank 1
1 - Assert ODT to for Rank 0 (non-targeted Rank)
Note: This register should be set to 0 for LPDDR3 devices
Rank 0 Read ODT Control (R0RDODTCTL): Specifies the
behavior of ODT signals when a Read command is issued to Rank
0h 0.
28
RW 0 - Read ODT is disabled for Rank 0
1 - Assert ODT to for Rank 1 (non-targeted Rank)
Note: This register is reserved for LPDDR3 devices
Rank 1 Write ODT Control (R1WRODTCTL): Specifies the
behavior of ODT signals when a Write command is issued to Rank
1.
0h 00 - Write ODT is disabled
27:26
RW 01 - Assert ODT to Rank 0 (non-targeted Rank)
10 - Assert ODT to Rank 1 (targeted Rank)
11 - Assert ODT to Rank 0 and Rank 1
Note: 10 and 11 are reserved values for LPDDR3

154 334818
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Bit Default &

Field Name (ID): Description
Range Access

Rank 0 Write ODT Control (R0WRODTCTL): Specifies the

behavior of ODT signals when a Write command is issued to Rank
0.
0h 00 - Write ODT is disabled
25:24
RW 01 - Assert ODT to Rank 0 (targeted Rank)
10 - Assert ODT to Rank 1 (non-targeted Rank)
11 - Assert ODT to Rank 0 and Rank 1
Note: 10 and 11 are reserved values for LPDDR3

23:18
0h Reserved (RSVD23_18): Reserved.
RO

Read ODT assertion to de-assertion delay (DDR3L Only)

(RDODTSTOP): Specifies Read ODT assertion to ODT de-assert
0h
17:14 delay (in DRAM clocks).
RW
DDR3L Equation: RDODTSTOP = DOCRx.WRODTSTOP (subtract 1
if DOCRx.WRODTSTART = 1 in 2N mode).

13
0h Reserved (RSVD13): Reserved.
RO

Read command to ODT assertion delay (DDR3L Only)

(RDODTSTART): Specifies Read ODT assertion delay after Read
0h Command (in DRAM clocks).
12:9
RW DDR3L Equation: RDODTSTART = CL CWL (add 1 if
DOCRx.WRODTSTART = 0 in 2N mode).
The max value for this CR is 0xE
Write ODT Assertion to De-assertion Delay (WRODTSTOP):
Specifies number of clocks after ODT assertion that D-Unit
0h deasserts ODT signal (in DRAM clocks).
8:5
RW LPDDR3 Equation: WRODTSTOP = RU(tODTon(max)/tCK) +
RU((tDQSSmax+tWPST)/tCK) + BL/2 - RD(tODToffmin/tCK)
DDR3L Equation: WRODTSTOP >= 6

4
0h Reserved (RSVD4): Reserved.
RO

Write command to ODT assertion delay (WRODTSTART):

Specifies number of clocks after Write command that D-Unit
asserts ODT signal (in DRAM clocks).
LPDDR3 Equation: WRODTSTART = WL - RU(tODTon(max)/tCK)
0h DDR3L Equation: WRODTSTART = 0 Note: DDR3 spec requires
3:0
RW ODT to be asserted high when the DRAM Write command is
issued. In DDR3L 2N mode the value can be set to 0 to assert ODT
one DRAM clock earlier than the Write Command (WR) or set to 1
to assert at the same clock as command (CS assertion).
The max value for this CR is 0xE

5.4.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—

Offset 1430h
Specifies the parameters to control D-Unit power management features.

Access Method

334818 155
 MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SREDLY
SUSPMOP
RSVD31_29

DYNPMOP
RSVD23
SRPMCLKW

DYNSREN
Bit Default &
Field Name (ID): Description
Range Access

31:29
0h Reserved (RSVD31_29): Reserved.
RO

SUSPEND/SUSPENDP Power Management Message Opcode

(SUSPMOP): DDRIO PHY Power Mode Opcode: After the D-Unit
has placed the DRAM devices in Self Refresh/PASR mode as the
result of a SUSPEND/SUSPENDP message, it sends this 5-bit value
0h
28:24 to the DDRIO PHY to tell it which power saving mode it should
RW
enter.
Changing this register value while in SUSPEND will have no effect.
Note: This opcode cannot be a PM state where it disables PHY PLLs
i.e PM7 in LPDDR PHY.

23
0h Reserved (RSVD23): Reserved.
RO

PM Message Wait for Clock Gate Enable (SRPMCLKW): Specifies when it is safe
to send PM message to the PHY. When enabled, D-Unit waits for SPID Clock to
deassert before sending a PM message on SR entry.

0h • 0: D-Unit will not wait for SPID_clk to deassert before sending

22
RW the PM message to PHY.
• 1: D-Unit will wait for SPID_clk to deassert before sending PM
message to the PHY.
Note: The value must be 1 when DYNPMOP = 7h.

Dynamic Self-Refresh Power Management Message Opcode

(DYNPMOP): DDRIO PHY Power Mode Opcode: After the D-Unit
has placed the DRAM devices in Self Refresh mode as the result of
0h
21:17 a Dynamic Self-Refresh, it sends this 5bit value to the DDRIO PHY
RW
to tell it which power saving mode it should enter.
Changing this register value while in self-refresh will only change
the PM state for the next entry in DynSR.
Dynamic Self-Refresh Enable (DYNSREN): When set to 1, the
D-Unit will automatically control DRAM Self Refresh entry and exit
based on interface state and requests in pending queues. When
0h
16 there is no pending request in the queues and PMI is idle, then the
RW
D-Unit will place the DRAM devices in Self Refresh mode. The
DRAM devices will be brought out of Self-Refresh when idle
conditions don't hold.

156 334818
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Bit Default &

Field Name (ID): Description
Range Access

Self-Refresh Entry Delay (SREDLY): Specifies the minimum

0h
15:0 time the D-Unit will wait before it enters Dynamic Self-Refresh
RW
mode when idle (in 16x DRAM Clocks).

5.4.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—

Offset 1434h
Specifies the parameters to control D-Unit power management features.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10000028h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
CSTRIST

CMDTRIST

PCLSTO

ODTTRIST
RPTCLKGTDIS

CLKGTDIS

PCLSTODIS
SBEPCLKGTDIS

LPMODEOP
RSVD31_30

RSVD6

ENCKSTP

DISPWRDN
PASR

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

D-Unit Repeaters Clock Gate Disable (RPTCLKGTDIS):

Setting this bit to 0 allows majority of the repeaters between D-
Unit and PHY to clock gate when there is no activity in order to
save power.
0h 0 - Enable Repeaters clock gating, 1 - Disable Repeaters clock
29
RW gating.
Note: This is a de-feature bit and should be set to 0 for normal
operation.
Note: The value should only change after DRAM Timing Registers
(DTR) are programmed.
IOSF-SB End Point Clock Gate Disable (SBEPCLKGTDIS):
Setting this bit to 0 enables the clock gating of IOSF-SB End
Points in D-Unit and CPGC when there is no IOSF-SB activity in
order to save power.
1h 0 - Enable IOSF-SB EP clock gating, 1 - Disable IOSF-SB clock
28
RW gating.
Note: This is a de-feature bit and should be set to 0 for normal
operation.
Note: The value should only change after DRAM Timing Registers
(DTR) are programmed.

334818 157
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Local Clock Gate Disable (CLKGTDIS): Setting this bit to 0 allows the majority of
the D-Unit clocks to be gated off when there is no activity in order to save power.
When set to 1, D-Unit clockgating is disabled.
0h • 0: Enable.
27
RW
• 1: Disable.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.

Chip Select Tristate Enable (CSTRIST):

• 0: The DRAM CS pins associated with the enabled ranks are
0h never tristated.
26
RW
• 1: The DRAM CS pins are tristated when DRAM clock is
stopped or tristated.
Note: CS is not tristated when global tristate flow is disabled (DCBR.TRISTDIS = 1).

Command/Address Tristate (CMDTRIST):

• 00: The DRAM CA pins are never tristated.
• 01: The DRAM CA pins are only tristated when all enabled CKE
0h
25:24 pins are low.
RW
• 10: The DRAM CA pins are tristated when not driving a valid
command.
• 11: Reserved
Partial Array Self-Refresh Segment Mask (PASR): This is the
0h
23:16 Segment Mask used for the MRW to enable PASR during
RW
SUSPENDP (Partial Array Self Refresh entry).
Page Close Timeout Period (PCLSTO): Specifies the time from
0h the last access of a DRAM page until that page is scheduled to
15:8
RW close by sending a Precharge command to DRAM (in 16 x DRAM
clocks).
Page Close Timeout Disable (PCLSTODIS): When disabled, D-Unit will not close
the DRAM page when idle.
0h • 0: Enable page close timer.
7
RW
• 1: Disable page close timer (Used during DRAM init and
DDRIO training).

6
0h Reserved (RSVD6): Reserved.
RO

ODT Tristate Enable (ODTTRIST):

• 0: The DRAM ODT pins associated with the enabled ranks are
1h never tristated.
5
RW
• 1: DRAMs ODT pins are tristated when DRAM clock is stopped
or tristated.
Note: ODT is not tristated when global tristate flow is disabled (DCBR.TRISTDIS = 1)

158 334818
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Bit Default &

Field Name (ID): Description
Range Access

Clock Stop/Tristate Enable (ENCKSTP): Enable/Disable CK Stop/Tristate During

Power down.
• 00: Disable CK Stop/Tristate During Power down.
1h • 01: Enable CK Stop During Power down.
4:3
RW
• 10: Enable CK Tristate During Power down.
• 11: Reserved
Note: CK is not stopped or tristated when global tristate flow is disabled
(DCBR.TRISTDIS = 1).

Low Power Mode Opcode (LPMODEOP): D-Unit will send the

value in this register after it has entered Powerdown Mode and has
0h stopped/tristated the clock.
2:1
RW 00: Disable LPMode.
Note: LPMODE entry is not possible when global tristate flow is
disabled (DCBR.TRISTDIS = 1).
Disable Power Down (DISPWRDN): Setting this bit to 1 disables dynamic control
of DRAM Power-Down entry and exit by keeping the CKE pins driven high. BIOS may
set it to 1 during DRAM initialization and DDRIO training. This bit should be set to 0
for normal operation.
• 0: The D-Unit dynamically controls the CKE pins to place the
0h DRAM devices in Power Down mode and bring them out of
0
RW Power Down mode.
• 1: The D-Unit constantly drives the CKE pins high to keep the
DRAM devices from entering Power Down mode when ranks
are idle.
Note: This bit is overridden if CKEMODE = 1. This bit does not control CKE behavior
on SR entry/exit.

5.4.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1438h

Specifies the parameters to control scheduling of refresh commands.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1750h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 0
DISREFDBTCLR
REFSKWDIS

EXTRAREFDBT

MINREFRATE

OREFDIS
RSVD31_22

RSVD19_18

RSVD17_16

REFWMPNC

REFWMHI

RSVD3_1

334818 159
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

31:22
0h Reserved (RSVD31_22): Reserved.
RO

Disable Refresh Debt Clear (DISREFDBTCLR): When set, D-Unit will not clear
refresh debt before Self Refresh SR Entry:

0h • 0: D-Unit sends all postponed REF commands to DRAM before

21 it enters Self Refresh.
RW
• 1: D-Unit enters SR without clearing the Refresh Debt (for
Debug only).
Refresh Skew Disable (REFSKWDIS): Disables Skewing of Refresh Counting
between Ranks. Each rank has its own refresh counter. By default incrementing these
refresh counters are skewed by 1/2 the tREFI period. Setting this bit to a 1 disables
this feature and all refresh counters will increment at the same time per tREFI period.
Skewing the tREFI counters can improve performance since traffic to all ranks does
not have to be blocked to perform refresh.
0h
20
RW • 0: Incrementing the refresh counters are skewed by 1/2 tREFI
period.
• 1: All refresh counters will increment at the same time per
tREFI period.

19:18
0h Reserved (RSVD19_18): Reserved.
RO

17:16
0h Reserved (RSVD17_16): Reserved.
RO

Extra Refresh Debit (EXTRAREFDBT): When set to 1, D-Unit

0h
15 adds one extra refresh debit (for a total of two) on Self-refresh
RW
exit.
Minimum Refresh Rate (MINREFRATE): Ensures that refresh rate never drops
below a certain limit regardless of TQ polling.
• 000: Disable tREFI counter and stop issuing refresh
commands.
• 001: 0.25x refresh rate (i.e. 4x tREFI same as no limit).
1h • 010: 0.5x refresh rate (i.e. 2x tREFI).
14:12
RW • 011: 1x refresh rate (i.e. 1x tREFI).
• 100: 2x refresh rate (i.e. 0.5x tREFI).
• 101: 4x refresh rate (i.e. 0.25x tREFI).
• 110: 4x refresh rate with derating forced on i.e. 0.25x tREFI.
• 111: Reserved.
Refresh Panic Watermark (REFWMPNC): When the Refresh
counter per rank is greater than this value, the D-Unit will send a
7h REF command to the rank regardless of pending requests.
11:8
RW Note: REFWMPNC must be greater than or equal to REFWMHI and
greater than 2, Max Value must be less than 8 to not violate
9xtREFI JEDEC requirement.

160 334818
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Bit Default &

Field Name (ID): Description
Range Access

Refresh High Watermark (REFWMHI): When the Refresh

counter per rank is greater than this value, the D-Unit will send a
5h REF command to the rank if there is no critical priority requests in
7:4
RW the pending queues.
Note: Value must be greater or equal to 1 and less than or equal
to REFWMPNC.

3:1
0h Reserved (RSVD3_1): Reserved.
RO

Opportunistic Refresh Disable (OREFDIS): Disable opportunistic scheduling of

refresh.
• 0: D-Unit will send a REF command only if there is no pending
0h request to that rank.
0
RW • 1: D-Unit will not send any opportunistic refreshes. Refresh
commands are only sent when the refresh counter is greater
than REFWMHI.
Note: When set, DISREFDBTCLR must also be set to be able to enter SR.

5.4.15 D-Unit Scheduler (D_CR_DSCH)—Offset 143Ch

Specifies parameters to control scheduling of commands to DRAM.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 3901C08h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0
WPQCOUNT

RPQCOUNT

BLKRDBF_ADD_RDDATA_CR

INORDERMODE

TMWR_TA_DELTA
BGF_EARLY_RDDATA_VALID

SPID_EARLY_RDDATA_VALID

RSVD15_14
RSVD31

BYPASSEN
BLKRDBF

STRETCHMODE

Bit Default &

Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

334818 161
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

BGF Early Read Data Valid (BGF_EARLY_RDDATA_VALID): Specifies the

number of clocks the D-Unit sends the read data valid through the BGF earlier as
compared to the data.

0h • 00: Always write read valid in same SPID clock as data.

30:29
RW • 01: Always write read valid one SPID clock before data.
• 10: Write read valid up to 2 SPID clocks before data.
• 11: Reserved
SPID Early Read Data Valid
0h (SPID_EARLY_RDDATA_VALID): Specifies the delay in SPID
28:27
RW clocks from RDDATA_VALID assertion to actual data on SPID. The
value should match what is programmed in DDRIO (PHY).
Write Pending Queue Count (WPQCOUNT): Used to limit the
1Ch number of available slots in Write Pending Queue/ Write Data
26:21
RW Buffer. WPQCOUNT will only recognize changes when PMI ISM is
not active.
Read Pending Queue Count (RPQCOUNT): Used to limit the
10h
20:16 number of entries in Read Pending Queue. RPQCOUNT will only
RW
recognize changes when PMI ISM is not active.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

Read Return Data Additional Credits

(BLKRDBF_ADD_RDDATA_CR): Number of additional full
7h cacheline (64B) read data return credits exposed to D-Unit when
13:10
RW BLKRDBF is set.
Note: The value in this field has no effect on Read return credits
when BLKRDBF is not set.
In-Order Mode (INORDERMODE):
• 0h: In order mode disabled: Commands are sent out of order.
• 1h: Partial in order mode: Read and Write CAS commands are
sent in the order they were recieved. ACT and PRE can go out
of order.
0h
9:8
RW • 2h: Full in order mode serialized test: All DRAM commands
CAS ACT PRE associated with a PMI request are issued to DDR
before any DRAM commands for a subsequent PMI request.
• 3h: Reserved.
In order modes should be enabled during init/training/CPGC testing. Should never be
changed while the D-Unit queues are nonempty.

7
0h Idle Bypass Mode Enable (BYPASSEN): Reserved.
RW

Block When RDB Full (BLKRDBF): When set D-Unit stops

0h
6 scheduling new read commands to DRAM when the read data
RW
buffer (RDB) is full.

162 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Stretch Mode (STRETCHMODE): When stretch mode is enabled, commands are

initiated only on Phase 0 of SPIDClk.
• 00: Stretch mode is disabled.
0h
5:4 • 01: Commands are initiated on Phase 0 of every SPID clocks.
RW
• 10: Commands are initiated on Phase 0 of even SPID clocks.
• 11: Commands are initiated on Phase 0 of odd SPID clocks.
Masked Write Turnaround Delta (TMWR_TA_DELTA): The value in this register
8h is subtracted from Masked Write to Read, Masked Write to Write and Masked Write to
3:0 Masked Write turnaround times to account for half BL MWr commands in LPDDR4.
RW
• LPDDR4: = MWr tCCD = MWr BL/2 = 8.

5.4.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1440h

Specifies parameters to control ZQ Calibration.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1057h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1
ZQCALSTRTR1
ZQCALSTRTR0

RSVD28_23

SRXZQC

RSVD20_18

RSVD15_14
ZQCALTYPE

ZQCLMODE
ZQCDIS

ZQINT

Bit Default &

Field Name (ID): Description
Range Access

ZQ Calibration Type (ZQCALTYPE): Determines whether the

ZQ Calibration is a long or short calibration command (due to
0h
31 ZQCALSTRT).
RW
0: Short calibration (ZQCS).
1: Long calibration (ZQCL).
ZQ Calibration Start Rank 1 (ZQCALSTRTR1): Set this bit to 1
to start the ZQ calibration sequence on Rank 1. This bit will remain
0h a 1 until the ZQ calibration is complete for rank 1, then it will
30
RW/V return to 0.
0: ZQ calibration is done.
1: ZQ calibration has started and is in progress.

334818 163
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

ZQ Calibration Start Rank 0 (ZQCALSTRTR0): Set this bit to 1

to start the ZQ calibration sequence on Rank 0. This bit will remain
0h a 1 until the ZQ calibration is complete for rank 0, then it will
29
RW/V return to 0.
0: ZQ calibration is done.
1: ZQ calibration has started and is in progress.

28:23
0h Reserved (RSVD28_23): Reserved.
RO

Self-Refresh Exit ZQ Calibration Control (SRXZQC):

• 00: On DynSR exit ZQ timer determines the ZQ type. When
the state is lost (i.e due to AutoPG/S0ix) ZQCL is always
performed.
0h • 01: Always perform ZQCL after self refresh exit, in LPDDR4,
22:21
RW ZQ with traffic blocked.
• 10: Always perform ZQCS on SR exit. For LPDDR4, ZQ while
traffic is allowed.
• 11: No ZQCL commands are sent (it disables ZQCAL
commands on SR exit).

20:18
0h Reserved (RSVD20_18): Reserved.
RO

ZQ Calibration Mode (ZQCLMODE): Specifies how ZQCal commands are sent to

different ranks.
0h
17 • 0: ZQCal commands are sent in parallel to all ranks.
RW
• 1: ZQCal commands are sent serially to each rank.
Periodic ZQ Calibration Disable (ZQCDIS):
0h
16 • 0: Periodic ZQ Calibration is Enabled.
RW
• 1: Disable periodic ZQ Calibration.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

ZQ Calibration Interval (ZQINT): Specifies the time interval

1057h
13:0 between two ZQCS (LPDDR3) or ZQ Start (LPDDR4) commands to
RW
a DRAM device. (in RTC 32.8KHz clocks)

5.4.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset

144Ch
Specifies parameters for VNN Scaling Timer in D-Unit. The values in this register will be
set by P-code during VNN scaling period.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

164 334818
MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD30_12
VNN_TIMER_EN

VNN_TIMER_TIME
Bit Default &
Field Name (ID): Description
Range Access

VNN Scaling Timer Enable (VNN_TIMER_EN):

0h
31 • 0: The D-Unit VNN Scaling Timer is disabled.
RW
• 1: The D-Unit VNN Scaling Timer is enabled.

30:12
0h Reserved (RSVD30_12): Reserved.
RO

0h VNN Timer Time (VNN_TIMER_TIME): The final timer value

11:0
RW (in 16 x DRAM clocks).

5.4.18 Periodic DRAM Temperature Polling Control (TQ)

(D_CR_TQCTL)—Offset 1450h
Specifies the control for periodic temperature monitoring and control of DRAM device.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 6C000008h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
TQDATAR1

TQDATAR0

RSVD25_22

RSVD7_5
TQPOLLPER

ENDERATE
SRTEN

TQDATAPUSHEN

TQPOLLEN
TQPOLLSREN

Bit Default &

Field Name (ID): Description
Range Access

TQ Data Rank 1 (TQDATAR1): If Rank 1 is disabled, this value

3h will remain zero.
31:29
RW/V This field contains the data of the last DRAM Mode Register Read
to MR4 MRR issued. It is overwritten with each command.

334818 165
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

TQ Data Rank 0 (TQDATAR0): This field contains the data of

3h
28:26 the last DRAM Mode Register Read to MR4 MRR issued. It is
RW/V
overwritten with each command.

25:22
0h Reserved (RSVD25_22): Reserved.
RO

TQ Poll Period (TQPOLLPER): This sets the frequency by which

0h
21:8 the D-Unit polls the DRAM mode register MR4 to determine
RW
required refresh rate (in 4x tREFI units).

7:5
0h Reserved (RSVD7_5): Reserved.
RO

Self Refresh Temperature Range Enable (DDR3 Only)

(SRTEN): When set, before every Self refresh entry, D-Unit
0h writes a 1 to bit 7 of TQOFFSET.MR_VALUE when TQDATA for that
4
RW rank indicates a value higher then 0x3, and writes a 0 to that bit
otherwise. The new MR_VALUE is then written into MR2 of DDR3
for each enabled rank.
Enable Dynamic Timing Derating (ENDERATE): When set to
1, the Dynamic Timing Derating is enabled. When the D-Unit
1h
3 determines (via TQ polling) that the DRAM requires timing
RW
derating in addition to refresh interval adjustment, the D-Unit will
automatically adjust the relevant timing parameters.
0h Enable TQ Data Push (TQDATAPUSHEN): When set to 1, D-
2
RW Unit pushes the data form the last MR4 read to a punit register.
Enable TQ Poll on Self-Refresh Exit (TQPOLLSREN): This bit
0h
1 enables MR4 read on Self Refresh Exit. If disabled, D-Unit will not
RW
read MR4 value on Self-Refresh exit.
Enable Periodic TQ Poll (TQPOLLEN): This bit enables periodic
0h
0 TQ Poll. If disabled, D-Unit will not read MR4 value periodically.
RW
Note: Will be enabled only if refreshes are enabled.

5.4.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset

1454h
Specifies temperature offset and refresh rate adjustments requested by software.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

166 334818
MCHBAR

MR_VALUE

MR3_OFFSET_UPDATE
RSVD31_26

RSVD15_11

MR4_ADDER

RSVD7_3

MR3_THERM_OFFSET
Bit Default &
Field Name (ID): Description
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

MR Value (MR_VALUE): MR2 Shadow Register (DDR3L Only):

0h BIOS writes the correct value of MR2 register in DDR3L into this
25:16
RW field at boot time. D-Unit modifies one bit and rewrites the MR2
into DDR3L DRAM before SR entry.

15:11
0h Reserved (RSVD15_11): Reserved
RO

MR4 Adder (MR4_ADDER): D-Unit adds the value of this field to

0h
10:8 TQDATA read from MR4 the resulting value is used to control
RW
refresh rate and AC timing derating.

7:3
0h Reserved (RSVD7_3): Reserved.
RO

MR3 Offset Update (MR3_OFFSET_UPDATE): When set, D-

0h Unit writes the merged value of MR3_VALUE and
2
RW/V MR3_THERM_OFFSET into MR3 of DRAM. D-Unit clears this bit
once the value is written.

1:0
0h MR3 Thermal Offset (MR3_THERM_OFFSET): Reserved.
RW

5.4.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 14A4h

Specifies parameters to control data scrambling in D-Unit.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCRM_EN

RSVD27_16
RSVD30

CLOCKGATE

KEY

334818 167
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Bit Default &

Field Name (ID): Description
Range Access

Enable Data Scrambler (SCRM_EN): When set to 1, data

0h
31 scrambling is enabled. When set to 0, data scrambling is disabled.
RW
Should be set before D_CR_BGF_CTL_BGF_RUN is set to 1.

30
0h Reserved (RSVD30): Reserved.
RO

Scrambler Clock Gate Select (CLOCKGATE): This field controls how the scrambler
output code is clock gated to reduce power.
• 00: Clock gate disabled.
0h
29:28 • 01: Clock Gate every 2 cycle.
RW
• 10: Clock Gate every 3 cycle.
• 11: Clock Gate every 4 cycle.

27:16
0h Reserved (RSVD27_16): Reserved.
RO

0h Scrambling Key (KEY): Sets the key for the scrambler. The key
15:0
RW should be a random value that is set following each cold boot.

5.4.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset

14ACh
Contains the target address for ECC error injection.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADDRESS
RSVD31

RSVD0

Bit Default &

Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

Error Injection Target Address (ADDRESS): Specifies the PMI

0h address of the write transaction to be injected with the error. Only
30:1
RW applicable to Write transactions. Read/under-fill read of the partial
write operation is not affected.

0
0h Reserved (RSVD0): Reserved.
RO

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5.4.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—

Offset 14B0h
Controls injecting correctable or uncorrectable errors into the write requests specified
by target address.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD31_4

SEL_HI
EN_HI
SEL_LO
EN_LO
Bit Default &
Field Name (ID): Description
Range Access

31:4
0h Reserved (RSVD31_4): Reserved
RO

Error Injection Type Higher 32B (SEL_HI): If enabled, the error injection is
continuously armed for ERR_INJ.ADDR 32B write address matching until it is cleared.
• 00: No error injection.
• 01: Uncorrectable Error (UE) is armed for write address
matching to inject UE by using the same poisoning scheme,
0h i.e. inverting corresponding write ECC[6:0] on QW0 of the 32B
3
RW data.
• 10: Correctable Error (CE) is armed for write address
matching to inject CE by inverting corresponding write ECC[0]
on QW0 of the 32B data.
• 11: Reserved.
Error Injection Enable Higher 32B (EN_HI): When set the
0h
2 error injection is continuously armed for higher 32B of
RW
D_CR_ERR_INJ_ADDR write address matching until it is cleared.
Error Injection Type Lower 32B (SEL_LO): 0 - Uncorrectable
Error (UE) is armed for write address matching to inject UE by
using the same poisoning scheme, i.e. inverting corresponding
0h
1 write ECC[6:0] on every QW of the 32B data.
RW
1 - Correctable Error (CE) is armed for write address matching to
inject CE by inverting corresponding write ECC[0] on every QW of
the 32B data.
Error Injection Enable Lower 32B (EN_LO): When set, the
0h
0 error injection is continuously armed for lower 32B of
RW
D_CR_ERR_INJ_ADDR write address matching until it is cleared.

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5.4.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 14B4h

Detected ECC errors are captured in this register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYNDROME_QW

TAG
CLEAR

CERR
MERR
ECC_VISA

ERR_BURST

ERR_CHUNK

Bit Default &

Field Name (ID): Description
Range Access

0h Clear (CLEAR): Setting this bit to one clears all fields in this
31
RW/V register, including itself.
PMI VISA Byte Select (ECC_VISA): Select ECC or PMI byte on VISA :
• 00: ECC byte,
0h
30:29 • 01: PMI Data Byte [7:0],
RW
• 10: PMI Data Byte [63:56],
• 11: PMI Data Byte [255:248]
Correctable Single-bit Error (CERR): This bit is set when a
correctable single-bit error occurs on a memory read data
transfer. When this bit is set, the address that caused the error
0h
28 and the error syndrome are also logged and they are locked to
RW/V
further single bit errors, until this bit is cleared. A multiple bit
error that occurs after this bit is set will override the address/error
syndrome information.
Uncorrectable Multiple-bit Error (MERR): This bit is set when
an uncorrectable multiple-bit error occurs on a memory read data
0h
27 transfer. When this bit is set, the address that caused the error
RW/V
and the error syndrome are also logged and they are locked until
this bit is cleared.
0h Error Burst Number (ERR_BURST): Burst number (in BL8) of
26:25
RW/V the error within a chunk.
Error Chunk Number (ERR_CHUNK): Chunk number of the
0h error.
24
RW/V 0 - lower 32B chunk has error if MERR/CERR is set
1 - higher 32B chunk has the error if MERR/CERR is set

170 334818
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Bit Default &

Field Name (ID): Description
Range Access

0h Quad Word ECC Syndrome (SYNDROME_QW): ECC Syndrome

23:16
RW/V for a QW (64 bit) within 32B Address
0h Request Tag (TAG): Read Return Tag matches with the PMI
15:0
RW/V Request Tag which triggered the error log.

5.4.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 14BCh

Contains the values read from D-Unit fuses.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FUSESTAT
RSVD31_16

Bit Default &

Field Name (ID): Description
Range Access

31:16
0h Reserved (RSVD31_16): Reserved.
RO

D-Unit Status (FUSESTAT): D-Unit bits are captured into this register and are
available to be read.
• [0]: fus_dun_ecc_dis.
• [3:1]: fus_dun_max_supported_device_size[2:0].
0h • [4:4]: fus_dun_lpddr3_dis.
15:0
RO/V
• [5:5]: fus_dun_lpddr4_dis.
• [6:6]: reserved.
• [7:7]: fus_dun_ddr3l_dis.
• [15:8]: reserved.

5.4.25 Major Mode Control (D_CR_MMC)—Offset 1524h

Specifies parameters to control read/write major mode operation and transitions.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

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Default: 2B01E518h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0RSVD31_30 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0

RSVD22_18
RAW_WMM

RSVD26

WMMEXIT
RIMPRIO

WIMTHRS

WMMENTRY
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

RAW Conflict Read Priority for WMM Transition

(RAW_WMM): If a conflict read reaches this priority (or greater
depending on access class occupancy), WMM will be triggered to
5h
29:27 unblock the corresponding write. D-Unit will stay in WMM until
RW
corresponding write is issued.
Note: The value in this bit must not be higher than lowest terminal
priority level of each access class.

26
0h Reserved (RSVD26): Reserved.
RO

6h Read Isoch Trigger Priority (RIMPRIO): If any read in the

25:23
RW RPQ is at this programmable priority, RIM is triggered.

22:18
0h Reserved (RSVD22_18): Reserved.
RO

Write Isoch Threshold (WIMTHRS): When the number of

1Eh entries in WPQ is greater than or equal to this value (higher than
17:12
RW WMM entry watermark, less than WPQ size), it triggers write isoch
mode (WIM).
Write Major Mode Exit Watermark (WMMEXIT): When the
14h
11:6 number of entries in WPQ is less than this value, the D-Unit will
RW
switch back to read major mode.
Write Major Mode Entry Watermark (WMMENTRY): When
18h the number of entries in WPQ is greater than or equal to this
5:0
RW value, the D-Unit will switch to write major mode (WMM).
Note: the value must not be set to 0.

5.4.26 Major Mode RD/WR Counter (Set A and B)

(D_CR_MMRDWR_AB)—Offset 1528h
Minimum read and maximum write counter control. This register defines the minimum
number of reads in RMM and maximum number of writes in WMM before a mode
transition happens.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

172 334818
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Default: 1F207C8h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0

RSVD31_26

RSVD13_12
MINRDB
MAXWRB

MINRDA
MAXWRA
Bit Default &
Field Name (ID): Description
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

1Fh Max Writes B (MAXWRB): Maximum number of writes D-Unit

25:20
RW can send in WMM mode before returning to RMM (set B).
8h Min Reads B (MINRDB): Minimum number of reads that has to
19:14
RW be serviced before a switch to WMM is allowed (set B).

13:12
0h Reserved (RSVD13_12): Reserved.
RO

1Fh Max Writes A (MAXWRA): Maximum number of writes D-Unit

11:6
RW can send in WMM mode before returning to RMM (set A).
8h Min Reads A (MINRDA): Minimum number of reads that has to
5:0
RW be serviced before a switch to WMM is allowed (set A).

5.4.27 Major Mode RD/WR Counter (Set C and D)

(D_CR_MMRDWR_CD)—Offset 152Ch
Minimum read and maximum write counter control. This register defines the minumum
number of reads in RMM and maximum number of writes in WMM before a mode
transition happens (sets C and D).

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F207C8h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0
MINRDC
RSVD31_26

RSVD13_12

MAXWRC
MAXWRD

MINRDD

334818 173
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Bit Default &

Field Name (ID): Description
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

1Fh Max Writes D (MAXWRD): Maximum number of writes D-Unit

25:20
RW can send in WMM mode before returning to RMM (set D).
8h Min Reads D (MINRDD): Minimum number of reads that has to
19:14
RW be serviced before a switch to WMM is allowed (set D).

13:12
0h Reserved (RSVD13_12): Reserved.
RO

1Fh Max Writes C (MAXWRC): Maximum number of writes D-Unit

11:6
RW can send in WMM mode before returning to RMM (set C).
8h Min Reads C (MINRDC): Minimum number of reads that has to
5:0
RW be serviced before a switch to WMM is allowed (set C).

5.4.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1530h

Each field of this register defines the initial priority of one access class.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 17C2h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 1 0
AC4IP

AC3IP

AC2IP

AC1IP

AC0IP
RSVD31_15

Bit Default &

Field Name (ID): Description
Range Access

31:15
0h Reserved (RSVD31_15): Reserved.
RO

1h Access Class 4 Initial Priority (AC4IP): Initial priority level of

14:12
RW read requests coming with access class 4.
3h Access Class 3 Initial Priority (AC3IP): Initial priority level of
11:9
RW read requests coming with access class 3.
7h Access Class 2 Initial Priority (AC2IP): Initial priority level of
8:6
RW read requests coming with access class 2.
0h Access Class 1 Initial Priority (AC1IP): Initial priority level of
5:3
RW read requests coming with access class 1.
2h Access Class 0 Initial Priority (AC0IP): Initial priority level of
2:0
RW read requests coming with access class 0.

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5.4.29 Access Class 0 Priority Promotion Control

(D_CR_RD_PROM0)—Offset 1534h
This register defines the priority promotion policy for access class 0. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
next level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F52940h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0
P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
RSVD31_30

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.4.30 Access Class 1 Priority Promotion Control

(D_CR_RD_PROM1)—Offset 1538h
This register defines the priority promotion policy for access class 1. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
associated level and the request has reached its maximum priority.

Access Method

334818 175
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Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 14000000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

Ah Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.4.31 Access Class 2 Priority Promotion Control

(D_CR_RD_PROM2)—Offset 153Ch
This register defines the priority promotion policy for access class 2. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
next level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

176 334818
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P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
RSVD31_30
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.4.32 Access Class 3 Priority Promotion Control

(D_CR_RD_PROM3)—Offset 1540h
This register defines the aging policy for access class 3. Each field of this register
defines the number of CASes that pass before the request is promoted to the next
priority level. A value of 31 indicates the request should never be promoted to the next
level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F29400h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

334818 177
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Bit Default &

Field Name (ID): Description
Range Access

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
5h Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
5h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.4.33 Access Class 4 Priority Promotion Control

(D_CR_RD_PROM4)—Offset 1544h
This register defines the aging policy for access class 3. Each field of this register
defines the number of CASes that pass before the request is promoted to the next
priority level. A value of 31 indicates the request should never be promoted to the next
level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F5294Ah

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.

178 334818
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Bit Default &

Field Name (ID): Description
Range Access

Ah Priority 3 Residency (P3RES): Number of CASes that pass

14:10
RW before a request in this priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
Ah Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.4.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1548h

Specifies when the request with initial priority 0 get promoted to a higher priority level.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 6h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

DEADLINE_THRS
RSVD31_11

Bit Default &

Field Name (ID): Description
Range Access

31:11
0h Reserved (RSVD31_11): Reserved.
RO

Deadline Threshold (DEADLINE_THRS): A requests with initial

priority of 0 will exit priority 0 when its deadline is equal or less
6h
10:0 than this value plus current time. This field does not affect the
RW
priority of any requests in access classes with initial priority bigger
than 0.

5.4.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—

Offset 154Ch
This register controls blocking rules enforced in RMM and WMM.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1800h

334818 179
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3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0

RSVD31_25

RSVD23_20

RSVD15_14
WMM_REG_R1

WMM_PRIO_R4
WMM_PRIO_R3
WMM_PRIO_R2
WMM_PRIO_R1

RMM_REG_R6
RMM_REG_R5
RMM_REG_R4
RMM_REG_R3
RMM_REG_R2
RMM_REG_R1

RSVD7_4

RMM_PRIO_R4
RMM_PRIO_R3
RMM_PRIO_R2
RMM_PRIO_R1
Bit Default &
Field Name (ID): Description
Range Access

31:25
0h Reserved (RSVD31_25): Reserved.
RO

0h WMM Regular Rule 1 (WMM_REG_R1): Disable WMM unsafe

24
RW write page hits block safe write page misses same bank.

23:20
0h Reserved (RSVD23_20): Reserved.
RO

WMM Priority Rule 4 (WMM_PRIO_R4): Disable WMM unsafe

priority 1 read miss block write hit to same bank.
0h
19 Note: This rule does not block the bank that is being blocked by
RW
WMM_PRIO_R3.
Priority rules 1, 3 and 4 should be enabled/disabled together.
WMM Priority Rule 3 (WMM_PRIO_R3): Disable WMM unsafe
priority 1 write hit block write miss to same bank.
0h
18 Note: This rule does not block the bank that is being blocked by
RW
WMM_PRIO_R1.
Priority rules 1,3 and 4 should be enabled/disabled together.
0h WMM Priority Rule 2 (WMM_PRIO_R2): Disable WMM CAS
17
RW block rule.
WMM Priority Rule 1 (WMM_PRIO_R1): Disable WMM unsafe
0h
16 top priority 1 write miss block write hit same bank.
RW
Priority rules 1, 3 and 4 should be enabled/disabled together.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

0h RMM Regular Rule 6 (RMM_REG_R6): Disable RMM unsafe

13
RW write page hits block safe write page misses same bank.
RMM Regular Rule 5 (RMM_REG_R5): Disable RMM unsafe
read page miss block all safe and unsafe write page hit to the
1h
12 same bank.
RW
Note: This field must not be set to 0 (enabled) if RMM_REG_R4 is
also 0.
RMM Regular Rule 4 (RMM_REG_R4): Disable RMM unsafe
1h write page hit block safe read page miss same bank.
11
RW Note: This field must not be set to 0 (enabled) if RMM_REG_R5 is
also 0.

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Bit Default &

Field Name (ID): Description
Range Access

RMM Regular Rule 3 (RMM_REG_R3): Disable RMM unsafe

0h read page hit block safe read and write page miss same bank.
10
RW Note: This rule does not block the bank that is being blocked by
RMM_PRIO_R3 and RMM_PRIO_R1.
0h RMM Regular Rule 2 (RMM_REG_R2): Disable RMM unsafe
9
RW read page empty block safe write page empty same rank.
0h RMM Regular Rule 1 (RMM_REG_R1): Disable RMM unsafe
8
RW read page hit block safe write page hit same rank.

7:4
0h Reserved (RSVD7_4): Reserved.
RO

RMM Priority Rule 4 (RMM_PRIO_R4): Disable RMM unsafe

critical read miss block read and write hit to same bank.
0h
3 Note: This rule does not block the bank that is being blocked by
RW
RMM_PRIO_R3.
Priority rules 1, 3 and 4 should be enabled/disabled together.
RMM Priority Rule 3 (RMM_PRIO_R3): Disable RMM unsafe
critical read hit block read and write miss to same bank.
0h
2 Note: This rule does not block the bank that is being blocked by
RW
RMM_PRIO_R1.
Priority rules 1, 3 and 4 should be enabled/disabled together.
0h RMM Priority Rule 2 (RMM_PRIO_R2): Disable RMM CAS block
1
RW rule.
RMM Priority Rule 1 (RMM_PRIO_R1): Disable RMM unsafe
0h top critical read miss block read and write hit same bank.
0
RW Note: Priority rules 1, 3 and 4 should be enabled/disabled
together.

5.4.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—

Offset 1554h
Self refresh command register to allow sending WAKE and SUSPEND messages to D-
Unit. (Only one bit can be set at a time). Posted writes to this register are not
completed until hardware clears the field.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SUSPEND

WAKE
RSVD31_4

SUSPENDP

RSVD1

334818 181
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Bit Default &

Field Name (ID): Description
Range Access

31:4
0h Reserved (RSVD31_4): Reserved.
RO

SUSPENDP (SUSPENDP): A SUSPENDP message will put the

DRAM into self-refresh mode. The D-Unit will complete servicing
outstanding memory requests and flush all queued Refresh
commands to DRAM before putting the DRAM in self refresh mode.
0h Finally, a PM message will be sent to the PHY. The bit is cleared by
3
RW/V hardware after the PHY indicates the transition requested in the
PM message has been completed. D-Unit will perform an MRW to
MR17 with an opcode as defined by DPMC0.PASR before it places
the DRAM into Self-Refresh.

SUSPEND (SUSPEND): A SUSPEND message will put the DRAM

into self-refresh mode. The D-Unit will complete servicing
outstanding memory requests and flush all queued Refresh
commands to DRAM before putting the DRAM in Self Refresh
0h
2 mode. Finally, a PM message will be sent to the PHY. The bit is
RW/V
cleared by hardware only after the PHY indicates the transition
requested in the PM message has been completed.
Note: When COLDWAKE is set prior of setting this bit the DRAM
will not be placed in SR.

1
0h Reserved (RSVD1): Reserved.
RO

WAKE (WAKE): Take PHY out of PM states and wakes the DRAM
out of self refresh mode. The bit is cleared by hardware only when
0h
0 the DRAM has exited out of self refresh mode and is accessible.
RW/V
Note: When COLDWAKE is set prior of setting this bit the D-Unit
will not send SR exit command and will not set the DCO.IC bit.

5.4.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—

Offset 1580h
LPDDR4 DQS Retraining control register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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DQS_RETRAIN_INT

RSVD15_14

RSVD3_2
DQS_OSC_RT

DQS_RETRAIN_SRX_EN
DQS_RETRAIN_EN
Bit Default &
Field Name (ID): Description
Range Access

DQS Periodic Retraining Interval (DQS_RETRAIN_INT):

0h
31:16 This sets the frequency by which the D-Unit initiates periodic
RW
retraining (in 1x NREFI).

15:14
0h Reserved (RSVD15_14): Reserved.
RO

DQS Oscillator Runtime (DQS_OSC_RT): After D-Unit starts

DQS oscillator, it must wait this amount of time before being able
0h
13:4 to read the value in MR18 and MR19 (in 16x DRAM clocks).
RW
Value in this register must be at least equal to DRAM's MR23
value. + tOSCO.

3:2
0h Reserved (RSVD3_2): Reserved.
RO

DQS Retrain SRX Exit (DQS_RETRAIN_SRX_EN): Enable

0h retraining on SR exit.
1
RW This bit enables LPDDR4 DQS retraining on Self Refresh Exit. If
disabled, D-Unit will not perform retraining on SR exit.
DQS Retrain Enable (DQS_RETRAIN_EN): Periodic retraining
enable:
0h This bit enables periodic DQS retraining. If disabled, D-Unit will
0
RW not perform retraining periodically.
Note: Will be enabled only if DCO.IC is set and refreshes are
enabled in DRF.MINREFRATE.

5.4.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset

1584h
Controls the data bits swizzling crossbar for MR4.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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MR4_BYTE_SEL2
MR4_BIT2_SEL2

MR4_BIT1_SEL2

MR4_BIT0_SEL2

MR4_BYTE_SEL
RSVD31

RSVD27

RSVD23

RSVD19_18

RSVD15

MR4_BIT2_SEL

RSVD11

MR4_BIT1_SEL

RSVD7

MR4_BIT0_SEL

RSVD3_2
Bit Default &
Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

0h MR4 Bit 2 Select 2nd Byte (MR4_BIT2_SEL2): Selects bit 2 of

30:28
RW MR4 data.

27
0h Reserved (RSVD27): Reserved
RO

0h MR4 Bit 1 Select 2nd Byte (MR4_BIT1_SEL2): Selects bit 1 of

26:24
RW MR4 data

23
0h Reserved (RSVD23): Reserved
RO

0h MR4 Bit 0 Select 2nd Byte (MR4_BIT0_SEL2): Selects bit 0 of

22:20
RW MR4 data.

19:18
0h Reserved (RSVD19_18): Reserved
RO

0h MR4 Byte 2 Select (MR4_BYTE_SEL2): Selects byte position of

17:16
RW the MR4 data for second device.

15
0h Reserved (RSVD15): Reserved
RO

14:12
0h MR4 Bit 2 Select (MR4_BIT2_SEL): Selects bit 2 of MR4 data.
RW

11
0h Reserved (RSVD11): Reserved.
RO

10:8
0h MR4 Bit 1 Select (MR4_BIT1_SEL): Selects bit 1 of MR4 data.
RW

7
0h Reserved (RSVD7): Reserved.
RO

6:4
0h MR4 Bit 0 Select (MR4_BIT0_SEL): Selects bit 0 of MR4 data.
RW

3:2
0h Reserved (RSVD3_2): Reserved.
RO

0h MR4 Byte Select (MR4_BYTE_SEL): Selects byte position of

1:0
RW the MR4 data first device.

5.5 Registers Summary

Table 5-5. Summary of pcs_regs_wrapper Registers
Offset Offset Default
Register Name (ID)—Offset
Start End Value

1600h 1603h DRAM Rank Population 0 (D_CR_DRP0)—Offset 1600h 10000000h

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Table 5-5. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset Default
Register Name (ID)—Offset
Start End Value

1608h 160Bh DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1608h 210702CBh

160Ch 160Fh DRAM Timing Register 1A (D_CR_DTR1A)—Offset 160Ch 30481218h

1610h 1613h DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1610h 8C080C30h

1614h 1617h DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1614h 3002EA28h

1618h 161Bh DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1618h 30209149h

161Ch 161Fh DRAM Timing Register 5A (D_CR_DTR5A)—Offset 161Ch 304200C2h

1620h 1623h DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1620h 20100000h

1624h 1627h DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1624h D060C06h

1628h 162Bh DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1628h CC50A18h

162Ch 162Fh D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 162Ch 0h

1630h 1633h D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1630h 0h

1634h 1637h D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1634h 10000028h

1638h 163Bh DRAM Refresh Control (D_CR_DRFC)—Offset 1638h 1750h

163Ch 163Fh D-Unit Scheduler (D_CR_DSCH)—Offset 163Ch 3901C08h

1640h 1643h DRAM Calibration Control (D_CR_DCAL)—Offset 1640h 1057h

1644h 1647h VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 164Ch 20000h

164Ch 164Fh VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 164Ch 0h

Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset

1650h 1653h 6C000008h
1650h

1654h 1657h TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1654h 0h

1658h 165Bh Data Scrambler (D_CR_SCRAMCTRL)—Offset 16A4h 0h

16A4h 16A7h Data Scrambler (D_CR_SCRAMCTRL)—Offset 16A4h 0h

16ACh 16AFh Error Injection Address Register (D_CR_ERR_INJ)—Offset 16ACh 0h

16B0h 16B3h Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 16B0h 0h

16B4h 16B7h Error Log Register (D_CR_ERR_ECC_LOG)—Offset 16B4h 0h

16BCh 16BFh D-Unit Status (D_CR_DFUSESTAT)—Offset 16BCh 0h

1724h 1727h Major Mode Control (D_CR_MMC)—Offset 1724h 2B01E518h

Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset

1728h 172Bh 1F207C8h
1728h

Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—

172Ch 172Fh 1F207C8h
Offset 172Ch

1730h 1733h Access Class Initial Priority (D_CR_ACCIP)—Offset 1730h 17C2h

Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset

1734h 1737h 1F52940h
1734h

Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset

1738h 173Bh 14000000h
1738h

Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset

173Ch 173Fh 0h
173Ch

Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset

1740h 1743h 1F29400h
1740h

Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset

1744h 1747h 1F5294Ah
1744h

1748h 174Bh Deadline Threshold (D_CR_DL_THRS)—Offset 1748h 6h

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Table 5-5. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset Default
Register Name (ID)—Offset
Start End Value

174Ch 174Fh Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 174Ch 1800h

1754h 1757h DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1754h 0h

1780h 1783h DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1780h 0h

1784h 1787h MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1784h 0h

5.5.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1600h

Rank configuration register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10000000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BLMODE

DWID
ADDRDEC

CASWIZZLE
DRAMDEVICE_PR

DRAMTYPE

RSVD18_16

RSVD3
DDMEN
RKEN1
RKEN0
ECCEN

BAHEN

RSVD13_9

DDEN
RSIEN

Bit Default &

Field Name (ID): Description
Range Access

DRAM Device Per Rank (DRAMDEVICE_PR): Specifies the number of DRAM

devices that are ganged together to form a single rank.
• 00: 1 DRAM device in each rank.
0h • 01: 2 DRAM devices in each rank.
31:30
RW
• 10: 4 DRAM devices in each rank.
• 11: 8 DRAM devices in each rank.
Note: The actual number of devices is one more than the value programmed when
ECC is enabled.

Address Decode (ADDRDEC): Specifies the address mapping to be used:

• 00: 1KB (A).
1h
29:28 • 01: 2KB (B).
RW
• 10: 4KB (C).
• 11: Reserved.

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Bit Default &

Field Name (ID): Description
Range Access

Burst Length Mode (BLMODE):

• 000: Fixed BL8.
• 001: Onthefly BL8.

0h
• 010: Fixed BL16.
27:25
RW • 011: Onthefly BL16.
• 100: Fixed BL32.
• 101: Onthefly BL32.
• 110-111: Reserved.
DRAM Type (DRAMTYPE):
• 000: DDR3L.
• 001: LPDDR3.
0h • 010: LPDDR4.
24:22
RW
• 011: Reserved.
• 100: Reserved.
• 101-111: Reserved.

ECC Enable (ECCEN):

• 0: ECC is disabled.
0h
21
RW • 1: ECC is enabled.
This bit determines if the D-Unit treats the PMI BE_ECC bits as ECC bits or Byte
Enable. This should only be used in configurations that support ECC (DDR3L).

CA Swizzle Type (CASWIZZLE):

• 00: uniDIMM/SODIMM.
0h
20:19 • 01: BGA.
RW
• 10: BGA mirrored (LPDDR3 Only).
• 11: UDIMM (DDR3L Only).

18:16
0h Reserved (RSVD18_16): Reserved.
RO

Bank Address Hashing Enable (BAHEN): See Address Mapping section for full
description.
0h
15 • 0: Bank Address Hashing disabled.
RW
• 1: Bank Address Hashing enabled.
Rank Select Interleave Enable (RSIEN): See Address Mapping section for full
description.
0h
14 • 0: Rank Select Interleaving disabled.
RW
• 1: Rank Select Interleaving enabled.

13:9
0h Reserved (RSVD13_9): Reserved.
RO

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Bit Default &

Field Name (ID): Description
Range Access

DRAM Device Density (DDEN): Density of the DRAM devices populated on Ranks 0
and 1.
• 000: 4 Gb.
• 001: 6 Gb.
0h • 010: 8 Gb.
8:6
RW
• 011: 12 Gb.
• 100: 16 Gb.
• 101-111: Reserved.
Note: For LPDDR4 this value is the die density.

DRAM Device Data Width (DWID): Data width of the DRAM device populated on
Ranks 0 and 1.
• 00: x8.
0h
5:4 • 01: x16.
RW
• 10: x32.
• 11: x64.

3
0h Reserved (RSVD3): Reserved.
RO

Dual Data Mode Enable (DDMEN):

• 0: PMI Dual Data Mode is disabled in D-Unit, full cacheline
0h
2 read and writes go through a single D-Unit.
RW
• 1: PMI Dual Data Mode is enabled, only half cacheline read/
writes go through a single D-Unit.
0h Rank Enable 1 (RKEN1): Enable Rank 1: Must be set to 1 to
1
RW enable use of this rank.
Rank Enable 0 (RKEN0): Enable Rank 0: Must be set to 1 to
0h
0 enable use of this rank.
RW
Note: Setting this bit to 0 is not a functional mode.

5.5.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1608h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 210702CBh

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 1
TCKCKEH

TXSDLL

TXSR

TRPPB
TRCD

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Bit Default &

Field Name (ID): Description
Range Access

Valid Clocks Before CKE High [tCKCKEH/tCSCKEH/tCKSRX] (TCKCKEH):

Number of valid clocks before CKE high (in DRAM clocks).
• LPDDR4: The value in this register covers both tCKCKEH and
tCSCKEH.
• DDR3L/LPDDR3: The value covers tCKSRX which is defined as
the number of valid DRAM clocks that have to toggle before
10h
31:25 the issuing of the Self Refresh Exit SRX. This value is also used
RW
if the clock frequency is changed or the clock is stopped or
tristated during Power Down i.e. the number valid DRAM
clocks that have to toggle before the issuing of the Power
Down Exit PDX command.
tCKCKEH can be used to compensate for clock stabilization delays in the
motherboard. Note: D-unit hardware enforces minimum of two SPID clock before
CKEH, any value in this register is the additional time.

Exit Self-Refresh to Valid Commands Requiring a Locked

DLL Delay [tXSDLL] (TXSDLL): D-Unit waits max(tXSR+tZQCL/
tZQCS, tXSDLL) before allowing traffic to DRAM (in 64 x DRAM
8h Clocks).
24:21
RW LPDDR3/LPDDR4: tXSDLL = 0.
DDR3L: tXSDLL = tDLLK = 512 Clocks = 8 x 64 DRAM Clocks.
Note: In the equation above, tZQCL/tZQCS = 0 if no ZQ is
performed on SR exit.
Exit Self-Refresh to Valid Command Delay [tXS/tXSR]
(TXSR): DDR3L: tXS - Delay between Self Refresh Exit SRX to
70h
20:12 any DRAM Command not requiring DLL Lock.
RW
LPDDR: tXSR - Delay between Self Refresh Exit SRX to any DRAM
Command. (in DRAM clocks).
Activate RAS to CAS Command Delay [tRCD] (TRCD):
Specifies the delay between a DRAM Activate command and a
Bh
11:6 DRAM Read or Write command to the same bank (in DRAM
RW
clocks).
Note: Derating adds 1.875ns to this timing.
Precharge to Activate Command Delay of a Single Bank
[tRPpb] (TRPPB): Specifies the delay between a DRAM
Precharge command and a DRAM Activate command to the same
Bh
5:0 bank (in DRAM Clocks).
RW
Note : this CR should be constrained to a minimum of 4 in LPDDR3
and minimum of 8 in LPDDR4.
Note: Derating adds 1.875ns to this timing.

5.5.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 160Ch

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 30481218h

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3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0

TXP

RSVD26

TZQCL

TZQLAT
TZQCS
Bit Default &
Field Name (ID): Description
Range Access

Exit Power Down to Next Command Delay [tXP] (TXP):

Specifies the delay from the DRAM Power Down Exit (PDX)
6h
31:27 command to any valid command (in DRAM clocks).
RW
Note: The value in this field must be programmed to tXPDLL when
Slow Exit Mode Power-down is enabled for DDR3L.

26
0h Reserved (RSVD26): Reserved.
RO

ZQ (long) Calibration Time [tZQCL/tZQCAL] (TZQCL):

• LPDDR3/DDR3L: tZQCL/tZQoper: Specifies the delay between
the DRAM ZQ Calibration Long (ZQCL) command and any
DRAM command during normal operation.
120h
25:14 • LPDDR4: tZQCAL: ZQ Calibration time (in DRAM clocks).
RW
Note: This field defines the ZQ Calibration Long delay during normal operation. It is
not the same as tZQinit which uses the same ZQCL command but the delay is longer.
tZQinit applies only during poweron initialization of the DRAM devices and tZQoper
applies during normal operation. BIOS executes the DRAM initialization sequence so
it has to ensure tZQinit is met and not the D-Unit.

ZQ Short Calibration Time [tZQCS] (TZQCS): ZQCS to any

DRAM Command Delay: Specifies the delay between the DRAM ZQ
48h Calibration Short (ZQCS) command and any DRAM command (in
13:6
RW DRAM clocks).
DDR3L and LPDDR3 only. LPDDR4 does not support ZQCS
command
ZQ Latch Time [tZQLAT] (TZQLAT): Specifies the delay
18h between the DRAM ZQ Calibration Latch command and any DRAM
5:0
RW command (in DRAM clocks).
LPDDR4 only.Not used in DDR3L/LPDDR3.

5.5.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1610h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 8C080C30h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0

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TCKE
RSVD22_21

RSVD16

NREFI
NRFCAB
Bit Default &
Field Name (ID): Description
Range Access

All Bank Refresh Cycle Time [tRFCab] (NRFCAB): Specifies

118h
31:23 the delay between the REFab command to the next valid
RW
command. (in DRAM clocks)

22:21
0h Reserved (RSVD22_21): Reserved.
RO

4h CKE Minimum Pulse Width [tCKE] (TCKE): Specifies the

20:17
RW minimum time from CKEL to CKEH (in DRAM clocks).

16
0h Reserved (RSVD16): Reserved.
RO

Refresh Interval Time [tREFI] (NREFI): Specifies the average

C30h time between refresh commands. JEDEC Base Refresh Interval
15:0
RW time (in DRAM clocks).
Note: D-Unit will ignore the 2 LSBs of this field.

5.5.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1614h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 3002EA28h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 1 0 1 0 0 0
TCWL

TWMWSB
TCMD
TRTP

TCCD_INC

TWTP

Bit Default &

Field Name (ID): Description
Range Access

Read to Precharge Delay [tRDPRE] (TRTP): Specifies the minimum delay

between the DRAM Read and Precharge commands to the same bank (in DRAM
clocks).
6h
31:27 • LPDDR3 Equation: = BL/2 + tRTP - 4.
RW
• LPDDR4 Equation: = BL/2 + Max (8, tRTP) - 8.
• DDR3L Equation: = tRTP.

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Bit Default &

Field Name (ID): Description
Range Access

CAS to CAS Command Delay Adder (TCCD_INC): Specifies

0h the number of clocks to be added to turnaround times (for Stretch
26:20
RW Mode). It increases delay between Read to Read or Read to Write
commands (in 4 x DRAM clocks).
Write to Precharge Command Delay [tWRPRE] (TWTP): Specifies the minimum
delay between the DRAM Write command and the Precharge command to the same
17h bank (in DRAM clocks).
19:13
RW • LPDDR3/LPDDR4 Equation: tWTP = BL/2 + WL + tWR + 1.
• DDR3L Equation: tWTP = BL/2 + CWL + tWR.
DRAM Command Valid Duration (TCMD): Specifies the number of DRAM clocks a
command is held valid on the DRAM Address and Control buses. 1N is the DDR3 basic
requirement. 2N is the extended mode for board signal integrity.
• 0h: Reserved.
1h
12:11
RW • 1h: 1 DRAM Clock (1N).
• 2h: 2 DRAM Clocks (2N).
• 3h: Reserved.
Note: DDR3L only. tCMD must be set to 1N for LPDDR3/LPDDR4.

Write Latency [WL/CWL] (TCWL): The delay between the

8h
10:6 internal write command and the availability of the first word of
RW
DRAM input data (in DRAM clocks).
Write CAS to Masked Write CAS Delay Same Bank (TWMWSB): Specifies the
minimum delay between DRAM Write command to Masked Write command to same
bank (in DRAM clocks).
28h
5:0 • LPDDR4 Equation: tWMWSB = tCCDMW (BL16) or tCCDMW +
RW
8 (BL32).
Note: Masked Write operation in LPDDR4 is always BL16. D-Unit applies this timing
for same rank as well as same bank.

5.5.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1618h

Specifies DRAM timings parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 30209149h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1
TFAW

TWRDR

TRWDR

TWWDR

TRRDR

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Bit Default &

Field Name (ID): Description
Range Access

Four Bank Activate Window [tFAW] (TFAW): A rolling

30h timeframe in which a maximum of four Activate commands can be
31:24
RW issued to the same rank. This is to limit the peak current draw
from the DRAM devices (in DRAM clocks).
Write to Read DQ Delay Different Ranks (TWRDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Read data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tWRDR = WL + tDQSSmax + BL/2 +
tWPST - (RL + tDQSCKmin - tRPRE).
8h
23:18
RW • LPDDR4 Equation: tWRDR = WL - RL + BL/2 + 4 -
tDQSCKmin.
• DDR3L Equation: tWRDR = CWL + tDQSSmax + BL/2 +
tWPST - (CL + tDQSCKmin - tRPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.

Read to Write DQ Delay Different Ranks (TRWDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Write data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tRWDR = RL + tDQSCKmax + BL/2 +
tRPST - (WL + tDQSSmin - tWPRE).
9h
17:12 • LPDDR4 Equation: tRWDR = RL + tDQSCKmax + BL/2 - (WL -
RW
2).
• DDR3L Equation: tRWDR = CL + tDQSCKmax + BL/2 + tRPST
- (CWL + tDQSSmin - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be adjusted by tODTon.
Note: For DDR3L using ODT, this latency may need to be increased by one clock.

Write to Write DQ Delay Different Ranks (TWWDR): Specifies the delay from
the start of a Write data burst of one rank to the start of a Write data burst of a
different rank (in DRAM clocks).
• LPDDR3 Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin
5h + tWPRE.
11:6
RW
• LPDDR4 Equation: tWWDR = BL/2 + 4 - tDQSSmin.
• DDR3L Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin +
tWPRE.
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.

Read to Read DQ Delay Different Ranks (TRRDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Read data burst of a different
rank (in DRAM clocks).

5:0
9h • LPDDR3/4 Equation: tRRDR = BL/2 + tDQSCKmax -
RW tDQSCKmin + tRPRE.
• DDR3L Equation: tRRDR = BL/2 + tRPST + tDQSCKmax -
tDQSCKmin + tRPRE + 1.

5.5.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 161Ch

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

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Default: 304200C2h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0

TDERATE_INC
RSVD26

TWWSR

TRRSR

TWRSR

TRWSR
TRRD

Bit Default &

Field Name (ID): Description
Range Access

Row Activation to Row Activation Delay [tRRD] (TRRD):

Specifies the minimum delay in DRAM clocks between two DRAM
6h
31:27 Activate commands to the same rank but different banks (tRC is
RW
the minimum delay between activations of the same bank).
Note: Derating adds 1.875ns to this timing.

26
0h Reserved (RSVD26): Reserved.
RO

Derate Increment (TDERATE_INC): Specifies the additional

delay that is added to DRAM timing when indicated by MR4 status.
0h (in DRAM clocks)
25:23
RW LPDDR3/LPDDR4: Value is 1.875ns.
Note: The value in this register is only added to these timing
parameters: tRCD, tRAS, tRP and tRRD.
Write to Write DQ Delay Same Rank (TWWSR): Specifies the
10h delay from a DRAM Write to another Write command of the same
22:18
RW rank (in DRAM clocks).
LPDDR3/LPDDR4/DDR3L Equation: tRRSR = tCCD.
Read to Read DQ Delay Same Rank (TRRSR): Specifies the
10h delay from a DRAM Read to another Read command of the same
17:13
RW rank (in DRAM clocks).
LPDDR3/LPDDR4/DDR3L Equation: tRRSR = tCCD.
Write to Read DQ Delay Same Rank (TWRSR): Specifies the delay from a DRAM
Read to Write command of the same rank (in DRAM clocks).

3h • LPDDR3/LPDDR4 Equation: tWRSR = WL + tDQSSmax + BL/2

12:6 + tWTR.
RW
• DDR3L Equation: tWRSR = CWL + tDQSSmax + BL/2 +
tWPST + tWTR.
Read to Write DQ Delay Same Rank (TRWSR): Specifies the delay from a DRAM
Read to a Write command of the same rank (in DRAM clocks).
• LPDDR3/LPDDR4 Equation: tRWSR = RL + tDQSCKmax + BL/
2h 2 - WL + tWPRE.
5:0
RW
• DDR3L Equation: tRWSR = CL + tDQSCKmax + BL/2 + tRPST
- (CWL +tDQSSmin - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Note: For DDR3L using ODT, this latency may need to be increased by one clock.

194 334818
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5.5.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1620h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 20100000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD7
TPSTMRRBLK
OREFDLY

TCKCKEL

MNTDLY

TPREMRBLK
Bit Default &
Field Name (ID): Description
Range Access

20h Opportunistic Refresh Idle Timer (OREFDLY): Rank idle

31:24
RW period that defines an opportunity for refresh (in DRAM clocks).
Valid Clocks After CKE Low [tCKELCK/tCKELCS/tCPDED/tCKSRE]
(TCKCKEL): Specifies the amount of time that DRAM clocks need to toggle after CKE
goes low (in DRAM Clocks).
• For LPDDR3, this covers tCPDED.
2h
23:19
RW • For LPDDR4, this covers both tCKELCK and tCKELCS.
• For DDR3L, this is tCKSRE.
Note: D-Unit hardware enforces minimum of one SPID clocks after CKEL, any value in
this register is the additional time.

Maintenance Operation Delay (MNTDLY): When a critical read

request is pending in RPQ and a maintenance operation (MRR,
0h ZQCal, Ref, etc, panic refresh is an exception to this delay.) needs
18:15
RW to be performed, D-Unit waits this amount of time before
performing the maintenance operation to allow for some high
priority requests to be issued (in 4x SPID clocks).
Mode Register Read to Any Command Delay
(TPSTMRRBLK): Specifies the quiet time after issuing MRR
command (in DRAM Clocks).
0h
14:8 Note: D-Unit treats MRR as a read and always applies relevant
RW
turnaround times, any value programmed in this CR must be
greater than those turnaround times for D-Unit to enforce any
additional time from MRR to the next read/write.

7
0h Reserved (RSVD7): Reserved.
RO

334818 195
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Any Command to Mode Register Read/Write Delay

(TPREMRBLK): Specifies the quiet time before issuing MRR/MRW
command. (in DRAM clocks).
0h
6:0 Note: D-Unit treats MRR as a read and always applies relevant
RW
turnaround times, any value programmed in this CR must be
greater than those turnaround times for D-Unit to enforce any
additional time from previous read/writes.

5.5.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1624h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: D060C06h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0

RSVD8_7
TRDPDEN
TWRPDEN
TRPAB

TPSTMRWBLK

TRAS
Bit Default &
Field Name (ID): Description
Range Access

All Bank Precharge to Activate Command Delay [tRPab] (TRPAB): Specifies

the delay between a DRAM Precharge All Bank command and a DRAM Activate
command (in DRAM Clocks). Note: This CR should be constrained to a minimum of 4
3h in LP3 and minimum of 8 in LP4. Note: Derating adds 1.875ns to this timing.
31:26
RW
• For LPDDR, tRPpb = tRP, tRPab = tRP + 3ns.
• For DDR3L 8ch tRPpb = tRPab = tRP.
Mode Register Write to any Command Delay [tMRD/tMRW]
2h (TPSTMRWBLK): Specifies the quiet time after issuing MRW
25:23
RW command (in 8 x DRAM clocks).
Note: This time covers for both tMRD and tMRW.
Write Command to Power Down Delay [tWRPDEN]
6h (TWRPDEN): Specifies the minimum time between a write
22:16
RW command to PowerDown command (in DRAM clocks).
Must be at least equal to tWR + tCCD + tWL + 2.
Read Command to Power Down Delay [tRDPDEN]
6h (TRDPDEN): Specifies the minimum time between a read
15:9
RW command to PowerDown command (in DRAM clocks).
Must be at least equal to CL/RL + tDQSCKmax + tCCD + tRPST.

196 334818
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Bit Default &

Field Name (ID): Description
Range Access

8:7
0h Reserved (RSVD8_7): Reserved.
RO

Row Activation Period [tRAS] (TRAS): Specifies the minimum

6h delay between the DRAM Activate and Precharge commands to
6:0
RW the same bank (in DRAM clocks).
Note: Derating adds 1.875ns to this timing.

5.5.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1628h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: CC50A18h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0
TCKESR

LPMDRES

LPMDTOCKEDLY

PWDDLY
CKETOLPMDDLY

Bit Default &

Field Name (ID): Description
Range Access

Minimum Self-Refresh Time [tSR/tCKESR] (TCKESR):

3h
31:26 Specifies the minimum time that DRAM should remain in SR (in
RW
DRAM clocks).
Minimum Low Power Mode Residency (LPMDRES): Specifies
6h
25:21 the minimum time that PHY should remain in LPMode (in DRAM
RW
clocks).
Low Power Mode Exit to Clock Enable Delay
(LPMDTOCKEDLY): Specifies the minimum time between the LP
Ah
20:15 Mode exit to the CK stop/tristate deassertion and powerdown exit
RW
(in DRAM clocks).
Note: Must be equal to t_idle_latency and less than 0x3C.
Clock Stop to Low Power Mode Delay (CKETOLPMDDLY):
Specifies the time between CK stop/tristate to the Low Power
Ah Mode entry. This timing parameter is used to delay Low Power
14:8
RW Mode entry (in DRAM clocks).
Note: Must be at least equal to t_idle_length parameter and less
than 0x7C.

334818 197
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Power Down Idle Timer (PWDDLY): This is a non-JEDEC

18h
7:0 timing parameter used to delay powerdown entry (in DRAM
RW
clocks).

5.5.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset

162Ch
Specifies the parameters to control DRAM ODT.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDODTSTART

WRODTSTART
RDODTSTOP

WRODTSTOP

RSVD4
RSVD31_30

R1WRODTCTL

R0WRODTCTL

RSVD23_18

RSVD13
R1RDODTCTL
R0RDODTCTL

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

Rank 1 Read ODT Control (R1RDODTCTL): Specifies the

behavior of ODT signals when a Read command is issued to Rank
0h 1.
29
RW 0 - Read ODT is disabled for Rank 1
1 - Assert ODT to for Rank 0 (non-targeted Rank)
Note: This register should be set to 0 for LPDDR3 devices
Rank 0 Read ODT Control (R0RDODTCTL): Specifies the
behavior of ODT signals when a Read command is issued to Rank
0h 0.
28
RW 0 - Read ODT is disabled for Rank 0
1 - Assert ODT to for Rank 1 (non-targeted Rank)
Note: This register is reserved for LPDDR3 devices
Rank 1 Write ODT Control (R1WRODTCTL): Specifies the
behavior of ODT signals when a Write command is issued to Rank
1.
0h 00 - Write ODT is disabled
27:26
RW 01 - Assert ODT to Rank 0 (non-targeted Rank)
10 - Assert ODT to Rank 1 (targeted Rank)
11 - Assert ODT to Rank 0 and Rank 1
Note: 10 and 11 are reserved values for LPDDR3

198 334818
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Bit Default &

Field Name (ID): Description
Range Access

Rank 0 Write ODT Control (R0WRODTCTL): Specifies the

behavior of ODT signals when a Write command is issued to Rank
0.
0h 00 - Write ODT is disabled
25:24
RW 01 - Assert ODT to Rank 0 (targeted Rank)
10 - Assert ODT to Rank 1 (non-targeted Rank)
11 - Assert ODT to Rank 0 and Rank 1
Note: 10 and 11 are reserved values for LPDDR3

23:18
0h Reserved (RSVD23_18): Reserved.
RO

Read ODT assertion to de-assertion delay (DDR3L Only)

(RDODTSTOP): Specifies Read ODT assertion to ODT de-assert
0h
17:14 delay (in DRAM clocks).
RW
DDR3L Equation: RDODTSTOP = DOCRx.WRODTSTOP (subtract 1
if DOCRx.WRODTSTART = 1 in 2N mode).

13
0h Reserved (RSVD13): Reserved.
RO

Read command to ODT assertion delay (DDR3L Only)

(RDODTSTART): Specifies Read ODT assertion delay after Read
0h Command (in DRAM clocks).
12:9
RW DDR3L Equation: RDODTSTART = CL CWL (add 1 if
DOCRx.WRODTSTART = 0 in 2N mode).
The max value for this CR is 0xE
Write ODT Assertion to De-assertion Delay (WRODTSTOP):
Specifies number of clocks after ODT assertion that D-Unit
0h deasserts ODT signal (in DRAM clocks).
8:5
RW LPDDR3 Equation: WRODTSTOP = RU(tODTon(max)/tCK) +
RU((tDQSSmax+tWPST)/tCK) + BL/2 - RD(tODToffmin/tCK)
DDR3L Equation: WRODTSTOP >= 6

4
0h Reserved (RSVD4): Reserved.
RO

Write command to ODT assertion delay (WRODTSTART):

Specifies number of clocks after Write command that D-Unit
asserts ODT signal (in DRAM clocks).
LPDDR3 Equation: WRODTSTART = WL - RU(tODTon(max)/tCK)
0h DDR3L Equation: WRODTSTART = 0 Note: DDR3 spec requires
3:0
RW ODT to be asserted high when the DRAM Write command is
issued. In DDR3L 2N mode the value can be set to 0 to assert ODT
one DRAM clock earlier than the Write Command (WR) or set to 1
to assert at the same clock as command (CS assertion).
The max value for this CR is 0xE

5.5.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—

Offset 1630h
Specifies the parameters to control D-Unit power management features.

Access Method

334818 199
 MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SREDLY
SUSPMOP
RSVD31_29

DYNPMOP
RSVD23
SRPMCLKW

DYNSREN
Bit Default &
Field Name (ID): Description
Range Access

31:29
0h Reserved (RSVD31_29): Reserved.
RO

SUSPEND/SUSPENDP Power Management Message Opcode

(SUSPMOP): DDRIO PHY Power Mode Opcode: After the D-Unit
has placed the DRAM devices in Self Refresh/PASR mode as the
result of a SUSPEND/SUSPENDP message, it sends this 5-bit value
0h
28:24 to the DDRIO PHY to tell it which power saving mode it should
RW
enter.
Changing this register value while in SUSPEND will have no effect.
Note: This opcode cannot be a PM state where it disables PHY PLLs
i.e PM7 in LPDDR PHY.

23
0h Reserved (RSVD23): Reserved.
RO

PM Message Wait for Clock Gate Enable (SRPMCLKW): Specifies when it is safe
to send PM message to the PHY. When enabled, D-Unit waits for SPID Clock to
deassert before sending a PM message on SR entry.

0h • 0: D-Unit will not wait for SPID_clk to deassert before sending

22
RW the PM message to PHY.
• 1: D-Unit will wait for SPID_clk to deassert before sending PM
message to the PHY.
Note: The value must be 1 when DYNPMOP = 7h.

Dynamic Self-Refresh Power Management Message Opcode

(DYNPMOP): DDRIO PHY Power Mode Opcode: After the D-Unit
has placed the DRAM devices in Self Refresh mode as the result of
0h
21:17 a Dynamic Self-Refresh, it sends this 5bit value to the DDRIO PHY
RW
to tell it which power saving mode it should enter.
Changing this register value while in self-refresh will only change
the PM state for the next entry in DynSR.
Dynamic Self-Refresh Enable (DYNSREN): When set to 1, the
D-Unit will automatically control DRAM Self Refresh entry and exit
based on interface state and requests in pending queues. When
0h
16 there is no pending request in the queues and PMI is idle, then the
RW
D-Unit will place the DRAM devices in Self Refresh mode. The
DRAM devices will be brought out of Self-Refresh when idle
conditions don't hold.

200 334818
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Bit Default &

Field Name (ID): Description
Range Access

Self-Refresh Entry Delay (SREDLY): Specifies the minimum

0h
15:0 time the D-Unit will wait before it enters Dynamic Self-Refresh
RW
mode when idle (in 16x DRAM Clocks).

5.5.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—

Offset 1634h
Specifies the parameters to control D-Unit power management features.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10000028h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
CSTRIST

CMDTRIST

PCLSTO

ODTTRIST
RPTCLKGTDIS

CLKGTDIS

PCLSTODIS
SBEPCLKGTDIS

LPMODEOP
RSVD31_30

RSVD6

ENCKSTP

DISPWRDN
PASR

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

D-Unit Repeaters Clock Gate Disable (RPTCLKGTDIS):

Setting this bit to 0 allows majority of the repeaters between D-
Unit and PHY to clock gate when there is no activity in order to
save power.
0h 0 - Enable Repeaters clock gating, 1 - Disable Repeaters clock
29
RW gating.
Note: This is a de-feature bit and should be set to 0 for normal
operation.
Note: The value should only change after DRAM Timing Registers
(DTR) are programmed.
IOSF-SB End Point Clock Gate Disable (SBEPCLKGTDIS):
Setting this bit to 0 enables the clock gating of IOSF-SB End
Points in D-Unit and CPGC when there is no IOSF-SB activity in
order to save power.
1h 0 - Enable IOSF-SB EP clock gating, 1 - Disable IOSF-SB clock
28
RW gating.
Note: This is a de-feature bit and should be set to 0 for normal
operation.
Note: The value should only change after DRAM Timing Registers
(DTR) are programmed.

334818 201
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Local Clock Gate Disable (CLKGTDIS): Setting this bit to 0 allows the majority of
the D-Unit clocks to be gated off when there is no activity in order to save power.
When set to 1, D-Unit clockgating is disabled.
0h • 0: Enable.
27
RW
• 1: Disable.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.

Chip Select Tristate Enable (CSTRIST):

• 0: The DRAM CS pins associated with the enabled ranks are
0h never tristated.
26
RW
• 1: The DRAM CS pins are tristated when DRAM clock is
stopped or tristated.
Note: CS is not tristated when global tristate flow is disabled (DCBR.TRISTDIS = 1).

Command/Address Tristate (CMDTRIST):

• 00: The DRAM CA pins are never tristated.
• 01: The DRAM CA pins are only tristated when all enabled CKE
0h
25:24 pins are low.
RW
• 10: The DRAM CA pins are tristated when not driving a valid
command.
• 11: Reserved
Partial Array Self-Refresh Segment Mask (PASR): This is the
0h
23:16 Segment Mask used for the MRW to enable PASR during
RW
SUSPENDP (Partial Array Self Refresh entry).
Page Close Timeout Period (PCLSTO): Specifies the time from
0h the last access of a DRAM page until that page is scheduled to
15:8
RW close by sending a Precharge command to DRAM (in 16 x DRAM
clocks).
Page Close Timeout Disable (PCLSTODIS): When disabled, D-Unit will not close
the DRAM page when idle.
0h • 0: Enable page close timer.
7
RW
• 1: Disable page close timer (Used during DRAM init and
DDRIO training).

6
0h Reserved (RSVD6): Reserved.
RO

ODT Tristate Enable (ODTTRIST):

• 0: The DRAM ODT pins associated with the enabled ranks are
1h never tristated.
5
RW
• 1: DRAMs ODT pins are tristated when DRAM clock is stopped
or tristated.
Note: ODT is not tristated when global tristate flow is disabled (DCBR.TRISTDIS = 1)

202 334818
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Bit Default &

Field Name (ID): Description
Range Access

Clock Stop/Tristate Enable (ENCKSTP): Enable/Disable CK Stop/Tristate During

Power down.
• 00: Disable CK Stop/Tristate During Power down.
1h • 01: Enable CK Stop During Power down.
4:3
RW
• 10: Enable CK Tristate During Power down.
• 11: Reserved
Note: CK is not stopped or tristated when global tristate flow is disabled
(DCBR.TRISTDIS = 1).

Low Power Mode Opcode (LPMODEOP): D-Unit will send the

value in this register after it has entered Powerdown Mode and has
0h stopped/tristated the clock.
2:1
RW 00: Disable LPMode.
Note: LPMODE entry is not possible when global tristate flow is
disabled (DCBR.TRISTDIS = 1).
Disable Power Down (DISPWRDN): Setting this bit to 1 disables dynamic control
of DRAM Power-Down entry and exit by keeping the CKE pins driven high. BIOS may
set it to 1 during DRAM initialization and DDRIO training. This bit should be set to 0
for normal operation.
• 0: The D-Unit dynamically controls the CKE pins to place the
0h DRAM devices in Power Down mode and bring them out of
0
RW Power Down mode.
• 1: The D-Unit constantly drives the CKE pins high to keep the
DRAM devices from entering Power Down mode when ranks
are idle.
Note: This bit is overridden if CKEMODE = 1. This bit does not control CKE behavior
on SR entry/exit.

5.5.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1638h

Specifies the parameters to control scheduling of refresh commands.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1750h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 0
DISREFDBTCLR
REFSKWDIS

EXTRAREFDBT

MINREFRATE

OREFDIS
RSVD31_22

RSVD19_18

RSVD17_16

REFWMPNC

REFWMHI

RSVD3_1

334818 203
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

31:22
0h Reserved (RSVD31_22): Reserved.
RO

Disable Refresh Debt Clear (DISREFDBTCLR): When set, D-Unit will not clear
refresh debt before Self Refresh SR Entry:

0h • 0: D-Unit sends all postponed REF commands to DRAM before

21 it enters Self Refresh.
RW
• 1: D-Unit enters SR without clearing the Refresh Debt (for
Debug only).
Refresh Skew Disable (REFSKWDIS): Disables Skewing of Refresh Counting
between Ranks. Each rank has its own refresh counter. By default incrementing these
refresh counters are skewed by 1/2 the tREFI period. Setting this bit to a 1 disables
this feature and all refresh counters will increment at the same time per tREFI period.
Skewing the tREFI counters can improve performance since traffic to all ranks does
not have to be blocked to perform refresh.
0h
20
RW • 0: Incrementing the refresh counters are skewed by 1/2 tREFI
period.
• 1: All refresh counters will increment at the same time per
tREFI period.

19:18
0h Reserved (RSVD19_18): Reserved.
RO

17:16
0h Reserved (RSVD17_16): Reserved.
RO

Extra Refresh Debit (EXTRAREFDBT): When set to 1, D-Unit

0h
15 adds one extra refresh debit (for a total of two) on Self-refresh
RW
exit.
Minimum Refresh Rate (MINREFRATE): Ensures that refresh rate never drops
below a certain limit regardless of TQ polling.
• 000: Disable tREFI counter and stop issuing refresh
commands.
• 001: 0.25x refresh rate (i.e. 4x tREFI same as no limit).
1h • 010: 0.5x refresh rate (i.e. 2x tREFI).
14:12
RW • 011: 1x refresh rate (i.e. 1x tREFI).
• 100: 2x refresh rate (i.e. 0.5x tREFI).
• 101: 4x refresh rate (i.e. 0.25x tREFI).
• 110: 4x refresh rate with derating forced on i.e. 0.25x tREFI.
• 111: Reserved.
Refresh Panic Watermark (REFWMPNC): When the Refresh
counter per rank is greater than this value, the D-Unit will send a
7h REF command to the rank regardless of pending requests.
11:8
RW Note: REFWMPNC must be greater than or equal to REFWMHI and
greater than 2, Max Value must be less than 8 to not violate
9xtREFI JEDEC requirement.

204 334818
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Bit Default &

Field Name (ID): Description
Range Access

Refresh High Watermark (REFWMHI): When the Refresh

counter per rank is greater than this value, the D-Unit will send a
5h REF command to the rank if there is no critical priority requests in
7:4
RW the pending queues.
Note: Value must be greater or equal to 1 and less than or equal
to REFWMPNC.

3:1
0h Reserved (RSVD3_1): Reserved.
RO

Opportunistic Refresh Disable (OREFDIS): Disable opportunistic scheduling of

refresh.
• 0: D-Unit will send a REF command only if there is no pending
0h request to that rank.
0
RW • 1: D-Unit will not send any opportunistic refreshes. Refresh
commands are only sent when the refresh counter is greater
than REFWMHI.
Note: When set, DISREFDBTCLR must also be set to be able to enter SR.

5.5.15 D-Unit Scheduler (D_CR_DSCH)—Offset 163Ch

Specifies parameters to control scheduling of commands to DRAM.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 3901C08h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0
WPQCOUNT

RPQCOUNT

BLKRDBF_ADD_RDDATA_CR

INORDERMODE

TMWR_TA_DELTA
BGF_EARLY_RDDATA_VALID

SPID_EARLY_RDDATA_VALID

RSVD15_14
RSVD31

BYPASSEN
BLKRDBF

STRETCHMODE

Bit Default &

Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

334818 205
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

BGF Early Read Data Valid (BGF_EARLY_RDDATA_VALID): Specifies the

number of clocks the D-Unit sends the read data valid through the BGF earlier as
compared to the data.

0h • 00: Always write read valid in same SPID clock as data.

30:29
RW • 01: Always write read valid one SPID clock before data.
• 10: Write read valid up to 2 SPID clocks before data.
• 11: Reserved
SPID Early Read Data Valid
0h (SPID_EARLY_RDDATA_VALID): Specifies the delay in SPID
28:27
RW clocks from RDDATA_VALID assertion to actual data on SPID. The
value should match what is programmed in DDRIO (PHY).
Write Pending Queue Count (WPQCOUNT): Used to limit the
1Ch number of available slots in Write Pending Queue/ Write Data
26:21
RW Buffer. WPQCOUNT will only recognize changes when PMI ISM is
not active.
Read Pending Queue Count (RPQCOUNT): Used to limit the
10h
20:16 number of entries in Read Pending Queue. RPQCOUNT will only
RW
recognize changes when PMI ISM is not active.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

Read Return Data Additional Credits

(BLKRDBF_ADD_RDDATA_CR): Number of additional full
7h cacheline (64B) read data return credits exposed to D-Unit when
13:10
RW BLKRDBF is set.
Note: The value in this field has no effect on Read return credits
when BLKRDBF is not set.
In-Order Mode (INORDERMODE):
• 0h: In order mode disabled: Commands are sent out of order.
• 1h: Partial in order mode: Read and Write CAS commands are
sent in the order they were recieved. ACT and PRE can go out
of order.
0h
9:8
RW • 2h: Full in order mode serialized test: All DRAM commands
CAS ACT PRE associated with a PMI request are issued to DDR
before any DRAM commands for a subsequent PMI request.
• 3h: Reserved.
In order modes should be enabled during init/training/CPGC testing. Should never be
changed while the D-Unit queues are nonempty.

7
0h Idle Bypass Mode Enable (BYPASSEN): Reserved.
RW

Block When RDB Full (BLKRDBF): When set D-Unit stops

0h
6 scheduling new read commands to DRAM when the read data
RW
buffer (RDB) is full.

206 334818
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Bit Default &

Field Name (ID): Description
Range Access

Stretch Mode (STRETCHMODE): When stretch mode is enabled, commands are

initiated only on Phase 0 of SPIDClk.
• 00: Stretch mode is disabled.
0h
5:4 • 01: Commands are initiated on Phase 0 of every SPID clocks.
RW
• 10: Commands are initiated on Phase 0 of even SPID clocks.
• 11: Commands are initiated on Phase 0 of odd SPID clocks.
Masked Write Turnaround Delta (TMWR_TA_DELTA): The value in this register
8h is subtracted from Masked Write to Read, Masked Write to Write and Masked Write to
3:0 Masked Write turnaround times to account for half BL MWr commands in LPDDR4.
RW
• LPDDR4: = MWr tCCD = MWr BL/2 = 8.

5.5.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1640h

Specifies parameters to control ZQ Calibration.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1057h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1
ZQCALSTRTR1
ZQCALSTRTR0

RSVD28_23

SRXZQC

RSVD20_18

RSVD15_14
ZQCALTYPE

ZQCLMODE
ZQCDIS

ZQINT

Bit Default &

Field Name (ID): Description
Range Access

ZQ Calibration Type (ZQCALTYPE): Determines whether the

ZQ Calibration is a long or short calibration command (due to
0h
31 ZQCALSTRT).
RW
0: Short calibration (ZQCS).
1: Long calibration (ZQCL).
ZQ Calibration Start Rank 1 (ZQCALSTRTR1): Set this bit to 1
to start the ZQ calibration sequence on Rank 1. This bit will remain
0h a 1 until the ZQ calibration is complete for rank 1, then it will
30
RW/V return to 0.
0: ZQ calibration is done.
1: ZQ calibration has started and is in progress.

334818 207
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

ZQ Calibration Start Rank 0 (ZQCALSTRTR0): Set this bit to 1

to start the ZQ calibration sequence on Rank 0. This bit will remain
0h a 1 until the ZQ calibration is complete for rank 0, then it will
29
RW/V return to 0.
0: ZQ calibration is done.
1: ZQ calibration has started and is in progress.

28:23
0h Reserved (RSVD28_23): Reserved.
RO

Self-Refresh Exit ZQ Calibration Control (SRXZQC):

• 00: On DynSR exit ZQ timer determines the ZQ type. When
the state is lost (i.e due to AutoPG/S0ix) ZQCL is always
performed.
0h • 01: Always perform ZQCL after self refresh exit, in LPDDR4,
22:21
RW ZQ with traffic blocked.
• 10: Always perform ZQCS on SR exit. For LPDDR4, ZQ while
traffic is allowed.
• 11: No ZQCL commands are sent (it disables ZQCAL
commands on SR exit).

20:18
0h Reserved (RSVD20_18): Reserved.
RO

ZQ Calibration Mode (ZQCLMODE): Specifies how ZQCal commands are sent to

different ranks.
0h
17 • 0: ZQCal commands are sent in parallel to all ranks.
RW
• 1: ZQCal commands are sent serially to each rank.
Periodic ZQ Calibration Disable (ZQCDIS):
0h
16 • 0: Periodic ZQ Calibration is Enabled.
RW
• 1: Disable periodic ZQ Calibration.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

ZQ Calibration Interval (ZQINT): Specifies the time interval

1057h
13:0 between two ZQCS (LPDDR3) or ZQ Start (LPDDR4) commands to
RW
a DRAM device. (in RTC 32.8KHz clocks)

5.5.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset

164Ch
Specifies parameters for VNN Scaling Timer in D-Unit. The values in this register will be
set by P-code during VNN scaling period.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

208 334818
MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD30_12
VNN_TIMER_EN

VNN_TIMER_TIME
Bit Default &
Field Name (ID): Description
Range Access

VNN Scaling Timer Enable (VNN_TIMER_EN):

0h
31 • 0: The D-Unit VNN Scaling Timer is disabled.
RW
• 1: The D-Unit VNN Scaling Timer is enabled.

30:12
0h Reserved (RSVD30_12): Reserved.
RO

0h VNN Timer Time (VNN_TIMER_TIME): The final timer value

11:0
RW (in 16 x DRAM clocks).

5.5.18 Periodic DRAM Temperature Polling Control (TQ)

(D_CR_TQCTL)—Offset 1650h
Specifies the control for periodic temperature monitoring and control of DRAM device.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 6C000008h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
TQDATAR1

TQDATAR0

RSVD25_22

RSVD7_5
TQPOLLPER

ENDERATE
SRTEN

TQDATAPUSHEN

TQPOLLEN
TQPOLLSREN

Bit Default &

Field Name (ID): Description
Range Access

TQ Data Rank 1 (TQDATAR1): If Rank 1 is disabled, this value

3h will remain zero.
31:29
RW/V This field contains the data of the last DRAM Mode Register Read
to MR4 MRR issued. It is overwritten with each command.

334818 209
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

TQ Data Rank 0 (TQDATAR0): This field contains the data of

3h
28:26 the last DRAM Mode Register Read to MR4 MRR issued. It is
RW/V
overwritten with each command.

25:22
0h Reserved (RSVD25_22): Reserved.
RO

TQ Poll Period (TQPOLLPER): This sets the frequency by which

0h
21:8 the D-Unit polls the DRAM mode register MR4 to determine
RW
required refresh rate (in 4x tREFI units).

7:5
0h Reserved (RSVD7_5): Reserved.
RO

Self Refresh Temperature Range Enable (DDR3 Only)

(SRTEN): When set, before every Self refresh entry, D-Unit
0h writes a 1 to bit 7 of TQOFFSET.MR_VALUE when TQDATA for that
4
RW rank indicates a value higher then 0x3, and writes a 0 to that bit
otherwise. The new MR_VALUE is then written into MR2 of DDR3
for each enabled rank.
Enable Dynamic Timing Derating (ENDERATE): When set to
1, the Dynamic Timing Derating is enabled. When the D-Unit
1h
3 determines (via TQ polling) that the DRAM requires timing
RW
derating in addition to refresh interval adjustment, the D-Unit will
automatically adjust the relevant timing parameters.
0h Enable TQ Data Push (TQDATAPUSHEN): When set to 1, D-
2
RW Unit pushes the data form the last MR4 read to a punit register.
Enable TQ Poll on Self-Refresh Exit (TQPOLLSREN): This bit
0h
1 enables MR4 read on Self Refresh Exit. If disabled, D-Unit will not
RW
read MR4 value on Self-Refresh exit.
Enable Periodic TQ Poll (TQPOLLEN): This bit enables periodic
0h
0 TQ Poll. If disabled, D-Unit will not read MR4 value periodically.
RW
Note: Will be enabled only if refreshes are enabled.

5.5.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset

1654h
Specifies temperature offset and refresh rate adjustments requested by software.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

210 334818
MCHBAR

MR_VALUE

MR3_OFFSET_UPDATE
RSVD31_26

RSVD15_11

MR4_ADDER

RSVD7_3

MR3_THERM_OFFSET
Bit Default &
Field Name (ID): Description
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

MR Value (MR_VALUE):
MR2 Shadow Register (DDR3L Only):
0h
25:16 BIOS writes the correct value of MR2 register in DDR3L into this
RW
field at boot time. D-Unit modifies one bit and rewrites the MR2
into DDR3L DRAM before SR entry.

15:11
0h Reserved (RSVD15_11): Reserved
RO

MR4 Adder (MR4_ADDER): D-Unit adds the value of this field to

0h
10:8 TQDATA read from MR4 the resulting value is used to control
RW
refresh rate and AC timing derating.

7:3
0h Reserved (RSVD7_3): Reserved.
RO

MR3 Offset Update (MR3_OFFSET_UPDATE): When set, D-

0h Unit writes the merged value of MR3_VALUE and
2
RW/V MR3_THERM_OFFSET into MR3 of DRAM. D-Unit clears this bit
once the value is written.

1:0
0h MR3 Thermal Offset (MR3_THERM_OFFSET): Reserved.
RW

5.5.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 16A4h

Specifies parameters to control data scrambling in D-Unit.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CLOCKGATE

KEY
RSVD30

RSVD27_16
SCRM_EN

334818 211
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Enable Data Scrambler (SCRM_EN): When set to 1, data

0h
31 scrambling is enabled. When set to 0, data scrambling is disabled.
RW
Should be set before D_CR_BGF_CTL_BGF_RUN is set to 1.

30
0h Reserved (RSVD30): Reserved.
RO

Scrambler Clock Gate Select (CLOCKGATE): This field controls how the scrambler
output code is clock gated to reduce power.
• 00: Clock gate disabled.
0h
29:28 • 01: Clock Gate every 2 cycle.
RW
• 10: Clock Gate every 3 cycle.
• 11: Clock Gate every 4 cycle.

27:16
0h Reserved (RSVD27_16): Reserved.
RO

0h Scrambling Key (KEY): Sets the key for the scrambler. The key
15:0
RW should be a random value that is set following each cold boot.

5.5.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset

16ACh
Contains the target address for ECC error injection.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADDRESS
RSVD31

RSVD0

Bit Default &

Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

Error Injection Target Address (ADDRESS): Specifies the PMI

0h address of the write transaction to be injected with the error. Only
30:1
RW applicable to Write transactions. Read/under-fill read of the partial
write operation is not affected.

0
0h Reserved (RSVD0): Reserved.
RO

212 334818
MCHBAR

5.5.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—

Offset 16B0h
Controls injecting correctable or uncorrectable errors into the write requests specified
by target address.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD31_4

SEL_HI
EN_HI
SEL_LO
EN_LO
Bit Default &
Field Name (ID): Description
Range Access

31:4
0h Reserved (RSVD31_4): Reserved
RO

Error Injection Type Higher 32B (SEL_HI): If enabled, the error injection is
continuously armed for ERR_INJ.ADDR 32B write address matching until it is cleared.
• 00: No error injection.
• 01: Uncorrectable Error (UE) is armed for write address
matching to inject UE by using the same poisoning scheme,
0h i.e. inverting corresponding write ECC[6:0] on QW0 of the 32B
3
RW data.
• 10: Correctable Error (CE) is armed for write address
matching to inject CE by inverting corresponding write ECC[0]
on QW0 of the 32B data.
• 11: Reserved.
Error Injection Enable Higher 32B (EN_HI): When set the
0h
2 error injection is continuously armed for higher 32B of
RW
D_CR_ERR_INJ_ADDR write address matching until it is cleared.
Error Injection Type Lower 32B (SEL_LO): 0 - Uncorrectable
Error (UE) is armed for write address matching to inject UE by
using the same poisoning scheme, i.e. inverting corresponding
0h
1 write ECC[6:0] on every QW of the 32B data.
RW
1 - Correctable Error (CE) is armed for write address matching to
inject CE by inverting corresponding write ECC[0] on every QW of
the 32B data.
Error Injection Enable Lower 32B (EN_LO): When set, the
0h
0 error injection is continuously armed for lower 32B of
RW
D_CR_ERR_INJ_ADDR write address matching until it is cleared.

334818 213
 MCHBAR

5.5.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 16B4h

Detected ECC errors are captured in this register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYNDROME_QW

TAG
CLEAR

CERR
MERR
ECC_VISA

ERR_BURST

ERR_CHUNK

Bit Default &

Field Name (ID): Description
Range Access

0h Clear (CLEAR): Setting this bit to one clears all fields in this
31
RW/V register, including itself.
PMI VISA Byte Select (ECC_VISA): Select ECC or PMI byte on VISA :
• 00: ECC byte,
0h
30:29 • 01: PMI Data Byte [7:0],
RW
• 10: PMI Data Byte [63:56],
• 11: PMI Data Byte [255:248]
Correctable Single-bit Error (CERR): This bit is set when a
correctable single-bit error occurs on a memory read data
transfer. When this bit is set, the address that caused the error
0h
28 and the error syndrome are also logged and they are locked to
RW/V
further single bit errors, until this bit is cleared. A multiple bit
error that occurs after this bit is set will override the address/error
syndrome information.
Uncorrectable Multiple-bit Error (MERR): This bit is set when
an uncorrectable multiple-bit error occurs on a memory read data
0h
27 transfer. When this bit is set, the address that caused the error
RW/V
and the error syndrome are also logged and they are locked until
this bit is cleared.
0h Error Burst Number (ERR_BURST): Burst number (in BL8) of
26:25
RW/V the error within a chunk.
Error Chunk Number (ERR_CHUNK): Chunk number of the
0h error.
24
RW/V 0 - lower 32B chunk has error if MERR/CERR is set
1 - higher 32B chunk has the error if MERR/CERR is set

214 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h Quad Word ECC Syndrome (SYNDROME_QW): ECC Syndrome

23:16
RW/V for a QW (64 bit) within 32B Address
0h Request Tag (TAG): Read Return Tag matches with the PMI
15:0
RW/V Request Tag which triggered the error log.

5.5.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 16BCh

Contains the values read from D-Unit fuses.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FUSESTAT
RSVD31_16

Bit Default &

Field Name (ID): Description
Range Access

31:16
0h Reserved (RSVD31_16): Reserved.
RO

D-Unit Status (FUSESTAT): D-Unit bits are captured into this register and are
available to be read.
• [0]: fus_dun_ecc_dis.
• [3:1]: fus_dun_max_supported_device_size[2:0].
0h • [4:4]: fus_dun_lpddr3_dis.
15:0
RO/V
• [5:5]: fus_dun_lpddr4_dis.
• [6:6]: reserved.
• [7:7]: fus_dun_ddr3l_dis.
• [15:8]: reserved.

5.5.25 Major Mode Control (D_CR_MMC)—Offset 1724h

Specifies parameters to control read/write major mode operation and transitions.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

334818 215
 MCHBAR

Default: 2B01E518h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0RSVD31_30 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0

RSVD22_18
RAW_WMM

RSVD26

WMMEXIT
RIMPRIO

WIMTHRS

WMMENTRY
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

RAW Conflict Read Priority for WMM Transition

(RAW_WMM): If a conflict read reaches this priority (or greater
depending on access class occupancy), WMM will be triggered to
5h
29:27 unblock the corresponding write. D-Unit will stay in WMM until
RW
corresponding write is issued.
Note: The value in this bit must not be higher than lowest terminal
priority level of each access class.

26
0h Reserved (RSVD26): Reserved.
RO

6h Read Isoch Trigger Priority (RIMPRIO): If any read in the

25:23
RW RPQ is at this programmable priority, RIM is triggered.

22:18
0h Reserved (RSVD22_18): Reserved.
RO

Write Isoch Threshold (WIMTHRS): When the number of

1Eh entries in WPQ is greater than or equal to this value (higher than
17:12
RW WMM entry watermark, less than WPQ size), it triggers write isoch
mode (WIM).
Write Major Mode Exit Watermark (WMMEXIT): When the
14h
11:6 number of entries in WPQ is less than this value, the D-Unit will
RW
switch back to read major mode.
Write Major Mode Entry Watermark (WMMENTRY): When
18h the number of entries in WPQ is greater than or equal to this
5:0
RW value, the D-Unit will switch to write major mode (WMM).
Note: the value must not be set to 0.

5.5.26 Major Mode RD/WR Counter (Set A and B)

(D_CR_MMRDWR_AB)—Offset 1728h
Minimum read and maximum write counter control. This register defines the minimum
number of reads in RMM and maximum number of writes in WMM before a mode
transition happens.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

216 334818
MCHBAR

Default: 1F207C8h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0

RSVD31_26

RSVD13_12
MINRDB
MAXWRB

MINRDA
MAXWRA
Bit Default &
Field Name (ID): Description
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

1Fh Max Writes B (MAXWRB): Maximum number of writes D-Unit

25:20
RW can send in WMM mode before returning to RMM (set B).
8h Min Reads B (MINRDB): Minimum number of reads that has to
19:14
RW be serviced before a switch to WMM is allowed (set B).

13:12
0h Reserved (RSVD13_12): Reserved.
RO

1Fh Max Writes A (MAXWRA): Maximum number of writes D-Unit

11:6
RW can send in WMM mode before returning to RMM (set A).
8h Min Reads A (MINRDA): Minimum number of reads that has to
5:0
RW be serviced before a switch to WMM is allowed (set A).

5.5.27 Major Mode RD/WR Counter (Set C and D)

(D_CR_MMRDWR_CD)—Offset 172Ch
Minimum read and maximum write counter control. This register defines the minumum
number of reads in RMM and maximum number of writes in WMM before a mode
transition happens (sets C and D).

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F207C8h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0
MINRDC
RSVD31_26

RSVD13_12

MAXWRC
MAXWRD

MINRDD

334818 217
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

1Fh Max Writes D (MAXWRD): Maximum number of writes D-Unit

25:20
RW can send in WMM mode before returning to RMM (set D).
8h Min Reads D (MINRDD): Minimum number of reads that has to
19:14
RW be serviced before a switch to WMM is allowed (set D).

13:12
0h Reserved (RSVD13_12): Reserved.
RO

1Fh Max Writes C (MAXWRC): Maximum number of writes D-Unit

11:6
RW can send in WMM mode before returning to RMM (set C).
8h Min Reads C (MINRDC): Minimum number of reads that has to
5:0
RW be serviced before a switch to WMM is allowed (set C).

5.5.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1730h

Each field of this register defines the initial priority of one access class.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 17C2h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 1 0
AC4IP

AC3IP

AC2IP

AC1IP

AC0IP
RSVD31_15

Bit Default &

Field Name (ID): Description
Range Access

31:15
0h Reserved (RSVD31_15): Reserved.
RO

1h Access Class 4 Initial Priority (AC4IP): Initial priority level of

14:12
RW read requests coming with access class 4.
3h Access Class 3 Initial Priority (AC3IP): Initial priority level of
11:9
RW read requests coming with access class 3.
7h Access Class 2 Initial Priority (AC2IP): Initial priority level of
8:6
RW read requests coming with access class 2.
0h Access Class 1 Initial Priority (AC1IP): Initial priority level of
5:3
RW read requests coming with access class 1.
2h Access Class 0 Initial Priority (AC0IP): Initial priority level of
2:0
RW read requests coming with access class 0.

218 334818
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5.5.29 Access Class 0 Priority Promotion Control

(D_CR_RD_PROM0)—Offset 1734h
This register defines the priority promotion policy for access class 0. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
next level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F52940h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0
P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
RSVD31_30

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.5.30 Access Class 1 Priority Promotion Control

(D_CR_RD_PROM1)—Offset 1738h
This register defines the priority promotion policy for access class 1. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
associated level and the request has reached its maximum priority.

Access Method

334818 219
 MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 14000000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

Ah Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.5.31 Access Class 2 Priority Promotion Control

(D_CR_RD_PROM2)—Offset 173Ch
This register defines the priority promotion policy for access class 2. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
next level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

220 334818
MCHBAR

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
RSVD31_30
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.5.32 Access Class 3 Priority Promotion Control

(D_CR_RD_PROM3)—Offset 1740h
This register defines the aging policy for access class 3. Each field of this register
defines the number of CASes that pass before the request is promoted to the next
priority level. A value of 31 indicates the request should never be promoted to the next
level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F29400h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

334818 221
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
5h Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
5h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.5.33 Access Class 4 Priority Promotion Control

(D_CR_RD_PROM4)—Offset 1744h
This register defines the aging policy for access class 3. Each field of this register
defines the number of CASes that pass before the request is promoted to the next
priority level. A value of 31 indicates the request should never be promoted to the next
level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F5294Ah

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.

222 334818
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Bit Default &

Field Name (ID): Description
Range Access

Ah Priority 3 Residency (P3RES): Number of CASes that pass

14:10
RW before a request in this priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
Ah Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.5.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1748h

Specifies when the request with initial priority 0 get promoted to a higher priority level.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 6h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

DEADLINE_THRS
RSVD31_11

Bit Default &

Field Name (ID): Description
Range Access

31:11
0h Reserved (RSVD31_11): Reserved.
RO

Deadline Threshold (DEADLINE_THRS): A requests with initial

priority of 0 will exit priority 0 when its deadline is equal or less
6h
10:0 than this value plus current time. This field does not affect the
RW
priority of any requests in access classes with initial priority bigger
than 0.

5.5.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—

Offset 174Ch
This register controls blocking rules enforced in RMM and WMM.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1800h

334818 223
 MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0

RSVD31_25

RSVD23_20

RSVD15_14
WMM_REG_R1

WMM_PRIO_R4
WMM_PRIO_R3
WMM_PRIO_R2
WMM_PRIO_R1

RMM_REG_R6
RMM_REG_R5
RMM_REG_R4
RMM_REG_R3
RMM_REG_R2
RMM_REG_R1

RSVD7_4

RMM_PRIO_R4
RMM_PRIO_R3
RMM_PRIO_R2
RMM_PRIO_R1
Bit Default &
Field Name (ID): Description
Range Access

31:25
0h Reserved (RSVD31_25): Reserved.
RO

0h WMM Regular Rule 1 (WMM_REG_R1): Disable WMM unsafe

24
RW write page hits block safe write page misses same bank.

23:20
0h Reserved (RSVD23_20): Reserved.
RO

WMM Priority Rule 4 (WMM_PRIO_R4): Disable WMM unsafe

priority 1 read miss block write hit to same bank.
0h
19 Note: This rule does not block the bank that is being blocked by
RW
WMM_PRIO_R3.
Priority rules 1, 3 and 4 should be enabled/disabled together.
WMM Priority Rule 3 (WMM_PRIO_R3): Disable WMM unsafe
priority 1 write hit block write miss to same bank.
0h
18 Note: This rule does not block the bank that is being blocked by
RW
WMM_PRIO_R1.
Priority rules 1,3 and 4 should be enabled/disabled together.
0h WMM Priority Rule 2 (WMM_PRIO_R2): Disable WMM CAS
17
RW block rule.
WMM Priority Rule 1 (WMM_PRIO_R1): Disable WMM unsafe
0h
16 top priority 1 write miss block write hit same bank.
RW
Priority rules 1, 3 and 4 should be enabled/disabled together.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

0h RMM Regular Rule 6 (RMM_REG_R6): Disable RMM unsafe

13
RW write page hits block safe write page misses same bank.
RMM Regular Rule 5 (RMM_REG_R5): Disable RMM unsafe
read page miss block all safe and unsafe write page hit to the
1h
12 same bank.
RW
Note: This field must not be set to 0 (enabled) if RMM_REG_R4 is
also 0.
RMM Regular Rule 4 (RMM_REG_R4): Disable RMM unsafe
1h write page hit block safe read page miss same bank.
11
RW Note: This field must not be set to 0 (enabled) if RMM_REG_R5 is
also 0.

224 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

RMM Regular Rule 3 (RMM_REG_R3): Disable RMM unsafe

0h read page hit block safe read and write page miss same bank.
10
RW Note: This rule does not block the bank that is being blocked by
RMM_PRIO_R3 and RMM_PRIO_R1.
0h RMM Regular Rule 2 (RMM_REG_R2): Disable RMM unsafe
9
RW read page empty block safe write page empty same rank.
0h RMM Regular Rule 1 (RMM_REG_R1): Disable RMM unsafe
8
RW read page hit block safe write page hit same rank.

7:4
0h Reserved (RSVD7_4): Reserved.
RO

RMM Priority Rule 4 (RMM_PRIO_R4): Disable RMM unsafe

critical read miss block read and write hit to same bank.
0h
3 Note: This rule does not block the bank that is being blocked by
RW
RMM_PRIO_R3.
Priority rules 1, 3 and 4 should be enabled/disabled together.
RMM Priority Rule 3 (RMM_PRIO_R3): Disable RMM unsafe
critical read hit block read and write miss to same bank.
0h
2 Note: This rule does not block the bank that is being blocked by
RW
RMM_PRIO_R1.
Priority rules 1, 3 and 4 should be enabled/disabled together.
0h RMM Priority Rule 2 (RMM_PRIO_R2): Disable RMM CAS block
1
RW rule.
RMM Priority Rule 1 (RMM_PRIO_R1): Disable RMM unsafe
0h top critical read miss block read and write hit same bank.
0
RW Note: Priority rules 1, 3 and 4 should be enabled/disabled
together.

5.5.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—

Offset 1754h
Self refresh command register to allow sending WAKE and SUSPEND messages to D-
Unit. (Only one bit can be set at a time). Posted writes to this register are not
completed until hardware clears the field.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SUSPEND

WAKE
RSVD31_4

SUSPENDP

RSVD1

334818 225
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

31:4
0h Reserved (RSVD31_4): Reserved.
RO

SUSPENDP (SUSPENDP): A SUSPENDP message will put the

DRAM into self-refresh mode. The D-Unit will complete servicing
outstanding memory requests and flush all queued Refresh
commands to DRAM before putting the DRAM in self refresh mode.
0h Finally, a PM message will be sent to the PHY. The bit is cleared by
3
RW/V hardware after the PHY indicates the transition requested in the
PM message has been completed. D-Unit will perform an MRW to
MR17 with an opcode as defined by DPMC0.PASR before it places
the DRAM into Self-Refresh.

SUSPEND (SUSPEND): A SUSPEND message will put the DRAM

into self-refresh mode. The D-Unit will complete servicing
outstanding memory requests and flush all queued Refresh
commands to DRAM before putting the DRAM in Self Refresh
0h
2 mode. Finally, a PM message will be sent to the PHY. The bit is
RW/V
cleared by hardware only after the PHY indicates the transition
requested in the PM message has been completed.
Note: When COLDWAKE is set prior of setting this bit the DRAM
will not be placed in SR.

1
0h Reserved (RSVD1): Reserved.
RO

WAKE (WAKE): Take PHY out of PM states and wakes the DRAM
out of self refresh mode. The bit is cleared by hardware only when
0h
0 the DRAM has exited out of self refresh mode and is accessible.
RW/V
Note: When COLDWAKE is set prior of setting this bit the D-Unit
will not send SR exit command and will not set the DCO.IC bit.

5.5.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—

Offset 1780h
LPDDR4 DQS Retraining control register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

226 334818
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DQS_RETRAIN_INT

RSVD15_14

RSVD3_2
DQS_OSC_RT

DQS_RETRAIN_SRX_EN
DQS_RETRAIN_EN
Bit Default &
Field Name (ID): Description
Range Access

DQS Periodic Retraining Interval (DQS_RETRAIN_INT):

0h
31:16 This sets the frequency by which the D-Unit initiates periodic
RW
retraining (in 1x NREFI).

15:14
0h Reserved (RSVD15_14): Reserved.
RO

DQS Oscillator Runtime (DQS_OSC_RT): After D-Unit starts

DQS oscillator, it must wait this amount of time before being able
0h
13:4 to read the value in MR18 and MR19 (in 16x DRAM clocks).
RW
Value in this register must be at least equal to DRAM's MR23
value. + tOSCO.

3:2
0h Reserved (RSVD3_2): Reserved.
RO

DQS Retrain SRX Exit (DQS_RETRAIN_SRX_EN): Enable

0h retraining on SR exit.
1
RW This bit enables LPDDR4 DQS retraining on Self Refresh Exit. If
disabled, D-Unit will not perform retraining on SR exit.
DQS Retrain Enable (DQS_RETRAIN_EN): Periodic retraining
enable:
0h This bit enables periodic DQS retraining. If disabled, D-Unit will
0
RW not perform retraining periodically.
Note: Will be enabled only if DCO.IC is set and refreshes are
enabled in DRF.MINREFRATE.

5.5.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset

1784h
Controls the data bits swizzling crossbar for MR4.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

334818 227
 MCHBAR

MR4_BYTE_SEL2
MR4_BIT2_SEL2

MR4_BIT1_SEL2

MR4_BIT0_SEL2

MR4_BYTE_SEL
RSVD31

RSVD27

RSVD23

RSVD19_18

RSVD15

MR4_BIT2_SEL

RSVD11

MR4_BIT1_SEL

RSVD7

MR4_BIT0_SEL

RSVD3_2
Bit Default &
Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

0h MR4 Bit 2 Select 2nd Byte (MR4_BIT2_SEL2): Selects bit 2 of

30:28
RW MR4 data.

27
0h Reserved (RSVD27): Reserved
RO

0h MR4 Bit 1 Select 2nd Byte (MR4_BIT1_SEL2): Selects bit 1 of

26:24
RW MR4 data

23
0h Reserved (RSVD23): Reserved
RO

0h MR4 Bit 0 Select 2nd Byte (MR4_BIT0_SEL2): Selects bit 0 of

22:20
RW MR4 data.

19:18
0h Reserved (RSVD19_18): Reserved
RO

0h MR4 Byte 2 Select (MR4_BYTE_SEL2): Selects byte position of

17:16
RW the MR4 data for second device.

15
0h Reserved (RSVD15): Reserved
RO

14:12
0h MR4 Bit 2 Select (MR4_BIT2_SEL): Selects bit 2 of MR4 data.
RW

11
0h Reserved (RSVD11): Reserved.
RO

10:8
0h MR4 Bit 1 Select (MR4_BIT1_SEL): Selects bit 1 of MR4 data.
RW

7
0h Reserved (RSVD7): Reserved.
RO

6:4
0h MR4 Bit 0 Select (MR4_BIT0_SEL): Selects bit 0 of MR4 data.
RW

3:2
0h Reserved (RSVD3_2): Reserved.
RO

0h MR4 Byte Select (MR4_BYTE_SEL): Selects byte position of

1:0
RW the MR4 data first device.

5.6 Registers Summary

Table 5-6. Summary of memss_regs Registers
Offset Offset Default
Register Name (ID)—Offset
Start End Value

1A00h 1A03h DRAM Rank Population 0 (D_CR_DRP0)—Offset 1A00h 10000000h

228 334818
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Table 5-6. Summary of memss_regs Registers (Continued)

Offset Offset Default
Register Name (ID)—Offset
Start End Value

1A08h 1A0Bh DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1A08h 210702CBh

1A0Ch 1A0Fh DRAM Timing Register 1A (D_CR_DTR1A)—Offset 1A0Ch 30481218h

1A10h 1A13h DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1A10h 8C080C30h

1A14h 1A17h DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1A14h 3002EA28h

1A18h 1A1Bh DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1A18h 30209149h

1A1Ch 1A1Fh DRAM Timing Register 5A (D_CR_DTR5A)—Offset 1A1Ch 304200C2h

1A20h 1A23h DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1A20h 20100000h

1A24h 1A27h DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1A24h D060C06h

1A28h 1A2Bh DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1A28h CC50A18h

1A2Ch 1A2Fh D-Unit ODT Control Register A (D_CR_DOCRA)—Offset 1A2Ch 0h

1A30h 1A33h D-Unit Power Management Control 0 (D_CR_DPMC0)—Offset 1A30h 0h

1A34h 1A37h D-Unit Power Management Control 1 (D_CR_DPMC1)—Offset 1A34h 10000028h

1A38h 1A3Bh DRAM Refresh Control (D_CR_DRFC)—Offset 1A38h 1750h

1A3Ch 1A3Fh D-Unit Scheduler (D_CR_DSCH)—Offset 1A3Ch 3901C08h

1A40h 1A43h DRAM Calibration Control (D_CR_DCAL)—Offset 1A40h 1057h

1A44h 1A47h VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 1A4Ch 20000h

1A4Ch 1A4Fh VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset 1A4Ch 0h

Periodic DRAM Temperature Polling Control (TQ) (D_CR_TQCTL)—Offset

1A50h 1A53h 6C000008h
1A50h

1A54h 1A57h TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset 1A54h 0h

1A58h 1A5Bh Data Scrambler (D_CR_SCRAMCTRL)—Offset 1AA4h 0h

1AA4h 1AA7h Data Scrambler (D_CR_SCRAMCTRL)—Offset 1AA4h 0h

1AACh 1AAFh Error Injection Address Register (D_CR_ERR_INJ)—Offset 1AACh 0h

1AB0h 1AB3h Error Injection Control Register (D_CR_ERR_INJ_CTL)—Offset 1AB0h 0h

1AB4h 1AB7h Error Log Register (D_CR_ERR_ECC_LOG)—Offset 1AB4h 0h

1ABCh 1ABFh D-Unit Status (D_CR_DFUSESTAT)—Offset 1ABCh 0h

1B24h 1B27h Major Mode Control (D_CR_MMC)—Offset 1B24h 2B01E518h

Major Mode RD/WR Counter (Set A and B) (D_CR_MMRDWR_AB)—Offset

1B28h 1B2Bh 1F207C8h
1B28h

Major Mode RD/WR Counter (Set C and D) (D_CR_MMRDWR_CD)—

1B2Ch 1B2Fh 1F207C8h
Offset 1B2Ch

1B30h 1B33h Access Class Initial Priority (D_CR_ACCIP)—Offset 1B30h 17C2h

Access Class 0 Priority Promotion Control (D_CR_RD_PROM0)—Offset

1B34h 1B37h 1F52940h
1B34h

Access Class 1 Priority Promotion Control (D_CR_RD_PROM1)—Offset

1B38h 1B3Bh 14000000h
1B38h

Access Class 2 Priority Promotion Control (D_CR_RD_PROM2)—Offset

1B3Ch 1B3Fh 0h
1B3Ch

Access Class 3 Priority Promotion Control (D_CR_RD_PROM3)—Offset

1B40h 1B43h 1F29400h
1B40h

Access Class 4 Priority Promotion Control (D_CR_RD_PROM4)—Offset

1B44h 1B47h 1F5294Ah
1B44h

1B48h 1B4Bh Deadline Threshold (D_CR_DL_THRS)—Offset 1B48h 6h

334818 229
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Table 5-6. Summary of memss_regs Registers (Continued)

Offset Offset Default
Register Name (ID)—Offset
Start End Value

1B4Ch 1B4Fh Major Mode Blocking Rules Control (D_CR_MM_BLK)—Offset 1B4Ch 1800h

1B54h 1B57h DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—Offset 1B54h 0h

1B80h 1B83h DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—Offset 1B80h 0h

1B84h 1B87h MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset 1B84h 0h

5.6.1 DRAM Rank Population 0 (D_CR_DRP0)—Offset 1A00h

Rank configuration register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10000000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BLMODE

DWID
ADDRDEC

CASWIZZLE
DRAMDEVICE_PR

DRAMTYPE

RSVD18_16

RSVD3
DDMEN
RKEN1
RKEN0
ECCEN

BAHEN

RSVD13_9

DDEN
RSIEN

Bit Default &

Field Name (ID): Description
Range Access

DRAM Device Per Rank (DRAMDEVICE_PR): Specifies the number of DRAM

devices that are ganged together to form a single rank.
• 00: 1 DRAM device in each rank.
0h • 01: 2 DRAM devices in each rank.
31:30
RW
• 10: 4 DRAM devices in each rank.
• 11: 8 DRAM devices in each rank.
Note: The actual number of devices is one more than the value programmed when
ECC is enabled.

Address Decode (ADDRDEC): Specifies the address mapping to be used:

• 00: 1KB (A).
1h
29:28 • 01: 2KB (B).
RW
• 10: 4KB (C).
• 11: Reserved.

230 334818
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Bit Default &

Field Name (ID): Description
Range Access

Burst Length Mode (BLMODE):

• 000: Fixed BL8.
• 001: Onthefly BL8.

0h
• 010: Fixed BL16.
27:25
RW • 011: Onthefly BL16.
• 100: Fixed BL32.
• 101: Onthefly BL32.
• 110-111: Reserved.
DRAM Type (DRAMTYPE):
• 000: DDR3L.
• 001: LPDDR3.
0h • 010: LPDDR4.
24:22
RW
• 011: Reserved.
• 100: Reserved.
• 101-111: Reserved.

ECC Enable (ECCEN):

• 0: ECC is disabled.
0h
21
RW • 1: ECC is enabled.
This bit determines if the D-Unit treats the PMI BE_ECC bits as ECC bits or Byte
Enables. This should only be used in configurations that support ECC (DDR3L).

CA Swizzle Type (CASWIZZLE):

• 00: uniDIMM/SODIMM.
0h
20:19 • 01: BGA.
RW
• 10: BGA mirrored (LPDDR3 Only).
• 11: UDIMM (DDR3L Only).

18:16
0h Reserved (RSVD18_16): Reserved.
RO

Bank Address Hashing Enable (BAHEN): See Address Mapping section for full
description.
0h
15 • 0: Bank Address Hashing disabled.
RW
• 1: Bank Address Hashing enabled.
Rank Select Interleave Enable (RSIEN): See Address Mapping section for full
description.
0h
14 • 0: Rank Select Interleaving disabled.
RW
• 1: Rank Select Interleaving enabled.

13:9
0h Reserved (RSVD13_9): Reserved.
RO

334818 231
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Bit Default &

Field Name (ID): Description
Range Access

DRAM Device Density (DDEN): Density of the DRAM devices populated on Ranks 0
and 1.
• 000: 4 Gb.
• 001: 6 Gb.
0h • 010: 8 Gb.
8:6
RW
• 011: 12 Gb.
• 100: 16 Gb.
• 101-111: Reserved.
Note: For LPDDR4 this value is the die density.

DRAM Device Data Width (DWID): Data width of the DRAM device populated on
Ranks 0 and 1.
• 00: x8.
0h
5:4 • 01: x16.
RW
• 10: x32.
• 11: x64.

3
0h Reserved (RSVD3): Reserved.
RO

Dual Data Mode Enable (DDMEN):

• 0: PMI Dual Data Mode is disabled in D-Unit, full cacheline
0h
2 read and writes go through a single D-Unit.
RW
• 1: PMI Dual Data Mode is enabled, only half cacheline read/
writes go through a single D-Unit.
0h Rank Enable 1 (RKEN1): Enable Rank 1: Must be set to 1 to
1
RW enable use of this rank.
Rank Enable 0 (RKEN0): Enable Rank 0: Must be set to 1 to
0h
0 enable use of this rank.
RW
Note: Setting this bit to 0 is not a functional mode.

5.6.2 DRAM Timing Register 0A (D_CR_DTR0A)—Offset 1A08h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 210702CBh

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 1
TCKCKEH

TXSDLL

TXSR

TRPPB
TRCD

232 334818
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Bit Default &

Field Name (ID): Description
Range Access

Valid Clocks Before CKE High [tCKCKEH/tCSCKEH/tCKSRX] (TCKCKEH):

Number of valid clocks before CKE high (in DRAM clocks).
• LPDDR4: The value in this register covers both tCKCKEH and
tCSCKEH.
• DDR3L/LPDDR3: The value covers tCKSRX which is defined as
the number of valid DRAM clocks that have to toggle before
10h
31:25 the issuing of the Self Refresh Exit SRX. This value is also used
RW
if the clock frequency is changed or the clock is stopped or
tristated during Power Down i.e. the number valid DRAM
clocks that have to toggle before the issuing of the Power
Down Exit PDX command.
tCKCKEH can be used to compensate for clock stabilization delays in the
motherboard. Note: D-unit hardware enforces minimum of two SPID clock before
CKEH, any value in this register is the additional time.

Exit Self-Refresh to Valid Commands Requiring a Locked

DLL Delay [tXSDLL] (TXSDLL): D-Unit waits max(tXSR+tZQCL/
tZQCS, tXSDLL) before allowing traffic to DRAM (in 64 x DRAM
8h Clocks).
24:21
RW LPDDR3/LPDDR4: tXSDLL = 0.
DDR3L: tXSDLL = tDLLK = 512 Clocks = 8 x 64 DRAM Clocks.
Note: In the equation above, tZQCL/tZQCS = 0 if no ZQ is
performed on SR exit.
Exit Self-Refresh to Valid Command Delay [tXS/tXSR]
(TXSR): DDR3L: tXS - Delay between Self Refresh Exit SRX to
70h
20:12 any DRAM Command not requiring DLL Lock.
RW
LPDDR: tXSR - Delay between Self Refresh Exit SRX to any DRAM
Command. (in DRAM clocks).
Activate RAS to CAS Command Delay [tRCD] (TRCD):
Specifies the delay between a DRAM Activate command and a
Bh
11:6 DRAM Read or Write command to the same bank (in DRAM
RW
clocks).
Note: Derating adds 1.875ns to this timing.
Precharge to Activate Command Delay of a Single Bank
[tRPpb] (TRPPB): Specifies the delay between a DRAM
Precharge command and a DRAM Activate command to the same
Bh
5:0 bank (in DRAM Clocks).
RW
Note : this CR should be constrained to a minimum of 4 in LPDDR3
and minimum of 8 in LPDDR4.
Note: Derating adds 1.875ns to this timing.

5.6.3 DRAM Timing Register 1A (D_CR_DTR1A)—Offset 1A0Ch

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 30481218h

334818 233
 MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0

TXP

RSVD26

TZQCL

TZQLAT
TZQCS
Bit Default &
Field Name (ID): Description
Range Access

Exit Power Down to Next Command Delay [tXP] (TXP):

Specifies the delay from the DRAM Power Down Exit (PDX)
6h
31:27 command to any valid command (in DRAM clocks).
RW
Note: The value in this field must be programmed to tXPDLL when
Slow Exit Mode Power-down is enabled for DDR3L.

26
0h Reserved (RSVD26): Reserved.
RO

ZQ (long) Calibration Time [tZQCL/tZQCAL] (TZQCL):

• LPDDR3/DDR3L: tZQCL/tZQoper: Specifies the delay between
the DRAM ZQ Calibration Long (ZQCL) command and any
DRAM command during normal operation.
120h
25:14 • LPDDR4: tZQCAL: ZQ Calibration time (in DRAM clocks).
RW
Note: This field defines the ZQ Calibration Long delay during normal operation. It is
not the same as tZQinit which uses the same ZQCL command but the delay is longer.
tZQinit applies only during poweron initialization of the DRAM devices and tZQoper
applies during normal operation. BIOS executes the DRAM initialization sequence so
it has to ensure tZQinit is met and not the D-Unit.

ZQ Short Calibration Time [tZQCS] (TZQCS): ZQCS to any

DRAM Command Delay: Specifies the delay between the DRAM ZQ
48h Calibration Short (ZQCS) command and any DRAM command (in
13:6
RW DRAM clocks).
DDR3L and LPDDR3 only. LPDDR4 does not support ZQCS
command
ZQ Latch Time [tZQLAT] (TZQLAT): Specifies the delay
18h between the DRAM ZQ Calibration Latch command and any DRAM
5:0
RW command (in DRAM clocks).
LPDDR4 only.Not used in DDR3L/LPDDR3.

5.6.4 DRAM Timing Register 2A (D_CR_DTR2A)—Offset 1A10h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 8C080C30h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0

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TCKE
RSVD22_21

RSVD16

NREFI
NRFCAB
Bit Default &
Field Name (ID): Description
Range Access

All Bank Refresh Cycle Time [tRFCab] (NRFCAB): Specifies

118h
31:23 the delay between the REFab command to the next valid
RW
command. (in DRAM clocks)

22:21
0h Reserved (RSVD22_21): Reserved.
RO

4h CKE Minimum Pulse Width [tCKE] (TCKE): Specifies the

20:17
RW minimum time from CKEL to CKEH (in DRAM clocks).

16
0h Reserved (RSVD16): Reserved.
RO

Refresh Interval Time [tREFI] (NREFI): Specifies the average

C30h time between refresh commands. JEDEC Base Refresh Interval
15:0
RW time (in DRAM clocks).
Note: D-Unit will ignore the 2 LSBs of this field.

5.6.5 DRAM Timing Register 3A (D_CR_DTR3A)—Offset 1A14h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 3002EA28h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 1 0 1 0 0 0
TCWL

TWMWSB
TCMD
TRTP

TCCD_INC

TWTP

Bit Default &

Field Name (ID): Description
Range Access

Read to Precharge Delay [tRDPRE] (TRTP): Specifies the minimum delay

between the DRAM Read and Precharge commands to the same bank (in DRAM
clocks).
6h
31:27 • LPDDR3 Equation: = BL/2 + tRTP - 4.
RW
• LPDDR4 Equation: = BL/2 + Max (8, tRTP) - 8.
• DDR3L Equation: = tRTP.

334818 235
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Bit Default &

Field Name (ID): Description
Range Access

CAS to CAS Command Delay Adder (TCCD_INC): Specifies

0h the number of clocks to be added to turnaround times (for Stretch
26:20
RW Mode). It increases delay between Read to Read or Read to Write
commands (in 4 x DRAM clocks).
Write to Precharge Command Delay [tWRPRE] (TWTP): Specifies the minimum
delay between the DRAM Write command and the Precharge command to the same
17h bank (in DRAM clocks).
19:13
RW • LPDDR3/LPDDR4 Equation: tWTP = BL/2 + WL + tWR + 1.
• DDR3L Equation: tWTP = BL/2 + CWL + tWR.
DRAM Command Valid Duration (TCMD): Specifies the number of DRAM clocks a
command is held valid on the DRAM Address and Control buses. 1N is the DDR3 basic
requirement. 2N is the extended mode for board signal integrity.
• 0h: Reserved.
1h
12:11
RW • 1h: 1 DRAM Clock (1N).
• 2h: 2 DRAM Clocks (2N).
• 3h: Reserved.
Note: DDR3L only. tCMD must be set to 1N for LPDDR3/LPDDR4.

Write Latency [WL/CWL] (TCWL): The delay between the

8h
10:6 internal write command and the availability of the first word of
RW
DRAM input data (in DRAM clocks).
Write CAS to Masked Write CAS Delay Same Bank (TWMWSB): Specifies the
minimum delay between DRAM Write command to Masked Write command to same
bank (in DRAM clocks).
28h
5:0 • LPDDR4 Equation: tWMWSB = tCCDMW (BL16) or tCCDMW +
RW
8 (BL32).
Note: Masked Write operation in LPDDR4 is always BL16. D-Unit applies this timing
for same rank as well as same bank.

5.6.6 DRAM Timing Register 4A (D_CR_DTR4A)—Offset 1A18h

Specifies DRAM timings parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 30209149h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1
TFAW

TWRDR

TRWDR

TWWDR

TRRDR

236 334818
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Bit Default &

Field Name (ID): Description
Range Access

Four Bank Activate Window [tFAW] (TFAW): A rolling

30h timeframe in which a maximum of four Activate commands can be
31:24
RW issued to the same rank. This is to limit the peak current draw
from the DRAM devices (in DRAM clocks).
Write to Read DQ Delay Different Ranks (TWRDR): Specifies the delay from the
start of a Write data burst of one rank to the start of a Read data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tWRDR = WL + tDQSSmax + BL/2 +
tWPST - (RL + tDQSCKmin - tRPRE).
8h
23:18
RW • LPDDR4 Equation: tWRDR = WL - RL + BL/2 + 4 -
tDQSCKmin.
• DDR3L Equation: tWRDR = CWL + tDQSSmax + BL/2 +
tWPST - (CL + tDQSCKmin - tRPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.

Read to Write DQ Delay Different Ranks (TRWDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Write data burst of a different
rank (in DRAM clocks).
• LPDDR3 Equation: tRWDR = RL + tDQSCKmax + BL/2 +
tRPST - (WL + tDQSSmin - tWPRE).
9h
17:12 • LPDDR4 Equation: tRWDR = RL + tDQSCKmax + BL/2 - (WL -
RW
2).
• DDR3L Equation: tRWDR = CL + tDQSCKmax + BL/2 + tRPST
- (CWL + tDQSSmin - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be adjusted by tODTon.
Note: For DDR3L using ODT, this latency may need to be increased by one clock.

Write to Write DQ Delay Different Ranks (TWWDR): Specifies the delay from
the start of a Write data burst of one rank to the start of a Write data burst of a
different rank (in DRAM clocks).
• LPDDR3 Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin
5h + tWPRE.
11:6
RW
• LPDDR4 Equation: tWWDR = BL/2 + 4 - tDQSSmin.
• DDR3L Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin +
tWPRE.
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.

Read to Read DQ Delay Different Ranks (TRRDR): Specifies the delay from the
start of a Read data burst of one rank to the Start of a Read data burst of a different
rank (in DRAM clocks).

5:0
9h • LPDDR3/4 Equation: tRRDR = BL/2 + tDQSCKmax -
RW tDQSCKmin + tRPRE.
• DDR3L Equation: tRRDR = BL/2 + tRPST + tDQSCKmax -
tDQSCKmin + tRPRE + 1.

5.6.7 DRAM Timing Register 5A (D_CR_DTR5A)—Offset 1A1Ch

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

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 MCHBAR

Default: 304200C2h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0

TDERATE_INC
RSVD26

TWWSR

TRRSR

TWRSR

TRWSR
TRRD

Bit Default &

Field Name (ID): Description
Range Access

Row Activation to Row Activation Delay [tRRD] (TRRD):

Specifies the minimum delay in DRAM clocks between two DRAM
6h
31:27 Activate commands to the same rank but different banks (tRC is
RW
the minimum delay between activations of the same bank).
Note: Derating adds 1.875ns to this timing.

26
0h Reserved (RSVD26): Reserved.
RO

Derate Increment (TDERATE_INC): Specifies the additional

delay that is added to DRAM timing when indicated by MR4 status.
0h (in DRAM clocks)
25:23
RW LPDDR3/LPDDR4: Value is 1.875ns.
Note: The value in this register is only added to these timing
parameters: tRCD, tRAS, tRP and tRRD.
Write to Write DQ Delay Same Rank (TWWSR): Specifies the
10h delay from a DRAM Write to another Write command of the same
22:18
RW rank (in DRAM clocks).
LPDDR3/LPDDR4/DDR3L Equation: tRRSR = tCCD.
Read to Read DQ Delay Same Rank (TRRSR): Specifies the
10h delay from a DRAM Read to another Read command of the same
17:13
RW rank (in DRAM clocks).
LPDDR3/LPDDR4/DDR3L Equation: tRRSR = tCCD.
Write to Read DQ Delay Same Rank (TWRSR): Specifies the delay from a DRAM
Read to Write command of the same rank (in DRAM clocks).

3h • LPDDR3/LPDDR4 Equation: tWRSR = WL + tDQSSmax + BL/2

12:6 + tWTR.
RW
• DDR3L Equation: tWRSR = CWL + tDQSSmax + BL/2 +
tWPST + tWTR.
Read to Write DQ Delay Same Rank (TRWSR): Specifies the delay from a DRAM
Read to a Write command of the same rank (in DRAM clocks).
• LPDDR3/LPDDR4 Equation: tRWSR = RL + tDQSCKmax + BL/
2h 2 - WL + tWPRE.
5:0
RW
• DDR3L Equation: tRWSR = CL + tDQSCKmax + BL/2 + tRPST
- (CWL +tDQSSmin - tWPRE).
Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.
Note: For DDR3L using ODT, this latency may need to be increased by one clock.

238 334818
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5.6.8 DRAM Timing Register 6A (D_CR_DTR6A)—Offset 1A20h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 20100000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD7
TPSTMRRBLK
OREFDLY

TCKCKEL

MNTDLY

TPREMRBLK
Bit Default &
Field Name (ID): Description
Range Access

20h Opportunistic Refresh Idle Timer (OREFDLY): Rank idle

31:24
RW period that defines an opportunity for refresh (in DRAM clocks).
Valid Clocks After CKE Low [tCKELCK/tCKELCS/tCPDED/tCKSRE]
(TCKCKEL): Specifies the amount of time that DRAM clocks need to toggle after CKE
goes low (in DRAM Clocks).
• For LPDDR3, this covers tCPDED.
2h
23:19
RW • For LPDDR4, this covers both tCKELCK and tCKELCS.
• For DDR3L, this is tCKSRE.
Note: D-Unit hardware enforces minimum of one SPID clocks after CKEL, any value in
this register is the additional time.

Maintenance Operation Delay (MNTDLY): When a critical read

request is pending in RPQ and a maintenance operation (MRR,
0h ZQCal, Ref, etc, panic refresh is an exception to this delay.) needs
18:15
RW to be performed, D-Unit waits this amount of time before
performing the maintenance operation to allow for some high
priority requests to be issued (in 4x SPID clocks).
Mode Register Read to Any Command Delay
(TPSTMRRBLK): Specifies the quiet time after issuing MRR
command (in DRAM Clocks).
0h
14:8 Note: D-Unit treats MRR as a read and always applies relevant
RW
turnaround times, any value programmed in this CR must be
greater than those turnaround times for D-Unit to enforce any
additional time from MRR to the next read/write.

7
0h Reserved (RSVD7): Reserved.
RO

334818 239
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Any Command to Mode Register Read/Write Delay

(TPREMRBLK): Specifies the quiet time before issuing MRR/MRW
command. (in DRAM clocks).
0h
6:0 Note: D-Unit treats MRR as a read and always applies relevant
RW
turnaround times, any value programmed in this CR must be
greater than those turnaround times for D-Unit to enforce any
additional time from previous read/writes.

5.6.9 DRAM Timing Register 7A (D_CR_DTR7A)—Offset 1A24h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: D060C06h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0

RSVD8_7
TRDPDEN
TWRPDEN
TRPAB

TPSTMRWBLK

TRAS
Bit Default &
Field Name (ID): Description
Range Access

All Bank Precharge to Activate Command Delay [tRPab] (TRPAB): Specifies

the delay between a DRAM Precharge All Bank command and a DRAM Activate
command (in DRAM Clocks). Note: This CR should be constrained to a minimum of 4
3h in LP3 and minimum of 8 in LP4. Note: Derating adds 1.875ns to this timing.
31:26
RW
• For LPDDR, tRPpb = tRP, tRPab = tRP + 3ns.
• For DDR3L 8ch tRPpb = tRPab = tRP.
Mode Register Write to any Command Delay [tMRD/tMRW]
2h (TPSTMRWBLK): Specifies the quiet time after issuing MRW
25:23
RW command (in 8 x DRAM clocks).
Note: This time covers for both tMRD and tMRW.
Write Command to Power Down Delay [tWRPDEN]
6h (TWRPDEN): Specifies the minimum time between a write
22:16
RW command to PowerDown command (in DRAM clocks).
Must be at least equal to tWR + tCCD + tWL + 2.
Read Command to Power Down Delay [tRDPDEN]
6h (TRDPDEN): Specifies the minimum time between a read
15:9
RW command to PowerDown command (in DRAM clocks).
Must be at least equal to CL/RL + tDQSCKmax + tCCD + tRPST.

240 334818
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Bit Default &

Field Name (ID): Description
Range Access

8:7
0h Reserved (RSVD8_7): Reserved.
RO

Row Activation Period [tRAS] (TRAS): Specifies the minimum

6h delay between the DRAM Activate and Precharge commands to
6:0
RW the same bank (in DRAM clocks).
Note: Derating adds 1.875ns to this timing.

5.6.10 DRAM Timing Register 8A (D_CR_DTR8A)—Offset 1A28h

Specifies DRAM timing parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: CC50A18h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0
TCKESR

LPMDRES

LPMDTOCKEDLY

PWDDLY
CKETOLPMDDLY

Bit Default &

Field Name (ID): Description
Range Access

Minimum Self-Refresh Time [tSR/tCKESR] (TCKESR):

3h
31:26 Specifies the minimum time that DRAM should remain in SR (in
RW
DRAM clocks).
Minimum Low Power Mode Residency (LPMDRES): Specifies
6h
25:21 the minimum time that PHY should remain in LPMode (in DRAM
RW
clocks).
Low Power Mode Exit to Clock Enable Delay
(LPMDTOCKEDLY): Specifies the minimum time between the LP
Ah
20:15 Mode exit to the CK stop/tristate deassertion and powerdown exit
RW
(in DRAM clocks).
Note: Must be equal to t_idle_latency and less than 0x3C.
Clock Stop to Low Power Mode Delay (CKETOLPMDDLY):
Specifies the time between CK stop/tristate to the Low Power
Ah Mode entry. This timing parameter is used to delay Low Power
14:8
RW Mode entry (in DRAM clocks).
Note: Must be at least equal to t_idle_length parameter and less
than 0x7C.

334818 241
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Power Down Idle Timer (PWDDLY): This is a non-JEDEC

18h
7:0 timing parameter used to delay powerdown entry (in DRAM
RW
clocks).

5.6.11 D-Unit ODT Control Register A (D_CR_DOCRA)—Offset

1A2Ch
Specifies the parameters to control DRAM ODT.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDODTSTART

WRODTSTART
RDODTSTOP

WRODTSTOP

RSVD4
RSVD31_30

R1WRODTCTL

R0WRODTCTL

RSVD23_18

RSVD13
R1RDODTCTL
R0RDODTCTL

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

Rank 1 Read ODT Control (R1RDODTCTL): Specifies the

behavior of ODT signals when a Read command is issued to Rank
0h 1.
29
RW 0 - Read ODT is disabled for Rank 1
1 - Assert ODT to for Rank 0 (non-targeted Rank)
Note: This register should be set to 0 for LPDDR3 devices
Rank 0 Read ODT Control (R0RDODTCTL): Specifies the
behavior of ODT signals when a Read command is issued to Rank
0h 0.
28
RW 0 - Read ODT is disabled for Rank 0
1 - Assert ODT to for Rank 1 (non-targeted Rank)
Note: This register is reserved for LPDDR3 devices
Rank 1 Write ODT Control (R1WRODTCTL): Specifies the
behavior of ODT signals when a Write command is issued to Rank
1.
0h 00 - Write ODT is disabled
27:26
RW 01 - Assert ODT to Rank 0 (non-targeted Rank)
10 - Assert ODT to Rank 1 (targeted Rank)
11 - Assert ODT to Rank 0 and Rank 1
Note: 10 and 11 are reserved values for LPDDR3

242 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Rank 0 Write ODT Control (R0WRODTCTL): Specifies the

behavior of ODT signals when a Write command is issued to Rank
0.
0h 00 - Write ODT is disabled
25:24
RW 01 - Assert ODT to Rank 0 (targeted Rank)
10 - Assert ODT to Rank 1 (non-targeted Rank)
11 - Assert ODT to Rank 0 and Rank 1
Note: 10 and 11 are reserved values for LPDDR3

23:18
0h Reserved (RSVD23_18): Reserved.
RO

Read ODT assertion to de-assertion delay (DDR3L Only)

(RDODTSTOP): Specifies Read ODT assertion to ODT de-assert
0h
17:14 delay (in DRAM clocks).
RW
DDR3L Equation: RDODTSTOP = DOCRx.WRODTSTOP (subtract 1
if DOCRx.WRODTSTART = 1 in 2N mode).

13
0h Reserved (RSVD13): Reserved.
RO

Read command to ODT assertion delay (DDR3L Only)

(RDODTSTART): Specifies Read ODT assertion delay after Read
0h Command (in DRAM clocks).
12:9
RW DDR3L Equation: RDODTSTART = CL CWL (add 1 if
DOCRx.WRODTSTART = 0 in 2N mode).
The max value for this CR is 0xE
Write ODT Assertion to De-assertion Delay (WRODTSTOP):
Specifies number of clocks after ODT assertion that D-Unit
0h deasserts ODT signal (in DRAM clocks).
8:5
RW LPDDR3 Equation: WRODTSTOP = RU(tODTon(max)/tCK) +
RU((tDQSSmax+tWPST)/tCK) + BL/2 - RD(tODToffmin/tCK)
DDR3L Equation: WRODTSTOP >= 6

4
0h Reserved (RSVD4): Reserved.
RO

Write command to ODT assertion delay (WRODTSTART):

Specifies number of clocks after Write command that D-Unit
asserts ODT signal (in DRAM clocks).
LPDDR3 Equation: WRODTSTART = WL - RU(tODTon(max)/tCK)
0h DDR3L Equation: WRODTSTART = 0 Note: DDR3 spec requires
3:0
RW ODT to be asserted high when the DRAM Write command is
issued. In DDR3L 2N mode the value can be set to 0 to assert ODT
one DRAM clock earlier than the Write Command (WR) or set to 1
to assert at the same clock as command (CS assertion).
The max value for this CR is 0xE

5.6.12 D-Unit Power Management Control 0 (D_CR_DPMC0)—

Offset 1A30h
Specifies the parameters to control D-Unit power management features.

Access Method

334818 243
 MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SREDLY
SUSPMOP
RSVD31_29

DYNPMOP
RSVD23
SRPMCLKW

DYNSREN
Bit Default &
Field Name (ID): Description
Range Access

31:29
0h Reserved (RSVD31_29): Reserved.
RO

SUSPEND/SUSPENDP Power Management Message Opcode

(SUSPMOP): DDRIO PHY Power Mode Opcode: After the D-Unit
has placed the DRAM devices in Self Refresh/PASR mode as the
result of a SUSPEND/SUSPENDP message, it sends this 5-bit value
0h
28:24 to the DDRIO PHY to tell it which power saving mode it should
RW
enter.
Changing this register value while in SUSPEND will have no effect.
Note: This opcode cannot be a PM state where it disables PHY PLLs
i.e PM7 in LPDDR PHY.

23
0h Reserved (RSVD23): Reserved.
RO

PM Message Wait for Clock Gate Enable (SRPMCLKW): Specifies when it is safe
to send PM message to the PHY. When enabled, D-Unit waits for SPID Clock to
deassert before sending a PM message on SR entry.

0h • 0: D-Unit will not wait for SPID_clk to deassert before sending

22
RW the PM message to PHY.
• 1: D-Unit will wait for SPID_clk to deassert before sending PM
message to the PHY.
Note: The value must be 1 when DYNPMOP = 7h.

Dynamic Self-Refresh Power Management Message Opcode

(DYNPMOP): DDRIO PHY Power Mode Opcode: After the D-Unit
has placed the DRAM devices in Self Refresh mode as the result of
0h
21:17 a Dynamic Self-Refresh, it sends this 5bit value to the DDRIO PHY
RW
to tell it which power saving mode it should enter.
Changing this register value while in self-refresh will only change
the PM state for the next entry in DynSR.
Dynamic Self-Refresh Enable (DYNSREN): When set to 1, the
D-Unit will automatically control DRAM Self Refresh entry and exit
based on interface state and requests in pending queues. When
0h
16 there is no pending request in the queues and PMI is idle, then the
RW
D-Unit will place the DRAM devices in Self Refresh mode. The
DRAM devices will be brought out of Self-Refresh when idle
conditions don't hold.

244 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Self-Refresh Entry Delay (SREDLY): Specifies the minimum

0h
15:0 time the D-Unit will wait before it enters Dynamic Self-Refresh
RW
mode when idle (in 16x DRAM Clocks).

5.6.13 D-Unit Power Management Control 1 (D_CR_DPMC1)—

Offset 1A34h
Specifies the parameters to control D-Unit power management features.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10000028h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
CSTRIST

CMDTRIST

PCLSTO

ODTTRIST
RPTCLKGTDIS

CLKGTDIS

PCLSTODIS
SBEPCLKGTDIS

LPMODEOP
RSVD31_30

RSVD6

ENCKSTP

DISPWRDN
PASR

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

D-Unit Repeaters Clock Gate Disable (RPTCLKGTDIS):

Setting this bit to 0 allows majority of the repeaters between D-
Unit and PHY to clock gate when there is no activity in order to
save power.
0h 0 - Enable Repeaters clock gating, 1 - Disable Repeaters clock
29
RW gating.
Note: This is a de-feature bit and should be set to 0 for normal
operation.
Note: The value should only change after DRAM Timing Registers
(DTR) are programmed.
IOSF-SB End Point Clock Gate Disable (SBEPCLKGTDIS):
Setting this bit to 0 enables the clock gating of IOSF-SB End
Points in D-Unit and CPGC when there is no IOSF-SB activity in
order to save power.
1h 0 - Enable IOSF-SB EP clock gating, 1 - Disable IOSF-SB clock
28
RW gating.
Note: This is a de-feature bit and should be set to 0 for normal
operation.
Note: The value should only change after DRAM Timing Registers
(DTR) are programmed.

334818 245
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Local Clock Gate Disable (CLKGTDIS): Setting this bit to 0 allows the majority of
the D-Unit clocks to be gated off when there is no activity in order to save power.
When set to 1, D-Unit clockgating is disabled.
0h • 0: Enable.
27
RW
• 1: Disable.
Note: This is a de-feature bit and should be set to 0 for normal operation. Note: The
value should only change after DRAM Timing Registers (DTR) are programmed.

Chip Select Tristate Enable (CSTRIST):

• 0: The DRAM CS pins associated with the enabled ranks are
0h never tristated.
26
RW
• 1: The DRAM CS pins are tristated when DRAM clock is
stopped or tristated.
Note: CS is not tristated when global tristate flow is disabled (DCBR.TRISTDIS = 1).

Command/Address Tristate (CMDTRIST):

• 00: The DRAM CA pins are never tristated.
• 01: The DRAM CA pins are only tristated when all enabled CKE
0h
25:24 pins are low.
RW
• 10: The DRAM CA pins are tristated when not driving a valid
command.
• 11: Reserved
Partial Array Self-Refresh Segment Mask (PASR): This is the
0h
23:16 Segment Mask used for the MRW to enable PASR during
RW
SUSPENDP (Partial Array Self Refresh entry).
Page Close Timeout Period (PCLSTO): Specifies the time from
0h the last access of a DRAM page until that page is scheduled to
15:8
RW close by sending a Precharge command to DRAM (in 16 x DRAM
clocks).
Page Close Timeout Disable (PCLSTODIS): When disabled, D-Unit will not close
the DRAM page when idle.
0h • 0: Enable page close timer.
7
RW
• 1: Disable page close timer (Used during DRAM init and
DDRIO training).

6
0h Reserved (RSVD6): Reserved.
RO

ODT Tristate Enable (ODTTRIST):

• 0: The DRAM ODT pins associated with the enabled ranks are
1h never tristated.
5
RW
• 1: DRAMs ODT pins are tristated when DRAM clock is stopped
or tristated.
Note: ODT is not tristated when global tristate flow is disabled (DCBR.TRISTDIS = 1)

246 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Clock Stop/Tristate Enable (ENCKSTP): Enable/Disable CK Stop/Tristate During

Power down.
• 00: Disable CK Stop/Tristate During Power down.
1h • 01: Enable CK Stop During Power down.
4:3
RW
• 10: Enable CK Tristate During Power down.
• 11: Reserved
Note: CK is not stopped or tristated when global tristate flow is disabled
(DCBR.TRISTDIS = 1).

Low Power Mode Opcode (LPMODEOP): D-Unit will send the

value in this register after it has entered Powerdown Mode and has
0h stopped/tristated the clock.
2:1
RW 00: Disable LPMode.
Note: LPMODE entry is not possible when global tristate flow is
disabled (DCBR.TRISTDIS = 1).
Disable Power Down (DISPWRDN): Setting this bit to 1 disables dynamic control
of DRAM Power-Down entry and exit by keeping the CKE pins driven high. BIOS may
set it to 1 during DRAM initialization and DDRIO training. This bit should be set to 0
for normal operation.
• 0: The D-Unit dynamically controls the CKE pins to place the
0h DRAM devices in Power Down mode and bring them out of
0
RW Power Down mode.
• 1: The D-Unit constantly drives the CKE pins high to keep the
DRAM devices from entering Power Down mode when ranks
are idle.
Note: This bit is overridden if CKEMODE = 1. This bit does not control CKE behavior
on SR entry/exit.

5.6.14 DRAM Refresh Control (D_CR_DRFC)—Offset 1A38h

Specifies the parameters to control scheduling of refresh commands.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1750h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 0
DISREFDBTCLR
REFSKWDIS

EXTRAREFDBT

MINREFRATE

OREFDIS
RSVD31_22

RSVD19_18

RSVD17_16

REFWMPNC

REFWMHI

RSVD3_1

334818 247
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

31:22
0h Reserved (RSVD31_22): Reserved.
RO

Disable Refresh Debt Clear (DISREFDBTCLR): When set, D-Unit will not clear
refresh debt before Self Refresh SR Entry:

0h • 0: D-Unit sends all postponed REF commands to DRAM before

21 it enters Self Refresh.
RW
• 1: D-Unit enters SR without clearing the Refresh Debt (for
Debug only).
Refresh Skew Disable (REFSKWDIS): Disables Skewing of Refresh Counting
between Ranks. Each rank has its own refresh counter. By default incrementing these
refresh counters are skewed by 1/2 the tREFI period. Setting this bit to a 1 disables
this feature and all refresh counters will increment at the same time per tREFI period.
Skewing the tREFI counters can improve performance since traffic to all ranks does
not have to be blocked to perform refresh.
0h
20
RW • 0: Incrementing the refresh counters are skewed by 1/2 tREFI
period.
• 1: All refresh counters will increment at the same time per
tREFI period.

19:18
0h Reserved (RSVD19_18): Reserved.
RO

17:16
0h Reserved (RSVD17_16): Reserved.
RO

Extra Refresh Debit (EXTRAREFDBT): When set to 1, D-Unit

0h
15 adds one extra refresh debit (for a total of two) on Self-refresh
RW
exit.
Minimum Refresh Rate (MINREFRATE): Ensures that refresh rate never drops
below a certain limit regardless of TQ polling.
• 000: Disable tREFI counter and stop issuing refresh
commands.
• 001: 0.25x refresh rate (i.e. 4x tREFI same as no limit).
1h • 010: 0.5x refresh rate (i.e. 2x tREFI).
14:12
RW • 011: 1x refresh rate (i.e. 1x tREFI).
• 100: 2x refresh rate (i.e. 0.5x tREFI).
• 101: 4x refresh rate (i.e. 0.25x tREFI).
• 110: 4x refresh rate with derating forced on i.e. 0.25x tREFI.
• 111: Reserved.
Refresh Panic Watermark (REFWMPNC): When the Refresh
counter per rank is greater than this value, the D-Unit will send a
7h REF command to the rank regardless of pending requests.
11:8
RW Note: REFWMPNC must be greater than or equal to REFWMHI and
greater than 2, Max Value must be less than 8 to not violate
9xtREFI JEDEC requirement.

248 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Refresh High Watermark (REFWMHI): When the Refresh

counter per rank is greater than this value, the D-Unit will send a
5h REF command to the rank if there is no critical priority requests in
7:4
RW the pending queues.
Note: Value must be greater or equal to 1 and less than or equal
to REFWMPNC.

3:1
0h Reserved (RSVD3_1): Reserved.
RO

Opportunistic Refresh Disable (OREFDIS): Disable opportunistic scheduling of

refresh.
• 0: D-Unit will send a REF command only if there is no pending
0h request to that rank.
0
RW • 1: D-Unit will not send any opportunistic refreshes. Refresh
commands are only sent when the refresh counter is greater
than REFWMHI.
Note: When set, DISREFDBTCLR must also be set to be able to enter SR.

5.6.15 D-Unit Scheduler (D_CR_DSCH)—Offset 1A3Ch

Specifies parameters to control scheduling of commands to DRAM.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 3901C08h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0
WPQCOUNT

RPQCOUNT

BLKRDBF_ADD_RDDATA_CR

INORDERMODE

TMWR_TA_DELTA
BGF_EARLY_RDDATA_VALID

SPID_EARLY_RDDATA_VALID

RSVD15_14
RSVD31

BYPASSEN
BLKRDBF

STRETCHMODE

Bit Default &

Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

334818 249
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

BGF Early Read Data Valid (BGF_EARLY_RDDATA_VALID): Specifies the

number of clocks the D-Unit sends the read data valid through the BGF earlier as
compared to the data.

0h • 00: Always write read valid in same SPID clock as data.

30:29
RW • 01: Always write read valid one SPID clock before data.
• 10: Write read valid up to 2 SPID clocks before data.
• 11: Reserved
SPID Early Read Data Valid
0h (SPID_EARLY_RDDATA_VALID): Specifies the delay in SPID
28:27
RW clocks from RDDATA_VALID assertion to actual data on SPID. The
value should match what is programmed in DDRIO (PHY).
Write Pending Queue Count (WPQCOUNT): Used to limit the
1Ch number of available slots in Write Pending Queue/ Write Data
26:21
RW Buffer. WPQCOUNT will only recognize changes when PMI ISM is
not active.
Read Pending Queue Count (RPQCOUNT): Used to limit the
10h
20:16 number of entries in Read Pending Queue. RPQCOUNT will only
RW
recognize changes when PMI ISM is not active.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

Read Return Data Additional Credits

(BLKRDBF_ADD_RDDATA_CR): Number of additional full
7h cacheline (64B) read data return credits exposed to D-Unit when
13:10
RW BLKRDBF is set.
Note: The value in this field has no effect on Read return credits
when BLKRDBF is not set.
In-Order Mode (INORDERMODE):
• 0h: In order mode disabled: Commands are sent out of order.
• 1h: Partial in order mode: Read and Write CAS commands are
sent in the order they were recieved. ACT and PRE can go out
of order.
0h
9:8
RW • 2h: Full in order mode serialized test: All DRAM commands
CAS ACT PRE associated with a PMI request are issued to DDR
before any DRAM commands for a subsequent PMI request.
• 3h: Reserved.
In order modes should be enabled during init/training/CPGC testing. Should never be
changed while the D-Unit queues are nonempty.

7
0h Idle Bypass Mode Enable (BYPASSEN): Reserved.
RW

Block When RDB Full (BLKRDBF): When set D-Unit stops

0h
6 scheduling new read commands to DRAM when the read data
RW
buffer (RDB) is full.

250 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Stretch Mode (STRETCHMODE): When stretch mode is enabled, commands are

initiated only on Phase 0 of SPIDClk.
• 00: Stretch mode is disabled.
0h
5:4 • 01: Commands are initiated on Phase 0 of every SPID clocks.
RW
• 10: Commands are initiated on Phase 0 of even SPID clocks.
• 11: Commands are initiated on Phase 0 of odd SPID clocks.
Masked Write Turnaround Delta (TMWR_TA_DELTA): The value in this register
8h is subtracted from Masked Write to Read, Masked Write to Write and Masked Write to
3:0 Masked Write turnaround times to account for half BL MWr commands in LPDDR4.
RW
• LPDDR4: = MWr tCCD = MWr BL/2 = 8.

5.6.16 DRAM Calibration Control (D_CR_DCAL)—Offset 1A40h

Specifies parameters to control ZQ Calibration.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1057h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1
ZQCALSTRTR1
ZQCALSTRTR0

RSVD28_23

SRXZQC

RSVD20_18

RSVD15_14
ZQCALTYPE

ZQCLMODE
ZQCDIS

ZQINT

Bit Default &

Field Name (ID): Description
Range Access

ZQ Calibration Type (ZQCALTYPE): Determines whether the

ZQ Calibration is a long or short calibration command (due to
0h
31 ZQCALSTRT).
RW
0: Short calibration (ZQCS).
1: Long calibration (ZQCL).
ZQ Calibration Start Rank 1 (ZQCALSTRTR1): Set this bit to 1
to start the ZQ calibration sequence on Rank 1. This bit will remain
0h a 1 until the ZQ calibration is complete for rank 1, then it will
30
RW/V return to 0.
0: ZQ calibration is done.
1: ZQ calibration has started and is in progress.

334818 251
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

ZQ Calibration Start Rank 0 (ZQCALSTRTR0): Set this bit to 1

to start the ZQ calibration sequence on Rank 0. This bit will remain
0h a 1 until the ZQ calibration is complete for rank 0, then it will
29
RW/V return to 0.
0: ZQ calibration is done.
1: ZQ calibration has started and is in progress.

28:23
0h Reserved (RSVD28_23): Reserved.
RO

Self-Refresh Exit ZQ Calibration Control (SRXZQC):

• 00: On DynSR exit ZQ timer determines the ZQ type. When
the state is lost (i.e due to AutoPG/S0ix) ZQCL is always
performed.
0h • 01: Always perform ZQCL after self refresh exit, in LPDDR4,
22:21
RW ZQ with traffic blocked.
• 10: Always perform ZQCS on SR exit. For LPDDR4, ZQ while
traffic is allowed.
• 11: No ZQCL commands are sent (it disables ZQCAL
commands on SR exit).

20:18
0h Reserved (RSVD20_18): Reserved.
RO

ZQ Calibration Mode (ZQCLMODE): Specifies how ZQCal commands are sent to

different ranks.
0h
17 • 0: ZQCal commands are sent in parallel to all ranks.
RW
• 1: ZQCal commands are sent serially to each rank.
Periodic ZQ Calibration Disable (ZQCDIS):
0h
16 • 0: Periodic ZQ Calibration is Enabled.
RW
• 1: Disable periodic ZQ Calibration.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

ZQ Calibration Interval (ZQINT): Specifies the time interval

1057h
13:0 between two ZQCS (LPDDR3) or ZQ Start (LPDDR4) commands to
RW
a DRAM device. (in RTC 32.8KHz clocks)

5.6.17 VNN Scaling Timer Control (D_CR_VNNTIMER)—Offset

1A4Ch
Specifies parameters for VNN Scaling Timer in D-Unit. The values in this register will be
set by P-code during VNN scaling period.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

252 334818
MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD30_12
VNN_TIMER_EN

VNN_TIMER_TIME
Bit Default &
Field Name (ID): Description
Range Access

VNN Scaling Timer Enable (VNN_TIMER_EN):

0h
31 • 0: The D-Unit VNN Scaling Timer is disabled.
RW
• 1: The D-Unit VNN Scaling Timer is enabled.

30:12
0h Reserved (RSVD30_12): Reserved.
RO

0h VNN Timer Time (VNN_TIMER_TIME): The final timer value

11:0
RW (in 16 x DRAM clocks).

5.6.18 Periodic DRAM Temperature Polling Control (TQ)

(D_CR_TQCTL)—Offset 1A50h
Specifies the control for periodic temperature monitoring and control of DRAM device.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 6C000008h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
TQDATAR1

TQDATAR0

RSVD25_22

RSVD7_5
TQPOLLPER

ENDERATE
SRTEN

TQDATAPUSHEN

TQPOLLEN
TQPOLLSREN

Bit Default &

Field Name (ID): Description
Range Access

TQ Data Rank 1 (TQDATAR1): If Rank 1 is disabled, this value

3h will remain zero.
31:29
RW/V This field contains the data of the last DRAM Mode Register Read
to MR4 MRR issued. It is overwritten with each command.

334818 253
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

TQ Data Rank 0 (TQDATAR0): This field contains the data of

3h
28:26 the last DRAM Mode Register Read to MR4 MRR issued. It is
RW/V
overwritten with each command.

25:22
0h Reserved (RSVD25_22): Reserved.
RO

TQ Poll Period (TQPOLLPER): This sets the frequency by which

0h
21:8 the D-Unit polls the DRAM mode register MR4 to determine
RW
required refresh rate (in 4x tREFI units).

7:5
0h Reserved (RSVD7_5): Reserved.
RO

Self Refresh Temperature Range Enable (DDR3 Only)

(SRTEN): When set, before every Self refresh entry, D-Unit
0h writes a 1 to bit 7 of TQOFFSET.MR_VALUE when TQDATA for that
4
RW rank indicates a value higher then 0x3, and writes a 0 to that bit
otherwise. The new MR_VALUE is then written into MR2 of DDR3
for each enabled rank.
Enable Dynamic Timing Derating (ENDERATE): When set to
1, the Dynamic Timing Derating is enabled. When the D-Unit
1h
3 determines (via TQ polling) that the DRAM requires timing
RW
derating in addition to refresh interval adjustment, the D-Unit will
automatically adjust the relevant timing parameters.
0h Enable TQ Data Push (TQDATAPUSHEN): When set to 1, D-
2
RW Unit pushes the data form the last MR4 read to a punit register.
Enable TQ Poll on Self-Refresh Exit (TQPOLLSREN): This bit
0h
1 enables MR4 read on Self Refresh Exit. If disabled, D-Unit will not
RW
read MR4 value on Self-Refresh exit.
Enable Periodic TQ Poll (TQPOLLEN): This bit enables periodic
0h
0 TQ Poll. If disabled, D-Unit will not read MR4 value periodically.
RW
Note: Will be enabled only if refreshes are enabled.

5.6.19 TQ Temperature Offset Control (D_CR_TQOFFSET)—Offset

1A54h
Specifies temperature offset and refresh rate adjustments requested by software.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

254 334818
MCHBAR

MR_VALUE

MR3_OFFSET_UPDATE
RSVD31_26

RSVD15_11

MR4_ADDER

RSVD7_3

MR3_THERM_OFFSET
Bit Default &
Field Name (ID): Description
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

MR Value (MR_VALUE): MR2 Shadow Register (DDR3L Only):

0h BIOS writes the correct value of MR2 register in DDR3L into this
25:16
RW field at boot time. D-Unit modifies one bit and rewrites the MR2
into DDR3L DRAM before SR entry.

15:11
0h Reserved (RSVD15_11): Reserved
RO

MR4 Adder (MR4_ADDER): D-Unit adds the value of this field to

0h
10:8 TQDATA read from MR4 the resulting value is used to control
RW
refresh rate and AC timing derating.

7:3
0h Reserved (RSVD7_3): Reserved.
RO

MR3 Offset Update (MR3_OFFSET_UPDATE): When set, D-

0h Unit writes the merged value of MR3_VALUE and
2
RW/V MR3_THERM_OFFSET into MR3 of DRAM. D-Unit clears this bit
once the value is written.

1:0
0h MR3 Thermal Offset (MR3_THERM_OFFSET): Reserved.
RW

5.6.20 Data Scrambler (D_CR_SCRAMCTRL)—Offset 1AA4h

Specifies parameters to control data scrambling in D-Unit.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCRM_EN

RSVD27_16
RSVD30

CLOCKGATE

KEY

334818 255
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Enable Data Scrambler (SCRM_EN): When set to 1, data

0h
31 scrambling is enabled. When set to 0, data scrambling is disabled.
RW
Should be set before D_CR_BGF_CTL_BGF_RUN is set to 1.

30
0h Reserved (RSVD30): Reserved.
RO

Scrambler Clock Gate Select (CLOCKGATE): This field controls how the scrambler
output code is clock gated to reduce power.
• 00: Clock gate disabled.
0h
29:28 • 01: Clock Gate every 2 cycle.
RW
• 10: Clock Gate every 3 cycle.
• 11: Clock Gate every 4 cycle.

27:16
0h Reserved (RSVD27_16): Reserved.
RO

0h Scrambling Key (KEY): Sets the key for the scrambler. The key
15:0
RW should be a random value that is set following each cold boot.

5.6.21 Error Injection Address Register (D_CR_ERR_INJ)—Offset

1AACh
Contains the target address for ECC error injection.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADDRESS
RSVD31

RSVD0

Bit Default &

Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

Error Injection Target Address (ADDRESS): Specifies the PMI

0h address of the write transaction to be injected with the error. Only
30:1
RW applicable to Write transactions. Read/under-fill read of the partial
write operation is not affected.

0
0h Reserved (RSVD0): Reserved.
RO

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5.6.22 Error Injection Control Register (D_CR_ERR_INJ_CTL)—

Offset 1AB0h
Controls injecting correctable or uncorrectable errors into the write requests specified
by target address.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD31_4

SEL_HI
EN_HI
SEL_LO
EN_LO
Bit Default &
Field Name (ID): Description
Range Access

31:4
0h Reserved (RSVD31_4): Reserved
RO

Error Injection Type Higher 32B (SEL_HI): If enabled, the error injection is
continuously armed for ERR_INJ.ADDR 32B write address matching until it is cleared.
• 00: No error injection.
• 01: Uncorrectable Error (UE) is armed for write address
matching to inject UE by using the same poisoning scheme,
0h i.e. inverting corresponding write ECC[6:0] on QW0 of the 32B
3
RW data.
• 10: Correctable Error (CE) is armed for write address
matching to inject CE by inverting corresponding write ECC[0]
on QW0 of the 32B data.
• 11: Reserved.
Error Injection Enable Higher 32B (EN_HI): When set the
0h
2 error injection is continuously armed for higher 32B of
RW
D_CR_ERR_INJ_ADDR write address matching until it is cleared.
Error Injection Type Lower 32B (SEL_LO): 0 - Uncorrectable
Error (UE) is armed for write address matching to inject UE by
using the same poisoning scheme, i.e. inverting corresponding
0h
1 write ECC[6:0] on every QW of the 32B data.
RW
1 - Correctable Error (CE) is armed for write address matching to
inject CE by inverting corresponding write ECC[0] on every QW of
the 32B data.
Error Injection Enable Lower 32B (EN_LO): When set, the
0h
0 error injection is continuously armed for lower 32B of
RW
D_CR_ERR_INJ_ADDR write address matching until it is cleared.

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5.6.23 Error Log Register (D_CR_ERR_ECC_LOG)—Offset 1AB4h

Detected ECC errors are captured in this register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYNDROME_QW

TAG
CLEAR

CERR
MERR
ECC_VISA

ERR_BURST

ERR_CHUNK

Bit Default &

Field Name (ID): Description
Range Access

0h Clear (CLEAR): Setting this bit to one clears all fields in this
31
RW/V register, including itself.
PMI VISA Byte Select (ECC_VISA): Select ECC or PMI byte on VISA :
• 00: ECC byte,
0h
30:29 • 01: PMI Data Byte [7:0],
RW
• 10: PMI Data Byte [63:56],
• 11: PMI Data Byte [255:248]
Correctable Single-bit Error (CERR): This bit is set when a
correctable single-bit error occurs on a memory read data
transfer. When this bit is set, the address that caused the error
0h
28 and the error syndrome are also logged and they are locked to
RW/V
further single bit errors, until this bit is cleared. A multiple bit
error that occurs after this bit is set will override the address/error
syndrome information.
Uncorrectable Multiple-bit Error (MERR): This bit is set when
an uncorrectable multiple-bit error occurs on a memory read data
0h
27 transfer. When this bit is set, the address that caused the error
RW/V
and the error syndrome are also logged and they are locked until
this bit is cleared.
0h Error Burst Number (ERR_BURST): Burst number (in BL8) of
26:25
RW/V the error within a chunk.
Error Chunk Number (ERR_CHUNK): Chunk number of the
0h error.
24
RW/V 0 - lower 32B chunk has error if MERR/CERR is set
1 - higher 32B chunk has the error if MERR/CERR is set

258 334818
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Bit Default &

Field Name (ID): Description
Range Access

0h Quad Word ECC Syndrome (SYNDROME_QW): ECC Syndrome

23:16
RW/V for a QW (64 bit) within 32B Address
0h Request Tag (TAG): Read Return Tag matches with the PMI
15:0
RW/V Request Tag which triggered the error log.

5.6.24 D-Unit Status (D_CR_DFUSESTAT)—Offset 1ABCh

Contains the values read from D-Unit fuses.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FUSESTAT
RSVD31_16

Bit Default &

Field Name (ID): Description
Range Access

31:16
0h Reserved (RSVD31_16): Reserved.
RO

D-Unit Status (FUSESTAT): D-Unit bits are captured into this register and are
available to be read.
• [0]: fus_dun_ecc_dis.
• [3:1]: fus_dun_max_supported_device_size[2:0].
0h • [4:4]: fus_dun_lpddr3_dis.
15:0
RO/V
• [5:5]: fus_dun_lpddr4_dis.
• [6:6]: reserved.
• [7:7]: fus_dun_ddr3l_dis.
• [15:8]: reserved.

5.6.25 Major Mode Control (D_CR_MMC)—Offset 1B24h

Specifies parameters to control read/write major mode operation and transitions.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

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 MCHBAR

Default: 2B01E518h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0RSVD31_30 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0

RSVD22_18
RAW_WMM

RSVD26

WMMEXIT
RIMPRIO

WIMTHRS

WMMENTRY
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

RAW Conflict Read Priority for WMM Transition

(RAW_WMM): If a conflict read reaches this priority (or greater
depending on access class occupancy), WMM will be triggered to
5h
29:27 unblock the corresponding write. D-Unit will stay in WMM until
RW
corresponding write is issued.
Note: The value in this bit must not be higher than lowest terminal
priority level of each access class.

26
0h Reserved (RSVD26): Reserved.
RO

6h Read Isoch Trigger Priority (RIMPRIO): If any read in the

25:23
RW RPQ is at this programmable priority, RIM is triggered.

22:18
0h Reserved (RSVD22_18): Reserved.
RO

Write Isoch Threshold (WIMTHRS): When the number of

1Eh entries in WPQ is greater than or equal to this value (higher than
17:12
RW WMM entry watermark, less than WPQ size), it triggers write isoch
mode (WIM).
Write Major Mode Exit Watermark (WMMEXIT): When the
14h
11:6 number of entries in WPQ is less than this value, the D-Unit will
RW
switch back to read major mode.
Write Major Mode Entry Watermark (WMMENTRY): When
18h the number of entries in WPQ is greater than or equal to this
5:0
RW value, the D-Unit will switch to write major mode (WMM).
Note: the value must not be set to 0.

5.6.26 Major Mode RD/WR Counter (Set A and B)

(D_CR_MMRDWR_AB)—Offset 1B28h
Minimum read and maximum write counter control. This register defines the minimum
number of reads in RMM and maximum number of writes in WMM before a mode
transition happens.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

260 334818
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Default: 1F207C8h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0

RSVD31_26

RSVD13_12
MINRDB
MAXWRB

MINRDA
MAXWRA
Bit Default &
Field Name (ID): Description
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

1Fh Max Writes B (MAXWRB): Maximum number of writes D-Unit

25:20
RW can send in WMM mode before returning to RMM (set B).
8h Min Reads B (MINRDB): Minimum number of reads that has to
19:14
RW be serviced before a switch to WMM is allowed (set B).

13:12
0h Reserved (RSVD13_12): Reserved.
RO

1Fh Max Writes A (MAXWRA): Maximum number of writes D-Unit

11:6
RW can send in WMM mode before returning to RMM (set A).
8h Min Reads A (MINRDA): Minimum number of reads that has to
5:0
RW be serviced before a switch to WMM is allowed (set A).

5.6.27 Major Mode RD/WR Counter (Set C and D)

(D_CR_MMRDWR_CD)—Offset 1B2Ch
Minimum read and maximum write counter control. This register defines the minumum
number of reads in RMM and maximum number of writes in WMM before a mode
transition happens (sets C and D).

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F207C8h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0
MINRDC
RSVD31_26

RSVD13_12

MAXWRC
MAXWRD

MINRDD

334818 261
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Bit Default &

Field Name (ID): Description
Range Access

31:26
0h Reserved (RSVD31_26): Reserved.
RO

1Fh Max Writes D (MAXWRD): Maximum number of writes D-Unit

25:20
RW can send in WMM mode before returning to RMM (set D).
8h Min Reads D (MINRDD): Minimum number of reads that has to
19:14
RW be serviced before a switch to WMM is allowed (set D).

13:12
0h Reserved (RSVD13_12): Reserved.
RO

1Fh Max Writes C (MAXWRC): Maximum number of writes D-Unit

11:6
RW can send in WMM mode before returning to RMM (set C).
8h Min Reads C (MINRDC): Minimum number of reads that has to
5:0
RW be serviced before a switch to WMM is allowed (set C).

5.6.28 Access Class Initial Priority (D_CR_ACCIP)—Offset 1B30h

Each field of this register defines the initial priority of one access class.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 17C2h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 1 0
AC4IP

AC3IP

AC2IP

AC1IP

AC0IP
RSVD31_15

Bit Default &

Field Name (ID): Description
Range Access

31:15
0h Reserved (RSVD31_15): Reserved.
RO

1h Access Class 4 Initial Priority (AC4IP): Initial priority level of

14:12
RW read requests coming with access class 4.
3h Access Class 3 Initial Priority (AC3IP): Initial priority level of
11:9
RW read requests coming with access class 3.
7h Access Class 2 Initial Priority (AC2IP): Initial priority level of
8:6
RW read requests coming with access class 2.
0h Access Class 1 Initial Priority (AC1IP): Initial priority level of
5:3
RW read requests coming with access class 1.
2h Access Class 0 Initial Priority (AC0IP): Initial priority level of
2:0
RW read requests coming with access class 0.

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5.6.29 Access Class 0 Priority Promotion Control

(D_CR_RD_PROM0)—Offset 1B34h
This register defines the priority promotion policy for access class 0. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
next level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F52940h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0
P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
RSVD31_30

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
Ah Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.6.30 Access Class 1 Priority Promotion Control

(D_CR_RD_PROM1)—Offset 1B38h
This register defines the priority promotion policy for access class 1. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
associated level and the request has reached its maximum priority.

Access Method

334818 263
 MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 14000000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

Ah Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.6.31 Access Class 2 Priority Promotion Control

(D_CR_RD_PROM2)—Offset 1B3Ch
This register defines the priority promotion policy for access class 2. Each field of this
register defines the number of CASes that pass before the request is promoted to the
next priority level. A value of 31 indicates the request should never be promoted to the
next level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

264 334818
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P6RES

P5RES

P4RES

P3RES

P2RES

P1RES
RSVD31_30
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
0h Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
0h Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
0h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.6.32 Access Class 3 Priority Promotion Control

(D_CR_RD_PROM3)—Offset 1B40h
This register defines the aging policy for access class 3. Each field of this register
defines the number of CASes that pass before the request is promoted to the next
priority level. A value of 31 indicates the request should never be promoted to the next
level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F29400h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

334818 265
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
5h Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.
5h Priority 3 Residency (P3RES): Number of CASes that pass
14:10
RW before a request in this priority promotes to the next priority level.
0h Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
0h Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.6.33 Access Class 4 Priority Promotion Control

(D_CR_RD_PROM4)—Offset 1B44h
This register defines the aging policy for access class 3. Each field of this register
defines the number of CASes that pass before the request is promoted to the next
priority level. A value of 31 indicates the request should never be promoted to the next
level and the request has reached its maximum priority.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1F5294Ah

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0
RSVD31_30

P6RES

P5RES

P4RES

P3RES

P2RES

P1RES

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (RSVD31_30): Reserved.
RO

0h Priority 6 Residency (P6RES): Number of CASes that pass

29:25
RW before a request in this priority promotes to the next priority level.
1Fh Priority 5 Residency (P5RES): Number of CASes that pass
24:20
RW before a request in this priority promotes to the next priority level.
Ah Priority 4 Residency (P4RES): Number of CASes that pass
19:15
RW before a request in this priority promotes to the next priority level.

266 334818
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Bit Default &

Field Name (ID): Description
Range Access

Ah Priority 3 Residency (P3RES): Number of CASes that pass

14:10
RW before a request in this priority promotes to the next priority level.
Ah Priority 2 Residency (P2RES): Number of CASes that pass
9:5
RW before a request in this priority promotes to the next priority level.
Ah Priority 1 Residency (P1RES): Number of CASes that pass
4:0
RW before a request in this priority promotes to the next priority level.

5.6.34 Deadline Threshold (D_CR_DL_THRS)—Offset 1B48h

Specifies when the request with initial priority 0 get promoted to a higher priority level.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 6h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

DEADLINE_THRS
RSVD31_11

Bit Default &

Field Name (ID): Description
Range Access

31:11
0h Reserved (RSVD31_11): Reserved.
RO

Deadline Threshold (DEADLINE_THRS): A requests with initial

priority of 0 will exit priority 0 when its deadline is equal or less
6h
10:0 than this value plus current time. This field does not affect the
RW
priority of any requests in access classes with initial priority bigger
than 0.

5.6.35 Major Mode Blocking Rules Control (D_CR_MM_BLK)—

Offset 1B4Ch
This register controls blocking rules enforced in RMM and WMM.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1800h

334818 267
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3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0

RSVD31_25

RSVD23_20

RSVD15_14
WMM_REG_R1

WMM_PRIO_R4
WMM_PRIO_R3
WMM_PRIO_R2
WMM_PRIO_R1

RMM_REG_R6
RMM_REG_R5
RMM_REG_R4
RMM_REG_R3
RMM_REG_R2
RMM_REG_R1

RSVD7_4

RMM_PRIO_R4
RMM_PRIO_R3
RMM_PRIO_R2
RMM_PRIO_R1
Bit Default &
Field Name (ID): Description
Range Access

31:25
0h Reserved (RSVD31_25): Reserved.
RO

0h WMM Regular Rule 1 (WMM_REG_R1): Disable WMM unsafe

24
RW write page hits block safe write page misses same bank.

23:20
0h Reserved (RSVD23_20): Reserved.
RO

WMM Priority Rule 4 (WMM_PRIO_R4): Disable WMM unsafe

priority 1 read miss block write hit to same bank.
0h
19 Note: This rule does not block the bank that is being blocked by
RW
WMM_PRIO_R3.
Priority rules 1, 3 and 4 should be enabled/disabled together.
WMM Priority Rule 3 (WMM_PRIO_R3): Disable WMM unsafe
priority 1 write hit block write miss to same bank.
0h
18 Note: This rule does not block the bank that is being blocked by
RW
WMM_PRIO_R1.
Priority rules 1,3 and 4 should be enabled/disabled together.
0h WMM Priority Rule 2 (WMM_PRIO_R2): Disable WMM CAS
17
RW block rule.
WMM Priority Rule 1 (WMM_PRIO_R1): Disable WMM unsafe
0h
16 top priority 1 write miss block write hit same bank.
RW
Priority rules 1, 3 and 4 should be enabled/disabled together.

15:14
0h Reserved (RSVD15_14): Reserved.
RO

0h RMM Regular Rule 6 (RMM_REG_R6): Disable RMM unsafe

13
RW write page hits block safe write page misses same bank.
RMM Regular Rule 5 (RMM_REG_R5): Disable RMM unsafe
read page miss block all safe and unsafe write page hit to the
1h
12 same bank.
RW
Note: This field must not be set to 0 (enabled) if RMM_REG_R4 is
also 0.
RMM Regular Rule 4 (RMM_REG_R4): Disable RMM unsafe
1h write page hit block safe read page miss same bank.
11
RW Note: This field must not be set to 0 (enabled) if RMM_REG_R5 is
also 0.

268 334818
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Bit Default &

Field Name (ID): Description
Range Access

RMM Regular Rule 3 (RMM_REG_R3): Disable RMM unsafe

0h read page hit block safe read and write page miss same bank.
10
RW Note: This rule does not block the bank that is being blocked by
RMM_PRIO_R3 and RMM_PRIO_R1.
0h RMM Regular Rule 2 (RMM_REG_R2): Disable RMM unsafe
9
RW read page empty block safe write page empty same rank.
0h RMM Regular Rule 1 (RMM_REG_R1): Disable RMM unsafe
8
RW read page hit block safe write page hit same rank.

7:4
0h Reserved (RSVD7_4): Reserved.
RO

RMM Priority Rule 4 (RMM_PRIO_R4): Disable RMM unsafe

critical read miss block read and write hit to same bank.
0h
3 Note: This rule does not block the bank that is being blocked by
RW
RMM_PRIO_R3.
Priority rules 1, 3 and 4 should be enabled/disabled together.
RMM Priority Rule 3 (RMM_PRIO_R3): Disable RMM unsafe
critical read hit block read and write miss to same bank.
0h
2 Note: This rule does not block the bank that is being blocked by
RW
RMM_PRIO_R1.
Priority rules 1, 3 and 4 should be enabled/disabled together.
0h RMM Priority Rule 2 (RMM_PRIO_R2): Disable RMM CAS block
1
RW rule.
RMM Priority Rule 1 (RMM_PRIO_R1): Disable RMM unsafe
0h top critical read miss block read and write hit same bank.
0
RW Note: Priority rules 1, 3 and 4 should be enabled/disabled
together.

5.6.36 DRAM Self-Refresh Command (D_CR_DRAM_SR_CMD)—

Offset 1B54h
Self refresh command register to allow sending WAKE and SUSPEND messages to D-
Unit. (Only one bit can be set at a time). Posted writes to this register are not
completed until hardware clears the field.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SUSPEND

WAKE
RSVD31_4

SUSPENDP

RSVD1

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Bit Default &

Field Name (ID): Description
Range Access

31:4
0h Reserved (RSVD31_4): Reserved.
RO

SUSPENDP (SUSPENDP): A SUSPENDP message will put the

DRAM into self-refresh mode. The D-Unit will complete servicing
outstanding memory requests and flush all queued Refresh
commands to DRAM before putting the DRAM in self refresh mode.
0h Finally, a PM message will be sent to the PHY. The bit is cleared by
3
RW/V hardware after the PHY indicates the transition requested in the
PM message has been completed. D-Unit will perform an MRW to
MR17 with an opcode as defined by DPMC0.PASR before it places
the DRAM into Self-Refresh.

SUSPEND (SUSPEND): A SUSPEND message will put the DRAM

into self-refresh mode. The D-Unit will complete servicing
outstanding memory requests and flush all queued Refresh
commands to DRAM before putting the DRAM in Self Refresh
0h
2 mode. Finally, a PM message will be sent to the PHY. The bit is
RW/V
cleared by hardware only after the PHY indicates the transition
requested in the PM message has been completed.
Note: When COLDWAKE is set prior of setting this bit the DRAM
will not be placed in SR.

1
0h Reserved (RSVD1): Reserved.
RO

WAKE (WAKE): Take PHY out of PM states and wakes the DRAM
out of self refresh mode. The bit is cleared by hardware only when
0h
0 the DRAM has exited out of self refresh mode and is accessible.
RW/V
Note: When COLDWAKE is set prior of setting this bit the D-Unit
will not send SR exit command and will not set the DCO.IC bit.

Bit Default &

Field Name (ID): Description
Range Access

Clear Mask (CLEAR_MASK): Mask ANDed with pseudo-random

FFFFFFFFh
31:0 data. Resets to all 1s. Setting bit n to 0 in this register will force
RW
every nth bit in the data to be set to 0

5.6.37 DQS Retraining Control (D_CR_DQS_RETRAINING_CTL)—

Offset 1B80h
LPDDR4 DQS Retraining control register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD15_14

DQS_RETRAIN_EN
RSVD3_2

DQS_RETRAIN_SRX_EN
DQS_RETRAIN_INT

DQS_OSC_RT
Bit Default &
Field Name (ID): Description
Range Access

DQS Periodic Retraining Interval (DQS_RETRAIN_INT):

0h
31:16 This sets the frequency by which the D-Unit initiates periodic
RW
retraining (in 1x NREFI).

15:14
0h Reserved (RSVD15_14): Reserved.
RO

DQS Oscillator Runtime (DQS_OSC_RT): After D-Unit starts

DQS oscillator, it must wait this amount of time before being able
0h
13:4 to read the value in MR18 and MR19 (in 16x DRAM clocks).
RW
Value in this register must be at least equal to DRAM's MR23
value. + tOSCO.

3:2
0h Reserved (RSVD3_2): Reserved.
RO

DQS Retrain SRX Exit (DQS_RETRAIN_SRX_EN): Enable

0h retraining on SR exit.
1
RW This bit enables LPDDR4 DQS retraining on Self Refresh Exit. If
disabled, D-Unit will not perform retraining on SR exit.
DQS Retrain Enable (DQS_RETRAIN_EN): Periodic retraining
enable:
0h This bit enables periodic DQS retraining. If disabled, D-Unit will
0
RW not perform retraining periodically.
Note: Will be enabled only if DCO.IC is set and refreshes are
enabled in DRF.MINREFRATE.

5.6.38 MR4 De-Swizzle Control (D_CR_MR4_DESWIZZLE)—Offset

1B84h
Controls the data bits swizzling crossbar for MR4.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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MR4_BYTE_SEL2
MR4_BIT2_SEL2

MR4_BIT1_SEL2

MR4_BIT0_SEL2

MR4_BYTE_SEL
RSVD31

RSVD27

RSVD23

RSVD19_18

RSVD15

MR4_BIT2_SEL

RSVD11

MR4_BIT1_SEL

RSVD7

MR4_BIT0_SEL

RSVD3_2
Bit Default &
Field Name (ID): Description
Range Access

31
0h Reserved (RSVD31): Reserved.
RO

0h MR4 Bit 2 Select 2nd Byte (MR4_BIT2_SEL2): Selects bit 2 of

30:28
RW MR4 data.

27
0h Reserved (RSVD27): Reserved
RO

0h MR4 Bit 1 Select 2nd Byte (MR4_BIT1_SEL2): Selects bit 1 of

26:24
RW MR4 data

23
0h Reserved (RSVD23): Reserved
RO

0h MR4 Bit 0 Select 2nd Byte (MR4_BIT0_SEL2): Selects bit 0 of

22:20
RW MR4 data.

19:18
0h Reserved (RSVD19_18): Reserved
RO

0h MR4 Byte 2 Select (MR4_BYTE_SEL2): Selects byte position of

17:16
RW the MR4 data for second device.

15
0h Reserved (RSVD15): Reserved
RO

14:12
0h MR4 Bit 2 Select (MR4_BIT2_SEL): Selects bit 2 of MR4 data.
RW

11
0h Reserved (RSVD11): Reserved.
RO

10:8
0h MR4 Bit 1 Select (MR4_BIT1_SEL): Selects bit 1 of MR4 data.
RW

7
0h Reserved (RSVD7): Reserved.
RO

6:4
0h MR4 Bit 0 Select (MR4_BIT0_SEL): Selects bit 0 of MR4 data.
RW

3:2
0h Reserved (RSVD3_2): Reserved.
RO

0h MR4 Byte Select (MR4_BYTE_SEL): Selects byte position of

1:0
RW the MR4 data first device.

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5.7 Registers Summary

Table 5-7. Summary of pcs_regs_wrapper Registers
Offset Offset
Register Name (ID)—Offset Default Value
Start End

Thermal Device Mailbox Data0

7000h 7003h (P_CR_THERMAL_MAILBOX_DATA0_0_0_0_MCHBAR)—Offset 0h
7000h

Thermal Device Mailbox Data1

7004h 7007h (P_CR_THERMAL_MAILBOX_DATA1_0_0_0_MCHBAR)—Offset 0h
7004h

Thermal Device Mailbox Interface

7008h 700Bh (P_CR_THERMAL_MAILBOX_INTERFACE_0_0_0_MCHBAR)— 0h
Offset 7008h

Thermal Device IRQ and Lock Configuration

700Ch 700Fh (P_CR_THERMAL_DEVICE_IRQ_0_0_0_MCHBAR)—Offset 0h
700Ch

Package Thermal Interrupt Control

7010h 7013h (P_CR_PKG_THERM_INTERRUPT_0_0_0_MCHBAR)—Offset 0h
7010h

ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0
_0_MCHBAR
7014h 7017h 0h
(P_CR_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_M
CHBAR)—Offset 7014h

Package Thermal Status

701Ch 701Fh 0h
(P_CR_PKG_THERM_STATUS_0_0_0_MCHBAR)—Offset 701Ch

LPDDR DRAM Thermal (MR4) Status of Channel 01

7024h 7027h (P_CR_MEM_MR4_TEMPERATURE_DEV1_0_0_0_MCHBAR)— 0h
Offset 7024h

LPDDR DRAM Thermal (MR4) Status of Channel 10

7028h 702Bh (P_CR_MEM_MR4_TEMPERATURE_DEV2_0_0_0_MCHBAR)— 0h
Offset 7028h

Machine Check Error Source Log

702Ch 702Fh 0h
(P_CR_MCA_ERROR_SRC_0_0_0_MCHBAR)—Offset 702Ch

DDR Thermal Throttling Control

7030h 7033h (P_CR_DDR_THERM_THRT_CTRL_0_0_0_MCHBAR)—Offset 0h
7030h

DDR Thermal Interrupt Control

7034h 7037h (P_CR_DDR_THERM_INTERRUPT_0_0_0_MCHBAR)—Offset 0h
7034h

DDR Thermal Status

7038h 703Bh 0h
(P_CR_DDR_THERM_STATUS_0_0_0_MCHBAR)—Offset 7038h

Dram Energy Counter

7048h 704Bh (P_CR_DDR_ENERGY_STATUS_0_0_0_MCHBAR)—Offset 0h
7048h

DDR RAPL Performance Status

704Ch 704Fh (P_CR_DDR_RAPL_PERF_STATUS_0_0_0_MCHBAR)—Offset 58F0h
704Ch

Package RAPL Performance Status

7050h 7053h (P_CR_PACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR)— 0h
Offset 7050h

IA Core Performance / Power Priority Control

7054h 7057h (P_CR_PRIMARY_PLANE_TURBO_PLCY_0_0_0_MCHBAR)— 0h
Offset 7054h

Graphics Performance / Power Priority Control

7058h 705Bh (P_CR_SECONDARY_PLANE_TURBO_PLCY_0_0_0_MCHBAR)— 10h
Offset 7058h

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Table 5-7. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

IA Energy Counter
705Ch 705Fh (P_CR_PRIMARY_PLANE_ENERGY_STATUS_0_0_0_MCHBAR) 0h
—Offset 705Ch

Graphics Energy Counter

7060h 7063h (P_CR_SECONDARY_PLANE_ENERGY_STATUS_0_0_0_MCHBA 0h
R)—Offset 7060h

PACKAGE_POWER_SKU_UNIT
7068h 706Bh (P_CR_PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR)— 330A0E08h
Offset 7068h

SOC Energy Counter

706Ch 706Fh (P_CR_PACKAGE_ENERGY_STATUS_0_0_0_MCHBAR)—Offset 0h
706Ch

GT_PERF_STATUS
7070h 7073h 0h
(P_CR_GT_PERF_STATUS_0_0_0_MCHBAR)—Offset 7070h

Temperature Reference and Control

7074h 7077h (P_CR_TEMPERATURE_TARGET_0_0_0_MCHBAR)—Offset 5A0000h
7074h

BIOS Reset Completion

7078h 707Bh 0h
(P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)—Offset 7078h

BIOS_MAILBOX_DATA
7080h 7083h 0h
(P_CR_BIOS_MAILBOX_DATA_0_0_0_MCHBAR)—Offset 7080h

BIOS_MAILBOX_INTERFACE
7084h 7087h (P_CR_BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR)—Offset 0h
7084h

CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
7088h 708Bh (P_CR_CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR)— 0h
Offset 7088h

GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
708Ch 708Fh (P_CR_GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBA 0h
R)—Offset 708Ch

SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
7090h 7093h (P_CR_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_ 0h
MCHBAR)—Offset 7090h

Memory Frequency Status

7094h 7097h (P_CR_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_0_0_MC 0h
HBAR)—Offset 7094h

Package Power SKU and RAPL Power Control Capabilities

70A0h 70A7h (P_CR_PACKAGE_POWER_SKU_0_0_0_MCHBAR)—Offset 12024000600118h
70A0h

Package RAPL Power Limit

70A8h 70AFh (P_CR_PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR)—Offset 0h
70A8h

IA_PERF_LIMIT_REASONS
70B0h 70B3h (P_CR_IA_PERF_LIMIT_REASONS_0_0_0_MCHBAR)—Offset 0h
70B0h

IA Core C0 Residency Counter

70C0h 70C3h (P_CR_TELEM_IA_C0_RESIDENCY_0_0_0_MCHBAR)—Offset 0h
70C0h

Graphics C0 Residency Counter

70C4h 70C7h (P_CR_TELEM_GT_C0_RESIDENCY_0_0_0_MCHBAR)—Offset 0h
70C4h

I-unit Processing System C0 Residency Counter

70C8h 70CBh (P_CR_TELEM_IUNIT_C0_RESIDENCY_0_0_0_MCHBAR)— 0h
Offset 70C8h

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Table 5-7. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

TELEM_IA_FREQ_ACCUMULATOR
70CCh 70CFh (P_CR_TELEM_IA_FREQ_ACCUMULATOR_0_0_0_MCHBAR)— 0h
Offset 70CCh

Graphics C0 Residency Counter

70D0h 70D3h (P_CR_TELEM_GT_FREQ_ACCUMULATOR_0_0_0_MCHBAR)— 0h
Offset 70D0h

I-unit Processing System C0 Residency Counter

70D4h 70D7h (P_CR_TELEM_IUNIT_FREQ_ACCUMULATOR_0_0_0_MCHBAR) 0h
—Offset 70D4h

Memory Active Residency

70E8h 70EFh (P_CR_TELEM_FAR_MEMORY_ACTIVE_0_0_0_MCHBAR)— 0h
Offset 70E8h

Package Temperatures
70F4h 70F7h (P_CR_PACKAGE_TEMPERATURES_0_0_0_MCHBAR)—Offset 0h
70F4h

Package Thermal Limit Control

7104h 7107h (P_CR_THERMAL_LIMIT_CONTROL_0_0_0_MCHBAR)—Offset 0h
7104h

Memory Subsystem Frequency Capabilities

7108h 710Bh (P_CR_MEMSS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR) 0h
—Offset 7108h

Memory Controller (MC) BIOS Reset Request and Status

7114h 7117h 0h
(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR)—Offset 7114h

MEMSS_FREQUENCY_CAPABILITIES1
7118h 711Bh (P_CR_MEMSS_FREQUENCY_CAPABILITIES1_0_0_0_MCHBAR 0h
)—Offset 7118h

PP1_C0_CORE_CLOCK_0_0_0_MCHBAR
7160h 7163h (P_CR_PP1_C0_CORE_CLOCK_0_0_0_MCHBAR)—Offset 0h
7160h

Core Exists Vector

7164h 7167h (P_CR_CORE_EXISTS_VECTOR_0_0_0_MCHBAR)—Offset 0h
7164h

Software Core Disable Mask

7168h 716Bh (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR)—Offset 0h
7168h

PL3 and PL4 Control

71F0h 71F7h 0h
(P_CR_PL3_CONTROL_0_0_0_MCHBAR)—Offset 71F0h

Graphics Superqueue Active Clocks

7244h 7247h (P_CR_PP1_ANY_THREAD_ACTIVITY_0_0_0_MCHBAR)— 0h
Offset 7244h

LPDDR DRAM Thermal (MR4) Status of Channel 00

7248h 724Bh (P_CR_MEM_MR4_TEMPERATURE_DEV3_0_0_0_MCHBAR)— 0h
Offset 7248h

LPDDR DRAM Thermal (MR4) Status of Channel 11

724Ch 724Fh (P_CR_MEM_MR4_TEMPERATURE_DEV4_0_0_0_MCHBAR)— 0h
Offset 724Ch

5.7.1 Thermal Device Mailbox Data0

(P_CR_THERMAL_MAILBOX_DATA0_0_0_0_MCHBAR)—
Offset 7000h
This register represents the lower 32b of the thermal mailbox data. THIS REGISTER IS
DUPLICATED IN THE PCU IO SPACE, CHANGES MUST BE MADE IN BOTH PLACES

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Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA
Bit Default &
Field Name (ID): Description
Range Access

0h DATA[31:0] (DATA): This field contains the low 32 bits of data

31:0
RW/V associated with specific commands.

5.7.2 Thermal Device Mailbox Data1

(P_CR_THERMAL_MAILBOX_DATA1_0_0_0_MCHBAR)—
Offset 7004h
This register represents the upper 32b of the thermal mailbox data. THIS REGISTER IS
DUPLICATED IN THE PCU IO SPACE, CHANGES MUST BE MADE IN BOTH PLACES

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA

Bit Default &

Field Name (ID): Description
Range Access

0h DATA[63:32] (DATA): This field contains the low 32 bits of data

31:0
RW/V associated with specific commands.

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5.7.3 Thermal Device Mailbox Interface

(P_CR_THERMAL_MAILBOX_INTERFACE_0_0_0_MCHBAR
)—Offset 7008h
This register implements the control and response of the Thermal Device Mailbox.
Software may use this mailbox to configure and query various parameters into SOC
thermal / power control. This particular register is responsible for initiating requests to
the thermal device and reading responses. THIS REGISTER IS DUPLICATED IN THE PCU
IO SPACE, CHANGES MUST BE MADE IN BOTH PLACES

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADDR_CNTL
RUN_BUSY

RSVD

COMMAND
Bit Default &
Field Name (ID): Description
Range Access

Run/Busy (RUN_BUSY): The run/busy control is used for managing the

semaphore on the mailbox interface. Typical usage involves the following flow:

• Software waits for the interface run/busy bit to clear.

• Software writes the mailbox data registers as appropriate for
this command.
• Software writes a command encoding and sets the run/busy
bit in the interface register.
• Software waits for the interface run/busy bit to clear to
0h
31 indicate the command has been handled.
RW/1S/V
• Software queries the completion code in the command field of
the interface register to ensure it passed (0b indicates pass)
Bit encoding for the run/busy:

• 0 = The thermal mailbox is idle or the last request has been

completed. Software may initiate new requests.
• 1 = The thermal mailbox is busy. The thermal device is still
handling a request. Writes to thermal mailbox are not allowed
at this time.
0h
30:29 Reserved.
RO

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Bit Default &

Field Name (ID): Description
Range Access

Additional Parameters (ADDR_CNTL): This field is used as an

additional modifier to the command encoding for incoming
0h mailbox requests. In thermal device mailbox responses, this field
28:8
RW/V is always zero. The applicability of this additional parameter field
is handled on a case by case basis for the services supplied by this
mailbox
Command / Completion Code (COMMAND): For incoming
requests (where run/busy=1), this field represents the command
opcode. For responses (where run/busy=0), this field represents
0h
7:0 the response completion code. A completion code of 0b indicates
RW/V
passing, all other completion codes indicate failure. For detailed
definition of services provided by this mailbox, please see the full
mailbox specification.

5.7.4 Thermal Device IRQ and Lock Configuration

(P_CR_THERMAL_DEVICE_IRQ_0_0_0_MCHBAR)—Offset
700Ch
IRQ vector number for thermal/power device that is sent to the IOAPIC and Lock field
for INTR_LAT_0_0_1_PCI.INTRPIN

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LOCK

RESERVED

IRQ

Bit Default &

Field Name (ID): Description
Range Access

0h LOCK (LOCK): Used to lock P_CR_INTR_LAT_0_0_1_PCI.INTPIN.

31
RW/L BIOS should set this lock bit before passing control to the OS

30:8
0h RESERVED (RESERVED): Reserved
RO

IRQ (IRQ): IRQ vector number for the thermal / power device.
0h
7:0 This field controls the event vector issues to the IOAPIC. It must
RW
be configured by BIOS for INTA support.

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5.7.5 Package Thermal Interrupt Control

(P_CR_PKG_THERM_INTERRUPT_0_0_0_MCHBAR)—
Offset 7010h
This register is used to manage processor thermal interrupts, including management of
filtering on the virtual thermal sensor control signal. These features are designed to
allow software to implement smooth control of thermally significant events for platform
thermal management. THIS REGISTER IS DUPLICATED IN THE PCU IO SPACE,
CHANGES MUST BE MADE IN BOTH PLACES

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD

RSVD

CRITICAL_THERMAL_INT_ENABLE
THRESHOLD2_INT_ENABLE
THRESHOLD1_INT_ENABLE
TIME_WINDOW

THRESHOLD2_TEMP

THRESHOLD1_TEMP

Bit Default &

Field Name (ID): Description
Range Access

0h
31 Reserved.
RO

Time Window (TIME_WINDOW): Virtual Temperature thermal filter RC time

constant. Virtual temperature readings are run through an RC filter before they are
fed into status and interrupt generation. This filtering allows software smooth control
of thermal responses to thermally significant events. The bits of this field describe
parameters for a mathematical equation for time window configuration. This field is
0h split into two sub-fields:
30:24
RW
• x = bits[6:5]
• y = bits[4:0]
Time window equation: time_window =
PACKAGE_POWER_SKU_UNIT.TIME_UNIT * ((1+x/4)^y)

Thermal Threshold 2 Temperature (THRESHOLD2_TEMP):

Thermal interrupt threshold temperature in degrees Celsius.
0h Described in a signed, 2's complement format with the LSB
23:16
RW representing 1'C resolution (S8.7.0). E.g., a reading of 0x28 ==
40'C. This threshold is managed relative to the filtered
temperature.

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 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Thermal Threshold 1 Temperature (THRESHOLD1_TEMP):

Thermal interrupt threshold temperature in degrees Celsius.
0h Described in a signed, 2's complement format with the LSB
15:8
RW representing 1'C resolution (S8.7.0). E.g., a reading of 0x28 ==
40'C. This threshold is managed relative to the filtered
temperature.
0h
7:3 Reserved.
RO

Critical Thermal Event Interrupt Enable

(CRITICAL_THERMAL_INT_ENABLE): Enable thermal
0h interrupt generation when the processor has detected a critical
2
RW thermal event that requires immediate servicing. This event is
intended to be an alert indicating thermal control failure and is an
early warning of thermal runaway.
THRESHOLD2_INT_ENABLE (THRESHOLD2_INT_ENABLE):
When set, enables the generation of a thermal interrupt whenever
0h the Thermal Threshold 2 Temperature is crossed. Interrupts are
1
RW generated when the threshold is crossed in either direction.
Interrupt destination is programmed in the TMBAR configuration
space.
Threshold 1 Interrupt Enable
(THRESHOLD1_INT_ENABLE): When set, enables the
0h generation of a thermal interrupt whenever the Thermal Threshold
0
RW 1 Temperature is crossed. Interrupts are generated when the
threshold is crossed in either direction. Interrupt destination is
programmed in the TMBAR configuration space.

5.7.6 ISPDRIVER_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0
_0_MCHBAR
(P_CR_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_
0_MCHBAR)—Offset 7014h
PUNIT_MMIO: Image Processing System Frequency Capabilities
This register describes the frequency capabilities of the image processing system. Units
are 25MHz multiplied by the ratio.
Minimum and maximum ratio fields are initialized by pCode at reset. Last resolved ratio
is updated upon changes to the processing system frequency. The efficient ratio is
determined by firmware and may be updated dynamically depending on firmware
support.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LAST_RESOLVED_RATIO

MAX_RATIO

MIN_RATIO
EFFICIENT_RATIO
Bit Default &
Field Name (ID): Description
Range Access

LAST_RESOLVED_RATIO (LAST_RESOLVED_RATIO): Last

0h resolved ratio for the image processing system. Units are 25MHz
31:24
RO/V multiplied by the ratio. This value is updated dynamically
whenever the processing system frequency changes.
0h MAX_RATIO (MAX_RATIO): Maximum ratio for the image
23:16
RO/V processing system. Units are 25MHz multiplied by the ratio.
EFFICIENT_RATIO (EFFICIENT_RATIO): Firmware-calculated
0h
15:8 efficient ratio for the image processing system. Units are 25MHz
RO/V
multiplied by the ratio.
0h MIN_RATIO (MIN_RATIO): Minimum ratio for the image
7:0
RO/V processing system. Units are 25MHz multiplied by the ratio.

5.7.7 Package Thermal Status

(P_CR_PKG_THERM_STATUS_0_0_0_MCHBAR)—Offset
701Ch
This register is used to monitor the status of the package level virtual thermal sensor
and details on the source of package level thermal events. The package level virtual
thermal sensor is a filtered version of the mximum temperature observed at any
domain within the package. That temperture is applied to the Package Thermal
Interrupt configuration for event delivery to software for run-time thermal
management. When an event is observed, this register describe the source(s) of that
event.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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CRITICAL_THERMAL_EVENT_STATUS
TEMPERATURE

THRESHOLD2_LOG
THRESHOLD2_STATUS
THRESHOLD1_LOG
THRESHOLD1_STATUS
CRITICAL_THERMAL_EVENT_LOG
RSVD

RSVD
Bit Default &
Field Name (ID): Description
Range Access

0h
31:24 Reserved.
RO

Temperature (TEMPERATURE): Virtual maximum SOC

temperature in degrees Celsius. Caculated as a maximum of all
0h on-die thermal sensor readings and filtered accoring to the time
23:16
RO/V constant described in the PKG_THERM_INTERRUPT register. Data
format is signed, 2's complement with the LSB representing 1'C
resolution (S8.7.0).
0h
15:6 Reserved.
RO

Critical Thermal Event Log

(CRITICAL_THERMAL_EVENT_LOG): Sticky log bit indicating
0h
5 that the processor has operated out of its thermal specification
RW/0C/V
since the last time software cleared this bit. Set by hardware on a
0 to 1 transition of Critical Thermal Event Status.
Critical Thermal Event Status
(CRITICAL_THERMAL_EVENT_STATUS): Status bit indicating
0h
4 that the processor is operating outside of its thermal specification.
RO/V
It is intended as an early warning of thermal runaway in the silicon
and shutdown is recommended.
Thermal Threshold 2 Log (THRESHOLD2_LOG): Sticky log bit
0h that indicates temperature has crossed the software
3
RW/0C/V programmable thermal threshold2 in either falling or rising
directions.
Thermal Threshold 2 Status (THRESHOLD2_STATUS):
0h Indicates that the current filtered temperature (bits 23:16 of this
2
RO/V register) is greater than or equal to the Threshold2 defined in the
PKG_THERM_INTERRUPT configuration register.
Thermal Threshold 1 Log (THRESHOLD1_LOG): Sticky log bit
0h that indicates temperature has crossed the software
1
RW/0C/V programmable thermal threshold1 in either falling or rising
directions.

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Bit Default &

Field Name (ID): Description
Range Access

Thermal Threshold 1 Status (THRESHOLD1_STATUS):

0h Indicates that the current filtered temperature (bits 23:16 of this
0
RO/V register) is greater than or equal to the Threshold1 defined in the
PKG_THERM_INTERRUPT configuration register.

5.7.8 LPDDR DRAM Thermal (MR4) Status of Channel 01

(P_CR_MEM_MR4_TEMPERATURE_DEV1_0_0_0_MCHBAR
)—Offset 7024h
LPDDR DRAM Thermal (MR4) Status of Channel 01, when there are multiple DRAMs in a
rank, the maximun MR4 is reported

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR4_RANK_1

MR4_RANK_0
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

31:6
0h RESERVED_0 (RESERVED_0): Reserved
RO

MR4 DRAM thermal status of Channel 01 Rank 1

0h (MR4_RANK_1): This field is updated each read of LPDDR DRAM
5:3
RW MR4 Device Temperature Status per rank. Update rate is
configured by BIOS.
MR4 DRAM thermal status of Channel 01 Rank 0
0h (MR4_RANK_0): This field is updated each read of LPDDR DRAM
2:0
RW MR4 Device Temperature Status per rank. Update rate is
configured by BIOS.

5.7.9 LPDDR DRAM Thermal (MR4) Status of Channel 10

(P_CR_MEM_MR4_TEMPERATURE_DEV2_0_0_0_MCHBAR
)—Offset 7028h
LPDDR DRAM Thermal (MR4) Status of Channel 10, when there are multiple DRAMs in a
rank, the maximun MR4 is reported

Access Method

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Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR4_RANK_1

MR4_RANK_0
RESERVED_0
Bit Default &
Field Name (ID): Description
Range Access

31:6
0h RESERVED_0 (RESERVED_0): Reserved
RO

MR4 DRAM thermal status of Channel 10 Rank 1

0h (MR4_RANK_1): This field is updated each read of LPDDR DRAM
5:3
RW MR4 Device Temperature Status per rank. Update rate is
configured by BIOS.
MR4 DRAM thermal status of Channel 10 Rank 0
0h (MR4_RANK_0): This field is updated each read of LPDDR DRAM
2:0
RW MR4 Device Temperature Status per rank. Update rate is
configured by BIOS.

5.7.10 Machine Check Error Source Log

(P_CR_MCA_ERROR_SRC_0_0_0_MCHBAR)—Offset 702Ch
This register logs error source information i.e IERR or MCERR information for Pcode.
The error fields are cleared by HW or BIOS. This register is also shadowed in the I/O
space.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CATERR
IERR
MCERR

RSVD

RESERVED

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Bit Default &

Field Name (ID): Description
Range Access

0h CATERR (CATERR): Asserted by HW on IERR or MCERR

31
RW/V assertion.

30
0h IERR (IERR): Asserted by HW on IERR assertion.
RW/V

29
0h MCERR (MCERR): Asserted by HW on MCERR assertion.
RW/V

0h
28:8 Reserved.
RO

7:0
0h RESERVED (RESERVED): Undefined - reserved for future use.
RW

5.7.11 DDR Thermal Throttling Control

(P_CR_DDR_THERM_THRT_CTRL_0_0_0_MCHBAR)—
Offset 7030h
This register is used to configure thermal throttling policies for memory.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FM_THERM_THRT_ENABLE
MEM_THRT_CFG
THROTTLE_LEVEL
RESERVED_1

DDR3L_REFRESH_RATE
THROTTLE_LEVEL_ENABLE

RESERVED_0

MEM_THRT_ENABLE

NM_THERM_THRT_ENABLE

FM_THERM_THRT_THRESHOLD
NM_THERM_THRT_THRESHOLD

Bit Default &

Field Name (ID): Description
Range Access

31:26
0h RESERVED_1 (RESERVED_1): RESERVED
RO

0h DDR3L Refresh Rate (DDR3L_REFRESH_RATE): This field is

25
RW/V to allow platform software to request refresh rate for DDR3L
DDR3L Throttle Enable (THROTTLE_LEVEL_ENABLE): When
0h set and DRAM_Type is DDR3L, SOC throttles memory traffic to
24
RW/V level specified in THRT_LVL NOTE: This field is ignored if
DRAM_Type is not DDR3L

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 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

DDR3L Throttle Level (THROTTLE_LEVEL): Throttle level in

0h %BW, in units of 1%. Default = 0%. Input of 100 or higher is
23:16
RW/V clipped to 100%, NOTE: this field is ignored if DRAM_type is not
DDR3L

15:10
0h RESERVED_0 (RESERVED_0): RESERVED
RO

Memory Thermal Throttle Enable (MEM_THRT_ENABLE):

When set, memory traffic is throttled if memory MR4 value >=
0h
9 THERM_THRT_THRESHOLD, respectively. Thermal throttling is
RW/V
achieved by applying memory bandwidth clips in the memory
subsystem.
Memory Thermal Throttling Configuration (MEM_THRT_CFG): Configure
memory throttling behavior. Policies are defined as follows:

• 0 = Thermal throttling policy uses instanous MR4 status for

0h THERM_THRT_THRESHOLD
8
RW/V
• 1 = Thermal throttling policy uses time filtered MR4 status for
THERM_THRT_THRESHOLD. Filtering time constant is
configured in the DDR_THERM_INTERRUPT register.

7
0h Reserved (NM_THERM_THRT_ENABLE): Reserved
RW/V

6:4
0h Reserved (NM_THERM_THRT_THRESHOLD): Reserved
RW/V

LPDDR Memory Thermal Throttling Enable

(FM_THERM_THRT_ENABLE): When set, throttling is activated
0h if LPDDR memory MR4 value is greater than or equal to
3
RW/V THERM_THRT_THRESHOLD. For the standard LPDDR DRAM that is
only capable up to Tcasemax of 85C this bit should be set to
enable LPDDR throttling to keep DRAM within its Tcasemax spec.
LPDDR Memory Thermal Throttling Threshold
(FM_THERM_THRT_THRESHOLD): Configurable threshold of LPDDR memory MR4
value greater than or equal to which thermal throttling is activated. For the standard
0h LPDDR DRAM that is only capable up to Tcasemax of 85C this field should be
2:0 configured to avoid DRAM to exceed its Tcasemax spec.
RW/V
• Memory MR4 >= Threshold = Enable thermal throttling
• Memory MR4 < Threshold = Disable thermal throttling

5.7.12 DDR Thermal Interrupt Control

(P_CR_DDR_THERM_INTERRUPT_0_0_0_MCHBAR)—
Offset 7034h
This register is used to manage DDR thermal interrupts, including management of
filtering on the virtual DRAM thermal sensor control signal. These features are designed
to allow software to implement smooth control of thermally significant events for
platform thermal management.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

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Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FAR_MEM_MR4_THRESHOLD2

FAR_MEM_MR4_THRESHOLD1
TIME_WINDOW

NEAR_MEM_MR4_THRESHOLD2

NEAR_MEM_MR4_THRESHOLD1
RSVD

RSVD

NEAR_MEM_MR4_THRESHOLD2_INT_ENABLE

NEAR_MEM_MR4_THRESHOLD1_INT_ENABLE

FAR_MEM_MR4_THRESHOLD2_INT_ENABLE

FAR_MEM_MR4_THRESHOLD1_INT_ENABLE
Bit Default &
Field Name (ID): Description
Range Access

0h
31 Reserved.
RO

Time Window (TIME_WINDOW): Virtual Temperature thermal filter RC time

constant. Virtual temperature readings are run through an RC filter before they are
fed into status and interrupt generation. This filtering allows software smooth control
of thermal responses to thermally significant events. The bits of this field describe
parameters for a mathematical equation for time window configuration. This field is
0h split into two sub-fields:
30:24
RW
• x = bits[6:5]
• y = bits[4:0]
Time window equation: time_window =
PACKAGE_POWER_SKU_UNIT.TIME_UNIT * ((1+x/4)^y)

0h
23:16 Reserved.
RO

0h Reserved (NEAR_MEM_MR4_THRESHOLD2_INT_ENABLE):
15
RW Reserved

14:12
0h Reserved (NEAR_MEM_MR4_THRESHOLD2): Reserved
RW

0h Reserved (NEAR_MEM_MR4_THRESHOLD1_INT_ENABLE):
11
RW Reserved

10:8
0h Reserved (NEAR_MEM_MR4_THRESHOLD1): Reserved
RW

Memory MR4 Threshold 2 Interrupt Enable

(FAR_MEM_MR4_THRESHOLD2_INT_ENABLE): Enable
0h thermal interrupt generation whenever the virtual maximum
7
RW memory MR4 has crossed THRESHOLD2. Interrupts are triggered
when the filtered MR4 temperature crosses in both rising and
falling directions.

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Bit Default &

Field Name (ID): Description
Range Access

Memory MR4 Threshold 2 (FAR_MEM_MR4_THRESHOLD2):

0h
6:4 Configurable memory threshold2 value for memory thermal
RW
interrupt generation
Memory MR4 Threshold 1 Interrupt Enable
(FAR_MEM_MR4_THRESHOLD1_INT_ENABLE): Enable
0h thermal interrupt generation whenever the virtual maximum
3
RW memory MR4 has crossed THRESHOLD1. Interrupts are triggered
when the filtered MR4 temperature crosses in both rising and
falling directions.
Memory MR4 Threshold 1 (FAR_MEM_MR4_THRESHOLD1):
0h
2:0 Configurable memory threshold1 value for memory thermal
RW
interrupt generation

5.7.13 DDR Thermal Status

(P_CR_DDR_THERM_STATUS_0_0_0_MCHBAR)—Offset
7038h
Status register for monitoring DDR thermal status. Data reported here is aggregated by
memory type, and values reported represent the maximum MR4 readings observed in
those respective domains. Temperatures are additionally filtered by the MR4 thermal
filtering time constant described in the DDR Thermal Interrupt configuration register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FAR_MEM_MR4_THRESHOLD2_LOG

FAR_MEM_MR4_THRESHOLD1_LOG
NEAR_MEM_MR4_THRESHOLD2_LOG

NEAR_MEM_MR4_THRESHOLD1_LOG
NEAR_MEM_MR4

FAR_MEM_MR4
RSVD

RSVD

FAR_MEM_MR4_THRESHOLD2_STATUS

FAR_MEM_MR4_THRESHOLD1_STATUS
NEAR_MEM_MR4_THRESHOLD2_STATUS

NEAR_MEM_MR4_THRESHOLD1_STATUS

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Bit Default &

Field Name (ID): Description
Range Access

0h
31:22 Reserved.
RO

21:19
0h Reserved (NEAR_MEM_MR4): Reserved
RO/V

LPDDR Memory MR4 (FAR_MEM_MR4): Virtual maximum

0h memory MR4 reading. Caculated as a maximum of all LPDDR
18:16
RO/V memory MR4 readingsand filtered accoring to the time constant
described in DDR_THERM_INTERRUPT register.
0h
15:8 Reserved.
RO

7
0h Reserved (NEAR_MEM_MR4_THRESHOLD2_LOG): Reserved
RW/0C/V

0h Reserved (NEAR_MEM_MR4_THRESHOLD2_STATUS):
6
RO/V Reserved

5
0h Reserved (NEAR_MEM_MR4_THRESHOLD1_LOG): Reserved
RW/0C/V

0h Reserved (NEAR_MEM_MR4_THRESHOLD1_STATUS):
4
RO/V Reserved
Memory MR4 Threshold2 Log
(FAR_MEM_MR4_THRESHOLD2_LOG): Indicates that the
0h virtual maximum memory MR4 has crossed THRESHOLD2 since
3
RW/0C/V the last time this register was cleared. The bit is set when the
threshold is crossed in either direction. Software may clear this
bit.
Memory MR4 Threshold2 Status
(FAR_MEM_MR4_THRESHOLD2_STATUS): Status bit is set
0h
2 when the virtual maximum memory MR4 reading is greater than
RO/V
or equal to THRESHOLD2. It is cleared when temperature is less
than THRESHOLD2
Memory MR4 Threshold1 Log
(FAR_MEM_MR4_THRESHOLD1_LOG): Indicates that the
0h virtual maximum memory MR4 has crossed THRESHOLD1 since
1
RW/0C/V the last time this register was cleared. The bit is set when the
threshold is crossed in either direction. Software may clear this
bit.
Memory MR4 Threshold1 Status
(FAR_MEM_MR4_THRESHOLD1_STATUS): Status bit is set
0h
0 when the virtual maximum memory MR4 reading is greater than
RO/V
or equal to THRESHOLD1. It is cleared when temperature is less
than THRESHOLD1

5.7.14 Dram Energy Counter

(P_CR_DDR_ENERGY_STATUS_0_0_0_MCHBAR)—Offset
7048h
Reports total energy consumed in DRAM. The energy status is reported in units which
are defined by PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT. The counter will
wrap around and continue counting from zero when it reaches its limit and therefore

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should be polled sufficiently frequently to avoid aliasing. Typically, software will

calculate delta energy and delta time and divide the two to estimate Watts consumed
over a time window. The value of this register is updated at approximately every 1ms.
This energy status is what is used by DDR RAPL or OLTM control algorithms if the
product supports those features.
To calculate Watts: Watts = delta(energy) / delta(time) /
2^PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT THIS REGISTER IS
DUPLICATED IN THE PCU IO SPACE, CHANGES MUST BE MADE IN BOTH PLACES

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JOULES

Bit Default &

Field Name (ID): Description
Range Access

JOULES (JOULES): Total Joules of energy consumed by all

0h
31:0 DIMMs. Units are proportional to Joules and are defined by
RO/V
PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT.

5.7.15 DDR RAPL Performance Status

(P_CR_DDR_RAPL_PERF_STATUS_0_0_0_MCHBAR)—
Offset 704Ch
Memory RAPL performance throttling counter. This counter accumulates time that any
channel in the memory controller is bandwidth throttled due to memory RAPL
constraints. This counter counts total time (in
PACKAGE_POWER_SKU_UNIT_MSR.TIME_UNIT units) that any channel is throttled. If
two channels are throttled, this counter increments at a 2x rate, so that for 1ms in wall
clock time the counter counts 2ms. This counter does not include throttling as a result
of thermal management or MEMHOT. This register is updated at approximately 1ms
intervals. This counter is normalized to 'seconds' and is not subject to variation of
actual DRAM clock speeds. This register is readonly for software via MMIO MSR and
PECI/PCS. This register starts counting at zero from reset and continues counting
forever and wraparounds may occur, so software should ensure the sample rate is
sufficient to avoid aliasing. This is an unsigned value.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 58F0h

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3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 0 0 0

DURATION
Bit Default &
Field Name (ID): Description
Range Access

DDR Bandwidth Throttle Duration (DURATION): Bandwidth

throttle duration counter due to Memory RAPL. Sum across all
58F0h
31:0 channels in PACKAGE_POWER_SKU_UNIT_MSR.TIME_UNIT units.
RW
This data can serve as a proxy for the potential performance
impacts of RAPL on memory accesses.

5.7.16 Package RAPL Performance Status

(P_CR_PACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR)
—Offset 7050h
Counts time that any core in the IA domain is performance throttled below OS request
and below the base frequency (P1) because of power limits (PL1 or PL2). Counts in
time units defined by PACKAGE_POWER_SKU_UNIT_MSR.TIME_UNIT. If software uses
the TURBO_ACTIVATION_RATIO or PECI ACPI P-NOTIFY, the turbo activation ratios
described by those features will may elevate the effective OS request (as calculated by
this counter) to max turbo. This register starts counting at zero from reset and
continues counting forever and wraparounds may occur, so software should ensure the
sample rate is sufficient to avoid aliasing. This is an unsigned value.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
COUNTS

Bit Default &

Field Name (ID): Description
Range Access

Performance Throttle Duration (COUNTS): Time that any core

in the IA domain is performance throttled below OS request and
0h
31:0 below the base frequency (P1) because of power limits (PL1 or
RW
PL2). Counts in time units defined by
PACKAGE_POWER_SKU_UNIT_MSR.TIME_UNIT

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5.7.17 IA Core Performance / Power Priority Control

(P_CR_PRIMARY_PLANE_TURBO_PLCY_0_0_0_MCHBAR)
—Offset 7054h
The PRIMARY_PLANE_TURBO_POWER_POLICY and
SECONDARY_PLANE_TURBO_POWER_POLICY are used together as hints to balance the
power budget between the primary (IA core) and secondary (Graphics) power planes.
This biasing is effectively a performance biasing, and it helps Punit firmware assess
where software needs performance the most

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PRIPTP
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

31:5
0h RESERVED_0 (RESERVED_0): Reserved
RO

IA Core Priority Level (PRIPTP): Performance priority Level for

0h
4:0 the IA Core (primary) power plane. A higher number implies a
RW
higher priority.

5.7.18 Graphics Performance / Power Priority Control

(P_CR_SECONDARY_PLANE_TURBO_PLCY_0_0_0_MCHBA
R)—Offset 7058h
The PRIMARY_PLANE_TURBO_POWER_POLICY and
SECONDARY_PLANE_TURBO_POWER_POLICY are used together as hints to balance the
power budget between the primary (IA core) and secondary (Graphics) power planes.
This biasing is effectively a performance biasing, and it helps Punit firmware assess
where software needs performance the most

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10h

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3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

SECPTP
RESERVED_0
Bit Default &
Field Name (ID): Description
Range Access

31:5
0h RESERVED_0 (RESERVED_0): Reserved
RO

Graphics Priority Level (SECPTP): Performance priority Level

10h
4:0 for the Graphics (secondary) power plane. A higher number
RW
implies a higher priority.

5.7.19 IA Energy Counter

(P_CR_PRIMARY_PLANE_ENERGY_STATUS_0_0_0_MCHB
AR)—Offset 705Ch
Reports total energy consumed across all IA cores. The energy status is reported in
units which are defined by PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT. The
counter will wrap around and continue counting from zero when it reaches its limit and
therefore should be polled sufficiently frequently to avoid aliasing. Typically, software
will calculate delta energy and delta time and divide the two to estimate Watts
consumed over a time window. The value of this register is updated at approximately
every 1ms.
To calculate Watts: Watts = delta(energy) / delta(time) /
2^PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT THIS REGISTER IS
DUPLICATED IN THE PCU IO SPACE, CHANGES MUST BE MADE IN BOTH PLACES

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA

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Bit Default &

Field Name (ID): Description
Range Access

IA Energy Counter (DATA): Contains an accumulated value of

the energy consumed in the primary power plane. To find the
energy consumed in a given time window, sofwtare should
0h
31:0 subtract the two energy readings. Software will have to take care
RO/V
of counter wrapping around when it overflows.
Units are proportional to Joules exact precsion is defined by
PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT

5.7.20 Graphics Energy Counter

(P_CR_SECONDARY_PLANE_ENERGY_STATUS_0_0_0_MC
HBAR)—Offset 7060h
Reports total energy consumed across all IA cores. The energy status is reported in
units which are defined by PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT. The
counter will wrap around and continue counting from zero when it reaches its limit and
therefore should be polled sufficiently frequently to avoid aliasing. Typically, software
will calculate delta energy and delta time and divide the two to estimate Watts
consumed over a time window. The value of this register is updated at approximately
every 1ms.
To calculate Watts: Watts = delta(energy) / delta(time) /
2^PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT THIS REGISTER IS
DUPLICATED IN THE PCU IO SPACE, CHANGES MUST BE MADE IN BOTH PLACES

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA

Bit Default &

Field Name (ID): Description
Range Access

Graphics Energy Counter (DATA): Contains an accumulated

value of the energy consumed in the secondary power plane. To
find the energy consumed in a given time window, sofwtare
0h
31:0 should subtract the two energy readings. Software will have to
RO/V
take care of counter wrapping around when it overflows.
Units are proportional to Joules exact precsion is defined by
PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT

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5.7.21 PACKAGE_POWER_SKU_UNIT
(P_CR_PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR)—
Offset 7068h
Defines units for calculating SKU power, current, energy, resistance and timing
parameters.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 330A0E08h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0

ENERGY_UNIT
RESISTANCE_UNIT

TIME_UNIT
CURRENT_UNIT

PWR_UNIT
RESERVED_2

RESERVED_1

RESERVED_0
Bit Default &
Field Name (ID): Description
Range Access

RESISTANCE_UNIT (RESISTANCE_UNIT): Used to define the

units of resistance for control registers that describe parameters
3h
31:28 in ohms such as VR_CURRENT_CONFIG. The actual unit value is
RW
calculated by 1mohm / 2^RESISTANCE_UNIT. The default value of
3 corresponds to 0.125mohm.
CURRENT_UNIT (CURRENT_UNIT): Used to define the units of
3h amps in control registers such as VR_CURRENT_CONFIG. The
27:24
RW actual unit value is calculated by 1A / 2^CURRENT_UNIT. The
default value of 3 corresponds to 0.125A.

23:20
0h RESERVED_2 (RESERVED_2): Reserved
RSV

TIME_UNIT (TIME_UNIT): Used for to define the time units in

Ah registers such as PL1, PL2, PL3 and PL4. The actual unit value is
19:16
RW calculated by 1s / 2^TIME_UNIT. The default value of 10
corresponds to 0.977ms.

15:13
0h RESERVED_1 (RESERVED_1): Reserved
RSV

ENERGY_UNIT (ENERGY_UNIT): Used to define the units of

Eh energy reporting registers such as PACKAGE_ENERGY_STATUS.
12:8
RW The actual unit value is calculated by 1 J / 2^ENERGY_UNIT. The
default value of 14 corresponds to ~61uJ per bit.

7:4
0h RESERVED_0 (RESERVED_0): Reserved
RSV

334818 295
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Bit Default &

Field Name (ID): Description
Range Access

PWR_UNIT (PWR_UNIT): Used to define the units of power

8h control registers such as PL1, PL2, PL3 and PL4. The actual unit
3:0
RW value is calculated by 1 W / 2^PWR_UNIT. The default value of 8
corresponds to 3.9mW per bit.

5.7.22 SOC Energy Counter

(P_CR_PACKAGE_ENERGY_STATUS_0_0_0_MCHBAR)—
Offset 706Ch
Reports total energy consumed across the entire SOC / Package. The energy status is
reported in units which are defined by
PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT. The counter will wrap around and
continue counting from zero when it reaches its limit and therefore should be polled
sufficiently frequently to avoid aliasing. Typically, software will calculate delta energy
and delta time and divide the two to estimate Watts consumed over a time window. The
value of this register is updated at approximately every 1ms. This energy status is what
is used by RAPL PL1, PL2 and PL3 control algorithms.
To calculate Watts: Watts = delta(energy) / delta(time) /
2^PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT THIS REGISTER IS
DUPLICATED IN THE PCU IO SPACE, CHANGES MUST BE MADE IN BOTH PLACES

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA

Bit Default &

Field Name (ID): Description
Range Access

SOC Energy Counter (DATA): Contains accumulated energy

consumed by the entire CPU. This counter will wrap around and
0h
31:0 keep counting when the counter overflows.
RO/V
Units are proportional to Joules exact precsion is defined by
PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT

5.7.23 GT_PERF_STATUS
(P_CR_GT_PERF_STATUS_0_0_0_MCHBAR)—Offset
7070h
Contains the voltage and ratio status for GT. This register is mapped to
GT_PERF_STATUS_0_0_0_MCHBAR.

296 334818
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Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RP_STATE_RATIO_SLICE

RP_STATE_RATIO_UNSLICE

RP_STATE_VOLTAGE
RSVD

Bit Default &

Field Name (ID): Description
Range Access

0h
31:26 Reserved.
RO

RP_STATE_RATIO_SLICE (RP_STATE_RATIO_SLICE): Ratio

0h of the current RP-state, in 16.6Mhz 1xclks. When the graphics
25:17
RO/V engine is in RC6, this field is zeroed out.

RP_STATE_RATIO_UNSLICE (RP_STATE_RATIO_UNSLICE):
0h Ratio of the current RP-state, in 16.6Mhz 1xclks. When the
16:8
RO/V graphics engine is in RC6, this field is zeroed out.

0h RP_STATE_VOLTAGE (RP_STATE_VOLTAGE): RP-State

7:0
RO/V Voltage GT Target Voltage in U1.7 Volts

5.7.24 Temperature Reference and Control

(P_CR_TEMPERATURE_TARGET_0_0_0_MCHBAR)—Offset
7074h
This register contains information about the fan speed control target temperature as
well as details on the reference temperature for IA core DTS relative temperature
reading. MSR_Name: TEMPERATURE_TARGET MSR_Addr: 0x1A2

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 5A0000h

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3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TJ_MAX_TCC_OFFSET

REF_TEMP

FAN_TEMP_TARGET_OFFSET
RESERVED_1

RESERVED_0
Bit Default &
Field Name (ID): Description
Range Access

31
0h RESERVED_1 (RESERVED_1): Reserved
RSV

Thermal Monitor Activation Offset Control

(TJ_MAX_TCC_OFFSET): This field allows platform software to
configure the temperature at which thermal monitor engages to
0h be lower than the manufacturing configured maximum constraint.
30:24
RW This field is programmed in 1'C units. E.g., if the default silicon
configured maximum temperature is 100'C and this field is
configured to 10, then the silicon will engage thermal throttling
algorithms at 90'C
Reference Temperature (REF_TEMP): Tjmax a.k.a. Thermal
Monitor activation temperature or Prochot Temperature. This is
the maximum junction temperature at which thermal throttling
aka thermal monitor is activated. This temperature is the
5Ah
23:16 maximum temperature at which the silicon is capable of operating
RO/V
at. All IA core digital thermal sensor readings are reported as a
relative nagative offset from this reference temperature, such that
a readon of zero implies the cores are running at this
temperature.
Fan Temperature Target Offset
0h (FAN_TEMP_TARGET_OFFSET): Fan Temperature Target Offset
15:8
RO/V a.k.a. TControl indicates the relative offset from the the Thermal
Monitor Trip Temperature at which fans should be engaged.

7:0
0h RESERVED_0 (RESERVED_0): Reserved
RSV

5.7.25 BIOS Reset Completion

(P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)—Offset 7078h
This register is used as a means for BIOS to communicate staging to the Punit / Pcode.
The exact definition and utility of each bit may differ across products. The general
philosophy is that when BIOS is done with stage0, it writes the RST_CPL0 bit and then
waits for the PCODE_INIT_DONE0 bit to be set before proceeding to the next step.

Access Method

298 334818
MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESERVED0

PCODE_INIT_DONE7
PCODE_INIT_DONE6
PCODE_INIT_DONE5
PCODE_INIT_DONE4
PCODE_INIT_DONE3
PCODE_INIT_DONE2
PCODE_INIT_DONE1
PCODE_INIT_DONE
RST_CPL7
RST_CPL6
RST_CPL5
RST_CPL4
RST_CPL3
RST_CPL2
RST_CPL1
RST_CPL
Bit Default &
Field Name (ID): Description
Range Access

31:16
0h RESERVED0 (RESERVED0): reserved
RW

Stage7 Pcode Reset Complete (PCODE_INIT_DONE7):

Pcode sets this bit when it has completed this stage, BIOS must
0h
15 wait for this bit to be set before proceeding to the next stage.
RO/V
Stage validity is product-specific and this stage may not be
applicable to this product.
Stage6 Pcode Reset Complete (PCODE_INIT_DONE6):
Pcode sets this bit when it has completed this stage, BIOS must
0h
14 wait for this bit to be set before proceeding to the next stage.
RO/V
Stage validity is product-specific and this stage may not be
applicable to this product.
Stage5 Pcode Reset Complete (PCODE_INIT_DONE5):
Pcode sets this bit when it has completed this stage, BIOS must
0h
13 wait for this bit to be set before proceeding to the next stage.
RO/V
Stage validity is product-specific and this stage may not be
applicable to this product.
Stage4 Pcode Reset Complete (PCODE_INIT_DONE4):
Pcode sets this bit when it has completed this stage, BIOS must
0h
12 wait for this bit to be set before proceeding to the next stage.
RO/V
Stage validity is product-specific and this stage may not be
applicable to this product.
Stage3 Pcode Reset Complete (PCODE_INIT_DONE3):
Pcode sets this bit when it has completed this stage, BIOS must
0h
11 wait for this bit to be set before proceeding to the next stage.
RO/V
Stage validity is product-specific and this stage may not be
applicable to this product.
Stage2 Pcode Reset Complete (PCODE_INIT_DONE2):
Pcode sets this bit when it has completed this stage, BIOS must
0h
10 wait for this bit to be set before proceeding to the next stage.
RO/V
Stage validity is product-specific and this stage may not be
applicable to this product.

334818 299
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Stage1 Pcode Reset Complete (PCODE_INIT_DONE1):

Pcode sets this bit when it has completed this stage, BIOS must
0h
9 wait for this bit to be set before proceeding to the next stage.
RO/V
Stage validity is product-specific and this stage may not be
applicable to this product.
Stage0 Pcode Reset Complete (PCODE_INIT_DONE): Pcode
has completed its actions in response to Stage0 BIOS Reset
0h complete. Between BIOS Stage0 complete and pcode Stage0
8
RO/V complete, pcode will apply all power savings configurations to PCS
and will set up C_STATE_LATENCY control MSR settings for IRTL
management.

7
0h Stage7 BIOS Reset Complete (RST_CPL7): reset complete
RW

Stage6 BIOS Reset Complete (RST_CPL6): BIOS sets this bit

when it has completed this stage, Pcode must wait for this bit to
0h
6 be set before proceeding to the next stage. Stage validity is
RW
product-specific and this stage may not be applicable to this
product.
Stage5 BIOS Reset Complete (RST_CPL5): BIOS sets this bit
when it has completed this stage, Pcode must wait for this bit to
0h
5 be set before proceeding to the next stage. Stage validity is
RW
product-specific and this stage may not be applicable to this
product.
Stage4 BIOS Reset Complete (RST_CPL4): BIOS sets this bit
when it has completed this stage, Pcode must wait for this bit to
0h
4 be set before proceeding to the next stage. Stage validity is
RW
product-specific and this stage may not be applicable to this
product.
Stage3 BIOS Reset Complete (RST_CPL3): BIOS sets this bit
when it has completed this stage, Pcode must wait for this bit to
0h
3 be set before proceeding to the next stage. Stage validity is
RW
product-specific and this stage may not be applicable to this
product.
Stage2 BIOS Reset Complete (RST_CPL2): BIOS sets this bit
when it has completed this stage, Pcode must wait for this bit to
0h
2 be set before proceeding to the next stage. Stage validity is
RW
product-specific and this stage may not be applicable to this
product.
Stage1 BIOS Reset Complete (RST_CPL1): BIOS sets this bit
when it has completed this stage, Pcode must wait for this bit to
0h
1 be set before proceeding to the next stage. Stage validity is
RW
product-specific and this stage may not be applicable to this
product.

300 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Stage0 BIOS Reset Complete (RST_CPL): Set by BIOS to

indicate that all power management configurations as part of reset
are complete. This must include Punit patch load done as well as
all relevant Punit power management register and mailbox
0h
0 configurations done. Once this bit is set, Punit will allow normal
RW
power management to start. Before setting this bit, P-states and
C-states support is disabled. BIOS should wait before receiving
the Pcode Stage0 reset complete before proceeding with any
further steps.

5.7.26 BIOS_MAILBOX_DATA
(P_CR_BIOS_MAILBOX_DATA_0_0_0_MCHBAR)—Offset
7080h
Data register for the BIOStoPCODE mailbox. This mailbox is implemented as a means
for accessing statistics and implementing BIOS-Pcode handshakes. This register is used
in conjunction with BIOS_MAILBOX_INTERFACE. THIS REGISTER IS DUPLICATED IN
THE PCU IO SPACE, CHANGES MUST BE MADE IN BOTH PLACES

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA

Bit Default &

Field Name (ID): Description
Range Access

0h DATA (DATA): This field contains the data associated with

31:0
RW/V specific commands.

5.7.27 BIOS_MAILBOX_INTERFACE
(P_CR_BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR)—
Offset 7084h
Control and Status register for the BIOStoPCODE mailbox. This mailbox is implemented
as a means for accessing statistics and implementing BIOS-Pcode handshakes. This
register is used in conjunction with BIOS_MAILBOX_DATA. THIS REGISTER IS
DUPLICATED IN THE PCU IO SPACE, CHANGES MUST BE MADE IN BOTH PLACES

Access Method

334818 301
 MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RUN_BUSY

RSVD

ADDRESS

COMMAND
Bit Default &
Field Name (ID): Description
Range Access

RUN_BUSY (RUN_BUSY): SW may write to the two mailbox

registers only when RUN_BUSY is clear(0). Setting RUN_BUSY to
0h 1 will pend a Fast Path event to Pcode. After setting this bit SW
31
RW/1S/V will poll this bit until it is cleared. PCODE will clear RUN_BUSY
after updating the mailbox registers with the result and error
code.
0h
30:29 Reserved.
RO

0h ADDRESS (ADDRESS): This field is used to specify an additional

28:8
RW/V parameter to extend the command when needed.
COMMAND (COMMAND): This field contains the SW request
0h
7:0 command or the PCODE response code depending on the setting
RW/V
of RUN_BUSY.

5.7.28 CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBA
R)—Offset 7088h
PUNIT_MMIO: Core Frequency Capabilities
This register describes the frequency capabilities of the IA cores. Units are 100MHz
multiplied by the ratio.
Minimum and maximum ratio fields are initialized by pCode at reset. Last resolved ratio
is updated upon changes to the processing system frequency. The efficient ratio is
determined by firmware and may be updated dynamically depending on firmware
support.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

302 334818
MCHBAR

LAST_RESOLVED_FREQ

EFFICIENT_FREQ
MAX_SUPPORTED_FREQ

MIN_SUPPORTED_FREQ
Bit Default &
Field Name (ID): Description
Range Access

LAST_RESOLVED_FREQ (LAST_RESOLVED_FREQ): Last

0h resolved ratio for the IA cores. Units are 100MHz multiplied by the
31:24
RO/V ratio. This value is updated dynamically whenever the IA core
frequency changes.
MAX_SUPPORTED_FREQ (MAX_SUPPORTED_FREQ):
0h
23:16 Maximum ratio for the IA cores. Units are 100MHz multiplied by
RO/V
the ratio.
EFFICIENT_FREQ (EFFICIENT_FREQ): Firmware-calculated
0h
15:8 efficient ratio for the IA cores. Units are 100MHz multiplied by the
RO/V
ratio.
MIN_SUPPORTED_FREQ (MIN_SUPPORTED_FREQ):
0h
7:0 Minimum supported ratio for the IA cores. Units are 100MHz
RO/V
multiplied by the ratio.

5.7.29 GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR
(P_CR_GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_M
CHBAR)—Offset 708Ch
PUNIT_MMIO: Graphics Engine Frequency Capabilities
This register describes the frequency capabilities of the integrated graphics engine.
Units are 50MHz multiplied by the ratio.
Minimum and maximum ratio fields are initialized by pCode at reset. Last resolved ratio
is updated upon changes to the integrated graphics engine frequency. The efficient
ratio is determined by firmware and may be updated dynamically depending on
firmware support.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

334818 303
 MCHBAR

LAST_RESOLVED_FREQ

EFFICIENT_FREQ
MAX_SUPPORTED_FREQ

MIN_SUPPORTED_FREQ
Bit Default &
Field Name (ID): Description
Range Access

LAST_RESOLVED_FREQ (LAST_RESOLVED_FREQ): Last

0h resolved ratio for the integrated graphics engine. Units are 50MHz
31:24
RO/V multiplied by the ratio. This value is updated dynamically
whenever the graphics engine frequency changes.
MAX_SUPPORTED_FREQ (MAX_SUPPORTED_FREQ):
0h
23:16 Maximum supported ratio for the integrated graphics engine. Units
RO/V
are 50MHz multiplied by the ratio.
EFFICIENT_FREQ (EFFICIENT_FREQ): Firmware-calculated
0h
15:8 efficient ratio for the integrated graphics engine. Units are 50MHz
RO/V
multiplied by the ratio.
MIN_SUPPORTED_FREQ (MIN_SUPPORTED_FREQ):
0h
7:0 Minimum supported ratio for the integrated graphics engine. Units
RO/V
are 50MHz multiplied by the ratio.

5.7.30 SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBA
R
(P_CR_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0
_0_MCHBAR)—Offset 7090h
PUNIT_MMIO: System Agent Frequency Capabilities
This register describes the frequency capabilities of the System Agent. Units are
16.666MHz multiplied by the ratio.
Last resolved ratio is updated upon changes to the System Agent frequency.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

304 334818
MCHBAR

LAST_RESOLVED_RATIO

RESERVED_2

RESERVED_1

RESERVED_0
Bit Default &
Field Name (ID): Description
Range Access

0h LAST_RESOLVED_RATIO (LAST_RESOLVED_RATIO): Last

31:24
RO/V resolved System Agent ratio, in units of 16.666MHz.

23:16
0h RESERVED_2 (RESERVED_2): Reserved
RO/V

15:8
0h RESERVED_1 (RESERVED_1): Reserved
RO/V

7:0
0h RESERVED_0 (RESERVED_0): Reserved
RO/V

5.7.31 Memory Frequency Status

(P_CR_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_0_0
_MCHBAR)—Offset 7094h
This register reports out the LPDDR memory frequency. The actual capabilities of the
SOC with respect to LPDDR frequency is described in the
MEMSS_FREQUENCY_CAPABILITIES register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LAST_RESOLVED_RATIO

RESERVED_2

RESERVED_1

RESERVED_0

334818 305
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Last Resolved Memory Frequency

(LAST_RESOLVED_RATIO): This field reports out the LPDDR
memory frequency in integer multiple of 133.33MHz. This register
0h
31:24 reflects what BIOS has programmed as the default LPDDR
RO/V
frequency in products that do not support run-time memory
frequency control. For products supporting run-time memory
frequency control, this field describes the last resolved frequency.

23:16
0h RESERVED_2 (RESERVED_2): Reserved
RO/V

15:8
0h RESERVED_1 (RESERVED_1): Reserved
RO/V

7:0
0h RESERVED_0 (RESERVED_0): Reserved
RO/V

5.7.32 Package Power SKU and RAPL Power Control Capabilities

(P_CR_PACKAGE_POWER_SKU_0_0_0_MCHBAR)—Offset
70A0h
This register describes the the power SKU of the part and limits on time window and
power limit configuration allowed in the RAPL PL1 and PL2 configuration registers.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 12024000600118h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000010010000000100100000000000000011000000000000100011000
PKG_TDP
PKG_MAX_WIN

PKG_MIN_PWR
PKG_MAX_PWR
RESERVED_3

RESERVED_2

RESERVED_1

RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

63:55
0h RESERVED_3 (RESERVED_3): Reserved
RO

306 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

RAPL Maximum Allowed Time Window (PKG_MAX_WIN): The maximal time

window allowed to be programmed for RAPL PL1 and PL2 controls for the SKU. Higher
values will be clamped to this value. The bits of this field describe parameters for a
mathematical equation for time window configuration. This field is split into two sub-
fields:
12h
54:48
RW • x = bits[6:5]
• y = bits[4:0]
Time window equation: time_window =
PACKAGE_POWER_SKU_UNIT.TIME_UNIT * ((1+x/4)^y)

47
0h RESERVED_2 (RESERVED_2): Reserved
RO

RAPL Maximum Power Limit (PKG_MAX_PWR): The maximal

package power setting allowed for the SKU. Higher values will be
240h clamped to this value. The maximum setting is typical not
46:32
RW guaranteed. The default value for this field is determined by fuses.
The units for this value are defined in
PACKAGE_POWER_SKU_MSR[PWR_UNIT].

31
0h RESERVED_1 (RESERVED_1): Reserved
RO

Package Minimum Power (PKG_MIN_PWR): The minimal

60h
30:16 package power setting allowed for the SKU. Lower values may not
RW
be achievable by run-time RAPL PL1 and PL2 control algorithms.

15
0h RESERVED_0 (RESERVED_0): Reserved
RO

PKG_TDP (PKG_TDP): The TDP package power setting allowed

118h for the SKU. The TDP setting is typical not guaranteed. The default
14:0
RW value for this field is determined by fuses. The units for this value
are defined in PACKAGE_POWER_SKU_MSR[PWR_UNIT].

5.7.33 Package RAPL Power Limit

(P_CR_PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR)—Offset
70A8h
Package RAPL Power Limit allows a software agent to define power limitation for the
package domain. Power limitation is defined in terms of average power usage (Watts)
over a time window specified. Two power limits and associated time windows can be
specified. These power limits are commonly referred to as PL1 (long time window) and
PL2 (short time window). Each power limit provides independent clamping control that
would permit the processor cores to go below OS-requested state to meet the power
limits. A lock mechanism allow the software agent to enforce power limit settings. Once
the lock bit is set, the power limit settings are static and un-modifiable until next
RESET.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

334818 307
 MCHBAR

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000

PKG_CLMP_LIM_2
PKG_PWR_LIM_2_EN

PKG_CLMP_LIM_1
PKG_PWR_LIM_1_EN
PKG_PWR_LIM_2

PKG_PWR_LIM_1
PKG_PWR_LIM_LOCK

PKG_PWR_LIM_2_TIME

PKG_PWR_LIM_1_TIME
RESERVED_1

RESERVED_0
Bit Default &
Field Name (ID): Description
Range Access

Package RAPL Lock (PKG_PWR_LIM_LOCK): When set all

0h settings in this register are locked and are treated as Read Only.
63
RW/L This lock control is persistent until the next reset. This bit will
typically set by BIOS during boot time or resume from Sx.

62:56
0h RESERVED_1 (RESERVED_1): Reserved
RSV

Power Limit 2 (PL2) Time Window (PKG_PWR_LIM_2_TIME): Time window

for Power Limit 1 (PL2). This describes the control window of the power limit. This
time window is described in an RC time constant format, which means that if 1s is
programmed, the power limit constraint really applies at more like 5s. The maximal
time window is bounded by PACKAGE_POWER_SKU_MSR.PKG_MAX_WIN. Thre is no
constraint on the minimum programmable time window, however at very short time
windows the control algorithms may not be effective. The bits of this field describe
0h
55:49 parameters for a mathematical equation for time window configuration. This field is
RW/L split into two sub-fields:

• x = bits[6:5]
• y = bits[4:0]
Time window equation: time_window =
PACKAGE_POWER_SKU_UNIT.TIME_UNIT * ((1+x/4)^y)

Power Limit 2 (PL2) Clamp (PKG_CLMP_LIM_2): Clamp mode control for PL2.

• 0 = PL2 power control is prevented from forcing P-states

below the base frequency / P1 for any domain in the SOC.
0h
48
RW/L
• 1 = PL2 power control will take all actions necessary to meet
the power target, even if that involves running at clock
frequencies below the base frequency / P1 level.
In order to ensure proper SOC cooling, it is generally recommended that the clamp
mode is always enabled.

Power Limit 2 (PL2) Enable (PKG_PWR_LIM_2_EN): Enable

0h
47 for Power Limit 2 (PL2). Setting this bit activates the power limit
RW/L
and time window defined for PL2.
Power Limit 2 (PL2) (PKG_PWR_LIM_2): Sets the average
power usage limit of the package domain corresponding to the PL2
time window. The power units of this field are specified by the
0h PACKAGE_POWER_SKU_UNIT_MSR.PWR_UNIT. This power limit
46:32
RW/L must be configured by software before it will engage. The PL2
limit is most commonly associated with long time windows (1s and
longer), although there are no explicit constraints on what
software configures.

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Bit Default &

Field Name (ID): Description
Range Access

31:24
0h RESERVED_0 (RESERVED_0): Reserved
RSV

Power Limit 1 (PL1) Time Window (PKG_PWR_LIM_1_TIME): Time window

for Power Limit 1 (PL1). This describes the control window of the power limit. This
time window is described in an RC time constant format, which means that if 1s is
programmed, the power limit constraint really applies at more like 5s. The maximal
time window is bounded by PACKAGE_POWER_SKU_MSR.PKG_MAX_WIN. Thre is no
constraint on the minimum programmable time window, however at very short time
0h windows the control algorithms may not be effective. The bits of this field describe
23:17 parameters for a mathematical equation for time window configuration. This field is
RW/L split into two sub-fields:

• x = bits[6:5]
• y = bits[4:0]
Time window equation: time_window =
PACKAGE_POWER_SKU_UNIT.TIME_UNIT * ((1+x/4)^y)

Power Limit 1 (PL1) Clamp (PKG_CLMP_LIM_1): Clamp mode control for PL1.

• 0 = PL1 power control is prevented from forcing P-states

below the base frequency / P1 for any domain in the SOC.
0h
16
RW/L
• 1 = PL1 power control will take all actions necessary to meet
the power target, even if that involves running at clock
frequencies below the base frequency / P1 level.
In order to ensure proper SOC cooling, it is generally recommended that the clamp
mode is always enabled.

Power Limit 1 (PL1) Enable (PKG_PWR_LIM_1_EN): Enable

0h
15 for Power Limit 1 (PL1). Setting this bit activates the power limit
RW/L
and time window defined for PL1.
Power Limit 1 (PL1) (PKG_PWR_LIM_1): Sets the average
power usage limit of the package domain corresponding to the PL1
time window. The power units of this field are specified by the
0h PACKAGE_POWER_SKU_UNIT_MSR.PWR_UNIT. This power limit
14:0
RW/L must be configured by software before it will engage. The PL1
limit is most commonly associated with long time windows (1s and
longer), although there are no explicit constraints on what
software configures.

5.7.34 IA_PERF_LIMIT_REASONS
(P_CR_IA_PERF_LIMIT_REASONS_0_0_0_MCHBAR)—
Offset 70B0h
This register reports reasons for performance limitations on the IA cores. Status bits
are an instantaneous indication of an active constraint. Log bits indicate that a
constraint was enforced since the log bit was last cleared.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

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3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IA_UTILIZATION_LOG
QOS_LOG

MCT_LOG
EDP_LOG
MULTI_CORE_TURBO_LOG
VR_THERMALERT_LOG

DEV3_LOG
DEV2_LOG

PL2_LOG
PL1_LOG
SPARE6_LOG
SPARE5_LOG
SPARE4_LOG

THERMAL_LOG
PROCHOT_LOG
QOS_STATUS
MAX_EFFICIENCY_FREQ_STATUS
MCT_STATUS
MAX_EFFICIENCY_FREQ_LOG

EDP_STATUS
MULTI_CORE_TURBO_STATUS
VR_THERMALERT_STATUS
IA_UTILIZATION_STATUS
DEV3_STATUS
DEV2_STATUS
SPARE6_STATUS
SPARE5_STATUS
SPARE4_STATUS
PL2_STATUS
PL1_STATUS
THERMAL_STATUS
PROCHOT_STATUS
Bit Default &
Field Name (ID): Description
Range Access

QOS_LOG (QOS_LOG): Logged indication that frequency was

0h
31 clamped below the software-defined quality-of-service floor. This
RW/0C/V
bit is set by firmware, and is clearable by software.
MAX_EFFICIENCY_FREQ_LOG
(MAX_EFFICIENCY_FREQ_LOG): Logged indication that
0h
30 frequency was clamped below the firmware-calculated maximum
RW/0C/V
efficiency frequency. This bit is set by firmware, and is clearable
by software.
MCT_LOG (MCT_LOG): Logged indication that frequency was
0h
29 clamped due to ratio change transition attenuation. This bit is set
RW/0C/V
by firmware, and is clearable by software.
EDP_LOG (EDP_LOG): Logged indication that frequency was
0h clamped due to the package-level Electrical Design Point
28
RW/0C/V constraint. This bit is set by firmware, and is clearable by
software.
MULTI_CORE_TURBO_LOG (MULTI_CORE_TURBO_LOG):
0h Logged indication that frequency was clamped due to effective
27
RW/0C/V multi-core turbo constraints. This bit is set by firmware, and is
clearable by software.
VR_THERMALERT_LOG (VR_THERMALERT_LOG): Logged
0h indication that frequency was clamped due to a voltage regulator
26
RW/0C/V thermal excursion. This bit is set by firmware, and is clearable by
software.
IA_UTILIZATION_LOG (IA_UTILIZATION_LOG): Logged
0h indication that frequency was clamped due to the autonomous
25
RW/0C/V utilization-based P-state control algorithm. This bit is set by
firmware, and is clearable by software.
DEV3_LOG (DEV3_LOG): Logged indication that frequency was
0h
24 clamped due to a Device 3 driver override. This bit is set by
RW/0C/V
firmware, and is clearable by software.

310 334818
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Bit Default &

Field Name (ID): Description
Range Access

DEV2_LOG (DEV2_LOG): Logged indication that frequency was

0h
23 clamped due to a Device 2 driver override. This bit is set by
RW/0C/V
firmware, and is clearable by software.
0h SPARE6_LOG (SPARE6_LOG): Spare log bit. This bit is set by
22
RW/0C/V firmware, and is clearable by software.
0h SPARE5_LOG (SPARE5_LOG): Spare log bit. This bit is set by
21
RW/0C/V firmware, and is clearable by software.
0h SPARE4_LOG (SPARE4_LOG): Spare log bit. This bit is set by
20
RW/0C/V firmware, and is clearable by software.
PL2_LOG (PL2_LOG): Logged indication that frequency was
0h
19 clamped due to a package-level PL2 excursion. This bit is set by
RW/0C/V
firmware, and is clearable by software.
PL1_LOG (PL1_LOG): Logged indication that frequency was
0h
18 clamped due to a package-level PL1 excursion. This bit is set by
RW/0C/V
firmware, and is clearable by software.
THERMAL_LOG (THERMAL_LOG): Logged indication that
0h
17 frequency was clamped due to a thermal excursion. This bit is set
RW/0C/V
by firmware, and is clearable by software.
PROCHOT_LOG (PROCHOT_LOG): Logged indication that
0h
16 frequency was clamped due to PROCHOT assertion. This bit is set
RW/0C/V
by firmware, and is clearable by software.
0h QOS_STATUS (QOS_STATUS): Frequency is limited below the
15
RO/V operating system or driver Quality-of-Service floor.
MAX_EFFICIENCY_FREQ_STATUS
0h
14 (MAX_EFFICIENCY_FREQ_STATUS): Frequency is limited
RO/V
below the maximum efficiency frequency.
MCT_STATUS (MCT_STATUS): Frequency is limited due to ratio
0h
13 change transition attenuation (MCT, prevents frequent ratio
RO/V
changes due to core C-state entry/exit).
0h EDP_STATUS (EDP_STATUS): Frequency is limited due to a
12
RO/V package-level EDP constraint.
MULTI_CORE_TURBO_STATUS
0h
11 (MULTI_CORE_TURBO_STATUS): Frequency is limited due to
RO/V
effective multi-core turbo constraints.
0h VR_THERMALERT_STATUS (VR_THERMALERT_STATUS):
10
RO/V Frequency is limited due to a VR thermal excursion.
IA_UTILIZATION_STATUS (IA_UTILIZATION_STATUS):
0h
9 Frequency is limited due to autonomous utilization-based P-state
RO/V
control.
0h DEV3_STATUS (DEV3_STATUS): Frequency is limited due to
8
RO/V Dev3 driver override.
0h DEV2_STATUS (DEV2_STATUS): Frequency is limited due to
7
RO/V Dev2 driver override.

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Bit Default &

Field Name (ID): Description
Range Access

6
0h SPARE6_STATUS (SPARE6_STATUS): Spare status bit.
RO/V

5
0h SPARE5_STATUS (SPARE5_STATUS): Spare status bit.
RO/V

4
0h SPARE4_STATUS (SPARE4_STATUS): Spare status bit.
RO/V

0h PL2_STATUS (PL2_STATUS): Frequency is limited due to a

3
RO/V package-level PL2 excursion.
0h PL1_STATUS (PL1_STATUS): Frequency is limited due to a
2
RO/V package-level PL1 excursion.
0h THERMAL_STATUS (THERMAL_STATUS): Frequency is limited
1
RO/V due to thermal excursion.
0h PROCHOT_STATUS (PROCHOT_STATUS): Frequency is limited
0
RO/V due to external PROCHOT assertion.

5.7.35 IA Core C0 Residency Counter

(P_CR_TELEM_IA_C0_RESIDENCY_0_0_0_MCHBAR)—
Offset 70C0h
This counter measures time that any core is active in the C0 state. This counter counts
at the crystal clock frequency divided by 16. This counter may be used along with the
IA Frequency Accumulator to calculate the average active clock ratio multiplier on the
IA domain. Average Active Frequency = Frequency Accumulator / C0
Residency

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA

Bit Default &

Field Name (ID): Description
Range Access

C0 Residency (DATA): This counter measures time that any

0h
31:0 core is active in the C0 state. This counter counts at the crystal
RO/V
clock frequency divided by 16.

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5.7.36 Graphics C0 Residency Counter

(P_CR_TELEM_GT_C0_RESIDENCY_0_0_0_MCHBAR)—
Offset 70C4h
This counter measures time that graphics is active in the C0 state. This counter counts
at the crystal clock frequency divided by 16. This counter may be used along with the
Graphics Frequency Accumulator to calculate the average active clock ratio multiplier
on the GT domain. Average Active Frequency = Frequency Accumulator / C0
Residency

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA

Bit Default &

Field Name (ID): Description
Range Access

C0 Residency (DATA): This counter measures time that graphics

0h
31:0 is active in the C0 state. This counter counts at the crystal clock
RO/V
frequency divided by 16.

5.7.37 I-unit Processing System C0 Residency Counter

(P_CR_TELEM_IUNIT_C0_RESIDENCY_0_0_0_MCHBAR)—
Offset 70C8h
This counter measures time that I-unit processing system is active in the C0 state. This
counter counts at the crystal clock frequency divided by 16. This counter may be used
along with the I-unit Frequency Accumulator to calculate the average active clock ratio
multiplier on the I-unit domain. Average Active Frequency = Frequency
Accumulator / C0 Residency

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA

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 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

C0 Residency (DATA): This counter measures time that I-unit

0h
31:0 processing system is active in the C0 state. This counter counts at
RO/V
the crystal clock frequency divided by 16.

5.7.38 TELEM_IA_FREQ_ACCUMULATOR
(P_CR_TELEM_IA_FREQ_ACCUMULATOR_0_0_0_MCHBAR
)—Offset 70CCh
Frequency accumulation data counted at ART >> 4

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA

Bit Default &

Field Name (ID): Description
Range Access

31:0
0h DATA (DATA): Residency data
RO/V

5.7.39 Graphics C0 Residency Counter

(P_CR_TELEM_GT_FREQ_ACCUMULATOR_0_0_0_MCHBAR
)—Offset 70D0h
This counter integrates the current clock ratio multiplier for the Graphics domain at the
same rate as the corresponding C0 residency counter. Its primary utility is in assessing
the average active frequency of the domain Average Active Frequency =
Frequency Accumulator / C0 Residency

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

314 334818
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DATA
Bit Default &
Field Name (ID): Description
Range Access

Clock Ratio Multiplier Accumulator (DATA): This counter

0h
31:0 integrates the current clock ratio of the domain at the same rate
RO/V
as the corresponding C0 residency counter

5.7.40 I-unit Processing System C0 Residency Counter

(P_CR_TELEM_IUNIT_FREQ_ACCUMULATOR_0_0_0_MCH
BAR)—Offset 70D4h
This counter integrates the current clock ratio multiplier for the I-unit processing
system domain at the same rate as the corresponding C0 residency counter. Its
primary utility is in assessing the average active frequency of the domain
Average Active Frequency = Frequency Accumulator / C0 Residency

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA

Bit Default &

Field Name (ID): Description
Range Access

Clock Ratio Multiplier Accumulator (DATA): This counter

0h
31:0 integrates the current clock ratio of the domain at the same rate
RO/V
as the corresponding C0 residency counter

5.7.41 Memory Active Residency

(P_CR_TELEM_FAR_MEMORY_ACTIVE_0_0_0_MCHBAR)—
Offset 70E8h
This counter measures the total time spent with memory active, as measured by any
rank being in the active or active idle state. The inverse of this counter indicates the
total time spent with all memory in the self-refresh state. This counter counts at the
crystal clock frequency divided by 16.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

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 MCHBAR

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000

DATA
Bit Default &
Field Name (ID): Description
Range Access

DATA (DATA): This counter measures the total time spent with
memory active, as measured by any rank being in the active or
0h
63:0 active idle state. The inverse of this counter indicates the total
RO/V
time spent with all memory in the self-refresh state. This counter
counts at the crystal clock frequency divided by 16.

5.7.42 Package Temperatures

(P_CR_PACKAGE_TEMPERATURES_0_0_0_MCHBAR)—
Offset 70F4h
Read-only register used for monitoring thermal status from all domains in the package.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SA_Temperature

ISP_Temperature

GT_Temperature

IA_Temperature

Bit Default &

Field Name (ID): Description
Range Access

System Agent Temperature (SA_Temperature): System

0h agent domain max temperature in degrees C. Reported in a
31:24
RO/V signed, 2's complement format with the LSB representing 1'C
resolution (S8.7.0). Raw, unfiltered
I-unit Temperature (ISP_Temperature): Camera domain max
0h temperature in degrees C. Reported in a signed, 2's complement
23:16
RO/V format with the LSB representing 1'C resolution (S8.7.0). Raw,
unfiltered

316 334818
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Bit Default &

Field Name (ID): Description
Range Access

Graphics Temperature (GT_Temperature): Graphics domain

0h max temperature in degrees C. Reported in a signed, 2's
15:8
RO/V complement format with the LSB representing 1'C resolution
(S8.7.0). Raw, unfiltered
IA Core Temperature (IA_Temperature): Virtual max
0h temperature of all IA cores in degrees C. Reported in a signed, 2's
7:0
RO/V complement format with the LSB representing 1'C resolution
(S8.7.0). Raw, unfiltered

5.7.43 Package Thermal Limit Control

(P_CR_THERMAL_LIMIT_CONTROL_0_0_0_MCHBAR)—
Offset 7104h
This register is used for run-time control of the package level virtual thermal sensor.
This interrupt and threshold is most commonly utilized by drivers wishing to control
maximum silicon temperature in order to manage local or system level thermals due to
various physical constraints. This temperature configuration applies only to in-die
thermal sensors and not to any DRAM related thermal control.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENABLE

THERMAL_LIMIT_TEMP
RSVD

Bit Default &

Field Name (ID): Description
Range Access

0h
31:9 Reserved.
RO

0h Enable (ENABLE): When set, it enables run-time thermal limit

8
RW control to the THERMAL_LIMIT_TEMP described in this register.

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 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Package Thermal Limit Temperature

(THERMAL_LIMIT_TEMP): Maximum SOC temperature allowed.
Described in a signed, 2's complement format with the least
0h
7:0 significant bit representing 1'C resolution (S8.7.0). If the setting is
RW
higher than the processor's factory configured maximum
temperature as described in the TEMPERATURE_TARGET MSR, this
field is ignored. This field may be updated at any time.

5.7.44 Memory Subsystem Frequency Capabilities

(P_CR_MEMSS_FREQUENCY_CAPABILITIES_0_0_0_MCHB
AR)—Offset 7108h
Describes the maximum frequency capabilities of DDR supported on this particular
SOC. If the maximum supported frequency reports a zero, it indicates that the
respective DRAM technology is not supported on this product.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NUM_NM_CH

WIO_FREQ

LP4_FREQ_HIGH

LP4_FREQ_LOW

LP3_FREQ_HIGH

LP3_FREQ_LOW

Bit Default &

Field Name (ID): Description
Range Access

31:30
0h Reserved (NUM_NM_CH): Reserved
RW

29:24
0h Reserved (WIO_FREQ): Reserved
RW

LPDDR4 Max Frequency (LP4_FREQ_HIGH): This field

0h indicates maximum LPDDR4 frequency that SOC supports, in
23:18
RW integer multiple of 133.33MHz. A value of zero indicates LPDDR4
is not supported.
LPDDR4 Max Frequency at Min Voltage (LP4_FREQ_LOW):
This field indicates maximum LPDDR4 frequency supported at the
0h minimum voltage level, in integer multiple of 133.33MHz. If this
17:12
RW frequency is the same as 'Max' frequency, it indicates there is no
voltage scaling. A value of zero indicates LPDDR4 is not
supported.

318 334818
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Bit Default &

Field Name (ID): Description
Range Access

LPDDR3 Max Frequency (LP3_FREQ_HIGH): This field

0h indicates maximum LPDDR3 frequency that SOC supports, in
11:6
RW integer multiple of 133.33MHz. A value of zero indicates LPDDR3
is not supported.
LPDDR3 Max Frequency at Min Voltage (LP3_FREQ_LOW):
This field indicates maximum LPDDR3 frequency supported at the
0h minimum voltage level, in integer multiple of 133.33MHz. If this
5:0
RW frequency is the same as 'Max' frequency, it indicates there is no
voltage scaling. A value of zero indicates LPDDR3 is not
supported.

5.7.45 Memory Controller (MC) BIOS Reset Request and Status

(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR)—Offset 7114h
This register is used as the primary interface between BIOS and P-unit with respect to
the Memory sub-system reset flow. This register provides both details about the
current memory configuration as well as memory power-up sequencing controls. The
typical memory subsystem reset and configuration flow is as follows. Each bullet
describes the strict sequential ordering of the flow.
• BIOS reads MEMSS_FREQUENCY_CAPABILITIES to discover silicon capabilities.
• BIOS detects LPDDR DRAM frequency and the number of LPDDR channels that have
DRAM devices attached. These results are then configured into the LPDDR channel
active and frequency configuration fields.
• BIOS discovers if DRAM is currently in self-refresh, and if so, it configures Request
Type (REQ_TYPE) to 100b to indicate this state. The SOC then uses this information
as a way to ensure proper self-refresh exit flows as part of power-up sequencing.
• Once the lower 16 bits of the MC_BIOS_REQ register are configured based on
platform discovery, BIOS sets Run/Busy to initiate firmware to start the memory
subsystem reset sequence.
• P-unit firmware executes the initial configuration of PHY settings, and when
complete it clears Run/Busy bit
• BIOS executes DDR PHY static configuration flow and initializes PHY PLL, and
ensures that both steps are complete
• BIOS sets MC_BIOS_REQ.PHY_CONFIG_COMPLETE and MC_BIOS_REQ.RUN_BUSY
to start the next phase
• P-unit firmware initiates the power-up sequence for D-units and Wide I/O collateral
logic.
• P-unit firmware sets MC_BIOS_REQ.DUNIT_RESET_COMPLETE and clears the Run/
Busy when it is done.
• BIOS observes Run/Busy deassertion and continues with MRC flow to initilize, train,
configure memory subsystem settings.
• BIOS sets MC_BIOS_REQ.CPGC_MODE_COMPLETE and MC_BIOS_REQ.RUN_BUSY
to start the next phase
• P-unit firmware configures D-unit, PHY to support normal operation of memory
subsystem, and when completed, clears the Run/Busy bit
• BIOS waits for MC_BIOS_REQ.RUN_BUSY to clear, and then complete remaining
configuration of Dunit and MLMC.

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 MCHBAR

• BIOS executes memory configuration validation and lock sequence with the CSE.
• BIOS sets MC_BIOS_REQ.MEM_INIT_DONE and MC_BIOS_REQ.RUN_BUSY to
indicate to Punit that all memory configuration is complete and memory
configuration is locked.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_2

RESERVED_1

FM_CH3_ACTIVE
FM_CH2_ACTIVE
FM_CH1_ACTIVE
FM_CH0_ACTIVE

RESERVED_0
RUN_BUSY

DRAM_TYPE

MEM_INIT_DONE
CPGC_MODE_COMPLETE
DUNIT_RESET_COMPLETE

WIO_ONLY

REQ_TYPE_SPECIAL

REQ_DATA
PHY_CONFIG_COMPLETE

REQ_TYPE
Bit Default &
Field Name (ID): Description
Range Access

Run/Busy (RUN_BUSY): This bit indicates that the BIOS request is pending for P-
unit firmware processing. BIOS sets this bit together with command details defined in
the lower bits of this register. Firmware may only clear this bit after the BIOS request
has been observed and completed.
0h
31 • 0 = The MC BIOS reset mailbox is idle or the last request has
RW
been completed. Software may initiate new requests.
• 1 = The MC BIOS reset mailbox is busy. It is still handling a
request. Writes to the mailbox are not allowed at this time.

30:27
0h RESERVED_2 (RESERVED_2): reserved
RW

DRAM_TYPE (DRAM_TYPE): BIOS programs DRAM type filed:

• 001b = LPDDR3
0h
26:24 • 010b = LPDDR4
RW
• 100b = DDR3L
• else = reserved

23:20
0h RESERVED_1 (RESERVED_1): reserved
RW

Memory Init Done (MEM_INIT_DONE): BIOS programs this

0h
19 bit after memory subsystem is fully configured, including security
RW
locking configuration completed

320 334818
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Bit Default &

Field Name (ID): Description
Range Access

CPGC Mode Complete (CPGC_MODE_COMPLETE): BIOS

0h programs this bit after the memory train/init flow is complete. This
18
RW initiates P-unit firmware execution of memory and D-unit clock
configuration settings for normal operation
D-unit Reset Complete (DUNIT_RESET_COMPLETE): Punit
programs this bit after memory subsystem IPs are powered and
0h corresponding reset flows are complete. At this point, those blocks
17
RW are ready for executing the memory training flow, including
intialization to support CPGC mode. BIOS can talk to Dunit after
this.
Memory PHY Configuration Complete
(PHY_CONFIG_COMPLETE): BIOS programs this bit indicating
0h
16 PHY initial configuration is complete and all DDR PHY PLLs are
RW
locked. Upon observation of this flag, P-unit firmware will initiate
the power-up sequence of memory subsystem related IPs
DDR Channel 11 Active (FM_CH3_ACTIVE): BIOS writes this value to indicate a
DDR memory channel has DRAM devices active to allow the channel to have active
memory traffic. Note, by default, a channel is not active and BIOS needs to explicitly
0h program a value of 1 to indicate that the channel is active. If a channel is fused off on
15 a particular SOC, BIOS input is ignored:
RW
• 0 = channel not active
• 1 = channel active
DDR Channel 00 Active (FM_CH2_ACTIVE): BIOS writes this value to indicate a
DDR memory channel has DRAM devices active to allow the channel to have active
memory traffic. Note, by default, a channel is not active and BIOS needs to explicitly
0h program a value of 1 to indicate that the channel is active. If a channel is fused off on
14 a particular SOC, BIOS input is ignored:
RW
• 0 = channel not active
• 1 = channel active
DDR Channel 10 Active (FM_CH1_ACTIVE): BIOS writes this value to indicate a
DDR memory channel has DRAM devices active to allow the channel to have active
memory traffic. Note, by default, a channel is not active and BIOS needs to explicitly
0h program a value of 1 to indicate that the channel is active. If a channel is fused off on
13 a particular SOC, BIOS input is ignored:
RW
• 0 = channel not active
• 1 = channel active
DDR Channel 01 Active (FM_CH0_ACTIVE): BIOS writes this value to indicate a
DDR memory channel has DRAM devices active to allow the channel to have active
memory traffic. Note, by default, a channel is not active and BIOS needs to explicitly
0h program a value of 1 to indicate that the channel is active. If a channel is fused off on
12 a particular SOC, BIOS input is ignored:
RW
• 0 = channel not active
• 1 = channel active

11
0h RESERVED_2 (WIO_ONLY): Reserved
RW

10
0h RESERVED_0 (RESERVED_0): reserved
RW

9
0h RESERVED_3 (REQ_TYPE_SPECIAL): reserved
RW

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Bit Default &

Field Name (ID): Description
Range Access

Request Type (REQ_TYPE): This field is used to configure reset hints to the P-unit
firmware. Encodings include:

0h • 1xxb = Memory is in self-refresh, manual self-refresh exit is

8:6 required
RW

• 0xxb = Memory is not in self-refresh or DRAM contents do not

need to be preserved.
DDR Frequency Configuration (REQ_DATA): BIOS programs
this field to request DDR frequency in integer multiple of
133.33MHz. BIOS reads MEMSS_FREQUENCY_CAPABILITIES
0h
5:0 register(s) to discover maximum SOC supported capabilities. And
RW
BIOS is expected to request only legal DDR
frequencies that are equal or lower than the maximum SOC
supported capabilities.

5.7.46 MEMSS_FREQUENCY_CAPABILITIES1
(P_CR_MEMSS_FREQUENCY_CAPABILITIES1_0_0_0_MCH
BAR)—Offset 7118h
Describes the maximum frequency capabilities of DDR supported and DDR
configuration on this particular SOC. If the maximum supported frequency reports a
zero, it indicates that the respective DRAM technology is not supported on this product.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DDR3L_FREQ_LOW 0 0 0
DDR_CONFIG_LIMITATION
RESERVED_2

RESERVED_1

DDR3L_FREQ_HIGH

Bit Default &

Field Name (ID): Description
Range Access

31:25
0h RESERVED_2 (RESERVED_2): reserved
RW

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Bit Default &

Field Name (ID): Description
Range Access

DDR_CONFIG_LIMITATION (DDR_CONFIG_LIMITATION): Describe the DDR

configuration limitation of this particular SOC:
0h • 0 = no DDR configuration limitation
24
RW
• 1 = DDR configuration is limited to1ch x 64-bit DDR3L, or 2ch
x32 LPDDR3 or LPDDR4

23:12
0h RESERVED_1 (RESERVED_1): reserved
RW

DDR3L Max Frequency (DDR3L_FREQ_HIGH): This field

0h indicates maximum DDR3L frequency that SOC supports, in
11:6
RW integer multiple of 133.33MHz. A value of zero indicates DDR3L is
not supported.
DDR3L Max Frequency at Min Voltage
(DDR3L_FREQ_LOW): This field indicates maximum DDR3L
0h frequency supported at the minimum voltage level, in integer
5:0
RW multiple of 133.33MHz. If this frequency is the same as 'Max'
frequency, it indicates there is no voltage scaling. A value of zero
indicates LPDDR4 is not supported.

5.7.47 PP1_C0_CORE_CLOCK_0_0_0_MCHBAR
(P_CR_PP1_C0_CORE_CLOCK_0_0_0_MCHBAR)—Offset
7160h
GT RC0 residency counter. Holds the accumulated number of CS clks that GT has been
in RC0.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA

Bit Default &

Field Name (ID): Description
Range Access

31:0
0h DATA (DATA): Accumulated cycles GT has been in RC0.
RO/V

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 MCHBAR

5.7.48 Core Exists Vector

(P_CR_CORE_EXISTS_VECTOR_0_0_0_MCHBAR)—Offset
7164h
Indication of the physical presence of IA cores in this silicon. IA core modules are
defined as containing pairs of cores and an associated L2 cache. Module existance can
therefore be inferred by OR'ing pairs of COREx_EXISTS in this register. This register
does not reflect the impact of any software-based core disabling. It always reflects the
capabilities of the silicon.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD

CORE3_EXISTS
CORE2_EXISTS
CORE1_EXISTS
CORE0_EXISTS
Bit Default &
Field Name (ID): Description
Range Access

0h
31:4 Reserved.
RO

0h CORE3_EXISTS (CORE3_EXISTS): Indication of core physical

3
RW presence
0h CORE2_EXISTS (CORE2_EXISTS): Indication of core physical
2
RW presence
0h CORE1_EXISTS (CORE1_EXISTS): Indication of core physical
1
RW presence
0h CORE0_EXISTS (CORE0_EXISTS): Indication of core physical
0
RW presence

5.7.49 Software Core Disable Mask

(P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR)—Offset
7168h
Software may disable cores using this interface. The bit definition of this register
exactly matches that defined in the CORE_EXISTS_VECTOR register. Punit firmware will
apply the mask programmed into this register against the CORE_EXISTS_VECTOR to
establish the resolved cores and modules to power up after a cold reset. The flow is as
follows:
• Cold boot

324 334818
MCHBAR

• BIOS reads CORE_EXISTS_VECTOR to establish which modules and cores are

present
• BIOS writes 1b to the corresponding core that it wishes to disable.
• BIOS may disable entire modules by writing 1b to a pair of cores.
• The results of the configuration are maintained in the sustain power well.
• BIOS initiates a cold reset flow at the platform. In a cold reset, the sustain power
well maintains power most other rails are power cycled.
• On cold reset exit, Punit firmware inspects the core configuration and launches only
the cores requested by BIOS. To software, it will appear as if these cores do not
exist.

Software may discover the resolved core exists vector: resolved_core_exists_vector =

(!CORE_DISABLE_MASK) & CORE_EXISTS_VECTOR

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD

CORE3_DISABLE_MASK
CORE2_DISABLE_MASK
CORE1_DISABLE_MASK
CORE0_DISABLE_MASK
Bit Default &
Field Name (ID): Description
Range Access

0h
31:4 Reserved.
RO

0h CORE3_DISABLE_MASK (CORE3_DISABLE_MASK): core3

3
RW disable mask
0h CORE2_DISABLE_MASK (CORE2_DISABLE_MASK): core2
2
RW disable mask
0h CORE1_DISABLE_MASK (CORE1_DISABLE_MASK): core1
1
RW disable mask
0h CORE0_DISABLE_MASK (CORE0_DISABLE_MASK): core0
0
RW disable mask

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 MCHBAR

5.7.50 PL3 and PL4 Control

(P_CR_PL3_CONTROL_0_0_0_MCHBAR)—Offset 71F0h
Control Power Limit 3 (PL3) and Power Limit 4 (PL4) using this register. This limit
control is physically different from the same control in the IA core MSR space.
• PL3 is designed to clamp peak sustained power to levels supported by the battery
or input power supply and as such manage lifetime degredation of that power
delivery element. With PL3, peak power excursions above the limit are allowed so
long as they do not exceed the configured duty cycle constraint in this register.
• PL4 is designed to clamp peak instantaneous power to levels below the max
supported by the battery or input power supply. These clamps are implemented a
priori and the SOC is guaranteed to constrain itself below the PL4 limit always.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
RSVD

PL4_ENABLE

RSVD

RSVD
PL3_ENABLE
LOCK

PMAX

POWER_LIMIT
DUTY_CYCLE

TIME_WINDOW

Bit Default &

Field Name (ID): Description
Range Access

Lock (LOCK): Write a 1b to lock this register until next reset.

0h
63 Once locked, no further updates may be written to any bits in the
RW/L
register.
0h
62:48 Reserved.
RO

PL4 Enable (PL4_ENABLE):

0h
47 • 0 = disabled
RW/L
• 1 = enabled
PL4 Max Power (PMAX): Power Limit 'PL4' or Pmax power limit
0h in the units as described PACAKGE_POWER_SKU_UNIT MSR. The
46:32
RW/L SOC guarantees it will never exceed this power limit even for very
short time windows.
0h
31 Reserved.
RO

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Bit Default &

Field Name (ID): Description
Range Access

PL3 Duty Cycle (DUTY_CYCLE): Power limit excursion duty

cycle control for PL3, describing what percentage of time it is
allowed for the SOC to exceed the programmed PL3 power limit.
0h 0% implies excursions are not supported ever and 100% implies
30:24
RW/L excursions are always allowed (effectively disabling the feature).
Units are in percentage(%). E.g., to allow for 20% excursion time
and 80% PL3 power limit clamp time, program a value of 14h.
Values greater than 100 (64h) are clipped to 100%.
PL3 Time Window (TIME_WINDOW): Duration over which duty cycle control will
be maintained. The bits of this field describe parameters for a mathematical equation
for time window configuration. This time window is strictly adhered to, if the window
described is 40ms, then silicon guarantees no excursions to the programmed duty
cycle within a rolling 40ms window. This field is split into two sub-fields:
0h
23:17
RW/L • x = bits[6:5]
• y = bits[4:0]
Time window equation: time_window =
PACKAGE_POWER_SKU_UNIT.TIME_UNIT * ((1+x/4)^y)

0h
16 Reserved.
RO

PL3 Enable (PL3_ENABLE):

0h
15 • 0 = disabled
RW/L
• 1 = enabled
PL3 Power Limit (POWER_LIMIT): Power Limit 3 (PL3) or
PAppMax power level. Any SOC power measurement observed
0h above this level is considered as an excursion against the PL3
14:0
RW/L power limit and duty cycle / time window budget. Units of this
power limit are defined by
PACKAGE_POWER_SKU_UNIT_MSR.PWR_UNIT.

5.7.51 Graphics Superqueue Active Clocks

(P_CR_PP1_ANY_THREAD_ACTIVITY_0_0_0_MCHBAR)—
Offset 7244h
Graphics Superqueue active residency counter. Counts at the crystal clock frequency
divided by 16.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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 MCHBAR

SUPERQUEUE_ACTIVE_RESIDENCY
Bit Default &
Field Name (ID): Description
Range Access

Superqueue Active Residency

0h (SUPERQUEUE_ACTIVE_RESIDENCY): Graphics Superqueue
31:0
RO/V active residency counter. Counts in crystal reference clocks
divided by 16.

5.7.52 LPDDR DRAM Thermal (MR4) Status of Channel 00

(P_CR_MEM_MR4_TEMPERATURE_DEV3_0_0_0_MCHBAR
)—Offset 7248h
LPDDR DRAM Thermal (MR4) Status of Channel 00, when there are multiple DRAMs in a
rank, the maximun MR4 is reported

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_0

MR4_RANK_1

MR4_RANK_0

Bit Default &

Field Name (ID): Description
Range Access

31:6
0h RESERVED_0 (RESERVED_0): Reserved
RO

MR4 DRAM thermal status of Channel 00 Rank 1

0h (MR4_RANK_1): This field is updated each read of LPDDR DRAM
5:3
RW MR4 Device Temperature Status per rank. Update rate is
configured by BIOS.

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MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

MR4 DRAM thermal status of Channel 00 Rank 0

0h (MR4_RANK_0): This field is updated each read of LPDDR DRAM
2:0
RW MR4 Device Temperature Status per rank. Update rate is
configured by BIOS.

5.7.53 LPDDR DRAM Thermal (MR4) Status of Channel 11

(P_CR_MEM_MR4_TEMPERATURE_DEV4_0_0_0_MCHBAR
)—Offset 724Ch
LPDDR DRAM Thermal (MR4) Status of Channel 11, when there are multiple DRAMs in a
rank, the maximun MR4 is reported

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MR4_RANK_1

MR4_RANK_0
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

31:6
0h RESERVED_0 (RESERVED_0): Reserved
RO

MR4 DRAM thermal status of Channel 11 Rank 1

0h (MR4_RANK_1): This field is updated each read of LPDDR DRAM
5:3
RW MR4 Device Temperature Status per rank. Update rate is
configured by BIOS.
MR4 DRAM thermal status of Channel 11 Rank 0
0h (MR4_RANK_0): This field is updated each read of LPDDR DRAM
2:0
RW MR4 Device Temperature Status per rank. Update rate is
configured by BIOS.

5.8 Registers Summary

Table 5-8. Summary of pcs_regs_wrapper Registers
Offset Offset
Register Name (ID)—Offset Default Value
Start End

Upstream Device Arbiter Grant Count A2T

6400h 6403h 1010101h
(A_CR_UPARB_GCNT_DEV_A2T_MCHBAR)—Offset 6400h

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Table 5-8. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

Upstream A2B Arbiter Channel 0 Grant Count

6404h 6407h 1010101h
(A_CR_UPARB_GCNT_A2B_0_MCHBAR)—Offset 6404h

Upstream A2B Arbiter Channel 1 Grant Count

6408h 640Bh 1010101h
(A_CR_UPARB_GCNT_A2B_1_MCHBAR)—Offset 6408h

Upstream A2B Arbiter Channel 2 Grant Count

640Ch 640Fh 1000100h
(A_CR_UPARB_GCNT_A2B_2_MCHBAR)—Offset 640Ch

Upstream A2B Arbiter Channel 3 Grant Count

6410h 6413h 1010101h
(A_CR_UPARB_GCNT_A2B_3_MCHBAR)—Offset 6410h

Upstream A2B Arbiter Channel 4 Grant Count

6414h 6417h 1000100h
(A_CR_UPARB_GCNT_A2B_4_MCHBAR)—Offset 6414h

Upstream A2B Arbiter Channel 5 Grant Count

6418h 641Bh 1000101h
(A_CR_UPARB_GCNT_A2B_5_MCHBAR)—Offset 6418h

Upstream A2B Arbiter Channel 6 Grant Count

641Ch 641Fh 1000101h
(A_CR_UPARB_GCNT_A2B_6_MCHBAR)—Offset 641Ch

Upstream A2B Arbiter Channel 7 Grant Count

6420h 6423h 1000101h
(A_CR_UPARB_GCNT_A2B_7_MCHBAR)—Offset 6420h

Upstream A2T Arbiter Channel 0 Grant Count

6424h 6427h 1000101h
(A_CR_UPARB_GCNT_A2T_0_MCHBAR)—Offset 6424h

Upstream P2P Arbiter Channel 0 Grant Count

6428h 642Bh 1010101h
(A_CR_UPARB_GCNT_P2P_0_MCHBAR)—Offset 6428h

Upstream P2P Arbiter Channel 1 Grant Count

642Ch 642Fh 1010101h
(A_CR_UPARB_GCNT_P2P_1_MCHBAR)—Offset 642Ch

Upstream Private Credit Return Grant Count Posted 0

6430h 6433h (A_CR_CRDARB_PRIV_GCNT_DEV_P_0_MCHBAR)—Offset 1000101h
6430h

Upstream Private Credit Return Grant Count Posted 1

6434h 6437h (A_CR_CRDARB_PRIV_GCNT_DEV_P_1_MCHBAR)—Offset 1010100h
6434h

Upstream Private Credit Return Grant Count Non-posted 0

6438h 643Bh (A_CR_CRDARB_PRIV_GCNT_DEV_N_0_MCHBAR)—Offset 1010101h
6438h

Upstream Private Credit Return Grant Count Posted 1

643Ch 643Fh (A_CR_CRDARB_PRIV_GCNT_DEV_N_1_MCHBAR)—Offset 1040104h
643Ch

Upstream Private Credit Return Grant Count Completion

6440h 6443h (A_CR_CRDARB_PRIV_GCNT_DEV_C_0_MCHBAR)—Offset 101h
6440h

Upstream Shared Credit Return Grant Count Posted 0

6444h 6447h (A_CR_CRDARB_SHRD_GCNT_DEV_P_0_MCHBAR)—Offset 1000101h
6444h

Upstream Shared Credit Return Grant Count Posted 1

6448h 644Bh (A_CR_CRDARB_SHRD_GCNT_DEV_P_1_MCHBAR)—Offset 1010100h
6448h

Upstream Shared Credit Return Grant Count Non-posted 0

644Ch 644Fh (A_CR_CRDARB_SHRD_GCNT_DEV_N_0_MCHBAR)—Offset 1010101h
644Ch

Upstream Shared Credit Return Grant Count Posted 1

6450h 6453h (A_CR_CRDARB_SHRD_GCNT_DEV_N_1_MCHBAR)—Offset 1040104h
6450h

Upstream Shared Credit Return Grant Count Completion

6454h 6457h (A_CR_CRDARB_SHRD_GCNT_DEV_C_0_MCHBAR)—Offset 101h
6454h

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Table 5-8. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

Upstream Credit Arbiter Private Credit Return Class Arbiter

6458h 645Bh Grant Count (A_CR_CRDARB_PRIV_GCNT_CLS_MCHBAR)— 10101h
Offset 6458h

Upstream Credit Arbiter Shared Cedit Return Class Arbiter

645Ch 645Fh Grant Count (A_CR_CRDARB_SHRD_GCNT_CLS_MCHBAR)— 10101h
Offset 645Ch

Gazelle Queue Limit Channel 0-3

6460h 6463h FFFFFFFFh
(A_CR_GZLQ_LIMIT_CH0_3_MCHBAR)—Offset 6460h

Gazelle Queue Limit Channels 4-7

6464h 6467h FFFFFFFFh
(A_CR_GZLQ_LIMIT_CH4_7_MCHBAR)—Offset 6464h

IOMMU Arbiter Grant Count VC0a Register

6468h 646Bh (A_CR_IOMMUARB_GCNT_VC0a_0_0_0_MCHBAR)—Offset 10101h
6468h

IOMMU Arbiter Grant Count VC0b Register

646Ch 646Fh (A_CR_IOMMUARB_GCNT_VC0b_0_0_0_MCHBAR)—Offset 10101h
646Ch

IOMMU Arbiter Grant Count VC1b Register

6470h 6473h (A_CR_IOMMUARB_GCNT_VC1b_0_0_0_MCHBAR)—Offset 10101h
6470h

Gazelle Queue Reserved Entries Channels 0-3

6474h 6477h 4040101h
(A_CR_GZLQ_RSVD_CH0_3_MCHBAR)—Offset 6474h

Gazelle Queue Reserved Entries Channels 4-7

6478h 647Bh 1010101h
(A_CR_GZLQ_RSVD_CH4_7_MCHBAR)—Offset 6478h

647Ch 647Fh Spare BIOS (A_CR_SPARE_BIOS_MCHBAR)—Offset 647Ch 0h

Upcmd Credit Maximum Channel 0

6490h 6493h (A_CR_UPCMD_CRDTMAX_CH0_0_0_0_MCHBAR)—Offset 4040Ch
6490h

Upcmd Credit Maximum Channel 1

6494h 6497h (A_CR_UPCMD_CRDTMAX_CH1_0_0_0_MCHBAR)—Offset 40404h
6494h

Upcmd Credit Maximum Channel 2

6498h 649Bh (A_CR_UPCMD_CRDTMAX_CH2_0_0_0_MCHBAR)—Offset 7F00h
6498h

Upcmd Credit Maximum Channel 3

649Ch 649Fh (A_CR_UPCMD_CRDTMAX_CH3_0_0_0_MCHBAR)—Offset 7F7Fh
649Ch

Upcmd Credit Maximum Channel 4

64A0h 64A3h (A_CR_UPCMD_CRDTMAX_CH4_0_0_0_MCHBAR)—Offset 400h
64A0h

Upcmd Credit Maximum Channel 5

64A4h 64A7h (A_CR_UPCMD_CRDTMAX_CH5_0_0_0_MCHBAR)—Offset 404h
64A4h

Upcmd Credit Maximum Channel 6

64A8h 64ABh (A_CR_UPCMD_CRDTMAX_CH6_0_0_0_MCHBAR)—Offset 404h
64A8h

Upcmd Credit Maximum Channel 7

64ACh 64AFh (A_CR_UPCMD_CRDTMAX_CH7_0_0_0_MCHBAR)—Offset 40Ch
64ACh

MOT OUT Base Register

64C0h 64C3h 0h
(A_CR_MOT_OUT_BASE_0_0_0_MCHBAR)—Offset 64C0h

MOT OUT Mask Register

64C4h 64C7h 0h
(A_CR_MOT_OUT_MASK_0_0_0_MCHBAR)—Offset 64C4h

64C8h 64CFh CHAP Select 1 (A_CR_CHAP_SLCT1_MCHBAR)—Offset 6500h 40061010202h

64D0h 64D7h CHAP Select 1 (A_CR_CHAP_SLCT1_MCHBAR)—Offset 6500h 80000C0063010217h

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Table 5-8. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

64D8h 64DFh CHAP Select 1 (A_CR_CHAP_SLCT1_MCHBAR)—Offset 6500h C0061000212h

64E0h 64E7h CHAP Select 1 (A_CR_CHAP_SLCT1_MCHBAR)—Offset 6500h 40001000202h

64E8h 64EFh CHAP Select 1 (A_CR_CHAP_SLCT1_MCHBAR)—Offset 6500h FFFFFFFFFFFFFFFFh

64F0h 64F7h CHAP Select 1 (A_CR_CHAP_SLCT1_MCHBAR)—Offset 6500h 40001000202h

6500h 6503h CHAP Select 1 (A_CR_CHAP_SLCT1_MCHBAR)—Offset 6500h 0h

6504h 6507h CHAP Select 2 (A_CR_CHAP_SLCT2_MCHBAR)—Offset 6504h 0h

6508h 650Bh CHAP Select 3 (A_CR_CHAP_SLCT3_MCHBAR)—Offset 6508h 4h

Slice and Channel Hash

6510h 6517h (A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR)—Offset C0061010202h
65C0h

Slice and Channel Hash

6518h 651Fh (A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR)—Offset F0FFFF0FFFF0FFFFh
65C0h

Slice and Channel Hash

6520h 6527h (A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR)—Offset C0061010202h
65C0h

Slice and Channel Hash

6588h 658Bh (A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR)—Offset 0h
65C0h

Slice and Channel Hash

658Ch 658Fh (A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR)—Offset FFFFFFFFh
65C0h

Slice and Channel Hash

65C0h 65C7h (A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR)—Offset 3C00000000h
65C0h

Mirror Range Register

65C8h 65CFh 0h
(A_CR_MIRROR_RANGE_0_0_0_MCHBAR)—Offset 65C8h

ASYM MEM REGION 0 CONFIGURATION WITH NO

INTERLEAVING
65D0h 65D3h 0h
(A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR)—Offset
65D0h

ASYM MEM REGION 1 CONFIGURATION WITH NO

INTERLEAVING
65D4h 65D7h 0h
(A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR)—Offset
65D4h

Two-Way Asymmetric Memory Region Configuration

65D8h 65DBh (A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR)—Offset 0h
65D8h

5.8.1 Upstream Device Arbiter Grant Count A2T

(A_CR_UPARB_GCNT_DEV_A2T_MCHBAR)—Offset 6400h
Upstream Device arbiter grant count for A-Unit to T-Unit transactions.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1010101h

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3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

VC0B_C

VC0B_P

VC0A_C

VC0A_P
RSVD

RSVD

RSVD

RSVD
Bit Default &
Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h VC0B Completion Grant Count (VC0B_C): VC0B completion

29:24
RW grant count to T-Unit.
0h
23:22 Reserved.
RO

1h VC0B Posted Grant Count (VC0B_P): VC0B posted transaction

21:16
RW grant count to T-Unit. This is only for MSIs.
0h
15:14 Reserved.
RO

1h VC0A Completion Grant Count (VC0A_C): VC0A completion

13:8
RW grant count to T-Unit.
0h
7:6 Reserved.
RO

1h VC0A Posted Grant Count (VC0A_P): VC0A posted to T-Unit

5:0
RW MSIs.

5.8.2 Upstream A2B Arbiter Channel 0 Grant Count

(A_CR_UPARB_GCNT_A2B_0_MCHBAR)—Offset 6404h
Upstream Class/Target arbiter grant count.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1010101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
CHID0_MMU_NP

CHID0_NP

CHID0_P
RSVD

RSVD

RSVD

RSVD
CHID0_TGT

334818 333
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 0 Target Arbiter Grant Count (CHID0_TGT):

29:24
RW Target arbiter grant count for the channel ID 0 class arbiter.
0h
23:22 Reserved.
RO

Channel ID 0 Non-posted IOMMU Grant Count

1h
21:16 (CHID0_MMU_NP): Grant count for IOMMU non-posted
RW
transactions on channel ID 0.
0h
15:14 Reserved.
RO

1h Channel ID 0 Non-posted Grant Count (CHID0_NP): Grant

13:8
RW count for non-posted transactions on channel ID 0.
0h
7:6 Reserved.
RO

1h Channel ID 0 P Grant Count (CHID0_P): Grant count for

5:0
RW posted transactions on channel ID 0.

5.8.3 Upstream A2B Arbiter Channel 1 Grant Count

(A_CR_UPARB_GCNT_A2B_1_MCHBAR)—Offset 6408h
Upstream Class/Target arbiter grant count.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1010101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
CHID1_MMU_NP

CHID1_NP

CHID1_P
RSVD

RSVD

RSVD

RSVD
CHID1_TGT

Bit Default &

Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 1 Target Arbiter Grant Count (CHID1_TGT):

29:24
RW Target arbiter grant count for the channel ID 1 class arbiter.

334 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h
23:22 Reserved.
RO

Channel ID 1 Non-posted IOMMU Grant Count

1h
21:16 (CHID1_MMU_NP): Grant count for IOMMU non-posted
RW
transactions on channel ID 1.
0h
15:14 Reserved.
RO

1h Channel ID 1 Non-posted Grant Count (CHID1_NP): Grant

13:8
RW count for non-posted transactions on channel ID 1.
0h
7:6 Reserved.
RO

1h Channel ID 1 P Grant Count (CHID1_P): Grant count for

5:0
RW posted transactions on channel ID 1.

5.8.4 Upstream A2B Arbiter Channel 2 Grant Count

(A_CR_UPARB_GCNT_A2B_2_MCHBAR)—Offset 640Ch
Upstream Class/Target arbiter grant count.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1000100h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
CHID2_TGT

CHID2_MMU_NP

CHID2_NP

CHID2_P
RSVD

RSVD

RSVD

RSVD

Bit Default &

Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 2 Target Arbiter Grant Count (CHID2_TGT):

29:24
RW Target arbiter grant count for the channel ID 2 class arbiter.
0h
23:22 Reserved.
RO

Channel ID 2 Non-posted IOMMU Grant Count

0h
21:16 (CHID2_MMU_NP): Grant count for IOMMU non-posted
RO
transactions on channel ID 2.

334818 335
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h
15:14 Reserved.
RO

1h Channel ID 2 Non-posted Grant Count (CHID2_NP): Grant

13:8
RW count for non-posted transactions on channel ID 2.
0h
7:6 Reserved.
RO

0h Channel ID 2 P Grant Count (CHID2_P): Grant count for

5:0
RO posted transactions on channel ID 2.

5.8.5 Upstream A2B Arbiter Channel 3 Grant Count

(A_CR_UPARB_GCNT_A2B_3_MCHBAR)—Offset 6410h
Upstream Class/Target arbiter grant count.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1010101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
RSVD

RSVD

RSVD

RSVD
CHID3_TGT

CHID3_MMU_NP

CHID3_NP

Bit Default & CHID3_P

Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 3 Target Arbiter Grant Count (CHID3_TGT):

29:24
RW Target arbiter grant count for the channel ID 3 class arbiter.
0h
23:22 Reserved.
RO

Channel ID 3 Non-posted IOMMU Grant Count

1h
21:16 (CHID3_MMU_NP): Grant count for IOMMU non-posted
RW
transactions on channel ID 3.
0h
15:14 Reserved.
RO

1h Channel ID 3 Non-posted Grant Count (CHID3_NP): Grant

13:8
RW count for non-posted transactions on channel ID 3.

336 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h
7:6 Reserved.
RO

1h Channel ID 3 P Grant Count (CHID3_P): Grant count for

5:0
RW posted transactions on channel ID 3.

5.8.6 Upstream A2B Arbiter Channel 4 Grant Count

(A_CR_UPARB_GCNT_A2B_4_MCHBAR)—Offset 6414h
Upstream Class/Target arbiter grant count.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1000100h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
RSVD

RSVD

RSVD

RSVD
CHID4_TGT

CHID4_MMU_NP

CHID4_NP

CHID4_P
Bit Default &
Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 4 Target Arbiter Grant Count (CHID4_TGT):

29:24
RW Target arbiter grant count for the channel ID 4 class arbiter.
0h
23:22 Reserved.
RO

Channel ID 4 Non-posted IOMMU Grant Count

0h
21:16 (CHID4_MMU_NP): Grant count for IOMMU non-posted
RO
transactions on channel ID 4.
0h
15:14 Reserved.
RO

1h Channel ID 4 Non-posted Grant Count (CHID4_NP): Grant

13:8
RW count for non-posted transactions on channel ID 4.
0h
7:6 Reserved.
RO

0h Channel ID 4 P Grant Count (CHID4_P): Grant count for

5:0
RO posted transactions on channel ID 4.

334818 337
 MCHBAR

5.8.7 Upstream A2B Arbiter Channel 5 Grant Count

(A_CR_UPARB_GCNT_A2B_5_MCHBAR)—Offset 6418h
Upstream Class/Target arbiter grant count.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1000101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
RSVD

RSVD

RSVD

RSVD
CHID5_TGT

CHID5_MMU_NP

CHID5_NP

CHID5_P
Bit Default &
Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 5 Target Arbiter Grant Count (CHID5_TGT):

29:24
RW Target arbiter grant count for the channel ID 5 class arbiter.
0h
23:22 Reserved.
RO

Channel ID 5 Non-posted IOMMU Grant Count

0h
21:16 (CHID5_MMU_NP): Grant count for IOMMU non-posted
RO
transactions on channel ID 5.
0h
15:14 Reserved.
RO

1h Channel ID 5 Non-posted Grant Count (CHID5_NP): Grant

13:8
RW count for non-posted transactions on channel ID 5.
0h
7:6 Reserved.
RO

1h Channel ID 5 P Grant Count (CHID5_P): Grant count for

5:0
RW posted transactions on channel ID 5.

5.8.8 Upstream A2B Arbiter Channel 6 Grant Count

(A_CR_UPARB_GCNT_A2B_6_MCHBAR)—Offset 641Ch
Upstream Class/Target arbiter grant count for A-Unit to B-Unit transactions.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

338 334818
MCHBAR

Default: 1000101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

CHID6_MMU_NP

CHID6_NP

CHID6_P
RSVD

RSVD

RSVD

RSVD
CHID6_TGT

Bit Default &

Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 6 Target Arbiter Grant Count (CHID6_TGT):

29:24
RW Target arbiter grant count for the channel ID 6 class arbiter.
0h
23:22 Reserved.
RO

Channel ID 6 Non-posted IOMMU Grant Count

0h
21:16 (CHID6_MMU_NP): Grant count for IOMMU non-posted
RO
transactions on channel ID 6.
0h
15:14 Reserved.
RO

1h Channel ID 6 Non-posted Grant Count (CHID6_NP): Grant

13:8
RW count for non-posted transactions on channel ID 6.
0h
7:6 Reserved.
RO

1h Channel ID 6 P Grant Count (CHID6_P): Grant count for

5:0
RW posted transactions on channel ID 6.

5.8.9 Upstream A2B Arbiter Channel 7 Grant Count

(A_CR_UPARB_GCNT_A2B_7_MCHBAR)—Offset 6420h
Upstream Class/Target arbiter grant count for A-Unit to B-Unit transactions.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1000101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

334818 339
 MCHBAR

CHID7_MMU_NP

CHID7_NP

CHID7_P
RSVD

RSVD

RSVD

RSVD
CHID7_TGT
Bit Default &
Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 7 Target Arbiter Grant Count (CHID7_TGT):

29:24
RW Target arbiter grant count for the channel ID 7 class arbiter.
0h
23:22 Reserved.
RO

Channel ID 7 Non-posted IOMMU Grant Count

0h
21:16 (CHID7_MMU_NP): Grant count for IOMMU non-posted
RO
transactions on channel ID 7.
0h
15:14 Reserved.
RO

1h Channel ID 7 Non-posted Grant Count (CHID7_NP): Grant

13:8
RW count for non-posted transactions on channel ID 7.
0h
7:6 Reserved.
RO

1h Channel ID 7 P Grant Count (CHID7_P): Grant count for

5:0
RW posted transactions on channel ID 7.

5.8.10 Upstream A2T Arbiter Channel 0 Grant Count

(A_CR_UPARB_GCNT_A2T_0_MCHBAR)—Offset 6424h
Upstream Class/Target arbiter grant count for A-Unit to T-Unit transactions.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1000101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
CHID0_MMU_NP

CHID0_NP

CHID0_P
RSVD

RSVD

RSVD

RSVD
CHID0_TGT

340 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 0 Target Arbiter Grant Count (CHID0_TGT):

29:24
RW Target arbiter grant count for the channel ID 0 a2t class arbiter.
0h
23:22 Reserved.
RO

Channel ID 0 Non-posted IOMMU Grant Count

0h
21:16 (CHID0_MMU_NP): Grant count for IOMMU non-posted
RO
transactions on channel ID 0.
0h
15:14 Reserved.
RO

1h Channel ID 0 Non-posted Grant Count (CHID0_NP): Grant

13:8
RW count for non-posted transactions on channel ID 0.
0h
7:6 Reserved.
RO

1h Channel ID 0 P Grant Count (CHID0_P): Grant count for

5:0
RW posted transactions on channel ID 0.

5.8.11 Upstream P2P Arbiter Channel 0 Grant Count

(A_CR_UPARB_GCNT_P2P_0_MCHBAR)—Offset 6428h
Upstream Class/Target arbiter grant count.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1010101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
CHID0_C

CHID0_N

CHID0_P
RSVD

RSVD

RSVD

RSVD
CHID0_TGT

Bit Default &

Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 0 Target Arbiter Grant Count (CHID0_TGT):

29:24
RO Target arbiter grant count for the channel ID 0 p2p class arbiter.
0h
23:22 Reserved.
RO

334818 341
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

1h Channel ID 0 C Grant Count (CHID0_C): Grant count for

21:16
RO completions on channel ID 0.
0h
15:14 Reserved.
RO

1h Channel ID 0 Non-posted Grant Count (CHID0_N): Grant

13:8
RO count for non-posted transactions on channel ID 0.
0h
7:6 Reserved.
RO

1h Channel ID 0 P Grant Count (CHID0_P): Grant count for

5:0
RO posted transactions on channel ID 0.

5.8.12 Upstream P2P Arbiter Channel 1 Grant Count

(A_CR_UPARB_GCNT_P2P_1_MCHBAR)—Offset 642Ch
Upstream Class/Target arbiter grant count.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1010101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
CHID1_N
RSVD

RSVD

RSVD

RSVD
CHID1_TGT

CHID1_C

CHID1_P
Bit Default &
Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 1 Target Arbiter Grant Count (CHID1_TGT):

29:24
RO Target arbiter grant count for the channel ID 1 p2p class arbiter.
0h
23:22 Reserved.
RO

1h Channel ID 1 C Grant Count (CHID1_C): Grant count for

21:16
RO completions on channel ID 1.
0h
15:14 Reserved.
RO

1h Channel ID 1 Non-posted Grant Count (CHID1_N): Grant

13:8
RO count for non-posted transactions on channel ID 1.
0h
7:6 Reserved.
RO

342 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

1h Channel ID 1 P Grant Count (CHID1_P): Grant count for

5:0
RO posted transactions on channel ID 1

5.8.13 Upstream Private Credit Return Grant Count Posted 0

(A_CR_CRDARB_PRIV_GCNT_DEV_P_0_MCHBAR)—Offset
6430h
PSF credit return device arb grant count posted.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1000101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
CHID3

CHID2

CHID1

CHID0
RSVD

RSVD

RSVD

RSVD
Bit Default &
Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 3 P Grant Count (CHID3): Grant count for posted

29:24
RW transactions on channel ID 3.
0h
23:22 Reserved.
RO

0h Channel ID 2 P Grant Count (CHID2): Grant count for posted

21:16
RO transactions on channel ID 2.
0h
15:14 Reserved.
RO

1h Channel ID 1 P Grant Count (CHID1): Grant count for posted

13:8
RW transactions on channel ID 1.
0h
7:6 Reserved.
RO

1h Channel ID 0 P Grant Count (CHID0): Grant count for posted

5:0
RW transactions on channel ID 0.

5.8.14 Upstream Private Credit Return Grant Count Posted 1

(A_CR_CRDARB_PRIV_GCNT_DEV_P_1_MCHBAR)—Offset
6434h
PSF credit return device arb grant count posted.

334818 343
 MCHBAR

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1010100h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
CHID7

CHID6

CHID5

CHID4
RSVD

RSVD

RSVD

RSVD
Bit Default &
Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 7 P Grant Count (CHID7): Grant count for posted

29:24
RW transactions on channel ID 7.
0h
23:22 Reserved.
RO

1h Channel ID 6 P Grant Count (CHID6): Grant count for posted

21:16
RW transactions on channel ID 6.
0h
15:14 Reserved.
RO

1h Channel ID 5 P Grant Count (CHID5): Grant count for posted

13:8
RW transactions on channel ID 5.
0h
7:6 Reserved.
RO

0h Channel ID 4 P Grant Count (CHID4): Grant count for posted

5:0
RO transactions on channel ID 4.

5.8.15 Upstream Private Credit Return Grant Count Non-posted 0

(A_CR_CRDARB_PRIV_GCNT_DEV_N_0_MCHBAR)—Offset
6438h
PSF credit return device arb grant count non-posted.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1010101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

344 334818
MCHBAR

CHID3

CHID2

CHID1

CHID0
RSVD

RSVD

RSVD

RSVD
Bit Default &
Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 3 Non-posted Grant Count (CHID3): Grant count

29:24
RW for non-posted transactions on channel ID 3.
0h
23:22 Reserved.
RO

1h Channel ID 2 Non-posted Grant Count (CHID2): Grant count

21:16
RW for non-posted transactions on channel ID 2.
0h
15:14 Reserved.
RO

1h Channel ID 1 Non-posted Grant Count (CHID1): Grant count

13:8
RW for non-posted transactions on channel ID 1.
0h
7:6 Reserved.
RO

1h Channel ID 0 Non-posted Grant Count (CHID0): Grant count

5:0
RW for non-posted transactions on channel ID 0.

5.8.16 Upstream Private Credit Return Grant Count Posted 1

(A_CR_CRDARB_PRIV_GCNT_DEV_N_1_MCHBAR)—Offset
643Ch
PSF credit return device arb grant count non-posted.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1040104h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
RSVD

RSVD

RSVD

RSVD
CHID7

CHID6

CHID5

CHID4

Bit Default &

Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 7 Non-posted Grant Count (CHID7): Grant count

29:24
RW for non-posted transactions on channel ID 7.

334818 345
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h
23:22 Reserved.
RO

4h Channel ID 6 Non-posted Grant Count (CHID6): Grant count

21:16
RW for non-posted transactions on channel ID 6.
0h
15:14 Reserved.
RO

1h Channel ID 5 Non-posted Grant Count (CHID5): Grant count

13:8
RW for non-posted transactions on channel ID 5.
0h
7:6 Reserved.
RO

4h Channel ID 4 Non-posted Grant Count (CHID4): Grant count

5:0
RW for non-posted transactions on channel ID 4.

5.8.17 Upstream Private Credit Return Grant Count Completion

(A_CR_CRDARB_PRIV_GCNT_DEV_C_0_MCHBAR)—Offset
6440h
PSF credit return device arb grant count completion.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
CHID3

CHID2

CHID1

CHID0
RSVD

RSVD

RSVD

RSVD

Bit Default &

Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

0h Channel ID 3 C Grant Count (CHID3): Grant count for

29:24
RO completions on channel ID 3.
0h
23:22 Reserved.
RO

0h Channel ID 2 C Grant Count (CHID2): Grant count for

21:16
RO completions on channel ID 2.
0h
15:14 Reserved.
RO

1h Channel ID 1 C Grant Count (CHID1): Grant count for

13:8
RW completions on channel ID 1.

346 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h
7:6 Reserved.
RO

1h Channel ID 0 C Grant Count (CHID0): Grant count for

5:0
RW completions on channel ID 0.

5.8.18 Upstream Shared Credit Return Grant Count Posted 0

(A_CR_CRDARB_SHRD_GCNT_DEV_P_0_MCHBAR)—Offset
6444h
PSF credit return device arb grant count Posteds

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1000101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
CHID3

CHID2

CHID1

CHID0
RSVD

RSVD

RSVD

RSVD
Bit Default &
Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 3 P Grant Count (CHID3): Grant count for posted

29:24
RW transactions on channel ID 3.
0h
23:22 Reserved.
RO

0h Channel ID 2 P Grant Count (CHID2): Grant count for posted

21:16
RO transactions on channel ID 2.
0h
15:14 Reserved.
RO

1h Channel ID 1 P Grant Count (CHID1): Grant count for posted

13:8
RW transactions on channel ID 1.
0h
7:6 Reserved.
RO

1h Channel ID 0 P Grant Count (CHID0): Grant count for posted

5:0
RW transactions on channel ID 0.

334818 347
 MCHBAR

5.8.19 Upstream Shared Credit Return Grant Count Posted 1

(A_CR_CRDARB_SHRD_GCNT_DEV_P_1_MCHBAR)—Offset
6448h
PSF credit return device arb grant count posted.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1010100h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
CHID7

CHID6

CHID5

CHID4
RSVD

RSVD

RSVD

RSVD
Bit Default &
Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 7 P Grant Count (CHID7): Grant count for posted

29:24
RW transactions on channel ID 7.
0h
23:22 Reserved.
RO

1h Channel ID 6 P Grant Count (CHID6): Grant count for posted

21:16
RW transactions on channel ID 6.
0h
15:14 Reserved.
RO

1h Channel ID 5 P Grant Count (CHID5): Grant count for posted

13:8
RW transactions on channel ID 5.
0h
7:6 Reserved.
RO

0h Channel ID 4 P Grant Count (CHID4): Grant count for posted

5:0
RO transactions on channel ID 4.

5.8.20 Upstream Shared Credit Return Grant Count Non-posted 0

(A_CR_CRDARB_SHRD_GCNT_DEV_N_0_MCHBAR)—
Offset 644Ch
PSF credit return device arb grant count non-posted.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1010101h

348 334818
MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

CHID3

CHID2

CHID1

CHID0
RSVD

RSVD

RSVD

RSVD
Bit Default &
Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

1h Channel ID 3 Non-posted Grant Count (CHID3): Grant count

29:24
RW for non-posted transactions on channel ID 3.
0h
23:22 Reserved.
RO

1h Channel ID 2 Non-posted Grant Count (CHID2): Grant count

21:16
RW for non-posted transactions on channel ID 2.
0h
15:14 Reserved.
RO

1h Channel ID 1 Non-posted Grant Count (CHID1): Grant count

13:8
RW for non-posted transactions on channel ID 1.
0h
7:6 Reserved.
RO

1h Channel ID 0 Non-posted Grant Count (CHID0): Grant count

5:0
RW for non-posted transactions on channel ID 0.

5.8.21 Upstream Shared Credit Return Grant Count Posted 1

(A_CR_CRDARB_SHRD_GCNT_DEV_N_1_MCHBAR)—
Offset 6450h
PSF credit return device arb grant count non-posted.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1040104h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
RSVD

RSVD

RSVD

RSVD
CHID7

CHID6

CHID5

CHID4

Bit Default &

Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

334818 349
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

1h Channel ID 7 Non-posted Grant Count (CHID7): Grant count

29:24
RW for non-posted transactions on channel ID 7.
0h
23:22 Reserved.
RO

4h Channel ID 6 Non-posted Grant Count (CHID6): Grant count

21:16
RW for non-posted transactions on channel ID 6.
0h
15:14 Reserved.
RO

1h Channel ID 5 Non-posted Grant Count (CHID5): Grant count

13:8
RW for non-posted transactions on channel ID 5.
0h
7:6 Reserved.
RO

4h Channel ID 4 Non-posted Grant Count (CHID4): Grant count

5:0
RW for non-posted transactions on channel ID 4.

5.8.22 Upstream Shared Credit Return Grant Count Completion

(A_CR_CRDARB_SHRD_GCNT_DEV_C_0_MCHBAR)—Offset
6454h
PSF credit return device arb grant count completion.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
CHID3

CHID2

CHID1

CHID0
RSVD

RSVD

RSVD

RSVD

Bit Default &

Field Name (ID): Description
Range Access

0h
31:30 Reserved.
RO

0h Channel ID 3 C Grant Count (CHID3): Grant count for

29:24
RO completions on channel ID 3.
0h
23:22 Reserved.
RO

0h Channel ID 2 C Grant Count (CHID2): Grant count for

21:16
RO completions on channel ID 2.
0h
15:14 Reserved.
RO

350 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

1h Channel ID 1 C Grant Count (CHID1): Grant count for

13:8
RW completions on channel ID 1.
0h
7:6 Reserved.
RO

1h Channel ID 0 C Grant Count (CHID0): Grant count for

5:0
RW completions on channel ID 0.

5.8.23 Upstream Credit Arbiter Private Credit Return Class

Arbiter Grant Count
(A_CR_CRDARB_PRIV_GCNT_CLS_MCHBAR)—Offset
6458h
PSF credit return class arb grant count

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
RSVD

RSVD

RSVD
C

NP

P
Bit Default &
Field Name (ID): Description
Range Access

0h
31:22 Reserved.
RO

21:16
1h Completion (C): All Completions.
RW

0h
15:14 Reserved.
RO

13:8
1h Non-posted (NP): All non-posted.
RW

0h
7:6 Reserved.
RO

5:0
1h Posted (P): All posted.
RW

5.8.24 Upstream Credit Arbiter Shared Cedit Return Class Arbiter

Grant Count

334818 351
 MCHBAR

(A_CR_CRDARB_SHRD_GCNT_CLS_MCHBAR)—Offset
645Ch
PSF credit return class arb grant count

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
RSVD

RSVD

RSVD
C

NP

P
Bit Default &
Field Name (ID): Description
Range Access

0h
31:22 Reserved.
RO

21:16
1h C (C): All Completions
RW

0h
15:14 Reserved.
RO

13:8
1h NP (NP): All Non Posteds
RW

0h
7:6 Reserved.
RO

5:0
1h P (P): All Posteds
RW

5.8.25 Gazelle Queue Limit Channel 0-3

(A_CR_GZLQ_LIMIT_CH0_3_MCHBAR)—Offset 6460h
Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: FFFFFFFFh

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CHID3

CHID2

CHID1

CHID0

352 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

FFh Channel ID 3 (CHID3): Gazelle queue limit for Upstream NP on

31:24
RW channel ID 3.
FFh Channel ID 2 (CHID2): Gazelle queue limit for Upstream NP on
23:16
RW channel ID 2.
FFh Channel ID 1 (CHID1): Gazelle queue limit for Upstream NP on
15:8
RW channel ID 1.
FFh Channel ID 0 (CHID0): Gazelle queue limit for Upstream NP on
7:0
RW channel ID 0.

5.8.26 Gazelle Queue Limit Channels 4-7

(A_CR_GZLQ_LIMIT_CH4_7_MCHBAR)—Offset 6464h
Gazelle queue limit for channel ID 4 to 7.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: FFFFFFFFh

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CHID7

CHID6

CHID5

CHID4
Bit Default &
Field Name (ID): Description
Range Access

FFh Channel ID 7 (CHID7): Gazelle queue limit for Upstream NP on

31:24
RW channel ID 7.
FFh Channel ID 6 (CHID6): Gazelle queue limit for Upstream NP on
23:16
RW channel ID 6.
FFh Channel ID 5 (CHID5): Gazelle queue limit for Upstream NP on
15:8
RW channel ID 5.
FFh Channel ID 4 (CHID4): Gazelle queue limit for Upstream NP on
7:0
RW channel ID 4.

5.8.27 IOMMU Arbiter Grant Count VC0a Register

(A_CR_IOMMUARB_GCNT_VC0a_0_0_0_MCHBAR)—Offset
6468h
IOMMU arbiter grant count.

Access Method

334818 353
 MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

DEV_NP

DEV_P
RSVD

RSVD

RSVD
CLASS_CNT
Bit Default &
Field Name (ID): Description
Range Access

0h
31:22 Reserved.
RO

21:16
1h Class Count (CLASS_CNT): IOMMU arbiter class grant count.
RW

0h
15:14 Reserved.
RO

1h Device Non-posted (DEV_NP): IOMMU arbiter device grant

13:8
RW count for NP.
0h
7:6 Reserved.
RO

1h Device Posted (DEV_P): IOMMU arbiter device grant count for

5:0
RW p.

5.8.28 IOMMU Arbiter Grant Count VC0b Register

(A_CR_IOMMUARB_GCNT_VC0b_0_0_0_MCHBAR)—Offset
646Ch
IOMMU arbiter grant count.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
DEV_NP

DEV_P
RSVD

RSVD

RSVD
CLASS_CNT

354 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h
31:22 Reserved.
RO

21:16
1h Class Count (CLASS_CNT): IOMMU arbiter class grant count.
RW

0h
15:14 Reserved.
RO

1h Device Non-posted (DEV_NP): IOMMU arbiter device grant

13:8
RW count for NP.
0h
7:6 Reserved.
RO

1h Device Posted (DEV_P): IOMMU arbiter device grant count for

5:0
RW p.

5.8.29 IOMMU Arbiter Grant Count VC1b Register

(A_CR_IOMMUARB_GCNT_VC1b_0_0_0_MCHBAR)—Offset
6470h
IOMMU arbiter grant count.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 10101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

DEV_P
DEV_NP
RSVD

CLASS_CNT

RSVD

RSVD

Bit Default &

Field Name (ID): Description
Range Access

0h
31:22 Reserved.
RO

21:16
1h Class Count (CLASS_CNT): IOMMU arbiter class grant count.
RW

0h
15:14 Reserved.
RO

1h Device Non-posted (DEV_NP): IOMMU arbiter device grant

13:8
RW count for NP.
0h
7:6 Reserved.
RO

334818 355
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

1h Device Posted (DEV_P): IOMMU arbiter device grant count for

5:0
RW p.

5.8.30 Gazelle Queue Reserved Entries Channels 0-3

(A_CR_GZLQ_RSVD_CH0_3_MCHBAR)—Offset 6474h
Gazelle queue limit for channel ID 0 to 3.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 4040101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
CHID3

CHID2

CHID1

CHID0
Bit Default &
Field Name (ID): Description
Range Access

4h Channel ID 3 (CHID3): Gazelle queue limit for Upstream NP on

31:24
RW channel ID 3.
4h Channel ID 2 (CHID2): Gazelle queue limit for Upstream NP on
23:16
RW channel ID 2.
1h Channel ID 1 (CHID1): Gazelle queue limit for Upstream NP on
15:8
RW Channel ID 1.
1h Channel ID 0 (CHID0): Gazelle queue limit for Upstream NP on
7:0
RW Channel ID 0.

5.8.31 Gazelle Queue Reserved Entries Channels 4-7

(A_CR_GZLQ_RSVD_CH4_7_MCHBAR)—Offset 6478h
GazelleQ limit for CHID 0 to 3

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1010101h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

356 334818
MCHBAR

CHID7

CHID6

CHID5

CHID4
Bit Default &
Field Name (ID): Description
Range Access

1h Channel ID 7 (CHID7): Gazelle queue limit for Upstream NP on

31:24
RW channel ID 7.
1h Channel ID 6 (CHID6): Gazellequeue limit for Upstream NP on
23:16
RW channel ID 6.
1h Channel ID 5 (CHID5): Gazelle queue limit for Upstream NP on
15:8
RW channel ID 5.
1h Channel ID 4 (CHID4): Gazelle queue limit for Upstream NP on
7:0
RW channel ID 4.

5.8.32 Spare BIOS (A_CR_SPARE_BIOS_MCHBAR)—Offset 647Ch

Spare CR in MCHBAR.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPARE_RW

Bit Default &

Field Name (ID): Description
Range Access

0h SPARE RW Bits (SPARE_RW): Spare RW 32 bits in BIOSWR

31:0
RW policy group.

5.8.33 Upcmd Credit Maximum Channel 0

(A_CR_UPCMD_CRDTMAX_CH0_0_0_0_MCHBAR)—Offset
6490h
Upcmd Credit Max for PSF0 on Ch0 : Maximum number of credits exposed to PSF0.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

334818 357
 MCHBAR

Default: 4040Ch

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0

NP_MAX
RSVD

CMP_MAX

RSVD

RSVD

P_MAX
Bit Default &
Field Name (ID): Description
Range Access

0h
31:23 Reserved.
RO

4h Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for

22:16
RW Chid.
0h
15 Reserved.
RO

4h Non-Posted Max (NP_MAX): Max non-posted credits sent to

14:8
RW PSF0 for Chid.
0h
7 Reserved.
RO

6:0
Ch Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW

5.8.34 Upcmd Credit Maximum Channel 1

(A_CR_UPCMD_CRDTMAX_CH1_0_0_0_MCHBAR)—Offset
6494h
Upcmd Credit Max for PSF0 on Ch1 : Maximum number of credits exposed to PSF0.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 40404h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
RSVD

CMP_MAX

RSVD

NP_MAX

RSVD

P_MAX

Bit Default &

Field Name (ID): Description
Range Access

0h
31:23 Reserved.
RO

358 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

4h Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for

22:16
RW Chid.
0h
15 Reserved.
RO

4h Non-Posted Max (NP_MAX): Max non-posted credits sent to

14:8
RW PSF0 for Chid.
0h
7 Reserved.
RO

6:0
4h Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW

5.8.35 Upcmd Credit Maximum Channel 2

(A_CR_UPCMD_CRDTMAX_CH2_0_0_0_MCHBAR)—Offset
6498h
Upcmd Credit Max for PSF0 on Ch2 : Maximum number of credits exposed to PSF0.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 7F00h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
RSVD

CMP_MAX

RSVD

NP_MAX

RSVD

P_MAX

Bit Default &

Field Name (ID): Description
Range Access

0h
31:23 Reserved.
RO

0h Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for

22:16
RW Chid.
0h
15 Reserved.
RO

7Fh Non-Posted Max (NP_MAX): Max non-posted credits sent to

14:8
RW PSF0 for Chid.
0h
7 Reserved.
RO

6:0
0h Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW

334818 359
 MCHBAR

5.8.36 Upcmd Credit Maximum Channel 3

(A_CR_UPCMD_CRDTMAX_CH3_0_0_0_MCHBAR)—Offset
649Ch
Upcmd Credit Max for PSF0 on Ch3 : Maximum number of credits exposed to PSF0.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 7F7Fh

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1

NP_MAX
RSVD

CMP_MAX

RSVD

RSVD

P_MAX
Bit Default &
Field Name (ID): Description
Range Access

0h
31:23 Reserved.
RO

0h Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for

22:16
RW Chid.
0h
15 Reserved.
RO

7Fh Non-Posted Max (NP_MAX): Max non-posted credits sent to

14:8
RW PSF0 for Chid.
0h
7 Reserved.
RO

6:0
7Fh Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW

5.8.37 Upcmd Credit Maximum Channel 4

(A_CR_UPCMD_CRDTMAX_CH4_0_0_0_MCHBAR)—Offset
64A0h
Upcmd Credit Max for PSF0 on Ch4 : Maximum number of credits exposed to PSF0.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 400h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

360 334818
MCHBAR

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

NP_MAX
RSVD

CMP_MAX

RSVD

RSVD

P_MAX
Bit Default &
Field Name (ID): Description
Range Access

0h
31:23 Reserved.
RO

0h Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for

22:16
RW Chid.
0h
15 Reserved.
RO

4h Non-Posted Max (NP_MAX): Max non-posted credits sent to

14:8
RW PSF0 for Chid.
0h
7 Reserved.
RO

6:0
0h Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW

5.8.38 Upcmd Credit Maximum Channel 5

(A_CR_UPCMD_CRDTMAX_CH5_0_0_0_MCHBAR)—Offset
64A4h
Upcmd Credit Max for PSF0 on Ch5 : Maximum number of credits exposed to PSF0.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 404h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
RSVD

CMP_MAX

RSVD

RSVD

P_MAX
NP_MAX

Bit Default &

Field Name (ID): Description
Range Access

0h
31:23 Reserved.
RO

0h Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for

22:16
RW Chid.
0h
15 Reserved.
RO

334818 361
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

4h Non-Posted Max (NP_MAX): Max non-posted credits sent to

14:8
RW PSF0 for Chid.
0h
7 Reserved.
RO

6:0
4h Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW

5.8.39 Upcmd Credit Maximum Channel 6

(A_CR_UPCMD_CRDTMAX_CH6_0_0_0_MCHBAR)—Offset
64A8h
Upcmd Credit Max for PSF0 on Ch6 : Maximum number of credits exposed to PSF0.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 404h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
RSVD

CMP_MAX

RSVD

NP_MAX

RSVD

P_MAX
Bit Default &
Field Name (ID): Description
Range Access

0h
31:23 Reserved.
RO

0h Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for

22:16
RW Chid.
0h
15 Reserved.
RO

4h Non-Posted Max (NP_MAX): Max non-posted credits sent to

14:8
RW PSF0 for Chid.
0h
7 Reserved.
RO

6:0
4h Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW

5.8.40 Upcmd Credit Maximum Channel 7

(A_CR_UPCMD_CRDTMAX_CH7_0_0_0_MCHBAR)—Offset
64ACh
Upcmd Credit Max for PSF0 on Ch7 : Maximum number of credits exposed to PSF0.

362 334818
MCHBAR

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 40Ch

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0
RSVD

CMP_MAX

RSVD

NP_MAX

RSVD

P_MAX
Bit Default &
Field Name (ID): Description
Range Access

0h
31:23 Reserved.
RO

0h Completion Max (CMP_MAX): Max Cmp credits sent to PSF0 for

22:16
RW Chid.
0h
15 Reserved.
RO

4h Non-Posted Max (NP_MAX): Max non-posted credits sent to

14:8
RW PSF0 for Chid.
0h
7 Reserved.
RO

6:0
Ch Posted Max (P_MAX): Max posted credits sent to PSF0 for Chid.
RW

5.8.41 MOT OUT Base Register

(A_CR_MOT_OUT_BASE_0_0_0_MCHBAR)—Offset 64C0h
This register contains the value of the start address of the MOT debug data region. The
smallest reserved region for MOT debug data (if enabled) is 16MB. MOT region must be
power-of-two sized and naturally

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

334818 363
 MCHBAR

MOT_OUT_BASE
IMR_EN
TR_EN
RSVD

RSVD
Bit Default &
Field Name (ID): Description
Range Access

IMR enable (IMR_EN): IMR Enable: Enables access checking for

0h the MOT region. Note: this does not enable MOT itself merely
31
RW enables access control checks for transactions that attempt to
access the MOT buffer.
Trace Enable (TR_EN): Asset Classification (AC)[0]: Trace
0h Enable: Enables snooping of transactions to the IMR region by
30
RO tracing agents such as MOT. Reserved and set to 0 for the MOT
region, since otherwise this would enable recursive
0h
29 Reserved.
RO

MOT_OUT_BASE address (MOT_OUT_BASE): Specifies bits

38:24 of the start address of the MOT memory region. Region size
0h must be a strict poweroftwo at least 16MB and naturally aligned to
28:14
RW the size. These bits are compared with the result of the
MOT_OUT_MASK[28:14] applied to bits 38:24 of the incoming
address to determine if an access falls within the MOT region.
0h
13:0 Reserved.
RO

5.8.42 MOT OUT Mask Register

(A_CR_MOT_OUT_MASK_0_0_0_MCHBAR)—Offset 64C4h
This register specifies the size of the MOT region. If a request address [39:24] AND-ed
with MOT_OUT_MASK[15:0] matches the MOT_OUT_BASE[15:0], then the request falls
within the MOT_OUT region

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GT_IWB_EN
IA_IWB_EN

MOT_OUT_MASK
RSVD

RSVD

364 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

GT Implicit Writeback Enable (GT_IWB_EN): Asset

Classification AC[2]: GT Implicit WB Enable: Enables implicit
writebacks to protected region from GT caching agent. When set
0h to 1 enables implicit writeback data HITM data from GT to be
31
RW returned to the requester. When set to 0 inhibits HITM data from
GT from being returned to the requester. HITM data from IA cores
may be returned to the requester depending on the setting of the
IA_IWB_EN bit.
IA Implicit Writeback Enable (IA_IWB_EN): Asset
Classification AC[1]: IA Implicit WB Enable: Enables implicit
writebacks to protected region from IA caching agent. When set to
0h 1 enables implicit writeback data HITM data from IA cores to be
30
RW returned to the requester. When set to 0 inhibits HITM data from
IA cores from being returned to the requester. HITM data from GT
may be returned to the requester depending on the setting of the
GT_IWB_EN bit.
0h
29 Reserved.
RO

MOT OUT Mask (MOT_OUT_MASK): Specifies the size of the

0h MOT region. If Request Address [38:24] ANDed with
28:14
RW MOT_OUT_MASK[28:14] matches the MOT_OUT_BASE[28:14]
then the request falls within the MOT_OUT region
0h
13:0 Reserved.
RO

5.8.43 CHAP Select 1 (A_CR_CHAP_SLCT1_MCHBAR)—Offset

6500h
Chap event select register 1.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CHID_Y_CNT_UPTXN

CHID_X_CNT_UPTXN
RSVD

RSVD

334818 365
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h
31:24 Reserved.
RO

0h Channel ID Y Count Upstream txn (CHID_Y_CNT_UPTXN):

23:16
RW Count upstream txn on all VCs where CHID_Y[i]=1.
0h
15:8 Reserved.
RO

0h Channel ID X Count Upstream txn (CHID_X_CNT_UPTXN):

7:0
RW Count upstream txn on all VCs where CHID_X[i]=1.

5.8.44 CHAP Select 2 (A_CR_CHAP_SLCT2_MCHBAR)—Offset

6504h
Chap event select register 2.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CHID_Y_CNT_DNTXN

CHID_X_CNT_DNTXN
RSVD

RSVD

Bit Default &

Field Name (ID): Description
Range Access

0h
31:24 Reserved.
RO

Channel ID Y Count Downstream txn

0h
23:16 (CHID_Y_CNT_DNTXN): Count downstream txn on all VCs
RW
where CHID_Y[i]=1.
0h
15:8 Reserved.
RO

Channel ID X Count Downstream txn

0h
7:0 (CHID_X_CNT_DNTXN): Count downstream txn on all VCs
RW
where CHID_X[i]=1.

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5.8.45 CHAP Select 3 (A_CR_CHAP_SLCT3_MCHBAR)—Offset

6508h
Chap event select register 3.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 4h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

RSVD

Q_OCCUPANCY_Y

Q_OCCUPANCY_X
Bit Default &
Field Name (ID): Description
Range Access

0h
31:4 Reserved.
RO

Q Occupancy Y (Q_OCCUPANCY_Y): Count occupancy/residency of certain Q in A-

Unit
• 00: UpCmd
1h
3:2 • 01: UpData
RW
• 10: GzlQ
• 11: DnCmd/Data
Q Occupancy X (Q_OCCUPANCY_X): Count occupancy/residency of certain Q in A-
Unit
• 00: UpCmd
0h
1:0 • 01: UpData
RW
• 10: GzlQ
• 11: DnCmd/Data

5.8.46 Slice and Channel Hash

(A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR)—Offset
65C0h
A-Unit slice and channel hash function.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

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Default: 3C00000000h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000011110000000000000000000000000000000000

SYM_SLICE1_CHANNEL_ENABLED
SYM_SLICE0_CHANNEL_ENABLED

ENABLE_PMI_DUAL_DATA_MODE
CH_1_DISABLED

SLICE_0_MEM_DISABLED
INTERLEAVE_MODE
HVM_MODE
SLICE_1_DISABLED
RSVD

CH_HASH_MASK

RSVD

RSVD

RSVD
LOCK

SLICE_HASH_MASK
Bit Default &
Field Name (ID): Description
Range Access

Lock (LOCK): Intended usage is for BIOS to set the LOCK when it
0h
63 updates the CR. A-Unit implements only storage for this bit. No
RW
hardware exists to implement hardware locking.
0h
62:52 Reserved.
RO

Channel Hash Mask (CH_HASH_MASK): When both PMI

channels in a slice are enabled, this field specifies the Channel
Hash Mask to be applied on Addr[19:6] postremap DRAM address
of the request to compute which PMI channel a request must be
0h routed to. Relevant only when HVM mode is disabled and only for
51:38
RW requests that do not fall under the MOT region. B-Unit will
override the programmed value to include the Channel Selector bit
See SLICEHASH.INTERLEAVE_MODE field. Note that HVM mode
and MOT regions have special hash requirements and hence they
do not use the CH_HASH_MASK.
Channel Enabled for Slice 1
(SYM_SLICE1_CHANNEL_ENABLED): Specifies which channel
3h
37:36 is enabled for Slice 1, This is for those cases where Channel 0 or 1
RW
could be disabled for Slice 1 If both bits are set then channel
select will be based on the Channel Select logic
Channel Enabled for Slice 0
(SYM_SLICE0_CHANNEL_ENABLED): Specifies which channel
3h
35:34 is enabled for Slice 0, This is for those cases where Channel 0 or 1
RW
could be disabled for Slice 0 If both bits are set then channel
select will be based on the Channel Select logic
0h
33 Reserved.
RO

Channel 1 Disabled (CH_1_DISABLED): Channel 1 in both

0h
32 slices are disabled no memory address mapped to ch 1. All
RW
requests sent to channel 0.

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Bit Default &

Field Name (ID): Description
Range Access

Enable PMI Dual Data Mode

0h
31 (ENABLE_PMI_DUAL_DATA_MODE): When set to 1, Single
RW
Command Interface and Dual Data Interface for Reads and Writes
0h
30:20 Reserved.
RO

Slice Hash Mask (SLICE_HASH_MASK): When both slices are

enabled this field specifies the Slice Hash Mask to be applied on
Addr[19:6] physical address of the request to compute which slice
a request must be routed to. Relevant only when HVM mode is
disabled and only for physical addresses that do not fall under the
0h
19:6 Asymmetric Memory Region and the MOT region. B-Unit will
RW
override the programmed value to include the Slice Selector bit
See INTERLEAVE_MODE field. Note that HVM mode nonaddress
IDI requests asymmetric memory region and MOT regions have
special hash requirements and hence they do not use the
SLICE_HASH_MASK.
0h
5 Reserved.
RO

Slice 0 Mem Disabled (SLICE_0_MEM_DISABLED): Slice 0 is

0h
4 disabled for memory accesses; no memory address mapped to
RW
Slice 0 and all memory requests sent to Slice 1.
Interleave Mode (INTERLEAVE_MODE): Default interleave mode that specifies
how the Slice Selector and Channel Selector bits are to be determined. Relevant only
when HVM mode is disabled and only for system memory addresses that do not fall
under the MOT region or the Asymmetric memory region in the System Address Map.
Legal encodings are 0x0 0x1 and 0x2. An encoding of 0x3 is treated as if it was 0x2.
When both slices and all four PMI channels are enabled:
• 0h: Default Slice Selector is Addr[10] and Default Channel
Selector is Addr[11]
• 1h: Default Slice Selector is Addr[11] and Default Channel
Selector is Addr[12]
• 2h: Default Slice Selector is Addr[12] and Default Channel
Selector is Addr[13]
0h When both slices are enabled but only one channel in each slice enabled:
3:2
RW
• 0h: Default Slice Selector is Addr[10]
• 1h: Default Slice Selector is Addr[11]
• 2h: Default Slice Selector is Addr[12]
When only SLICE0 is enabled and both channels on that slice are enabled:
• 0h: Default Channel Selector is Addr[10]
• 1h: Default Channel Selector is Addr[11]
• 2h: Default Channel Selector is Addr[12]
When SLICE0 and only one channel in that slice is enabled this field is not relevant.
B-Unit overrides the setting of the SLICE_HASH_MASK to always include the Slice
Selector bit. Similarly, B-Unit overrides the setting of the CH_HASH_MASK to always
include the Channel Selector bit.

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Bit Default &

Field Name (ID): Description
Range Access

HVM Mode (HVM_MODE):

• 0: HVM mode is disabled.
• 1: HVM mode is enabled.
When HVM mode is enabled, Slice Hash and Channel Hash is done as follows: Both
slices and all four PMI channels enabled:

0h • Slice Hash is Request Physical Addr[29]

1
RW • Channel Hash is PostRemap Addr[30]
Both slices enabled but only one PMI channel in each slice enabled:
• Slice Hash is Request Physical Addr[29]
Only one SLICE0 enabled but both PMI channels in SLICE0 enabled:
• Channel Hash is PostRemap Addr[29]
When HVM_MODE is enabled TOLUD must be set at 2GB.

0h Slice 1 Disabled (SLICE_1_DISABLED): Slice 1 is disabled; no

0
RW memory address mapped to Slice 1. All request sent to Slice 0.

5.8.47 Mirror Range Register

(A_CR_MIRROR_RANGE_0_0_0_MCHBAR)—Offset 65C8h
Mirror Range: This register defines base and limit of the 8M aligned region in memory
that captures the mirror writes. Since b[22:0] are assumed to be 0's the smallest size
of the region is 8M

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
MIRROR_LIMIT

MIRROR_BASE
RSVD

RSVD

Bit Default &

Field Name (ID): Description
Range Access

0h
63:48 Reserved.
RO

0h Mirror Limit Address (MIRROR_LIMIT): Mirror Limit: specifies

47:32
RW b38:b23 of HPA indicating the end of mirror packet buffer region
0h
31:16 Reserved.
RO

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Bit Default &

Field Name (ID): Description
Range Access

0h Mirror_Base Address (MIRROR_BASE): Mirror Base: specifies

15:0
RW b38:b23 of HPA indicating the start of mirror packet buffer region

5.8.48 ASYM MEM REGION 0 CONFIGURATION WITH NO

INTERLEAVING
(A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR)—Offset
65D0h
Specification of asymmetric memory region 0 (in slice 0) for the configuration with 2
asymmetric memory regions.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SLICE0_ASYM_ENABLE

SLICE0_ASYM_LIMIT

RSVD

RSVD
SLICE0_ASYM_CHANNEL_SELECT

SLICE0_ASYM_BASE

Bit Default &

Field Name (ID): Description
Range Access

Enable Asymmetric Region in Slice 0, With No Interleaving

0h
31 (SLICE0_ASYM_ENABLE): Setting this bit to 0 disables
RW
asymmetric memory region 0; setting it to 1 enables the region.
Channel Select for ASYM Region Slice 0
0h
30 (SLICE0_ASYM_CHANNEL_SELECT): Specifies which Channel
RW
in ASYM Slice 0 request is sent
Limit Address for Asymmetric Memory Region, Slice 0, With
No Interleaving (SLICE0_ASYM_LIMIT): Specifies bits
0h
29:19 [38:31] of the highest address of asymmetric memory region 0 (in
RW
slice 0); all the lower bits of the region's highest address are equal
to 1.
0h
18:15 Reserved.
RO

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Bit Default &

Field Name (ID): Description
Range Access

Base Address for Asymmetric Memory Region, Slice 0, With

0h No Interleaving (SLICE0_ASYM_BASE): Specifies bits [38:31]
14:4
RW of the base address of asymmetric memory region 0 (in slice 0);
all the lower bits of the region's base address are equal to 0.
0h
3:0 Reserved.
RO

5.8.49 ASYM MEM REGION 1 CONFIGURATION WITH NO

INTERLEAVING
(A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR)—Offset
65D4h
Specification of asymmetric memory region 1 (in slice 1) for the configuration with 2
asymmetric memory regions.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SLICE1_ASYM_CHANNEL_SELECT

SLICE1_ASYM_LIMIT

RSVD

SLICE1_ASYM_BASE

RSVD
SLICE1_ASYM_ENABLE

Bit Default &

Field Name (ID): Description
Range Access

Enable Asymmetric Region in Slice 1, With No Interleaving

0h
31 (SLICE1_ASYM_ENABLE): Setting this bit to 0 disables
RW
asymmetric memory region 1; setting it to 1 enables the region.
Channel Select for ASYM SLICE 1
0h
30 (SLICE1_ASYM_CHANNEL_SELECT): Specifies Channel for
RW
ASYM Region Slice 1

372 334818
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Bit Default &

Field Name (ID): Description
Range Access

Limit Address for Asymmetric Memory Region, Slice 1, With

No Interleaving (SLICE1_ASYM_LIMIT): Specifies bits
0h
29:19 [38:31] of the highest address of asymmetric memory region 1 (in
RW
slice 1); all the lower bits of the region's highest address are equal
to 1.
0h
18:15 Reserved.
RO

Limit Address for Asymmetric Memory Region, Slice 1, With

0h No Interleaving (SLICE1_ASYM_BASE): Specifies bits [38:31]
14:4
RW of the base address of asymmetric memory region 1 (in slice 1);
all the lower bits of the region's base address are equal to 0.
0h
3:0 Reserved.
RO

5.8.50 Two-Way Asymmetric Memory Region Configuration

(A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR)—
Offset 65D8h
Specification of asymmetric memory region 1 (in slice 1) for the configuration with 2
asymmetric memory regions.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ASYM_2WAY_INTLV_MODE
ASYM_2WAY_INTERLEAVE_ENABLE

ASYM_2WAY_LIMIT
RSVD

RSVD

ASYM_2WAY_BASE

RSVD

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Bit Default &

Field Name (ID): Description
Range Access

Enable Two-Way Asymmetric Memory Configuration

0h (ASYM_2WAY_INTERLEAVE_ENABLE): Setting this bit to 0
31
RW disables Interleave Asymmetric memory region 1, setting it to 1
enables the region.
0h
30:28 Reserved.
RO

Limit Address for Two-Way Asymmetric Memory Region

0h (ASYM_2WAY_LIMIT): Specifies bits [38:28] of the highest
27:17
RW address of Interleave Asymmetric Region, all the lower bits of the
region's highest address are equal to 1.
0h
16:15 Reserved.
RO

Base Address for Two-Way Asymmetric Memory Region

0h (ASYM_2WAY_BASE): Specifies bits [38:28] of the base
14:4
RW address of Interleave Asymmetric Region; all the lower bits of the
region's base address are equal to 0.
0h
3:2 Reserved.
RO

Two-Way Asymmetric Interleave Mode

(ASYM_2WAY_INTLV_MODE): Going with 2 bits here. 2'b00 :
Asymmetric memory Split between Channel 0 of Slice 0 and Slice
0h
1:0 1 2'b01 : Asymmetric memory split between Channel 1 of Slice 0
RW
and Slice 1 2'b10 : Asymmetric memory split between Channel 0
and Channel 1 of Slice 0 2'b11 : Asymmetric memory split
between Channel 0 and Channel 1 of Slice 1

5.9 Registers Summary

Table 5-9. Summary of pcs_regs_wrapper Registers
Offset Offset
Register Name (ID)—Offset Default Value
Start End

B-Unit Miscellaneous Configuration

6800h 6803h 7h
(B_CR_BMISC_0_0_0_MCHBAR)—Offset 6800h

Slice 0 Memory Access Count

6808h 680Fh 0h
(B_CR_MEM_ACCESS_COUNT_SLICE0)—Offset 6868h

Slice 0 Memory Access Count

6810h 6817h C0061010202h
(B_CR_MEM_ACCESS_COUNT_SLICE0)—Offset 6868h

Slice 0 Memory Access Count

6818h 681Fh C0061010202h
(B_CR_MEM_ACCESS_COUNT_SLICE0)—Offset 6868h

Slice 0 Memory Access Count

6868h 686Bh 0h
(B_CR_MEM_ACCESS_COUNT_SLICE0)—Offset 6868h

Slice 1 Memory Access Count

686Ch 686Fh 0h
(B_CR_MEM_ACCESS_COUNT_SLICE1)—Offset 686Ch

IMR0 Mask (B_CR_BIMR0MASK_0_0_0_MCHBAR)—Offset

6870h 6873h 0h
6874h

IMR0 Mask (B_CR_BIMR0MASK_0_0_0_MCHBAR)—Offset

6874h 6877h 0h
6874h

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Table 5-9. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

IMR0 Control Policy (B_CR_BIMR0CP_0_0_0_MCHBAR)—

6878h 687Fh C0061010202h
Offset 6878h

IMR0 Read Access Policy

6880h 6887h 0h
(B_CR_BIMR0RAC_0_0_0_MCHBAR)—Offset 6880h

IMR0 Write Access Policy

6888h 688Fh 0h
(B_CR_BIMR0WAC_0_0_0_MCHBAR)—Offset 6888h

IMR1 Base (B_CR_BIMR1BASE_0_0_0_MCHBAR)—Offset

6890h 6893h 0h
6890h

IMR1 Mask (B_CR_BIMR1MASK_0_0_0_MCHBAR)—Offset

6894h 6897h 0h
6894h

IMR1 Control Policy (B_CR_BIMR1CP_0_0_0_MCHBAR)—

6898h 689Fh C0061010202h
Offset 6898h

IMR1 Read Access Policy

68A0h 68A7h 0h
(B_CR_BIMR1RAC_0_0_0_MCHBAR)—Offset 68A0h

IMR1 Write Access Policy

68A8h 68AFh 0h
(B_CR_BIMR1WAC_0_0_0_MCHBAR)—Offset 68A8h

Base 0 IMR2 Base (B_CR_BIMR2BASE_0_0_0_MCHBAR)—

68B0h 68B3h 0h
Offset 68B0h

IMR2 Mask (B_CR_BIMR2MASK_0_0_0_MCHBAR)—Offset

68B4h 68B7h 0h
68B4h

IMR2 Control Policy (B_CR_BIMR2CP_0_0_0_MCHBAR)—

68B8h 68BFh C0061010202h
Offset 68B8h

IMR2 Read Access Policy

68C0h 68C7h 0h
(B_CR_BIMR2RAC_0_0_0_MCHBAR)—Offset 68C0h

IMR2 Write Access Policy

68C8h 68CFh 0h
(B_CR_BIMR2WAC_0_0_0_MCHBAR)—Offset 68C8h

IMR3 Base (B_CR_BIMR3BASE_0_0_0_MCHBAR)—Offset

68D0h 68D3h 0h
68D0h

IMR3 Mask (B_CR_BIMR3MASK_0_0_0_MCHBAR)—Offset

68D4h 68D7h 0h
68D4h

IMR3 Control Policy (B_CR_BIMR3CP_0_0_0_MCHBAR)—

68D8h 68DFh C0061010202h
Offset 68D8h

IMR3 Read Access Policy

68E0h 68E7h 0h
(B_CR_BIMR3RAC_0_0_0_MCHBAR)—Offset 68E0h

IMR3 Write Access Policy

68E8h 68EFh 0h
(B_CR_BIMR3WAC_0_0_0_MCHBAR)—Offset 68E8h

IMR4 Base (B_CR_BIMR4BASE_0_0_0_MCHBAR)—Offset

68F0h 68F3h 0h
68F0h

IMR4 Mask (B_CR_BIMR4MASK_0_0_0_MCHBAR)—Offset

68F4h 68F7h 0h
68F4h

B-Unit IMR4 Control Policy

68F8h 68FFh C0061010202h
(B_CR_BIMR4CP_0_0_0_MCHBAR)—Offset 68F8h

IMR4 Read Access Policy

6900h 6907h 0h
(B_CR_BIMR4RAC_0_0_0_MCHBAR)—Offset 6900h

IMR4 Write Access Policy

6908h 690Fh 0h
(B_CR_BIMR4WAC_0_0_0_MCHBAR)—Offset 6908h

IMR5 Base (B_CR_BIMR5BASE_0_0_0_MCHBAR)—Offset

6910h 6913h 0h
6910h

IMR5 Mask (B_CR_BIMR5MASK_0_0_0_MCHBAR)—Offset

6914h 6917h 0h
6914h

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Table 5-9. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

IMR5 Control Policy (B_CR_BIMR5CP_0_0_0_MCHBAR)—

6918h 691Fh C0061010202h
Offset 6918h

IMR5 Read Access Policy

6920h 6927h 0h
(B_CR_BIMR5RAC_0_0_0_MCHBAR)—Offset 6920h

IMR5 Write Access Policy

6928h 692Fh 0h
(B_CR_BIMR5WAC_0_0_0_MCHBAR)—Offset 6928h

IMR6 Base (B_CR_BIMR6BASE_0_0_0_MCHBAR)—Offset

6930h 6933h 0h
6930h

IMR6 Mask (B_CR_BIMR6MASK_0_0_0_MCHBAR)—Offset

6934h 6937h 0h
6934h

IMR6 Control Policy (B_CR_BIMR6CP_0_0_0_MCHBAR)—

6938h 693Fh C0061010202h
Offset 6938h

IMR6 Read Access Policy

6940h 6947h 0h
(B_CR_BIMR6RAC_0_0_0_MCHBAR)—Offset 6940h

IMR6 Write Access Policy

6948h 694Fh 0h
(B_CR_BIMR6WAC_0_0_0_MCHBAR)—Offset 6948h

IMR7 Base (B_CR_BIMR7BASE_0_0_0_MCHBAR)—Offset

6950h 6953h 0h
6950h

IMR7 Mask (B_CR_BIMR7MASK_0_0_0_MCHBAR)—Offset

6954h 6957h 0h
6954h

IMR7 Control Policy (B_CR_BIMR7CP_0_0_0_MCHBAR)—

6958h 695Fh C0061010202h
Offset 6958h

IMR7 Read Access Policy

6960h 6967h 0h
(B_CR_BIMR7RAC_0_0_0_MCHBAR)—Offset 6960h

IMR7 Write Access Policy

6968h 696Fh 0h
(B_CR_BIMR7WAC_0_0_0_MCHBAR)—Offset 6968h

IMR8 Base (B_CR_BIMR8BASE_0_0_0_MCHBAR)—Offset

6970h 6973h 0h
6970h

IMR8 Mask (B_CR_BIMR8MASK_0_0_0_MCHBAR)—Offset

6974h 6977h 0h
6974h

IMR8 Control Policy (B_CR_BIMR8CP_0_0_0_MCHBAR)—

6978h 697Fh C0061010202h
Offset 6978h

IMR8 Read Access Policy

6980h 6987h 0h
(B_CR_BIMR8RAC_0_0_0_MCHBAR)—Offset 6980h

IMR8 Write Access Policy

6988h 698Fh 0h
(B_CR_BIMR8WAC_0_0_0_MCHBAR)—Offset 6988h

IMR9 Base (B_CR_BIMR9BASE_0_0_0_MCHBAR)—Offset

6990h 6993h 0h
6990h

IMR9 Mask (B_CR_BIMR9MASK_0_0_0_MCHBAR)—Offset

6994h 6997h 0h
6994h

IMR9 Control Policy (B_CR_BIMR9CP_0_0_0_MCHBAR)—

6998h 699Fh C0061010202h
Offset 6998h

IMR9 Read Access Policy

69A0h 69A7h 0h
(B_CR_BIMR9RAC_0_0_0_MCHBAR)—Offset 69A0h

IMR9 Write Access Policy

69A8h 69AFh 0h
(B_CR_BIMR9WAC_0_0_0_MCHBAR)—Offset 69A8h

IMR10 Base (B_CR_BIMR10BASE_0_0_0_MCHBAR)—Offset

69B0h 69B3h 0h
69B0h

IMR10 Mask (B_CR_BIMR10MASK_0_0_0_MCHBAR)—Offset

69B4h 69B7h 0h
69B4h

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Table 5-9. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

IMR10 Control Policy (B_CR_BIMR10CP_0_0_0_MCHBAR)—

69B8h 69BFh C0061010202h
Offset 69B8h

IMR10 Read Access Policy

69C0h 69C7h 0h
(B_CR_BIMR10RAC_0_0_0_MCHBAR)—Offset 69C0h

IMR10 Write Access Policy

69C8h 69CFh 0h
(B_CR_BIMR10WAC_0_0_0_MCHBAR)—Offset 69C8h

IMR11 Base (B_CR_BIMR11BASE_0_0_0_MCHBAR)—Offset

69D0h 69D3h 0h
69D0h

IMR11 Mask (B_CR_BIMR11MASK_0_0_0_MCHBAR)—Offset

69D4h 69D7h 0h
69D4h

IMR11 Control Policy (B_CR_BIMR11CP_0_0_0_MCHBAR)—

69D8h 69DFh C0061010202h
Offset 69D8h

IMR11 Read Access Policy

69E0h 69E7h 0h
(B_CR_BIMR11RAC_0_0_0_MCHBAR)—Offset 69E0h

IMR11 Write Access Policy

69E8h 69EFh 0h
(B_CR_BIMR11WAC_0_0_0_MCHBAR)—Offset 69E8h

IMR12 Base (B_CR_BIMR12BASE_0_0_0_MCHBAR)—Offset

69F0h 69F3h 0h
69F0h

IMR12 Mask (B_CR_BIMR12MASK_0_0_0_MCHBAR)—Offset

69F4h 69F7h 0h
69F4h

IMR12 Control Policy (B_CR_BIMR12CP_0_0_0_MCHBAR)—

69F8h 69FFh C0061010202h
Offset 69F8h

IMR12 Read Access Policy

6A00h 6A07h 0h
(B_CR_BIMR12RAC_0_0_0_MCHBAR)—Offset 6A00h

IMR12 Write Access Policy

6A08h 6A0Fh 0h
(B_CR_BIMR12WAC_0_0_0_MCHBAR)—Offset 6A08h

IMR13 Base (B_CR_BIMR13BASE_0_0_0_MCHBAR)—Offset

6A10h 6A13h 0h
6A10h

IMR13 Mask (B_CR_BIMR13MASK_0_0_0_MCHBAR)—Offset

6A14h 6A17h 0h
6A14h

IMR13 Control Policy (B_CR_BIMR13CP_0_0_0_MCHBAR)—

6A18h 6A1Fh C0061010202h
Offset 6A18h

IMR13 Read Access Policy

6A20h 6A27h 0h
(B_CR_BIMR13RAC_0_0_0_MCHBAR)—Offset 6A20h

IMR13 Write Access Policy

6A28h 6A2Fh 0h
(B_CR_BIMR13WAC_0_0_0_MCHBAR)—Offset 6A28h

IMR14 Base (B_CR_BIMR14BASE_0_0_0_MCHBAR)—Offset

6A30h 6A33h 0h
6A30h

IMR14 Mask (B_CR_BIMR14MASK_0_0_0_MCHBAR)—Offset

6A34h 6A37h 0h
6A34h

IMR14 Control Policy (B_CR_BIMR14CP_0_0_0_MCHBAR)—

6A38h 6A3Fh C0061010202h
Offset 6A38h

IMR14 Read Access Policy

6A40h 6A47h 0h
(B_CR_BIMR14RAC_0_0_0_MCHBAR)—Offset 6A40h

IMR14 Write Access Policy

6A48h 6A4Fh 0h
(B_CR_BIMR14WAC_0_0_0_MCHBAR)—Offset 6A48h

IMR15 Base (B_CR_BIMR15BASE_0_0_0_MCHBAR)—Offset

6A50h 6A53h 0h
6A50h

IMR15 Mask (B_CR_BIMR15MASK_0_0_0_MCHBAR)—Offset

6A54h 6A57h 0h
6A54h

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Table 5-9. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

IMR15 Control Policy (B_CR_BIMR15CP_0_0_0_MCHBAR)—

6A58h 6A5Fh C0061010202h
Offset 6A58h

IMR15 Read Access Policy

6A60h 6A67h 0h
(B_CR_BIMR15RAC_0_0_0_MCHBAR)—Offset 6A60h

IMR15 Write Access Policy

6A68h 6A6Fh 0h
(B_CR_BIMR15WAC_0_0_0_MCHBAR)—Offset 6A68h

IMR16 Base (B_CR_BIMR16BASE_0_0_0_MCHBAR)—Offset

6A70h 6A73h 0h
6A70h

IMR16 Mask (B_CR_BIMR16MASK_0_0_0_MCHBAR)—Offset

6A74h 6A77h 0h
6A74h

IMR16 Control Policy (B_CR_BIMR16CP_0_0_0_MCHBAR)—

6A78h 6A7Fh C0061010202h
Offset 6A78h

IMR16 Read Access Policy

6A80h 6A87h 0h
(B_CR_BIMR16RAC_0_0_0_MCHBAR)—Offset 6A80h

IMR16 Write Access Policy

6A88h 6A8Fh 0h
(B_CR_BIMR16WAC_0_0_0_MCHBAR)—Offset 6A88h

IMR17 Base (B_CR_BIMR17BASE_0_0_0_MCHBAR)—Offset

6A90h 6A93h 0h
6A90h

IMR17 Mask (B_CR_BIMR17MASK_0_0_0_MCHBAR)—Offset

6A94h 6A97h 0h
6A94h

IMR17 Control Policy (B_CR_BIMR17CP_0_0_0_MCHBAR)—

6A98h 6A9Fh C0061010202h
Offset 6A98h

IMR17 Read Access Policy

6AA0h 6AA7h 0h
(B_CR_BIMR17RAC_0_0_0_MCHBAR)—Offset 6AA0h

IMR17 Write Access Policy

6AA8h 6AAFh 0h
(B_CR_BIMR17WAC_0_0_0_MCHBAR)—Offset 6AA8h

IMR18 Base (B_CR_BIMR18BASE_0_0_0_MCHBAR)—Offset

6AB0h 6AB3h 0h
6AB0h

IMR18 Mask (B_CR_BIMR18MASK_0_0_0_MCHBAR)—Offset

6AB4h 6AB7h 0h
6AB4h

IMR18 Control Policy (B_CR_BIMR18CP_0_0_0_MCHBAR)—

6AB8h 6ABFh C0061010202h
Offset 6AB8h

IMR18 Read Access Policy

6AC0h 6AC7h 0h
(B_CR_BIMR18RAC_0_0_0_MCHBAR)—Offset 6AC0h

IMR18 Write Access Policy

6AC8h 6ACFh 0h
(B_CR_BIMR18WAC_0_0_0_MCHBAR)—Offset 6AC8h

IMR19 Base (B_CR_BIMR19BASE_0_0_0_MCHBAR)—Offset

6AD0h 6AD3h 0h
6AD0h

IMR19 Mask (B_CR_BIMR19MASK_0_0_0_MCHBAR)—Offset

6AD4h 6AD7h 0h
6AD4h

IMR19 Control Policy (B_CR_BIMR19CP_0_0_0_MCHBAR)—

6AD8h 6ADFh C0061010202h
Offset 6AD8h

IMR19 Read Access Policy

6AE0h 6AE7h 0h
(B_CR_BIMR19RAC_0_0_0_MCHBAR)—Offset 6AE0h

IMR19 Write Access Policy

6AE8h 6AEFh 0h
(B_CR_BIMR19WAC_0_0_0_MCHBAR)—Offset 6AE8h

MOT Out Base (B_CR_MOT_OUT_BASE_0_0_0_MCHBAR)—

6AF0h 6AF3h 0h
Offset 6AF0h

MOT Out Mask (B_CR_MOT_OUT_MASK_0_0_0_MCHBAR)—

6AF4h 6AF7h 0h
Offset 6AF4h

378 334818
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Table 5-9. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

MOT Buffer Control Policy

6AF8h 6AFFh C0061010202h
(B_CR_BMOT_BUF_CP_0_0_0_MCHBAR)—Offset 6AF8h

MOT Buffer Read Access Policy

6B00h 6B07h 60010017h
(B_CR_BMOT_BUF_RAC_0_0_0_MCHBAR)—Offset 6B00h

MOT Buffer Write Access Policy

6B08h 6B0Fh 60010000h
(B_CR_BMOT_BUF_WAC_0_0_0_MCHBAR)—Offset 6B08h

IMR Global BM Control Policy

6B10h 6B17h C0061010202h
(B_CR_BIMRGLOBAL_BM_CP_0_0_0_MCHBAR)—Offset 6B10h

IMR Global BM Read Access Control

6B18h 6B1Fh (B_CR_BIMRGLOBAL_BM_RAC_0_0_0_MCHBAR)—Offset FFFFFFFFFFFFFFFFh
6B18h

IMR Global BM Write Access Policy

6B20h 6B27h (B_CR_BIMRGLOBAL_BM_WAC_0_0_0_MCHBAR)—Offset C0061010202h
6B20h

Graphics Stolen Memory Control Policy

6B28h 6B2Fh C0061010202h
(B_CR_BGSMCP_0_0_0_MCHBAR)—Offset 6B28h

GSM Read Access Policy (B_CR_BGSMRAC_0_0_0_MCHBAR)—

6B30h 6B37h 100060010100h
Offset 6B30h

GSM Write Access Policy

6B38h 6B3Fh 100060010100h
(B_CR_BGSMWAC_0_0_0_MCHBAR)—Offset 6B38h

TPM Control Policy (B_CR_TPM_CP_0_0_0_MCHBAR)—Offset

6B40h 6B47h C0061010202h
6B40h

TPM Access Control (B_CR_TPM_AC_0_0_0_MCHBAR)—Offset

6B48h 6B4Fh C0061010202h
6B48h

BGSM Control Register

6B50h 6B53h 19h
(B_CR_BGSM_CTRL_0_0_0_MCHBAR)—Offset 6B50h

SMM Control Register (B_CR_BSMR_CTRL_0_0_0_MCHBAR)—

6B54h 6B57h 7h
Offset 6B54h

Default VTd Control Register

6B58h 6B5Bh 1Ch
(B_CR_BDEFVTDPMR_CTRL_0_0_0_MCHBAR)—Offset 6B58h

MOT Trigger Trace Control

6B7Ch 6B7Fh (B_CR_MOT_TRIG_TRACE_CTRL_0_0_0_MCHBAR)—Offset E0000000h
6B7Ch

MOT Slice 0 Memory Pointer

6B80h 6B87h (B_CR_MOT_SLICE_0_MEM_PTR_0_0_0_MCHBAR)—Offset 2h
6B80h

MOT Slice 1 Memory Pointer

6B88h 6B8Fh (B_CR_MOT_SLICE_1_MEM_PTR_0_0_0_MCHBAR)—Offset 2h
6B88h

MOT Slice 0 Record ID

6B90h 6B93h (B_CR_MOT_SLICE_0_RECORD_ID_0_0_0_MCHBAR)—Offset 0h
6B90h

MOT Slice 1 Record ID

6B94h 6B97h (B_CR_MOT_SLICE_1_RECORD_ID_0_0_0_MCHBAR)—Offset 0h
6B94h

MOT Filter Match 0

6BA0h 6BA7h (B_CR_MOT_FILTER_MATCH0_0_0_0_MCHBAR)—Offset 0h
6BA0h

MOT Filter Mask

6BA8h 6BAFh 7FFFFFFFE0h
(B_CR_MOT_FILTER_MASK0_0_0_0_MCHBAR)—Offset 6BA8h

MOT Filter Match 1

6BB0h 6BB7h (B_CR_MOT_FILTER_MATCH1_0_0_0_MCHBAR)—Offset 0h
6BB0h

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Table 5-9. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

MOT Filter Mask 1

6BB8h 6BBFh 7FFFFFFFE0h
(B_CR_MOT_FILTER_MASK1_0_0_0_MCHBAR)—Offset 6BB8h

MOT Filter Misc 0

6BC0h 6BC7h 0h
(B_CR_MOT_FILTER_MISC0_0_0_0_MCHBAR)—Offset 6BC0h

MOT Filter Misc 1

6BC8h 6BCFh 0h
(B_CR_MOT_FILTER_MISC1_0_0_0_MCHBAR)—Offset 6BC8h

MOT Trigger Match 0

6BD0h 6BD7h (B_CR_MOT_TRIGGER_MATCH0_0_0_0_MCHBAR)—Offset 0h
6BD0h

MOT Trigger Mask 0

6BD8h 6BDFh (B_CR_MOT_TRIGGER_MASK0_0_0_0_MCHBAR)—Offset 7FFFFFFFE0h
6BD8h

MOT Trigger Match 1

6BE0h 6BE7h (B_CR_MOT_TRIGGER_MATCH1_0_0_0_MCHBAR)—Offset 0h
6BE0h

MOT Trigger Mask 1

6BE8h 6BEFh (B_CR_MOT_TRIGGER_MASK1_0_0_0_MCHBAR)—Offset 7FFFFFFFE0h
6BE8h

MOT Trigger Misc 0

6BF0h 6BF7h (B_CR_MOT_TRIGGER_MISC0_0_0_0_MCHBAR)—Offset 0h
6BF0h

MOT Trigger Misc 1

6BF8h 6BFFh (B_CR_MOT_TRIGGER_MISC1_0_0_0_MCHBAR)—Offset 0h
6BF8h

BIOSWR Control Policy

6C08h 6C0Fh C0061010202h
(B_CR_BIOSWR_CP_0_0_0_MCHBAR)—Offset 6C08h

BIOSWR Read Access Policy

6C10h 6C17h 80000C00630D0217h
(B_CR_BIOSWR_RAC_0_0_0_MCHBAR)—Offset 6C10h

BIOSWR Write Access Policy

6C18h 6C1Fh C00610C0212h
(B_CR_BIOSWR_WAC_0_0_0_MCHBAR)—Offset 6C18h

TPM Selector (B_CR_TPM_SELECTOR_0_0_0_MCHBAR)—

6C24h 6C27h 0h
Offset 6C24h

B-Unit Pcode/Ucode Write, All Read Control Policy Register

6C28h 6C2Fh (B_CR_P_U_CODEWR_ALLRD_CP_0_0_0_MCHBAR)—Offset 40001000202h
6C28h

B-Unit Pcode/Ucode Read Access Policy

6C30h 6C37h (B_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCHBAR)—Offset FFFFFFFFFFFFFFFFh
6C30h

B-Unit Pcode/Ucode Write Access Policy

6C38h 6C3Fh (B_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_MCHBAR)—Offset 40001000202h
6C38h

Default VTd BAR (B_CR_DEFVTDBAR_0_0_0_MCHBAR)—

6C80h 6C87h 0h
Offset 6C80h

Gfx VTd BAR (B_CR_GFXVTDBAR_0_0_0_MCHBAR)—Offset

6C88h 6C8Fh 0h
6C88h

B-Unit Lites Group 0 Control

6C90h 6C93h 0h
(B_CR_LITES0_CTL_0_0_0_MCHBAR)—Offset 6C90h

B-Unit Lites Group 0 Opcode Match Filter

6C94h 6C97h (B_CR_LITES0_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 0h
6C94h

B-Unit Lites Group 0 Agent Match Filter

6C98h 6C9Bh (B_CR_LITES0_AGENT_MATCH_0_0_0_MCHBAR)—Offset 0h
6C98h

380 334818
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Table 5-9. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

B-Unit Lites Group 0 U2C IntData Match Filter

6C9Ch 6C9Fh (B_CR_LITES0_U2CINTDATA_MATCH_0_0_0_MCHBAR)— 0h
Offset 6C9Ch

B-Unit Lites Group 0 Address Match Filter

LITES0_ADDR_MATCH
6CA0h 6CA7h 0h
(B_CR_LITES0_ADDR_MATCH_0_0_0_MCHBAR)—Offset
6CA0h

B-Unit Lites Group 0 Address Mask Filter LITES0_ADDR_MASK

6CA8h 6CAFh 0h
(B_CR_LITES0_ADDR_MASK_0_0_0_MCHBAR)—Offset 6CA8h

B-Unit Lites Group 0 Data Match Filter LITES0_DATA_MATCH

6CB0h 6CB3h (B_CR_LITES0_DATA_MATCH_0_0_0_MCHBAR)—Offset 0h
6CB0h

B-Unit Lites Group 0 Data Mask Filter LITES0_DATA_MASK

6CB4h 6CB7h 0h
(B_CR_LITES0_DATA_MASK_0_0_0_MCHBAR)—Offset 6CB4h

B-Unit Lites Group 1 Control

6CC0h 6CC3h 0h
(B_CR_LITES1_CTL_0_0_0_MCHBAR)—Offset 6CC0h

B-Unit Lites Group 1 Opcode Match Filter

6CC4h 6CC7h (B_CR_LITES1_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 0h
6CC4h

B-Unit Lites Group 1 Agent Match Filter

6CC8h 6CCBh (B_CR_LITES1_AGENT_MATCH_0_0_0_MCHBAR)—Offset 0h
6CC8h

B-Unit Lites Group 1 U2C IntData Match Filter

6CCCh 6CCFh (B_CR_LITES1_U2CINTDATA_MATCH_0_0_0_MCHBAR)— 0h
Offset 6CCCh

B-Unit Lites Group 1 Address Match Filter

LITES1_ADDR_MATCH
6CD0h 6CD7h 0h
(B_CR_LITES1_ADDR_MATCH_0_0_0_MCHBAR)—Offset
6CD0h

B-Unit Lites Group 1 Address Mask Filter LITES1_ADDR_MASK

6CD8h 6CDFh 0h
(B_CR_LITES1_ADDR_MASK_0_0_0_MCHBAR)—Offset 6CD8h

B-Unit Lites Group 1 Data Match Filter LITES1_DATA_MATCH

6CE0h 6CE3h 0h
(B_CR_LITES1_DATA_MATCH_0_0_0_MCHBAR)—Offset 6CE0h

B-Unit Lites Group 1 Data Mask Filter LITES1_DATA_MASK

6CE4h 6CE7h 0h
(B_CR_LITES1_DATA_MASK_0_0_0_MCHBAR)—Offset 6CE4h

B-Unit Lites Group 2 Control

6CF0h 6CF3h 0h
(B_CR_LITES2_CTL_0_0_0_MCHBAR)—Offset 6CF0h

B-Unit Lites Group 2 Opcode Match Filter

6CF4h 6CF7h (B_CR_LITES2_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 0h
6CF4h

B-Unit Lites Group 2 Agent Match Filter

6CF8h 6CFBh (B_CR_LITES2_AGENT_MATCH_0_0_0_MCHBAR)—Offset 0h
6CF8h

B-Unit Lites Group 2 U2C IntData Match Filter

6CFCh 6CFFh (B_CR_LITES2_U2CINTDATA_MATCH_0_0_0_MCHBAR)— 0h
Offset 6CFCh

B-Unit Lites Group 2 Address Match Filter

LITES2_ADDR_MATCH
6D00h 6D07h 0h
(B_CR_LITES2_ADDR_MATCH_0_0_0_MCHBAR)—Offset
6D00h

B-Unit Lites Group 2 Address Mask Filter LITES2_ADDR_MASK

6D08h 6D0Fh 0h
(B_CR_LITES2_ADDR_MASK_0_0_0_MCHBAR)—Offset 6D08h

B-Unit Lites Group 2 Data Match Filter LITES2_DATA_MATCH

6D10h 6D13h (B_CR_LITES2_DATA_MATCH_0_0_0_MCHBAR)—Offset 0h
6D10h

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Table 5-9. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

B-Unit Lites Group 2 Data Mask Filter LITES2_DATA_MASK

6D14h 6D17h 0h
(B_CR_LITES2_DATA_MASK_0_0_0_MCHBAR)—Offset 6D14h

B-Unit Lites Group 3 Control

6D20h 6D23h 0h
(B_CR_LITES3_CTL_0_0_0_MCHBAR)—Offset 6D20h

B-Unit Lites Group 3 Opcode Match Filter

6D24h 6D27h (B_CR_LITES3_OPCODE_MATCH_0_0_0_MCHBAR)—Offset 0h
6D24h

B-Unit Lites Group 3 Agent Match Filter

6D28h 6D2Bh (B_CR_LITES3_AGENT_MATCH_0_0_0_MCHBAR)—Offset 0h
6D28h

B-Unit Lites Group 3 U2C IntData Match Filter

6D2Ch 6D2Fh (B_CR_LITES3_U2CINTDATA_MATCH_0_0_0_MCHBAR)— 0h
Offset 6D2Ch

B-Unit Lites Group 3 Address Match Filter

LITES3_ADDR_MATCH
6D30h 6D37h 0h
(B_CR_LITES3_ADDR_MATCH_0_0_0_MCHBAR)—Offset
6D30h

B-Unit Lites Group 3 Address Mask Filter LITES3_ADDR_MASK

6D38h 6D3Fh 0h
(B_CR_LITES3_ADDR_MASK_0_0_0_MCHBAR)—Offset 6D38h

B-Unit Lites Group 3 Data Match Filter LITES3_DATA_MATCH

6D40h 6D43h (B_CR_LITES3_DATA_MATCH_0_0_0_MCHBAR)—Offset 0h
6D40h

B-Unit Lites Group 3 Data Mask Filter LITES3_DATA_MASK

6D44h 6D47h 0h
(B_CR_LITES3_DATA_MASK_0_0_0_MCHBAR)—Offset 6D44h

B-Unit Lites and Emon Master Control LITESEMONCTL

6D48h 6D4Bh 0h
(B_CR_LITESEMON_CTL_0_0_0_MCHBAR)—Offset 6D48h

B-Unit Arbiter Control BARBCTRL0 (B_CR_BARBCTRL0)—

6D4Ch 6D4Fh 4040404h
Offset 6D4Ch

B-Unit Arbiter Control BARBCTRL1 (B_CR_BARBCTRL1)—

6D50h 6D53h 4040404h
Offset 6D50h

6D54h 6D57h B-Unit Scheduler Control (B_CR_BSCHWT0)—Offset 6D54h 4040404h

6D58h 6D5Bh B-Unit Scheduler Control (B_CR_BSCHWT1)—Offset 6D58h 4040404h

6D5Ch 6D5Fh B-Unit Scheduler Control (B_CR_BSCHWT2)—Offset 6D5Ch 4040404h

6D60h 6D63h B-Unit Scheduler Control (B_CR_BSCHWT3)—Offset 6D60h 4040404h

6D64h 6D67h B-Unit Flush Control (B_CR_BWFLUSH)—Offset 6D64h FF010000h

6D68h 6D6Bh B-Unit Flush Weights (B_CR_BFLWT)—Offset 6D68h 404h

Weighted Scheduling Control of High Priority ISOC and Other

6D6Ch 6D6Fh 80003F0Fh
Requests (B_CR_BISOCWT)—Offset 6D6Ch

6D70h 6D73h B-Unit Control (B_CR_BCTRL2)—Offset 6D70h F0034h

Asset Classification Bits (B_CR_AC_RS0_0_0_0_MCHBAR)—

6D74h 6D77h 100000h
Offset 6D74h

IDI Real-Time Feature Configuration Bits

6D78h 6D7Bh 0h
(B_CR_RT_EN_0_0_0_MCHBAR)—Offset 6D78h

6D7Ch 6D7Fh B-Unit Control Register 3 (B_CR_BCTRL3)—Offset 6D7Ch 140h

Asymmetric Memory Region 0 With No Interleaving

Configuration
6E40h 6E43h 0h
(B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR)—Offset
6E40h

382 334818
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Table 5-9. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

Asymmetric Memory Region 1 With No Interleaving

Configuration
6E44h 6E47h 0h
(B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR)—Offset
6E44h

B-Unit Machine Check Mode Low (B_CR_BMCMODE_LOW)—

6E48h 6E4Bh 1h
Offset 6E48h

B-Unit Machine Check Mode High (B_CR_BMCMODE_HIGH)—

6E4Ch 6E4Fh 0h
Offset 6E4Ch

Two-Way Asymmetric Memory Region Configuration

6E50h 6E53h (B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR)—Offset 0h
6E50h

5.9.1 B-Unit Miscellaneous Configuration

(B_CR_BMISC_0_0_0_MCHBAR)—Offset 6800h
Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 7h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
RESERVED_0

READ_FSEG_FROM_DRAM
SEND_BOOT_VECTOR_TO_DRAM
ABSEGINDRAM

READ_ESEG_FROM_DRAM

Bit Default &

Field Name (ID): Description
Range Access

31:4
0h Reserved (RESERVED_0): Reserved.
RO

Send Boot Vector to DRAM

0h (SEND_BOOT_VECTOR_TO_DRAM): When set,IA accesses to
3
RW 0xFFFF_0000 to 0XFFFF_FFFF will be sent to memory, regardless
of the Host IO Boundary setting in TOLUD.

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Bit Default &

Field Name (ID): Description
Range Access

ABSeginDRAM Legacy Video Area (ABSEGINDRAM): When

this bit is set, reads and writes targeting A or Bsegments are
1h
2 routed to DRAM. Asegment corresponds to the memory range
RW
0xA_0000 to 0xA_FFFF. Bsegment corresponds to the memory
ranges 0xB_0000 to 0xB_7FFF and 0xB_8000 to 0xB_FFFF.
Read FSeg from DRAM (READ_FSEG_FROM_DRAM): When
1h this bit is set, reads targeting Fsegment are routed to DRAM.
1
RW Fsegment corresponds to the memory range 0xF_0000 to
0xF_FFFF.
Read ESeg from DRAM (READ_ESEG_FROM_DRAM): When
1h this bit is set, reads targeting Esegment are routed to DRAM.
0
RW Esegment corresponds to the memory range 0xE_0000 to
0xE_FFFF.

5.9.2 Slice 0 Memory Access Count

(B_CR_MEM_ACCESS_COUNT_SLICE0)—Offset 6868h
Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM_ACCESS_COUNT

Bit Default &

Field Name (ID): Description
Range Access

Memory Access Count (MEM_ACCESS_COUNT): Counts the

number of PMI transactions that the B-Unit has sent to any PMI
0h
31:0 channel. Counts both reads and writes. Counter is not saturating
RO/V
and will roll over to zero. It is up to the consumer of the counter to
handle roll over cases.

5.9.3 Slice 1 Memory Access Count

(B_CR_MEM_ACCESS_COUNT_SLICE1)—Offset 686Ch
Access Method

384 334818
MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MEM_ACCESS_COUNT
Bit Default &
Field Name (ID): Description
Range Access

Memory Access Count (MEM_ACCESS_COUNT): Counts the

number of PMI transactions that the B-Unit has sent to any PMI
0h
31:0 channel. Counts both reads and writes. Counter is not saturating
RO/V
and will roll over to zero. It is up to the consumer of the counter to
handle roll over cases.

5.9.4 IMR0 Mask (B_CR_BIMR0MASK_0_0_0_MCHBAR)—Offset

6874h
This register, along with IMR0BASE, IMR0RAC, and IMR0WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR0RAC and IMR0WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GT_IWB_EN
IA_IWB_EN
RESERVED_0

IMR0_MASK

334818 385
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit WB Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables return to the
0h
31 requester of implicit writeback HITM data from GT. When set to 0,
RW
inhibits HITM data from GT from being returned to the requester.
HITM data from IA cores may be returned to the requester
depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit WB Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 HITM data from IA cores to be returned to the requester. When set
RW
to 0, inhibits HITM data from IA cores from being returned to the
requester. HITM data from GT may be returned to the requester,
depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR0 Mask (IMR0_MASK): These bits are ANDed with

0h bits 38:10 of the incoming address to determine if the combined
28:0
RW result matches the IMR0BASE[28:0] value. A match indicates that
the incoming address falls within the IMR0 region.

5.9.5 IMR0 Control Policy (B_CR_BIMR0CP_0_0_0_MCHBAR)—

Offset 6878h
This register controls the access policy to the Read Access Policy BIMR0RAC, Write
Access Policy BIMR0WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010
IMR0_CTRL_POL

386 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR0 Control Policy (IMR0_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR0RAC,
63:0
RW BIMR0WAC and BIMR0CP registers based on the value from each
agent's 6bit SAI field.

5.9.6 IMR0 Read Access Policy

(B_CR_BIMR0RAC_0_0_0_MCHBAR)—Offset 6880h
This register, along with IMR0BASE, IMR0MASK and IMR0WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR0_READ_POL_63
IMR0_READ_POL_62
IMR0_READ_POL_61
IMR0_READ_POL_60
IMR0_READ_POL_59
IMR0_READ_POL_58
IMR0_READ_POL_57
IMR0_READ_POL_56
IMR0_READ_POL_55
IMR0_READ_POL_54
IMR0_READ_POL_53
IMR0_READ_POL_52
IMR0_READ_POL_51
IMR0_READ_POL_50
IMR0_READ_POL_49
IMR0_READ_POL_48
IMR0_READ_POL_47
IMR0_READ_POL_46
IMR0_READ_POL_45
IMR0_READ_POL_44
IMR0_READ_POL_43
IMR0_READ_POL_42
IMR0_READ_POL_41
IMR0_READ_POL_40
IMR0_READ_POL_39
IMR0_READ_POL_38
IMR0_READ_POL_37
IMR0_READ_POL_36
IMR0_READ_POL_35
IMR0_READ_POL_34
IMR0_READ_POL_33
IMR0_READ_POL_32
IMR0_READ_POL_31
IMR0_READ_POL_30
IMR0_READ_POL_29
IMR0_READ_POL_28
IMR0_READ_POL_27
IMR0_READ_POL_26
IMR0_READ_POL_25
IMR0_READ_POL_24
IMR0_READ_POL_23
IMR0_READ_POL_22
IMR0_READ_POL_21
IMR0_READ_POL_20
IMR0_READ_POL_19
IMR0_READ_POL_18
IMR0_READ_POL_17
IMR0_READ_POL_16
IMR0_READ_POL_15
IMR0_READ_POL_14
IMR0_READ_POL_13
IMR0_READ_POL_12
IMR0_READ_POL_11
IMR0_READ_POL_10
IMR0_READ_POL_9
IMR0_READ_POL_8
IMR0_READ_POL_7
IMR0_READ_POL_6
IMR0_READ_POL_5
IMR0_READ_POL_4
IMR0_READ_POL_3
IMR0_READ_POL_2
IMR0_READ_POL_1
IMR0_READ_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR0 Read Access Policy 63 (IMR0_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 62 (IMR0_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 61 (IMR0_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 60 (IMR0_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 59 (IMR0_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.

334818 387
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Bit Default &

Field Name (ID): Description
Range Access

IMR0 Read Access Policy 58 (IMR0_READ_POL_58): Bit

0h
58 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 57 (IMR0_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 56 (IMR0_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 55 (IMR0_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 54 (IMR0_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 53 (IMR0_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 52 (IMR0_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 51 (IMR0_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 50 (IMR0_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 49 (IMR0_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 48 (IMR0_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 47 (IMR0_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 46 (IMR0_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 45 (IMR0_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 44 (IMR0_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.

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Bit Default &

Field Name (ID): Description
Range Access

IMR0 Read Access Policy 43 (IMR0_READ_POL_43): Bit

0h
43 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 42 (IMR0_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 41 (IMR0_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 40 (IMR0_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 39 (IMR0_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 38 (IMR0_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 37 (IMR0_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 36 (IMR0_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 35 (IMR0_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 34 (IMR0_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 33 (IMR0_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 32 (IMR0_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 31 (IMR0_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 30 (IMR0_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 29 (IMR0_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.

334818 389
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Bit Default &

Field Name (ID): Description
Range Access

IMR0 Read Access Policy 28 (IMR0_READ_POL_28): Bit

0h
28 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 27 (IMR0_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 26 (IMR0_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 25 (IMR0_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 24 (IMR0_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 23 (IMR0_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 22 (IMR0_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 21 (IMR0_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 20 (IMR0_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 19 (IMR0_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 18 (IMR0_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 17 (IMR0_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 16 (IMR0_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 15 (IMR0_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 14 (IMR0_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.

390 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR0 Read Access Policy 13 (IMR0_READ_POL_13): Bit

0h
13 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 12 (IMR0_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 11 (IMR0_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 10 (IMR0_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 9 (IMR0_READ_POL_9): Bit vector
0h
9 used to determine which agents are allowed read access to the
RO
IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 8 (IMR0_READ_POL_8): Bit vector
0h
8 used to determine which agents are allowed read access to the
RW
IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 7 (IMR0_READ_POL_7): Bit vector
0h
7 used to determine which agents are allowed read access to the
RO
IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 6 (IMR0_READ_POL_6): Bit vector
0h
6 used to determine which agents are allowed read access to the
RO
IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 5 (IMR0_READ_POL_5): Bit vector
0h
5 used to determine which agents are allowed read access to the
RW
IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 4 (IMR0_READ_POL_4): Bit vector
0h
4 used to determine which agents are allowed read access to the
RW
IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 3 (IMR0_READ_POL_3): Bit vector
0h
3 used to determine which agents are allowed read access to the
RW
IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 2 (IMR0_READ_POL_2): Bit vector
0h
2 used to determine which agents are allowed read access to the
RW
IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 1 (IMR0_READ_POL_1): Bit vector
0h
1 used to determine which agents are allowed read access to the
RW
IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Read Access Policy 0 (IMR0_READ_POL_0): Bit vector
0h
0 used to determine which agents are allowed read access to the
RW
IMR0 region, based on each agent's 6bit encoded SAI value.

334818 391
 MCHBAR

5.9.7 IMR0 Write Access Policy

(B_CR_BIMR0WAC_0_0_0_MCHBAR)—Offset 6888h
This register, along with IMR0BASE, IMR0MASK and IMR0RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR0_WRITE_POL_63
IMR0_WRITE_POL_62
IMR0_WRITE_POL_61
IMR0_WRITE_POL_60
IMR0_WRITE_POL_59
IMR0_WRITE_POL_58
IMR0_WRITE_POL_57
IMR0_WRITE_POL_56
IMR0_WRITE_POL_55
IMR0_WRITE_POL_54
IMR0_WRITE_POL_53
IMR0_WRITE_POL_52
IMR0_WRITE_POL_51
IMR0_WRITE_POL_50
IMR0_WRITE_POL_49
IMR0_WRITE_POL_48
IMR0_WRITE_POL_47
IMR0_WRITE_POL_46
IMR0_WRITE_POL_45
IMR0_WRITE_POL_44
IMR0_WRITE_POL_43
IMR0_WRITE_POL_42
IMR0_WRITE_POL_41
IMR0_WRITE_POL_40
IMR0_WRITE_POL_39
IMR0_WRITE_POL_38
IMR0_WRITE_POL_37
IMR0_WRITE_POL_36
IMR0_WRITE_POL_35
IMR0_WRITE_POL_34
IMR0_WRITE_POL_33
IMR0_WRITE_POL_32
IMR0_WRITE_POL_31
IMR0_WRITE_POL_30
IMR0_WRITE_POL_29
IMR0_WRITE_POL_28
IMR0_WRITE_POL_27
IMR0_WRITE_POL_26
IMR0_WRITE_POL_25
IMR0_WRITE_POL_24
IMR0_WRITE_POL_23
IMR0_WRITE_POL_22
IMR0_WRITE_POL_21
IMR0_WRITE_POL_20
IMR0_WRITE_POL_19
IMR0_WRITE_POL_18
IMR0_WRITE_POL_17
IMR0_WRITE_POL_16
IMR0_WRITE_POL_15
IMR0_WRITE_POL_14
IMR0_WRITE_POL_13
IMR0_WRITE_POL_12
IMR0_WRITE_POL_11
IMR0_WRITE_POL_10
IMR0_WRITE_POL_9
IMR0_WRITE_POL_8
IMR0_WRITE_POL_7
IMR0_WRITE_POL_6
IMR0_WRITE_POL_5
IMR0_WRITE_POL_4
IMR0_WRITE_POL_3
IMR0_WRITE_POL_2
IMR0_WRITE_POL_1
IMR0_WRITE_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR0 Write Access Policy 63 (IMR0_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 62 (IMR0_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 61 (IMR0_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 60 (IMR0_WRITE_POL_60): Bit
0h
60 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 59 (IMR0_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 58 (IMR0_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 57 (IMR0_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.

392 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR0 Write Access Policy 56 (IMR0_WRITE_POL_56): Bit

0h
56 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 55 (IMR0_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 54 (IMR0_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 53 (IMR0_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 52 (IMR0_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 51 (IMR0_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 50 (IMR0_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 49 (IMR0_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 48 (IMR0_WRITE_POL_48): Bit
0h
48 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 47 (IMR0_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 46 (IMR0_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 45 (IMR0_WRITE_POL_45): Bit
0h
45 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 44 (IMR0_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 43 (IMR0_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 42 (IMR0_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.

334818 393
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR0 Write Access Policy 41 (IMR0_WRITE_POL_41): Bit

0h
41 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 40 (IMR0_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 39 (IMR0_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 38 (IMR0_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 37 (IMR0_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 36 (IMR0_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 35 (IMR0_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 34 (IMR0_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 33 (IMR0_WRITE_POL_33): Bit
0h
33 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 32 (IMR0_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 31 (IMR0_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 30 (IMR0_WRITE_POL_30): Bit
0h
30 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 29 (IMR0_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 28 (IMR0_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 27 (IMR0_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.

394 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR0 Write Access Policy 26 (IMR0_WRITE_POL_26): Bit

0h
26 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 25 (IMR0_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 24 (IMR0_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 23 (IMR0_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 22 (IMR0_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 21 (IMR0_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 20 (IMR0_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 19 (IMR0_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 18 (IMR0_WRITE_POL_18): Bit
0h
18 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 17 (IMR0_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 16 (IMR0_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 15 (IMR0_WRITE_POL_15): Bit
0h
15 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 14 (IMR0_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 13 (IMR0_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 12 (IMR0_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.

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Bit Default &

Field Name (ID): Description
Range Access

IMR0 Write Access Policy 11 (IMR0_WRITE_POL_11): Bit

0h
11 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 10 (IMR0_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 9 (IMR0_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 8 (IMR0_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 7 (IMR0_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 6 (IMR0_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 5 (IMR0_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 4 (IMR0_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 3 (IMR0_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 2 (IMR0_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 1 (IMR0_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.
IMR0 Write Access Policy 0 (IMR0_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the IMR0 region, based on each agent's 6bit encoded SAI value.

5.9.8 IMR1 Base (B_CR_BIMR1BASE_0_0_0_MCHBAR)—Offset

6890h
This register, along with IMR1MASK, IMR1RAC and IMR1WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or

396 334818
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from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR1RAC and IMR1WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR_EN
TR_EN
RESERVED_1

IMR1_BASE
Bit Default &
Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Trace Enable (TR_EN): Asset Classification AC[0]: Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

Base 1 IMR1 Base (IMR1_BASE): Specifies bits 38:10 of the

start address of IMR1 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR1MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR1 defined region.

5.9.9 IMR1 Mask (B_CR_BIMR1MASK_0_0_0_MCHBAR)—Offset

6894h
This register, along with IMR1BASE, IMR1RAC and IMR1WAC, defines an isolated region
of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR1RAC and IMR1WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

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3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GT_IWB_EN
IA_IWB_EN

IMR1_MASK
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

GT Implicit Writeback Enable (GT_IWB_EN): Asset

Classification AC[2]: Enables implicit writebacks to protected
region from GT caching agent. When set to 1, enables return to
0h
31 the requester of implicit writeback HITM data from GT. When set
RW
to 0, inhibits HITM data from GT from being returned to the
requester. HITM data from IA cores may be returned to the
requester depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: Implicit Writeback Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 data HITM data from IA cores to be returned to the requester.
RW
When set to 0, inhibits HITM data from IA cores from being
returned to the requester. HITM data from GT may be returned to
the requester depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 1 IMR1 Mask (IMR1_MASK): These bits are ANDed with

0h bits 38:10 of the incoming address to determine if the combined
28:0
RW result matches the IMR1BASE[28:0] value. A match indicates that
the incoming address falls within the IMR1 region.

5.9.10 IMR1 Control Policy (B_CR_BIMR1CP_0_0_0_MCHBAR)—

Offset 6898h
This register controls the access policy to the Read Access Policy BIMR1RAC, the Write
Access Policy BIMR1WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010

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IMR1_CTRL_POL
Bit Default &
Field Name (ID): Description
Range Access

IMR1 Control Policy (IMR1_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR1RAC,
63:0
RW BIMR1WAC and BIMR1CP registers, based on the value from each
agent's 6bit SAI field.

5.9.11 IMR1 Read Access Policy

(B_CR_BIMR1RAC_0_0_0_MCHBAR)—Offset 68A0h
This register, along with IMR1BASE, IMR1MASK and IMR1WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR1_READ_POL_63
IMR1_READ_POL_62
IMR1_READ_POL_61
IMR1_READ_POL_60
IMR1_READ_POL_59
IMR1_READ_POL_58
IMR1_READ_POL_57
IMR1_READ_POL_56
IMR1_READ_POL_55
IMR1_READ_POL_54
IMR1_READ_POL_53
IMR1_READ_POL_52
IMR1_READ_POL_51
IMR1_READ_POL_50
IMR1_READ_POL_49
IMR1_READ_POL_48
IMR1_READ_POL_47
IMR1_READ_POL_46
IMR1_READ_POL_45
IMR1_READ_POL_44
IMR1_READ_POL_43
IMR1_READ_POL_42
IMR1_READ_POL_41
IMR1_READ_POL_40
IMR1_READ_POL_39
IMR1_READ_POL_38
IMR1_READ_POL_37
IMR1_READ_POL_36
IMR1_READ_POL_35
IMR1_READ_POL_34
IMR1_READ_POL_33
IMR1_READ_POL_32
IMR1_READ_POL_31
IMR1_READ_POL_30
IMR1_READ_POL_29
IMR1_READ_POL_28
IMR1_READ_POL_27
IMR1_READ_POL_26
IMR1_READ_POL_25
IMR1_READ_POL_24
IMR1_READ_POL_23
IMR1_READ_POL_22
IMR1_READ_POL_21
IMR1_READ_POL_20
IMR1_READ_POL_19
IMR1_READ_POL_18
IMR1_READ_POL_17
IMR1_READ_POL_16
IMR1_READ_POL_15
IMR1_READ_POL_14
IMR1_READ_POL_13
IMR1_READ_POL_12
IMR1_READ_POL_11
IMR1_READ_POL_10
IMR1_READ_POL_9
IMR1_READ_POL_8
IMR1_READ_POL_7
IMR1_READ_POL_6
IMR1_READ_POL_5
IMR1_READ_POL_4
IMR1_READ_POL_3
IMR1_READ_POL_2
IMR1_READ_POL_1
IMR1_READ_POL_0

Bit Default &

Field Name (ID): Description
Range Access

IMR1 Read Access Policy 63 (IMR1_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 62 (IMR1_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 61 (IMR1_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.

334818 399
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Bit Default &

Field Name (ID): Description
Range Access

IMR1 Read Access Policy 60 (IMR1_READ_POL_60): Bit

0h
60 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 59 (IMR1_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 58 (IMR1_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 57 (IMR1_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 56 (IMR1_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 55 (IMR1_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 54 (IMR1_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 53 (IMR1_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 52 (IMR1_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 51 (IMR1_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 50 (IMR1_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 49 (IMR1_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 48 (IMR1_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 47 (IMR1_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 46 (IMR1_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.

400 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR1 Read Access Policy 45 (IMR1_READ_POL_45): Bit

0h
45 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 44 (IMR1_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 43 (IMR1_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 42 (IMR1_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 41 (IMR1_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 40 (IMR1_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 39 (IMR1_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 38 (IMR1_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 37 (IMR1_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 36 (IMR1_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 35 (IMR1_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 34 (IMR1_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 33 (IMR1_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 32 (IMR1_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 31 (IMR1_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.

334818 401
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Bit Default &

Field Name (ID): Description
Range Access

IMR1 Read Access Policy 30 (IMR1_READ_POL_30): Bit

0h
30 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 29 (IMR1_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 28 (IMR1_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 27 (IMR1_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 26 (IMR1_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 25 (IMR1_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 24 (IMR1_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 23 (IMR1_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 22 (IMR1_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 21 (IMR1_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 20 (IMR1_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 19 (IMR1_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 18 (IMR1_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 17 (IMR1_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 16 (IMR1_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.

402 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR1 Read Access Policy 15 (IMR1_READ_POL_15): Bit

0h
15 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 14 (IMR1_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 13 (IMR1_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 12 (IMR1_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 11 (IMR1_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 10 (IMR1_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 9 (IMR1_READ_POL_9): Bit vector
0h
9 used to determine which agents are allowed read access to the
RO
IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 8 (IMR1_READ_POL_8): Bit vector
0h
8 used to determine which agents are allowed read access to the
RW
IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 7 (IMR1_READ_POL_7): Bit vector
0h
7 used to determine which agents are allowed read access to the
RO
IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 6 (IMR1_READ_POL_6): Bit vector
0h
6 used to determine which agents are allowed read access to the
RO
IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 5 (IMR1_READ_POL_5): Bit vector
0h
5 used to determine which agents are allowed read access to the
RW
IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 4 (IMR1_READ_POL_4): Bit vector
0h
4 used to determine which agents are allowed read access to the
RW
IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 3 (IMR1_READ_POL_3): Bit vector
0h
3 used to determine which agents are allowed read access to the
RW
IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 2 (IMR1_READ_POL_2): Bit vector
0h
2 used to determine which agents are allowed read access to the
RW
IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Read Access Policy 1 (IMR1_READ_POL_1): Bit vector
0h
1 used to determine which agents are allowed read access to the
RW
IMR1 region, based on each agent's 6bit encoded SAI value.

334818 403
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR1 Read Access Policy 0 (IMR1_READ_POL_0): Bit vector

0h
0 used to determine which agents are allowed read access to the
RW
IMR1 region, based on each agent's 6bit encoded SAI value.

5.9.12 IMR1 Write Access Policy

(B_CR_BIMR1WAC_0_0_0_MCHBAR)—Offset 68A8h
This register, along with IMR1BASE, IMR1MASK and IMR1RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR1_WRITE_POL_63
IMR1_WRITE_POL_62
IMR1_WRITE_POL_61
IMR1_WRITE_POL_60
IMR1_WRITE_POL_59
IMR1_WRITE_POL_58
IMR1_WRITE_POL_57
IMR1_WRITE_POL_56
IMR1_WRITE_POL_55
IMR1_WRITE_POL_54
IMR1_WRITE_POL_53
IMR1_WRITE_POL_52
IMR1_WRITE_POL_51
IMR1_WRITE_POL_50
IMR1_WRITE_POL_49
IMR1_WRITE_POL_48
IMR1_WRITE_POL_47
IMR1_WRITE_POL_46
IMR1_WRITE_POL_45
IMR1_WRITE_POL_44
IMR1_WRITE_POL_43
IMR1_WRITE_POL_42
IMR1_WRITE_POL_41
IMR1_WRITE_POL_40
IMR1_WRITE_POL_39
IMR1_WRITE_POL_38
IMR1_WRITE_POL_37
IMR1_WRITE_POL_36
IMR1_WRITE_POL_35
IMR1_WRITE_POL_34
IMR1_WRITE_POL_33
IMR1_WRITE_POL_32
IMR1_WRITE_POL_31
IMR1_WRITE_POL_30
IMR1_WRITE_POL_29
IMR1_WRITE_POL_28
IMR1_WRITE_POL_27
IMR1_WRITE_POL_26
IMR1_WRITE_POL_25
IMR1_WRITE_POL_24
IMR1_WRITE_POL_23
IMR1_WRITE_POL_22
IMR1_WRITE_POL_21
IMR1_WRITE_POL_20
IMR1_WRITE_POL_19
IMR1_WRITE_POL_18
IMR1_WRITE_POL_17
IMR1_WRITE_POL_16
IMR1_WRITE_POL_15
IMR1_WRITE_POL_14
IMR1_WRITE_POL_13
IMR1_WRITE_POL_12
IMR1_WRITE_POL_11
IMR1_WRITE_POL_10
IMR1_WRITE_POL_9
IMR1_WRITE_POL_8
IMR1_WRITE_POL_7
IMR1_WRITE_POL_6
IMR1_WRITE_POL_5
IMR1_WRITE_POL_4
IMR1_WRITE_POL_3
IMR1_WRITE_POL_2
IMR1_WRITE_POL_1
IMR1_WRITE_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR1 Write Access Policy 63 (IMR1_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 62 (IMR1_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 61 (IMR1_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 60 (IMR1_WRITE_POL_60): Bit
0h
60 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 59 (IMR1_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.

404 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR1 Write Access Policy 58 (IMR1_WRITE_POL_58): Bit

0h
58 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 57 (IMR1_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 56 (IMR1_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 55 (IMR1_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 54 (IMR1_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 53 (IMR1_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 52 (IMR1_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 51 (IMR1_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 50 (IMR1_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 49 (IMR1_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 48 (IMR1_WRITE_POL_48): Bit
0h
48 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 47 (IMR1_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 46 (IMR1_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 45 (IMR1_WRITE_POL_45): Bit
0h
45 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 44 (IMR1_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.

334818 405
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR1 Write Access Policy 43 (IMR1_WRITE_POL_43): Bit

0h
43 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 42 (IMR1_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 41 (IMR1_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 40 (IMR1_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 39 (IMR1_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 38 (IMR1_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 37 (IMR1_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 36 (IMR1_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 35 (IMR1_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 34 (IMR1_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 33 (IMR1_WRITE_POL_33): Bit
0h
33 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 32 (IMR1_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 31 (IMR1_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 30 (IMR1_WRITE_POL_30): Bit
0h
30 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 29 (IMR1_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.

406 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR1 Write Access Policy 28 (IMR1_WRITE_POL_28): Bit

0h
28 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 27 (IMR1_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 26 (IMR1_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 25 (IMR1_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 24 (IMR1_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 23 (IMR1_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 22 (IMR1_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 21 (IMR1_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 20 (IMR1_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 19 (IMR1_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 18 (IMR1_WRITE_POL_18): Bit
0h
18 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 17 (IMR1_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 16 (IMR1_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 15 (IMR1_WRITE_POL_15): Bit
0h
15 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 14 (IMR1_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.

334818 407
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR1 Write Access Policy 13 (IMR1_WRITE_POL_13): Bit

0h
13 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 12 (IMR1_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 11 (IMR1_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 10 (IMR1_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 9 (IMR1_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 8 (IMR1_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 7 (IMR1_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 6 (IMR1_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 5 (IMR1_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 4 (IMR1_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 3 (IMR1_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 2 (IMR1_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 1 (IMR1_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.
IMR1 Write Access Policy 0 (IMR1_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the IMR1 region, based on each agent's 6bit encoded SAI value.

408 334818
MCHBAR

5.9.13 Base 0 IMR2 Base (B_CR_BIMR2BASE_0_0_0_MCHBAR)—

Offset 68B0h
This register, along with IMR2MASK, IMR2RAC and IMR2WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR2RAC and IMR2WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IMR2_BASE
RESERVED_1
IMR_EN
TR_EN

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

Base 0 IMR2 Base (IMR2_BASE): Specifies bits 38:10 of the

start address of IMR2 region. IMR region size must be a strict
0h power of two, at least 1KB and naturally aligned to the size. These
28:0
RW bits are compared with the result of the IMR2MASK[28:0] applied
to bits 38:10 of the incoming address to determine if an access
falls within the IMR2 defined region.

5.9.14 IMR2 Mask (B_CR_BIMR2MASK_0_0_0_MCHBAR)—Offset

68B4h
This register, along with IMR2BASE, IMR2RAC, and IMR2WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR2RAC and IMR2WAC
registers.

334818 409
 MCHBAR

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GT_IWB_EN
IA_IWB_EN
RESERVED_0

IMR2_MASK
Bit Default &
Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 HITM data from GT to be returned to the requester. When set to 0,
RW
inhibits HITM data from GT from being returned to the requester.
HITM data from IA cores may be returned to the requester
depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit Writeback Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 HITM data from IA cores to be returned to the requester. When set
RW
to 0, inhibits HITM data from IA cores from being returned to the
requester. HITM data from GT may be returned to the requester
depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR2 Mask (IMR2_MASK): These bits are ANDed with

0h bits 38:10 of the incoming address to determine if the combined
28:0
RW result matches the IMR2BASE[28:0] value. A match indicates that
the incoming address falls within the IMR2 region.

5.9.15 IMR2 Control Policy (B_CR_BIMR2CP_0_0_0_MCHBAR)—

Offset 68B8h
This register controls the access policy to the Read Access Policy BIMR2RAC, Write
Access Policy BIMR2WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

410 334818
MCHBAR

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010

IMR2_CTRL_POL
Bit Default &
Field Name (ID): Description
Range Access

IMR2 Control Policy (IMR2_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR2RAC,
63:0
RW BIMR2WAC and BIMR2CP registers, based on the value from each
agent's 6bit SAI field.

5.9.16 IMR2 Read Access Policy

(B_CR_BIMR2RAC_0_0_0_MCHBAR)—Offset 68C0h
This register, along with IMR2BASE, IMR2MASK and IMR2WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR2_READ_POL_63
IMR2_READ_POL_62
IMR2_READ_POL_61
IMR2_READ_POL_60
IMR2_READ_POL_59
IMR2_READ_POL_58
IMR2_READ_POL_57
IMR2_READ_POL_56
IMR2_READ_POL_55
IMR2_READ_POL_54
IMR2_READ_POL_53
IMR2_READ_POL_52
IMR2_READ_POL_51
IMR2_READ_POL_50
IMR2_READ_POL_49
IMR2_READ_POL_48
IMR2_READ_POL_47
IMR2_READ_POL_46
IMR2_READ_POL_45
IMR2_READ_POL_44
IMR2_READ_POL_43
IMR2_READ_POL_42
IMR2_READ_POL_41
IMR2_READ_POL_40
IMR2_READ_POL_39
IMR2_READ_POL_38
IMR2_READ_POL_37
IMR2_READ_POL_36
IMR2_READ_POL_35
IMR2_READ_POL_34
IMR2_READ_POL_33
IMR2_READ_POL_32
IMR2_READ_POL_31
IMR2_READ_POL_30
IMR2_READ_POL_29
IMR2_READ_POL_28
IMR2_READ_POL_27
IMR2_READ_POL_26
IMR2_READ_POL_25
IMR2_READ_POL_24
IMR2_READ_POL_23
IMR2_READ_POL_22
IMR2_READ_POL_21
IMR2_READ_POL_20
IMR2_READ_POL_19
IMR2_READ_POL_18
IMR2_READ_POL_17
IMR2_READ_POL_16
IMR2_READ_POL_15
IMR2_READ_POL_14
IMR2_READ_POL_13
IMR2_READ_POL_12
IMR2_READ_POL_11
IMR2_READ_POL_10
IMR2_READ_POL_9
IMR2_READ_POL_8
IMR2_READ_POL_7
IMR2_READ_POL_6
IMR2_READ_POL_5
IMR2_READ_POL_4
IMR2_READ_POL_3
IMR2_READ_POL_2
IMR2_READ_POL_1
IMR2_READ_POL_0

Bit Default &

Field Name (ID): Description
Range Access

IMR2 Read Access Policy 63 (IMR2_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.

334818 411
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR2 Read Access Policy 62 (IMR2_READ_POL_62): Bit

0h
62 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 61 (IMR2_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 60 (IMR2_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 59 (IMR2_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 58 (IMR2_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 57 (IMR2_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 56 (IMR2_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 55 (IMR2_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 54 (IMR2_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 53 (IMR2_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 52 (IMR2_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 51 (IMR2_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 50 (IMR2_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 49 (IMR2_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 48 (IMR2_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.

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Bit Default &

Field Name (ID): Description
Range Access

IMR2 Read Access Policy 47 (IMR2_READ_POL_47): Bit

0h
47 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 46 (IMR2_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 45 (IMR2_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 44 (IMR2_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 43 (IMR2_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 42 (IMR2_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 41 (IMR2_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 40 (IMR2_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 39 (IMR2_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 38 (IMR2_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 37 (IMR2_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 36 (IMR2_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 35 (IMR2_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 34 (IMR2_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 33 (IMR2_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.

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Bit Default &

Field Name (ID): Description
Range Access

IMR2 Read Access Policy 32 (IMR2_READ_POL_32): Bit

0h
32 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 31 (IMR2_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 30 (IMR2_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 29 (IMR2_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 28 (IMR2_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 27 (IMR2_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 26 (IMR2_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 25 (IMR2_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 24 (IMR2_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 23 (IMR2_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 22 (IMR2_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 21 (IMR2_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 20 (IMR2_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 19 (IMR2_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 18 (IMR2_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.

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Bit Default &

Field Name (ID): Description
Range Access

IMR2 Read Access Policy 17 (IMR2_READ_POL_17): Bit

0h
17 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 16 (IMR2_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 15 (IMR2_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 14 (IMR2_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 13 (IMR2_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 12 (IMR2_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 11 (IMR2_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 10 (IMR2_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 9 (IMR2_READ_POL_9): Bit vector
0h
9 used to determine which agents are allowed read access to the
RO
IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 8 (IMR2_READ_POL_8): Bit vector
0h
8 used to determine which agents are allowed read access to the
RW
IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 7 (IMR2_READ_POL_7): Bit vector
0h
7 used to determine which agents are allowed read access to the
RO
IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 6 (IMR2_READ_POL_6): Bit vector
0h
6 used to determine which agents are allowed read access to the
RO
IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 5 (IMR2_READ_POL_5): Bit vector
0h
5 used to determine which agents are allowed read access to the
RW
IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 4 (IMR2_READ_POL_4): Bit vector
0h
4 used to determine which agents are allowed read access to the
RW
IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 3 (IMR2_READ_POL_3): Bit vector
0h
3 used to determine which agents are allowed read access to the
RW
IMR2 region, based on each agent's 6bit encoded SAI value.

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Bit Default &

Field Name (ID): Description
Range Access

IMR2 Read Access Policy 2 (IMR2_READ_POL_2): Bit vector

0h
2 used to determine which agents are allowed read access to the
RW
IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 1 (IMR2_READ_POL_1): Bit vector
0h
1 used to determine which agents are allowed read access to the
RW
IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Read Access Policy 0 (IMR2_READ_POL_0): Bit vector
0h
0 used to determine which agents are allowed read access to the
RW
IMR2 region, based on each agent's 6bit encoded SAI value.

5.9.17 IMR2 Write Access Policy

(B_CR_BIMR2WAC_0_0_0_MCHBAR)—Offset 68C8h
This register, along with IMR2BASE, IMR2MASK and IMR2RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR2_WRITE_POL_63
IMR2_WRITE_POL_62
IMR2_WRITE_POL_61
IMR2_WRITE_POL_60
IMR2_WRITE_POL_59
IMR2_WRITE_POL_58
IMR2_WRITE_POL_57
IMR2_WRITE_POL_56
IMR2_WRITE_POL_55
IMR2_WRITE_POL_54
IMR2_WRITE_POL_53
IMR2_WRITE_POL_52
IMR2_WRITE_POL_51
IMR2_WRITE_POL_50
IMR2_WRITE_POL_49
IMR2_WRITE_POL_48
IMR2_WRITE_POL_47
IMR2_WRITE_POL_46
IMR2_WRITE_POL_45
IMR2_WRITE_POL_44
IMR2_WRITE_POL_43
IMR2_WRITE_POL_42
IMR2_WRITE_POL_41
IMR2_WRITE_POL_40
IMR2_WRITE_POL_39
IMR2_WRITE_POL_38
IMR2_WRITE_POL_37
IMR2_WRITE_POL_36
IMR2_WRITE_POL_35
IMR2_WRITE_POL_34
IMR2_WRITE_POL_33
IMR2_WRITE_POL_32
IMR2_WRITE_POL_31
IMR2_WRITE_POL_30
IMR2_WRITE_POL_29
IMR2_WRITE_POL_28
IMR2_WRITE_POL_27
IMR2_WRITE_POL_26
IMR2_WRITE_POL_25
IMR2_WRITE_POL_24
IMR2_WRITE_POL_23
IMR2_WRITE_POL_22
IMR2_WRITE_POL_21
IMR2_WRITE_POL_20
IMR2_WRITE_POL_19
IMR2_WRITE_POL_18
IMR2_WRITE_POL_17
IMR2_WRITE_POL_16
IMR2_WRITE_POL_15
IMR2_WRITE_POL_14
IMR2_WRITE_POL_13
IMR2_WRITE_POL_12
IMR2_WRITE_POL_11
IMR2_WRITE_POL_10
IMR2_WRITE_POL_9
IMR2_WRITE_POL_8
IMR2_WRITE_POL_7
IMR2_WRITE_POL_6
IMR2_WRITE_POL_5
IMR2_WRITE_POL_4
IMR2_WRITE_POL_3
IMR2_WRITE_POL_2
IMR2_WRITE_POL_1
IMR2_WRITE_POL_0

Bit Default &

Field Name (ID): Description
Range Access

IMR2 Write Access Policy 63 (IMR2_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 62 (IMR2_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 61 (IMR2_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.

416 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR2 Write Access Policy 60 (IMR2_WRITE_POL_60): Bit

0h
60 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 59 (IMR2_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 58 (IMR2_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 57 (IMR2_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 56 (IMR2_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 55 (IMR2_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 54 (IMR2_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 53 (IMR2_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 52 (IMR2_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 51 (IMR2_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 50 (IMR2_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 49 (IMR2_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 48 (IMR2_WRITE_POL_48): Bit
0h
48 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 47 (IMR2_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 46 (IMR2_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.

334818 417
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR2 Write Access Policy 45 (IMR2_WRITE_POL_45): Bit

0h
45 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 44 (IMR2_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 43 (IMR2_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 42 (IMR2_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 41 (IMR2_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 40 (IMR2_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 39 (IMR2_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 38 (IMR2_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 37 (IMR2_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 36 (IMR2_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 35 (IMR2_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 34 (IMR2_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 33 (IMR2_WRITE_POL_33): Bit
0h
33 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 32 (IMR2_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 31 (IMR2_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.

418 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR2 Write Access Policy 30 (IMR2_WRITE_POL_30): Bit

0h
30 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 29 (IMR2_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 28 (IMR2_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 27 (IMR2_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 26 (IMR2_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 25 (IMR2_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 24 (IMR2_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 23 (IMR2_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 22 (IMR2_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 21 (IMR2_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 20 (IMR2_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 19 (IMR2_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 18 (IMR2_WRITE_POL_18): Bit
0h
18 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 17 (IMR2_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 16 (IMR2_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.

334818 419
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR2 Write Access Policy 15 (IMR2_WRITE_POL_15): Bit

0h
15 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 14 (IMR2_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 13 (IMR2_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 12 (IMR2_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 11 (IMR2_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 10 (IMR2_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 9 (IMR2_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 8 (IMR2_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 7 (IMR2_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 6 (IMR2_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 5 (IMR2_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 4 (IMR2_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 3 (IMR2_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 2 (IMR2_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.
IMR2 Write Access Policy 1 (IMR2_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.

420 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR2 Write Access Policy 0 (IMR2_WRITE_POL_0): Bit

0h
0 vector used to determine which agents are allowed write access to
RW
the IMR2 region, based on each agent's 6bit encoded SAI value.

5.9.18 IMR3 Base (B_CR_BIMR3BASE_0_0_0_MCHBAR)—Offset

68D0h
This register, along with IMR3MASK, IMR3RAC and IMR3WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR3RAC and IMR3WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR3_BASE
IMR_EN
TR_EN
RESERVED_1

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

Base 0 IMR3 Base (IMR3_BASE): Specifies bits 38:10 of the

start address of IMR3 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR3MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR3 defined region.

334818 421
 MCHBAR

5.9.19 IMR3 Mask (B_CR_BIMR3MASK_0_0_0_MCHBAR)—Offset

68D4h
This register, along with IMR3BASE, IMR3RAC and IMR3WAC, defines an isolated region
of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR3RAC and IMR3WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IMR3_MASK
IA_IWB_EN
GT_IWB_EN

RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 HITM data from GT to be returned to the requester. When set to 0,
RW
inhibits HITM data from GT from being returned to the requester.
HITM data from IA cores may be returned to the requester
depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit Writeback Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 HITM data from IA cores to be returned to the requester. When set
RW
to 0, inhibits HITM data from IA cores from being returned to the
requester. HITM data from GT may be returned to the requester
depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR3 Mask (IMR3_MASK): These bits are ANDed with

0h bits 38:10 of the incoming address to determine if the combined
28:0
RW result matches the IMR3BASE[28:0] value. A match indicates that
the incoming address falls within the IMR3 region.

422 334818
MCHBAR

5.9.20 IMR3 Control Policy (B_CR_BIMR3CP_0_0_0_MCHBAR)—

Offset 68D8h
This register controls the access policy to the Read Access Policy BIMR3RAC, the Write
Access Policy BIMR3WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010

IMR3_CTRL_POL

Bit Default &

Field Name (ID): Description
Range Access

IMR3 Control Policy (IMR3_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR3RAC,
63:0
RW BIMR3WAC and BIMR3CP registers, based on the value from each
agent's 6bit SAI field.

5.9.21 IMR3 Read Access Policy

(B_CR_BIMR3RAC_0_0_0_MCHBAR)—Offset 68E0h
This register, along with IMR3BASE, IMR3MASK and IMR3WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000

334818 423
 MCHBAR

IMR3_READ_POL_63
IMR3_READ_POL_62
IMR3_READ_POL_61
IMR3_READ_POL_60
IMR3_READ_POL_59
IMR3_READ_POL_58
IMR3_READ_POL_57
IMR3_READ_POL_56
IMR3_READ_POL_55
IMR3_READ_POL_54
IMR3_READ_POL_53
IMR3_READ_POL_52
IMR3_READ_POL_51
IMR3_READ_POL_50
IMR3_READ_POL_49
IMR3_READ_POL_48
IMR3_READ_POL_47
IMR3_READ_POL_46
IMR3_READ_POL_45
IMR3_READ_POL_44
IMR3_READ_POL_43
IMR3_READ_POL_42
IMR3_READ_POL_41
IMR3_READ_POL_40
IMR3_READ_POL_39
IMR3_READ_POL_38
IMR3_READ_POL_37
IMR3_READ_POL_36
IMR3_READ_POL_35
IMR3_READ_POL_34
IMR3_READ_POL_33
IMR3_READ_POL_32
IMR3_READ_POL_31
IMR3_READ_POL_30
IMR3_READ_POL_29
IMR3_READ_POL_28
IMR3_READ_POL_27
IMR3_READ_POL_26
IMR3_READ_POL_25
IMR3_READ_POL_24
IMR3_READ_POL_23
IMR3_READ_POL_22
IMR3_READ_POL_21
IMR3_READ_POL_20
IMR3_READ_POL_19
IMR3_READ_POL_18
IMR3_READ_POL_17
IMR3_READ_POL_16
IMR3_READ_POL_15
IMR3_READ_POL_14
IMR3_READ_POL_13
IMR3_READ_POL_12
IMR3_READ_POL_11
IMR3_READ_POL_10
IMR3_READ_POL_9
IMR3_READ_POL_8
IMR3_READ_POL_7
IMR3_READ_POL_6
IMR3_READ_POL_5
IMR3_READ_POL_4
IMR3_READ_POL_3
IMR3_READ_POL_2
IMR3_READ_POL_1
IMR3_READ_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR3 Read Access Policy 63 (IMR3_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 62 (IMR3_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 61 (IMR3_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 60 (IMR3_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 59 (IMR3_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 58 (IMR3_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 57 (IMR3_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 56 (IMR3_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 55 (IMR3_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 54 (IMR3_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 53 (IMR3_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 52 (IMR3_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.

424 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR3 Read Access Policy 51 (IMR3_READ_POL_51): Bit

0h
51 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 50 (IMR3_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 49 (IMR3_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 48 (IMR3_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 47 (IMR3_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 46 (IMR3_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 45 (IMR3_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 44 (IMR3_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 43 (IMR3_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 42 (IMR3_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 41 (IMR3_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 40 (IMR3_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 39 (IMR3_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 38 (IMR3_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 37 (IMR3_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.

334818 425
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR3 Read Access Policy 36 (IMR3_READ_POL_36): Bit

0h
36 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 35 (IMR3_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 34 (IMR3_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 33 (IMR3_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 32 (IMR3_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 31 (IMR3_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 30 (IMR3_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 29 (IMR3_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 28 (IMR3_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 27 (IMR3_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 26 (IMR3_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 25 (IMR3_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 24 (IMR3_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 23 (IMR3_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 22 (IMR3_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.

426 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR3 Read Access Policy 21 (IMR3_READ_POL_21): Bit

0h
21 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 20 (IMR3_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 19 (IMR3_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 18 (IMR3_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 17 (IMR3_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 16 (IMR3_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 15 (IMR3_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 14 (IMR3_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 13 (IMR3_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 12 (IMR3_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 11 (IMR3_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 10 (IMR3_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 9 (IMR3_READ_POL_9): Bit vector
0h
9 used to determine which agents are allowed read access to the
RO
IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 8 (IMR3_READ_POL_8): Bit vector
0h
8 used to determine which agents are allowed read access to the
RW
IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 7 (IMR3_READ_POL_7): Bit vector
0h
7 used to determine which agents are allowed read access to the
RO
IMR3 region, based on each agent's 6bit encoded SAI value.

334818 427
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR3 Read Access Policy 6 (IMR3_READ_POL_6): Bit vector

0h
6 used to determine which agents are allowed read access to the
RO
IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 5 (IMR3_READ_POL_5): Bit vector
0h
5 used to determine which agents are allowed read access to the
RW
IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 4 (IMR3_READ_POL_4): Bit vector
0h
4 used to determine which agents are allowed read access to the
RW
IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 3 (IMR3_READ_POL_3): Bit vector
0h
3 used to determine which agents are allowed read access to the
RW
IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 2 (IMR3_READ_POL_2): Bit vector
0h
2 used to determine which agents are allowed read access to the
RW
IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 1 (IMR3_READ_POL_1): Bit vector
0h
1 used to determine which agents are allowed read access to the
RW
IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Read Access Policy 0 (IMR3_READ_POL_0): Bit vector
0h
0 used to determine which agents are allowed read access to the
RW
IMR3 region, based on each agent's 6bit encoded SAI value.

5.9.22 IMR3 Write Access Policy

(B_CR_BIMR3WAC_0_0_0_MCHBAR)—Offset 68E8h
This register, along with IMR3BASE, IMR3MASK and IMR3RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR3_WRITE_POL_63
IMR3_WRITE_POL_62
IMR3_WRITE_POL_61
IMR3_WRITE_POL_60
IMR3_WRITE_POL_59
IMR3_WRITE_POL_58
IMR3_WRITE_POL_57
IMR3_WRITE_POL_56
IMR3_WRITE_POL_55
IMR3_WRITE_POL_54
IMR3_WRITE_POL_53
IMR3_WRITE_POL_52
IMR3_WRITE_POL_51
IMR3_WRITE_POL_50
IMR3_WRITE_POL_49
IMR3_WRITE_POL_48
IMR3_WRITE_POL_47
IMR3_WRITE_POL_46
IMR3_WRITE_POL_45
IMR3_WRITE_POL_44
IMR3_WRITE_POL_43
IMR3_WRITE_POL_42
IMR3_WRITE_POL_41
IMR3_WRITE_POL_40
IMR3_WRITE_POL_39
IMR3_WRITE_POL_38
IMR3_WRITE_POL_37
IMR3_WRITE_POL_36
IMR3_WRITE_POL_35
IMR3_WRITE_POL_34
IMR3_WRITE_POL_33
IMR3_WRITE_POL_32
IMR3_WRITE_POL_31
IMR3_WRITE_POL_30
IMR3_WRITE_POL_29
IMR3_WRITE_POL_28
IMR3_WRITE_POL_27
IMR3_WRITE_POL_26
IMR3_WRITE_POL_25
IMR3_WRITE_POL_24
IMR3_WRITE_POL_23
IMR3_WRITE_POL_22
IMR3_WRITE_POL_21
IMR3_WRITE_POL_20
IMR3_WRITE_POL_19
IMR3_WRITE_POL_18
IMR3_WRITE_POL_17
IMR3_WRITE_POL_16
IMR3_WRITE_POL_15
IMR3_WRITE_POL_14
IMR3_WRITE_POL_13
IMR3_WRITE_POL_12
IMR3_WRITE_POL_11
IMR3_WRITE_POL_10
IMR3_WRITE_POL_9
IMR3_WRITE_POL_8
IMR3_WRITE_POL_7
IMR3_WRITE_POL_6
IMR3_WRITE_POL_5
IMR3_WRITE_POL_4
IMR3_WRITE_POL_3
IMR3_WRITE_POL_2
IMR3_WRITE_POL_1
IMR3_WRITE_POL_0

428 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR3 Write Access Policy 63 (IMR3_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 62 (IMR3_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 61 (IMR3_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 60 (IMR3_WRITE_POL_60): Bit
0h
60 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 59 (IMR3_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 58 (IMR3_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 57 (IMR3_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 56 (IMR3_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 55 (IMR3_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 54 (IMR3_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 53 (IMR3_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 52 (IMR3_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 51 (IMR3_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 50 (IMR3_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 49 (IMR3_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.

334818 429
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR3 Write Access Policy 48 (IMR3_WRITE_POL_48): Bit

0h
48 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 47 (IMR3_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 46 (IMR3_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 45 (IMR3_WRITE_POL_45): Bit
0h
45 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 44 (IMR3_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 43 (IMR3_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 42 (IMR3_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 41 (IMR3_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 40 (IMR3_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 39 (IMR3_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 38 (IMR3_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 37 (IMR3_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 36 (IMR3_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 35 (IMR3_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 34 (IMR3_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.

430 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR3 Write Access Policy 33 (IMR3_WRITE_POL_33): Bit

0h
33 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 32 (IMR3_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 31 (IMR3_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 30 (IMR3_WRITE_POL_30): Bit
0h
30 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 29 (IMR3_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 28 (IMR3_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 27 (IMR3_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 26 (IMR3_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 25 (IMR3_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 24 (IMR3_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 23 (IMR3_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 22 (IMR3_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 21 (IMR3_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 20 (IMR3_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 19 (IMR3_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.

334818 431
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Bit Default &

Field Name (ID): Description
Range Access

IMR3 Write Access Policy 18 (IMR3_WRITE_POL_18): Bit

0h
18 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 17 (IMR3_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 16 (IMR3_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 15 (IMR3_WRITE_POL_15): Bit
0h
15 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 14 (IMR3_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 13 (IMR3_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 12 (IMR3_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 11 (IMR3_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 10 (IMR3_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 9 (IMR3_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 8 (IMR3_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 7 (IMR3_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 6 (IMR3_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 5 (IMR3_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 4 (IMR3_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.

432 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR3 Write Access Policy 3 (IMR3_WRITE_POL_3): Bit

0h
3 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 2 (IMR3_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 1 (IMR3_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.
IMR3 Write Access Policy 0 (IMR3_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the IMR3 region, based on each agent's 6bit encoded SAI value.

5.9.23 IMR4 Base (B_CR_BIMR4BASE_0_0_0_MCHBAR)—Offset

68F0h
This register, along with IMR4MASK, IMR4RAC and IMR4WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR4RAC and IMR4WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR4_BASE
IMR_EN
TR_EN
RESERVED_1

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

334818 433
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Base 0 IMR4 Base (IMR4_BASE): Specifies bits 38:10 of the

start address of IMR4 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR4MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR4 defined region.

5.9.24 IMR4 Mask (B_CR_BIMR4MASK_0_0_0_MCHBAR)—Offset

68F4h
This register, along with IMR4BASE, IMR4RAC and IMR4WAC, defines an isolated region
of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR4RAC and IMR4WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR4_MASK
GT_IWB_EN
IA_IWB_EN
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 HITM data from GT to be returned to the requester. When set to 0,
RW
inhibits HITM data from GT from being returned to the requester.
HITM data from IA cores may be returned to the requester,
depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit Writeback Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 data HITM data from IA cores to be returned to the requester.
RW
When set to 0, inhibits HITM data from IA cores from being
returned to the requester. HITM data from GT may be returned to
the requester, depending on the setting of the GT_IWB_EN bit.

434 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR4 Mask (IMR4_MASK): These bits are ANDed with

0h bits 38:10 of the incoming address to determine if the combined
28:0
RW result matches the IMR4BASE[28:0] value. A match indicates that
the incoming address falls within the IMR4 region.

5.9.25 B-Unit IMR4 Control Policy

(B_CR_BIMR4CP_0_0_0_MCHBAR)—Offset 68F8h
This register controls the access policy to the Read Access Policy BIMR4RAC, the Write
Access Policy BIMR4WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010
IMR4_CTRL_POL

Bit Default &

Field Name (ID): Description
Range Access

B-Unit IMR4 Control Policy (IMR4_CTRL_POL): Bit vector

C0061010
202h
used to determine which agents are allowed access to the
63:0
RW BIMR4RAC, BIMR4WAC and BIMR4CP registers, based on the
value from each agent's 6bit SAI field.

5.9.26 IMR4 Read Access Policy

(B_CR_BIMR4RAC_0_0_0_MCHBAR)—Offset 6900h
This register, along with IMR4BASE, IMR4MASK and IMR4WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

334818 435
 MCHBAR

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR4_READ_POL_63
IMR4_READ_POL_62
IMR4_READ_POL_61
IMR4_READ_POL_60
IMR4_READ_POL_59
IMR4_READ_POL_58
IMR4_READ_POL_57
IMR4_READ_POL_56
IMR4_READ_POL_55
IMR4_READ_POL_54
IMR4_READ_POL_53
IMR4_READ_POL_52
IMR4_READ_POL_51
IMR4_READ_POL_50
IMR4_READ_POL_49
IMR4_READ_POL_48
IMR4_READ_POL_47
IMR4_READ_POL_46
IMR4_READ_POL_45
IMR4_READ_POL_44
IMR4_READ_POL_43
IMR4_READ_POL_42
IMR4_READ_POL_41
IMR4_READ_POL_40
IMR4_READ_POL_39
IMR4_READ_POL_38
IMR4_READ_POL_37
IMR4_READ_POL_36
IMR4_READ_POL_35
IMR4_READ_POL_34
IMR4_READ_POL_33
IMR4_READ_POL_32
IMR4_READ_POL_31
IMR4_READ_POL_30
IMR4_READ_POL_29
IMR4_READ_POL_28
IMR4_READ_POL_27
IMR4_READ_POL_26
IMR4_READ_POL_25
IMR4_READ_POL_24
IMR4_READ_POL_23
IMR4_READ_POL_22
IMR4_READ_POL_21
IMR4_READ_POL_20
IMR4_READ_POL_19
IMR4_READ_POL_18
IMR4_READ_POL_17
IMR4_READ_POL_16
IMR4_READ_POL_15
IMR4_READ_POL_14
IMR4_READ_POL_13
IMR4_READ_POL_12
IMR4_READ_POL_11
IMR4_READ_POL_10
IMR4_READ_POL_9
IMR4_READ_POL_8
IMR4_READ_POL_7
IMR4_READ_POL_6
IMR4_READ_POL_5
IMR4_READ_POL_4
IMR4_READ_POL_3
IMR4_READ_POL_2
IMR4_READ_POL_1
IMR4_READ_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR4 Read Access Policy 63 (IMR4_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 62 (IMR4_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 61 (IMR4_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 60 (IMR4_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 59 (IMR4_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 58 (IMR4_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 57 (IMR4_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 56 (IMR4_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 55 (IMR4_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 54 (IMR4_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.

436 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR4 Read Access Policy 53 (IMR4_READ_POL_53): Bit

0h
53 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 52 (IMR4_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 51 (IMR4_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 50 (IMR4_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 49 (IMR4_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 48 (IMR4_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 47 (IMR4_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 46 (IMR4_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 45 (IMR4_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 44 (IMR4_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 43 (IMR4_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 42 (IMR4_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 41 (IMR4_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 40 (IMR4_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 39 (IMR4_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.

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Bit Default &

Field Name (ID): Description
Range Access

IMR4 Read Access Policy 38 (IMR4_READ_POL_38): Bit

0h
38 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 37 (IMR4_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 36 (IMR4_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 35 (IMR4_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 34 (IMR4_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 33 (IMR4_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 32 (IMR4_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 31 (IMR4_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 30 (IMR4_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 29 (IMR4_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 28 (IMR4_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 27 (IMR4_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 26 (IMR4_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 25 (IMR4_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 24 (IMR4_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.

438 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR4 Read Access Policy 23 (IMR4_READ_POL_23): Bit

0h
23 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 22 (IMR4_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 21 (IMR4_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 20 (IMR4_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 19 (IMR4_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 18 (IMR4_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 17 (IMR4_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 16 (IMR4_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 15 (IMR4_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 14 (IMR4_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 13 (IMR4_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 12 (IMR4_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 11 (IMR4_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 10 (IMR4_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 9 (IMR4_READ_POL_9): Bit vector
0h
9 used to determine which agents are allowed read access to the
RO
IMR4 region, based on each agent's 6bit encoded SAI value.

334818 439
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Bit Default &

Field Name (ID): Description
Range Access

IMR4 Read Access Policy 8 (IMR4_READ_POL_8): Bit vector

0h
8 used to determine which agents are allowed read access to the
RW
IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 7 (IMR4_READ_POL_7): Bit vector
0h
7 used to determine which agents are allowed read access to the
RO
IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 6 (IMR4_READ_POL_6): Bit vector
0h
6 used to determine which agents are allowed read access to the
RO
IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 5 (IMR4_READ_POL_5): Bit vector
0h
5 used to determine which agents are allowed read access to the
RW
IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 4 (IMR4_READ_POL_4): Bit vector
0h
4 used to determine which agents are allowed read access to the
RW
IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 3 (IMR4_READ_POL_3): Bit vector
0h
3 used to determine which agents are allowed read access to the
RW
IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 2 (IMR4_READ_POL_2): Bit vector
0h
2 used to determine which agents are allowed read access to the
RW
IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 1 (IMR4_READ_POL_1): Bit vector
0h
1 used to determine which agents are allowed read access to the
RW
IMR4 region, based on each agent's 6bit encoded SAI value.
IMR4 Read Access Policy 0 (IMR4_READ_POL_0): Bit vector
0h
0 used to determine which agents are allowed read access to the
RW
IMR4 region, based on each agent's 6bit encoded SAI value.

5.9.27 IMR4 Write Access Policy

(B_CR_BIMR4WAC_0_0_0_MCHBAR)—Offset 6908h
This register, along with IMR4BASE, IMR4MASK and IMR4RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000

440 334818
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IMR4_WRITE_POL_63
IMR4_WRITE_POL_62
IMR4_WRITE_POL_61
IMR4_WRITE_POL_60
IMR4_WRITE_POL_59
IMR4_WRITE_POL_58
IMR4_WRITE_POL_57
IMR4_WRITE_POL_56
IMR4_WRITE_POL_55
IMR4_WRITE_POL_54
IMR4_WRITE_POL_53
IMR4_WRITE_POL_52
IMR4_WRITE_POL_51
IMR4_WRITE_POL_50
IMR4_WRITE_POL_49
IMR4_WRITE_POL_48
IMR4_WRITE_POL_47
IMR4_WRITE_POL_46
IMR4_WRITE_POL_45
IMR4_WRITE_POL_44
IMR4_WRITE_POL_43
IMR4_WRITE_POL_42
IMR4_WRITE_POL_41
IMR4_WRITE_POL_40
IMR4_WRITE_POL_39
IMR4_WRITE_POL_38
IMR4_WRITE_POL_37
IMR4_WRITE_POL_36
IMR4_WRITE_POL_35
IMR4_WRITE_POL_34
IMR4_WRITE_POL_33
IMR4_WRITE_POL_32
IMR4_WRITE_POL_31
IMR4_WRITE_POL_30
IMR4_WRITE_POL_29
IMR4_WRITE_POL_28
IMR4_WRITE_POL_27
IMR4_WRITE_POL_26
IMR4_WRITE_POL_25
IMR4_WRITE_POL_24
IMR4_WRITE_POL_23
IMR4_WRITE_POL_22
IMR4_WRITE_POL_21
IMR4_WRITE_POL_20
IMR4_WRITE_POL_19
IMR4_WRITE_POL_18
IMR4_WRITE_POL_17
IMR4_WRITE_POL_16
IMR4_WRITE_POL_15
IMR4_WRITE_POL_14
IMR4_WRITE_POL_13
IMR4_WRITE_POL_12
IMR4_WRITE_POL_11
IMR4_WRITE_POL_10
IMR4_WRITE_POL_9
IMR4_WRITE_POL_8
IMR4_WRITE_POL_7
IMR4_WRITE_POL_6
IMR4_WRITE_POL_5
IMR4_WRITE_POL_4
IMR4_WRITE_POL_3
IMR4_WRITE_POL_2
IMR4_WRITE_POL_1
IMR4_WRITE_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR4_WRITE_POL_63 (IMR4_WRITE_POL_63): B-Unit IMR4

0h Write Access Policy: Bit vector used to determine which agents are
63
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_62 (IMR4_WRITE_POL_62): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
62
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_61 (IMR4_WRITE_POL_61): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
61
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_60 (IMR4_WRITE_POL_60): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
60
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_59 (IMR4_WRITE_POL_59): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
59
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_58 (IMR4_WRITE_POL_58): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
58
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_57 (IMR4_WRITE_POL_57): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
57
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_56 (IMR4_WRITE_POL_56): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
56
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_55 (IMR4_WRITE_POL_55): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
55
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.

334818 441
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Bit Default &

Field Name (ID): Description
Range Access

IMR4_WRITE_POL_54 (IMR4_WRITE_POL_54): B-Unit IMR4

0h Write Access Policy: Bit vector used to determine which agents are
54
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_53 (IMR4_WRITE_POL_53): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
53
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_52 (IMR4_WRITE_POL_52): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
52
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_51 (IMR4_WRITE_POL_51): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
51
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_50 (IMR4_WRITE_POL_50): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
50
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_49 (IMR4_WRITE_POL_49): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
49
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_48 (IMR4_WRITE_POL_48): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
48
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_47 (IMR4_WRITE_POL_47): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
47
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_46 (IMR4_WRITE_POL_46): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
46
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_45 (IMR4_WRITE_POL_45): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
45
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_44 (IMR4_WRITE_POL_44): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
44
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.

442 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR4_WRITE_POL_43 (IMR4_WRITE_POL_43): B-Unit IMR4

0h Write Access Policy: Bit vector used to determine which agents are
43
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_42 (IMR4_WRITE_POL_42): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
42
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_41 (IMR4_WRITE_POL_41): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
41
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_40 (IMR4_WRITE_POL_40): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
40
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_39 (IMR4_WRITE_POL_39): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
39
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_38 (IMR4_WRITE_POL_38): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
38
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_37 (IMR4_WRITE_POL_37): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
37
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_36 (IMR4_WRITE_POL_36): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
36
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_35 (IMR4_WRITE_POL_35): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
35
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_34 (IMR4_WRITE_POL_34): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
34
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_33 (IMR4_WRITE_POL_33): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
33
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.

334818 443
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Bit Default &

Field Name (ID): Description
Range Access

IMR4_WRITE_POL_32 (IMR4_WRITE_POL_32): B-Unit IMR4

0h Write Access Policy: Bit vector used to determine which agents are
32
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_31 (IMR4_WRITE_POL_31): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
31
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_30 (IMR4_WRITE_POL_30): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
30
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_29 (IMR4_WRITE_POL_29): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
29
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_28 (IMR4_WRITE_POL_28): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
28
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_27 (IMR4_WRITE_POL_27): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
27
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_26 (IMR4_WRITE_POL_26): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
26
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_25 (IMR4_WRITE_POL_25): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
25
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_24 (IMR4_WRITE_POL_24): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
24
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_23 (IMR4_WRITE_POL_23): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
23
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_22 (IMR4_WRITE_POL_22): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
22
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.

444 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR4_WRITE_POL_21 (IMR4_WRITE_POL_21): B-Unit IMR4

0h Write Access Policy: Bit vector used to determine which agents are
21
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_20 (IMR4_WRITE_POL_20): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
20
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_19 (IMR4_WRITE_POL_19): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
19
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_18 (IMR4_WRITE_POL_18): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
18
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_17 (IMR4_WRITE_POL_17): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
17
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_16 (IMR4_WRITE_POL_16): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
16
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_15 (IMR4_WRITE_POL_15): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
15
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_14 (IMR4_WRITE_POL_14): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
14
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_13 (IMR4_WRITE_POL_13): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
13
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_12 (IMR4_WRITE_POL_12): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
12
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_11 (IMR4_WRITE_POL_11): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
11
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.

334818 445
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Bit Default &

Field Name (ID): Description
Range Access

IMR4_WRITE_POL_10 (IMR4_WRITE_POL_10): B-Unit IMR4

0h Write Access Policy: Bit vector used to determine which agents are
10
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_9 (IMR4_WRITE_POL_9): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
9
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_8 (IMR4_WRITE_POL_8): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
8
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_7 (IMR4_WRITE_POL_7): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
7
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_6 (IMR4_WRITE_POL_6): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
6
RO allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_5 (IMR4_WRITE_POL_5): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
5
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_4 (IMR4_WRITE_POL_4): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
4
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_3 (IMR4_WRITE_POL_3): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
3
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_2 (IMR4_WRITE_POL_2): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
2
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_1 (IMR4_WRITE_POL_1): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
1
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.
IMR4_WRITE_POL_0 (IMR4_WRITE_POL_0): B-Unit IMR4
0h Write Access Policy: Bit vector used to determine which agents are
0
RW allowed write access to the IMR4 region, based on each agent's
6bit encoded SAI value.

446 334818
MCHBAR

5.9.28 IMR5 Base (B_CR_BIMR5BASE_0_0_0_MCHBAR)—Offset

6910h
This register, along with IMR5MASK, IMR5RAC and IMR5WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR5RAC and IMR5WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IMR5_BASE
RESERVED_1
IMR_EN
TR_EN

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

Base 0 IMR5 Base (IMR5_BASE): Specifies bits 38:10 of the

start address of IMR5 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR5MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR5 defined region.

5.9.29 IMR5 Mask (B_CR_BIMR5MASK_0_0_0_MCHBAR)—Offset

6914h
This register, along with IMR5BASE, IMR5RAC and IMR5WAC, defines an isolated region
of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR5RAC and IMR5WAC
registers.

334818 447
 MCHBAR

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GT_IWB_EN
IA_IWB_EN
RESERVED_0

IMR5_MASK
Bit Default &
Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 HITM data from GT to be returned to the requester. When set to 0,
RW
inhibits HITM data from GT from being returned to the requester.
HITM data from IA cores may be returned to the requester,
depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit Writeback Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 HITM data from IA cores to be returned to the requester. When set
RW
to 0, inhibits HITM data from IA cores from being returned to the
requester. HITM data from GT may be returned to the requester,
depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR5 Mask (IMR5_MASK): These bits are ANDed with

0h bits 38:10 of the incoming address to determine if the combined
28:0
RW result matches the IMR5BASE[28:0] value. A match indicates that
the incoming address falls within the IMR5 region.

5.9.30 IMR5 Control Policy (B_CR_BIMR5CP_0_0_0_MCHBAR)—

Offset 6918h
This register controls the access policy to the Read Access Policy BIMR5RAC, the Write
Access Policy BIMR5WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

448 334818
MCHBAR

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010

IMR5_CTRL_POL
Bit Default &
Field Name (ID): Description
Range Access

IMR5 Control Policy (IMR5_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR5RAC,
63:0
RW BIMR5WAC and BIMR5CP registers, based on the value from each
agent's 6bit SAI field.

5.9.31 IMR5 Read Access Policy

(B_CR_BIMR5RAC_0_0_0_MCHBAR)—Offset 6920h
This register, along with IMR5BASE, IMR5MASK and IMR5WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR5_READ_POL_63
IMR5_READ_POL_62
IMR5_READ_POL_61
IMR5_READ_POL_60
IMR5_READ_POL_59
IMR5_READ_POL_58
IMR5_READ_POL_57
IMR5_READ_POL_56
IMR5_READ_POL_55
IMR5_READ_POL_54
IMR5_READ_POL_53
IMR5_READ_POL_52
IMR5_READ_POL_51
IMR5_READ_POL_50
IMR5_READ_POL_49
IMR5_READ_POL_48
IMR5_READ_POL_47
IMR5_READ_POL_46
IMR5_READ_POL_45
IMR5_READ_POL_44
IMR5_READ_POL_43
IMR5_READ_POL_42
IMR5_READ_POL_41
IMR5_READ_POL_40
IMR5_READ_POL_39
IMR5_READ_POL_38
IMR5_READ_POL_37
IMR5_READ_POL_36
IMR5_READ_POL_35
IMR5_READ_POL_34
IMR5_READ_POL_33
IMR5_READ_POL_32
IMR5_READ_POL_31
IMR5_READ_POL_30
IMR5_READ_POL_29
IMR5_READ_POL_28
IMR5_READ_POL_27
IMR5_READ_POL_26
IMR5_READ_POL_25
IMR5_READ_POL_24
IMR5_READ_POL_23
IMR5_READ_POL_22
IMR5_READ_POL_21
IMR5_READ_POL_20
IMR5_READ_POL_19
IMR5_READ_POL_18
IMR5_READ_POL_17
IMR5_READ_POL_16
IMR5_READ_POL_15
IMR5_READ_POL_14
IMR5_READ_POL_13
IMR5_READ_POL_12
IMR5_READ_POL_11
IMR5_READ_POL_10
IMR5_READ_POL_9
IMR5_READ_POL_8
IMR5_READ_POL_7
IMR5_READ_POL_6
IMR5_READ_POL_5
IMR5_READ_POL_4
IMR5_READ_POL_3
IMR5_READ_POL_2
IMR5_READ_POL_1
IMR5_READ_POL_0

Bit Default &

Field Name (ID): Description
Range Access

IMR5 Read Access Policy 63 (IMR5_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.

334818 449
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR5 Read Access Policy 62 (IMR5_READ_POL_62): Bit

0h
62 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 61 (IMR5_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 60 (IMR5_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 59 (IMR5_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 58 (IMR5_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 57 (IMR5_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 56 (IMR5_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 55 (IMR5_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 54 (IMR5_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 53 (IMR5_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 52 (IMR5_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 51 (IMR5_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 50 (IMR5_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 49 (IMR5_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 48 (IMR5_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.

450 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR5 Read Access Policy 47 (IMR5_READ_POL_47): Bit

0h
47 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 46 (IMR5_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 45 (IMR5_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 44 (IMR5_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 43 (IMR5_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 42 (IMR5_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 41 (IMR5_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 40 (IMR5_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 39 (IMR5_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 38 (IMR5_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 37 (IMR5_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 36 (IMR5_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 35 (IMR5_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 34 (IMR5_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 33 (IMR5_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.

334818 451
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR5 Read Access Policy 32 (IMR5_READ_POL_32): Bit

0h
32 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 31 (IMR5_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 30 (IMR5_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 29 (IMR5_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 28 (IMR5_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 27 (IMR5_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 26 (IMR5_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 25 (IMR5_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 24 (IMR5_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 23 (IMR5_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 22 (IMR5_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 21 (IMR5_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 20 (IMR5_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 19 (IMR5_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 18 (IMR5_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.

452 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR5 Read Access Policy 17 (IMR5_READ_POL_17): Bit

0h
17 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 16 (IMR5_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 15 (IMR5_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 14 (IMR5_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 13 (IMR5_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 12 (IMR5_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 11 (IMR5_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 10 (IMR5_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 9 (IMR5_READ_POL_9): Bit vector
0h
9 used to determine which agents are allowed read access to the
RO
IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 8 (IMR5_READ_POL_8): Bit vector
0h
8 used to determine which agents are allowed read access to the
RW
IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 7 (IMR5_READ_POL_7): Bit vector
0h
7 used to determine which agents are allowed read access to the
RO
IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 6 (IMR5_READ_POL_6): Bit vector
0h
6 used to determine which agents are allowed read access to the
RO
IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 5 (IMR5_READ_POL_5): Bit vector
0h
5 used to determine which agents are allowed read access to the
RW
IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 4 (IMR5_READ_POL_4): Bit vector
0h
4 used to determine which agents are allowed read access to the
RW
IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 3 (IMR5_READ_POL_3): Bit vector
0h
3 used to determine which agents are allowed read access to the
RW
IMR5 region, based on each agent's 6bit encoded SAI value.

334818 453
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR5 Read Access Policy 2 (IMR5_READ_POL_2): Bit vector

0h
2 used to determine which agents are allowed read access to the
RW
IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 1 (IMR5_READ_POL_1): Bit vector
0h
1 used to determine which agents are allowed read access to the
RW
IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Read Access Policy 0 (IMR5_READ_POL_0): Bit vector
0h
0 used to determine which agents are allowed read access to the
RW
IMR5 region, based on each agent's 6bit encoded SAI value.

5.9.32 IMR5 Write Access Policy

(B_CR_BIMR5WAC_0_0_0_MCHBAR)—Offset 6928h
This register, along with IMR5BASE, IMR5MASK and IMR5RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR5_WRITE_POL_63
IMR5_WRITE_POL_62
IMR5_WRITE_POL_61
IMR5_WRITE_POL_60
IMR5_WRITE_POL_59
IMR5_WRITE_POL_58
IMR5_WRITE_POL_57
IMR5_WRITE_POL_56
IMR5_WRITE_POL_55
IMR5_WRITE_POL_54
IMR5_WRITE_POL_53
IMR5_WRITE_POL_52
IMR5_WRITE_POL_51
IMR5_WRITE_POL_50
IMR5_WRITE_POL_49
IMR5_WRITE_POL_48
IMR5_WRITE_POL_47
IMR5_WRITE_POL_46
IMR5_WRITE_POL_45
IMR5_WRITE_POL_44
IMR5_WRITE_POL_43
IMR5_WRITE_POL_42
IMR5_WRITE_POL_41
IMR5_WRITE_POL_40
IMR5_WRITE_POL_39
IMR5_WRITE_POL_38
IMR5_WRITE_POL_37
IMR5_WRITE_POL_36
IMR5_WRITE_POL_35
IMR5_WRITE_POL_34
IMR5_WRITE_POL_33
IMR5_WRITE_POL_32
IMR5_WRITE_POL_31
IMR5_WRITE_POL_30
IMR5_WRITE_POL_29
IMR5_WRITE_POL_28
IMR5_WRITE_POL_27
IMR5_WRITE_POL_26
IMR5_WRITE_POL_25
IMR5_WRITE_POL_24
IMR5_WRITE_POL_23
IMR5_WRITE_POL_22
IMR5_WRITE_POL_21
IMR5_WRITE_POL_20
IMR5_WRITE_POL_19
IMR5_WRITE_POL_18
IMR5_WRITE_POL_17
IMR5_WRITE_POL_16
IMR5_WRITE_POL_15
IMR5_WRITE_POL_14
IMR5_WRITE_POL_13
IMR5_WRITE_POL_12
IMR5_WRITE_POL_11
IMR5_WRITE_POL_10
IMR5_WRITE_POL_9
IMR5_WRITE_POL_8
IMR5_WRITE_POL_7
IMR5_WRITE_POL_6
IMR5_WRITE_POL_5
IMR5_WRITE_POL_4
IMR5_WRITE_POL_3
IMR5_WRITE_POL_2
IMR5_WRITE_POL_1
IMR5_WRITE_POL_0

Bit Default &

Field Name (ID): Description
Range Access

IMR5 Write Access Policy 63 (IMR5_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 62 (IMR5_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 61 (IMR5_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.

454 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR5 Write Access Policy 60 (IMR5_WRITE_POL_60): Bit

0h
60 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 59 (IMR5_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 58 (IMR5_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 57 (IMR5_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 56 (IMR5_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 55 (IMR5_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 54 (IMR5_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 53 (IMR5_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 52 (IMR5_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 51 (IMR5_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 50 (IMR5_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 49 (IMR5_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 48 (IMR5_WRITE_POL_48): Bit
0h
48 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 47 (IMR5_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 46 (IMR5_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.

334818 455
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR5 Write Access Policy 45 (IMR5_WRITE_POL_45): Bit

0h
45 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 44 (IMR5_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 43 (IMR5_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 42 (IMR5_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 41 (IMR5_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 40 (IMR5_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 39 (IMR5_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 38 (IMR5_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 37 (IMR5_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 36 (IMR5_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 35 (IMR5_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 34 (IMR5_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 33 (IMR5_WRITE_POL_33): Bit
0h
33 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 32 (IMR5_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 31 (IMR5_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.

456 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR5 Write Access Policy 30 (IMR5_WRITE_POL_30): Bit

0h
30 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 29 (IMR5_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 28 (IMR5_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 27 (IMR5_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 26 (IMR5_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 25 (IMR5_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 24 (IMR5_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 23 (IMR5_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 22 (IMR5_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 21 (IMR5_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 20 (IMR5_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 19 (IMR5_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 18 (IMR5_WRITE_POL_18): Bit
0h
18 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 17 (IMR5_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 16 (IMR5_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.

334818 457
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Bit Default &

Field Name (ID): Description
Range Access

IMR5 Write Access Policy 15 (IMR5_WRITE_POL_15): Bit

0h
15 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 14 (IMR5_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 13 (IMR5_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 12 (IMR5_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 11 (IMR5_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 10 (IMR5_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 9 (IMR5_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 8 (IMR5_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 7 (IMR5_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 6 (IMR5_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 5 (IMR5_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 4 (IMR5_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 3 (IMR5_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 2 (IMR5_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.
IMR5 Write Access Policy 1 (IMR5_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.

458 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR5 Write Access Policy 0 (IMR5_WRITE_POL_0): Bit

0h
0 vector used to determine which agents are allowed write access to
RW
the IMR5 region, based on each agent's 6bit encoded SAI value.

5.9.33 IMR6 Base (B_CR_BIMR6BASE_0_0_0_MCHBAR)—Offset

6930h
This register, along with IMR6MASK, IMR6RAC and IMR6WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR6RAC and IMR6WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR6_BASE
IMR_EN
TR_EN
RESERVED_1

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

Base 0 IMR6 Base (IMR6_BASE): Specifies bits 38:10 of the

start address of IMR6 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR6MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR6 defined region.

334818 459
 MCHBAR

5.9.34 IMR6 Mask (B_CR_BIMR6MASK_0_0_0_MCHBAR)—Offset

6934h
This register, along with IMR6BASE, IMR6RAC and IMR6WAC, defines an isolated region
of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR6RAC and IMR6WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IMR6_MASK
IA_IWB_EN
GT_IWB_EN

RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit WB Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 HITM data from GT to be returned to the requester. When set to 0,
RW
inhibits HITM data from GT from being returned to the requester.
HITM data from IA cores may be returned to the requester,
depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit WB Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 HITM data from IA cores to be returned to the requester. When set
RW
to 0, inhibits HITM data from IA cores from being returned to the
requester. HITM data from GT may be returned to the requester,
depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR6 Mask (IMR6_MASK): These bits are ANDed with

0h bits 38:10 of the incoming address to determine if the combined
28:0
RW result matches the IMR6BASE[28:0] value. A match indicates that
the incoming address falls within the IMR6 region.

460 334818
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5.9.35 IMR6 Control Policy (B_CR_BIMR6CP_0_0_0_MCHBAR)—

Offset 6938h
This register controls the access policy to the Read Access Policy BIMR6RAC, the Write
Access Policy BIMR6WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010

IMR6_CTRL_POL

Bit Default &

Field Name (ID): Description
Range Access

IMR6 Control Policy (IMR6_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR6RAC,
63:0
RW BIMR6WAC, BIMR6CP registers, based on the value from each
agent's 6bit SAI field.

5.9.36 IMR6 Read Access Policy

(B_CR_BIMR6RAC_0_0_0_MCHBAR)—Offset 6940h
This register, along with IMR6BASE, IMR6MASK and IMR6WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000

334818 461
 MCHBAR

IMR6_READ_POL_63
IMR6_READ_POL_62
IMR6_READ_POL_61
IMR6_READ_POL_60
IMR6_READ_POL_59
IMR6_READ_POL_58
IMR6_READ_POL_57
IMR6_READ_POL_56
IMR6_READ_POL_55
IMR6_READ_POL_54
IMR6_READ_POL_53
IMR6_READ_POL_52
IMR6_READ_POL_51
IMR6_READ_POL_50
IMR6_READ_POL_49
IMR6_READ_POL_48
IMR6_READ_POL_47
IMR6_READ_POL_46
IMR6_READ_POL_45
IMR6_READ_POL_44
IMR6_READ_POL_43
IMR6_READ_POL_42
IMR6_READ_POL_41
IMR6_READ_POL_40
IMR6_READ_POL_39
IMR6_READ_POL_38
IMR6_READ_POL_37
IMR6_READ_POL_36
IMR6_READ_POL_35
IMR6_READ_POL_34
IMR6_READ_POL_33
IMR6_READ_POL_32
IMR6_READ_POL_31
IMR6_READ_POL_30
IMR6_READ_POL_29
IMR6_READ_POL_28
IMR6_READ_POL_27
IMR6_READ_POL_26
IMR6_READ_POL_25
IMR6_READ_POL_24
IMR6_READ_POL_23
IMR6_READ_POL_22
IMR6_READ_POL_21
IMR6_READ_POL_20
IMR6_READ_POL_19
IMR6_READ_POL_18
IMR6_READ_POL_17
IMR6_READ_POL_16
IMR6_READ_POL_15
IMR6_READ_POL_14
IMR6_READ_POL_13
IMR6_READ_POL_12
IMR6_READ_POL_11
IMR6_READ_POL_10
IMR6_READ_POL_9
IMR6_READ_POL_8
IMR6_READ_POL_7
IMR6_READ_POL_6
IMR6_READ_POL_5
IMR6_READ_POL_4
IMR6_READ_POL_3
IMR6_READ_POL_2
IMR6_READ_POL_1
IMR6_READ_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR6 Read Access Policy 63 (IMR6_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 62 (IMR6_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 61 (IMR6_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 60 (IMR6_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 59 (IMR6_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 58 (IMR6_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 57 (IMR6_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 56 (IMR6_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 55 (IMR6_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 54 (IMR6_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 53 (IMR6_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 52 (IMR6_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.

462 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR6 Read Access Policy 51 (IMR6_READ_POL_51): Bit

0h
51 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 50 (IMR6_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 49 (IMR6_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 48 (IMR6_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 47 (IMR6_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 46 (IMR6_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 45 (IMR6_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 44 (IMR6_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 43 (IMR6_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 42 (IMR6_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 41 (IMR6_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 40 (IMR6_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 39 (IMR6_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 38 (IMR6_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 37 (IMR6_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.

334818 463
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Bit Default &

Field Name (ID): Description
Range Access

IMR6 Read Access Policy 36 (IMR6_READ_POL_36): Bit

0h
36 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 35 (IMR6_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 34 (IMR6_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 33 (IMR6_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 32 (IMR6_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 31 (IMR6_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 30 (IMR6_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 29 (IMR6_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 28 (IMR6_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 27 (IMR6_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 26 (IMR6_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 25 (IMR6_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 24 (IMR6_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 23 (IMR6_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 22 (IMR6_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.

464 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR6 Read Access Policy 21 (IMR6_READ_POL_21): Bit

0h
21 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 20 (IMR6_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 19 (IMR6_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 18 (IMR6_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 17 (IMR6_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 16 (IMR6_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 15 (IMR6_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 14 (IMR6_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 13 (IMR6_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 12 (IMR6_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 11 (IMR6_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 10 (IMR6_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 9 (IMR6_READ_POL_9): Bit vector
0h
9 used to determine which agents are allowed read access to the
RO
IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 8 (IMR6_READ_POL_8): Bit vector
0h
8 used to determine which agents are allowed read access to the
RW
IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 7 (IMR6_READ_POL_7): Bit vector
0h
7 used to determine which agents are allowed read access to the
RO
IMR6 region, based on each agent's 6bit encoded SAI value.

334818 465
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR6 Read Access Policy 6 (IMR6_READ_POL_6): Bit vector

0h
6 used to determine which agents are allowed read access to the
RO
IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 5 (IMR6_READ_POL_5): Bit vector
0h
5 used to determine which agents are allowed read access to the
RW
IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 4 (IMR6_READ_POL_4): Bit vector
0h
4 used to determine which agents are allowed read access to the
RW
IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 3 (IMR6_READ_POL_3): Bit vector
0h
3 used to determine which agents are allowed read access to the
RW
IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 2 (IMR6_READ_POL_2): Bit vector
0h
2 used to determine which agents are allowed read access to the
RW
IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 1 (IMR6_READ_POL_1): Bit vector
0h
1 used to determine which agents are allowed read access to the
RW
IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Read Access Policy 0 (IMR6_READ_POL_0): Bit vector
0h
0 used to determine which agents are allowed read access to the
RW
IMR6 region, based on each agent's 6bit encoded SAI value.

5.9.37 IMR6 Write Access Policy

(B_CR_BIMR6WAC_0_0_0_MCHBAR)—Offset 6948h
This register, along with IMR6BASE, IMR6MASK and IMR6RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR6_WRITE_POL_63
IMR6_WRITE_POL_62
IMR6_WRITE_POL_61
IMR6_WRITE_POL_60
IMR6_WRITE_POL_59
IMR6_WRITE_POL_58
IMR6_WRITE_POL_57
IMR6_WRITE_POL_56
IMR6_WRITE_POL_55
IMR6_WRITE_POL_54
IMR6_WRITE_POL_53
IMR6_WRITE_POL_52
IMR6_WRITE_POL_51
IMR6_WRITE_POL_50
IMR6_WRITE_POL_49
IMR6_WRITE_POL_48
IMR6_WRITE_POL_47
IMR6_WRITE_POL_46
IMR6_WRITE_POL_45
IMR6_WRITE_POL_44
IMR6_WRITE_POL_43
IMR6_WRITE_POL_42
IMR6_WRITE_POL_41
IMR6_WRITE_POL_40
IMR6_WRITE_POL_39
IMR6_WRITE_POL_38
IMR6_WRITE_POL_37
IMR6_WRITE_POL_36
IMR6_WRITE_POL_35
IMR6_WRITE_POL_34
IMR6_WRITE_POL_33
IMR6_WRITE_POL_32
IMR6_WRITE_POL_31
IMR6_WRITE_POL_30
IMR6_WRITE_POL_29
IMR6_WRITE_POL_28
IMR6_WRITE_POL_27
IMR6_WRITE_POL_26
IMR6_WRITE_POL_25
IMR6_WRITE_POL_24
IMR6_WRITE_POL_23
IMR6_WRITE_POL_22
IMR6_WRITE_POL_21
IMR6_WRITE_POL_20
IMR6_WRITE_POL_19
IMR6_WRITE_POL_18
IMR6_WRITE_POL_17
IMR6_WRITE_POL_16
IMR6_WRITE_POL_15
IMR6_WRITE_POL_14
IMR6_WRITE_POL_13
IMR6_WRITE_POL_12
IMR6_WRITE_POL_11
IMR6_WRITE_POL_10
IMR6_WRITE_POL_9
IMR6_WRITE_POL_8
IMR6_WRITE_POL_7
IMR6_WRITE_POL_6
IMR6_WRITE_POL_5
IMR6_WRITE_POL_4
IMR6_WRITE_POL_3
IMR6_WRITE_POL_2
IMR6_WRITE_POL_1
IMR6_WRITE_POL_0

466 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR6 Write Access Policy 63 (IMR6_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 62 (IMR6_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 61 (IMR6_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 60 (IMR6_WRITE_POL_60): Bit
0h
60 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 59 (IMR6_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 58 (IMR6_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 57 (IMR6_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 56 (IMR6_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 55 (IMR6_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 54 (IMR6_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 53 (IMR6_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 52 (IMR6_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 51 (IMR6_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 50 (IMR6_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 49 (IMR6_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.

334818 467
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR6 Write Access Policy 48 (IMR6_WRITE_POL_48): Bit

0h
48 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 47 (IMR6_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 46 (IMR6_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 45 (IMR6_WRITE_POL_45): Bit
0h
45 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 44 (IMR6_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 43 (IMR6_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 42 (IMR6_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 41 (IMR6_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 40 (IMR6_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 39 (IMR6_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 38 (IMR6_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 37 (IMR6_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 36 (IMR6_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 35 (IMR6_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 34 (IMR6_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.

468 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR6 Write Access Policy 33 (IMR6_WRITE_POL_33): Bit

0h
33 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 32 (IMR6_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 31 (IMR6_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 30 (IMR6_WRITE_POL_30): Bit
0h
30 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 29 (IMR6_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 28 (IMR6_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 27 (IMR6_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 26 (IMR6_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 25 (IMR6_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 24 (IMR6_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 23 (IMR6_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 22 (IMR6_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 21 (IMR6_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 20 (IMR6_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 19 (IMR6_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.

334818 469
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR6 Write Access Policy 18 (IMR6_WRITE_POL_18): Bit

0h
18 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 17 (IMR6_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 16 (IMR6_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 15 (IMR6_WRITE_POL_15): Bit
0h
15 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 14 (IMR6_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 13 (IMR6_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 12 (IMR6_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 11 (IMR6_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 10 (IMR6_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 9 (IMR6_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 8 (IMR6_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 7 (IMR6_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 6 (IMR6_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 5 (IMR6_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 4 (IMR6_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.

470 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR6 Write Access Policy 3 (IMR6_WRITE_POL_3): Bit

0h
3 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 2 (IMR6_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 1 (IMR6_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.
IMR6 Write Access Policy 0 (IMR6_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the IMR6 region, based on each agent's 6bit encoded SAI value.

5.9.38 IMR7 Base (B_CR_BIMR7BASE_0_0_0_MCHBAR)—Offset

6950h
This register, along with IMR7MASK, IMR7RAC and IMR7WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR7RAC and IMR7WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR7_BASE
IMR_EN
TR_EN
RESERVED_1

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

334818 471
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Base 0 IMR7 Base (IMR7_BASE): Specifies bits 38:10 of the

start address of IMR7 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR7MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR7 defined region.

5.9.39 IMR7 Mask (B_CR_BIMR7MASK_0_0_0_MCHBAR)—Offset

6954h
This register, along with IMR7BASE, IMR7RAC and IMR7WAC, defines an isolated region
of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR7RAC and IMR7WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR7_MASK
GT_IWB_EN
IA_IWB_EN
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit WB Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 HITM data from GT to be returned to the requester. When set to 0,
RW
inhibits HITM data from GT from being returned to the requester.
HITM data from IA cores may be returned to the requester,
depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit WB Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 HITM data from IA cores to be returned to the requester. When set
RW
to 0, inhibits HITM data from IA cores from being returned to the
requester. HITM data from GT may be returned to the requester,
depending on the setting of the GT_IWB_EN bit.

472 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR7 Mask (IMR7_MASK): These bits are ANDed with

0h bits 38:10 of the incoming address to determine if the combined
28:0
RW result matches the IMR7BASE[28:0] value. A match indicates that
the incoming address falls within the IMR7 region.

5.9.40 IMR7 Control Policy (B_CR_BIMR7CP_0_0_0_MCHBAR)—

Offset 6958h
This register controls the access policy to the Read Access Policy BIMR7RAC, the Write
Access Policy BIMR7WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010
IMR7_CTRL_POL

Bit Default &

Field Name (ID): Description
Range Access

IMR7 Control Policy (IMR7_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR7RAC,
63:0
RW BIMR7WAC and BIMR7CP registers, based on the value from each
agent's 6bit SAI field.

5.9.41 IMR7 Read Access Policy

(B_CR_BIMR7RAC_0_0_0_MCHBAR)—Offset 6960h
This register, along with IMR7BASE, IMR7MASK and IMR7WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

334818 473
 MCHBAR

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR7_READ_POL_63
IMR7_READ_POL_62
IMR7_READ_POL_61
IMR7_READ_POL_60
IMR7_READ_POL_59
IMR7_READ_POL_58
IMR7_READ_POL_57
IMR7_READ_POL_56
IMR7_READ_POL_55
IMR7_READ_POL_54
IMR7_READ_POL_53
IMR7_READ_POL_52
IMR7_READ_POL_51
IMR7_READ_POL_50
IMR7_READ_POL_49
IMR7_READ_POL_48
IMR7_READ_POL_47
IMR7_READ_POL_46
IMR7_READ_POL_45
IMR7_READ_POL_44
IMR7_READ_POL_43
IMR7_READ_POL_42
IMR7_READ_POL_41
IMR7_READ_POL_40
IMR7_READ_POL_39
IMR7_READ_POL_38
IMR7_READ_POL_37
IMR7_READ_POL_36
IMR7_READ_POL_35
IMR7_READ_POL_34
IMR7_READ_POL_33
IMR7_READ_POL_32
IMR7_READ_POL_31
IMR7_READ_POL_30
IMR7_READ_POL_29
IMR7_READ_POL_28
IMR7_READ_POL_27
IMR7_READ_POL_26
IMR7_READ_POL_25
IMR7_READ_POL_24
IMR7_READ_POL_23
IMR7_READ_POL_22
IMR7_READ_POL_21
IMR7_READ_POL_20
IMR7_READ_POL_19
IMR7_READ_POL_18
IMR7_READ_POL_17
IMR7_READ_POL_16
IMR7_READ_POL_15
IMR7_READ_POL_14
IMR7_READ_POL_13
IMR7_READ_POL_12
IMR7_READ_POL_11
IMR7_READ_POL_10
IMR7_READ_POL_9
IMR7_READ_POL_8
IMR7_READ_POL_7
IMR7_READ_POL_6
IMR7_READ_POL_5
IMR7_READ_POL_4
IMR7_READ_POL_3
IMR7_READ_POL_2
IMR7_READ_POL_1
IMR7_READ_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR7 Read Access Policy 63 (IMR7_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 62 (IMR7_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 61 (IMR7_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 60 (IMR7_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 59 (IMR7_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 58 (IMR7_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 57 (IMR7_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 56 (IMR7_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 55 (IMR7_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 54 (IMR7_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.

474 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR7 Read Access Policy 53 (IMR7_READ_POL_53): Bit

0h
53 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 52 (IMR7_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 51 (IMR7_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 50 (IMR7_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 49 (IMR7_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 48 (IMR7_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 47 (IMR7_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 46 (IMR7_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 45 (IMR7_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 44 (IMR7_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 43 (IMR7_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 42 (IMR7_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 41 (IMR7_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 40 (IMR7_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 39 (IMR7_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.

334818 475
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR7 Read Access Policy 38 (IMR7_READ_POL_38): Bit

0h
38 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 37 (IMR7_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 36 (IMR7_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 35 (IMR7_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 34 (IMR7_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 33 (IMR7_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 32 (IMR7_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 31 (IMR7_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 30 (IMR7_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 29 (IMR7_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 28 (IMR7_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 27 (IMR7_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 26 (IMR7_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 25 (IMR7_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 24 (IMR7_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.

476 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR7 Read Access Policy 23 (IMR7_READ_POL_23): Bit

0h
23 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 22 (IMR7_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 21 (IMR7_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 20 (IMR7_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 19 (IMR7_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 18 (IMR7_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 17 (IMR7_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 16 (IMR7_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 15 (IMR7_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 14 (IMR7_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 13 (IMR7_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 12 (IMR7_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 11 (IMR7_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 10 (IMR7_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 9 (IMR7_READ_POL_9): Bit vector
0h
9 used to determine which agents are allowed read access to the
RO
IMR7 region, based on each agent's 6bit encoded SAI value.

334818 477
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR7 Read Access Policy 8 (IMR7_READ_POL_8): Bit vector

0h
8 used to determine which agents are allowed read access to the
RW
IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 7 (IMR7_READ_POL_7): Bit vector
0h
7 used to determine which agents are allowed read access to the
RO
IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 6 (IMR7_READ_POL_6): Bit vector
0h
6 used to determine which agents are allowed read access to the
RO
IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 5 (IMR7_READ_POL_5): Bit vector
0h
5 used to determine which agents are allowed read access to the
RW
IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 4 (IMR7_READ_POL_4): Bit vector
0h
4 used to determine which agents are allowed read access to the
RW
IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 3 (IMR7_READ_POL_3): Bit vector
0h
3 used to determine which agents are allowed read access to the
RW
IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 2 (IMR7_READ_POL_2): Bit vector
0h
2 used to determine which agents are allowed read access to the
RW
IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 1 (IMR7_READ_POL_1): Bit vector
0h
1 used to determine which agents are allowed read access to the
RW
IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Read Access Policy 0 (IMR7_READ_POL_0): Bit vector
0h
0 used to determine which agents are allowed read access to the
RW
IMR7 region, based on each agent's 6bit encoded SAI value.

5.9.42 IMR7 Write Access Policy

(B_CR_BIMR7WAC_0_0_0_MCHBAR)—Offset 6968h
This register, along with IMR7BASE, IMR7MASK and IMR7RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000

478 334818
MCHBAR

IMR7_WRITE_POL_63
IMR7_WRITE_POL_62
IMR7_WRITE_POL_61
IMR7_WRITE_POL_60
IMR7_WRITE_POL_59
IMR7_WRITE_POL_58
IMR7_WRITE_POL_57
IMR7_WRITE_POL_56
IMR7_WRITE_POL_55
IMR7_WRITE_POL_54
IMR7_WRITE_POL_53
IMR7_WRITE_POL_52
IMR7_WRITE_POL_51
IMR7_WRITE_POL_50
IMR7_WRITE_POL_49
IMR7_WRITE_POL_48
IMR7_WRITE_POL_47
IMR7_WRITE_POL_46
IMR7_WRITE_POL_45
IMR7_WRITE_POL_44
IMR7_WRITE_POL_43
IMR7_WRITE_POL_42
IMR7_WRITE_POL_41
IMR7_WRITE_POL_40
IMR7_WRITE_POL_39
IMR7_WRITE_POL_38
IMR7_WRITE_POL_37
IMR7_WRITE_POL_36
IMR7_WRITE_POL_35
IMR7_WRITE_POL_34
IMR7_WRITE_POL_33
IMR7_WRITE_POL_32
IMR7_WRITE_POL_31
IMR7_WRITE_POL_30
IMR7_WRITE_POL_29
IMR7_WRITE_POL_28
IMR7_WRITE_POL_27
IMR7_WRITE_POL_26
IMR7_WRITE_POL_25
IMR7_WRITE_POL_24
IMR7_WRITE_POL_23
IMR7_WRITE_POL_22
IMR7_WRITE_POL_21
IMR7_WRITE_POL_20
IMR7_WRITE_POL_19
IMR7_WRITE_POL_18
IMR7_WRITE_POL_17
IMR7_WRITE_POL_16
IMR7_WRITE_POL_15
IMR7_WRITE_POL_14
IMR7_WRITE_POL_13
IMR7_WRITE_POL_12
IMR7_WRITE_POL_11
IMR7_WRITE_POL_10
IMR7_WRITE_POL_9
IMR7_WRITE_POL_8
IMR7_WRITE_POL_7
IMR7_WRITE_POL_6
IMR7_WRITE_POL_5
IMR7_WRITE_POL_4
IMR7_WRITE_POL_3
IMR7_WRITE_POL_2
IMR7_WRITE_POL_1
IMR7_WRITE_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR7 Write Access Policy 63 (IMR7_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 62 (IMR7_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 61 (IMR7_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 60 (IMR7_WRITE_POL_60): Bit
0h
60 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 59 (IMR7_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 58 (IMR7_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 57 (IMR7_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 56 (IMR7_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 55 (IMR7_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 54 (IMR7_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 53 (IMR7_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 52 (IMR7_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.

334818 479
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR7 Write Access Policy 51 (IMR7_WRITE_POL_51): Bit

0h
51 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 50 (IMR7_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 49 (IMR7_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 48 (IMR7_WRITE_POL_48): Bit
0h
48 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 47 (IMR7_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 46 (IMR7_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 45 (IMR7_WRITE_POL_45): Bit
0h
45 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 44 (IMR7_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 43 (IMR7_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 42 (IMR7_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 41 (IMR7_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 40 (IMR7_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 39 (IMR7_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 38 (IMR7_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 37 (IMR7_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.

480 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR7 Write Access Policy 36 (IMR7_WRITE_POL_36): Bit

0h
36 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 35 (IMR7_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 34 (IMR7_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 33 (IMR7_WRITE_POL_33): Bit
0h
33 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 32 (IMR7_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 31 (IMR7_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 30 (IMR7_WRITE_POL_30): Bit
0h
30 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 29 (IMR7_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 28 (IMR7_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 27 (IMR7_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 26 (IMR7_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 25 (IMR7_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 24 (IMR7_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 23 (IMR7_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 22 (IMR7_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.

334818 481
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR7 Write Access Policy 21 (IMR7_WRITE_POL_21): Bit

0h
21 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 20 (IMR7_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 19 (IMR7_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 18 (IMR7_WRITE_POL_18): Bit
0h
18 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 17 (IMR7_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 16 (IMR7_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 15 (IMR7_WRITE_POL_15): Bit
0h
15 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 14 (IMR7_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 13 (IMR7_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 12 (IMR7_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 11 (IMR7_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 10 (IMR7_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 9 (IMR7_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 8 (IMR7_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 7 (IMR7_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.

482 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR7 Write Access Policy 6 (IMR7_WRITE_POL_6): Bit

0h
6 vector used to determine which agents are allowed write access to
RO
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 5 (IMR7_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 4 (IMR7_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 3 (IMR7_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 2 (IMR7_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 1 (IMR7_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.
IMR7 Write Access Policy 0 (IMR7_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the IMR7 region, based on each agent's 6bit encoded SAI value.

5.9.43 IMR8 Base (B_CR_BIMR8BASE_0_0_0_MCHBAR)—Offset

6970h
This register, along with IMR8MASK, IMR8RAC and IMR8WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR8RAC and IMR8WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR8_BASE
IMR_EN
TR_EN
RESERVED_1

334818 483
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

Base 0 IMR8 Base (IMR8_BASE): Specifies bits 38:10 of the

start address of IMR8 region. IMR region size must be a strict
0h power of two at least 1KB and naturally aligned to the size. These
28:0
RW bits are compared with the result of the IMR8MASK[28:0] applied
to bits 38:10 of the incoming address to determine if an access
falls within the IMR8 defined region.

5.9.44 IMR8 Mask (B_CR_BIMR8MASK_0_0_0_MCHBAR)—Offset

6974h
This register, along with IMR8BASE, IMR8RAC and IMR8WAC, defines an isolated region
of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR8RAC and IMR8WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR8_MASK
GT_IWB_EN
IA_IWB_EN
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 HITM data from GT to be returned to the requester. When set to 0,
RW
inhibits HITM data from GT from being returned to the requester.
HITM data from IA cores may be returned to the requester
depending on the setting of the IA_IWB_EN bit.

484 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[1]: IA Implicit Writeback Enable

(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 data HITM data from IA cores to be returned to the requester.
RW
When set to 0, inhibits HITM data from IA cores from being
returned to the requester. HITM data from GT may be returned to
the requester depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR8 Mask (IMR8_MASK): These bits are ANDed with

0h bits 38:10 of the incoming address to determine if the combined
28:0
RW result matches the IMR8BASE[28:0] value. A match indicates that
the incoming address falls within the IMR8 region.

5.9.45 IMR8 Control Policy (B_CR_BIMR8CP_0_0_0_MCHBAR)—

Offset 6978h
This register controls the access policy to the Read Access Policy BIMR8RAC, the Write
Access Policy BIMR8WAC, and, self-referentially to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010
IMR8_CTRL_POL

Bit Default &

Field Name (ID): Description
Range Access

IMR8 Control Policy (IMR8_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR8RAC,
63:0
RW BIMR8WAC and BIMR8CP registers, based on the value from each
agent's 6bit SAI field.

334818 485
 MCHBAR

5.9.46 IMR8 Read Access Policy

(B_CR_BIMR8RAC_0_0_0_MCHBAR)—Offset 6980h
This register, along with IMR8BASE, IMR8MASK and IMR8WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR8_READ_POL_63
IMR8_READ_POL_62
IMR8_READ_POL_61
IMR8_READ_POL_60
IMR8_READ_POL_59
IMR8_READ_POL_58
IMR8_READ_POL_57
IMR8_READ_POL_56
IMR8_READ_POL_55
IMR8_READ_POL_54
IMR8_READ_POL_53
IMR8_READ_POL_52
IMR8_READ_POL_51
IMR8_READ_POL_50
IMR8_READ_POL_49
IMR8_READ_POL_48
IMR8_READ_POL_47
IMR8_READ_POL_46
IMR8_READ_POL_45
IMR8_READ_POL_44
IMR8_READ_POL_43
IMR8_READ_POL_42
IMR8_READ_POL_41
IMR8_READ_POL_40
IMR8_READ_POL_39
IMR8_READ_POL_38
IMR8_READ_POL_37
IMR8_READ_POL_36
IMR8_READ_POL_35
IMR8_READ_POL_34
IMR8_READ_POL_33
IMR8_READ_POL_32
IMR8_READ_POL_31
IMR8_READ_POL_30
IMR8_READ_POL_29
IMR8_READ_POL_28
IMR8_READ_POL_27
IMR8_READ_POL_26
IMR8_READ_POL_25
IMR8_READ_POL_24
IMR8_READ_POL_23
IMR8_READ_POL_22
IMR8_READ_POL_21
IMR8_READ_POL_20
IMR8_READ_POL_19
IMR8_READ_POL_18
IMR8_READ_POL_17
IMR8_READ_POL_16
IMR8_READ_POL_15
IMR8_READ_POL_14
IMR8_READ_POL_13
IMR8_READ_POL_12
IMR8_READ_POL_11
IMR8_READ_POL_10
IMR8_READ_POL_9
IMR8_READ_POL_8
IMR8_READ_POL_7
IMR8_READ_POL_6
IMR8_READ_POL_5
IMR8_READ_POL_4
IMR8_READ_POL_3
IMR8_READ_POL_2
IMR8_READ_POL_1
IMR8_READ_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR8 Read Access Policy 63 (IMR8_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 62 (IMR8_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 61 (IMR8_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 60 (IMR8_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 59 (IMR8_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 58 (IMR8_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 57 (IMR8_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.

486 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR8 Read Access Policy 56 (IMR8_READ_POL_56): Bit

0h
56 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 55 (IMR8_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 54 (IMR8_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 53 (IMR8_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 52 (IMR8_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 51 (IMR8_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 50 (IMR8_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 49 (IMR8_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 48 (IMR8_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 47 (IMR8_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 46 (IMR8_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 45 (IMR8_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 44 (IMR8_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 43 (IMR8_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 42 (IMR8_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.

334818 487
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR8 Read Access Policy 41 (IMR8_READ_POL_41): Bit

0h
41 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 40 (IMR8_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 39 (IMR8_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 38 (IMR8_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 37 (IMR8_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 36 (IMR8_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 35 (IMR8_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 34 (IMR8_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 33 (IMR8_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 32 (IMR8_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 31 (IMR8_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 30 (IMR8_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 29 (IMR8_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 28 (IMR8_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 27 (IMR8_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.

488 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR8 Read Access Policy 26 (IMR8_READ_POL_26): Bit

0h
26 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 25 (IMR8_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 24 (IMR8_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 23 (IMR8_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 22 (IMR8_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 21 (IMR8_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 20 (IMR8_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 19 (IMR8_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 18 (IMR8_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 17 (IMR8_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 16 (IMR8_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 15 (IMR8_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 14 (IMR8_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 13 (IMR8_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 12 (IMR8_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.

334818 489
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR8 Read Access Policy 11 (IMR8_READ_POL_11): Bit

0h
11 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 10 (IMR8_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 9 (IMR8_READ_POL_9): Bit vector
0h
9 used to determine which agents are allowed read access to the
RO
IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 8 (IMR8_READ_POL_8): Bit vector
0h
8 used to determine which agents are allowed read access to the
RW
IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 7 (IMR8_READ_POL_7): Bit vector
0h
7 used to determine which agents are allowed read access to the
RO
IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 6 (IMR8_READ_POL_6): Bit vector
0h
6 used to determine which agents are allowed read access to the
RO
IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 5 (IMR8_READ_POL_5): Bit vector
0h
5 used to determine which agents are allowed read access to the
RW
IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 4 (IMR8_READ_POL_4): Bit vector
0h
4 used to determine which agents are allowed read access to the
RW
IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 3 (IMR8_READ_POL_3): Bit vector
0h
3 used to determine which agents are allowed read access to the
RW
IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 2 (IMR8_READ_POL_2): Bit vector
0h
2 used to determine which agents are allowed read access to the
RW
IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 1 (IMR8_READ_POL_1): Bit vector
0h
1 used to determine which agents are allowed read access to the
RW
IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Read Access Policy 0 (IMR8_READ_POL_0): Bit vector
0h
0 used to determine which agents are allowed read access to the
RW
IMR8 region, based on each agent's 6bit encoded SAI value.

5.9.47 IMR8 Write Access Policy

(B_CR_BIMR8WAC_0_0_0_MCHBAR)—Offset 6988h
This register, along with IMR8BASE, IMR8MASK and IMR8RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

490 334818
MCHBAR

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR8_WRITE_POL_63
IMR8_WRITE_POL_62
IMR8_WRITE_POL_61
IMR8_WRITE_POL_60
IMR8_WRITE_POL_59
IMR8_WRITE_POL_58
IMR8_WRITE_POL_57
IMR8_WRITE_POL_56
IMR8_WRITE_POL_55
IMR8_WRITE_POL_54
IMR8_WRITE_POL_53
IMR8_WRITE_POL_52
IMR8_WRITE_POL_51
IMR8_WRITE_POL_50
IMR8_WRITE_POL_49
IMR8_WRITE_POL_48
IMR8_WRITE_POL_47
IMR8_WRITE_POL_46
IMR8_WRITE_POL_45
IMR8_WRITE_POL_44
IMR8_WRITE_POL_43
IMR8_WRITE_POL_42
IMR8_WRITE_POL_41
IMR8_WRITE_POL_40
IMR8_WRITE_POL_39
IMR8_WRITE_POL_38
IMR8_WRITE_POL_37
IMR8_WRITE_POL_36
IMR8_WRITE_POL_35
IMR8_WRITE_POL_34
IMR8_WRITE_POL_33
IMR8_WRITE_POL_32
IMR8_WRITE_POL_31
IMR8_WRITE_POL_30
IMR8_WRITE_POL_29
IMR8_WRITE_POL_28
IMR8_WRITE_POL_27
IMR8_WRITE_POL_26
IMR8_WRITE_POL_25
IMR8_WRITE_POL_24
IMR8_WRITE_POL_23
IMR8_WRITE_POL_22
IMR8_WRITE_POL_21
IMR8_WRITE_POL_20
IMR8_WRITE_POL_19
IMR8_WRITE_POL_18
IMR8_WRITE_POL_17
IMR8_WRITE_POL_16
IMR8_WRITE_POL_15
IMR8_WRITE_POL_14
IMR8_WRITE_POL_13
IMR8_WRITE_POL_12
IMR8_WRITE_POL_11
IMR8_WRITE_POL_10
IMR8_WRITE_POL_9
IMR8_WRITE_POL_8
IMR8_WRITE_POL_7
IMR8_WRITE_POL_6
IMR8_WRITE_POL_5
IMR8_WRITE_POL_4
IMR8_WRITE_POL_3
IMR8_WRITE_POL_2
IMR8_WRITE_POL_1
IMR8_WRITE_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR8 Write Access Policy 63 (IMR8_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 62 (IMR8_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 61 (IMR8_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 60 (IMR8_WRITE_POL_60): Bit
0h
60 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 59 (IMR8_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 58 (IMR8_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 57 (IMR8_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 56 (IMR8_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 55 (IMR8_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 54 (IMR8_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.

334818 491
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR8 Write Access Policy 53 (IMR8_WRITE_POL_53): Bit

0h
53 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 52 (IMR8_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 51 (IMR8_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 50 (IMR8_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 49 (IMR8_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 48 (IMR8_WRITE_POL_48): Bit
0h
48 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 47 (IMR8_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 46 (IMR8_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 45 (IMR8_WRITE_POL_45): Bit
0h
45 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 44 (IMR8_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 43 (IMR8_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 42 (IMR8_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 41 (IMR8_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 40 (IMR8_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 39 (IMR8_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.

492 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR8 Write Access Policy 38 (IMR8_WRITE_POL_38): Bit

0h
38 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 37 (IMR8_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 36 (IMR8_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 35 (IMR8_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 34 (IMR8_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 33 (IMR8_WRITE_POL_33): Bit
0h
33 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 32 (IMR8_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 31 (IMR8_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 30 (IMR8_WRITE_POL_30): Bit
0h
30 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 29 (IMR8_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 28 (IMR8_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 27 (IMR8_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 26 (IMR8_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 25 (IMR8_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 24 (IMR8_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.

334818 493
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR8 Write Access Policy 23 (IMR8_WRITE_POL_23): Bit

0h
23 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 22 (IMR8_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 21 (IMR8_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 20 (IMR8_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 19 (IMR8_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 18 (IMR8_WRITE_POL_18): Bit
0h
18 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 17 (IMR8_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 16 (IMR8_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 15 (IMR8_WRITE_POL_15): Bit
0h
15 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 14 (IMR8_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 13 (IMR8_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 12 (IMR8_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 11 (IMR8_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 10 (IMR8_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 9 (IMR8_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.

494 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR8 Write Access Policy 8 (IMR8_WRITE_POL_8): Bit

0h
8 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 7 (IMR8_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 6 (IMR8_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 5 (IMR8_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 4 (IMR8_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 3 (IMR8_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 2 (IMR8_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 1 (IMR8_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.
IMR8 Write Access Policy 0 (IMR8_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the IMR8 region, based on each agent's 6bit encoded SAI value.

5.9.48 IMR9 Base (B_CR_BIMR9BASE_0_0_0_MCHBAR)—Offset

6990h
This register, along with IMR9MASK, IMR9RAC and IMR9WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR9RAC and IMR9WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

334818 495
 MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IMR_EN
TR_EN

IMR9_BASE
RESERVED_1

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

Base 1 IMR9 Base (IMR9_BASE): Specifies bits 38:10 of the

start address of IMR9 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR9MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR9 defined region.

5.9.49 IMR9 Mask (B_CR_BIMR9MASK_0_0_0_MCHBAR)—Offset

6994h
This register, along with IMR9BASE, IMR9RAC and IMR9WAC, defines an isolated region
of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR9RAC and IMR9WAC
registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GT_IWB_EN
IA_IWB_EN

IMR9_MASK
RESERVED_0

496 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 data HITM data from GT to be returned to the requester. When set
RW
to 0, inhibits HITM data from GT from being returned to the
requester. HITM data from IA cores may be returned to the
requester depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit Writeback Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 HITM data from IA cores to be returned to the requester. When set
RW
to 0, inhibits HITM data from IA cores from being returned to the
requester. HITM data from GT may be returned to the requester,
depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 1 IMR9 Mask (IMR9_MASK): These bits are ANDed with

0h bits 38:10 of the incoming address to determine if the combined
28:0
RW result matches the IMR9BASE[28:0] value. A match indicates that
the incoming address falls within the IMR9 region.

5.9.50 IMR9 Control Policy (B_CR_BIMR9CP_0_0_0_MCHBAR)—

Offset 6998h
This register controls the access policy to the Read Access Policy BIMR9RAC, the Write
Access Policy BIMR9WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010
IMR9_CTRL_POL

334818 497
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR9 Control Policy (IMR9_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR9RAC,
63:0
RW BIMR9WAC, BIMR9CP registers based on the value from each
agent's 6bit SAI field.

5.9.51 IMR9 Read Access Policy

(B_CR_BIMR9RAC_0_0_0_MCHBAR)—Offset 69A0h
This register, along with IMR9BASE, IMR9MASK and IMR9WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR9_READ_POL_63
IMR9_READ_POL_62
IMR9_READ_POL_61
IMR9_READ_POL_60
IMR9_READ_POL_59
IMR9_READ_POL_58
IMR9_READ_POL_57
IMR9_READ_POL_56
IMR9_READ_POL_55
IMR9_READ_POL_54
IMR9_READ_POL_53
IMR9_READ_POL_52
IMR9_READ_POL_51
IMR9_READ_POL_50
IMR9_READ_POL_49
IMR9_READ_POL_48
IMR9_READ_POL_47
IMR9_READ_POL_46
IMR9_READ_POL_45
IMR9_READ_POL_44
IMR9_READ_POL_43
IMR9_READ_POL_42
IMR9_READ_POL_41
IMR9_READ_POL_40
IMR9_READ_POL_39
IMR9_READ_POL_38
IMR9_READ_POL_37
IMR9_READ_POL_36
IMR9_READ_POL_35
IMR9_READ_POL_34
IMR9_READ_POL_33
IMR9_READ_POL_32
IMR9_READ_POL_31
IMR9_READ_POL_30
IMR9_READ_POL_29
IMR9_READ_POL_28
IMR9_READ_POL_27
IMR9_READ_POL_26
IMR9_READ_POL_25
IMR9_READ_POL_24
IMR9_READ_POL_23
IMR9_READ_POL_22
IMR9_READ_POL_21
IMR9_READ_POL_20
IMR9_READ_POL_19
IMR9_READ_POL_18
IMR9_READ_POL_17
IMR9_READ_POL_16
IMR9_READ_POL_15
IMR9_READ_POL_14
IMR9_READ_POL_13
IMR9_READ_POL_12
IMR9_READ_POL_11
IMR9_READ_POL_10
IMR9_READ_POL_9
IMR9_READ_POL_8
IMR9_READ_POL_7
IMR9_READ_POL_6
IMR9_READ_POL_5
IMR9_READ_POL_4
IMR9_READ_POL_3
IMR9_READ_POL_2
IMR9_READ_POL_1
IMR9_READ_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR9 Read Access Policy 63 (IMR9_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 62 (IMR9_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 61 (IMR9_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 60 (IMR9_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 59 (IMR9_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.

498 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR9 Read Access Policy 58 (IMR9_READ_POL_58): Bit

0h
58 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 57 (IMR9_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 56 (IMR9_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 55 (IMR9_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 54 (IMR9_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 53 (IMR9_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 52 (IMR9_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 51 (IMR9_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 50 (IMR9_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 49 (IMR9_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 48 (IMR9_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 47 (IMR9_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 46 (IMR9_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 45 (IMR9_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 44 (IMR9_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.

334818 499
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR9 Read Access Policy 43 (IMR9_READ_POL_43): Bit

0h
43 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 42 (IMR9_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 41 (IMR9_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 40 (IMR9_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 39 (IMR9_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 38 (IMR9_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 37 (IMR9_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 36 (IMR9_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 35 (IMR9_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 34 (IMR9_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 33 (IMR9_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 32 (IMR9_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 31 (IMR9_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 30 (IMR9_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 29 (IMR9_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.

500 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR9 Read Access Policy 28 (IMR9_READ_POL_28): Bit

0h
28 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 27 (IMR9_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 26 (IMR9_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 25 (IMR9_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 24 (IMR9_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 23 (IMR9_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 22 (IMR9_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 21 (IMR9_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 20 (IMR9_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 19 (IMR9_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 18 (IMR9_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 17 (IMR9_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 16 (IMR9_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 15 (IMR9_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 14 (IMR9_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.

334818 501
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR9 Read Access Policy 13 (IMR9_READ_POL_13): Bit

0h
13 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 12 (IMR9_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 11 (IMR9_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 10 (IMR9_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 9 (IMR9_READ_POL_9): Bit vector
0h
9 used to determine which agents are allowed read access to the
RO
IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 8 (IMR9_READ_POL_8): Bit vector
0h
8 used to determine which agents are allowed read access to the
RW
IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 7 (IMR9_READ_POL_7): Bit vector
0h
7 used to determine which agents are allowed read access to the
RO
IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 6 (IMR9_READ_POL_6): Bit vector
0h
6 used to determine which agents are allowed read access to the
RO
IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 5 (IMR9_READ_POL_5): Bit vector
0h
5 used to determine which agents are allowed read access to the
RW
IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 4 (IMR9_READ_POL_4): Bit vector
0h
4 used to determine which agents are allowed read access to the
RW
IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 3 (IMR9_READ_POL_3): Bit vector
0h
3 used to determine which agents are allowed read access to the
RW
IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 2 (IMR9_READ_POL_2): Bit vector
0h
2 used to determine which agents are allowed read access to the
RW
IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 1 (IMR9_READ_POL_1): Bit vector
0h
1 used to determine which agents are allowed read access to the
RW
IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Read Access Policy 0 (IMR9_READ_POL_0): Bit vector
0h
0 used to determine which agents are allowed read access to the
RW
IMR9 region, based on each agent's 6bit encoded SAI value.

502 334818
MCHBAR

5.9.52 IMR9 Write Access Policy

(B_CR_BIMR9WAC_0_0_0_MCHBAR)—Offset 69A8h
This register, along with IMR9BASE, IMR9MASK and IMR9RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR9_WRITE_POL_63
IMR9_WRITE_POL_62
IMR9_WRITE_POL_61
IMR9_WRITE_POL_60
IMR9_WRITE_POL_59
IMR9_WRITE_POL_58
IMR9_WRITE_POL_57
IMR9_WRITE_POL_56
IMR9_WRITE_POL_55
IMR9_WRITE_POL_54
IMR9_WRITE_POL_53
IMR9_WRITE_POL_52
IMR9_WRITE_POL_51
IMR9_WRITE_POL_50
IMR9_WRITE_POL_49
IMR9_WRITE_POL_48
IMR9_WRITE_POL_47
IMR9_WRITE_POL_46
IMR9_WRITE_POL_45
IMR9_WRITE_POL_44
IMR9_WRITE_POL_43
IMR9_WRITE_POL_42
IMR9_WRITE_POL_41
IMR9_WRITE_POL_40
IMR9_WRITE_POL_39
IMR9_WRITE_POL_38
IMR9_WRITE_POL_37
IMR9_WRITE_POL_36
IMR9_WRITE_POL_35
IMR9_WRITE_POL_34
IMR9_WRITE_POL_33
IMR9_WRITE_POL_32
IMR9_WRITE_POL_31
IMR9_WRITE_POL_30
IMR9_WRITE_POL_29
IMR9_WRITE_POL_28
IMR9_WRITE_POL_27
IMR9_WRITE_POL_26
IMR9_WRITE_POL_25
IMR9_WRITE_POL_24
IMR9_WRITE_POL_23
IMR9_WRITE_POL_22
IMR9_WRITE_POL_21
IMR9_WRITE_POL_20
IMR9_WRITE_POL_19
IMR9_WRITE_POL_18
IMR9_WRITE_POL_17
IMR9_WRITE_POL_16
IMR9_WRITE_POL_15
IMR9_WRITE_POL_14
IMR9_WRITE_POL_13
IMR9_WRITE_POL_12
IMR9_WRITE_POL_11
IMR9_WRITE_POL_10
IMR9_WRITE_POL_9
IMR9_WRITE_POL_8
IMR9_WRITE_POL_7
IMR9_WRITE_POL_6
IMR9_WRITE_POL_5
IMR9_WRITE_POL_4
IMR9_WRITE_POL_3
IMR9_WRITE_POL_2
IMR9_WRITE_POL_1
IMR9_WRITE_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR9 Write Access Policy 63 (IMR9_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 62 (IMR9_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 61 (IMR9_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 60 (IMR9_WRITE_POL_60): Bit
0h
60 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 59 (IMR9_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 58 (IMR9_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 57 (IMR9_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.

334818 503
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR9 Write Access Policy 56 (IMR9_WRITE_POL_56): Bit

0h
56 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 55 (IMR9_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 54 (IMR9_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 53 (IMR9_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 52 (IMR9_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 51 (IMR9_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 50 (IMR9_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 49 (IMR9_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 48 (IMR9_WRITE_POL_48): Bit
0h
48 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 47 (IMR9_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 46 (IMR9_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 45 (IMR9_WRITE_POL_45): Bit
0h
45 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 44 (IMR9_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 43 (IMR9_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 42 (IMR9_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.

504 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR9 Write Access Policy 41 (IMR9_WRITE_POL_41): Bit

0h
41 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 40 (IMR9_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 39 (IMR9_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 38 (IMR9_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 37 (IMR9_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 36 (IMR9_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 35 (IMR9_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 34 (IMR9_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 33 (IMR9_WRITE_POL_33): Bit
0h
33 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 32 (IMR9_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 31 (IMR9_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 30 (IMR9_WRITE_POL_30): Bit
0h
30 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 29 (IMR9_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 28 (IMR9_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 27 (IMR9_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.

334818 505
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR9 Write Access Policy 26 (IMR9_WRITE_POL_26): Bit

0h
26 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 25 (IMR9_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 24 (IMR9_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 23 (IMR9_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 22 (IMR9_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 21 (IMR9_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 20 (IMR9_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 19 (IMR9_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 18 (IMR9_WRITE_POL_18): Bit
0h
18 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 17 (IMR9_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 16 (IMR9_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 15 (IMR9_WRITE_POL_15): Bit
0h
15 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 14 (IMR9_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 13 (IMR9_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 12 (IMR9_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.

506 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR9 Write Access Policy 11 (IMR9_WRITE_POL_11): Bit

0h
11 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 10 (IMR9_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 9 (IMR9_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 8 (IMR9_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 7 (IMR9_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 6 (IMR9_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 5 (IMR9_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 4 (IMR9_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 3 (IMR9_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 2 (IMR9_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 1 (IMR9_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.
IMR9 Write Access Policy 0 (IMR9_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the IMR9 region, based on each agent's 6bit encoded SAI value.

5.9.53 IMR10 Base (B_CR_BIMR10BASE_0_0_0_MCHBAR)—

Offset 69B0h
This register, along with IMR10MASK, IMR10RAC and IMR10WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or

334818 507
 MCHBAR

from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR10RAC and
IMR10WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR_EN
TR_EN
RESERVED_1

IMR10_BASE
Bit Default &
Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

Base 0 IMR10 Base (IMR10_BASE): Specifies bits 38:10 of the

start address of IMR10 region. IMR region size must be a strict
0h power of two at least 1KB and naturally aligned to the size. These
28:0
RW bits are compared with the result of the IMR10MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR10 defined region.

5.9.54 IMR10 Mask (B_CR_BIMR10MASK_0_0_0_MCHBAR)—

Offset 69B4h
This register, along with IMR10BASE, IMR10RAC and IMR10WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR10RAC and
IMR10WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

508 334818
MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GT_IWB_EN
IA_IWB_EN

IMR10_MASK
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 data HITM data from GT to be returned to the requester. When set
RW
to 0, inhibits HITM data from GT from being returned to the
requester. HITM data from IA cores may be returned to the
requester depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit Writeback Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 data HITM data from IA cores to be returned to the requester.
RW
When set to 0, inhibits HITM data from IA cores from being
returned to the requester. HITM data from GT may be returned to
the requester depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR10 Mask (IMR10_MASK): These bits are ANDed

0h with bits 38:10 of the incoming address to determine if the
28:0
RW combined result matches the IMR10BASE[28:0] value. A match
indicates that the incoming address falls within the IMR10 region.

5.9.55 IMR10 Control Policy

(B_CR_BIMR10CP_0_0_0_MCHBAR)—Offset 69B8h
This register controls the access policy to the Read Access Policy BIMR10RAC, the Write
Access Policy BIMR10WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010

334818 509
 MCHBAR

IMR10_CTRL_POL
Bit Default &
Field Name (ID): Description
Range Access

IMR10 Control Policy (IMR10_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR10RAC,
63:0
RW BIMR10WAC and BIMR10CP, registers based on the value from
each agent's 6bit SAI field.

5.9.56 IMR10 Read Access Policy

(B_CR_BIMR10RAC_0_0_0_MCHBAR)—Offset 69C0h
This register, along with IMR10BASE, IMR10MASK and IMR10WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR10_READ_POL_63
IMR10_READ_POL_62
IMR10_READ_POL_61
IMR10_READ_POL_60
IMR10_READ_POL_59
IMR10_READ_POL_58
IMR10_READ_POL_57
IMR10_READ_POL_56
IMR10_READ_POL_55
IMR10_READ_POL_54
IMR10_READ_POL_53
IMR10_READ_POL_52
IMR10_READ_POL_51
IMR10_READ_POL_50
IMR10_READ_POL_49
IMR10_READ_POL_48
IMR10_READ_POL_47
IMR10_READ_POL_46
IMR10_READ_POL_45
IMR10_READ_POL_44
IMR10_READ_POL_43
IMR10_READ_POL_42
IMR10_READ_POL_41
IMR10_READ_POL_40
IMR10_READ_POL_39
IMR10_READ_POL_38
IMR10_READ_POL_37
IMR10_READ_POL_36
IMR10_READ_POL_35
IMR10_READ_POL_34
IMR10_READ_POL_33
IMR10_READ_POL_32
IMR10_READ_POL_31
IMR10_READ_POL_30
IMR10_READ_POL_29
IMR10_READ_POL_28
IMR10_READ_POL_27
IMR10_READ_POL_26
IMR10_READ_POL_25
IMR10_READ_POL_24
IMR10_READ_POL_23
IMR10_READ_POL_22
IMR10_READ_POL_21
IMR10_READ_POL_20
IMR10_READ_POL_19
IMR10_READ_POL_18
IMR10_READ_POL_17
IMR10_READ_POL_16
IMR10_READ_POL_15
IMR10_READ_POL_14
IMR10_READ_POL_13
IMR10_READ_POL_12
IMR10_READ_POL_11
IMR10_READ_POL_10
IMR10_READ_POL_9
IMR10_READ_POL_8
IMR10_READ_POL_7
IMR10_READ_POL_6
IMR10_READ_POL_5
IMR10_READ_POL_4
IMR10_READ_POL_3
IMR10_READ_POL_2
IMR10_READ_POL_1
IMR10_READ_POL_0

Bit Default &

Field Name (ID): Description
Range Access

IMR10 Read Access Policy 63 (IMR10_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 62 (IMR10_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.

510 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR10 Read Access Policy 61 (IMR10_READ_POL_61): Bit

0h
61 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 60 (IMR10_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 59 (IMR10_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 58 (IMR10_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 57 (IMR10_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 56 (IMR10_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 55 (IMR10_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 54 (IMR10_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 53 (IMR10_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 52 (IMR10_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 51 (IMR10_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 50 (IMR10_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 49 (IMR10_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 48 (IMR10_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 47 (IMR10_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.

334818 511
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR10 Read Access Policy 46 (IMR10_READ_POL_46): Bit

0h
46 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 45 (IMR10_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 44 (IMR10_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 43 (IMR10_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 42 (IMR10_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 41 (IMR10_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 40 (IMR10_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 39 (IMR10_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 38 (IMR10_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 37 (IMR10_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 36 (IMR10_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 35 (IMR10_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 34 (IMR10_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 33 (IMR10_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 32 (IMR10_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.

512 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR10 Read Access Policy 31 (IMR10_READ_POL_31): Bit

0h
31 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 30 (IMR10_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 29 (IMR10_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 28 (IMR10_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 27 (IMR10_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 26 (IMR10_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 25 (IMR10_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 24 (IMR10_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 23 (IMR10_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 22 (IMR10_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 21 (IMR10_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 20 (IMR10_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 19 (IMR10_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 18 (IMR10_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 17 (IMR10_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.

334818 513
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR10 Read Access Policy 16 (IMR10_READ_POL_16): Bit

0h
16 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 15 (IMR10_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 14 (IMR10_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 13 (IMR10_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 12 (IMR10_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 11 (IMR10_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 10 (IMR10_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 9 (IMR10_READ_POL_9): Bit
0h
9 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 8 (IMR10_READ_POL_8): Bit
0h
8 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 7 (IMR10_READ_POL_7): Bit
0h
7 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 6 (IMR10_READ_POL_6): Bit
0h
6 vector used to determine which agents are allowed read access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 5 (IMR10_READ_POL_5): Bit
0h
5 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 4 (IMR10_READ_POL_4): Bit
0h
4 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 3 (IMR10_READ_POL_3): Bit
0h
3 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 2 (IMR10_READ_POL_2): Bit
0h
2 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.

514 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR10 Read Access Policy 1 (IMR10_READ_POL_1): Bit

0h
1 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Read Access Policy 0 (IMR10_READ_POL_0): Bit
0h
0 vector used to determine which agents are allowed read access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.

5.9.57 IMR10 Write Access Policy

(B_CR_BIMR10WAC_0_0_0_MCHBAR)—Offset 69C8h
This register along with IMR10BASE, IMR10MASK and IMR10RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR10_WRITE_POL_63
IMR10_WRITE_POL_62
IMR10_WRITE_POL_61
IMR10_WRITE_POL_60
IMR10_WRITE_POL_59
IMR10_WRITE_POL_58
IMR10_WRITE_POL_57
IMR10_WRITE_POL_56
IMR10_WRITE_POL_55
IMR10_WRITE_POL_54
IMR10_WRITE_POL_53
IMR10_WRITE_POL_52
IMR10_WRITE_POL_51
IMR10_WRITE_POL_50
IMR10_WRITE_POL_49
IMR10_WRITE_POL_48
IMR10_WRITE_POL_47
IMR10_WRITE_POL_46
IMR10_WRITE_POL_45
IMR10_WRITE_POL_44
IMR10_WRITE_POL_43
IMR10_WRITE_POL_42
IMR10_WRITE_POL_41
IMR10_WRITE_POL_40
IMR10_WRITE_POL_39
IMR10_WRITE_POL_38
IMR10_WRITE_POL_37
IMR10_WRITE_POL_36
IMR10_WRITE_POL_35
IMR10_WRITE_POL_34
IMR10_WRITE_POL_33
IMR10_WRITE_POL_32
IMR10_WRITE_POL_31
IMR10_WRITE_POL_30
IMR10_WRITE_POL_29
IMR10_WRITE_POL_28
IMR10_WRITE_POL_27
IMR10_WRITE_POL_26
IMR10_WRITE_POL_25
IMR10_WRITE_POL_24
IMR10_WRITE_POL_23
IMR10_WRITE_POL_22
IMR10_WRITE_POL_21
IMR10_WRITE_POL_20
IMR10_WRITE_POL_19
IMR10_WRITE_POL_18
IMR10_WRITE_POL_17
IMR10_WRITE_POL_16
IMR10_WRITE_POL_15
IMR10_WRITE_POL_14
IMR10_WRITE_POL_13
IMR10_WRITE_POL_12
IMR10_WRITE_POL_11
IMR10_WRITE_POL_10
IMR10_WRITE_POL_9
IMR10_WRITE_POL_8
IMR10_WRITE_POL_7
IMR10_WRITE_POL_6
IMR10_WRITE_POL_5
IMR10_WRITE_POL_4
IMR10_WRITE_POL_3
IMR10_WRITE_POL_2
IMR10_WRITE_POL_1
IMR10_WRITE_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR10 Write Access Policy 63 (IMR10_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 62 (IMR10_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 61 (IMR10_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 60 (IMR10_WRITE_POL_60): Bit
0h
60 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.

334818 515
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Bit Default &

Field Name (ID): Description
Range Access

IMR10 Write Access Policy 59 (IMR10_WRITE_POL_59): Bit

0h
59 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 58 (IMR10_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 57 (IMR10_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 56 (IMR10_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 55 (IMR10_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 54 (IMR10_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 53 (IMR10_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 52 (IMR10_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 51 (IMR10_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 50 (IMR10_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 49 (IMR10_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 48 (IMR10_WRITE_POL_48): Bit
0h
48 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 47 (IMR10_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 46 (IMR10_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 45 (IMR10_WRITE_POL_45): Bit
0h
45 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.

516 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR10 Write Access Policy 44 (IMR10_WRITE_POL_44): Bit

0h
44 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 43 (IMR10_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 42 (IMR10_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 41 (IMR10_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 40 (IMR10_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 39 (IMR10_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 38 (IMR10_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 37 (IMR10_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 36 (IMR10_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 35 (IMR10_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 34 (IMR10_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 33 (IMR10_WRITE_POL_33): Bit
0h
33 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 32 (IMR10_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 31 (IMR10_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 30 (IMR10_WRITE_POL_30): Bit
0h
30 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.

334818 517
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Bit Default &

Field Name (ID): Description
Range Access

IMR10 Write Access Policy 29 (IMR10_WRITE_POL_29): Bit

0h
29 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 28 (IMR10_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 27 (IMR10_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 26 (IMR10_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 25 (IMR10_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 24 (IMR10_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 23 (IMR10_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 22 (IMR10_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 21 (IMR10_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 20 (IMR10_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 19 (IMR10_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 18 (IMR10_WRITE_POL_18): Bit
0h
18 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 17 (IMR10_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 16 (IMR10_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 15 (IMR10_WRITE_POL_15): Bit
0h
15 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.

518 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR10 Write Access Policy 14 (IMR10_WRITE_POL_14): Bit

0h
14 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 13 (IMR10_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 12 (IMR10_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 11 (IMR10_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 10 (IMR10_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 9 (IMR10_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 8 (IMR10_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 7 (IMR10_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 6 (IMR10_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 5 (IMR10_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 4 (IMR10_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 3 (IMR10_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 2 (IMR10_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 1 (IMR10_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.
IMR10 Write Access Policy 0 (IMR10_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the IMR10 region, based on each agent's 6bit encoded SAI value.

334818 519
 MCHBAR

5.9.58 IMR11 Base (B_CR_BIMR11BASE_0_0_0_MCHBAR)—

Offset 69D0h
This register, along with IMR11MASK, IMR11RAC and IMR11WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR11RAC and
IMR11WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IMR11_BASE
RESERVED_1
IMR_EN
TR_EN

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

Base 0 IMR11 Base (IMR11_BASE): Specifies bits 38:10 of the

start address of IMR11 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR11MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR11 defined region.

5.9.59 IMR11 Mask (B_CR_BIMR11MASK_0_0_0_MCHBAR)—

Offset 69D4h
This register, along with IMR11BASE, IMR11RAC and IMR11WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR11RAC and
IMR11WAC registers.

520 334818
MCHBAR

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GT_IWB_EN
IA_IWB_EN
RESERVED_0

IMR11_MASK
Bit Default &
Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 data HITM data from GT to be returned to the requester. When set
RW
to 0, inhibits HITM data from GT from being returned to the
requester. HITM data from IA cores may be returned to the
requester, depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit Writeback Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 data HITM data from IA cores to be returned to the requester.
RW
When set to 0, inhibits HITM data from IA cores from being
returned to the requester. HITM data from GT may be returned to
the requester, depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR11 Mask (IMR11_MASK): These bits are ANDed

0h with bits 38:10 of the incoming address to determine if the
28:0
RW combined result matches the IMR11BASE[28:0] value. A match
indicates that the incoming address falls within the IMR11 region.

5.9.60 IMR11 Control Policy

(B_CR_BIMR11CP_0_0_0_MCHBAR)—Offset 69D8h
This register controls the access policy to the Read Access Policy BIMR11RAC, the Write
Access Policy BIMR11WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

334818 521
 MCHBAR

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010

IMR11_CTRL_POL
Bit Default &
Field Name (ID): Description
Range Access

IMR11 Control Policy (IMR11_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR11RAC,
63:0
RW BIMR11WAC and BIMR11CP registers, based on the value from
each agent's 6bit SAI field.

5.9.61 IMR11 Read Access Policy

(B_CR_BIMR11RAC_0_0_0_MCHBAR)—Offset 69E0h
This register, along with IMR11BASE, IMR11MASK and IMR11WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR11_READ_POL_63
IMR11_READ_POL_62
IMR11_READ_POL_61
IMR11_READ_POL_60
IMR11_READ_POL_59
IMR11_READ_POL_58
IMR11_READ_POL_57
IMR11_READ_POL_56
IMR11_READ_POL_55
IMR11_READ_POL_54
IMR11_READ_POL_53
IMR11_READ_POL_52
IMR11_READ_POL_51
IMR11_READ_POL_50
IMR11_READ_POL_49
IMR11_READ_POL_48
IMR11_READ_POL_47
IMR11_READ_POL_46
IMR11_READ_POL_45
IMR11_READ_POL_44
IMR11_READ_POL_43
IMR11_READ_POL_42
IMR11_READ_POL_41
IMR11_READ_POL_40
IMR11_READ_POL_39
IMR11_READ_POL_38
IMR11_READ_POL_37
IMR11_READ_POL_36
IMR11_READ_POL_35
IMR11_READ_POL_34
IMR11_READ_POL_33
IMR11_READ_POL_32
IMR11_READ_POL_31
IMR11_READ_POL_30
IMR11_READ_POL_29
IMR11_READ_POL_28
IMR11_READ_POL_27
IMR11_READ_POL_26
IMR11_READ_POL_25
IMR11_READ_POL_24
IMR11_READ_POL_23
IMR11_READ_POL_22
IMR11_READ_POL_21
IMR11_READ_POL_20
IMR11_READ_POL_19
IMR11_READ_POL_18
IMR11_READ_POL_17
IMR11_READ_POL_16
IMR11_READ_POL_15
IMR11_READ_POL_14
IMR11_READ_POL_13
IMR11_READ_POL_12
IMR11_READ_POL_11
IMR11_READ_POL_10
IMR11_READ_POL_9
IMR11_READ_POL_8
IMR11_READ_POL_7
IMR11_READ_POL_6
IMR11_READ_POL_5
IMR11_READ_POL_4
IMR11_READ_POL_3
IMR11_READ_POL_2
IMR11_READ_POL_1
IMR11_READ_POL_0

Bit Default &

Field Name (ID): Description
Range Access

IMR11 Read Access Policy 63 (IMR11_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.

522 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR11 Read Access Policy 62 (IMR11_READ_POL_62): Bit

0h
62 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 61 (IMR11_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 60 (IMR11_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 59 (IMR11_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 58 (IMR11_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 57 (IMR11_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 56 (IMR11_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 55 (IMR11_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 54 (IMR11_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 53 (IMR11_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 52 (IMR11_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 51 (IMR11_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 50 (IMR11_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 49 (IMR11_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 48 (IMR11_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.

334818 523
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR11 Read Access Policy 47 (IMR11_READ_POL_47): Bit

0h
47 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 46 (IMR11_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 45 (IMR11_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 44 (IMR11_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 43 (IMR11_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 42 (IMR11_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 41 (IMR11_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 40 (IMR11_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 39 (IMR11_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 38 (IMR11_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 37 (IMR11_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 36 (IMR11_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 35 (IMR11_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 34 (IMR11_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 33 (IMR11_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.

524 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR11 Read Access Policy 32 (IMR11_READ_POL_32): Bit

0h
32 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 31 (IMR11_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 30 (IMR11_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 29 (IMR11_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 28 (IMR11_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 27 (IMR11_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 26 (IMR11_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 25 (IMR11_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 24 (IMR11_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 23 (IMR11_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 22 (IMR11_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 21 (IMR11_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 20 (IMR11_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 19 (IMR11_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 18 (IMR11_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.

334818 525
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Bit Default &

Field Name (ID): Description
Range Access

IMR11 Read Access Policy 17 (IMR11_READ_POL_17): Bit

0h
17 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 16 (IMR11_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 15 (IMR11_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 14 (IMR11_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 13 (IMR11_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 12 (IMR11_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 11 (IMR11_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 10 (IMR11_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 9 (IMR11_READ_POL_9): Bit
0h
9 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 8 (IMR11_READ_POL_8): Bit
0h
8 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 7 (IMR11_READ_POL_7): Bit
0h
7 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 6 (IMR11_READ_POL_6): Bit
0h
6 vector used to determine which agents are allowed read access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 5 (IMR11_READ_POL_5): Bit
0h
5 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 4 (IMR11_READ_POL_4): Bit
0h
4 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 3 (IMR11_READ_POL_3): Bit
0h
3 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.

526 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR11 Read Access Policy 2 (IMR11_READ_POL_2): Bit

0h
2 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 1 (IMR11_READ_POL_1): Bit
0h
1 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Read Access Policy 0 (IMR11_READ_POL_0): Bit
0h
0 vector used to determine which agents are allowed read access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.

5.9.62 IMR11 Write Access Policy

(B_CR_BIMR11WAC_0_0_0_MCHBAR)—Offset 69E8h
This register, along with IMR11BASE, IMR11MASK and IMR11RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR11_WRITE_POL_63
IMR11_WRITE_POL_62
IMR11_WRITE_POL_61
IMR11_WRITE_POL_60
IMR11_WRITE_POL_59
IMR11_WRITE_POL_58
IMR11_WRITE_POL_57
IMR11_WRITE_POL_56
IMR11_WRITE_POL_55
IMR11_WRITE_POL_54
IMR11_WRITE_POL_53
IMR11_WRITE_POL_52
IMR11_WRITE_POL_51
IMR11_WRITE_POL_50
IMR11_WRITE_POL_49
IMR11_WRITE_POL_48
IMR11_WRITE_POL_47
IMR11_WRITE_POL_46
IMR11_WRITE_POL_45
IMR11_WRITE_POL_44
IMR11_WRITE_POL_43
IMR11_WRITE_POL_42
IMR11_WRITE_POL_41
IMR11_WRITE_POL_40
IMR11_WRITE_POL_39
IMR11_WRITE_POL_38
IMR11_WRITE_POL_37
IMR11_WRITE_POL_36
IMR11_WRITE_POL_35
IMR11_WRITE_POL_34
IMR11_WRITE_POL_33
IMR11_WRITE_POL_32
IMR11_WRITE_POL_31
IMR11_WRITE_POL_30
IMR11_WRITE_POL_29
IMR11_WRITE_POL_28
IMR11_WRITE_POL_27
IMR11_WRITE_POL_26
IMR11_WRITE_POL_25
IMR11_WRITE_POL_24
IMR11_WRITE_POL_23
IMR11_WRITE_POL_22
IMR11_WRITE_POL_21
IMR11_WRITE_POL_20
IMR11_WRITE_POL_19
IMR11_WRITE_POL_18
IMR11_WRITE_POL_17
IMR11_WRITE_POL_16
IMR11_WRITE_POL_15
IMR11_WRITE_POL_14
IMR11_WRITE_POL_13
IMR11_WRITE_POL_12
IMR11_WRITE_POL_11
IMR11_WRITE_POL_10
IMR11_WRITE_POL_9
IMR11_WRITE_POL_8
IMR11_WRITE_POL_7
IMR11_WRITE_POL_6
IMR11_WRITE_POL_5
IMR11_WRITE_POL_4
IMR11_WRITE_POL_3
IMR11_WRITE_POL_2
IMR11_WRITE_POL_1
IMR11_WRITE_POL_0

Bit Default &

Field Name (ID): Description
Range Access

IMR11 Write Access Policy 63 (IMR11_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 62 (IMR11_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 61 (IMR11_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.

334818 527
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR11 Write Access Policy 60 (IMR11_WRITE_POL_60): Bit

0h
60 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 59 (IMR11_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 58 (IMR11_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 57 (IMR11_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 56 (IMR11_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 55 (IMR11_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 54 (IMR11_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 53 (IMR11_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 52 (IMR11_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 51 (IMR11_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 50 (IMR11_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 49 (IMR11_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 48 (IMR11_WRITE_POL_48): Bit
0h
48 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 47 (IMR11_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 46 (IMR11_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.

528 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR11 Write Access Policy 45 (IMR11_WRITE_POL_45): Bit

0h
45 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 44 (IMR11_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 43 (IMR11_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 42 (IMR11_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 41 (IMR11_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 40 (IMR11_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 39 (IMR11_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 38 (IMR11_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 37 (IMR11_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 36 (IMR11_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 35 (IMR11_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 34 (IMR11_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 33 (IMR11_WRITE_POL_33): Bit
0h
33 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 32 (IMR11_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 31 (IMR11_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.

334818 529
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR11 Write Access Policy 30 (IMR11_WRITE_POL_30): Bit

0h
30 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 29 (IMR11_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 28 (IMR11_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 27 (IMR11_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 26 (IMR11_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 25 (IMR11_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 24 (IMR11_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 23 (IMR11_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 22 (IMR11_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 21 (IMR11_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 20 (IMR11_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 19 (IMR11_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 18 (IMR11_WRITE_POL_18): Bit
0h
18 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 17 (IMR11_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 16 (IMR11_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.

530 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR11 Write Access Policy 15 (IMR11_WRITE_POL_15): Bit

0h
15 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 14 (IMR11_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 13 (IMR11_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 12 (IMR11_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 11 (IMR11_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 10 (IMR11_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 9 (IMR11_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 8 (IMR11_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 7 (IMR11_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 6 (IMR11_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 5 (IMR11_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 4 (IMR11_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 3 (IMR11_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 2 (IMR11_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.
IMR11 Write Access Policy 1 (IMR11_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.

334818 531
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR11 Write Access Policy 0 (IMR11_WRITE_POL_0): Bit

0h
0 vector used to determine which agents are allowed write access to
RW
the IMR11 region, based on each agent's 6bit encoded SAI value.

5.9.63 IMR12 Base (B_CR_BIMR12BASE_0_0_0_MCHBAR)—

Offset 69F0h
This register, along with IMR12MASK, IMR12RAC and IMR12WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR12RAC and
IMR12WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR12_BASE
IMR_EN
TR_EN
RESERVED_1

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

Base 0 IMR12 Base (IMR12_BASE): Specifies bits 38:10 of the

start address of IMR12 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR12MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR12 defined region.

532 334818
MCHBAR

5.9.64 IMR12 Mask (B_CR_BIMR12MASK_0_0_0_MCHBAR)—

Offset 69F4h
This register, along with IMR12BASE, IMR12RAC and IMR12WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR12RAC and
IMR12WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IMR12_MASK
IA_IWB_EN
GT_IWB_EN

RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 HITM data from GT to be returned to the requester. When set to 0,
RW
inhibits HITM data from GT from being returned to the requester.
HITM data from IA cores may be returned to the requester,
depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit Writeback Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 data HITM data from IA cores to be returned to the requester.
RW
When set to 0, inhibits HITM data from IA cores from being
returned to the requester. HITM data from GT may be returned to
the requester, depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR12 Mask (IMR12_MASK): These bits are ANDed

0h with bits 38:10 of the incoming address to determine if the
28:0
RW combined result matches the IMR12BASE[28:0] value. A match
indicates that the incoming address falls within the IMR12 region.

334818 533
 MCHBAR

5.9.65 IMR12 Control Policy

(B_CR_BIMR12CP_0_0_0_MCHBAR)—Offset 69F8h
This register controls the access policy to the Read Access Policy BIMR12RAC, the Write
Access Policy BIMR12WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010

IMR12_CTRL_POL

Bit Default &

Field Name (ID): Description
Range Access

IMR12 Control Policy (IMR12_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR12RAC,
63:0
RW BIMR12WAC and BIMR12CP registers, based on the value from
each agent's 6bit SAI field.

5.9.66 IMR12 Read Access Policy

(B_CR_BIMR12RAC_0_0_0_MCHBAR)—Offset 6A00h
This register, along with IMR12BASE, IMR12MASK and IMR12WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000

534 334818
MCHBAR

IMR12_READ_POL_63
IMR12_READ_POL_62
IMR12_READ_POL_61
IMR12_READ_POL_60
IMR12_READ_POL_59
IMR12_READ_POL_58
IMR12_READ_POL_57
IMR12_READ_POL_56
IMR12_READ_POL_55
IMR12_READ_POL_54
IMR12_READ_POL_53
IMR12_READ_POL_52
IMR12_READ_POL_51
IMR12_READ_POL_50
IMR12_READ_POL_49
IMR12_READ_POL_48
IMR12_READ_POL_47
IMR12_READ_POL_46
IMR12_READ_POL_45
IMR12_READ_POL_44
IMR12_READ_POL_43
IMR12_READ_POL_42
IMR12_READ_POL_41
IMR12_READ_POL_40
IMR12_READ_POL_39
IMR12_READ_POL_38
IMR12_READ_POL_37
IMR12_READ_POL_36
IMR12_READ_POL_35
IMR12_READ_POL_34
IMR12_READ_POL_33
IMR12_READ_POL_32
IMR12_READ_POL_31
IMR12_READ_POL_30
IMR12_READ_POL_29
IMR12_READ_POL_28
IMR12_READ_POL_27
IMR12_READ_POL_26
IMR12_READ_POL_25
IMR12_READ_POL_24
IMR12_READ_POL_23
IMR12_READ_POL_22
IMR12_READ_POL_21
IMR12_READ_POL_20
IMR12_READ_POL_19
IMR12_READ_POL_18
IMR12_READ_POL_17
IMR12_READ_POL_16
IMR12_READ_POL_15
IMR12_READ_POL_14
IMR12_READ_POL_13
IMR12_READ_POL_12
IMR12_READ_POL_11
IMR12_READ_POL_10
IMR12_READ_POL_9
IMR12_READ_POL_8
IMR12_READ_POL_7
IMR12_READ_POL_6
IMR12_READ_POL_5
IMR12_READ_POL_4
IMR12_READ_POL_3
IMR12_READ_POL_2
IMR12_READ_POL_1
IMR12_READ_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR12 Read Access Policy 63 (IMR12_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 62 (IMR12_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 61 (IMR12_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 60 (IMR12_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 59 (IMR12_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 58 (IMR12_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 57 (IMR12_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 56 (IMR12_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 55 (IMR12_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 54 (IMR12_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 53 (IMR12_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 52 (IMR12_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.

334818 535
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR12 Read Access Policy 51 (IMR12_READ_POL_51): Bit

0h
51 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 50 (IMR12_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 49 (IMR12_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 48 (IMR12_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 47 (IMR12_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 46 (IMR12_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 45 (IMR12_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 44 (IMR12_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 43 (IMR12_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 42 (IMR12_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 41 (IMR12_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 40 (IMR12_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 39 (IMR12_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 38 (IMR12_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 37 (IMR12_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.

536 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR12 Read Access Policy 36 (IMR12_READ_POL_36): Bit

0h
36 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 35 (IMR12_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 34 (IMR12_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 33 (IMR12_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 32 (IMR12_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 31 (IMR12_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 30 (IMR12_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 29 (IMR12_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 28 (IMR12_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 27 (IMR12_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 26 (IMR12_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 25 (IMR12_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 24 (IMR12_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 23 (IMR12_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 22 (IMR12_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.

334818 537
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR12 Read Access Policy 21 (IMR12_READ_POL_21): Bit

0h
21 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 20 (IMR12_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 19 (IMR12_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 18 (IMR12_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 17 (IMR12_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 16 (IMR12_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 15 (IMR12_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 14 (IMR12_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 13 (IMR12_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 12 (IMR12_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 11 (IMR12_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 10 (IMR12_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 9 (IMR12_READ_POL_9): Bit
0h
9 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 8 (IMR12_READ_POL_8): Bit
0h
8 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 7 (IMR12_READ_POL_7): Bit
0h
7 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.

538 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR12 Read Access Policy 6 (IMR12_READ_POL_6): Bit

0h
6 vector used to determine which agents are allowed read access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 5 (IMR12_READ_POL_5): Bit
0h
5 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 4 (IMR12_READ_POL_4): Bit
0h
4 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 3 (IMR12_READ_POL_3): Bit
0h
3 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 2 (IMR12_READ_POL_2): Bit
0h
2 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 1 (IMR12_READ_POL_1): Bit
0h
1 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Read Access Policy 0 (IMR12_READ_POL_0): Bit
0h
0 vector used to determine which agents are allowed read access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.

5.9.67 IMR12 Write Access Policy

(B_CR_BIMR12WAC_0_0_0_MCHBAR)—Offset 6A08h
This register, along with IMR12BASE, IMR12MASK and IMR12RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR12_WRITE_POL_9
IMR12_WRITE_POL_8
IMR12_WRITE_POL_7
IMR12_WRITE_POL_6
IMR12_WRITE_POL_5
IMR12_WRITE_POL_4
IMR12_WRITE_POL_3
IMR12_WRITE_POL_2
IMR12_WRITE_POL_1
IMR12_WRITE_POL_0
IMR12_WRITE_POL_63
IMR12_WRITE_POL_62
IMR12_WRITE_POL_61
IMR12_WRITE_POL_60
IMR12_WRITE_POL_59
IMR12_WRITE_POL_58
IMR12_WRITE_POL_57
IMR12_WRITE_POL_56
IMR12_WRITE_POL_55
IMR12_WRITE_POL_54
IMR12_WRITE_POL_53
IMR12_WRITE_POL_52
IMR12_WRITE_POL_51
IMR12_WRITE_POL_50
IMR12_WRITE_POL_49
IMR12_WRITE_POL_48
IMR12_WRITE_POL_47
IMR12_WRITE_POL_46
IMR12_WRITE_POL_45
IMR12_WRITE_POL_44
IMR12_WRITE_POL_43
IMR12_WRITE_POL_42
IMR12_WRITE_POL_41
IMR12_WRITE_POL_40
IMR12_WRITE_POL_39
IMR12_WRITE_POL_38
IMR12_WRITE_POL_37
IMR12_WRITE_POL_36
IMR12_WRITE_POL_35
IMR12_WRITE_POL_34
IMR12_WRITE_POL_33
IMR12_WRITE_POL_32
IMR12_WRITE_POL_31
IMR12_WRITE_POL_30
IMR12_WRITE_POL_29
IMR12_WRITE_POL_28
IMR12_WRITE_POL_27
IMR12_WRITE_POL_26
IMR12_WRITE_POL_25
IMR12_WRITE_POL_24
IMR12_WRITE_POL_23
IMR12_WRITE_POL_22
IMR12_WRITE_POL_21
IMR12_WRITE_POL_20
IMR12_WRITE_POL_19
IMR12_WRITE_POL_18
IMR12_WRITE_POL_17
IMR12_WRITE_POL_16
IMR12_WRITE_POL_15
IMR12_WRITE_POL_14
IMR12_WRITE_POL_13
IMR12_WRITE_POL_12
IMR12_WRITE_POL_11
IMR12_WRITE_POL_10

334818 539
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR12 Write Access Policy 63 (IMR12_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 62 (IMR12_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 61 (IMR12_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 60 (IMR12_WRITE_POL_60): Bit
0h
60 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 59 (IMR12_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 58 (IMR12_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 57 (IMR12_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 56 (IMR12_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 55 (IMR12_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 54 (IMR12_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 53 (IMR12_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 52 (IMR12_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 51 (IMR12_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 50 (IMR12_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 49 (IMR12_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.

540 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR12 Write Access Policy 48 (IMR12_WRITE_POL_48): Bit

0h
48 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 47 (IMR12_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 46 (IMR12_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 45 (IMR12_WRITE_POL_45): Bit
0h
45 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 44 (IMR12_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 43 (IMR12_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 42 (IMR12_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 41 (IMR12_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 40 (IMR12_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 39 (IMR12_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 38 (IMR12_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 37 (IMR12_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 36 (IMR12_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 35 (IMR12_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 34 (IMR12_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.

334818 541
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR12 Write Access Policy 33 (IMR12_WRITE_POL_33): Bit

0h
33 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 32 (IMR12_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 31 (IMR12_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 30 (IMR12_WRITE_POL_30): Bit
0h
30 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 29 (IMR12_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 28 (IMR12_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 27 (IMR12_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 26 (IMR12_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 25 (IMR12_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 24 (IMR12_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 23 (IMR12_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 22 (IMR12_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 21 (IMR12_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 20 (IMR12_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 19 (IMR12_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.

542 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR12 Write Access Policy 18 (IMR12_WRITE_POL_18): Bit

0h
18 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 17 (IMR12_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 16 (IMR12_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 15 (IMR12_WRITE_POL_15): Bit
0h
15 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 14 (IMR12_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 13 (IMR12_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 12 (IMR12_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 11 (IMR12_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 10 (IMR12_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 9 (IMR12_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 8 (IMR12_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 7 (IMR12_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 6 (IMR12_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 5 (IMR12_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 4 (IMR12_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.

334818 543
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR12 Write Access Policy 3 (IMR12_WRITE_POL_3): Bit

0h
3 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 2 (IMR12_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 1 (IMR12_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.
IMR12 Write Access Policy 0 (IMR12_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the IMR12 region, based on each agent's 6bit encoded SAI value.

5.9.68 IMR13 Base (B_CR_BIMR13BASE_0_0_0_MCHBAR)—

Offset 6A10h
This register, along with IMR13MASK, IMR13RAC and IMR13WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR13RAC and
IMR13WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR13_BASE
IMR_EN
TR_EN
RESERVED_1

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

544 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Base 0 IMR13 Base (IMR13_BASE): Specifies bits 38:10 of the

start address of IMR13 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR13MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR13 defined region.

5.9.69 IMR13 Mask (B_CR_BIMR13MASK_0_0_0_MCHBAR)—

Offset 6A14h
This register, along with IMR13BASE, IMR13RAC and IMR13WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR13RAC and
IMR13WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR13_MASK
GT_IWB_EN
IA_IWB_EN
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 HITM data from GT to be returned to the requester. When set to 0,
RW
inhibits HITM data from GT from being returned to the requester.
HITM data from IA cores may be returned to the requester
depending on the setting of the IA_IWB_EN bit.

334818 545
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[1]: IA Implicit Writeback Enable

(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 data HITM data from IA cores to be returned to the requester.
RW
When set to 0, inhibits HITM data from IA cores from being
returned to the requester. HITM data from GT may be returned to
the requester depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR13 Mask (IMR13_MASK): These bits are ANDed

0h with bits 38:10 of the incoming address to determine if the
28:0
RW combined result matches the IMR13BASE[28:0] value. A match
indicates that the incoming address falls within the IMR13 region.

5.9.70 IMR13 Control Policy

(B_CR_BIMR13CP_0_0_0_MCHBAR)—Offset 6A18h
This register controls the access policy to the Read Access Policy BIMR13RAC, the Write
Access Policy BIMR13WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010
IMR13_CTRL_POL

Bit Default &

Field Name (ID): Description
Range Access

IMR13 Control Policy (IMR13_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR13RAC,
63:0
RW BIMR13WAC and BIMR13CP registers, based on the value from
each agent's 6bit SAI field.

546 334818
MCHBAR

5.9.71 IMR13 Read Access Policy

(B_CR_BIMR13RAC_0_0_0_MCHBAR)—Offset 6A20h
This register, along with IMR13BASE, IMR13MASK and IMR13WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR13_READ_POL_63
IMR13_READ_POL_62
IMR13_READ_POL_61
IMR13_READ_POL_60
IMR13_READ_POL_59
IMR13_READ_POL_58
IMR13_READ_POL_57
IMR13_READ_POL_56
IMR13_READ_POL_55
IMR13_READ_POL_54
IMR13_READ_POL_53
IMR13_READ_POL_52
IMR13_READ_POL_51
IMR13_READ_POL_50
IMR13_READ_POL_49
IMR13_READ_POL_48
IMR13_READ_POL_47
IMR13_READ_POL_46
IMR13_READ_POL_45
IMR13_READ_POL_44
IMR13_READ_POL_43
IMR13_READ_POL_42
IMR13_READ_POL_41
IMR13_READ_POL_40
IMR13_READ_POL_39
IMR13_READ_POL_38
IMR13_READ_POL_37
IMR13_READ_POL_36
IMR13_READ_POL_35
IMR13_READ_POL_34
IMR13_READ_POL_33
IMR13_READ_POL_32
IMR13_READ_POL_31
IMR13_READ_POL_30
IMR13_READ_POL_29
IMR13_READ_POL_28
IMR13_READ_POL_27
IMR13_READ_POL_26
IMR13_READ_POL_25
IMR13_READ_POL_24
IMR13_READ_POL_23
IMR13_READ_POL_22
IMR13_READ_POL_21
IMR13_READ_POL_20
IMR13_READ_POL_19
IMR13_READ_POL_18
IMR13_READ_POL_17
IMR13_READ_POL_16
IMR13_READ_POL_15
IMR13_READ_POL_14
IMR13_READ_POL_13
IMR13_READ_POL_12
IMR13_READ_POL_11
IMR13_READ_POL_10
IMR13_READ_POL_9
IMR13_READ_POL_8
IMR13_READ_POL_7
IMR13_READ_POL_6
IMR13_READ_POL_5
IMR13_READ_POL_4
IMR13_READ_POL_3
IMR13_READ_POL_2
IMR13_READ_POL_1
IMR13_READ_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR13 Read Access Policy 63 (IMR13_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 62 (IMR13_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 61 (IMR13_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 60 (IMR13_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 59 (IMR13_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 58 (IMR13_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 57 (IMR13_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.

334818 547
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR13 Read Access Policy 56 (IMR13_READ_POL_56): Bit

0h
56 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 55 (IMR13_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 54 (IMR13_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 53 (IMR13_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 52 (IMR13_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 51 (IMR13_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 50 (IMR13_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 49 (IMR13_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 48 (IMR13_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 47 (IMR13_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 46 (IMR13_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 45 (IMR13_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 44 (IMR13_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 43 (IMR13_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 42 (IMR13_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.

548 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR13 Read Access Policy 41 (IMR13_READ_POL_41): Bit

0h
41 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 40 (IMR13_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 39 (IMR13_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 38 (IMR13_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 37 (IMR13_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 36 (IMR13_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 35 (IMR13_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 34 (IMR13_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 33 (IMR13_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 32 (IMR13_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 31 (IMR13_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 30 (IMR13_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 29 (IMR13_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 28 (IMR13_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 27 (IMR13_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.

334818 549
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR13 Read Access Policy 26 (IMR13_READ_POL_26): Bit

0h
26 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 25 (IMR13_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 24 (IMR13_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 23 (IMR13_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 22 (IMR13_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 21 (IMR13_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 20 (IMR13_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 19 (IMR13_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 18 (IMR13_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 17 (IMR13_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 16 (IMR13_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 15 (IMR13_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 14 (IMR13_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 13 (IMR13_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 12 (IMR13_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.

550 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR13 Read Access Policy 11 (IMR13_READ_POL_11): Bit

0h
11 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 10 (IMR13_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 9 (IMR13_READ_POL_9): Bit
0h
9 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 8 (IMR13_READ_POL_8): Bit
0h
8 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 7 (IMR13_READ_POL_7): Bit
0h
7 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 6 (IMR13_READ_POL_6): Bit
0h
6 vector used to determine which agents are allowed read access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 5 (IMR13_READ_POL_5): Bit
0h
5 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 4 (IMR13_READ_POL_4): Bit
0h
4 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 3 (IMR13_READ_POL_3): Bit
0h
3 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 2 (IMR13_READ_POL_2): Bit
0h
2 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 1 (IMR13_READ_POL_1): Bit
0h
1 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Read Access Policy 0 (IMR13_READ_POL_0): Bit
0h
0 vector used to determine which agents are allowed read access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.

5.9.72 IMR13 Write Access Policy

(B_CR_BIMR13WAC_0_0_0_MCHBAR)—Offset 6A28h
This register, along with IMR13BASE, IMR13MASK and IMR13RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

334818 551
 MCHBAR

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR13_WRITE_POL_63
IMR13_WRITE_POL_62
IMR13_WRITE_POL_61
IMR13_WRITE_POL_60
IMR13_WRITE_POL_59
IMR13_WRITE_POL_58
IMR13_WRITE_POL_57
IMR13_WRITE_POL_56
IMR13_WRITE_POL_55
IMR13_WRITE_POL_54
IMR13_WRITE_POL_53
IMR13_WRITE_POL_52
IMR13_WRITE_POL_51
IMR13_WRITE_POL_50
IMR13_WRITE_POL_49
IMR13_WRITE_POL_48
IMR13_WRITE_POL_47
IMR13_WRITE_POL_46
IMR13_WRITE_POL_45
IMR13_WRITE_POL_44
IMR13_WRITE_POL_43
IMR13_WRITE_POL_42
IMR13_WRITE_POL_41
IMR13_WRITE_POL_40
IMR13_WRITE_POL_39
IMR13_WRITE_POL_38
IMR13_WRITE_POL_37
IMR13_WRITE_POL_36
IMR13_WRITE_POL_35
IMR13_WRITE_POL_34
IMR13_WRITE_POL_33
IMR13_WRITE_POL_32
IMR13_WRITE_POL_31
IMR13_WRITE_POL_30
IMR13_WRITE_POL_29
IMR13_WRITE_POL_28
IMR13_WRITE_POL_27
IMR13_WRITE_POL_26
IMR13_WRITE_POL_25
IMR13_WRITE_POL_24
IMR13_WRITE_POL_23
IMR13_WRITE_POL_22
IMR13_WRITE_POL_21
IMR13_WRITE_POL_20
IMR13_WRITE_POL_19
IMR13_WRITE_POL_18
IMR13_WRITE_POL_17
IMR13_WRITE_POL_16
IMR13_WRITE_POL_15
IMR13_WRITE_POL_14
IMR13_WRITE_POL_13
IMR13_WRITE_POL_12
IMR13_WRITE_POL_11
IMR13_WRITE_POL_10
IMR13_WRITE_POL_9
IMR13_WRITE_POL_8
IMR13_WRITE_POL_7
IMR13_WRITE_POL_6
IMR13_WRITE_POL_5
IMR13_WRITE_POL_4
IMR13_WRITE_POL_3
IMR13_WRITE_POL_2
IMR13_WRITE_POL_1
IMR13_WRITE_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR13 Write Access Policy 63 (IMR13_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 62 (IMR13_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 61 (IMR13_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 60 (IMR13_WRITE_POL_60): Bit
0h
60 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 59 (IMR13_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 58 (IMR13_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 57 (IMR13_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 56 (IMR13_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 55 (IMR13_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 54 (IMR13_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.

552 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR13 Write Access Policy 53 (IMR13_WRITE_POL_53): Bit

0h
53 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 52 (IMR13_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 51 (IMR13_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 50 (IMR13_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 49 (IMR13_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 48 (IMR13_WRITE_POL_48): Bit
0h
48 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 47 (IMR13_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 46 (IMR13_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 45 (IMR13_WRITE_POL_45): Bit
0h
45 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 44 (IMR13_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 43 (IMR13_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 42 (IMR13_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 41 (IMR13_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 40 (IMR13_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 39 (IMR13_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.

334818 553
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR13 Write Access Policy 38 (IMR13_WRITE_POL_38): Bit

0h
38 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 37 (IMR13_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 36 (IMR13_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 35 (IMR13_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 34 (IMR13_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 33 (IMR13_WRITE_POL_33): Bit
0h
33 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 32 (IMR13_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 31 (IMR13_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 30 (IMR13_WRITE_POL_30): Bit
0h
30 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 29 (IMR13_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 28 (IMR13_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 27 (IMR13_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 26 (IMR13_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 25 (IMR13_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 24 (IMR13_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.

554 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR13 Write Access Policy 23 (IMR13_WRITE_POL_23): Bit

0h
23 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 22 (IMR13_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 21 (IMR13_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 20 (IMR13_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 19 (IMR13_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 18 (IMR13_WRITE_POL_18): Bit
0h
18 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 17 (IMR13_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 16 (IMR13_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 15 (IMR13_WRITE_POL_15): Bit
0h
15 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 14 (IMR13_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 13 (IMR13_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 12 (IMR13_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 11 (IMR13_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 10 (IMR13_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 9 (IMR13_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.

334818 555
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR13 Write Access Policy 8 (IMR13_WRITE_POL_8): Bit

0h
8 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 7 (IMR13_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 6 (IMR13_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 5 (IMR13_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 4 (IMR13_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 3 (IMR13_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 2 (IMR13_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 1 (IMR13_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.
IMR13 Write Access Policy 0 (IMR13_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the IMR13 region, based on each agent's 6bit encoded SAI value.

5.9.73 IMR14 Base (B_CR_BIMR14BASE_0_0_0_MCHBAR)—

Offset 6A30h
This register, along with IMR14MASK, IMR14RAC and IMR14WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR14RAC and
IMR14WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

556 334818
MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IMR_EN
TR_EN
RESERVED_1

IMR14_BASE
Bit Default &
Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

Base 0 IMR14 Base (IMR14_BASE): Specifies bits 38:10 of the

start address of IMR14 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR14MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR14 defined region.

5.9.74 IMR14 Mask (B_CR_BIMR14MASK_0_0_0_MCHBAR)—

Offset 6A34h
This register, along with IMR14BASE, IMR14RAC and IMR14WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR14RAC and
IMR14WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GT_IWB_EN
IA_IWB_EN

IMR14_MASK
RESERVED_0

334818 557
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 HITM data from GT to be returned to the requester. When set to 0,
RW
inhibits HITM data from GT from being returned to the requester.
HITM data from IA cores may be returned to the requester
depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit Writeback Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 data HITM data from IA cores to be returned to the requester.
RW
When set to 0, inhibits HITM data from IA cores from being
returned to the requester. HITM data from GT may be returned to
the requester, depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR14 Mask (IMR14_MASK): These bits are ANDed

0h with bits 38:10 of the incoming address to determine if the
28:0
RW combined result matches the IMR14BASE[28:0] value. A match
indicates that the incoming address falls within the IMR14 region.

5.9.75 IMR14 Control Policy

(B_CR_BIMR14CP_0_0_0_MCHBAR)—Offset 6A38h
This register controls the access policy to the Read Access Policy BIMR14RAC, the Write
Access Policy BIMR14WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010
IMR14_CTRL_POL

558 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR14 Control Policy (IMR14_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR14RAC,
63:0
RW BIMR14WAC and BIMR14CP registers, based on the value from
each agent's 6bit SAI field.

5.9.76 IMR14 Read Access Policy

(B_CR_BIMR14RAC_0_0_0_MCHBAR)—Offset 6A40h
This register, along with IMR14BASE, IMR14MASK and IMR14WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR14_READ_POL_63
IMR14_READ_POL_62
IMR14_READ_POL_61
IMR14_READ_POL_60
IMR14_READ_POL_59
IMR14_READ_POL_58
IMR14_READ_POL_57
IMR14_READ_POL_56
IMR14_READ_POL_55
IMR14_READ_POL_54
IMR14_READ_POL_53
IMR14_READ_POL_52
IMR14_READ_POL_51
IMR14_READ_POL_50
IMR14_READ_POL_49
IMR14_READ_POL_48
IMR14_READ_POL_47
IMR14_READ_POL_46
IMR14_READ_POL_45
IMR14_READ_POL_44
IMR14_READ_POL_43
IMR14_READ_POL_42
IMR14_READ_POL_41
IMR14_READ_POL_40
IMR14_READ_POL_39
IMR14_READ_POL_38
IMR14_READ_POL_37
IMR14_READ_POL_36
IMR14_READ_POL_35
IMR14_READ_POL_34
IMR14_READ_POL_33
IMR14_READ_POL_32
IMR14_READ_POL_31
IMR14_READ_POL_30
IMR14_READ_POL_29
IMR14_READ_POL_28
IMR14_READ_POL_27
IMR14_READ_POL_26
IMR14_READ_POL_25
IMR14_READ_POL_24
IMR14_READ_POL_23
IMR14_READ_POL_22
IMR14_READ_POL_21
IMR14_READ_POL_20
IMR14_READ_POL_19
IMR14_READ_POL_18
IMR14_READ_POL_17
IMR14_READ_POL_16
IMR14_READ_POL_15
IMR14_READ_POL_14
IMR14_READ_POL_13
IMR14_READ_POL_12
IMR14_READ_POL_11
IMR14_READ_POL_10
IMR14_READ_POL_9
IMR14_READ_POL_8
IMR14_READ_POL_7
IMR14_READ_POL_6
IMR14_READ_POL_5
IMR14_READ_POL_4
IMR14_READ_POL_3
IMR14_READ_POL_2
IMR14_READ_POL_1
IMR14_READ_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR14 Read Access Policy 63 (IMR14_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 62 (IMR14_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 61 (IMR14_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 60 (IMR14_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.

334818 559
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR14 Read Access Policy 59 (IMR14_READ_POL_59): Bit

0h
59 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 58 (IMR14_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 57 (IMR14_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 56 (IMR14_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 55 (IMR14_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 54 (IMR14_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 53 (IMR14_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 52 (IMR14_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 51 (IMR14_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 50 (IMR14_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 49 (IMR14_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 48 (IMR14_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 47 (IMR14_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 46 (IMR14_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 45 (IMR14_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.

560 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR14 Read Access Policy 44 (IMR14_READ_POL_44): Bit

0h
44 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 43 (IMR14_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 42 (IMR14_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 41 (IMR14_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 40 (IMR14_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 39 (IMR14_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 38 (IMR14_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 37 (IMR14_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 36 (IMR14_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 35 (IMR14_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 34 (IMR14_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 33 (IMR14_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 32 (IMR14_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 31 (IMR14_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 30 (IMR14_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.

334818 561
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR14 Read Access Policy 29 (IMR14_READ_POL_29): Bit

0h
29 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 28 (IMR14_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 27 (IMR14_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 26 (IMR14_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 25 (IMR14_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 24 (IMR14_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 23 (IMR14_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 22 (IMR14_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 21 (IMR14_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 20 (IMR14_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 19 (IMR14_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 18 (IMR14_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 17 (IMR14_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 16 (IMR14_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 15 (IMR14_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.

562 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR14 Read Access Policy 14 (IMR14_READ_POL_14): Bit

0h
14 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 13 (IMR14_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 12 (IMR14_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 11 (IMR14_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 10 (IMR14_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 9 (IMR14_READ_POL_9): Bit
0h
9 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 8 (IMR14_READ_POL_8): Bit
0h
8 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 7 (IMR14_READ_POL_7): Bit
0h
7 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 6 (IMR14_READ_POL_6): Bit
0h
6 vector used to determine which agents are allowed read access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 5 (IMR14_READ_POL_5): Bit
0h
5 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 4 (IMR14_READ_POL_4): Bit
0h
4 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 3 (IMR14_READ_POL_3): Bit
0h
3 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 2 (IMR14_READ_POL_2): Bit
0h
2 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 1 (IMR14_READ_POL_1): Bit
0h
1 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Read Access Policy 0 (IMR14_READ_POL_0): Bit
0h
0 vector used to determine which agents are allowed read access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.

334818 563
 MCHBAR

5.9.77 IMR14 Write Access Policy

(B_CR_BIMR14WAC_0_0_0_MCHBAR)—Offset 6A48h
This register, along with IMR14BASE IMR14MASK and IMR14RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR14_WRITE_POL_63
IMR14_WRITE_POL_62
IMR14_WRITE_POL_61
IMR14_WRITE_POL_60
IMR14_WRITE_POL_59
IMR14_WRITE_POL_58
IMR14_WRITE_POL_57
IMR14_WRITE_POL_56
IMR14_WRITE_POL_55
IMR14_WRITE_POL_54
IMR14_WRITE_POL_53
IMR14_WRITE_POL_52
IMR14_WRITE_POL_51
IMR14_WRITE_POL_50
IMR14_WRITE_POL_49
IMR14_WRITE_POL_48
IMR14_WRITE_POL_47
IMR14_WRITE_POL_46
IMR14_WRITE_POL_45
IMR14_WRITE_POL_44
IMR14_WRITE_POL_43
IMR14_WRITE_POL_42
IMR14_WRITE_POL_41
IMR14_WRITE_POL_40
IMR14_WRITE_POL_39
IMR14_WRITE_POL_38
IMR14_WRITE_POL_37
IMR14_WRITE_POL_36
IMR14_WRITE_POL_35
IMR14_WRITE_POL_34
IMR14_WRITE_POL_33
IMR14_WRITE_POL_32
IMR14_WRITE_POL_31
IMR14_WRITE_POL_30
IMR14_WRITE_POL_29
IMR14_WRITE_POL_28
IMR14_WRITE_POL_27
IMR14_WRITE_POL_26
IMR14_WRITE_POL_25
IMR14_WRITE_POL_24
IMR14_WRITE_POL_23
IMR14_WRITE_POL_22
IMR14_WRITE_POL_21
IMR14_WRITE_POL_20
IMR14_WRITE_POL_19
IMR14_WRITE_POL_18
IMR14_WRITE_POL_17
IMR14_WRITE_POL_16
IMR14_WRITE_POL_15
IMR14_WRITE_POL_14
IMR14_WRITE_POL_13
IMR14_WRITE_POL_12
IMR14_WRITE_POL_11
IMR14_WRITE_POL_10
IMR14_WRITE_POL_9
IMR14_WRITE_POL_8
IMR14_WRITE_POL_7
IMR14_WRITE_POL_6
IMR14_WRITE_POL_5
IMR14_WRITE_POL_4
IMR14_WRITE_POL_3
IMR14_WRITE_POL_2
IMR14_WRITE_POL_1
IMR14_WRITE_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR14 Write Access Policy 63 (IMR14_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 62 (IMR14_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 61 (IMR14_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 60 (IMR14_WRITE_POL_60): Bit
0h
60 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 59 (IMR14_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 58 (IMR14_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 57 (IMR14_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.

564 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR14 Write Access Policy 56 (IMR14_WRITE_POL_56): Bit

0h
56 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 55 (IMR14_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 54 (IMR14_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 53 (IMR14_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 52 (IMR14_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 51 (IMR14_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 50 (IMR14_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 49 (IMR14_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 48 (IMR14_WRITE_POL_48): Bit
0h
48 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 47 (IMR14_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 46 (IMR14_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 45 (IMR14_WRITE_POL_45): Bit
0h
45 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 44 (IMR14_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 43 (IMR14_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 42 (IMR14_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.

334818 565
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR14 Write Access Policy 41 (IMR14_WRITE_POL_41): Bit

0h
41 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 40 (IMR14_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 39 (IMR14_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 38 (IMR14_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 37 (IMR14_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 36 (IMR14_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 35 (IMR14_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 34 (IMR14_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 33 (IMR14_WRITE_POL_33): Bit
0h
33 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 32 (IMR14_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 31 (IMR14_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 30 (IMR14_WRITE_POL_30): Bit
0h
30 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 29 (IMR14_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 28 (IMR14_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 27 (IMR14_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.

566 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR14 Write Access Policy 26 (IMR14_WRITE_POL_26): Bit

0h
26 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 25 (IMR14_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 24 (IMR14_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 23 (IMR14_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 22 (IMR14_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 21 (IMR14_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 20 (IMR14_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 19 (IMR14_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 18 (IMR14_WRITE_POL_18): Bit
0h
18 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 17 (IMR14_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 16 (IMR14_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 15 (IMR14_WRITE_POL_15): Bit
0h
15 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 14 (IMR14_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 13 (IMR14_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 12 (IMR14_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.

334818 567
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Bit Default &

Field Name (ID): Description
Range Access

IMR14 Write Access Policy 11 (IMR14_WRITE_POL_11): Bit

0h
11 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 10 (IMR14_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 9 (IMR14_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 8 (IMR14_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 7 (IMR14_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 6 (IMR14_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 5 (IMR14_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 4 (IMR14_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 3 (IMR14_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 2 (IMR14_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 1 (IMR14_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.
IMR14 Write Access Policy 0 (IMR14_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the IMR14 region, based on each agent's 6bit encoded SAI value.

5.9.78 IMR15 Base (B_CR_BIMR15BASE_0_0_0_MCHBAR)—

Offset 6A50h
This register, along with IMR15MASK, IMR15RAC and IMR15WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or

568 334818
MCHBAR

from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR15RAC and
IMR15WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR_EN
TR_EN
RESERVED_1

IMR15_BASE
Bit Default &
Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

Base 0 IMR15 Base (IMR15_BASE): Specifies bits 38:10 of the

start address of IMR15 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR15MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR15 defined region.

5.9.79 IMR15 Mask (B_CR_BIMR15MASK_0_0_0_MCHBAR)—

Offset 6A54h
This register, along with IMR15BASE, IMR15RAC and IMR15WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR15RAC and
IMR15WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

334818 569
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3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GT_IWB_EN
IA_IWB_EN

IMR15_MASK
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 HITM data from GT to be returned to the requester. When set to 0,
RW
inhibits HITM data from GT from being returned to the requester.
HITM data from IA cores may be returned to the requester
depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit Writeback Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 HITM data from IA cores to be returned to the requester. When set
RW
to 0, inhibits HITM data from IA cores from being returned to the
requester. HITM data from GT may be returned to the requester,
depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR15 Mask (IMR15_MASK): These bits are ANDed

0h with bits 38:10 of the incoming address to determine if the
28:0
RW combined result matches the IMR15BASE[28:0] value. A match
indicates that the incoming address falls within the IMR15 region.

5.9.80 IMR15 Control Policy

(B_CR_BIMR15CP_0_0_0_MCHBAR)—Offset 6A58h
This register controls the access policy to the Read Access Policy BIMR15RAC, the Write
Access Policy BIMR15WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010

570 334818
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IMR15_CTRL_POL
Bit Default &
Field Name (ID): Description
Range Access

IMR15 Control Policy (IMR15_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR15RAC,
63:0
RW BIMR15WAC and BIMR15CP registers, based on the value from
each agent's 6bit SAI field.

5.9.81 IMR15 Read Access Policy

(B_CR_BIMR15RAC_0_0_0_MCHBAR)—Offset 6A60h
This register, along with IMR15BASE, IMR15MASK and IMR15WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR15_READ_POL_63
IMR15_READ_POL_62
IMR15_READ_POL_61
IMR15_READ_POL_60
IMR15_READ_POL_59
IMR15_READ_POL_58
IMR15_READ_POL_57
IMR15_READ_POL_56
IMR15_READ_POL_55
IMR15_READ_POL_54
IMR15_READ_POL_53
IMR15_READ_POL_52
IMR15_READ_POL_51
IMR15_READ_POL_50
IMR15_READ_POL_49
IMR15_READ_POL_48
IMR15_READ_POL_47
IMR15_READ_POL_46
IMR15_READ_POL_45
IMR15_READ_POL_44
IMR15_READ_POL_43
IMR15_READ_POL_42
IMR15_READ_POL_41
IMR15_READ_POL_40
IMR15_READ_POL_39
IMR15_READ_POL_38
IMR15_READ_POL_37
IMR15_READ_POL_36
IMR15_READ_POL_35
IMR15_READ_POL_34
IMR15_READ_POL_33
IMR15_READ_POL_32
IMR15_READ_POL_31
IMR15_READ_POL_30
IMR15_READ_POL_29
IMR15_READ_POL_28
IMR15_READ_POL_27
IMR15_READ_POL_26
IMR15_READ_POL_25
IMR15_READ_POL_24
IMR15_READ_POL_23
IMR15_READ_POL_22
IMR15_READ_POL_21
IMR15_READ_POL_20
IMR15_READ_POL_19
IMR15_READ_POL_18
IMR15_READ_POL_17
IMR15_READ_POL_16
IMR15_READ_POL_15
IMR15_READ_POL_14
IMR15_READ_POL_13
IMR15_READ_POL_12
IMR15_READ_POL_11
IMR15_READ_POL_10
IMR15_READ_POL_9
IMR15_READ_POL_8
IMR15_READ_POL_7
IMR15_READ_POL_6
IMR15_READ_POL_5
IMR15_READ_POL_4
IMR15_READ_POL_3
IMR15_READ_POL_2
IMR15_READ_POL_1
IMR15_READ_POL_0

Bit Default &

Field Name (ID): Description
Range Access

IMR15 Read Access Policy 63 (IMR15_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 62 (IMR15_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.

334818 571
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR15 Read Access Policy 61 (IMR15_READ_POL_61): Bit

0h
61 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 60 (IMR15_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 59 (IMR15_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 58 (IMR15_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 57 (IMR15_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 56 (IMR15_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 55 (IMR15_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 54 (IMR15_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 53 (IMR15_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 52 (IMR15_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 51 (IMR15_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 50 (IMR15_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 49 (IMR15_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 48 (IMR15_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 47 (IMR15_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.

572 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR15 Read Access Policy 46 (IMR15_READ_POL_46): Bit

0h
46 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 45 (IMR15_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 44 (IMR15_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 43 (IMR15_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 42 (IMR15_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 41 (IMR15_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 40 (IMR15_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 39 (IMR15_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 38 (IMR15_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 37 (IMR15_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 36 (IMR15_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 35 (IMR15_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 34 (IMR15_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 33 (IMR15_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 32 (IMR15_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.

334818 573
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR15 Read Access Policy 31 (IMR15_READ_POL_31): Bit

0h
31 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 30 (IMR15_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 29 (IMR15_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 28 (IMR15_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 27 (IMR15_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 26 (IMR15_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 25 (IMR15_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 24 (IMR15_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 23 (IMR15_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 22 (IMR15_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 21 (IMR15_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 20 (IMR15_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 19 (IMR15_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 18 (IMR15_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 17 (IMR15_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.

574 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR15 Read Access Policy 16 (IMR15_READ_POL_16): Bit

0h
16 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 15 (IMR15_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 14 (IMR15_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 13 (IMR15_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 12 (IMR15_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 11 (IMR15_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 10 (IMR15_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 9 (IMR15_READ_POL_9): Bit
0h
9 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 8 (IMR15_READ_POL_8): Bit
0h
8 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 7 (IMR15_READ_POL_7): Bit
0h
7 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 6 (IMR15_READ_POL_6): Bit
0h
6 vector used to determine which agents are allowed read access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 5 (IMR15_READ_POL_5): Bit
0h
5 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 4 (IMR15_READ_POL_4): Bit
0h
4 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 3 (IMR15_READ_POL_3): Bit
0h
3 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 2 (IMR15_READ_POL_2): Bit
0h
2 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.

334818 575
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR15 Read Access Policy 1 (IMR15_READ_POL_1): Bit

0h
1 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Read Access Policy 0 (IMR15_READ_POL_0): Bit
0h
0 vector used to determine which agents are allowed read access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.

5.9.82 IMR15 Write Access Policy

(B_CR_BIMR15WAC_0_0_0_MCHBAR)—Offset 6A68h
This register, along with IMR15BASE, IMR15MASK and IMR15RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR15_WRITE_POL_63
IMR15_WRITE_POL_62
IMR15_WRITE_POL_61
IMR15_WRITE_POL_60
IMR15_WRITE_POL_59
IMR15_WRITE_POL_58
IMR15_WRITE_POL_57
IMR15_WRITE_POL_56
IMR15_WRITE_POL_55
IMR15_WRITE_POL_54
IMR15_WRITE_POL_53
IMR15_WRITE_POL_52
IMR15_WRITE_POL_51
IMR15_WRITE_POL_50
IMR15_WRITE_POL_49
IMR15_WRITE_POL_48
IMR15_WRITE_POL_47
IMR15_WRITE_POL_46
IMR15_WRITE_POL_45
IMR15_WRITE_POL_44
IMR15_WRITE_POL_43
IMR15_WRITE_POL_42
IMR15_WRITE_POL_41
IMR15_WRITE_POL_40
IMR15_WRITE_POL_39
IMR15_WRITE_POL_38
IMR15_WRITE_POL_37
IMR15_WRITE_POL_36
IMR15_WRITE_POL_35
IMR15_WRITE_POL_34
IMR15_WRITE_POL_33
IMR15_WRITE_POL_32
IMR15_WRITE_POL_31
IMR15_WRITE_POL_30
IMR15_WRITE_POL_29
IMR15_WRITE_POL_28
IMR15_WRITE_POL_27
IMR15_WRITE_POL_26
IMR15_WRITE_POL_25
IMR15_WRITE_POL_24
IMR15_WRITE_POL_23
IMR15_WRITE_POL_22
IMR15_WRITE_POL_21
IMR15_WRITE_POL_20
IMR15_WRITE_POL_19
IMR15_WRITE_POL_18
IMR15_WRITE_POL_17
IMR15_WRITE_POL_16
IMR15_WRITE_POL_15
IMR15_WRITE_POL_14
IMR15_WRITE_POL_13
IMR15_WRITE_POL_12
IMR15_WRITE_POL_11
IMR15_WRITE_POL_10
IMR15_WRITE_POL_9
IMR15_WRITE_POL_8
IMR15_WRITE_POL_7
IMR15_WRITE_POL_6
IMR15_WRITE_POL_5
IMR15_WRITE_POL_4
IMR15_WRITE_POL_3
IMR15_WRITE_POL_2
IMR15_WRITE_POL_1
IMR15_WRITE_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR15 Write Access Policy 63 (IMR15_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 62 (IMR15_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 61 (IMR15_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 60 (IMR15_WRITE_POL_60): Bit
0h
60 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.

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Bit Default &

Field Name (ID): Description
Range Access

IMR15 Write Access Policy 59 (IMR15_WRITE_POL_59): Bit

0h
59 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 58 (IMR15_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 57 (IMR15_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 56 (IMR15_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 55 (IMR15_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 54 (IMR15_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 53 (IMR15_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 52 (IMR15_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 51 (IMR15_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 50 (IMR15_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 49 (IMR15_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 48 (IMR15_WRITE_POL_48): Bit
0h
48 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 47 (IMR15_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 46 (IMR15_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 45 (IMR15_WRITE_POL_45): Bit
0h
45 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.

334818 577
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Bit Default &

Field Name (ID): Description
Range Access

IMR15 Write Access Policy 44 (IMR15_WRITE_POL_44): Bit

0h
44 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 43 (IMR15_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 42 (IMR15_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 41 (IMR15_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 40 (IMR15_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 39 (IMR15_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 38 (IMR15_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 37 (IMR15_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 36 (IMR15_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 35 (IMR15_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 34 (IMR15_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 33 (IMR15_WRITE_POL_33): Bit
0h
33 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 32 (IMR15_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 31 (IMR15_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 30 (IMR15_WRITE_POL_30): Bit
0h
30 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.

578 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR15 Write Access Policy 29 (IMR15_WRITE_POL_29): Bit

0h
29 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 28 (IMR15_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 27 (IMR15_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 26 (IMR15_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 25 (IMR15_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 24 (IMR15_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 23 (IMR15_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 22 (IMR15_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 21 (IMR15_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 20 (IMR15_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 19 (IMR15_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 18 (IMR15_WRITE_POL_18): Bit
0h
18 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 17 (IMR15_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 16 (IMR15_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 15 (IMR15_WRITE_POL_15): Bit
0h
15 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.

334818 579
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Bit Default &

Field Name (ID): Description
Range Access

IMR15 Write Access Policy 14 (IMR15_WRITE_POL_14): Bit

0h
14 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 13 (IMR15_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 12 (IMR15_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 11 (IMR15_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 10 (IMR15_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 9 (IMR15_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 8 (IMR15_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 7 (IMR15_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 6 (IMR15_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 5 (IMR15_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 4 (IMR15_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 3 (IMR15_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 2 (IMR15_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 1 (IMR15_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.
IMR15 Write Access Policy 0 (IMR15_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the IMR15 region, based on each agent's 6bit encoded SAI value.

580 334818
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5.9.83 IMR16 Base (B_CR_BIMR16BASE_0_0_0_MCHBAR)—

Offset 6A70h
This register, along with IMR16MASK, IMR16RAC and IMR16WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR16RAC and
IMR16WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IMR16_BASE
RESERVED_1
IMR_EN
TR_EN

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

Base 0 IMR16 Base (IMR16_BASE): Specifies bits 38:10 of the

start address of IMR16 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR16MASK[28:0]
applied to bits 38:10 of the incoming address, to determine if an
access falls within the IMR16 defined region.

5.9.84 IMR16 Mask (B_CR_BIMR16MASK_0_0_0_MCHBAR)—

Offset 6A74h
This register, along with IMR16BASE, IMR16RAC and IMR16WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR16RAC and
IMR16WAC registers.

334818 581
 MCHBAR

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GT_IWB_EN
IA_IWB_EN
RESERVED_0

IMR16_MASK
Bit Default &
Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 data HITM data from GT to be returned to the requester. When set
RW
to 0, inhibits HITM data from GT from being returned to the
requester. HITM data from IA cores may be returned to the
requester, depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit Writeback Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 HITM data from IA cores to be returned to the requester. When set
RW
to 0, inhibits HITM data from IA cores from being returned to the
requester. HITM data from GT may be returned to the requester
depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR16 Mask (IMR16_MASK): These bits are ANDed

0h with bits 38:10 of the incoming address to determine if the
28:0
RW combined result matches the IMR16BASE[28:0] value. A match
indicates that the incoming address falls within the IMR16 region.

5.9.85 IMR16 Control Policy

(B_CR_BIMR16CP_0_0_0_MCHBAR)—Offset 6A78h
This register controls the access policy to the Read Access Policy BIMR16RAC, the Write
Access Policy BIMR16WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

582 334818
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Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010

IMR16_CTRL_POL
Bit Default &
Field Name (ID): Description
Range Access

IMR16 Control Policy (IMR16_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR16RAC,
63:0
RW BIMR16WAC and BIMR16CP registers, based on the value from
each agent's 6bit SAI field.

5.9.86 IMR16 Read Access Policy

(B_CR_BIMR16RAC_0_0_0_MCHBAR)—Offset 6A80h
This register, along with IMR16BASE, IMR16MASK and IMR16WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR16_READ_POL_63
IMR16_READ_POL_62
IMR16_READ_POL_61
IMR16_READ_POL_60
IMR16_READ_POL_59
IMR16_READ_POL_58
IMR16_READ_POL_57
IMR16_READ_POL_56
IMR16_READ_POL_55
IMR16_READ_POL_54
IMR16_READ_POL_53
IMR16_READ_POL_52
IMR16_READ_POL_51
IMR16_READ_POL_50
IMR16_READ_POL_49
IMR16_READ_POL_48
IMR16_READ_POL_47
IMR16_READ_POL_46
IMR16_READ_POL_45
IMR16_READ_POL_44
IMR16_READ_POL_43
IMR16_READ_POL_42
IMR16_READ_POL_41
IMR16_READ_POL_40
IMR16_READ_POL_39
IMR16_READ_POL_38
IMR16_READ_POL_37
IMR16_READ_POL_36
IMR16_READ_POL_35
IMR16_READ_POL_34
IMR16_READ_POL_33
IMR16_READ_POL_32
IMR16_READ_POL_31
IMR16_READ_POL_30
IMR16_READ_POL_29
IMR16_READ_POL_28
IMR16_READ_POL_27
IMR16_READ_POL_26
IMR16_READ_POL_25
IMR16_READ_POL_24
IMR16_READ_POL_23
IMR16_READ_POL_22
IMR16_READ_POL_21
IMR16_READ_POL_20
IMR16_READ_POL_19
IMR16_READ_POL_18
IMR16_READ_POL_17
IMR16_READ_POL_16
IMR16_READ_POL_15
IMR16_READ_POL_14
IMR16_READ_POL_13
IMR16_READ_POL_12
IMR16_READ_POL_11
IMR16_READ_POL_10
IMR16_READ_POL_9
IMR16_READ_POL_8
IMR16_READ_POL_7
IMR16_READ_POL_6
IMR16_READ_POL_5
IMR16_READ_POL_4
IMR16_READ_POL_3
IMR16_READ_POL_2
IMR16_READ_POL_1
IMR16_READ_POL_0

Bit Default &

Field Name (ID): Description
Range Access

IMR16 Read Access Policy 63 (IMR16_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.

334818 583
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR16 Read Access Policy 62 (IMR16_READ_POL_62): Bit

0h
62 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 61 (IMR16_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 60 (IMR16_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 59 (IMR16_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 58 (IMR16_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 57 (IMR16_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 56 (IMR16_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 55 (IMR16_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 54 (IMR16_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 53 (IMR16_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 52 (IMR16_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 51 (IMR16_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 50 (IMR16_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 49 (IMR16_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 48 (IMR16_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.

584 334818
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Bit Default &

Field Name (ID): Description
Range Access

IMR16 Read Access Policy 47 (IMR16_READ_POL_47): Bit

0h
47 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 46 (IMR16_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 45 (IMR16_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 44 (IMR16_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 43 (IMR16_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 42 (IMR16_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 41 (IMR16_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 40 (IMR16_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 39 (IMR16_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 38 (IMR16_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 37 (IMR16_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 36 (IMR16_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 35 (IMR16_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 34 (IMR16_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 33 (IMR16_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.

334818 585
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR16 Read Access Policy 32 (IMR16_READ_POL_32): Bit

0h
32 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 31 (IMR16_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 30 (IMR16_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 29 (IMR16_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 28 (IMR16_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 27 (IMR16_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 26 (IMR16_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 25 (IMR16_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 24 (IMR16_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 23 (IMR16_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 22 (IMR16_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 21 (IMR16_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 20 (IMR16_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 19 (IMR16_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 18 (IMR16_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.

586 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR16 Read Access Policy 17 (IMR16_READ_POL_17): Bit

0h
17 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 16 (IMR16_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 15 (IMR16_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 14 (IMR16_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 13 (IMR16_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 12 (IMR16_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 11 (IMR16_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 10 (IMR16_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 9 (IMR16_READ_POL_9): Bit
0h
9 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 8 (IMR16_READ_POL_8): Bit
0h
8 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 7 (IMR16_READ_POL_7): Bit
0h
7 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 6 (IMR16_READ_POL_6): Bit
0h
6 vector used to determine which agents are allowed read access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 5 (IMR16_READ_POL_5): Bit
0h
5 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 4 (IMR16_READ_POL_4): Bit
0h
4 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 3 (IMR16_READ_POL_3): Bit
0h
3 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.

334818 587
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR16 Read Access Policy 2 (IMR16_READ_POL_2): Bit

0h
2 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 1 (IMR16_READ_POL_1): Bit
0h
1 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Read Access Policy 0 (IMR16_READ_POL_0): Bit
0h
0 vector used to determine which agents are allowed read access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.

5.9.87 IMR16 Write Access Policy

(B_CR_BIMR16WAC_0_0_0_MCHBAR)—Offset 6A88h
This register, along with IMR16BASE, IMR16MASK and IMR16RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR16_WRITE_POL_63
IMR16_WRITE_POL_62
IMR16_WRITE_POL_61
IMR16_WRITE_POL_60
IMR16_WRITE_POL_59
IMR16_WRITE_POL_58
IMR16_WRITE_POL_57
IMR16_WRITE_POL_56
IMR16_WRITE_POL_55
IMR16_WRITE_POL_54
IMR16_WRITE_POL_53
IMR16_WRITE_POL_52
IMR16_WRITE_POL_51
IMR16_WRITE_POL_50
IMR16_WRITE_POL_49
IMR16_WRITE_POL_48
IMR16_WRITE_POL_47
IMR16_WRITE_POL_46
IMR16_WRITE_POL_45
IMR16_WRITE_POL_44
IMR16_WRITE_POL_43
IMR16_WRITE_POL_42
IMR16_WRITE_POL_41
IMR16_WRITE_POL_40
IMR16_WRITE_POL_39
IMR16_WRITE_POL_38
IMR16_WRITE_POL_37
IMR16_WRITE_POL_36
IMR16_WRITE_POL_35
IMR16_WRITE_POL_34
IMR16_WRITE_POL_33
IMR16_WRITE_POL_32
IMR16_WRITE_POL_31
IMR16_WRITE_POL_30
IMR16_WRITE_POL_29
IMR16_WRITE_POL_28
IMR16_WRITE_POL_27
IMR16_WRITE_POL_26
IMR16_WRITE_POL_25
IMR16_WRITE_POL_24
IMR16_WRITE_POL_23
IMR16_WRITE_POL_22
IMR16_WRITE_POL_21
IMR16_WRITE_POL_20
IMR16_WRITE_POL_19
IMR16_WRITE_POL_18
IMR16_WRITE_POL_17
IMR16_WRITE_POL_16
IMR16_WRITE_POL_15
IMR16_WRITE_POL_14
IMR16_WRITE_POL_13
IMR16_WRITE_POL_12
IMR16_WRITE_POL_11
IMR16_WRITE_POL_10
IMR16_WRITE_POL_9
IMR16_WRITE_POL_8
IMR16_WRITE_POL_7
IMR16_WRITE_POL_6
IMR16_WRITE_POL_5
IMR16_WRITE_POL_4
IMR16_WRITE_POL_3
IMR16_WRITE_POL_2
IMR16_WRITE_POL_1
IMR16_WRITE_POL_0

Bit Default &

Field Name (ID): Description
Range Access

IMR16 Write Access Policy 63 (IMR16_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 62 (IMR16_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 61 (IMR16_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.

588 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR16 Write Access Policy 60 (IMR16_WRITE_POL_60): Bit

0h
60 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 59 (IMR16_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 58 (IMR16_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 57 (IMR16_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 56 (IMR16_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 55 (IMR16_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 54 (IMR16_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 53 (IMR16_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 52 (IMR16_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 51 (IMR16_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 50 (IMR16_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 49 (IMR16_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 48 (IMR16_WRITE_POL_48): Bit
0h
48 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 47 (IMR16_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 46 (IMR16_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.

334818 589
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR16 Write Access Policy 45 (IMR16_WRITE_POL_45): Bit

0h
45 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 44 (IMR16_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 43 (IMR16_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 42 (IMR16_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 41 (IMR16_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 40 (IMR16_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 39 (IMR16_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 38 (IMR16_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 37 (IMR16_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 36 (IMR16_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 35 (IMR16_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 34 (IMR16_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 33 (IMR16_WRITE_POL_33): Bit
0h
33 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 32 (IMR16_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 31 (IMR16_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.

590 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR16 Write Access Policy 30 (IMR16_WRITE_POL_30): Bit

0h
30 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 29 (IMR16_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 28 (IMR16_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 27 (IMR16_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 26 (IMR16_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 25 (IMR16_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 24 (IMR16_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 23 (IMR16_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 22 (IMR16_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 21 (IMR16_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 20 (IMR16_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 19 (IMR16_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 18 (IMR16_WRITE_POL_18): Bit
0h
18 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 17 (IMR16_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 16 (IMR16_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.

334818 591
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR16 Write Access Policy 15 (IMR16_WRITE_POL_15): Bit

0h
15 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 14 (IMR16_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 13 (IMR16_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 12 (IMR16_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 11 (IMR16_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 10 (IMR16_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 9 (IMR16_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 8 (IMR16_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 7 (IMR16_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 6 (IMR16_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 5 (IMR16_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 4 (IMR16_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 3 (IMR16_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 2 (IMR16_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.
IMR16 Write Access Policy 1 (IMR16_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.

592 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR16 Write Access Policy 0 (IMR16_WRITE_POL_0): Bit

0h
0 vector used to determine which agents are allowed write access to
RW
the IMR16 region, based on each agent's 6bit encoded SAI value.

5.9.88 IMR17 Base (B_CR_BIMR17BASE_0_0_0_MCHBAR)—

Offset 6A90h
This register, along with IMR17MASK, IMR17RAC and IMR17WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR17RAC and
IMR17WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR17_BASE
IMR_EN
TR_EN
RESERVED_1

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

Base 0 IMR17BASE (IMR17_BASE): Specifies bits 38:10 of the

start address of IMR17 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR17MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR17 defined region.

334818 593
 MCHBAR

5.9.89 IMR17 Mask (B_CR_BIMR17MASK_0_0_0_MCHBAR)—

Offset 6A94h
This register, along with IMR17BASE, IMR17RAC and IMR17WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR17RAC and
IMR17WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IMR17_MASK
IA_IWB_EN
GT_IWB_EN

RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 HITM data from GT to be returned to the requester. When set to 0,
RW
inhibits HITM data from GT from being returned to the requester.
HITM data from IA cores may be returned to the requester,
depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit Writeback Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 data HITM data from IA cores to be returned to the requester.
RW
When set to 0, inhibits HITM data from IA cores from being
returned to the requester. HITM data from GT may be returned to
the requester depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR17 Mask (IMR17_MASK): These bits are ANDed

0h with bits 38:10 of the incoming address to determine if the
28:0
RW combined result matches the IMR17BASE[28:0] value. A match
indicates that the incoming address falls within the IMR17 region.

594 334818
MCHBAR

5.9.90 IMR17 Control Policy

(B_CR_BIMR17CP_0_0_0_MCHBAR)—Offset 6A98h
This register controls the access policy to the Read Access Policy BIMR17RAC, the Write
Access Policy BIMR17WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010

IMR17_CTRL_POL

Bit Default &

Field Name (ID): Description
Range Access

IMR17 Control Policy (IMR17_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR17RAC,
63:0
RW BIMR17WAC and BIMR17CP registers, based on the value from
each agent's 6bit SAI field.

5.9.91 IMR17 Read Access Policy

(B_CR_BIMR17RAC_0_0_0_MCHBAR)—Offset 6AA0h
This register, along with IMR17BASE, IMR17MASK and IMR17WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000

334818 595
 MCHBAR

IMR17_READ_POL_63
IMR17_READ_POL_62
IMR17_READ_POL_61
IMR17_READ_POL_60
IMR17_READ_POL_59
IMR17_READ_POL_58
IMR17_READ_POL_57
IMR17_READ_POL_56
IMR17_READ_POL_55
IMR17_READ_POL_54
IMR17_READ_POL_53
IMR17_READ_POL_52
IMR17_READ_POL_51
IMR17_READ_POL_50
IMR17_READ_POL_49
IMR17_READ_POL_48
IMR17_READ_POL_47
IMR17_READ_POL_46
IMR17_READ_POL_45
IMR17_READ_POL_44
IMR17_READ_POL_43
IMR17_READ_POL_42
IMR17_READ_POL_41
IMR17_READ_POL_40
IMR17_READ_POL_39
IMR17_READ_POL_38
IMR17_READ_POL_37
IMR17_READ_POL_36
IMR17_READ_POL_35
IMR17_READ_POL_34
IMR17_READ_POL_33
IMR17_READ_POL_32
IMR17_READ_POL_31
IMR17_READ_POL_30
IMR17_READ_POL_29
IMR17_READ_POL_28
IMR17_READ_POL_27
IMR17_READ_POL_26
IMR17_READ_POL_25
IMR17_READ_POL_24
IMR17_READ_POL_23
IMR17_READ_POL_22
IMR17_READ_POL_21
IMR17_READ_POL_20
IMR17_READ_POL_19
IMR17_READ_POL_18
IMR17_READ_POL_17
IMR17_READ_POL_16
IMR17_READ_POL_15
IMR17_READ_POL_14
IMR17_READ_POL_13
IMR17_READ_POL_12
IMR17_READ_POL_11
IMR17_READ_POL_10
IMR17_READ_POL_9
IMR17_READ_POL_8
IMR17_READ_POL_7
IMR17_READ_POL_6
IMR17_READ_POL_5
IMR17_READ_POL_4
IMR17_READ_POL_3
IMR17_READ_POL_2
IMR17_READ_POL_1
IMR17_READ_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR17 Read Access Policy 63 (IMR17_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 62 (IMR17_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 61 (IMR17_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 60 (IMR17_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 59 (IMR17_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 58 (IMR17_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 57 (IMR17_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 56 (IMR17_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 55 (IMR17_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 54 (IMR17_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 53 (IMR17_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 52 (IMR17_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.

596 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR17 Read Access Policy 51 (IMR17_READ_POL_51): Bit

0h
51 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 50 (IMR17_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 49 (IMR17_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 48 (IMR17_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 47 (IMR17_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 46 (IMR17_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 45 (IMR17_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 44 (IMR17_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 43 (IMR17_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 42 (IMR17_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 41 (IMR17_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 40 (IMR17_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 39 (IMR17_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 38 (IMR17_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 37 (IMR17_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.

334818 597
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR17 Read Access Policy 36 (IMR17_READ_POL_36): Bit

0h
36 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 35 (IMR17_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 34 (IMR17_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 33 (IMR17_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 32 (IMR17_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 31 (IMR17_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 30 (IMR17_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 29 (IMR17_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 28 (IMR17_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 27 (IMR17_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 26 (IMR17_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 25 (IMR17_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 24 (IMR17_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 23 (IMR17_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 22 (IMR17_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.

598 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR17 Read Access Policy 21 (IMR17_READ_POL_21): Bit

0h
21 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 20 (IMR17_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 19 (IMR17_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 18 (IMR17_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 17 (IMR17_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 16 (IMR17_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 15 (IMR17_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 14 (IMR17_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 13 (IMR17_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 12 (IMR17_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 11 (IMR17_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 10 (IMR17_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 9 (IMR17_READ_POL_9): Bit
0h
9 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 8 (IMR17_READ_POL_8): Bit
0h
8 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 7 (IMR17_READ_POL_7): Bit
0h
7 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.

334818 599
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR17 Read Access Policy 6 (IMR17_READ_POL_6): Bit

0h
6 vector used to determine which agents are allowed read access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 5 (IMR17_READ_POL_5): Bit
0h
5 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 4 (IMR17_READ_POL_4): Bit
0h
4 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 3 (IMR17_READ_POL_3): Bit
0h
3 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 2 (IMR17_READ_POL_2): Bit
0h
2 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 1 (IMR17_READ_POL_1): Bit
0h
1 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Read Access Policy 0 (IMR17_READ_POL_0): Bit
0h
0 vector used to determine which agents are allowed read access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.

5.9.92 IMR17 Write Access Policy

(B_CR_BIMR17WAC_0_0_0_MCHBAR)—Offset 6AA8h
This register, along with IMR17BASE, IMR17MASK and IMR17RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR17_WRITE_POL_9
IMR17_WRITE_POL_8
IMR17_WRITE_POL_7
IMR17_WRITE_POL_6
IMR17_WRITE_POL_5
IMR17_WRITE_POL_4
IMR17_WRITE_POL_3
IMR17_WRITE_POL_2
IMR17_WRITE_POL_1
IMR17_WRITE_POL_0
IMR17_WRITE_POL_63
IMR17_WRITE_POL_62
IMR17_WRITE_POL_61
IMR17_WRITE_POL_60
IMR17_WRITE_POL_59
IMR17_WRITE_POL_58
IMR17_WRITE_POL_57
IMR17_WRITE_POL_56
IMR17_WRITE_POL_55
IMR17_WRITE_POL_54
IMR17_WRITE_POL_53
IMR17_WRITE_POL_52
IMR17_WRITE_POL_51
IMR17_WRITE_POL_50
IMR17_WRITE_POL_49
IMR17_WRITE_POL_48
IMR17_WRITE_POL_47
IMR17_WRITE_POL_46
IMR17_WRITE_POL_45
IMR17_WRITE_POL_44
IMR17_WRITE_POL_43
IMR17_WRITE_POL_42
IMR17_WRITE_POL_41
IMR17_WRITE_POL_40
IMR17_WRITE_POL_39
IMR17_WRITE_POL_38
IMR17_WRITE_POL_37
IMR17_WRITE_POL_36
IMR17_WRITE_POL_35
IMR17_WRITE_POL_34
IMR17_WRITE_POL_33
IMR17_WRITE_POL_32
IMR17_WRITE_POL_31
IMR17_WRITE_POL_30
IMR17_WRITE_POL_29
IMR17_WRITE_POL_28
IMR17_WRITE_POL_27
IMR17_WRITE_POL_26
IMR17_WRITE_POL_25
IMR17_WRITE_POL_24
IMR17_WRITE_POL_23
IMR17_WRITE_POL_22
IMR17_WRITE_POL_21
IMR17_WRITE_POL_20
IMR17_WRITE_POL_19
IMR17_WRITE_POL_18
IMR17_WRITE_POL_17
IMR17_WRITE_POL_16
IMR17_WRITE_POL_15
IMR17_WRITE_POL_14
IMR17_WRITE_POL_13
IMR17_WRITE_POL_12
IMR17_WRITE_POL_11
IMR17_WRITE_POL_10

600 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR17 Write Access Policy 63 (IMR17_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 62 (IMR17_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 61 (IMR17_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 60 (IMR17_WRITE_POL_60): Bit
0h
60 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 59 (IMR17_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 58 (IMR17_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 57 (IMR17_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 56 (IMR17_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 55 (IMR17_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 54 (IMR17_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 53 (IMR17_WRITE_POL_53): Bit
0h
53 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 52 (IMR17_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 51 (IMR17_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 50 (IMR17_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 49 (IMR17_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.

334818 601
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR17 Write Access Policy 48 (IMR17_WRITE_POL_48): Bit

0h
48 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 47 (IMR17_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 46 (IMR17_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 45 (IMR17_WRITE_POL_45): Bit
0h
45 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 44 (IMR17_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 43 (IMR17_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 42 (IMR17_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 41 (IMR17_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 40 (IMR17_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 39 (IMR17_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 38 (IMR17_WRITE_POL_38): Bit
0h
38 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 37 (IMR17_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 36 (IMR17_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 35 (IMR17_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 34 (IMR17_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.

602 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR17 Write Access Policy 33 (IMR17_WRITE_POL_33): Bit

0h
33 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 32 (IMR17_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 31 (IMR17_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 30 (IMR17_WRITE_POL_30): Bit
0h
30 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 29 (IMR17_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 28 (IMR17_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 27 (IMR17_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 26 (IMR17_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 25 (IMR17_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 24 (IMR17_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 23 (IMR17_WRITE_POL_23): Bit
0h
23 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 22 (IMR17_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 21 (IMR17_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 20 (IMR17_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 19 (IMR17_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.

334818 603
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR17 Write Access Policy 18 (IMR17_WRITE_POL_18): Bit

0h
18 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 17 (IMR17_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 16 (IMR17_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 15 (IMR17_WRITE_POL_15): Bit
0h
15 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 14 (IMR17_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 13 (IMR17_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 12 (IMR17_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 11 (IMR17_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 10 (IMR17_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 9 (IMR17_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 8 (IMR17_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 7 (IMR17_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 6 (IMR17_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 5 (IMR17_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 4 (IMR17_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.

604 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR17 Write Access Policy 3 (IMR17_WRITE_POL_3): Bit

0h
3 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 2 (IMR17_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 1 (IMR17_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.
IMR17 Write Access Policy 0 (IMR17_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the IMR17 region, based on each agent's 6bit encoded SAI value.

5.9.93 IMR18 Base (B_CR_BIMR18BASE_0_0_0_MCHBAR)—

Offset 6AB0h
This register, along with IMR18MASK, IMR18RAC and IMR18WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation, if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR18RAC and
IMR18WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR18_BASE
IMR_EN
TR_EN
RESERVED_1

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

334818 605
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Base 0 IMR18 Base (IMR18_BASE): Specifies bits 38:10 of the

start address of IMR18 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR18MASK[28:0]
applied to bits 38:10 of the incoming address, to determine if an
access falls within the IMR18 defined region.

5.9.94 IMR18 Mask (B_CR_BIMR18MASK_0_0_0_MCHBAR)—

Offset 6AB4h
This register, along with IMR18BASE, IMR18RAC and IMR18WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR18RAC and
IMR18WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR18_MASK
GT_IWB_EN
IA_IWB_EN
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 data HITM data from GT to be returned to the requester. When set
RW
to 0, inhibits HITM data from GT from being returned to the
requester. HITM data from IA cores may be returned to the
requester depending on the setting of the IA_IWB_EN bit.

606 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[1]: IA Implicit Writeback Enable

(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 data HITM data from IA cores to be returned to the requester.
RW
When set to 0, inhibits HITM data from IA cores from being
returned to the requester. HITM data from GT may be returned to
the requester depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR18 Mask (IMR18_MASK): These bits are ANDed

0h with bits 38:10 of the incoming address to determine if the
28:0
RW combined result matches the IMR18BASE[28:0] value. A match
indicates that the incoming address falls within the IMR18 region.

5.9.95 IMR18 Control Policy

(B_CR_BIMR18CP_0_0_0_MCHBAR)—Offset 6AB8h
This register controls the access policy to the Read Access Policy BIMR18RAC, the Write
Access Policy BIMR18WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010
IMR18_CTRL_POL

Bit Default &

Field Name (ID): Description
Range Access

IMR18 Control Policy (IMR18_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR18RAC,
63:0
RW BIMR18WAC and BIMR18CP registers, based on the value from
each agent's 6bit SAI field.

334818 607
 MCHBAR

5.9.96 IMR18 Read Access Policy

(B_CR_BIMR18RAC_0_0_0_MCHBAR)—Offset 6AC0h
This register, along with IMR18BASE, IMR18MASK and IMR18WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR18_READ_POL_63
IMR18_READ_POL_62
IMR18_READ_POL_61
IMR18_READ_POL_60
IMR18_READ_POL_59
IMR18_READ_POL_58
IMR18_READ_POL_57
IMR18_READ_POL_56
IMR18_READ_POL_55
IMR18_READ_POL_54
IMR18_READ_POL_53
IMR18_READ_POL_52
IMR18_READ_POL_51
IMR18_READ_POL_50
IMR18_READ_POL_49
IMR18_READ_POL_48
IMR18_READ_POL_47
IMR18_READ_POL_46
IMR18_READ_POL_45
IMR18_READ_POL_44
IMR18_READ_POL_43
IMR18_READ_POL_42
IMR18_READ_POL_41
IMR18_READ_POL_40
IMR18_READ_POL_39
IMR18_READ_POL_38
IMR18_READ_POL_37
IMR18_READ_POL_36
IMR18_READ_POL_35
IMR18_READ_POL_34
IMR18_READ_POL_33
IMR18_READ_POL_32
IMR18_READ_POL_31
IMR18_READ_POL_30
IMR18_READ_POL_29
IMR18_READ_POL_28
IMR18_READ_POL_27
IMR18_READ_POL_26
IMR18_READ_POL_25
IMR18_READ_POL_24
IMR18_READ_POL_23
IMR18_READ_POL_22
IMR18_READ_POL_21
IMR18_READ_POL_20
IMR18_READ_POL_19
IMR18_READ_POL_18
IMR18_READ_POL_17
IMR18_READ_POL_16
IMR18_READ_POL_15
IMR18_READ_POL_14
IMR18_READ_POL_13
IMR18_READ_POL_12
IMR18_READ_POL_11
IMR18_READ_POL_10
IMR18_READ_POL_9
IMR18_READ_POL_8
IMR18_READ_POL_7
IMR18_READ_POL_6
IMR18_READ_POL_5
IMR18_READ_POL_4
IMR18_READ_POL_3
IMR18_READ_POL_2
IMR18_READ_POL_1
IMR18_READ_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR18 Read Access Policy 63 (IMR18_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 62 (IMR18_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 61 (IMR18_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 60 (IMR18_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 59 (IMR18_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 58 (IMR18_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 57 (IMR18_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.

608 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR18 Read Access Policy 56 (IMR18_READ_POL_56): Bit

0h
56 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 55 (IMR18_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 54 (IMR18_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 53 (IMR18_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 52 (IMR18_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 51 (IMR18_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 50 (IMR18_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 49 (IMR18_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 48 (IMR18_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 47 (IMR18_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 46 (IMR18_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 45 (IMR18_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 44 (IMR18_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 43 (IMR18_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 42 (IMR18_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.

334818 609
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR18 Read Access Policy 41 (IMR18_READ_POL_41): Bit

0h
41 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 40 (IMR18_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 39 (IMR18_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 38 (IMR18_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 37 (IMR18_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 36 (IMR18_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 35 (IMR18_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 34 (IMR18_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 33 (IMR18_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 32 (IMR18_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 31 (IMR18_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 30 (IMR18_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 29 (IMR18_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 28 (IMR18_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 27 (IMR18_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.

610 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR18 Read Access Policy 26 (IMR18_READ_POL_26): Bit

0h
26 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 25 (IMR18_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 24 (IMR18_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 23 (IMR18_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 22 (IMR18_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 21 (IMR18_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 20 (IMR18_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 19 (IMR18_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 18 (IMR18_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 17 (IMR18_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 16 (IMR18_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 15 (IMR18_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 14 (IMR18_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 13 (IMR18_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 12 (IMR18_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.

334818 611
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR18 Read Access Policy 11 (IMR18_READ_POL_11): Bit

0h
11 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 10 (IMR18_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 9 (IMR18_READ_POL_9): Bit
0h
9 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 8 (IMR18_READ_POL_8): Bit
0h
8 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 7 (IMR18_READ_POL_7): Bit
0h
7 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 6 (IMR18_READ_POL_6): Bit
0h
6 vector used to determine which agents are allowed read access to
RO
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 5 (IMR18_READ_POL_5): Bit
0h
5 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 4 (IMR18_READ_POL_4): Bit
0h
4 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 3 (IMR18_READ_POL_3): Bit
0h
3 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 2 (IMR18_READ_POL_2): Bit
0h
2 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 1 (IMR18_READ_POL_1): Bit
0h
1 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.
IMR18 Read Access Policy 0 (IMR18_READ_POL_0): Bit
0h
0 vector used to determine which agents are allowed read access to
RW
the IMR18 region, based on each agent's 6bit encoded SAI value.

5.9.97 IMR18 Write Access Policy

(B_CR_BIMR18WAC_0_0_0_MCHBAR)—Offset 6AC8h
This register, along with IMR18BASE, IMR18MASK and IMR18RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

612 334818
MCHBAR

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR18_WRITE_POL_63
IMR18_WRITE_POL_62
IMR18_WRITE_POL_61
IMR18_WRITE_POL_60
IMR18_WRITE_POL_59
IMR18_WRITE_POL_58
IMR18_WRITE_POL_57
IMR18_WRITE_POL_56
IMR18_WRITE_POL_55
IMR18_WRITE_POL_54
IMR18_WRITE_POL_53
IMR18_WRITE_POL_52
IMR18_WRITE_POL_51
IMR18_WRITE_POL_50
IMR18_WRITE_POL_49
IMR18_WRITE_POL_48
IMR18_WRITE_POL_47
IMR18_WRITE_POL_46
IMR18_WRITE_POL_45
IMR18_WRITE_POL_44
IMR18_WRITE_POL_43
IMR18_WRITE_POL_42
IMR18_WRITE_POL_41
IMR18_WRITE_POL_40
IMR18_WRITE_POL_39
IMR18_WRITE_POL_38
IMR18_WRITE_POL_37
IMR18_WRITE_POL_36
IMR18_WRITE_POL_35
IMR18_WRITE_POL_34
IMR18_WRITE_POL_33
IMR18_WRITE_POL_32
IMR18_WRITE_POL_31
IMR18_WRITE_POL_30
IMR18_WRITE_POL_29
IMR18_WRITE_POL_28
IMR18_WRITE_POL_27
IMR18_WRITE_POL_26
IMR18_WRITE_POL_25
IMR18_WRITE_POL_24
IMR18_WRITE_POL_23
IMR18_WRITE_POL_22
IMR18_WRITE_POL_21
IMR18_WRITE_POL_20
IMR18_WRITE_POL_19
IMR18_WRITE_POL_18
IMR18_WRITE_POL_17
IMR18_WRITE_POL_16
IMR18_WRITE_POL_15
IMR18_WRITE_POL_14
IMR18_WRITE_POL_13
IMR18_WRITE_POL_12
IMR18_WRITE_POL_11
IMR18_WRITE_POL_10
IMR18_WRITE_POL_9
IMR18_WRITE_POL_8
IMR18_WRITE_POL_7
IMR18_WRITE_POL_6
IMR18_WRITE_POL_5
IMR18_WRITE_POL_4
IMR18_WRITE_POL_3
IMR18_WRITE_POL_2
IMR18_WRITE_POL_1
IMR18_WRITE_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR18_WRITE_POL_63 (IMR18_WRITE_POL_63): B-Unit

0h IMR18 Write Access Policy: Bit vector used to determine which
63
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_62 (IMR18_WRITE_POL_62): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
62
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_61 (IMR18_WRITE_POL_61): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
61
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_60 (IMR18_WRITE_POL_60): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
60
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_59 (IMR18_WRITE_POL_59): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
59
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_58 (IMR18_WRITE_POL_58): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
58
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_57 (IMR18_WRITE_POL_57): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
57
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.

334818 613
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR18_WRITE_POL_56 (IMR18_WRITE_POL_56): B-Unit

0h IMR18 Write Access Policy: Bit vector used to determine which
56
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_55 (IMR18_WRITE_POL_55): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
55
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_54 (IMR18_WRITE_POL_54): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
54
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_53 (IMR18_WRITE_POL_53): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
53
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_52 (IMR18_WRITE_POL_52): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
52
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_51 (IMR18_WRITE_POL_51): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
51
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_50 (IMR18_WRITE_POL_50): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
50
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_49 (IMR18_WRITE_POL_49): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
49
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_48 (IMR18_WRITE_POL_48): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
48
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_47 (IMR18_WRITE_POL_47): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
47
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_46 (IMR18_WRITE_POL_46): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
46
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.

614 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR18_WRITE_POL_45 (IMR18_WRITE_POL_45): B-Unit

0h IMR18 Write Access Policy: Bit vector used to determine which
45
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_44 (IMR18_WRITE_POL_44): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
44
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_43 (IMR18_WRITE_POL_43): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
43
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_42 (IMR18_WRITE_POL_42): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
42
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_41 (IMR18_WRITE_POL_41): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
41
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_40 (IMR18_WRITE_POL_40): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
40
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_39 (IMR18_WRITE_POL_39): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
39
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_38 (IMR18_WRITE_POL_38): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
38
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_37 (IMR18_WRITE_POL_37): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
37
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_36 (IMR18_WRITE_POL_36): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
36
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_35 (IMR18_WRITE_POL_35): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
35
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.

334818 615
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR18_WRITE_POL_34 (IMR18_WRITE_POL_34): B-Unit

0h IMR18 Write Access Policy: Bit vector used to determine which
34
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_33 (IMR18_WRITE_POL_33): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
33
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_32 (IMR18_WRITE_POL_32): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
32
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_31 (IMR18_WRITE_POL_31): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
31
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_30 (IMR18_WRITE_POL_30): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
30
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_29 (IMR18_WRITE_POL_29): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
29
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_28 (IMR18_WRITE_POL_28): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
28
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_27 (IMR18_WRITE_POL_27): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
27
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_26 (IMR18_WRITE_POL_26): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
26
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_25 (IMR18_WRITE_POL_25): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
25
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_24 (IMR18_WRITE_POL_24): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
24
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.

616 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR18_WRITE_POL_23 (IMR18_WRITE_POL_23): B-Unit

0h IMR18 Write Access Policy: Bit vector used to determine which
23
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_22 (IMR18_WRITE_POL_22): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
22
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_21 (IMR18_WRITE_POL_21): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
21
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_20 (IMR18_WRITE_POL_20): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
20
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_19 (IMR18_WRITE_POL_19): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
19
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_18 (IMR18_WRITE_POL_18): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
18
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_17 (IMR18_WRITE_POL_17): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
17
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_16 (IMR18_WRITE_POL_16): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
16
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_15 (IMR18_WRITE_POL_15): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
15
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_14 (IMR18_WRITE_POL_14): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
14
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_13 (IMR18_WRITE_POL_13): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
13
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.

334818 617
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR18_WRITE_POL_12 (IMR18_WRITE_POL_12): B-Unit

0h IMR18 Write Access Policy: Bit vector used to determine which
12
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_11 (IMR18_WRITE_POL_11): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
11
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_10 (IMR18_WRITE_POL_10): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
10
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_9 (IMR18_WRITE_POL_9): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
9
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_8 (IMR18_WRITE_POL_8): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
8
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_7 (IMR18_WRITE_POL_7): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
7
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_6 (IMR18_WRITE_POL_6): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
6
RO agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_5 (IMR18_WRITE_POL_5): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
5
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_4 (IMR18_WRITE_POL_4): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
4
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_3 (IMR18_WRITE_POL_3): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
3
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_2 (IMR18_WRITE_POL_2): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
2
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.

618 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR18_WRITE_POL_1 (IMR18_WRITE_POL_1): B-Unit

0h IMR18 Write Access Policy: Bit vector used to determine which
1
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.
IMR18_WRITE_POL_0 (IMR18_WRITE_POL_0): B-Unit
0h IMR18 Write Access Policy: Bit vector used to determine which
0
RW agents are allowed write access to the IMR18 region, based on
each agent's 6bit encoded SAI value.

5.9.98 IMR19 Base (B_CR_BIMR19BASE_0_0_0_MCHBAR)—

Offset 6AD0h
This register, along with IMR19MASK, IMR19RAC and IMR19WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR19RAC and
IMR19WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR19_BASE
IMR_EN
TR_EN
RESERVED_1

Bit Default &

Field Name (ID): Description
Range Access

0h IMR Enable (IMR_EN): Enables access checking for the IMR

31
RW region.
0h Asset Classification AC[0]: Trace Enable (TR_EN): Enables
30
RW snooping of transactions to the IMR region by tracing agents.

29
0h Reserved (RESERVED_1): Reserved.
RO

334818 619
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Base 0 IMR19 Base (IMR19_BASE): Specifies bits 38:10 of the

start address of IMR19 region. IMR region size must be a strict
0h power of two, at least 1KB, and naturally aligned to the size.
28:0
RW These bits are compared with the result of the IMR19MASK[28:0]
applied to bits 38:10 of the incoming address to determine if an
access falls within the IMR19 defined region.

5.9.99 IMR19 Mask (B_CR_BIMR19MASK_0_0_0_MCHBAR)—

Offset 6AD4h
This register, along with IMR19BASE, IMR19RAC and IMR19WAC, defines an isolated
region of memory that can be masked to prohibit certain system agents from accessing
memory. When an agent sends a request to the B-Unit, whether snooped or not, an
IMR may optionally prevent that transaction from changing the state of memory or
from getting correct data in response to the operation if the agent's SAI field does not
specify the correct Policy. The IMR's Policy is configured by the IMR19RAC and
IMR19WAC registers.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IMR19_MASK
GT_IWB_EN
IA_IWB_EN
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 data HITM data from GT to be returned to the requester. When set
RW
to 0, inhibits HITM data from GT from being returned to the
requester. HITM data from IA cores may be returned to the
requester depending on the setting of the IA_IWB_EN bit.

620 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Asset Classification AC[1]: IA Implicit WB Enable

(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 data HITM data from IA cores to be returned to the requester.
RW
When set to 0, inhibits HITM data from IA cores from being
returned to the requester. HITM data from GT may be returned to
the requester depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_0): Reserved.
RO

Mask 0 IMR19 Mask (IMR19_MASK): These bits are ANDed

0h with bits 38:10 of the incoming address to determine if the
28:0
RW combined result matches the IMR19BASE[28:0] value. A match
indicates that the incoming address falls within the IMR19 region.

5.9.100 IMR19 Control Policy

(B_CR_BIMR19CP_0_0_0_MCHBAR)—Offset 6AD8h
This register controls the access policy to the Read Access Policy BIMR19RAC, the Write
Access Policy BIMR19WAC, and, self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010
IMR19_CTRL_POL

Bit Default &

Field Name (ID): Description
Range Access

IMR19 Control Policy (IMR19_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BIMR19RAC,
63:0
RW BIMR19WAC, BIMR19CP registers, based on the value from each
agent's 6bit SAI field.

334818 621
 MCHBAR

5.9.101 IMR19 Read Access Policy

(B_CR_BIMR19RAC_0_0_0_MCHBAR)—Offset 6AE0h
This register, along with IMR19BASE, IMR19MASK and IMR19WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR19_READ_POL_63
IMR19_READ_POL_62
IMR19_READ_POL_61
IMR19_READ_POL_60
IMR19_READ_POL_59
IMR19_READ_POL_58
IMR19_READ_POL_57
IMR19_READ_POL_56
IMR19_READ_POL_55
IMR19_READ_POL_54
IMR19_READ_POL_53
IMR19_READ_POL_52
IMR19_READ_POL_51
IMR19_READ_POL_50
IMR19_READ_POL_49
IMR19_READ_POL_48
IMR19_READ_POL_47
IMR19_READ_POL_46
IMR19_READ_POL_45
IMR19_READ_POL_44
IMR19_READ_POL_43
IMR19_READ_POL_42
IMR19_READ_POL_41
IMR19_READ_POL_40
IMR19_READ_POL_39
IMR19_READ_POL_38
IMR19_READ_POL_37
IMR19_READ_POL_36
IMR19_READ_POL_35
IMR19_READ_POL_34
IMR19_READ_POL_33
IMR19_READ_POL_32
IMR19_READ_POL_31
IMR19_READ_POL_30
IMR19_READ_POL_29
IMR19_READ_POL_28
IMR19_READ_POL_27
IMR19_READ_POL_26
IMR19_READ_POL_25
IMR19_READ_POL_24
IMR19_READ_POL_23
IMR19_READ_POL_22
IMR19_READ_POL_21
IMR19_READ_POL_20
IMR19_READ_POL_19
IMR19_READ_POL_18
IMR19_READ_POL_17
IMR19_READ_POL_16
IMR19_READ_POL_15
IMR19_READ_POL_14
IMR19_READ_POL_13
IMR19_READ_POL_12
IMR19_READ_POL_11
IMR19_READ_POL_10
IMR19_READ_POL_9
IMR19_READ_POL_8
IMR19_READ_POL_7
IMR19_READ_POL_6
IMR19_READ_POL_5
IMR19_READ_POL_4
IMR19_READ_POL_3
IMR19_READ_POL_2
IMR19_READ_POL_1
IMR19_READ_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR19 Read Access Policy 63 (IMR19_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 62 (IMR19_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 61 (IMR19_READ_POL_61): Bit
0h
61 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 60 (IMR19_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 59 (IMR19_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 58 (IMR19_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 57 (IMR19_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.

622 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR19 Read Access Policy 56 (IMR19_READ_POL_56): Bit

0h
56 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 55 (IMR19_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 54 (IMR19_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 53 (IMR19_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 52 (IMR19_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 51 (IMR19_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 50 (IMR19_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 49 (IMR19_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 48 (IMR19_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 47 (IMR19_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 46 (IMR19_READ_POL_46): Bit
0h
46 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 45 (IMR19_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 44 (IMR19_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 43 (IMR19_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 42 (IMR19_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.

334818 623
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR19 Read Access Policy 41 (IMR19_READ_POL_41): Bit

0h
41 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 40 (IMR19_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 39 (IMR19_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 38 (IMR19_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 37 (IMR19_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 36 (IMR19_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 35 (IMR19_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 34 (IMR19_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 33 (IMR19_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 32 (IMR19_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 31 (IMR19_READ_POL_31): Bit
0h
31 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 30 (IMR19_READ_POL_30): Bit
0h
30 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 29 (IMR19_READ_POL_29): Bit
0h
29 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 28 (IMR19_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 27 (IMR19_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.

624 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR19 Read Access Policy 26 (IMR19_READ_POL_26): Bit

0h
26 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 25 (IMR19_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 24 (IMR19_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 23 (IMR19_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 22 (IMR19_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 21 (IMR19_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 20 (IMR19_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 19 (IMR19_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 18 (IMR19_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 17 (IMR19_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 16 (IMR19_READ_POL_16): Bit
0h
16 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 15 (IMR19_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 14 (IMR19_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 13 (IMR19_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 12 (IMR19_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.

334818 625
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR19 Read Access Policy 11 (IMR19_READ_POL_11): Bit

0h
11 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 10 (IMR19_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 9 (IMR19_READ_POL_9): Bit
0h
9 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 8 (IMR19_READ_POL_8): Bit
0h
8 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 7 (IMR19_READ_POL_7): Bit
0h
7 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 6 (IMR19_READ_POL_6): Bit
0h
6 vector used to determine which agents are allowed read access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 5 (IMR19_READ_POL_5): Bit
0h
5 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 4 (IMR19_READ_POL_4): Bit
0h
4 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 3 (IMR19_READ_POL_3): Bit
0h
3 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 2 (IMR19_READ_POL_2): Bit
0h
2 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 1 (IMR19_READ_POL_1): Bit
0h
1 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Read Access Policy 0 (IMR19_READ_POL_0): Bit
0h
0 vector used to determine which agents are allowed read access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.

5.9.102 IMR19 Write Access Policy

(B_CR_BIMR19WAC_0_0_0_MCHBAR)—Offset 6AE8h
This register, along with IMR19BASE, IMR19MASK and IMR19RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

626 334818
MCHBAR

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
IMR19_WRITE_POL_63
IMR19_WRITE_POL_62
IMR19_WRITE_POL_61
IMR19_WRITE_POL_60
IMR19_WRITE_POL_59
IMR19_WRITE_POL_58
IMR19_WRITE_POL_57
IMR19_WRITE_POL_56
IMR19_WRITE_POL_55
IMR19_WRITE_POL_54
IMR19_WRITE_POL_53
IMR19_WRITE_POL_52
IMR19_WRITE_POL_51
IMR19_WRITE_POL_50
IMR19_WRITE_POL_49
IMR19_WRITE_POL_48
IMR19_WRITE_POL_47
IMR19_WRITE_POL_46
IMR19_WRITE_POL_45
IMR19_WRITE_POL_44
IMR19_WRITE_POL_43
IMR19_WRITE_POL_42
IMR19_WRITE_POL_41
IMR19_WRITE_POL_40
IMR19_WRITE_POL_39
IMR19_WRITE_POL_38
IMR19_WRITE_POL_37
IMR19_WRITE_POL_36
IMR19_WRITE_POL_35
IMR19_WRITE_POL_34
IMR19_WRITE_POL_33
IMR19_WRITE_POL_32
IMR19_WRITE_POL_31
IMR19_WRITE_POL_30
IMR19_WRITE_POL_29
IMR19_WRITE_POL_28
IMR19_WRITE_POL_27
IMR19_WRITE_POL_26
IMR19_WRITE_POL_25
IMR19_WRITE_POL_24
IMR19_WRITE_POL_23
IMR19_WRITE_POL_22
IMR19_WRITE_POL_21
IMR19_WRITE_POL_20
IMR19_WRITE_POL_19
IMR19_WRITE_POL_18
IMR19_WRITE_POL_17
IMR19_WRITE_POL_16
IMR19_WRITE_POL_15
IMR19_WRITE_POL_14
IMR19_WRITE_POL_13
IMR19_WRITE_POL_12
IMR19_WRITE_POL_11
IMR19_WRITE_POL_10
IMR19_WRITE_POL_9
IMR19_WRITE_POL_8
IMR19_WRITE_POL_7
IMR19_WRITE_POL_6
IMR19_WRITE_POL_5
IMR19_WRITE_POL_4
IMR19_WRITE_POL_3
IMR19_WRITE_POL_2
IMR19_WRITE_POL_1
IMR19_WRITE_POL_0
Bit Default &
Field Name (ID): Description
Range Access

IMR19 Write Access Policy 63 (IMR19_WRITE_POL_63): Bit

0h
63 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 62 (IMR19_WRITE_POL_62): Bit
0h
62 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 61 (IMR19_WRITE_POL_61): Bit
0h
61 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 60 (IMR19_WRITE_POL_60): Bit
0h
60 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 59 (IMR19_WRITE_POL_59): Bit
0h
59 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 58 (IMR19_WRITE_POL_58): Bit
0h
58 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 57 (IMR19_WRITE_POL_57): Bit
0h
57 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 56 (IMR19_WRITE_POL_56): Bit
0h
56 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 55 (IMR19_WRITE_POL_55): Bit
0h
55 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 54 (IMR19_WRITE_POL_54): Bit
0h
54 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.

334818 627
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR19 Write Access Policy 53 (IMR19_WRITE_POL_53): Bit

0h
53 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 52 (IMR19_WRITE_POL_52): Bit
0h
52 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 51 (IMR19_WRITE_POL_51): Bit
0h
51 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 50 (IMR19_WRITE_POL_50): Bit
0h
50 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 49 (IMR19_WRITE_POL_49): Bit
0h
49 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 48 (IMR19_WRITE_POL_48): Bit
0h
48 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 47 (IMR19_WRITE_POL_47): Bit
0h
47 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 46 (IMR19_WRITE_POL_46): Bit
0h
46 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 45 (IMR19_WRITE_POL_45): Bit
0h
45 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 44 (IMR19_WRITE_POL_44): Bit
0h
44 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 43 (IMR19_WRITE_POL_43): Bit
0h
43 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 42 (IMR19_WRITE_POL_42): Bit
0h
42 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 41 (IMR19_WRITE_POL_41): Bit
0h
41 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 40 (IMR19_WRITE_POL_40): Bit
0h
40 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 39 (IMR19_WRITE_POL_39): Bit
0h
39 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.

628 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR19 Write Access Policy 38 (IMR19_WRITE_POL_38): Bit

0h
38 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 37 (IMR19_WRITE_POL_37): Bit
0h
37 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 36 (IMR19_WRITE_POL_36): Bit
0h
36 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 35 (IMR19_WRITE_POL_35): Bit
0h
35 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 34 (IMR19_WRITE_POL_34): Bit
0h
34 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 33 (IMR19_WRITE_POL_33): Bit
0h
33 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 32 (IMR19_WRITE_POL_32): Bit
0h
32 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 31 (IMR19_WRITE_POL_31): Bit
0h
31 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 30 (IMR19_WRITE_POL_30): Bit
0h
30 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 29 (IMR19_WRITE_POL_29): Bit
0h
29 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 28 (IMR19_WRITE_POL_28): Bit
0h
28 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 27 (IMR19_WRITE_POL_27): Bit
0h
27 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 26 (IMR19_WRITE_POL_26): Bit
0h
26 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 25 (IMR19_WRITE_POL_25): Bit
0h
25 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 24 (IMR19_WRITE_POL_24): Bit
0h
24 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.

334818 629
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR19 Write Access Policy 23 (IMR19_WRITE_POL_23): Bit

0h
23 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 22 (IMR19_WRITE_POL_22): Bit
0h
22 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 21 (IMR19_WRITE_POL_21): Bit
0h
21 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 20 (IMR19_WRITE_POL_20): Bit
0h
20 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 19 (IMR19_WRITE_POL_19): Bit
0h
19 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 18 (IMR19_WRITE_POL_18): Bit
0h
18 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 17 (IMR19_WRITE_POL_17): Bit
0h
17 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 16 (IMR19_WRITE_POL_16): Bit
0h
16 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 15 (IMR19_WRITE_POL_15): Bit
0h
15 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 14 (IMR19_WRITE_POL_14): Bit
0h
14 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 13 (IMR19_WRITE_POL_13): Bit
0h
13 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 12 (IMR19_WRITE_POL_12): Bit
0h
12 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 11 (IMR19_WRITE_POL_11): Bit
0h
11 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 10 (IMR19_WRITE_POL_10): Bit
0h
10 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 9 (IMR19_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.

630 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IMR19 Write Access Policy 8 (IMR19_WRITE_POL_8): Bit

0h
8 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 7 (IMR19_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 6 (IMR19_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 5 (IMR19_WRITE_POL_5): Bit
0h
5 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 4 (IMR19_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 3 (IMR19_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 2 (IMR19_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 1 (IMR19_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.
IMR19 Write Access Policy 0 (IMR19_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the IMR19 region, based on each agent's 6bit encoded SAI value.

5.9.103 MOT Out Base (B_CR_MOT_OUT_BASE_0_0_0_MCHBAR)—

Offset 6AF0h
This register contains the value of the start address of the MOT debug data region. The
smallest reserved region for MOT debug data, if enabled, is 16MB. The MOT region
must be power of two sized and naturally aligned to its size. The MOT region is evenly
distributed between the slices and interleaved on a 4K granularity. When generating
addresses, B-Unit MOT H/W within each slice ensures that the addresses it generates
are within the region mapped to that slice.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

334818 631
 MCHBAR

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IMR_EN
TR_EN

MOT_OUT_BASE
RESERVED_1

RESERVED_0
Bit Default &
Field Name (ID): Description
Range Access

IMR Enable (IMR_EN): Enables access checking for the MOT

0h region. Note: this does not enable MOT itself, but merely enables
31
RW access control checks for transactions that attempt to access the
MOT buffer.
Asset Classification AC[0]: Trace Enable (TR_EN): Enables
0h snooping of transactions to the IMR region by tracing agents such
30
RO as MOT. Reserved and set to 0 for the MOT region, since otherwise
this would enable recursive tracing and corrupt MOT buffer.

29
0h Reserved (RESERVED_1): Reserved.
RO

MOT_OUT Base (MOT_OUT_BASE): Specifies bits 38:24 of the

start address of the MOT memory region. Region size must be a
0h strict power of two, at least 16MB, and naturally aligned to the
28:14
RW size. These bits are compared with the result of the
MOT_OUT_MASK[28:14] applied to bits 38:24 of the incoming
address to determine if an access falls within the MOT region.

13:0
0h Reserved (RESERVED_0): Reserved.
RO

5.9.104 MOT Out Mask

(B_CR_MOT_OUT_MASK_0_0_0_MCHBAR)—Offset 6AF4h
This register specifies the size of the MOT region. If a request address [38:24] ANDed
with MOT_OUT_MASK[28:14] matches the MOT_OUT_BASE[38:24], then the request
falls within the MOT_OUT region.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

632 334818
MCHBAR

GT_IWB_EN
IA_IWB_EN
RESERVED_1

RESERVED_0
MOT_OUT_MASK
Bit Default &
Field Name (ID): Description
Range Access

Asset Classification AC[2]: GT Implicit Writeback Enable

(GT_IWB_EN): Enables implicit writebacks to protected region
from GT caching agent. When set to 1, enables implicit writeback
0h
31 HITM data from GT to be returned to the requester. When set to 0,
RW
inhibits HITM data from GT from being returned to the requester.
HITM data from IA cores may be returned to the requester,
depending on the setting of the IA_IWB_EN bit.
Asset Classification AC[1]: IA Implicit WB Enable
(IA_IWB_EN): Enables implicit writebacks to protected region
from IA caching agent. When set to 1, enables implicit writeback
0h
30 HITM data from IA cores to be returned to the requester. When set
RW
to 0, inhibits HITM data from IA cores from being returned to the
requester. HITM data from GT may be returned to the requester,
depending on the setting of the GT_IWB_EN bit.

29
0h Reserved (RESERVED_1): Reserved.
RO

MOT Out Mask (MOT_OUT_MASK): Specifies the size of the

0h MOT region. If Request Address [38:24] ANDed with
28:14
RW MOT_OUT_MASK[28:14] matches the MOT_OUT_BASE[28:14]
then the request falls within the MOT_OUT region.

13:0
0h Reserved (RESERVED_0): Reserved.
RO

5.9.105 MOT Buffer Control Policy

(B_CR_BMOT_BUF_CP_0_0_0_MCHBAR)—Offset 6AF8h
This register controls the access policy to BMOT_BUF_RAC, BMOT_BUF_WAC, and, self-
referentially, to itself. The requesting agent's 6bit encoded SAI value is used as an
index into this register's bits to determine both read access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010

334818 633
 MCHBAR

MOT_BUF_CTRL_POL
Bit Default &
Field Name (ID): Description
Range Access

MOT Buffer Control Policy (MOT_BUF_CTRL_POL): Bit vector

C0061010
202h
used to determine which agents are allowed access to the
63:0
RW BMOT_BUF_RAC, BMOT_BUF_WAC and BMOT_BUF_CP registers,
based on the value from each agent's 6bit SAI field.

5.9.106 MOT Buffer Read Access Policy

(B_CR_BMOT_BUF_RAC_0_0_0_MCHBAR)—Offset 6B00h
This register, along with MOTBASE, MOTMASK and MOT_BUF_WAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 60010017h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000001100000000000010000000000010111
MOT_BUF_READ_POL_63
MOT_BUF_READ_POL_62
MOT_BUF_READ_POL_61
MOT_BUF_READ_POL_60
MOT_BUF_READ_POL_59
MOT_BUF_READ_POL_58
MOT_BUF_READ_POL_57
MOT_BUF_READ_POL_56
MOT_BUF_READ_POL_55
MOT_BUF_READ_POL_54
MOT_BUF_READ_POL_53
MOT_BUF_READ_POL_52
MOT_BUF_READ_POL_51
MOT_BUF_READ_POL_50
MOT_BUF_READ_POL_49
MOT_BUF_READ_POL_48
MOT_BUF_READ_POL_47
MOT_BUF_READ_POL_46
MOT_BUF_READ_POL_45
MOT_BUF_READ_POL_44
MOT_BUF_READ_POL_43
MOT_BUF_READ_POL_42
MOT_BUF_READ_POL_41
MOT_BUF_READ_POL_40
MOT_BUF_READ_POL_39
MOT_BUF_READ_POL_38
MOT_BUF_READ_POL_37
MOT_BUF_READ_POL_36
MOT_BUF_READ_POL_35
MOT_BUF_READ_POL_34
MOT_BUF_READ_POL_33
MOT_BUF_READ_POL_32
MOT_BUF_READ_POL_31
MOT_BUF_READ_POL_30
MOT_BUF_READ_POL_29
MOT_BUF_READ_POL_28
MOT_BUF_READ_POL_27
MOT_BUF_READ_POL_26
MOT_BUF_READ_POL_25
MOT_BUF_READ_POL_24
MOT_BUF_READ_POL_23
MOT_BUF_READ_POL_22
MOT_BUF_READ_POL_21
MOT_BUF_READ_POL_20
MOT_BUF_READ_POL_19
MOT_BUF_READ_POL_18
MOT_BUF_READ_POL_17
MOT_BUF_READ_POL_16
MOT_BUF_READ_POL_15
MOT_BUF_READ_POL_14
MOT_BUF_READ_POL_13
MOT_BUF_READ_POL_12
MOT_BUF_READ_POL_11
MOT_BUF_READ_POL_10
MOT_BUF_READ_POL_9
MOT_BUF_READ_POL_8
MOT_BUF_READ_POL_7
MOT_BUF_READ_POL_6
MOT_BUF_READ_POL_5
MOT_BUF_READ_POL_4
MOT_BUF_READ_POL_3
MOT_BUF_READ_POL_2
MOT_BUF_READ_POL_1
MOT_BUF_READ_POL_0

Bit Default &

Field Name (ID): Description
Range Access

MOT Read Access Policy 63 (MOT_BUF_READ_POL_63): Bit

0h
63 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 62 (MOT_BUF_READ_POL_62): Bit
0h
62 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.

634 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

MOT Read Access Policy 61 (MOT_BUF_READ_POL_61): Bit

0h
61 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 60 (MOT_BUF_READ_POL_60): Bit
0h
60 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 59 (MOT_BUF_READ_POL_59): Bit
0h
59 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 58 (MOT_BUF_READ_POL_58): Bit
0h
58 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 57 (MOT_BUF_READ_POL_57): Bit
0h
57 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 56 (MOT_BUF_READ_POL_56): Bit
0h
56 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 55 (MOT_BUF_READ_POL_55): Bit
0h
55 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 54 (MOT_BUF_READ_POL_54): Bit
0h
54 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 53 (MOT_BUF_READ_POL_53): Bit
0h
53 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 52 (MOT_BUF_READ_POL_52): Bit
0h
52 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 51 (MOT_BUF_READ_POL_51): Bit
0h
51 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 50 (MOT_BUF_READ_POL_50): Bit
0h
50 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 49 (MOT_BUF_READ_POL_49): Bit
0h
49 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 48 (MOT_BUF_READ_POL_48): Bit
0h
48 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 47 (MOT_BUF_READ_POL_47): Bit
0h
47 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.

334818 635
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

MOT Read Access Policy 46 (MOT_BUF_READ_POL_46): Bit

0h
46 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 45 (MOT_BUF_READ_POL_45): Bit
0h
45 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 44 (MOT_BUF_READ_POL_44): Bit
0h
44 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 43 (MOT_BUF_READ_POL_43): Bit
0h
43 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 42 (MOT_BUF_READ_POL_42): Bit
0h
42 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 41 (MOT_BUF_READ_POL_41): Bit
0h
41 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 40 (MOT_BUF_READ_POL_40): Bit
0h
40 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 39 (MOT_BUF_READ_POL_39): Bit
0h
39 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 38 (MOT_BUF_READ_POL_38): Bit
0h
38 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 37 (MOT_BUF_READ_POL_37): Bit
0h
37 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 36 (MOT_BUF_READ_POL_36): Bit
0h
36 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 35 (MOT_BUF_READ_POL_35): Bit
0h
35 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 34 (MOT_BUF_READ_POL_34): Bit
0h
34 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 33 (MOT_BUF_READ_POL_33): Bit
0h
33 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 32 (MOT_BUF_READ_POL_32): Bit
0h
32 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.

636 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

MOT Read Access Policy 31 (MOT_BUF_READ_POL_31): Bit

0h
31 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 30 (MOT_BUF_READ_POL_30): Bit
1h
30 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 29 (MOT_BUF_READ_POL_29): Bit
1h
29 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 28 (MOT_BUF_READ_POL_28): Bit
0h
28 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 27 (MOT_BUF_READ_POL_27): Bit
0h
27 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 26 (MOT_BUF_READ_POL_26): Bit
0h
26 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 25 (MOT_BUF_READ_POL_25): Bit
0h
25 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 24 (MOT_BUF_READ_POL_24): Bit
0h
24 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 23 (MOT_BUF_READ_POL_23): Bit
0h
23 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 22 (MOT_BUF_READ_POL_22): Bit
0h
22 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 21 (MOT_BUF_READ_POL_21): Bit
0h
21 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 20 (MOT_BUF_READ_POL_20): Bit
0h
20 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 19 (MOT_BUF_READ_POL_19): Bit
0h
19 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 18 (MOT_BUF_READ_POL_18): Bit
0h
18 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 17 (MOT_BUF_READ_POL_17): Bit
0h
17 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.

334818 637
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

MOT Read Access Policy 16 (MOT_BUF_READ_POL_16): Bit

1h
16 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 15 (MOT_BUF_READ_POL_15): Bit
0h
15 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 14 (MOT_BUF_READ_POL_14): Bit
0h
14 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 13 (MOT_BUF_READ_POL_13): Bit
0h
13 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 12 (MOT_BUF_READ_POL_12): Bit
0h
12 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 11 (MOT_BUF_READ_POL_11): Bit
0h
11 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 10 (MOT_BUF_READ_POL_10): Bit
0h
10 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 9 (MOT_BUF_READ_POL_9): Bit
0h
9 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 8 (MOT_BUF_READ_POL_8): Bit
0h
8 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 7 (MOT_BUF_READ_POL_7): Bit
0h
7 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 6 (MOT_BUF_READ_POL_6): Bit
0h
6 vector used to determine which agents are allowed read access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 5 (MOT_BUF_READ_POL_5): Bit
0h
5 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 4 (MOT_BUF_READ_POL_4): Bit
1h
4 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 3 (MOT_BUF_READ_POL_3): Bit
0h
3 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 2 (MOT_BUF_READ_POL_2): Bit
1h
2 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.

638 334818
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Bit Default &

Field Name (ID): Description
Range Access

MOT Read Access Policy 1 (MOT_BUF_READ_POL_1): Bit

1h
1 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Read Access Policy 0 (MOT_BUF_READ_POL_0): Bit
1h
0 vector used to determine which agents are allowed read access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.

5.9.107 MOT Buffer Write Access Policy

(B_CR_BMOT_BUF_WAC_0_0_0_MCHBAR)—Offset 6B08h
This register, along with MOTBASE, MOTMASK and MOT_BUF_RAC, defines an isolated
region of memory that can be masked to prohibit certain agents from accessing
memory. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 60010000h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000001100000000000010000000000000000
MOT_BUF_WRITE_POL_63
MOT_BUF_WRITE_POL_62
MOT_BUF_WRITE_POL_61
MOT_BUF_WRITE_POL_60
MOT_BUF_WRITE_POL_59
MOT_BUF_WRITE_POL_58
MOT_BUF_WRITE_POL_57
MOT_BUF_WRITE_POL_56
MOT_BUF_WRITE_POL_55
MOT_BUF_WRITE_POL_54
MOT_BUF_WRITE_POL_53
MOT_BUF_WRITE_POL_52
MOT_BUF_WRITE_POL_51
MOT_BUF_WRITE_POL_50
MOT_BUF_WRITE_POL_49
MOT_BUF_WRITE_POL_48
MOT_BUF_WRITE_POL_47
MOT_BUF_WRITE_POL_46
MOT_BUF_WRITE_POL_45
MOT_BUF_WRITE_POL_44
MOT_BUF_WRITE_POL_43
MOT_BUF_WRITE_POL_42
MOT_BUF_WRITE_POL_41
MOT_BUF_WRITE_POL_40
MOT_BUF_WRITE_POL_39
MOT_BUF_WRITE_POL_38
MOT_BUF_WRITE_POL_37
MOT_BUF_WRITE_POL_36
MOT_BUF_WRITE_POL_35
MOT_BUF_WRITE_POL_34
MOT_BUF_WRITE_POL_33
MOT_BUF_WRITE_POL_32
MOT_BUF_WRITE_POL_31
MOT_BUF_WRITE_POL_30
MOT_BUF_WRITE_POL_29
MOT_BUF_WRITE_POL_28
MOT_BUF_WRITE_POL_27
MOT_BUF_WRITE_POL_26
MOT_BUF_WRITE_POL_25
MOT_BUF_WRITE_POL_24
MOT_BUF_WRITE_POL_23
MOT_BUF_WRITE_POL_22
MOT_BUF_WRITE_POL_21
MOT_BUF_WRITE_POL_20
MOT_BUF_WRITE_POL_19
MOT_BUF_WRITE_POL_18
MOT_BUF_WRITE_POL_17
MOT_BUF_WRITE_POL_16
MOT_BUF_WRITE_POL_15
MOT_BUF_WRITE_POL_14
MOT_BUF_WRITE_POL_13
MOT_BUF_WRITE_POL_12
MOT_BUF_WRITE_POL_11
MOT_BUF_WRITE_POL_10
MOT_BUF_WRITE_POL_9
MOT_BUF_WRITE_POL_8
MOT_BUF_WRITE_POL_7
MOT_BUF_WRITE_POL_6
MOT_BUF_WRITE_POL_5
MOT_BUF_WRITE_POL_4
MOT_BUF_WRITE_POL_3
MOT_BUF_WRITE_POL_2
MOT_BUF_WRITE_POL_1
MOT_BUF_WRITE_POL_0
Bit Default &
Field Name (ID): Description
Range Access

MOT Write Access Policy 63 (MOT_BUF_WRITE_POL_63):

0h Bit vector used to determine which agents are allowed write
63
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 62 (MOT_BUF_WRITE_POL_62):
0h Bit vector used to determine which agents are allowed write
62
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.

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Bit Default &

Field Name (ID): Description
Range Access

MOT Write Access Policy 61 (MOT_BUF_WRITE_POL_61):

0h Bit vector used to determine which agents are allowed write
61
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 60 (MOT_BUF_WRITE_POL_60):
0h Bit vector used to determine which agents are allowed write
60
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 59 (MOT_BUF_WRITE_POL_59):
0h Bit vector used to determine which agents are allowed write
59
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 58 (MOT_BUF_WRITE_POL_58):
0h Bit vector used to determine which agents are allowed write
58
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 57 (MOT_BUF_WRITE_POL_57):
0h Bit vector used to determine which agents are allowed write
57
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 56 (MOT_BUF_WRITE_POL_56):
0h Bit vector used to determine which agents are allowed write
56
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 55 (MOT_BUF_WRITE_POL_55):
0h Bit vector used to determine which agents are allowed write
55
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 54 (MOT_BUF_WRITE_POL_54):
0h Bit vector used to determine which agents are allowed write
54
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 53 (MOT_BUF_WRITE_POL_53):
0h Bit vector used to determine which agents are allowed write
53
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 52 (MOT_BUF_WRITE_POL_52):
0h Bit vector used to determine which agents are allowed write
52
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 51 (MOT_BUF_WRITE_POL_51):
0h Bit vector used to determine which agents are allowed write
51
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.

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Bit Default &

Field Name (ID): Description
Range Access

MOT Write Access Policy 50 (MOT_BUF_WRITE_POL_50):

0h Bit vector used to determine which agents are allowed write
50
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 49 (MOT_BUF_WRITE_POL_49):
0h Bit vector used to determine which agents are allowed write
49
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 48 (MOT_BUF_WRITE_POL_48):
0h Bit vector used to determine which agents are allowed write
48
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 47 (MOT_BUF_WRITE_POL_47):
0h Bit vector used to determine which agents are allowed write
47
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 46 (MOT_BUF_WRITE_POL_46):
0h Bit vector used to determine which agents are allowed write
46
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 45 (MOT_BUF_WRITE_POL_45):
0h Bit vector used to determine which agents are allowed write
45
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 44 (MOT_BUF_WRITE_POL_44):
0h Bit vector used to determine which agents are allowed write
44
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 43 (MOT_BUF_WRITE_POL_43):
0h Bit vector used to determine which agents are allowed write
43
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 42 (MOT_BUF_WRITE_POL_42):
0h Bit vector used to determine which agents are allowed write
42
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 41 (MOT_BUF_WRITE_POL_41):
0h Bit vector used to determine which agents are allowed write
41
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 40 (MOT_BUF_WRITE_POL_40):
0h Bit vector used to determine which agents are allowed write
40
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.

334818 641
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Bit Default &

Field Name (ID): Description
Range Access

MOT Write Access Policy 39 (MOT_BUF_WRITE_POL_39):

0h Bit vector used to determine which agents are allowed write
39
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 38 (MOT_BUF_WRITE_POL_38):
0h Bit vector used to determine which agents are allowed write
38
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 37 (MOT_BUF_WRITE_POL_37):
0h Bit vector used to determine which agents are allowed write
37
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 36 (MOT_BUF_WRITE_POL_36):
0h Bit vector used to determine which agents are allowed write
36
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 35 (MOT_BUF_WRITE_POL_35):
0h Bit vector used to determine which agents are allowed write
35
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 34 (MOT_BUF_WRITE_POL_34):
0h Bit vector used to determine which agents are allowed write
34
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 33 (MOT_BUF_WRITE_POL_33):
0h Bit vector used to determine which agents are allowed write
33
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 32 (MOT_BUF_WRITE_POL_32):
0h Bit vector used to determine which agents are allowed write
32
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 31 (MOT_BUF_WRITE_POL_31):
0h Bit vector used to determine which agents are allowed write
31
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 30 (MOT_BUF_WRITE_POL_30):
1h Bit vector used to determine which agents are allowed write
30
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 29 (MOT_BUF_WRITE_POL_29):
1h Bit vector used to determine which agents are allowed write
29
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.

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Bit Default &

Field Name (ID): Description
Range Access

MOT Write Access Policy 28 (MOT_BUF_WRITE_POL_28):

0h Bit vector used to determine which agents are allowed write
28
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 27 (MOT_BUF_WRITE_POL_27):
0h Bit vector used to determine which agents are allowed write
27
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 26 (MOT_BUF_WRITE_POL_26):
0h Bit vector used to determine which agents are allowed write
26
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 25 (MOT_BUF_WRITE_POL_25):
0h Bit vector used to determine which agents are allowed write
25
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 24 (MOT_BUF_WRITE_POL_24):
0h Bit vector used to determine which agents are allowed write
24
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 23 (MOT_BUF_WRITE_POL_23):
0h Bit vector used to determine which agents are allowed write
23
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 22 (MOT_BUF_WRITE_POL_22):
0h Bit vector used to determine which agents are allowed write
22
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 21 (MOT_BUF_WRITE_POL_21):
0h Bit vector used to determine which agents are allowed write
21
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 20 (MOT_BUF_WRITE_POL_20):
0h Bit vector used to determine which agents are allowed write
20
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 19 (MOT_BUF_WRITE_POL_19):
0h Bit vector used to determine which agents are allowed write
19
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 18 (MOT_BUF_WRITE_POL_18):
0h Bit vector used to determine which agents are allowed write
18
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.

334818 643
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

MOT Write Access Policy 17 (MOT_BUF_WRITE_POL_17):

0h Bit vector used to determine which agents are allowed write
17
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 16 (MOT_BUF_WRITE_POL_16):
1h Bit vector used to determine which agents are allowed write
16
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 15 (MOT_BUF_WRITE_POL_15):
0h Bit vector used to determine which agents are allowed write
15
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 14 (MOT_BUF_WRITE_POL_14):
0h Bit vector used to determine which agents are allowed write
14
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 13 (MOT_BUF_WRITE_POL_13):
0h Bit vector used to determine which agents are allowed write
13
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 12 (MOT_BUF_WRITE_POL_12):
0h Bit vector used to determine which agents are allowed write
12
RW access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 11 (MOT_BUF_WRITE_POL_11):
0h Bit vector used to determine which agents are allowed write
11
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 10 (MOT_BUF_WRITE_POL_10):
0h Bit vector used to determine which agents are allowed write
10
RO access to the MOT region, based on each agent's 6bit encoded SAI
value.
MOT Write Access Policy 9 (MOT_BUF_WRITE_POL_9): Bit
0h
9 vector used to determine which agents are allowed write access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Write Access Policy 8 (MOT_BUF_WRITE_POL_8): Bit
0h
8 vector used to determine which agents are allowed write access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Write Access Policy 7 (MOT_BUF_WRITE_POL_7): Bit
0h
7 vector used to determine which agents are allowed write access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Write Access Policy 6 (MOT_BUF_WRITE_POL_6): Bit
0h
6 vector used to determine which agents are allowed write access to
RO
the MOT region, based on each agent's 6bit encoded SAI value.

644 334818
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Bit Default &

Field Name (ID): Description
Range Access

MOT Write Access Policy 5 (MOT_BUF_WRITE_POL_5): Bit

0h
5 vector used to determine which agents are allowed write access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Write Access Policy 4 (MOT_BUF_WRITE_POL_4): Bit
0h
4 vector used to determine which agents are allowed write access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Write Access Policy 3 (MOT_BUF_WRITE_POL_3): Bit
0h
3 vector used to determine which agents are allowed write access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Write Access Policy 2 (MOT_BUF_WRITE_POL_2): Bit
0h
2 vector used to determine which agents are allowed write access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Write Access Policy 1 (MOT_BUF_WRITE_POL_1): Bit
0h
1 vector used to determine which agents are allowed write access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.
MOT Write Access Policy 0 (MOT_BUF_WRITE_POL_0): Bit
0h
0 vector used to determine which agents are allowed write access to
RW
the MOT region, based on each agent's 6bit encoded SAI value.

5.9.108 IMR Global BM Control Policy

(B_CR_BIMRGLOBAL_BM_CP_0_0_0_MCHBAR)—Offset
6B10h
Defines the policy register that specifies who is allowed write access to
BIMRGLOBAL_BM_WAC register.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010
BM_CTRL_POL

334818 645
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

BM Control Policy (BM_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed write access to
63:0
RW BIMRGLOBAL_BM_WAC, based on each agent's 6bit encoded SAI
value.

5.9.109 IMR Global BM Read Access Control

(B_CR_BIMRGLOBAL_BM_RAC_0_0_0_MCHBAR)—Offset
6B18h
Defines the policy register that specifies who is allowed to read the BASE/MASK
registers for IMR0-IMR15. This single common policy register protects reads to all
base/mask registers.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: FFFFFFFFFFFFFFFFh

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

1111111111111111111111111111111111111111111111111111111111111111
BM_READ_POL

Bit Default &

Field Name (ID): Description
Range Access

BM Read Access Policy (BM_READ_POL): Bit vector used to

FFFFFFFFF
FFFFFFFh
determine which agents are allowed read access to all IMRxBASE
63:0
RO and IMRxMASK registers, based on each agent's 6bit encoded SAI
value.

5.9.110 IMR Global BM Write Access Policy

(B_CR_BIMRGLOBAL_BM_WAC_0_0_0_MCHBAR)—Offset
6B20h
Defines the policy register that specifies who is allowed to overwrite the BASE/MASK
registers for IMR0-IMR15. This single common policy register protects writes to all
base/mask registers.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

646 334818
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Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010

BM_WRITE_POL
Bit Default &
Field Name (ID): Description
Range Access

BM Write Access Policy (BM_WRITE_POL): Bit vector used to

C0061010
202h
determine which agents are allowed write access to all IMRxBASE
63:0
RW and IMRxMASK registers, based on each agent's 6bit encoded SAI
value.

5.9.111 Graphics Stolen Memory Control Policy

(B_CR_BGSMCP_0_0_0_MCHBAR)—Offset 6B28h
This register controls the access policy to the Read Access Policy BGSMRAC, Write
Access Policy BGSMWAC and self-referentially, to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010
GSM_CTRL_POL

Bit Default &

Field Name (ID): Description
Range Access

GSM Control Policy (GSM_CTRL_POL): Bit vector used to

C0061010
202h
determine which agents are allowed access to the BGSMRAC,
63:0
RW BGSMWAC and BGSMCP registers, based on the value from each
agent's 6bit SAI field.

334818 647
 MCHBAR

5.9.112 GSM Read Access Policy

(B_CR_BGSMRAC_0_0_0_MCHBAR)—Offset 6B30h
This register configures the Read Access Policy to the memory range from BGSM to
TOLUD1. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 100060010100h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000100000000000001100000000000010000000100000000

GSM_SAI_POL_9
GSM_SAI_POL_8
GSM_SAI_POL_7
GSM_SAI_POL_6
GSM_SAI_POL_5
GSM_SAI_POL_4
GSM_SAI_POL_3
GSM_SAI_POL_2
GSM_SAI_POL_1
GSM_SAI_POL_0
GSM_SAI_POL_63
GSM_SAI_POL_62
GSM_SAI_POL_61
GSM_SAI_POL_60
GSM_SAI_POL_59
GSM_SAI_POL_58
GSM_SAI_POL_57
GSM_SAI_POL_56
GSM_SAI_POL_55
GSM_SAI_POL_54
GSM_SAI_POL_53
GSM_SAI_POL_52
GSM_SAI_POL_51
GSM_SAI_POL_50
GSM_SAI_POL_49
GSM_SAI_POL_48
GSM_SAI_POL_47
GSM_SAI_POL_46
GSM_SAI_POL_45
GSM_SAI_POL_44
GSM_SAI_POL_43
GSM_SAI_POL_42
GSM_SAI_POL_41
GSM_SAI_POL_40
GSM_SAI_POL_39
GSM_SAI_POL_38
GSM_SAI_POL_37
GSM_SAI_POL_36
GSM_SAI_POL_35
GSM_SAI_POL_34
GSM_SAI_POL_33
GSM_SAI_POL_32
GSM_SAI_POL_31
GSM_SAI_POL_30
GSM_SAI_POL_29
GSM_SAI_POL_28
GSM_SAI_POL_27
GSM_SAI_POL_26
GSM_SAI_POL_25
GSM_SAI_POL_24
GSM_SAI_POL_23
GSM_SAI_POL_22
GSM_SAI_POL_21
GSM_SAI_POL_20
GSM_SAI_POL_19
GSM_SAI_POL_18
GSM_SAI_POL_17
GSM_SAI_POL_16
GSM_SAI_POL_15
GSM_SAI_POL_14
GSM_SAI_POL_13
GSM_SAI_POL_12
GSM_SAI_POL_11
GSM_SAI_POL_10
Bit Default &
Field Name (ID): Description
Range Access

SMM Read Access Policy 63 (GSM_SAI_POL_63): Bit vector

0h used to determine which agents are allowed read access to the
63
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 62 (GSM_SAI_POL_62): Bit vector
0h used to determine which agents are allowed read access to the
62
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 61 (GSM_SAI_POL_61): Bit vector
0h used to determine which agents are allowed read access to the
61
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 60 (GSM_SAI_POL_60): Bit vector
0h used to determine which agents are allowed read access to the
60
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 59 (GSM_SAI_POL_59): Bit vector
0h used to determine which agents are allowed read access to the
59
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 58 (GSM_SAI_POL_58): Bit vector
0h used to determine which agents are allowed read access to the
58
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.

648 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

SMM Read Access Policy 57 (GSM_SAI_POL_57): Bit vector

0h used to determine which agents are allowed read access to the
57
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 56 (GSM_SAI_POL_56): Bit vector
0h used to determine which agents are allowed read access to the
56
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 55 (GSM_SAI_POL_55): Bit vector
0h used to determine which agents are allowed read access to the
55
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 54 (GSM_SAI_POL_54): Bit vector
0h used to determine which agents are allowed read access to the
54
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 53 (GSM_SAI_POL_53): Bit vector
0h used to determine which agents are allowed read access to the
53
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 52 (GSM_SAI_POL_52): Bit vector
0h used to determine which agents are allowed read access to the
52
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 51 (GSM_SAI_POL_51): Bit vector
0h used to determine which agents are allowed read access to the
51
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 50 (GSM_SAI_POL_50): Bit vector
0h used to determine which agents are allowed read access to the
50
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 49 (GSM_SAI_POL_49): Bit vector
0h used to determine which agents are allowed read access to the
49
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 48 (GSM_SAI_POL_48): Bit vector
0h used to determine which agents are allowed read access to the
48
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 47 (GSM_SAI_POL_47): Bit vector
0h used to determine which agents are allowed read access to the
47
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.

334818 649
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

SMM Read Access Policy 46 (GSM_SAI_POL_46): Bit vector

0h used to determine which agents are allowed read access to the
46
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 45 (GSM_SAI_POL_45): Bit vector
0h used to determine which agents are allowed read access to the
45
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 44 (GSM_SAI_POL_44): Bit vector
1h used to determine which agents are allowed read access to the
44
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 43 (GSM_SAI_POL_43): Bit vector
0h used to determine which agents are allowed read access to the
43
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 42 (GSM_SAI_POL_42): Bit vector
0h used to determine which agents are allowed read access to the
42
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 41 (GSM_SAI_POL_41): Bit vector
0h used to determine which agents are allowed read access to the
41
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 40 (GSM_SAI_POL_40): Bit vector
0h used to determine which agents are allowed read access to the
40
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 39 (GSM_SAI_POL_39): Bit vector
0h used to determine which agents are allowed read access to the
39
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 38 (GSM_SAI_POL_38): Bit vector
0h used to determine which agents are allowed read access to the
38
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 37 (GSM_SAI_POL_37): Bit vector
0h used to determine which agents are allowed read access to the
37
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 36 (GSM_SAI_POL_36): Bit vector
0h used to determine which agents are allowed read access to the
36
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.

650 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

SMM Read Access Policy 35 (GSM_SAI_POL_35): Bit vector

0h used to determine which agents are allowed read access to the
35
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 34 (GSM_SAI_POL_34): Bit vector
0h used to determine which agents are allowed read access to the
34
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 33 (GSM_SAI_POL_33): Bit vector
0h used to determine which agents are allowed read access to the
33
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 32 (GSM_SAI_POL_32): Bit vector
0h used to determine which agents are allowed read access to the
32
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 31 (GSM_SAI_POL_31): Bit vector
0h used to determine which agents are allowed read access to the
31
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 30 (GSM_SAI_POL_30): Bit vector
1h used to determine which agents are allowed read access to the
30
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 29 (GSM_SAI_POL_29): Bit vector
1h used to determine which agents are allowed read access to the
29
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 28 (GSM_SAI_POL_28): Bit vector
0h used to determine which agents are allowed read access to the
28
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 27 (GSM_SAI_POL_27): Bit vector
0h used to determine which agents are allowed read access to the
27
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 26 (GSM_SAI_POL_26): Bit vector
0h used to determine which agents are allowed read access to the
26
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 25 (GSM_SAI_POL_25): Bit vector
0h used to determine which agents are allowed read access to the
25
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.

334818 651
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

SMM Read Access Policy 24 (GSM_SAI_POL_24): Bit vector

0h used to determine which agents are allowed read access to the
24
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 23 (GSM_SAI_POL_23): Bit vector
0h used to determine which agents are allowed read access to the
23
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 22 (GSM_SAI_POL_22): Bit vector
0h used to determine which agents are allowed read access to the
22
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 21 (GSM_SAI_POL_21): Bit vector
0h used to determine which agents are allowed read access to the
21
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 20 (GSM_SAI_POL_20): Bit vector
0h used to determine which agents are allowed read access to the
20
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 19 (GSM_SAI_POL_19): Bit vector
0h used to determine which agents are allowed read access to the
19
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 18 (GSM_SAI_POL_18): Bit vector
0h used to determine which agents are allowed read access to the
18
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 17 (GSM_SAI_POL_17): Bit vector
0h used to determine which agents are allowed read access to the
17
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 16 (GSM_SAI_POL_16): Bit vector
1h used to determine which agents are allowed read access to the
16
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 15 (GSM_SAI_POL_15): Bit vector
0h used to determine which agents are allowed read access to the
15
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 14 (GSM_SAI_POL_14): Bit vector
0h used to determine which agents are allowed read access to the
14
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.

652 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

SMM Read Access Policy 13 (GSM_SAI_POL_13): Bit vector

0h used to determine which agents are allowed read access to the
13
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 12 (GSM_SAI_POL_12): Bit vector
0h used to determine which agents are allowed read access to the
12
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 11 (GSM_SAI_POL_11): Bit vector
0h used to determine which agents are allowed read access to the
11
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 10 (GSM_SAI_POL_10): Bit vector
0h used to determine which agents are allowed read access to the
10
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 9 (GSM_SAI_POL_9): Bit vector
0h used to determine which agents are allowed read access to the
9
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 8 (GSM_SAI_POL_8): Bit vector
1h used to determine which agents are allowed read access to the
8
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 7 (GSM_SAI_POL_7): Bit vector
0h used to determine which agents are allowed read access to the
7
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 6 (GSM_SAI_POL_6): Bit vector
0h used to determine which agents are allowed read access to the
6
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 5 (GSM_SAI_POL_5): Bit vector
0h used to determine which agents are allowed read access to the
5
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 4 (GSM_SAI_POL_4): Bit vector
0h used to determine which agents are allowed read access to the
4
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 3 (GSM_SAI_POL_3): Bit vector
0h used to determine which agents are allowed read access to the
3
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.

334818 653
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

SMM Read Access Policy 2 (GSM_SAI_POL_2): Bit vector

0h used to determine which agents are allowed read access to the
2
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 1 (GSM_SAI_POL_1): Bit vector
0h used to determine which agents are allowed read access to the
1
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
SMM Read Access Policy 0 (GSM_SAI_POL_0): Bit vector
0h used to determine which agents are allowed read access to the
0
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.

5.9.113 GSM Write Access Policy

(B_CR_BGSMWAC_0_0_0_MCHBAR)—Offset 6B38h
This register configures the Write Access Policy for the memory range from BGSM to
TOLUD1. The requesting agent's 6bit encoded SAI value is used as an index into this
register's bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 100060010100h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000100000000000001100000000000010000000100000000
GSM_SAI_POL_63
GSM_SAI_POL_62
GSM_SAI_POL_61
GSM_SAI_POL_60
GSM_SAI_POL_59
GSM_SAI_POL_58
GSM_SAI_POL_57
GSM_SAI_POL_56
GSM_SAI_POL_55
GSM_SAI_POL_54
GSM_SAI_POL_53
GSM_SAI_POL_52
GSM_SAI_POL_51
GSM_SAI_POL_50
GSM_SAI_POL_49
GSM_SAI_POL_48
GSM_SAI_POL_47
GSM_SAI_POL_46
GSM_SAI_POL_45
GSM_SAI_POL_44
GSM_SAI_POL_43
GSM_SAI_POL_42
GSM_SAI_POL_41
GSM_SAI_POL_40
GSM_SAI_POL_39
GSM_SAI_POL_38
GSM_SAI_POL_37
GSM_SAI_POL_36
GSM_SAI_POL_35
GSM_SAI_POL_34
GSM_SAI_POL_33
GSM_SAI_POL_32
GSM_SAI_POL_31
GSM_SAI_POL_30
GSM_SAI_POL_29
GSM_SAI_POL_28
GSM_SAI_POL_27
GSM_SAI_POL_26
GSM_SAI_POL_25
GSM_SAI_POL_24
GSM_SAI_POL_23
GSM_SAI_POL_22
GSM_SAI_POL_21
GSM_SAI_POL_20
GSM_SAI_POL_19
GSM_SAI_POL_18
GSM_SAI_POL_17
GSM_SAI_POL_16
GSM_SAI_POL_15
GSM_SAI_POL_14
GSM_SAI_POL_13
GSM_SAI_POL_12
GSM_SAI_POL_11
GSM_SAI_POL_10
GSM_SAI_POL_9
GSM_SAI_POL_8
GSM_SAI_POL_7
GSM_SAI_POL_6
GSM_SAI_POL_5
GSM_SAI_POL_4
GSM_SAI_POL_3
GSM_SAI_POL_2
GSM_SAI_POL_1
GSM_SAI_POL_0

Bit Default &

Field Name (ID): Description
Range Access

GSM Write Access Policy 63 (GSM_SAI_POL_63): Bit vector

0h used to determine which agents are allowed write access to the
63
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 62 (GSM_SAI_POL_62): Bit vector
0h used to determine which agents are allowed write access to the
62
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.

654 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

GSM Write Access Policy 61 (GSM_SAI_POL_61): Bit vector

0h used to determine which agents are allowed write access to the
61
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 60 (GSM_SAI_POL_60): Bit vector
0h used to determine which agents are allowed write access to the
60
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 59 (GSM_SAI_POL_59): Bit vector
0h used to determine which agents are allowed write access to the
59
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 58 (GSM_SAI_POL_58): Bit vector
0h used to determine which agents are allowed write access to the
58
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 57 (GSM_SAI_POL_57): Bit vector
0h used to determine which agents are allowed write access to the
57
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 56 (GSM_SAI_POL_56): Bit vector
0h used to determine which agents are allowed write access to the
56
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 55 (GSM_SAI_POL_55): Bit vector
0h used to determine which agents are allowed write access to the
55
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 54 (GSM_SAI_POL_54): Bit vector
0h used to determine which agents are allowed write access to the
54
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 53 (GSM_SAI_POL_53): Bit vector
0h used to determine which agents are allowed write access to the
53
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 52 (GSM_SAI_POL_52): Bit vector
0h used to determine which agents are allowed write access to the
52
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 51 (GSM_SAI_POL_51): Bit vector
0h used to determine which agents are allowed write access to the
51
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.

334818 655
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

GSM Write Access Policy 50 (GSM_SAI_POL_50): Bit vector

0h used to determine which agents are allowed write access to the
50
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 49 (GSM_SAI_POL_49): Bit vector
0h used to determine which agents are allowed write access to the
49
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 48 (GSM_SAI_POL_48): Bit vector
0h used to determine which agents are allowed write access to the
48
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 47 (GSM_SAI_POL_47): Bit vector
0h used to determine which agents are allowed write access to the
47
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 46 (GSM_SAI_POL_46): Bit vector
0h used to determine which agents are allowed write access to the
46
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 45 (GSM_SAI_POL_45): Bit vector
0h used to determine which agents are allowed write access to the
45
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 44 (GSM_SAI_POL_44): Bit vector
1h used to determine which agents are allowed write access to the
44
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 43 (GSM_SAI_POL_43): Bit vector
0h used to determine which agents are allowed write access to the
43
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 42 (GSM_SAI_POL_42): Bit vector
0h used to determine which agents are allowed write access to the
42
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 41 (GSM_SAI_POL_41): Bit vector
0h used to determine which agents are allowed write access to the
41
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 40 (GSM_SAI_POL_40): Bit vector
0h used to determine which agents are allowed write access to the
40
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.

656 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

GSM Write Access Policy 39 (GSM_SAI_POL_39): Bit vector

0h used to determine which agents are allowed write access to the
39
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 38 (GSM_SAI_POL_38): Bit vector
0h used to determine which agents are allowed write access to the
38
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 37 (GSM_SAI_POL_37): Bit vector
0h used to determine which agents are allowed write access to the
37
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 36 (GSM_SAI_POL_36): Bit vector
0h used to determine which agents are allowed write access to the
36
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 35 (GSM_SAI_POL_35): Bit vector
0h used to determine which agents are allowed write access to the
35
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 34 (GSM_SAI_POL_34): Bit vector
0h used to determine which agents are allowed write access to the
34
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 33 (GSM_SAI_POL_33): Bit vector
0h used to determine which agents are allowed write access to the
33
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 32 (GSM_SAI_POL_32): Bit vector
0h used to determine which agents are allowed write access to the
32
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 31 (GSM_SAI_POL_31): Bit vector
0h used to determine which agents are allowed write access to the
31
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 30 (GSM_SAI_POL_30): Bit vector
1h used to determine which agents are allowed write access to the
30
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 29 (GSM_SAI_POL_29): Bit vector
1h used to determine which agents are allowed write access to the
29
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.

334818 657
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

GSM Write Access Policy 28 (GSM_SAI_POL_28): Bit vector

0h used to determine which agents are allowed write access to the
28
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 27 (GSM_SAI_POL_27): Bit vector
0h used to determine which agents are allowed write access to the
27
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 26 (GSM_SAI_POL_26): Bit vector
0h used to determine which agents are allowed write access to the
26
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 25 (GSM_SAI_POL_25): Bit vector
0h used to determine which agents are allowed write access to the
25
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 24 (GSM_SAI_POL_24): Bit vector
0h used to determine which agents are allowed write access to the
24
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 23 (GSM_SAI_POL_23): Bit vector
0h used to determine which agents are allowed write access to the
23
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 22 (GSM_SAI_POL_22): Bit vector
0h used to determine which agents are allowed write access to the
22
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 21 (GSM_SAI_POL_21): Bit vector
0h used to determine which agents are allowed write access to the
21
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 20 (GSM_SAI_POL_20): Bit vector
0h used to determine which agents are allowed write access to the
20
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 19 (GSM_SAI_POL_19): Bit vector
0h used to determine which agents are allowed write access to the
19
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 18 (GSM_SAI_POL_18): Bit vector
0h used to determine which agents are allowed write access to the
18
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.

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Bit Default &

Field Name (ID): Description
Range Access

GSM Write Access Policy 17 (GSM_SAI_POL_17): Bit vector

0h used to determine which agents are allowed write access to the
17
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 16 (GSM_SAI_POL_16): Bit vector
1h used to determine which agents are allowed write access to the
16
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 15 (GSM_SAI_POL_15): Bit vector
0h used to determine which agents are allowed write access to the
15
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 14 (GSM_SAI_POL_14): Bit vector
0h used to determine which agents are allowed write access to the
14
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 13 (GSM_SAI_POL_13): Bit vector
0h used to determine which agents are allowed write access to the
13
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 12 (GSM_SAI_POL_12): Bit vector
0h used to determine which agents are allowed write access to the
12
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 11 (GSM_SAI_POL_11): Bit vector
0h used to determine which agents are allowed write access to the
11
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 10 (GSM_SAI_POL_10): Bit vector
0h used to determine which agents are allowed write access to the
10
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 9 (GSM_SAI_POL_9): Bit vector
0h used to determine which agents are allowed write access to the
9
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 8 (GSM_SAI_POL_8): Bit vector
1h used to determine which agents are allowed write access to the
8
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 7 (GSM_SAI_POL_7): Bit vector
0h used to determine which agents are allowed write access to the
7
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.

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 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

GSM Write Access Policy 6 (GSM_SAI_POL_6): Bit vector

0h used to determine which agents are allowed write access to the
6
RO memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 5 (GSM_SAI_POL_5): Bit vector
0h used to determine which agents are allowed write access to the
5
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 4 (GSM_SAI_POL_4): Bit vector
0h used to determine which agents are allowed write access to the
4
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 3 (GSM_SAI_POL_3): Bit vector
0h used to determine which agents are allowed write access to the
3
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 2 (GSM_SAI_POL_2): Bit vector
0h used to determine which agents are allowed write access to the
2
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 1 (GSM_SAI_POL_1): Bit vector
0h used to determine which agents are allowed write access to the
1
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.
GSM Write Access Policy 0 (GSM_SAI_POL_0): Bit vector
0h used to determine which agents are allowed write access to the
0
RW memory range from BGSM to TOLUD1, based on each agent's 6bit
encoded SAI value.

5.9.114 TPM Control Policy (B_CR_TPM_CP_0_0_0_MCHBAR)—

Offset 6B40h
Defines the control policy register for TPM group.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010
CTRL_POL

660 334818
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Bit Default &

Field Name (ID): Description
Range Access

C0061010 TPM Control Policy (CTRL_POL): Bit vector used to determine

63:0 202h which agents are allowed write access to TPM_AC register, based
RW on each agent's 6-bit encoded SAI value.

5.9.115 TPM Access Control (B_CR_TPM_AC_0_0_0_MCHBAR)—

Offset 6B48h
Defines the policy register that specifies who is allowed read/write access to the
TPM_SELECTOR register.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010
AC_POL

Bit Default &

Field Name (ID): Description
Range Access

C0061010 TPM Access Policy (AC_POL): Bit vector used to determine

63:0 202h which agents are allowed read/write access to TPM_SELECTOR,
RW based on each agent's 6-bit encoded SAI value.

5.9.116 BGSM Control Register

(B_CR_BGSM_CTRL_0_0_0_MCHBAR)—Offset 6B50h
Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 19h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

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RS0_EN
GT_IWB_EN
IA_IWB_EN
RESERVED_0

TRACE_EN
RANGE_CHECK_EN
Bit Default &
Field Name (ID): Description
Range Access

31:5
0h Reserved (RESERVED_0): Reserved.
RO

RS0 Asset Classification Bit for Graphics and Data Stolen

Memory (RS0_EN): PII transactions from RS0 that hit the
Graphics and Data Stolen Memory range will be allowed access
1h only when both of the following conditions are met: a) Request
4
RW SAI is in the legal permitted list as specified in the RAC/WAC
policy registers and b) GSM_RS0_EN bit is set to 1. PII RS0
transactions targeting DRAM that do not hit any enabled IMR or
special protected regions will always be allowed access.
GT Implicit WB Enable (GT_IWB_EN): Enables implicit
writebacks to protected region from GT caching agent. When set
to 1, enables implicit writeback data HITM data from GT to be
1h
3 returned to the requester. When set to 0, inhibits HITM data from
RW
GT from being returned to the requester. HITM data from IA cores
may be returned to the requester depending on the setting of the
IA_IWB_EN bit.
IA Implicit WB Enable (IA_IWB_EN): Enables implicit
writebacks to protected region from IA caching agent. When set to
1, enables implicit writeback data HITM data from IA cores to be
0h
2 returned to the requester. When set to 0, inhibits HITM data from
RW
IA cores from being returned to the requester. HITM data from GT
may be returned to the requester, depending on the setting of the
GT_IWB_EN bit.
0h Trace Enable (TRACE_EN): Enables snooping of transactions to
1
RW the Graphics Stolen Memory region by tracing agents.
1h Range Check Enable (RANGE_CHECK_EN): Enables SAI
0
RW checking for the memory range from BGSM to TOLUD-1

5.9.117 SMM Control Register

(B_CR_BSMR_CTRL_0_0_0_MCHBAR)—Offset 6B54h
Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 7h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

662 334818
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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

RS0_EN
GT_IWB_EN
IA_IWB_EN
TRACE_EN
RESERVED_0

RANGE_CHECK_EN
Bit Default &
Field Name (ID): Description
Range Access

31:5
0h Reserved (RESERVED_0): Reserved.
RO

RS0 Asset Classification Bit for SMM Region (RS0_EN): No

0h PII transaction is allowed access to SMM region. As such RS0
4
RO asset classification bit does not apply and hence provisioned as a
readonly bit and set to 0.
GT Implicit Writeback Enable (GT_IWB_EN): Enables implicit
writebacks to protected region from GT caching agent. When set
to 1, enables implicit writeback data HITM data from GT to be
0h
3 returned to the requester. When set to 0, inhibits HITM data from
RW
GT from being returned to the requester. HITM data from IA cores
may be returned to the requester, depending on the setting of the
IA_IWB_EN bit.
IA Implicit Writeback Enable (IA_IWB_EN): Enables implicit
writebacks to protected region from IA caching agent. When set to
1, enables implicit writeback data HITM data from IA cores to be
1h
2 returned to the requester. When set to 0, inhibits HITM data from
RW
IA cores from being returned to the requester. HITM data from GT
may be returned to the requester depending on the setting of the
GT_IWB_EN bit.
1h Trace Enable (TRACE_EN): Enables snooping of transactions to
1
RW the SMM region by tracing agents.
1h Range Check Enable (RANGE_CHECK_EN): Enables SAI
0
RW checking for the SMM memory range: TSEGMB to BGSM.

5.9.118 Default VTd Control Register

(B_CR_BDEFVTDPMR_CTRL_0_0_0_MCHBAR)—Offset
6B58h
Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1Ch

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0

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RS0_EN

IA_IWB_EN
RESERVED_1

GT_IWB_EN

TRACE_EN
RESERVED_0
Bit Default &
Field Name (ID): Description
Range Access

31:5
0h Reserved (RESERVED_1): Reserved.
RO

RS0 Asset Classification Bit for the High and Low VTd PMRs
(RS0_EN): PII transactions from RS0 that hit VTd PMR high and
low memory ranges will be allowed access only when both of the
1h following conditions are met: a) Request SAI is in the legal
4
RW permitted list as specified in the RAC/WAC policy registers and b)
VTDPMR_RS0_EN bit is set to 1. PII RS0 transactions targeting
DRAM that do not hit any enabled IMR or special protected regions
will always be allowed access.
GT Implicit Writeback Enable (GT_IWB_EN): Enables implicit
writebacks to protected region from GT caching agent. When set
to 1, enables implicit writeback data HITM data from GT to be
1h
3 returned to the requester. When set to 0, inhibits HITM data from
RW
GT from being returned to the requester. HITM data from IA cores
may be returned to the requester, depending on the setting of the
IA_IWB_EN bit.
IA Implicit Writeback Enable (IA_IWB_EN): Enables implicit
writebacks to protected region from IA caching agent. When set to
1, enables implicit writeback data HITM data from IA cores to be
1h
2 returned to the requester. When set to 0, inhibits HITM data from
RW
IA cores from being returned to the requester. HITM data from GT
may be returned to the requester, depending on the setting of the
GT_IWB_EN bit.
0h Trace Enable (TRACE_EN): Enables snooping of transactions to
1
RW the Default VTd PHM and PLM regions by tracing agents.

0
0h Reserved (RESERVED_0): Reserved.
RO

5.9.119 MOT Trigger Trace Control

(B_CR_MOT_TRIG_TRACE_CTRL_0_0_0_MCHBAR)—Offset
6B7Ch
This register is the global MOT enable.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: E0000000h

664 334818
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3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ENABLE_EXTERNAL_TRIGGER_OUT_0
ENABLE_MOT_TRIGGER_1
ENABLE_MOT_TRIGGER_0
ENABLE_MOT_FILTER_1
ENABLE_MOT_FILTER_0
ENABLE_MOT
FLUSH_TIMER_PERIOD

RESERVED_0

MOT_STORAGE_ACTIVE

MOT_TRACE_STORAGE_STOP_SOURCE

MOT_TRACE_STORAGE_START_SOURCE

ENABLE_EXTERNAL_TRIGGER_IN_1
ENABLE_EXTERNAL_TRIGGER_IN_0
STICKY_TRIGGER_1_MATCH
STICKY_TRIGGER_0_MATCH
STICKY_FILTER_1_MATCH
STICKY_FILTER_0_MATCH

TRIGGER_OUT_SOURCE
Bit Default &
Field Name (ID): Description
Range Access

Flush Timer Period (FLUSH_TIMER_PERIOD): Specifies the

Eh
31:28 duration of the periodic MOT flush timer. Duration is 2^N cycles of
RW
a 19.2 MHz clock, where N is the value specified in the field.

27
0h Reserved (RESERVED_0): Reserved.
RO

Sticky Trigger 1 Match (STICKY_TRIGGER_1_MATCH): 1

0h
26 indicates Trigger 1 match. Cleared by powergood or explicit SW
RW/V
write.
Sticky Trigger 0 Match (STICKY_TRIGGER_0_MATCH): 1
0h
25 indicates Trigger 0 match. Cleared by powergood or explicit SW
RW/V
write.
Sticky Filter 1 Match (STICKY_FILTER_1_MATCH): 1
0h
24 indicates Filter 1 match. Cleared by powergood or explicit SW
RW/V
write.
Sticky Filter 0 Match (STICKY_FILTER_0_MATCH): 1
0h
23 indicates Filter 0 match. Cleared by powergood or explicit SW
RW/V
write.
MOT Storage Active (MOT_STORAGE_ACTIVE): Current
0h
22 status of MOT storage to memory. Used to save/restore trigger
RW/V
state across power states.
MOT Trace Storage Stop Source (MOT_TRACE_STORAGE_STOP_SOURCE): A
bit field allowing multiple triggers to result in a trace storage stop. Storage stop is the
logical OR of trigger sources selected. Note that selecting the same trigger to start
and stop trace storage results in start trace storage only.
• Bit position 5: External Trigger in 1

21:16
0h • Bit position 4: External Trigger in 0
RW
• Bit position 3: MOT Trigger 1
• Bit position 2: MOT Trigger 0
• Bit position 1: MOT Filter 1 match
• Bit position 0: MOT Filter 0 match

334818 665
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

MOT Trace Storage Start Source

(MOT_TRACE_STORAGE_START_SOURCE): A bit field allowing
multiple triggers to result in a trace storage start. Storage stop is
0h
15:10 the logical OR of trigger sources selected. Note that selecting the
RW
same trigger to start and stop trace storage results in start trace
storage only. For bit positions, see description for
MOT_TRACE_STORAGE_STOP_SOURCE field.
Enable External Trigger in 1 (ENABLE_EXTERNAL_TRIGGER_IN_1):
0h
9 • 1 to enable external trigger 1 to MOT from rdu_mid
RW
• 0 to disable external trigger 1 to MOT from rdu_mid
Enable External Trigger in 0 (ENABLE_EXTERNAL_TRIGGER_IN_0):
0h
8 • 1 to enable external trigger 0 to MOT from rdu_mid
RW
• 0 to disable external trigger 0 to MOT from rdu_mid
Trigger Out Source (TRIGGER_OUT_SOURCE): Select source of trigger sent to
rdu_mid.
• 00b: Filter 0
0h
7:6 • 01b: Filter 1
RW
• 10b: Trigger 0
• 11b: Trigger 1
Enable External Trigger Out 0 (ENABLE_EXTERNAL_TRIGGER_OUT_0):
0h
5 • 1: enable external trigger out to from MOT to rdu_mid
RW
• 0: disable external trigger out to from MOT to rdu_mid
Enable MOT Trigger 1 (ENABLE_MOT_TRIGGER_1):
0h
4 • 1: enable MOT trigger 1
RW
• 0: disable MOT trigger 1
Enable MOT Trigger 0 (ENABLE_MOT_TRIGGER_0):
0h
3 • 1: enable MOT trigger 0
RW
• 0: disable MOT trigger 0
Enable MOT Filter 1 (ENABLE_MOT_FILTER_1):
0h
2 • 1: enable MOT filter 1
RW
• 0: disable MOT filter 1
Enable MOT Filter 0 (ENABLE_MOT_FILTER_0):
0h
1 • 1: enable MOT filter 0
RW
• 0: disable MOT filter 0
Global MOT Enable (ENABLE_MOT):
0h
0 • 1: enable MOT
RW
• 0: disable MOT

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5.9.120 MOT Slice 0 Memory Pointer

(B_CR_MOT_SLICE_0_MEM_PTR_0_0_0_MCHBAR)—
Offset 6B80h
This register contains the memory address pointer used to determine where the MOT
slice 0 cache lines are stored. On a write, the B-Unit logic will set itself to the value of
the write Extraction of memory contents is performed as reads. On a read, the data
returned should match the current value of the pointer reflecting incrementing updates
from cache lines that have been stored. It also pins MOT to near or far memory.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 2h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000010

NEAR_OR_FAR_MEMORY
MOT_BUFFER_WRAP
RESERVED_0

RESERVED_1
MOT_MEMORY_POINTER

Bit Default &

Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_0): Reserved.
RO

MOT Memory Pointer (MOT_MEMORY_POINTER): The

0h
38:6 current pointer into MOT slice 0 region. Cache line granularity bits
RW/V
[38:6].

5:2
0h Reserved (RESERVED_1): Reserved.
RO

Near or Far Memory (NEAR_OR_FAR_MEMORY): Pin MOT

1h slice 0 to near1 or far0 memory. This logic is implemented in the
1
RW 2LM. Thus, this register bit is shadowed in its entirety in the 2LM.
Unused by MOT.
MOT Buffer Wrap (MOT_BUFFER_WRAP): Indication that the
0h
0 MOT slice 0 buffer has wrapped since the last clear of this write
RW/V
cleared by power good or explicit SW write.

334818 667
 MCHBAR

5.9.121 MOT Slice 1 Memory Pointer

(B_CR_MOT_SLICE_1_MEM_PTR_0_0_0_MCHBAR)—
Offset 6B88h
This register contains the memory address pointer used to determine where the MOT
slice 1 cache lines are stored. On a write, the B-Unit logic will set itself to the value of
the write. Extraction of memory contents are performed as reads. On a read, the data
returned should match the current value of the pointer, reflecting incrementing updates
from cache lines that have been stored. It also pins MOT to near or far memory.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 2h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000010

NEAR_OR_FAR_MEMORY
MOT_BUFFER_WRAP
RESERVED_0

RESERVED_1
MOT_MEMORY_POINTER

Bit Default &

Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_0): Reserved.
RO

MOT Memory Pointer (MOT_MEMORY_POINTER): The

0h
38:6 current pointer into MOT slice 1 region. Cache line granularity bits
RW/V
[38:6].

5:2
0h Reserved (RESERVED_1): Reserved.
RO

Near or Far Memory (NEAR_OR_FAR_MEMORY): Pin MOT

1h
1 slice 1 to near1 or far0 memory. This logic is implemented in the
RW
2LM. Thus, this register is shadowed in its entirety in the 2LM.
MOT Buffer Wrap (MOT_BUFFER_WRAP): Indication that the
0h
0 MOT slice 1 buffer has wrapped since the last clear of this write
RW/V
cleared by power good or explicit SW write.

668 334818
MCHBAR

5.9.122 MOT Slice 0 Record ID

(B_CR_MOT_SLICE_0_RECORD_ID_0_0_0_MCHBAR)—
Offset 6B90h
This register contains the unique MOT record ID and start trace indication for slice 0.
This state needs to be stored in a CR to allow it to persist across autoPG and s0ix
transitions.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_0

FIRST_PKT_CAPTURED

RECORD_ID

Bit Default &

Field Name (ID): Description
Range Access

31:27
0h Reserved (RESERVED_0): Reserved.
RO

0h First Packet Captured (FIRST_PKT_CAPTURED): Indicates

26
RW/V that MOT has captured the first data packet after tracing started.
0h Record ID (RECORD_ID): The current MOT unique record ID
25:0
RW/V number.

5.9.123 MOT Slice 1 Record ID

(B_CR_MOT_SLICE_1_RECORD_ID_0_0_0_MCHBAR)—
Offset 6B94h
This register contains the unique MOT record ID and start trace indication for slice 0.
This state needs to be stored in a CR to allow it to persist across autoPG and s0ix
transitions.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

334818 669
 MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FIRST_PKT_CAPTURED
RESERVED_0

RECORD_ID
Bit Default &
Field Name (ID): Description
Range Access

31:27
0h Reserved (RESERVED_0): Reserved.
RO

0h First Packet Captured (FIRST_PKT_CAPTURED): Indicates

26
RW/V that MOT has captured the first data packet after tracing started.
0h Record ID (RECORD_ID): The current MOT unique record ID
25:0
RW/V number.

5.9.124 MOT Filter Match 0

(B_CR_MOT_FILTER_MATCH0_0_0_0_MCHBAR)—Offset
6BA0h
This register contains the value of the MOT 0 access filter Match address.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
MOT_0_FILTER_MATCH_ADDRESS
RESERVED_0

RESERVED_1

670 334818
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Bit Default &

Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_0): Reserved.
RO

MOT 0 Filter Match Address

0h (MOT_0_FILTER_MATCH_ADDRESS): Access address to
38:5
RW match. Match results in trace of access. Half cache line granularity
bits 38:5 to support legacy devices.

4:0
0h Reserved (RESERVED_1): Reserved.
RO

5.9.125 MOT Filter Mask

(B_CR_MOT_FILTER_MASK0_0_0_0_MCHBAR)—Offset
6BA8h
This register contains the value of the MOT 0 access filter Mask address.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 7FFFFFFFE0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000111111111111111111111111111111111100000
MOT_0_FILTER_MASK_ADDRESS
RESERVED_0

RESERVED_1

Bit Default &

Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_0): Reserved.
RO

MOT 0 Filter Mask Address

3FFFFFFFF
h
(MOT_0_FILTER_MASK_ADDRESS): Access address bits to
38:5
RW mask. A value of 1 ignores the corresponding address bit. Half
cache line granularity bits 38:5 to support legacy devices.

4:0
0h Reserved (RESERVED_1): Reserved.
RO

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 MCHBAR

5.9.126 MOT Filter Match 1

(B_CR_MOT_FILTER_MATCH1_0_0_0_MCHBAR)—Offset
6BB0h
This register contains the value of the MOT 1 access filter Match address.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
RESERVED_0

MOT_1_FILTER_MATCH_ADDRESS

RESERVED_1
Bit Default &
Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_0): Reserved.
RO

MOT 1 Filter Match Address

0h (MOT_1_FILTER_MATCH_ADDRESS): Access address to
38:5
RW match. Match results in trace of access. Half cache line granularity
bits 38:5 to support legacy devices.

4:0
0h Reserved (RESERVED_1): Reserved.
RO

5.9.127 MOT Filter Mask 1

(B_CR_MOT_FILTER_MASK1_0_0_0_MCHBAR)—Offset
6BB8h
This register contains the value of the MOT 1 access filter Mask address.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 7FFFFFFFE0h

672 334818
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6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000111111111111111111111111111111111100000

MOT_1_FILTER_MASK_ADDRESS
RESERVED_0

RESERVED_1
Bit Default &
Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_0): Reserved.
RO

MOT 1 Filter Mask Address

3FFFFFFFF
h
(MOT_1_FILTER_MASK_ADDRESS): Access address bits to
38:5
RW mask. A value of 1 ignores the corresponding address bit. Half
cache line granularity bits 38:5 to support legacy devices.

4:0
0h Reserved (RESERVED_1): Reserved.
RO

5.9.128 MOT Filter Misc 0

(B_CR_MOT_FILTER_MISC0_0_0_0_MCHBAR)—Offset
6BC0h
This register contains the value of the MOT 0 access filter Match/Mask Agent LPID.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000

334818 673
 MCHBAR

VC_MATCH

ADDR_MATCH_POLARITY
IA_CORE_MATCH

GT_MATCH

ACCESS_TYPE_MATCH_READ_OR_WRITE
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

63:35
0h Reserved (RESERVED_0)
RO

IA Core Match (IA_CORE_MATCH): Match if transaction

0h
34:19 originated from one of up to 16 IA cores (one bit per logical
RW
processor).
GT Match (GT_MATCH):
0h
18 • 1: match
RW
• 0: ignore
0h VC Match (VC_MATCH): Match if transaction originated from
17:2
RW one of up to 16 virtual channel cores (one bit per VC).
Address Match Polarity (ADDR_MATCH_POLARITY):
0h
1 • 1: filter inversion
RW
• 0: match criteria
Access Type Match Read or Write
(ACCESS_TYPE_MATCH_READ_OR_WRITE):
0h
0 • 1: match writes
RW
• 0: match reads

5.9.129 MOT Filter Misc 1

(B_CR_MOT_FILTER_MISC1_0_0_0_MCHBAR)—Offset
6BC8h
This register contains the value of the MOT 1 access filter Match/Mask Agent LPID.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

674 334818
MCHBAR

0000000000000000000000000000000000000000000000000000000000000000

RESERVED_0

ADDR_MATCH_POLARITY
IA_CORE_MATCH

ACCESS_TYPE_MATCH_READ_OR_WRITE
GT_MATCH

VC_MATCH
Bit Default &
Field Name (ID): Description
Range Access

63:35
0h Reserved (RESERVED_0)
RO

IA Core Match (IA_CORE_MATCH): Match if transaction

0h
34:19 originated from one of up to 16 IA cores (one bit per logical
RW
processor).
GT Match (GT_MATCH):
0h
18 • 1: match
RW
• 0: ignore
0h VC Match (VC_MATCH): Match if transaction originated from
17:2
RW one of up to 16 virtual channel cores (one bit per VC).
Address Match Polarity (ADDR_MATCH_POLARITY):
0h
1 • 1: filter inversion
RW
• 0: match criteria
Access Type Match Reads or Writes
(ACCESS_TYPE_MATCH_READ_OR_WRITE):
0h
0 • 1: match writes
RW
• 0: match reads

5.9.130 MOT Trigger Match 0

(B_CR_MOT_TRIGGER_MATCH0_0_0_0_MCHBAR)—Offset
6BD0h
This register contains the value of the MOT 0 access trigger Match address.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

334818 675
 MCHBAR

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000

RESERVED_0

RESERVED_1
MOT_0_TRIGGER_MATCH_ADDRESS
Bit Default &
Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_0): Reserved.
RO

MOT 0 Trigger Match Address

0h (MOT_0_TRIGGER_MATCH_ADDRESS): Access address to
38:5
RW match. Match results in trace of access. Half cache line granularity
bits 38:5 to support legacy devices.

4:0
0h Reserved (RESERVED_1): Reserved.
RO

5.9.131 MOT Trigger Mask 0

(B_CR_MOT_TRIGGER_MASK0_0_0_0_MCHBAR)—Offset
6BD8h
This register contains the value of the MOT 0 access trigger Mask address.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 7FFFFFFFE0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000111111111111111111111111111111111100000

676 334818
MCHBAR

MOT_0_TRIGGER_MASK_ADDRESS
RESERVED_0

RESERVED_1
Bit Default &
Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_0): Reserved.
RO

MOT 0 Trigger Mask Address

3FFFFFFFF
h
(MOT_0_TRIGGER_MASK_ADDRESS): Access address bits to
38:5
RW mask. A value of 1 ignores the corresponding address bit. Half
cache line granularity bits 38:5 to support legacy devices.

4:0
0h Reserved (RESERVED_1): Reserved.
RO

5.9.132 MOT Trigger Match 1

(B_CR_MOT_TRIGGER_MATCH1_0_0_0_MCHBAR)—Offset
6BE0h
This register contains the value of the MOT 1 access trigger Match address.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
MOT_1_TRIGGER_MATCH_ADDRESS
RESERVED_0

RESERVED_1

334818 677
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_0): Reserved.
RO

MOT1 Trigger Match Address

0h (MOT_1_TRIGGER_MATCH_ADDRESS): Access address to
38:5
RW match. Match results in trace of access. Half cache line granularity
bits 38:5 to support legacy devices.

4:0
0h Reserved (RESERVED_1): Reserved.
RO

5.9.133 MOT Trigger Mask 1

(B_CR_MOT_TRIGGER_MASK1_0_0_0_MCHBAR)—Offset
6BE8h
This register contains the value of the MOT 1 access trigger Mask address.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 7FFFFFFFE0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000111111111111111111111111111111111100000
MOT_1_TRIGGER_MASK_ADDRESS
RESERVED_0

RESERVED_1

Bit Default &

Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_0): Reserved.
RO

MOT 1 Trigger Mask Address

3FFFFFFFF
h
(MOT_1_TRIGGER_MASK_ADDRESS): Access address bits to
38:5
RW mask. A value of 1 ignores the corresponding address bit. Half
cache line granularity bits 38:5 to support legacy devices.

4:0
0h Reserved (RESERVED_1): Reserved.
RO

678 334818
MCHBAR

5.9.134 MOT Trigger Misc 0

(B_CR_MOT_TRIGGER_MISC0_0_0_0_MCHBAR)—Offset
6BF0h
This register contains the value of the MOT 0 access trigger Match/Mask Agent LPID.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
RESERVED_0

ADDR_MATCH_POLARITY
GT_MATCH

VC_MATCH

ACCESS_TYPE_MATCH_READ_OR_WRITE
IA_CORE_MATCH

Bit Default &

Field Name (ID): Description
Range Access

63:35
0h Reserved (RESERVED_0)
RO

IA Core Match (IA_CORE_MATCH): Match if transaction

0h
34:19 originated from one of up to 16 IA cores (one bit per logical
RW
processor).
GT Match (GT_MATCH):
0h
18 • 1: match
RW
• 0: ignore
0h VC Match (VC_MATCH): Match if transaction originated from
17:2
RW one of up to 16 virtual channel cores (one bit per VC).
Address Match Polarity (ADDR_MATCH_POLARITY):
0h
1 • 1: filter inversion
RW
• 0: match criteria
Access Type -- Match Read or Write
(ACCESS_TYPE_MATCH_READ_OR_WRITE):
0h
0 • 1: match writes
RW
• 0: match reads

334818 679
 MCHBAR

5.9.135 MOT Trigger Misc 1

(B_CR_MOT_TRIGGER_MISC1_0_0_0_MCHBAR)—Offset
6BF8h
This register contains the value of the MOT 1 access trigger Match/Mask Agent LPID.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
RESERVED_0

ADDR_MATCH_POLARITY
GT_MATCH

VC_MATCH

ACCESS_TYPE_MATCH_READ_OR_WRITE
IA_CORE_MATCH

Bit Default &

Field Name (ID): Description
Range Access

63:35
0h Reserved (RESERVED_0)
RO

IA Core Match (IA_CORE_MATCH): Match if transaction

0h
34:19 originated from one of up to 16 IA cores (one bit per logical
RW
processor).
GT Match (GT_MATCH):
0h
18 • 1: match
RW
• 0: ignore
0h VC Match (VC_MATCH): Match if transaction originated from
17:2
RW one of up to 16 virtual channel cores (one bit per VC).
Address Match Polarity (ADDR_MATCH_POLARITY):
0h
1 • 1: filter inversion
RW
• 0: match criteria
Access Type -- Match Read or Write
(ACCESS_TYPE_MATCH_READ_OR_WRITE):
0h
0 • 1: match writes
RW
• 0: match reads

680 334818
MCHBAR

5.9.136 BIOSWR Control Policy

(B_CR_BIOSWR_CP_0_0_0_MCHBAR)—Offset 6C08h
This register specifies the control policy for the BIOSWR security policy group. It
controls write access to the Read Access Policy BIOSWR_RAC, Write Access Policy
BIOSWR_WAC configuration registers, and self-referentially to itself. The requesting
agent's 6bit encoded SAI value is used as an index into this register's bits to determine
both read access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010

MEM_RANGE_CTRL_POL

Bit Default &

Field Name (ID): Description
Range Access

Memory Range Control Policy (MEM_RANGE_CTRL_POL):

C0061010
202h
Bit vector used to determine which agents are allowed write
63:0
RW access to the BIOSWR_RAC, BIOSWR_WAC, and BIOSWR_CP
registers, based on the value from each agent's 6bit SAI field.

5.9.137 BIOSWR Read Access Policy

(B_CR_BIOSWR_RAC_0_0_0_MCHBAR)—Offset 6C10h
This register configures the Read Access Policy for the BIOSWR security policy group.
The requesting agent's 6bit encoded SAI value is used as an index into this register's
bits to determine read access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 80000C00630D0217h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

1000000000000000000011000000000001100011000011010000001000010111

334818 681
 MCHBAR

MEM_RANGE_POL
Bit Default &
Field Name (ID): Description
Range Access

80000C00 Memory Range Policy (MEM_RANGE_POL): Bit vector used to

630D0217
63:0 h
determine which agents are allowed read access, based on each
RW agent's 6bit encoded SAI value.

5.9.138 BIOSWR Write Access Policy

(B_CR_BIOSWR_WAC_0_0_0_MCHBAR)—Offset 6C18h
This register configures the Write Access Policy for the BIOSWR security policy group.
The requesting agent's 6bit encoded SAI value is used as an index into this register's
bits to determine write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C00610C0212h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000011000000001000010010
MEM_RANGE_POL

Bit Default &

Field Name (ID): Description
Range Access

C00610C0 Memory Range Policy (MEM_RANGE_POL): Bit vector used to

63:0 212h determine which agents are allowed write access, based on each
RW agent's 6bit encoded SAI value.

5.9.139 TPM Selector (B_CR_TPM_SELECTOR_0_0_0_MCHBAR)—

Offset 6C24h
Specifies where the TPM lives in the platform. B-Unit uses this register to source
decode for requests whose addresses fall within the fixed address range for the TPM.

Access Method

682 334818
MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TPM_SELECTOR
RESERVED_0
Bit Default &
Field Name (ID): Description
Range Access

31:2
0h Reserved (RESERVED_0): Reserved.
RO

TPM Selector (TPM_SELECTOR):

• 0h: fTPM enabled. Target of TPM accesses is the CSE.
0h • 1h: SPI TPM enabled. Target of TPM accesses is SPI.
1:0
RW
• 2h: LPC TPM enabled. Target of TPM accesses is LPC.
• 3h: All TPMs disabled. Target of TPM accesses is the PSF Error
Handler.

5.9.140 B-Unit Pcode/Ucode Write, All Read Control Policy

Register
(B_CR_P_U_CODEWR_ALLRD_CP_0_0_0_MCHBAR)—
Offset 6C28h
This register controls the access policy to the Read Access Policy
P_U_CODEWR_ALLRD_RAC and Write Access Policy P_U_CODEWR_ALLRD_WAC
configuration registers, and self-referentially to itself. The requesting agent's 6bit
encoded SAI value is used as an index into this register's bits to determine both read
access and write access.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 40001000202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000001000000000000000001000000000000001000000010

334818 683
 MCHBAR

IA_CTRL_POL
Bit Default &
Field Name (ID): Description
Range Access

B-Unit Pcode/Ucode Write, All Read Control Policy

40001000 (IA_CTRL_POL): Bit vector used to determine which agents are
63:0 202h allowed access to the P_U_CODEWR_ALLRD_RAC,
RW P_U_CODEWR_ALLRD_WAC, and P_U_CODEWR_ALLRD_CP
registers, based on the value from the agent's 6bit SAI field.

5.9.141 B-Unit Pcode/Ucode Read Access Policy

(B_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCHBAR)—
Offset 6C30h
This register configures the Read Access Policy for the B-Unit Pcode/Ucode Write, All
Read registers.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: FFFFFFFFFFFFFFFFh

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

1111111111111111111111111111111111111111111111111111111111111111
IA_SAI_POL

Bit Default &

Field Name (ID): Description
Range Access

B-Unit Pcode/Ucode Write, All Read SAI Read Access Policy

FFFFFFFFF
FFFFFFFh
(IA_SAI_POL): Bit vector used to determine which agents are
63:0
RO allowed read access to the B-Unit Pcode/Ucode Write, All Read
policy registers, based on each agent's 6bit encoded SAI value.

5.9.142 B-Unit Pcode/Ucode Write Access Policy

(B_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_MCHBAR)—
Offset 6C38h
This register configures the Write Access Policy for the B-Unit Pcode/Ucode Write, All
Read policy registers. The requesting agent's 6bit encoded SAI value is used as an
index into this register's bits to determine write access.

684 334818
MCHBAR

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 40001000202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000001000000000000000001000000000000001000000010

IA_SAI_POL
Bit Default &
Field Name (ID): Description
Range Access

B-Unit Pcode/Ucode Write, All Read SAI Write Access

40001000 Policy (IA_SAI_POL): Bit vector used to determine which
63:0 202h agents are allowed write access to the B-Unit IA Core
RW Configuration registers, based on each agent's 6bit encoded SAI
value.

5.9.143 Default VTd BAR (B_CR_DEFVTDBAR_0_0_0_MCHBAR)—

Offset 6C80h
BIOS must write DEFVTDBAR and then immediately follow it up with a read to
DEFVTDBAR to ensure that all copies of DEFVTDBAR in the system are updated.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
DEFVTDBAREN
DEFVTDBAR_40_BIT

DEFVTDBAR
RESERVED_0

RESERVED_1

LOCK

Bit Default &

Field Name (ID): Description
Range Access

63:40
0h Reserved (RESERVED_0): Reserved.
RO

334818 685
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

39
0h DEFVTDBAR 40 Bit (DEFVTDBAR_40_BIT): Reserved.
RO

Default IOMMU VTd Config Space Base (DEFVTDBAR): If

DEFVTDBAR is enabled, this field corresponds to bits 38:12 of the
base address default IOMMU VTd configuration space. BIOS will
program this register resulting in a base address for a 4KB block
of contiguous memory address space. This register ensures that a
0h
38:12 naturally aligned 4KB space is allocated within the first 512GB of
RW
addressable memory space. System Software uses this base
address to program the default VTd IOMMU register set. If
DEFVTDBAR is enabled and incoming Request Address[38:12]
matches DEFVTDBAR[38:12] the request targets the Default VTd
BAR.

11:2
0h Reserved (RESERVED_1): Reserved.
RO

Lock Register Content (LOCK): Locks the contents of the

0h register including itself. Unused by the B-Unit, and does not
1
RW implement the intended lock functionality. B-Unit includes this bit
to support shadow copies of the register that rely on this lock bit.
DEFVTDBAR Enable (DEFVTDBAREN):
• 0: DEFVTDBAR is disabled and does not claim any memory
0h
0
RW/L • 1: DEFVTDBAR memory mapped accesses are claimed and
decoded appropriately. This bit will remain 0 if VTd capability
is disabled.

5.9.144 Gfx VTd BAR (B_CR_GFXVTDBAR_0_0_0_MCHBAR)—

Offset 6C88h
BIOS must write GFXVTDBAR and then immediately follow it up with read of
DEVEN_0_0_0_PCI, then write (with value from read operation) to DEVEN_0_0_0_PCI
to ensure that all copies of GFXVTDBAR in the system are updated.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
GFXVTBAREN
RESERVED_0

GFXVTBAR

RESERVED_1

LOCK

686 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_0): Reserved.
RO

GFXVT Base Address (GFXVTBAR): This field corresponds to

bits 38 to 12 of the base address GFXVT configuration space. BIOS
will program this register, resulting in a base address for a 4KB
block of contiguous memory address space. This register ensures
0h
38:12 that a naturally aligned 4KB space is allocated within the first
RW
512GB of addressable memory space. System Software uses this
base address to program the GFXVT register set. If GFXVTBAR is
enabled and incoming Request Address[38:12] matches
GFXVTBAR[38:12] the request targets the Gfx VTd BAR.

11:2
0h Reserved (RESERVED_1): Reserved.
RO

Lock Register Content (LOCK): Locks the contents of the

0h register, including itself. Unused by the B-Unit, and does not
1
RW implement the intended lock functionality. B-Unit includes this bit
to support shadow copies of the register that rely on this lock bit.
GFXVTBAR Enable (GFXVTBAREN):
• 0: GFXVTBAR is disabled and does not claim any memory
0h
0
RW/L • 1: GFXVTBAR memory mapped accesses are claimed and
decoded appropriately. This bit will remain 0 if VTd capability
is disabled.

5.9.145 B-Unit Lites Group 0 Control

(B_CR_LITES0_CTL_0_0_0_MCHBAR)—Offset 6C90h
This register controls the functionality of the B-Unit Lites Group 0 mask/match
functionality.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INVERT_ADDR_MATCH
IDI_LENGTH_MATCH

ENABLE_DATA_MATCH
PII_LENGTH_MATCH

SLICE_MATCH

ALTU2CREQVIEW
RESERVED_0

DWORD_SELECT

ENABLE_GROUP

334818 687
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IDI Length Match (IDI_LENGTH_MATCH): Enables length matching for IDI

requests for Lites Group 0. Each bit, when set to 1, enables match for that length for
an IDI request. Lites logic supports only lengths 0-16B for PRd and PortIn and only
64B for all other opcodes.
• Bit 31:64B
• Bit 30:16B
• Bit 29:15B
• Bit 28:14B
• Bit 27:13B
• Bit 26:12B
• Bit 25:11B

31:14
0h • Bit 24:10B
RW
• Bit 23:9B
• Bit 22:8B
• Bit 21:7B
• Bit 20:6B
• Bit 19:5B
• Bit 18:4B
• Bit 17:3B
• Bit 16:2B
• Bit 15:1B
• Bit 14:0B
PII Length Match (PII_LENGTH_MATCH): Enables length matching for PII
requests for Lites Group 0. Each bit, when set to 1, enables length match for the PII
0h request.
13:12
RW • Bit 13:64B
• Bit 12:32B

11:10
0h Reserved (RESERVED_0): Reserved.
RO

Slice Match (SLICE_MATCH):

• 00: All mask/match hits are suppressed
0h
9:8 • 01: Mask/Match hits enabled only for Slice0
RW
• 10: Mask/match hits enabled only for Slice1
• 11: Mask/Match hits enabled for both Slices
DWord Select (DWORD_SELECT): Selects the dword within the
0h
7:4 512bit data field that is compared for data mask/matches for Lites
RW
Group 0.
0h Enable Data Match (ENABLE_DATA_MATCH): When set, this
3
RW field enables data matching on Lites Group 0.

688 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Alternate U2C Request View (ALTU2CREQVIEW): When set,

address match/mask, opcode match and agent match registers
0h
2 are used to generate matches for the U2C request observation
RW
point. When clear, Badmit observation point matches are reported
on the U2C request observation point.
Invert Address Match (INVERT_ADDR_MATCH): When set,
0h
1 inverts the polarity of the address match/mask logic, i.e., reports
RW
a match for addresses that are not in the specified range.
Enable Group (ENABLE_GROUP): Enables all match filters for
Lites Group 0. The following are the observation points that
contain match filters: Badmit logic within each slice after a
transaction is successfully admitted into the B-Unit, U2C request
0h launch, PMI datain for each PMI channel for read data, PMI
0
RW dataout for each PMI channel for writes, data write from
requesters to BRAM in each slice, and read data return on the live
bypass and nonlive bypass paths in each slice. To report a match
at an observation point, all match criteria for that point must be
satisfied.

5.9.146 B-Unit Lites Group 0 Opcode Match Filter

(B_CR_LITES0_OPCODE_MATCH_0_0_0_MCHBAR)—
Offset 6C94h
This register contains the IDI and PII opcodes that will enable a Lites Group0 opcode
match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OPCODE_MATCH

334818 689
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Opcode Match (OPCODE_MATCH): Bit vector that enables a match on the opcode
for C2U IDI requests, PII A2B requests, and U2C IDI requests. All three observation
points, Badmit in both slices and the U2C request interface, use this same opcode
match register. Each bit, when set, enables a match on the corresponding opcode,
and, when clear, will suppress a match on the corresponding opcode. To match on
any opcode, set all bits to 1.
• Bit 31: C2U_Req_CRd
• Bit 30: C2U_Req_DRd
• Bit 29: C2U_Req_DRdPTE
• Bit 28: C2U_Req_SetMonitor
• Bit 27: C2U_Req_RFO,U2C_Req_LTWrite_piclet
• Bit 26: C2U_Req_PRd,U2C_Req_VLW_piclet
• Bit 25: C2U_Req_UcRdF
• Bit 24: C2U_Req_PortIn,U2C_Req_SnpCode
• Bit 23: C2U_Req_IntA,U2C_Req_SnpData
• Bit 22: C2U_Req_Lock
• Bit 21: C2U_Req_SplitLock,U2C_Req_IntLog_piclet
• Bit 20: C2U_Req_Unlock,U2C_Req_IntPhy_piclet
• Bit 19: C2U_Req_ItoM
• Bit 18: C2U_Req_SpCyc,U2C_Req_SnpInv
0h
31:0
RW • Bit 17: C2U_Req_RdMonitor,U2C_Req_StopReq
• Bit 16: C2U_Req_ClrMonitor,U2C_Req_StartReq
• Bit 15: C2U_Req_CLFlush
• Bit 14: C2U_Req_WbMtoI,U2C_Req_IntLog_MSI
• Bit 13: C2U_Req_WbMtoE,U2C_Req_IntPhy_MSI
• Bit 12: C2U_Req_WiL
• Bit 11: C2U_Req_WCiL
• Bit 10: C2U_Req_WCilF
• Bit 9: C2U_Req_PortOut
• Bit 8: C2U_Req_IntPriUp,U2C_Req_LTWrite
• Bit 7: C2U_Req_IntLog
• Bit 6: C2U_Req_IntPhy
• Bit 5: C2U_Req_EOI,U2C_Req_VLW
• Bit 4: C2U_Req_ItoMWr
• Bit 3: A2B_Req_SnoopedRead
• Bit 2: A2B_Req_UnSnoopedRead,U2C_Req_IntPhy_IPI
• Bit 1: A2B_Req_SnoopedWrite
• Bit 0: A2B_Req_UnSnoopedWrite,U2C_Req_IntLog_IPI

690 334818
MCHBAR

5.9.147 B-Unit Lites Group 0 Agent Match Filter

(B_CR_LITES0_AGENT_MATCH_0_0_0_MCHBAR)—Offset
6C98h
This register designates which agents are enabled to trigger a Lites Group0 AgentID
match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VC_MATCH
GT_MATCH

CPU_CORE_MATCH
Bit Default &
Field Name (ID): Description
Range Access

GT Match (GT_MATCH): This field is used to match IDI

0h transactions from GT for Lites Group0. When set, enables a match
31
RW for a transaction originating from GT. When clear, suppresses a
match for a transaction from GT.

334818 691
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Bit Default &

Field Name (ID): Description
Range Access

VC Match (VC_MATCH): This field is used to match VC Channel ID for PII

transactions for Lites Group0. Each bit, when set, enables a match for a transaction
originating from that VC. When clear, suppresses a match for a transaction from that
VC.
• Bit 30: VC14
• Bit 29: VC13
• Bit 28: VC12
• Bit 27: VC11
• Bit 26: VC10
• Bit 25: VC9
0h
30:16 • Bit 24: VC8
RW
• Bit 23: VC7
• Bit 22: VC6
• Bit 21: VC5
• Bit 20: VC4
• Bit 19: VC3
• Bit 18: VC2
• Bit 17: VC1
• Bit 16: VC0
CPU Core Match (CPU_CORE_MATCH): This field is used to match Logical
Processor Core ID for CPU IDI transactions for Lites Group 0. Each bit, when set,
enables a match for a transaction originating from that core. When clear, suppresses
a match for a transaction from that core.
• Bit 15: CPU7 Core1
• Bit 14: CPU7 Core0
• Bit 13: CPU6 Core1
• Bit 12: CPU6 Core0
• Bit 11: CPU5 Core1
• Bit 10: CPU5 Core0

15:0
0h • Bit 9: CPU4 Core1
RW
• Bit 8: CPU4 Core0
• Bit 7: CPU3 Core1
• Bit 6: CPU3 Core0
• Bit 5: CPU2 Core1
• Bit 4: CPU2 Core0
• Bit 3: CPU1 Core1
• Bit 2: CPU1 Core0
• Bit 1: CPU0 Core1
• Bit 0: CPU0 Core0

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5.9.148 B-Unit Lites Group 0 U2C IntData Match Filter

(B_CR_LITES0_U2CINTDATA_MATCH_0_0_0_MCHBAR)—
Offset 6C9Ch
When U2C alternate view is enabled, this register specifies match criteria for U2C
IntData.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INTDATA_MASK

INTDATA_MATCH
Bit Default &
Field Name (ID): Description
Range Access

Mask for U2C Request IntData[15:0] (INTDATA_MASK):

This mask is for generating Lites Group 0 U2C request alternative
view match. Only bits [7:0] of this field are used; bits [15:8] are
0h ignored. If a mask bit in this register is 0, then the corresponding
31:16
RW bit in the INTDATA_MATCH field is ignored. If the mask bit is 1,
then the corresponding bit in the INTDATA_MATCH[7:0] field must
match its corresponding u2c request IntData[15:8] bit for a
match.
IntData Match (INTDATA_MATCH): U2C Request
IntData[15:8] value is compared with bits [7:0] of this field to
0h
15:0 generate a match for the U2C request address match. Bits [15:8]
RW
of this field are ignored. Note that matching based on the
IntData[7:0] bits is not supported.

5.9.149 B-Unit Lites Group 0 Address Match Filter

LITES0_ADDR_MATCH
(B_CR_LITES0_ADDR_MATCH_0_0_0_MCHBAR)—Offset
6CA0h
This register, together with the LITES0_ADDR_MASK register, specifies the request
address values that trigger a Lites Group 0 address match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

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 MCHBAR

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000

RESERVED_1

ADDRESS_MATCH

RESERVED_0
Bit Default &
Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_1): Reserved.
RO

0h Address Match (ADDRESS_MATCH): Address value to match

38:3
RW for Lites.

2:0
0h Reserved (RESERVED_0): Reserved.
RO

5.9.150 B-Unit Lites Group 0 Address Mask Filter

LITES0_ADDR_MASK
(B_CR_LITES0_ADDR_MASK_0_0_0_MCHBAR)—Offset
6CA8h
This register, together with the LITES0_ADDR_MATCH register, specifies the request
address values that trigger a Lites Group 0 address match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
ADDRESS_MASK
RESERVED_1

RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_1): Reserved.
RO

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Bit Default &

Field Name (ID): Description
Range Access

Address Mask (ADDRESS_MASK): Address mask value used

for comparing request address during filter operation for Lites. If
0h the mask bit in this register is 0, then the corresponding bit in the
38:3
RW ADDR_MATCH register is ignored. If the mask bit is 1, then the
corresponding bit in the ADDR_MATCH register must match the
corresponding request address bit for a match.

2:0
0h Reserved (RESERVED_0): Reserved.
RO

5.9.151 B-Unit Lites Group 0 Data Match Filter

LITES0_DATA_MATCH
(B_CR_LITES0_DATA_MATCH_0_0_0_MCHBAR)—Offset
6CB0h
This register, together with LITES0_DATA_MASK, specifies the data values that will
trigger a Lites Group 0 data filter match. All data observation points -- PMI data in, PMI
data out, read data to agent (both live and nonlive) and write data from agent -- use
the same Group 0 data match/mask registers for generating a match. Data match/
mask can be enabled for only one DW of the transaction data. The specific DW can be
selected via DWORD_SELECT.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA_MATCH

Bit Default &

Field Name (ID): Description
Range Access

31:0
0h Data Match (DATA_MATCH): Data value to match for Lites.
RW

5.9.152 B-Unit Lites Group 0 Data Mask Filter LITES0_DATA_MASK

(B_CR_LITES0_DATA_MASK_0_0_0_MCHBAR)—Offset
6CB4h
This register, together with LITES0_DATA_MATCH, specifies the data values that will
trigger a Lites Group 0 data filter match for Lites. All data observation points -- PMI
data in, PMI data out, read data to agent (both live and nonlive) and write data from

334818 695
 MCHBAR

agent -- use the same Group 0 data match/mask registers for generating a Group 0
data filter match. Data match/mask can be enabled for only one DW of the transaction
data. The specific DW can be selected via DWORD_SELECT.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA_MASK
Bit Default &
Field Name (ID): Description
Range Access

Data Mask (DATA_MASK): Data mask value used for comparing

data during filter operations for Lites. If the mask bit in this
0h register is 0, then the corresponding bit in the DATA_MATCH
31:0
RW register is ignored. If the mask bit is 1, then the corresponding bit
in the DATA_MATCH register must match the corresponding bit of
the request data for a match.

5.9.153 B-Unit Lites Group 1 Control

(B_CR_LITES1_CTL_0_0_0_MCHBAR)—Offset 6CC0h
This register controls the B-Unit Lites Group 1 mask/match functionality.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INVERT_ADDR_MATCH
IDI_LENGTH_MATCH

ENABLE_DATA_MATCH
PII_LENGTH_MATCH

SLICE_MATCH

ALTU2CREQVIEW
RESERVED_0

DWORD_SELECT

ENABLE_GROUP

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Bit Default &

Field Name (ID): Description
Range Access

IDI Length Match (IDI_LENGTH_MATCH): Enables length matching for IDI

requests for Lites Group 1. Each bit, when set to 1, enables match for that length for
an IDI request. Lites logic supports only lengths 0-16B for PRd and PortIn and only
64B for all other opcodes.
• Bit 31:64B
• Bit 30:16B
• Bit 29:15B
• Bit 28:14B
• Bit 27:13B
• Bit 26:12B
• Bit 25:11B

31:14
0h • Bit 24:10B
RW
• Bit 23:9B
• Bit 22:8B
• Bit 21:7B
• Bit 20:6B
• Bit 19:5B
• Bit 18:4B
• Bit 17:3B
• Bit 16:2B
• Bit 15:1B
• Bit 14:0B
PII Length Match (PII_LENGTH_MATCH): Enables length matching for PII
requests for Lites Group 1. Each bit, when set to 1, enables length match for the PII
0h request.
13:12
RW • Bit 13:64B
• Bit 12:32B

11:10
0h Reserved (RESERVED_0): Reserved.
RO

Slice Match (SLICE_MATCH):

• 00: All mask/match hits are suppressed
0h
9:8 • 01: mask/match hits enabled only for Slice0
RW
• 10: mask/match hits enabled only for Slice1
• 11: mask/match hits enabled for both Slices
DWord Select (DWORD_SELECT): Selects the dword within the
0h
7:4 512bit data field that is compared for data mask/matches for Lites
RW
Group 1.
0h Enable Data Match (ENABLE_DATA_MATCH): When set, this
3
RW field enables data matching on Lites Group 1.

334818 697
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Alternate U2C Request View (ALTU2CREQVIEW): When set,

address match/mask opcode match and agent match registers are
0h
2 used to generate matches for the U2C request observation point.
RW
When clear, Badmit observation point matches are reported on the
U2C request observation point.
Invert Address Match (INVERT_ADDR_MATCH): When set,
0h
1 inverts the polarity of the address match/mask logic, i.e., reports
RW
a match for addresses that are not in the specified range.
Enable Group (ENABLE_GROUP): Enables all match filters for
Lites Group 1. The following are the observation points that
contain match filters: Badmit logic within each slice after a
transaction is successfully admitted into the B-Unit, U2C request
0h launch, PMI datain for each PMI channel for read data, PMI
0
RW dataout for each PMI channel for writes, data write from
requesters to BRAM in each slice, and read data return on the live
bypass and nonlive bypass paths in each slice. To report a match
at an observation point, all match criteria for that point must be
satisfied.

5.9.154 B-Unit Lites Group 1 Opcode Match Filter

(B_CR_LITES1_OPCODE_MATCH_0_0_0_MCHBAR)—
Offset 6CC4h
This register contains the IDI and PII opcodes that will enable a Lites Group1 opcode
match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OPCODE_MATCH

698 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Opcode Match (OPCODE_MATCH): Bit vector that enables a match on the opcode
for C2U IDI requests, PII A2B requests, and U2C IDI requests. All three observation
points -- Badmit in both slices, and the U2C request interface -- use this same
opcode match register. Each bit, when set, enables a match on the corresponding
opcode, and when clear will suppress a match on the corresponding opcode. To
match on any opcode, set all bits to 1.
• Bit 31: C2U_Req_CRd
• Bit 30: C2U_Req_DRd
• Bit 29: C2U_Req_DRdPTE
• Bit 28: C2U_Req_SetMonitor
• Bit 27: C2U_Req_RFO,U2C_Req_LTWrite_piclet
• Bit 26: C2U_Req_PRd,U2C_Req_VLW_piclet
• Bit 25: C2U_Req_UcRdF
• Bit 24: C2U_Req_PortIn,U2C_Req_SnpCode
• Bit 23: C2U_Req_IntA,U2C_Req_SnpData
• Bit 22: C2U_Req_Lock
• Bit 21: C2U_Req_SplitLock,U2C_Req_IntLog_piclet
• Bit 20: C2U_Req_Unlock,U2C_Req_IntPhy_piclet
• Bit 19: C2U_Req_ItoM
• Bit 18: C2U_Req_SpCyc,U2C_Req_SnpInv
0h
31:0
RW • Bit 17: C2U_Req_RdMonitor,U2C_Req_StopReq
• Bit 16: C2U_Req_ClrMonitor,U2C_Req_StartReq
• Bit 15: C2U_Req_CLFlush
• Bit 14: C2U_Req_WbMtoI,U2C_Req_IntLog_MSI
• Bit 13: C2U_Req_WbMtoE,U2C_Req_IntPhy_MSI
• Bit 12: C2U_Req_WiL
• Bit 11: C2U_Req_WCiL
• Bit 10: C2U_Req_WCilF
• Bit 9: C2U_Req_PortOut
• Bit 8: C2U_Req_IntPriUp,U2C_Req_LTWrite
• Bit 7: C2U_Req_IntLog
• Bit 6: C2U_Req_IntPhy
• Bit 5: C2U_Req_EOI,U2C_Req_VLW
• Bit 4: C2U_Req_ItoMWr
• Bit 3: A2B_Req_SnoopedRead
• Bit 2: A2B_Req_UnSnoopedRead,U2C_Req_IntPhy_IPI
• Bit 1: A2B_Req_SnoopedWrite
• Bit 0: A2B_Req_UnSnoopedWrite,U2C_Req_IntLog_IPI

334818 699
 MCHBAR

5.9.155 B-Unit Lites Group 1 Agent Match Filter

(B_CR_LITES1_AGENT_MATCH_0_0_0_MCHBAR)—Offset
6CC8h
This register designates which agents are enabled to trigger a Lites Group1 AgentID
match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VC_MATCH
GT_MATCH

CPU_CORE_MATCH
Bit Default &
Field Name (ID): Description
Range Access

GT Match (GT_MATCH): This field is used to match IDI

0h transactions from GT for Lites Group1. When set, enables a match
31
RW for a transaction originating from GT. When clear, suppresses a
match for a transaction from GT.

700 334818
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Bit Default &

Field Name (ID): Description
Range Access

VC Match (VC_MATCH): This field is used to match VC Channel ID for PII

transactions for Lites Group1. Each bit, when set, enables a match for a transaction
originating from that VC. When clear, each bit suppresses a match for a transaction
from that VC.
• Bit 30: VC14
• Bit 29: VC13
• Bit 28: VC12
• Bit 27: VC11
• Bit 26: VC10
• Bit 25: VC9
0h
30:16 • Bit 24: VC8
RW
• Bit 23: VC7
• Bit 22: VC6
• Bit 21: VC5
• Bit 20: VC4
• Bit 19: VC3
• Bit 18: VC2
• Bit 17: VC1
• Bit 16: VC0
CPU Core Match (CPU_CORE_MATCH): This field is used to match Logical
Processor Core ID for CPU IDI transactions, for Lites Group 1. Each bit, when set,
enables a match for a transaction originating from that core. When clear, each bit
suppresses a match for a transaction from that core.
• Bit 15: CPU7 Core1
• Bit 14: CPU7 Core0
• Bit 13: CPU6 Core1
• Bit 12: CPU6 Core0
• Bit 11: CPU5 Core1
• Bit 10: CPU5 Core0

15:0
0h • Bit 9: CPU4 Core1
RW
• Bit 8: CPU4 Core0
• Bit 7: CPU3 Core1
• Bit 6: CPU3 Core0
• Bit 5: CPU2 Core1
• Bit 4: CPU2 Core0
• Bit 3: CPU1 Core1
• Bit 2: CPU1 Core0
• Bit 1: CPU0 Core1
• Bit 0: CPU0 Core0

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 MCHBAR

5.9.156 B-Unit Lites Group 1 U2C IntData Match Filter

(B_CR_LITES1_U2CINTDATA_MATCH_0_0_0_MCHBAR)—
Offset 6CCCh
When U2C alternate view is enabled, this register specifies match criteria for U2C
IntData.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INTDATA_MASK

INTDATA_MATCH
Bit Default &
Field Name (ID): Description
Range Access

IntData Mask (INTDATA_MASK): This mask is for generating

Lites Group 1 U2C request alternative view match. Only bits [7:0]
of this field are used; bits [15:8] are ignored. If a mask bit in this
0h
31:16 register is 0, then the corresponding bit in the INTDATA_MATCH
RW
field is ignored. If the mask bit is 1, then the corresponding bit in
the INTDATA_MATCH[7:0] field must match its corresponding u2c
request IntData[15:8] bit for a match.
IntData Match (INTDATA_MATCH): U2C Request
IntData[15:8] value is compared with bits [7:0] of this field to
0h
15:0 generate a match for the U2C request address match. Bits [15:8]
RW
of this field are ignored. Note that matching based on the
IntData[7:0] bits is not supported.

5.9.157 B-Unit Lites Group 1 Address Match Filter

LITES1_ADDR_MATCH
(B_CR_LITES1_ADDR_MATCH_0_0_0_MCHBAR)—Offset
6CD0h
This register, together with the LITES1_ADDR_MASK register, specifies the request
address values that trigger a Lites Group 1 address match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

702 334818
MCHBAR

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000

RESERVED_1

ADDRESS_MATCH

RESERVED_0
Bit Default &
Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_1): Reserved.
RO

0h Address Match (ADDRESS_MATCH): Address value to match

38:3
RW for Lites

2:0
0h Reserved (RESERVED_0): Reserved.
RO

5.9.158 B-Unit Lites Group 1 Address Mask Filter

LITES1_ADDR_MASK
(B_CR_LITES1_ADDR_MASK_0_0_0_MCHBAR)—Offset
6CD8h
This register, together with the LITES1_ADDR_MATCH register, specifies the request
address values that trigger a Lites Group 1 address match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
ADDRESS_MASK
RESERVED_1

RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_1): Reserved.
RO

334818 703
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Address Mask (ADDRESS_MASK): Address mask value used

for comparing request address during filter operation for Lites. If
0h the mask bit in this register is 0, then the corresponding bit in the
38:3
RW ADDR_MATCH register is ignored. If the mask bit is 1, then the
corresponding bit in the ADDR_MATCH register must match the
corresponding request address bit for a match.

2:0
0h Reserved (RESERVED_0): Reserved.
RO

5.9.159 B-Unit Lites Group 1 Data Match Filter

LITES1_DATA_MATCH
(B_CR_LITES1_DATA_MATCH_0_0_0_MCHBAR)—Offset
6CE0h
This register, together with LITES1_DATA_MASK, specifies the data values that will
trigger a Lites Group 1 data filter match. All data observation points -- PMI data in, PMI
data out, read data to agent (both live and nonlive) and write data from agent -- use
the same Group 1 data match/mask registers for generating a match. Data match/
mask can be enabled for only one DW of the transaction data. The specific DW can be
selected via DWORD_SELECT.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA_MATCH

Bit Default &

Field Name (ID): Description
Range Access

31:0
0h Data Match (DATA_MATCH): Data value to match for Lites.
RW

5.9.160 B-Unit Lites Group 1 Data Mask Filter LITES1_DATA_MASK

(B_CR_LITES1_DATA_MASK_0_0_0_MCHBAR)—Offset
6CE4h
This register, together with LITES1_DATA_MATCH, specifies the data values that will
trigger a Lites Group 1 data filter match for Lites. All data observation points -- PMI
data in, PMI data out, read data to agent (both live and nonlive) and write data from

704 334818
MCHBAR

agent -- use the same Group 1 data match/mask registers for generating a Group 1
data filter match. Data match/mask can be enabled for only one DW of the transaction
data. The specific DW can be selected via DWORD_SELECT.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA_MASK
Bit Default &
Field Name (ID): Description
Range Access

Data Mask (DATA_MASK): Data mask value used for comparing

data during filter operations for Lites. If the mask bit in this
0h register is 0, then the corresponding bit in the DATA_MATCH
31:0
RW register is ignored. If the mask bit is 1, then the corresponding bit
in the DATA_MATCH register must match the corresponding bit of
the request data for a match.

5.9.161 B-Unit Lites Group 2 Control

(B_CR_LITES2_CTL_0_0_0_MCHBAR)—Offset 6CF0h
This register controls the functionality of the B-Unit Lites Group 2 mask/match
functionality.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENABLE_GROUP
DWORD_SELECT

ALTU2CREQVIEW
IDI_LENGTH_MATCH

RESERVED_0
PII_LENGTH_MATCH

ENABLE_DATA_MATCH

INVERT_ADDR_MATCH
SLICE_MATCH

334818 705
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IDI Length Match (IDI_LENGTH_MATCH): Enables length matching for IDI

requests for Lites Group 2. Each bit, when set to 1, enables match for that length for
an IDI request. Lites logic supports only lengths 0-16B for PRd and PortIn and only
64B for all other opcodes.
• Bit 31:64B
• Bit 30:16B
• Bit 29:15B
• Bit 28:14B
• Bit 27:13B
• Bit 26:12B
• Bit 25:11B

31:14
0h • Bit 24:10B
RW
• Bit 23:9B
• Bit 22:8B
• Bit 21:7B
• Bit 20:6B
• Bit 19:5B
• Bit 18:4B
• Bit 17:3B
• Bit 16:2B
• Bit 15:1B
• Bit 14:0B
PII Length Match (PII_LENGTH_MATCH): Enables length matching for PII
requests for Lites Group 2. Each bit, when set to 1, enables length match for the PII
0h request.
13:12
RW • Bit 13:64B
• Bit 12:32B

11:10
0h Reserved (RESERVED_0): Reserved.
RO

Slice Match (SLICE_MATCH):

• 00: All mask/match hits are suppressed
0h
9:8 • 01: Mask/Match hits enabled only for Slice0
RW
• 10: Mask/match hits enabled only for Slice1
• 11: Mask/Match hits enabled for both Slices
Dword Select (DWORD_SELECT): Selects the dword within the
0h
7:4 512bit data field that is compared for data mask/matches for Lites
RW
Group 2.
0h Enable Data Match (ENABLE_DATA_MATCH): When set, this
3
RW field enables data matching on Lites Group 2.

706 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Altername UC2 Request View (ALTU2CREQVIEW): When set,

address match/mask opcode match and agent match registers are
0h
2 used to generate matches for the U2C request observation point.
RW
When clear, Badmit observation point matches are reported on the
U2C request observation point.
Invert Address Match (INVERT_ADDR_MATCH): When set,
0h
1 inverts the polarity of the address match/mask logic, i.e., reports
RW
a match for addresses that are not in the specified range.
Enable Group (ENABLE_GROUP): Enables all match filters for
Lites Group 2. The following are the observation points that
contain match filters: Badmit logic within each slice after a
transaction is successfully admitted into the B-Unit, U2C request
0h
0 launch PMI datain for each PMI channel read data, PMI dataout for
RW
each PMI channel write data, agent data write to BRAM in each
slice, read data return on the live bypass and nonlive bypass paths
in each slice. To report a match at an observation point all match
criteria for that point must be satisfied.

5.9.162 B-Unit Lites Group 2 Opcode Match Filter

(B_CR_LITES2_OPCODE_MATCH_0_0_0_MCHBAR)—
Offset 6CF4h
This register contains the IDI and PII opcodes that will enable a Lites Group2 opcode
match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OPCODE_MATCH

334818 707
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Opcode Match (OPCODE_MATCH): Bit vector that enables a match on the opcode
for C2U IDI requests, PII A2B requests, and U2C IDI requests. All three observation
points -- Badmit in both slices, and the U2C request interface -- use this same
opcode match register. Each bit, when set, enables a match on the corresponding
opcode and when clear will suppress a match on the corresponding opcode. To match
on any opcode, set all bits to 1.
• Bit 31: C2U_Req_CRd
• Bit 30: C2U_Req_DRd
• Bit 29: C2U_Req_DRdPTE
• Bit 28: C2U_Req_SetMonitor
• Bit 27: C2U_Req_RFO,U2C_Req_LTWrite_piclet
• Bit 26: C2U_Req_PRd,U2C_Req_VLW_piclet
• Bit 25: C2U_Req_UcRdF
• Bit 24: C2U_Req_PortIn,U2C_Req_SnpCode
• Bit 23: C2U_Req_IntA,U2C_Req_SnpData
• Bit 22: C2U_Req_Lock
• Bit 21: C2U_Req_SplitLock,U2C_Req_IntLog_piclet
• Bit 20: C2U_Req_Unlock,U2C_Req_IntPhy_piclet
• Bit 19: C2U_Req_ItoM
• Bit 18: C2U_Req_SpCyc,U2C_Req_SnpInv

31:0
0h • Bit 17: C2U_Req_RdMonitor,U2C_Req_StopReq
RW
• Bit 16: C2U_Req_ClrMonitor,U2C_Req_StartReq
• Bit 15: C2U_Req_CLFlush
• Bit 14: C2U_Req_WbMtoI,U2C_Req_IntLog_MSI
• Bit 13: C2U_Req_WbMtoE,U2C_Req_IntPhy_MSI
• Bit 12: C2U_Req_WiL
• Bit 11: C2U_Req_WCiL
• Bit 10: C2U_Req_WCilF
• Bit 9: C2U_Req_PortOut
• Bit 8: C2U_Req_IntPriUp,U2C_Req_LTWrite
• Bit 7: C2U_Req_IntLog
• Bit 6: C2U_Req_IntPhy
• Bit 5: C2U_Req_EOI,U2C_Req_VLW
• Bit 4: C2U_Req_ItoMWr
• Bit 3: A2B_Req_SnoopedRead
• Bit 2: A2B_Req_UnSnoopedRead,U2C_Req_IntPhy_IPI
• Bit 1: A2B_Req_SnoopedWrite
• Bit 0: A2B_Req_UnSnoopedWrite,U2C_Req_IntLog_IPI
•

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5.9.163 B-Unit Lites Group 2 Agent Match Filter

(B_CR_LITES2_AGENT_MATCH_0_0_0_MCHBAR)—Offset
6CF8h
This register designates which agents are enabled to trigger a Lites Group2 AgentID
match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VC_MATCH
GT_MATCH

CPU_CORE_MATCH
Bit Default &
Field Name (ID): Description
Range Access

GT Match (GT_MATCH): This field is used to match IDI

0h ransactions from GT for Lites Group2. When set, enables a match
31
RW for a transaction originating from GT. When clear, suppresses a
match for a transaction from GT.

334818 709
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

VC Match (VC_MATCH): This field is used to match VC Channel ID, for PII
transactions for Lites Group2. Each bit, when set, enables a match for a transaction
originating from that VC. When clear, suppresses a match for a transaction from that
VC.
• Bit 30: VC14
• Bit 29: VC13
• Bit 28: VC12
• Bit 27: VC11
• Bit 26: VC10
• Bit 25: VC9
0h
30:16 • Bit 24: VC8
RW
• Bit 23: VC7
• Bit 22: VC6
• Bit 21: VC5
• Bit 20: VC4
• Bit 19: VC3
• Bit 18: VC2
• Bit 17: VC1
• Bit 16: VC0
CPU Core Match (CPU_CORE_MATCH): This field is used to match Logical
Processor Core ID for CPU IDI transactions for Lites Group 2. Each bit, when set,
enables a match for a transaction originating from that core. When clear, suppresses
a match for a transaction from that core.
• Bit 15: CPU7 Core1
• Bit 14: CPU7 Core0
• Bit 13: CPU6 Core1
• Bit 12: CPU6 Core0
• Bit 11: CPU5 Core1
• Bit 10: CPU5 Core0

15:0
0h • Bit 9: CPU4 Core1
RW
• Bit 8: CPU4 Core0
• Bit 7: CPU3 Core1
• Bit 6: CPU3 Core0
• Bit 5: CPU2 Core1
• Bit 4: CPU2 Core0
• Bit 3: CPU1 Core1
• Bit 2: CPU1 Core0
• Bit 1: CPU0 Core1
• Bit 0: CPU0 Core0

710 334818
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5.9.164 B-Unit Lites Group 2 U2C IntData Match Filter

(B_CR_LITES2_U2CINTDATA_MATCH_0_0_0_MCHBAR)—
Offset 6CFCh
When U2C alternate view is enabled, this register specifies match criteria for U2C
IntData.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INTDATA_MASK

INTDATA_MATCH
Bit Default &
Field Name (ID): Description
Range Access

IntData Mask (INTDATA_MASK): This mask is for generating

Lites Group 2 U2C request alternative view match. Only bits [7:0]
of this field are used; bits [15:8] are ignored. If a mask bit in this
0h
31:16 register is 0, then the corresponding bit in the INTDATA_MATCH
RW
field is ignored. If the mask bit is 1, then the corresponding bit in
the INTDATA_MATCH[7:0] field must match its corresponding u2c
request IntData[15:8] bit for a match.
IntData Match (INTDATA_MATCH): U2C Request
IntData[15:8] value is compared with bits [7:0] of this field to
0h
15:0 generate a match for the U2C request address match. Bits [15:8]
RW
of this field are ignored. Note that matching based on the
IntData[7:0] bits is not supported.

5.9.165 B-Unit Lites Group 2 Address Match Filter

LITES2_ADDR_MATCH
(B_CR_LITES2_ADDR_MATCH_0_0_0_MCHBAR)—Offset
6D00h
This register, together with the LITES2_ADDR_MASK register, specifies the request
address values that trigger a Lites Group 2 address match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

334818 711
 MCHBAR

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000

RESERVED_1

ADDRESS_MATCH

RESERVED_0
Bit Default &
Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_1): Reserved.
RO

0h Address Match (ADDRESS_MATCH): Address value to match

38:3
RW for Lites.

2:0
0h Reserved (RESERVED_0): Reserved.
RO

5.9.166 B-Unit Lites Group 2 Address Mask Filter

LITES2_ADDR_MASK
(B_CR_LITES2_ADDR_MASK_0_0_0_MCHBAR)—Offset
6D08h
This register, together with the LITES2_ADDR_MATCH register, specifies the request
address values that trigger a Lites Group 2 address match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
ADDRESS_MASK
RESERVED_1

RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_1): Reserved.
RO

712 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Address Mask (ADDRESS_MASK): Address mask value used

for comparing request address during filter operation for Lites. If
0h the mask bit in this register is 0, then the corresponding bit in the
38:3
RW ADDR_MATCH register is ignored. If the mask bit is 1, then the
corresponding bit in the ADDR_MATCH register must match the
corresponding request address bit for a match.

2:0
0h Reserved (RESERVED_0): Reserved.
RO

5.9.167 B-Unit Lites Group 2 Data Match Filter

LITES2_DATA_MATCH
(B_CR_LITES2_DATA_MATCH_0_0_0_MCHBAR)—Offset
6D10h
This register, together with LITES2_DATA_MASK, specifies the data values that will
trigger a Lites Group 2 data filter match. All data observation points PMI data in PMI
data out read data to agent both live and nonlive and write data from agent use the
same Group 2 data match/mask registers for generating a match. Data match/mask
can be enabled for only one DW of the transaction data. The specific DW can be
selected via DWORD_SELECT.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA_MATCH

Bit Default &

Field Name (ID): Description
Range Access

31:0
0h Data Match (DATA_MATCH): Data value to match for Lites
RW

5.9.168 B-Unit Lites Group 2 Data Mask Filter LITES2_DATA_MASK

(B_CR_LITES2_DATA_MASK_0_0_0_MCHBAR)—Offset
6D14h
This register, together with LITES2_DATA_MATCH, specifies the data values that will
trigger a Lites Group 2 data filter match for Lites. All data observation points PMI data
in PMI data out read data to agent both live and nonlive and write data from agent use

334818 713
 MCHBAR

the same Group 2 data match/mask registers for generating a Group 2 data filter
match. Data match/mask can be enabled for only one DW of the transaction data. The
specific DW can be selected via DWORD_SELECT.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA_MASK
Bit Default &
Field Name (ID): Description
Range Access

Data Mask (DATA_MASK): Data mask value used for comparing

data during filter operations for Lites. If the mask bit in this
0h register is 0, then the corresponding bit in the DATA_MATCH
31:0
RW register is ignored. If the mask bit is 1, then the corresponding bit
in the DATA_MATCH register must match the corresponding bit of
the request data for a match.

5.9.169 B-Unit Lites Group 3 Control

(B_CR_LITES3_CTL_0_0_0_MCHBAR)—Offset 6D20h
This register controls the functionality of the B-Unit Lites Group 3 mask/match
functionality.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENABLE_GROUP
DWORD_SELECT

ALTU2CREQVIEW
IDI_LENGTH_MATCH

RESERVED_0
PII_LENGTH_MATCH

ENABLE_DATA_MATCH

INVERT_ADDR_MATCH
SLICE_MATCH

714 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IDI Length Match (IDI_LENGTH_MATCH): Enables length matching for IDI

requests for Lites Group 3. Each bit, when set to 1, enables match for that length for
an IDI request. Lites logic supports only lengths 0-16B for PRd and PortIn and only
64B for all other opcodes.
• Bit 31:64B
• Bit 30:16B
• Bit 29:15B
• Bit 28:14B
• Bit 27:13B
• Bit 26:12B
• Bit 25:11B

31:14
0h • Bit 24:10B
RW
• Bit 23:9B
• Bit 22:8B
• Bit 21:7B
• Bit 20:6B
• Bit 19:5B
• Bit 18:4B
• Bit 17:3B
• Bit 16:2B
• Bit 15:1B
• Bit 14:0B
PII Length Match (PII_LENGTH_MATCH): Enables length matching for PII
requests for Lites Group 3. Each bit, when set to 1, enables length match for the PII
0h request:
13:12
RW • Bit 13:64B
• Bit 12:32B

11:10
0h Reserved (RESERVED_0): Reserved.
RO

Slice Match (SLICE_MATCH):

• 00: All mask/match hits are suppressed
0h
9:8 • 01: mask/match hits enabled only for Slice0
RW
• 10: mask/match hits enabled only for Slice1
• 11: mask/match hits enabled for both Slices
Dword Select (DWORD_SELECT): Selects the dword within the
0h
7:4 512bit data field that is compared for data mask/matches for Lites
RW
Group 3.
0h Enable Data Match (ENABLE_DATA_MATCH): When set, this
3
RW field enables data matching on Lites Group 3.

334818 715
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Alternate U2C Request View (ALTU2CREQVIEW): When set,

address match/mask, opcode match and agent match registers
0h
2 are used to generate matches for the U2C request observation
RW
point. When clear, Badmit observation point matches are reported
on the U2C request observation point.
Invert Address Match (INVERT_ADDR_MATCH): When set
0h
1 inverts the polarity of the address match/mask logic i.e. reports a
RW
match for addresses that are not in the specified range.
Enable Group (ENABLE_GROUP): Enables all match filters for
Lites Group 3. The following are the observation points that
contain match filters Badmit logic within each slice after a
transaction is successfully admitted into the B-Unit U2C request
0h
0 launch PMI datain for each PMI channel read data PMI dataout for
RW
each PMI channel write data agent data write to BRAM in each
slice read data return on the live bypass and nonlive bypass paths
in each slice. To report a match at an observation point all match
criteria for that point must be satisfied.

5.9.170 B-Unit Lites Group 3 Opcode Match Filter

(B_CR_LITES3_OPCODE_MATCH_0_0_0_MCHBAR)—
Offset 6D24h
This register contains the IDI and PII opcodes that will enable a Lites Group3 opcode
match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OPCODE_MATCH

716 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Opcode Match (OPCODE_MATCH): Bit vector that enables a match on the opcode
for C2U IDI requests, PII A2B requests, and U2C IDI requests. All three observation
points -- Badmit in both slices, and the U2C request interface -- use this same
opcode match register. Each bit, when set, enables a match on the corresponding
opcode, and when clear will suppress a match on the corresponding opcode. To
match on any opcode, set all bits to 1.
• Bit 31: C2U_Req_CRd
• Bit 30: C2U_Req_DRd
• Bit 29: C2U_Req_DRdPTE
• Bit 28: C2U_Req_SetMonitor
• Bit 27: C2U_Req_RFO,U2C_Req_LTWrite_piclet
• Bit 26: C2U_Req_PRd,U2C_Req_VLW_piclet
• Bit 25: C2U_Req_UcRdF
• Bit 24: C2U_Req_PortIn,U2C_Req_SnpCode
• Bit 23: C2U_Req_IntA,U2C_Req_SnpData
• Bit 22: C2U_Req_Lock
• Bit 21: C2U_Req_SplitLock,U2C_Req_IntLog_piclet
• Bit 20: C2U_Req_Unlock,U2C_Req_IntPhy_piclet
• Bit 19: C2U_Req_ItoM
• Bit 18: C2U_Req_SpCyc,U2C_Req_SnpInv
0h
31:0
RW • Bit 17: C2U_Req_RdMonitor,U2C_Req_StopReq
• Bit 16: C2U_Req_ClrMonitor,U2C_Req_StartReq
• Bit 15: C2U_Req_CLFlush
• Bit 14: C2U_Req_WbMtoI,U2C_Req_IntLog_MSI
• Bit 13: C2U_Req_WbMtoE,U2C_Req_IntPhy_MSI
• Bit 12: C2U_Req_WiL
• Bit 11: C2U_Req_WCiL
• Bit 10: C2U_Req_WCilF
• Bit 9: C2U_Req_PortOut
• Bit 8: C2U_Req_IntPriUp,U2C_Req_LTWrite
• Bit 7: C2U_Req_IntLog
• Bit 6: C2U_Req_IntPhy
• Bit 5: C2U_Req_EOI,U2C_Req_VLW
• Bit 4: C2U_Req_ItoMWr
• Bit 3: A2B_Req_SnoopedRead
• Bit 2: A2B_Req_UnSnoopedRead,U2C_Req_IntPhy_IPI
• Bit 1: A2B_Req_SnoopedWrite
• Bit 0: A2B_Req_UnSnoopedWrite,U2C_Req_IntLog_IPI

334818 717
 MCHBAR

5.9.171 B-Unit Lites Group 3 Agent Match Filter

(B_CR_LITES3_AGENT_MATCH_0_0_0_MCHBAR)—Offset
6D28h
This register designates which agents are enabled to trigger a Lites Group3 AgentID
match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VC_MATCH
GT_MATCH

CPU_CORE_MATCH
Bit Default &
Field Name (ID): Description
Range Access

GT Match (GT_MATCH): This field is used to match IDI

0h ransactions from GT for Lites Group3. When set, enables a match
31
RW for a transaction originating from GT. When clear, suppresses a
match for a transaction from GT.

718 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

VC Match (VC_MATCH): This field is used to match VC Channel ID for PII

transactions, for Lites Group3. Each bit, when set, enables a match for a transaction
originating from that VC. When clear, the bit suppresses a match for a transaction
from that VC.
• Bit 30: VC14
• Bit 29: VC13
• Bit 28: VC12
• Bit 27: VC11
• Bit 26: VC10
• Bit 25: VC9
0h
30:16 • Bit 24: VC8
RW
• Bit 23: VC7
• Bit 22: VC6
• Bit 21: VC5
• Bit 20: VC4
• Bit 19: VC3
• Bit 18: VC2
• Bit 17: VC1
• Bit 16: VC0
CPU Core Match (CPU_CORE_MATCH): This field is used to match Logical
Processor Core ID for CPU IDI transactions, for Lites Group 3. Each bit, when set,
enables a match for a transaction originating from that core. When clear, the bit
suppresses a match for a transaction from that core.
• Bit 15: CPU7 Core1
• Bit 14: CPU7 Core0
• Bit 13: CPU6 Core1
• Bit 12: CPU6 Core0
• Bit 11: CPU5 Core1
• Bit 10: CPU5 Core0

15:0
0h • Bit 9: CPU4 Core1
RW
• Bit 8: CPU4 Core0
• Bit 7: CPU3 Core1
• Bit 6: CPU3 Core0
• Bit 5: CPU2 Core1
• Bit 4: CPU2 Core0
• Bit 3: CPU1 Core1
• Bit 2: CPU1 Core0
• Bit 1: CPU0 Core1
• Bit 0: CPU0 Core0

334818 719
 MCHBAR

5.9.172 B-Unit Lites Group 3 U2C IntData Match Filter

(B_CR_LITES3_U2CINTDATA_MATCH_0_0_0_MCHBAR)—
Offset 6D2Ch
When U2C alternate view is enabled, this register specifies match criteria for U2C
IntData.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INTDATA_MASK

INTDATA_MATCH
Bit Default &
Field Name (ID): Description
Range Access

IntData Mask (INTDATA_MASK): This mask is for generating

Lites Group 3 U2C request alternative view match. Only bits [7:0]
of this field are used; bits [15:8] are ignored. If a mask bit in this
0h
31:16 register is 0, then the corresponding bit in the INTDATA_MATCH
RW
field is ignored. If the mask bit is 1, then the corresponding bit in
the INTDATA_MATCH[7:0] field must match its corresponding u2c
request IntData[15:8] bit for a match.
IntData Match (INTDATA_MATCH): U2C Request
IntData[15:8] value is compared with bits [7:0] of this field to
0h
15:0 generate a match for the U2C request address match. Bits [15:8]
RW
of this field are ignored. Note that matching based on the
IntData[7:0] bits is not supported.

5.9.173 B-Unit Lites Group 3 Address Match Filter

LITES3_ADDR_MATCH
(B_CR_LITES3_ADDR_MATCH_0_0_0_MCHBAR)—Offset
6D30h
This register, together with the LITES3_ADDR_MASK register, specifies the request
address values that trigger a Lites Group 3 address match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

720 334818
MCHBAR

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000

RESERVED_1

ADDRESS_MATCH

RESERVED_0
Bit Default &
Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_1): Reserved.
RO

0h Address Match (ADDRESS_MATCH): Address value to match

38:3
RW for Lites.

2:0
0h Reserved (RESERVED_0): Reserved.
RO

5.9.174 B-Unit Lites Group 3 Address Mask Filter

LITES3_ADDR_MASK
(B_CR_LITES3_ADDR_MASK_0_0_0_MCHBAR)—Offset
6D38h
This register, together with the LITES3_ADDR_MATCH register, specifies the request
address values that trigger a Lites Group 3 address match on a transaction.

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000
ADDRESS_MASK
RESERVED_1

RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

63:39
0h Reserved (RESERVED_1): Reserved.
RO

334818 721
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Address Mask (ADDRESS_MASK): Address mask value used

for comparing request address during filter operation for Lites. If
0h the mask bit in this register is 0, then the corresponding bit in the
38:3
RW ADDR_MATCH register is ignored. If the mask bit is 1, then the
corresponding bit in the ADDR_MATCH register must match the
corresponding request address bit for a match.

2:0
0h Reserved (RESERVED_0): Reserved.
RO

5.9.175 B-Unit Lites Group 3 Data Match Filter

LITES3_DATA_MATCH
(B_CR_LITES3_DATA_MATCH_0_0_0_MCHBAR)—Offset
6D40h
This register, together with LITES3_DATA_MASK, specifies the data values that will
trigger a Lites Group 3 data filter match. All data observation points -- PMI data in, PMI
data out, read data to agent (both live and nonlive) and write data from agent -- use
the same Group 3 data match/mask registers for generating a match. Data match/
mask can be enabled for only one DW of the transaction data. The specific DW can be
selected via DWORD_SELECT.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA_MATCH

Bit Default &

Field Name (ID): Description
Range Access

31:0
0h DATA_MATCH (DATA_MATCH): Data value to match for Lites
RW

5.9.176 B-Unit Lites Group 3 Data Mask Filter LITES3_DATA_MASK

(B_CR_LITES3_DATA_MASK_0_0_0_MCHBAR)—Offset
6D44h
This register, together with LITES3_DATA_MATCH, specifies the data values that will
trigger a Lites Group 3 data filter match for Lites. All data observation points -- PMI
data in, PMI data out, read data to agent (both live and nonlive) and write data from

722 334818
MCHBAR

agent -- use the same Group 3 data match/mask registers for generating a Group 3
data filter match. Data match/mask can be enabled for only one DW of the transaction
data. The specific DW can be selected via DWORD_SELECT.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DATA_MASK
Bit Default &
Field Name (ID): Description
Range Access

Data Mask (DATA_MASK): Data mask value used for comparing

data during filter operations for Lites. If the mask bit in this
0h register is 0, then the corresponding bit in the DATA_MATCH
31:0
RW register is ignored. If the mask bit is 1, then the corresponding bit
in the DATA_MATCH register must match the corresponding bit of
the request data for a match.

5.9.177 B-Unit Lites and Emon Master Control LITESEMONCTL

(B_CR_LITESEMON_CTL_0_0_0_MCHBAR)—Offset 6D48h
This register controls the functionality of the B-Unit Lites Debug functionality and Emon
exposure to VISA.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

334818 723
 MCHBAR

ENABLE_LITES

EMON_BARB_CQ_SELECT

EMON_BARB_INGRESS_SELECT

EMON_VC_MASK

EMON_IDI_MASK

LITES_SLICE_SELECT
LITES_IDI_SELECT

LITES_PMI_SELECT
Bit Default &
Field Name (ID): Description
Range Access

Enable Lites (ENABLE_LITES):

0h
31 • 0: Lites logic is disabled. All Lites Views will be driven to 0s.
RW
• 1: Lites logic is enabled.
Emon Barb CQ Select (EMON_BARB_CQ_SELECT): Select barb conflictQ FIFO.

0h
• 0000 to 0111: pii0 to pii7
30:27
RW • 1xx0: idi slice0
• 1xx1: idi slice1
Emon Barb Ingress Select (EMON_BARB_INGRESS_SELECT): Select barb
ingress FIFO.
• 000: IDI attach point -0 -mono | per slice fifo0
• 001: IDI attach point -0 -slice fifo1
• 010: IDI attach point -1 -mono | per slice fifo1
0h
26:24 • 011: IDI attach point -1 - slice fifo
RW
• 100: IDI attach point -2 -mono | GT slice0
• 101: IDI attach point -2 - slice fifo | GT slice1
• 110: IDI attach point -3 -mono | per slice fifo0
• 111: IDI attach point -3 - slice fifo1
Emon VC Mask (EMON_VC_MASK): B-Unit and T-Unit expose
0h
23:13 only the Emons corresponding to the VC(s) specified in this field
RW
(it is a mask).
Emon IDI Mask (EMON_IDI_MASK): B-Unit and T-Unit expose
0h
12:5 only the Emons corresponding to the IDI agent(s) specified in this
RW
field (it is a mask).
Lites IDI Select (LITES_IDI_SELECT): B-Unit and T-Unit
0h
4:2 expose only the views corresponding to the IDI agent specified in
RW
this field.
Lites Slice Select (LITES_SLICE_SELECT): When set to 0, B-
Unit and T-Unit expose only Slice0 views. No Lites observability of
0h
1 any transaction routed to Slice 1. When set to 1, B-Unit and T-Unit
RW
expose only Slice1 views. No Lites observability of any transaction
routed to Slice0.

724 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Lites PMI Select (LITES_PMI_SELECT): When set to 0, B-Unit

exposes only PMI channel 0 views in either slice. No Lites
0h
0 observability of any transaction routed to PMI channel 1 in either
RW
slice. When set to 1, B-Unit exposes only PMI Channel 1 views in
either slice.

5.9.178 B-Unit Arbiter Control BARBCTRL0 (B_CR_BARBCTRL0)—

Offset 6D4Ch
Specifies the weighting for Agents 03 used by the B-Unit's Badmit Arbiter. The value
specified in the Agent Weight field is used by the Badmit arbiters weight counters to
determine the number of requests from an agent that are allowed to be granted before
updating the requester's age register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 4040404h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
RESERVED_0

RESERVED_1

RESERVED_2

RESERVED_3
AGENT3_WEIGHT

AGENT2_WEIGHT

AGENT1_WEIGHT

AGENT0_WEIGHT
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RESERVED_0): Reserved.
RO

4h Agent 3 Weight (AGENT3_WEIGHT): Arbiter weight for Agent

29:24
RW 3.

23:22
0h Reserved (RESERVED_1): Reserved.
RO

4h Agent 2 Weight (AGENT2_WEIGHT): Arbiter weight for Agent

21:16
RW 2.

15:14
0h Reserved (RESERVED_2): Reserved.
RO

4h Agent 1 Weight (AGENT1_WEIGHT): Arbiter weight for Agent

13:8
RW 1.

7:6
0h Reserved (RESERVED_3): Reserved.
RO

334818 725
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

4h Agent 0 Weight (AGENT0_WEIGHT): Arbiter weight for Agent

5:0
RW 0.

5.9.179 B-Unit Arbiter Control BARBCTRL1 (B_CR_BARBCTRL1)—

Offset 6D50h
Specifies the weighting for Agents 4-7 used by the B-Unit's Badmit Arbiter. The value
specified in the Agent Weight field is used by the Badmit arbiter's weight counters to
determine the number of requests from an agent that are allowed to be granted before
updating the requester's age register.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 4040404h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
RESERVED_0

RESERVED_1

RESERVED_2

RESERVED_3
AGENT7_WEIGHT

AGENT6_WEIGHT

AGENT5_WEIGHT

AGENT4_WEIGHT
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RESERVED_0): Reserved.
RO

4h Agent 7 Weight (AGENT7_WEIGHT): Arbiter weight for Agent

29:24
RW 7.

23:22
0h Reserved (RESERVED_1): Reserved.
RO

4h Agent 6 Weight (AGENT6_WEIGHT): Arbiter weight for Agent

21:16
RW 6.

15:14
0h Reserved (RESERVED_2): Reserved.
RO

4h Agent 5 Weight (AGENT5_WEIGHT): Arbiter weight for Agent

13:8
RW 5.

7:6
0h Reserved (RESERVED_3): Reserved.
RO

4h Agent 4 Weight (AGENT4_WEIGHT): Arbiter weight for Agent

5:0
RW 4.

726 334818
MCHBAR

5.9.180 B-Unit Scheduler Control (B_CR_BSCHWT0)—Offset 6D54h

Specifies the weighting for Agents 0-3 used by the B-Unit Scheduler. The value is used
by the B-Unit Scheduler to determine how many requests can be granted for the agent
before the agent's requests are masked by the Scheduler Arbiter, to allow other agents'
requests to be granted.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 4040404h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
RESERVED_0

AGENT3_WEIGHT

RESERVED_1

AGENT2_WEIGHT

RESERVED_2

AGENT1_WEIGHT

RESERVED_3

AGENT0_WEIGHT
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RESERVED_0): Reserved.
RO

4h Agent 3 Weight (AGENT3_WEIGHT): Arbiter weight for Agent

29:24
RW 3.

23:22
0h Reserved (RESERVED_1): Reserved.
RO

4h Agent 2 Weight (AGENT2_WEIGHT): Arbiter weight for Agent

21:16
RW 2.

15:14
0h Reserved (RESERVED_2): Reserved.
RO

4h Agent 1 Weight (AGENT1_WEIGHT): Arbiter weight for Agent

13:8
RW 1.

7:6
0h Reserved (RESERVED_3): Reserved.
RO

4h Agent 0 Weight (AGENT0_WEIGHT): Arbiter weight for Agent

5:0
RW 0.

5.9.181 B-Unit Scheduler Control (B_CR_BSCHWT1)—Offset 6D58h

Specifies the weighting for Agents 4-7 used by the B-Unit Scheduler. The value is used
by the B-Unit Scheduler to determine how many requests can be granted for the agent
before the agent's requests are masked by the Scheduler Arbiter to allow other agents'
requests to be granted.

Access Method

334818 727
 MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 4040404h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
RESERVED_0

AGENT7_WEIGHT

RESERVED_1

AGENT6_WEIGHT

RESERVED_2

AGENT5_WEIGHT

RESERVED_3

AGENT4_WEIGHT
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RESERVED_0): Reserved.
RO

4h Agent 7 Weight (AGENT7_WEIGHT): Arbiter weight for Agent

29:24
RW 7.

23:22
0h Reserved (RESERVED_1): Reserved.
RO

4h Agent 6 Weight (AGENT6_WEIGHT): Arbiter weight for Agent

21:16
RW 6.

15:14
0h Reserved (RESERVED_2): Reserved.
RO

4h Agent 5 Weight (AGENT5_WEIGHT): Arbiter weight for Agent

13:8
RW 5.

7:6
0h Reserved (RESERVED_3): Reserved.
RO

4h Agent 4 Weight (AGENT4_WEIGHT): Arbiter weight for Agent

5:0
RW 4.

5.9.182 B-Unit Scheduler Control (B_CR_BSCHWT2)—Offset 6D5Ch

Specifies the weighting for Agents 8-11 used by the B-Unit Scheduler. The value is used
by the B-Unit Scheduler to determine how many requests can be granted for the agent
before the agent's requests are masked by the Scheduler Arbiter to allow other agents'
requests to be granted.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 4040404h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

728 334818
MCHBAR

0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0

RESERVED_0

AGENT11_WEIGHT

RESERVED_1

AGENT10_WEIGHT

RESERVED_2

RESERVED_3
AGENT9_WEIGHT

AGENT8_WEIGHT
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RESERVED_0): Reserved.
RO

4h Agent 11 Weight (AGENT11_WEIGHT): Arbiter weight for

29:24
RW Agent 11.

23:22
0h Reserved (RESERVED_1): Reserved.
RO

4h Agent 10 Weight (AGENT10_WEIGHT): Arbiter weight for

21:16
RW Agent 10.

15:14
0h Reserved (RESERVED_2): Reserved.
RO

4h Agent 9 Weight (AGENT9_WEIGHT): Arbiter weight for Agent

13:8
RW 9.

7:6
0h Reserved (RESERVED_3): Reserved.
RO

4h Agent 8 Weight (AGENT8_WEIGHT): Arbiter weight for Agent

5:0
RW 8.

5.9.183 B-Unit Scheduler Control (B_CR_BSCHWT3)—Offset 6D60h

Specifies the weighting for Agents 12-15 used by the B-Unit Scheduler. The value is
used by the B-Unit Scheduler to determine how many requests can be granted for the
agent before the agent's requests are masked by the Scheduler Arbiter to allow other
agents' requests to be granted.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 4040404h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0

334818 729
 MCHBAR

RESERVED_0

RESERVED_1

RESERVED_2

RESERVED_3
AGENT15_WEIGHT

AGENT14_WEIGHT

AGENT13_WEIGHT

AGENT12_WEIGHT
Bit Default &
Field Name (ID): Description
Range Access

31:30
0h Reserved (RESERVED_0): Reserved.
RO

4h Agent 15 Weight (AGENT15_WEIGHT): Arbiter weight for

29:24
RW Agent 15.

23:22
0h Reserved (RESERVED_1): Reserved.
RO

4h Agent 14 Weight (AGENT14_WEIGHT): Arbiter weight for

21:16
RW Agent 14.

15:14
0h Reserved (RESERVED_2): Reserved.
RO

4h Agent 13 Weight (AGENT13_WEIGHT): Arbiter weight for

13:8
RW Agent 13.

7:6
0h Reserved (RESERVED_3): Reserved.
RO

4h Agent 12 Weight (AGENT12_WEIGHT): Arbiter weight for

5:0
RW Agent 12.

5.9.184 B-Unit Flush Control (B_CR_BWFLUSH)—Offset 6D64h

Controls the policy used to determine when dirty entries must be flushed to DRAM.
When the number of dirty entries is lower than a high watermark dirty_hwm the B-Unit
will opportunistically flush data to DRAM after the write flush timeout value. When the
number of dirty entries exceeds the high water mark, the B-Unit will initiate a
highpriority flush and push dirty data to DRAM until the count is once again below the
low water mark.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: FF010000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

730 334818
MCHBAR

ALL_ENTRIES_FLUSHED

DIRTY_LWM
FLUSH_THRESHOLD

RESERVED_0

DIRTY_HWM
Bit Default &
Field Name (ID): Description
Range Access

Flush Threshold (FLUSH_THRESHOLD): All write commands

FFh
31:24 are blocked at Badmit if the number of write commands in the
RW
Flush Pool exceeeds this value.

23:17
0h Reserved (RESERVED_0): Reserved.
RO

1h All Entries Flushed (ALL_ENTRIES_FLUSHED): All dirty

16
RO/V entries in the B-Unit, in both slices, have been flushed.
Dirty Low Water Mark (DIRTY_LWM): Low water mark for
0h dirty entries retained by the B-Unit. B-Unit will immediately
15:8
RW attempt to flush any dirty entry, hence setting the low water mark
to 0.
Dirty High Water Mark (DIRTY_HWM): High water mark for
0h dirty entries retained by the B-Unit. B-Unit will immediately
7:0
RW attempt to flush any dirty entry, hence setting the low water mark
to 0.

5.9.185 B-Unit Flush Weights (B_CR_BFLWT)—Offset 6D68h

Controls B-Unit alternate scheduling of reads and writes to DRAM.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 404h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
DISABLE_FLUSH_WEIGHTS

READ_WEIGHTS
WRITE_WEIGHTS
RESERVED_1

RESERVED_0

334818 731
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Disable Flush Weights (DISABLE_FLUSH_WEIGHTS): When

0h set to 1, disables flush weights. Flushing of dirty entries will start
31
RW when Dirty Limit is HWM, and continue until Dirty Limit is LWM. No
reads will be scheduled in between.

30:14
0h Reserved (RESERVED_1): Reserved.
RO

Write Weights (WRITE_WEIGHTS): Number of write requests

4h
13:8 sent to a PMI channel before switching to scheduling read
RW
requests, when use of flush weights is not disabled.

7:6
0h Reserved (RESERVED_0): Reserved.
RO

Read Weights (READ_WEIGHTS): Number of read requests

4h
5:0 sent to a PMI channel before switching to scheduling write
RW
requests, when use of flush weights is not disabled.

5.9.186 Weighted Scheduling Control of High Priority ISOC and

Other Requests (B_CR_BISOCWT)—Offset 6D6Ch
Controls alternate scheduling of High Priority ISOC requests and other requests.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 80003F0Fh

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1
ENABLE_ISOC_WEIGHTS

ISOC_REQUEST_WEIGHTS

NON_ISOC_REQUEST_WEIGHTS
RESERVED_1

RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

Enable ISOC Requests (ENABLE_ISOC_WEIGHTS): When set

1h to 1, enables switching from scheduling High Priority ISOC
31
RW requests to scheduling Best Effort and Low Priority ISOC requests,
based on ISOC weights and NONISOC weights.

732 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

30:14
0h Reserved (RESERVED_1): Reserved.
RO

3Fh ISOC Request Weights (ISOC_REQUEST_WEIGHTS): Weight

13:8
RW for high priority isochronous requests.

7:6
0h Reserved (RESERVED_0): Reserved.
RO

Non ISOC Request Weights

Fh
5:0 (NON_ISOC_REQUEST_WEIGHTS): Weight for non-high
RW
priority isochronous and best effort requests.

5.9.187 B-Unit Control (B_CR_BCTRL2)—Offset 6D70h

Contains basic control information used by the B-Unit.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: F0034h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0
ENABLE_READ_INVALIDATE_TIMER

BRAM_READ_INVALIDATE_TIME
MOT_DISABLE_STALL_ARB_ON_ERR

CASUAL_TIMER

DEMAND_SCRUB_ENABLE

DIRTY_STALL
ENABLE_64B_READ
RESERVED_2

MISS_VALID_ENTRIES
DRAM_ECC_ENABLE

RESERVED_1

ENABLE_64B_WRITE

ENABLE_READ_DONE_FOR_WRITE

Bit Default &

Field Name (ID): Description
Range Access

Enable Read Invalidate Timer

(ENABLE_READ_INVALIDATE_TIMER): When set to 1,
enables the BRAM to clear the RD_DONE bit and flush dirty data
0h
31 when a timer expires. Used when parity is not enabled, to force
RW
the B-Unit to not indefinitely cache previously read lines, and also
to cause a flush of dirty data that has been written to the BRAM
entry.

30:26
0h Reserved (RESERVED_2): Reserved.
RO

334818 733
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

DRAM_ECC_ENABLE (DRAM_ECC_ENABLE): If DRAM ECC is

enabled, the data error bits from the Dunit is used for indicating
0h
25 the derror for the corresponding transactions to the agents and
RW
forcing the poison bit when BUNIT PARITY is unsupported and
Read for partial writes are enabled
MOT Disable Stall Arbiter on Error
0h
24 (MOT_DISABLE_STALL_ARB_ON_ERR): If the HH widget gets
RW
an error, allow transactions to get arbitrated.
BRAM Read Invalidate Time
(BRAM_READ_INVALIDATE_TIME): Timer threshold to clear
Fh rd_done bits or flush a BRAM entry, if dirty. The value specified is
23:16
RW in multiples of 250ns. For each time interval specified, the read
done status of one BRAM entry will be cleared based on a BTAG
index which is then incremented to point to the next BRAM entry.
Casual Timer (CASUAL_TIMER): The number of clock cycles
0h that the B-Unit waits before starting a casual dirty flush. Casual
15:8
RW Flush feature will not be enabled by PND2 architecture. Instead, a
dirty write will be made eligible for scheduling immediately.

7:6
0h Reserved (RESERVED_1): Reserved.
RO

Enable 64B Write (ENABLE_64B_WRITE): When set, B-unit

1h will send 64B PMI Write requests for transactions requiring write
5
RW access to DRAM. Must always be set to one, otherwise functional
errors may occur.
Enable 64B Read (ENABLE_64B_READ): When set, B-unit will
1h send 64B PMI read requests for transactions requiring read access
4
RW to DRAM. Must always be set to one, otherwise functional errors
may occur.
Demand Scrub Enable (DEMAND_SCRUB_ENABLE): This
0h mode causes B-Unit to automatically issue a flush to PMI, thus
3
RO writing correct data back to memory for any read request that
returns with a correctable data error.
Enable Read Done for Write
1h (ENABLE_READ_DONE_FOR_WRITE): Enable Any writes (IWB
2
RW or normal writes) to set the read_done bit in bstat, which enables
return of data from the BRAM cache instead of Memory.
Miss Valid Entries (MISS_VALID_ENTRIES): This mode
causes reads to clean valid B-Unit buffer entries to look like
0h misses instead of hits. When this bit is set -- even when all
1
RW requested bytes are valid and present in the BRAM data buffer --
B-Unit will send read requests over the PMI interface to re-fetch
the data from DRAM, instead of returning it from the BRAM.
Dirty Stall (DIRTY_STALL): This mode causes reads or writes
0h from any requester interface to dirty valid B-Unit buffer entries to
0
RW stall on the appropriate requester interface until the entry has
been flushed from the B-Unit.

734 334818
MCHBAR

5.9.188 Asset Classification Bits

(B_CR_AC_RS0_0_0_0_MCHBAR)—Offset 6D74h
B-Unit Asset Classification AC[3] bits for IMRs and Special Protected Memory Region.
Controls whether RS0 Root Space 0 transactions from PII are allowed access to IMRs
and Protected Memory Region.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 100000h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 1
MOT_RS0_EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IMR_RS0_EN
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

31:21
0h Reserved (RESERVED_0): Reserved.
RO

MOT RS Asset Classification (MOT_RS0_EN): RS Asset

Classification bit for the MOT buffer. PII transactions from RS0 that
hit the MOT buffer will be allowed access only when both of the
1h following conditions are met: a) Request SAI is in the legal
20
RW permitted list, as specified in the RAC/WAC policy registers, and b)
MOT_RS0_EN bit is set to 1. PII RS0 transactions targeting DRAM
that do not hit any enabled IMR or special protected regions will
always be allowed access.
IMR RS Asset Classification (IMR_RS0_EN): RS Asset
Classification bit for IMRs 0-19. PII transactions from RS0 that hit
an enabled IMR address range will be allowed access only when
both of the following conditions are met: a) Request SAI is in the
0h
19:0 legal permitted list as specified in the IMRs RAC/WAC policy
RW
registers and b) IMR_AC_RS bit corresponding to the IMR is set to
1. PII RS0 transactions targeting DRAM that do not hit any
enabled IMR or special protected regions will always be allowed
access.

5.9.189 IDI Real-Time Feature Configuration Bits

(B_CR_RT_EN_0_0_0_MCHBAR)—Offset 6D78h
IDI Real-Time Feature Configuration register. Controls which IDI attachpoint support
Real-Time traffic/transactions.

Access Method

334818 735
 MCHBAR

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RT_ENABLE
RSVD

RT_IDI_AGENT

RSVD
Bit Default &
Field Name (ID): Description
Range Access

0h
31:18 Reserved.
RO

IDI Agent Real-Time Traffic Mask Bits (RT_IDI_AGENT):

IDI Agent Real-Time Traffic Mask Bits. Controls which IDI Agent
supports Real-Time Traffic/Transactions. Only one IDI Agent needs
0h
17:16 to be selected for real-time traffic. Currently not supporting
RW
multiple IDI agents to be enabled for real-time traffic at the same
time. This field will be active only when Bit 0:RT_ENABLE is set to
'1'
0h
15:1 Reserved.
RO

0h Real-Time Enable (RT_ENABLE): Global enable bit for Real-

0
RW Time Support

5.9.190 B-Unit Control Register 3 (B_CR_BCTRL3)—Offset 6D7Ch

Specifies miscellaneous controls for the the B-Unit.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 140h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0

736 334818
MCHBAR

SLICE_ANTI_STARVE_DISABLE
RSVD

SLICE_ANTI_STARVE_THRESHOLD
Bit Default &
Field Name (ID): Description
Range Access

0h
31:9 Reserved.
RO

Disable C2U Ingress Slice Anti-Starvation

(SLICE_ANTI_STARVE_DISABLE): When set, B-unit will
always make an available request in each instantiated per-slice
C2U Ingress FIFO for all IDI attach points eligible for arbitration in
1h their respective odd/even sa2xclk clock. When clear, B-unit will
8
RW mask a C2U Ingress Slice's available request from arbitration
when SLICE_ANTI_STARVE_THRESHOLD consecutive requests
has been granted for that IDI attach point from the other Slice
Ingress FIFO. Has no effect for IDI attach points that do not have
per-slice Ingress FIFOs
C2U Ingress Slice Anti-Starvation Threshold
(SLICE_ANTI_STARVE_THRESHOLD): Specifies the threshold
40h
7:0 for the number of consecutive requests B-admit arbiter will grant
RW
from the same Slice ingress FIFO for an IDI attachpoint, while the
other Slice also has a request available

5.9.191 Asymmetric Memory Region 0 With No Interleaving

Configuration
(B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR)—Offset
6E40h
Specification of asymmetric memory region 0 (in slice 0) for the configuration with 2
asymmetric memory regions. The register has no affect is SLICE_0_MEM_DISABLED is
set.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

334818 737
 MCHBAR

SLICE0_ASYM_ENABLE

SLICE0_ASYM_BASE
SLICE0_ASYM_LIMIT

RSVD

RSVD
SLICE0_ASYM_CHANNEL_SELECT

Bit Default &

Field Name (ID): Description
Range Access

Enable Asymmetric Region in Slice 0, With No Interleaving

0h
31 (SLICE0_ASYM_ENABLE): Setting this bit to 0 disables
RW
asymmetric memory region 0; setting it to 1 enables the region.
Channel Select for ASYM Region Slice 0
0h
30 (SLICE0_ASYM_CHANNEL_SELECT): Specifies Channel
RW
Selected for ASYM Region Mapped To Slice 0
Limit Address for Asymmetric Memory Region, Slice 0, With
No Interleaving (SLICE0_ASYM_LIMIT): Specifies bits
0h
29:19 [38:28] of the highest address of asymmetric memory region 0 (in
RW
slice 0); all the lower bits of the region's highest address are equal
to 1.
0h
18:15 Reserved.
RO

Base Address for Asymmetric Memory Region, Slice 0, With

0h No Interleaving (SLICE0_ASYM_BASE): Specifies bits [38:28]
14:4
RW of the base address of asymmetric memory region 0 (in slice 0);
all the lower bits of the region's base address are equal to 0.
0h
3:0 Reserved.
RO

5.9.192 Asymmetric Memory Region 1 With No Interleaving

Configuration
(B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR)—Offset
6E44h
Specification of asymmetric memory region 1 (in slice 1) for the configuration with 2
asymmetric memory regions. The register has no affect is SLICE_1_DISABLED is set.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

738 334818
MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SLICE1_ASYM_LIMIT
SLICE1_ASYM_CHANNEL_SELECT

RSVD
SLICE1_ASYM_ENABLE

SLICE1_ASYM_BASE

RSVD
Bit Default &
Field Name (ID): Description
Range Access

Enable Asymmetric Region in Slice 1, With No Interleaving.

0h
31 (SLICE1_ASYM_ENABLE): Setting this bit to 0 disables
RW
asymmetric memory region 1; setting it to 1 enables the region.
Channel Select for ASYM SLICE 1
0h
30 (SLICE1_ASYM_CHANNEL_SELECT): Specifies Channel
RW
Selected for ASYM Region Mapped To Slice 1.
Limit Address for Asymmetric Memory Region, Slice 1, With
No Interleaving (SLICE1_ASYM_LIMIT): Specifies bits
0h
29:19 [38:28] of the highest address of asymmetric memory region 1 (in
RW
slice 1); all the lower bits of the region's highest address are equal
to 1.
0h
18:15 Reserved.
RO

Base Address for Asymmetric Memory Region, Slice 1, With

0h No Interleaving (SLICE1_ASYM_BASE): Specifies bits [38:28]
14:4
RW of the base address of asymmetric memory region 1 (in slice 1);
all the lower bits of the region's base address are equal to 0.
0h
3:0 Reserved.
RO

5.9.193 B-Unit Machine Check Mode Low

(B_CR_BMCMODE_LOW)—Offset 6E48h
Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 1h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

334818 739
 MCHBAR

MC_SIGNAL_MODE
RESERVED_0
Bit Default &
Field Name (ID): Description
Range Access

31:1
0h Reserved (RESERVED_0): Reserved.
RO

Machine Check Signal Mode (MC_SIGNAL_MODE): When set

to 1, B-Unit will not allow any transaction with uncorrectable error
or subsequent memory transaction to propagate through to
Requester. This will essentially hang CPU and CPU will end up with
1h
0 IERR shutdown. Issue: When set to zero B-Unit will allow
RW
transaction with an uncorrectable error to propagate and signal
MC event to CPU if enabled in IA32_MC5_CTL. If enabled MC
event will be taken by CPU cores at the end of instruction
boundary after it detected by ROB

5.9.194 B-Unit Machine Check Mode High

(B_CR_BMCMODE_HIGH)—Offset 6E4Ch
Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

31:0
0h Reserved (RESERVED_0): Reserved.
RO

5.9.195 Two-Way Asymmetric Memory Region Configuration

(B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR)—
Offset 6E50h
Specification of asymmetric memory region for the configuration with 2way Interleaved
Asymmetric memory. It is only supported if all Slices and all Channels are Enabled

740 334818
MCHBAR

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ASYM_2WAY_INTERLEAVE_ENABLE

ASYM_2WAY_BASE

ASYM_2WAY_INTLV_MODE
RSVD

ASYM_2WAY_LIMIT

RSVD

RSVD
Bit Default &
Field Name (ID): Description
Range Access

Enable Two-Way Asymmetric Memory Configuration

0h (ASYM_2WAY_INTERLEAVE_ENABLE): Setting this bit to 0
31
RW disables 2Way Asymmetric Interleaving; setting it to 1 enables the
region.
0h
30:28 Reserved.
RO

Limit Address for Two-Way Asymmetric Memory Region

0h (ASYM_2WAY_LIMIT): Specifies bits [38:28] of the highest
27:17
RW address of Interleave Asymmetric Region; all the lower bits of the
region's highest address are equal to 1.
0h
16:15 Reserved.
RO

Base Address for Two-Way Asymmetric Memory Region

0h (ASYM_2WAY_BASE): Specifies bits [38:28] of the base
14:4
RW address of Interleave Asymmetric Region; all the lower bits of the
region's base address are equal to 0.
Two-Way Asymmetric Interleave Mode
(ASYM_2WAY_INTLV_MODE): Going with 2 bits here. 2'b00 :
Asymmetric memory Split between Channel 0 of Slice 0 and Slice
0h
3:2 1 2'b01 : Asymmetric memory split between Channel 1 of Slice 0
RW
and Slice 1 2'b10 : Asymmetric memory split between Channel 0
and Channel 1 of Slice 0 2'b11 : Asymmetric memory split
between Channel 0 and Channel 1 of Slice 1
0h
1:0 Reserved.
RO

334818 741
 MCHBAR

5.10 Registers Summary

Table 5-10. Summary of pcs_regs_wrapper Registers
Offset Offset
Register Name (ID)—Offset Default Value
Start End

7800h 7803h X2B_BARB_CTL1 (X2B_BARB_CTL1_MCHBAR)—Offset 7804h 150000h

7804h 7807h X2B_BARB_CTL1 (X2B_BARB_CTL1_MCHBAR)—Offset 7804h 0h

7808h 780Bh Clock Gating Control (CLKGATE_CTL_MCHBAR)—Offset 7808h 0h

780Ch 780Fh Miscellaneous Controls (MISC_CTL_MCHBAR)—Offset 780Ch 0h

CMiscellaneous T2A selector

7810h 7813h 4B000000h
(T2A_SELECTOR_MISC_MCHBAR)—Offset 7818h

CMiscellaneous T2A selector

7814h 7817h 0h
(T2A_SELECTOR_MISC_MCHBAR)—Offset 7818h

CMiscellaneous T2A selector

7818h 781Bh 38000AA0h
(T2A_SELECTOR_MISC_MCHBAR)—Offset 7818h

VC Read Ordering CFG

781Ch 781Fh F9F3h
(VC_READ_ORDERING_CFG_MCHBAR)—Offset 781Ch

VC Write Ordering CFG

7820h 7823h F9F3h
(VC_WRITE_ORDERING_CFG_MCHBAR)—Offset 7820h

IDI0 C2U Credit Control

7824h 7827h 6104h
(IDI0_C2U_CREDIT_CTRL_MCHBAR)—Offset 7824h

IDI1 C2U Credit Control

7828h 782Bh 6104h
(IDI1_C2U_CREDIT_CTRL_MCHBAR)—Offset 7828h

IDI2 C2U Credit Control

782Ch 782Fh A290h
(IDI2_C2U_CREDIT_CTRL_MCHBAR)—Offset 782Ch

IDI3 C2U Credit Control

7830h 7833h 0h
(IDI3_C2U_CREDIT_CTRL_MCHBAR)—Offset 7830h

IDI4 C2U Credit Control

7834h 7837h 0h
(IDI4_C2U_CREDIT_CTRL_MCHBAR)—Offset 7834h

IDI5 C2U Credit Control

7838h 783Bh 0h
(IDI5_C2U_CREDIT_CTRL_MCHBAR)—Offset 7838h

IDI6 C2U Credit Control

783Ch 783Fh 0h
(IDI6_C2U_CREDIT_CTRL_MCHBAR)—Offset 783Ch

IDI7 C2U Credit Control

7840h 7843h 0h
(IDI7_C2U_CREDIT_CTRL_MCHBAR)—Offset 7840h

PII2 A2T Credit Control (PII2_A2T_CREDIT_CTRL_MCHBAR)—

7844h 7847h 808h
Offset 7844h

BIOSWR Control Policy

7848h 784Fh C0061010202h
(T_CR_BIOSWR_CP_0_0_0_MCHBAR)—Offset 7848h

BIOSWR Read Access Control

7850h 7857h 80000C00630D0217h
(T_CR_BIOSWR_RAC_0_0_0_MCHBAR)—Offset 7850h

BIOSWR Write Access Control

7858h 785Fh C00610C0212h
(T_CR_BIOSWR_WAC_0_0_0_MCHBAR)—Offset 7858h

TUnit Pcode/Ucode Write, All Read Control Policy Register

7860h 7867h (T_CR_P_U_CODEWR_ALLRD_CP_0_0_0_MCHBAR)—Offset 40001000202h
7860h

TUnit Pcode/Ucode Read Access Control

7868h 786Fh (T_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCHBAR)—Offset FFFFFFFFFFFFFFFFh
7868h

742 334818
MCHBAR

Table 5-10. Summary of pcs_regs_wrapper Registers (Continued)

Offset Offset
Register Name (ID)—Offset Default Value
Start End

TUnit Pcode/Ucode Write Access Control

7870h 7877h (T_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_MCHBAR)—Offset 40801008602h
7870h

5.10.1 X2B_BARB_CTL1 (X2B_BARB_CTL1_MCHBAR)—Offset

7804h
Various weights for the X2B data arbiter.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED_1

RESERVED_0

PII2_READ_DATA_COMP_WEIGHT
IDI7_WRITE_DATA_WEIGHT

IDI6_WRITE_DATA_WEIGHT

IDI5_WRITE_DATA_WEIGHT

IDI4_WRITE_DATA_WEIGHT

IDI3_WRITE_DATA_WEIGHT

IDI2_WRITE_DATA_WEIGHT

IDI1_WRITE_DATA_WEIGHT

IDI0_WRITE_DATA_WEIGHT

Bit Default &

Field Name (ID): Description
Range Access

31:24
0h Reserved 1 (RESERVED_1): Reserved.
RO

IDI7 Write Data Weight (IDI7_WRITE_DATA_WEIGHT): IDI

0h
23:22 Attach Point 7 Write Data Weight only exists if this IDI attach
RW
exists.
IDI6 Write Data Weight (IDI6_WRITE_DATA_WEIGHT): IDI
0h
21:20 Attach Point 6 Write Data Weight only exists if this IDI attach
RW
exists.
IDI5 Write Data Weight (IDI5_WRITE_DATA_WEIGHT): IDI
0h
19:18 Attach Point 5 Write Data Weight only exists if this IDI attach
RW
exists.
IDI4 Write Data Weight (IDI4_WRITE_DATA_WEIGHT): IDI
0h
17:16 Attach Point 4 Write Data Weight only exists if this IDI attach
RW
exists.

334818 743
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IDI3 Write Data Weight (IDI3_WRITE_DATA_WEIGHT): IDI

0h
15:14 Attach Point 3 Write Data Weight only exists if this IDI attach
RW
exists.
IDI2 Write Data Weight (IDI2_WRITE_DATA_WEIGHT): IDI
0h
13:12 Attach Point 2 Write Data Weight only exists if this IDI attach
RW
exists.
IDI1 Write Data Weight (IDI1_WRITE_DATA_WEIGHT): IDI
0h
11:10 Attach Point 1 Write Data Weight only exists if this IDI attach
RW
exists.
IDI0 Write Data Weight (IDI0_WRITE_DATA_WEIGHT): IDI
0h
9:8 Attach Point 0 Write Data Weight only exists if this IDI attach
RW
exists.

7:2
0h Reserved 0 (RESERVED_0): Reserved.
RO

0h PII2 Read Data Completion Weight

1:0
RW (PII2_READ_DATA_COMP_WEIGHT)

5.10.2 Clock Gating Control (CLKGATE_CTL_MCHBAR)—Offset

7808h
Each bit controls a separate Clock Gating Domain. BIOS should write all bits in this
register to 1.
• 0: Overrides clock gating and forces the clock gating domain to behave like a
freerunning clock.
• 1: Enables Clock Gating.

The reset value for this register is controlled by an SA strap. SOCs can tie this strap to
a constant, an output from another unit. The Valleyview A0 setting is shown but other
SOCs/ steppings may have a different reset value. NOTE: This has to be revisited for
the new PND2 T-Unit structure clock gating control.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

744 334818
MCHBAR

B2X_DATSEL_CLK_GATE_EN
X2B_DATSEL_CLK_GATE_EN
IDI_U2C_CRDT_CNT_CLK_GATE_EN

TRKR_SB_VIOL_CLK_GATE_EN
TRKR_SB_VALID_CLK_GATE_EN

IOSF_SB_MSG_CLK_GATE_EN
T2A_Q_CLK_GATE_EN
A2TAPIC_CLK_GATE_EN
RESERVED_8
RESERVED_7
RESERVED_6
RESERVED_5
RESERVED_4
RESERVED_3

BT_FREE_CLK_GATE_EN
MON_LOG_CLK_GATE_EN
A2T_Q_CLK_GATE_EN

U2C_RESP_SEL_CLK_GATE_EN
T2A_REQ_SEL_CLK_GATE_EN
C2APIC_FIFO_CLK_GATE_EN
U2C_REQ_FIFO_CLK_GATE_EN

TRKR_SB_T2A_REQSTAT_CLK_GATE_EN
TRKR_SB_B2X_DATSTAT_CLK_GATE_EN

TRKR_SB_SNP_STAT_CLK_GATE_EN

IOSF_SB_CFG_REG_CLK_GATE_EN
U2C_REQ_SEL_CLK_GATE_EN

TRKR_SB_OLDST_CLK_GATE_EN
UOB_CLK_GATE_EN

TRK_SCBD_U2C_RSP_STAT_CLK_GATE_EN

TRKR_SB_WRSTAT_CLK_GATE_EN

TRKR_SB_REQ_CLK_GATE_EN

TRKR_SB_CLK_GATE_EN
Bit Default &
Field Name (ID): Description
Range Access

31
0h Reserved 8 (RESERVED_8): Reserved.
RO

30
0h Reserved 7 (RESERVED_7): Reserved.
RO

29
0h Reserved 6 (RESERVED_6): Reserved.
RO

28
0h Reserved 5 (RESERVED_5): Reserved.
RO

27
0h Reserved 4 (RESERVED_4): Reserved.
RO

26
0h Reserved 3 (RESERVED_3): Reserved.
RO

IDI_U2C_CRDT_CNT_CLK_GATE_EN
0h
25 (IDI_U2C_CRDT_CNT_CLK_GATE_EN): IDI U2C Credit
RW
Counters Clock Gate Enable
0h BT_FREE_CLK_GATE_EN (BT_FREE_CLK_GATE_EN): BT Free
24
RW Clock Gate Enable
0h Monitor Logic Clock Gate Enable
23
RW (MON_LOG_CLK_GATE_EN)

22
0h A2T Queue Clock Gate Enable (A2T_Q_CLK_GATE_EN)
RW

0h T2A Queue Clock Gate Enable (T2A_Q_CLK_GATE_EN): T2A

21
RW queue clock gate enable. NOTE: Need both request and writepull.

20
0h A2TAPIC Clock Gate Enable (A2TAPIC_CLK_GATE_EN)
RW

0h B2X Data Selector Clock Gate Enable

19
RW (B2X_DATSEL_CLK_GATE_EN)
0h X2B Data Selector Clock Gate Enable
18
RW (X2B_DATSEL_CLK_GATE_EN)
0h U2C Response Selector Clock Gate Enable
17
RW (U2C_RESP_SEL_CLK_GATE_EN)

334818 745
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

0h T2A Request Selector Clock Gate Enable

16
RW (T2A_REQ_SEL_CLK_GATE_EN)
0h C2APIC FIFO Clock Gate Enable
15
RW (C2APIC_FIFO_CLK_GATE_EN)
U2C Request FIFO Clock Gate Enable
0h
14 (U2C_REQ_FIFO_CLK_GATE_EN): NOTE: This should be the
RW
U2C request shim.
0h U2C Request Selector Clock Gate Enable
13
RW (U2C_REQ_SEL_CLK_GATE_EN): NOTE: Need per slice enable.
0h Upstream Ordering Block Clock Gate Enable
12
RW (UOB_CLK_GATE_EN)
Tracker Scoreboard Oldest Clock Gate Enable
0h
11 (TRKR_SB_OLDST_CLK_GATE_EN): Tracker Scoreboard oldest
RW
of available queue clock gate enable.
0h Tracker Scoreboard U2C Response Status Clock Gate
10
RW Enable (TRK_SCBD_U2C_RSP_STAT_CLK_GATE_EN)
0h Tracker Scoreboard T2A Request Status Clock Gate Enable
9
RW (TRKR_SB_T2A_REQSTAT_CLK_GATE_EN)
0h Tracker Scoreboard B2X Data Status Clock Gate Enable
8
RW (TRKR_SB_B2X_DATSTAT_CLK_GATE_EN)
0h Tracker Scoreboard Write Status Clock Gate Enable
7
RW (TRKR_SB_WRSTAT_CLK_GATE_EN)
0h Tracker Scoreboard Snoop Status Clock Gate Enable
6
RW (TRKR_SB_SNP_STAT_CLK_GATE_EN)
0h Tracker Scoreboard Request Clock Gate Enable
5
RW (TRKR_SB_REQ_CLK_GATE_EN)
0h Tracker Scoreboard Violation Clock Gate Enable
4
RW (TRKR_SB_VIOL_CLK_GATE_EN)
0h Tracker Scoreboard Valid Clock Gate Enable
3
RW (TRKR_SB_VALID_CLK_GATE_EN)
0h Tracker Scoreboard Clock Gate Enable
2
RW (TRKR_SB_CLK_GATE_EN)
0h IOSF SB Config Register Clock Gate Enable
1
RW (IOSF_SB_CFG_REG_CLK_GATE_EN)
0h IOSF SB Message Clock Gate Enable
0
RW (IOSF_SB_MSG_CLK_GATE_EN)

5.10.3 Miscellaneous Controls (MISC_CTL_MCHBAR)—Offset

780Ch
Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

746 334818
MCHBAR

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IDI_SHUTDOWN_BYP
SNP_RDY_VEC

SNP_REQ_VEC

IWB_FORWARDING_EN

SPARE2

DPTE_EN
RSVD

RSVD

C2U_DATA_TRACK_DIS

SPARE

GO_ACK_FIFO_EMPTY_CHECK_DIS

DPTE_CNT
Bit Default &
Field Name (ID): Description
Range Access

0h
31:27 Reserved.
RO

0h Snoop Ready Vector (SNP_RDY_VEC): Allows Debug to

26:24
RO/V dynamically read this state in the T-Unit.
0h
23:19 Reserved.
RO

0h Snoop Required Vector (SNP_REQ_VEC): Allows Debug to

18:16
RO/V dynamically read this state in the T-Unit.
C2U Data Tracking Disabled (C2U_DATA_TRACK_DIS):
0h
15 When set, this bit disables the tracking of c2u_data for IDI
RW
shutdown qualification.
IWB_FORWARDING_EN (IWB_FORWARDING_EN): When an
IWB comes into to B-unit, let it write the BRAM, even if the btag
entry is locked waiting on the memory read return. Also, once
0h
14 written into the BRAM, let the tub2xdata logic consider the ooaq
RO
entry as ready to receive data. These two allowances will forward
the IWB data to the requestor, without waiting on the memory
read return.

13:12
0h Spare 2 (SPARE2): Spare bits for hardware.
RW

Spare (SPARE): Readable and Writable Spare bits. SPARE[0] has

0h been consumed. It is used by PCODE to bypass IDI_SHUTDOWN
11:7
RW detection and will force IDI CSM FSM indicator to 1 for pgcb/idle
detection.
GO-ACK FIFO Empty Check Disable
0h (GO_ACK_FIFO_EMPTY_CHECK_DIS): When set, the T-unit
6
RW will NOT wait for the per-agent GO-ACK FIFO to be empty before
accepting a stopidi request from the associated agent.

334818 747
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IDI_SHUTDOWN Bypass (IDI_SHUTDOWN_BYP): Used by

0h
5 PCODE to bypass IDI_SHUTDOWN detection and will force IDI
RW
CSM FSM indicator to 1 for pgcb/idle detection.
DPTE Count (DPTE_CNT): This field controls the number of cycles between sending
Dynamic Prefetch Throttle Update Events to each IDI Attach Point. The 4-bit value in
this field is N and the Count is 2 to the Nth power.

• 0: T-Unit can send a DPTE every cycle.

0h • 1: T-Unit can send a DPTE every 2 cycles.

4:1
RW • 2: T-Unit can send a DPTE every 4 cycles.
• 3: T-Unit can send a DPTE every 8 cycles.
• 4: T-Unit can send a DPTE every 16 cycles.
• 15: T-Unit can send a DPTE every 32768 cycles.
DPTE Enable (DPTE_EN):
0h
0 • 0: Dynamic Prefetch Throttle Events are Disabled.
RW
• 1: Dynamic Prefetch Throttle Events are Enabled.

5.10.4 CMiscellaneous T2A selector

(T2A_SELECTOR_MISC_MCHBAR)—Offset 7818h
This register will provide miscellaneous defeatures and controls for the T2A selector
downstream block in the T-Unit.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 38000AA0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0
MAX_DS_NP_VC0A
Spare1

MAX_DS_NP_VC0B

Spare0
PII_IDLE_THRESHOLD

748 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

PII_IDLE_THRESHOLD (PII_IDLE_THRESHOLD): Number of

1x cycles that BT-unit PII idle conditions should exist before the
38h
31:24 ISM requests idle. The restart time of PII BGFs is on the order of
RW
150 to 210 ns. To avoid this penalty, idle should not be entered
too quickly.

23:13
0h Spare 1 (Spare1): Spare register bits for read/write.
RW

Maximum Downstream Nonposted Requests Issued For

VC0b (MAX_DS_NP_VC0B): Maximum number of downstream
5h nonposted requests the T2A selector can issue for VC0b. This
12:9
RW value should be programmed to less than or equal to the
MAX_DS_NP field value but hardware will cap it at that value
regardless.
Maximum Downstream Nonposted Requests Issued For
VC0a (MAX_DS_NP_VC0A): Maximum number of downstream
5h nonposted requests the T2A selector can issue for VC0a. This
8:5
RW value should be programmed to less than or equal to the
MAX_DS_NP field value but hardware will cap it at that value
regardless.

4:0
0h Spare 0 (Spare0): Spare register bits for read/write.
RW

5.10.5 VC Read Ordering CFG

(VC_READ_ORDERING_CFG_MCHBAR)—Offset 781Ch
Register that indicates whether a particular B2T agent ID is configured to be inorder 1
or can be outoforder 0 for read accesses. This is will cause the access to be routed
through the upstream ordering block value of 1 in the VCs bit or not value of 0 in the
VCs bit. This register is not meant to be a dynamic ability to change inorder/outoforder
nature and should be programmed by BIOS before devices are allowed to access
memory. Note that reset value should work without a write. The IDI attaches are not
upstream VCs or subject to the Upstream Ordering Block but to keep the handling
generic bits will be hardwired to 0 for each IDI attach in the system.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: F9F3h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1

334818 749
 MCHBAR

UPSTREAM_VC1BMMU_IN_ORDER
UPSTREAM_VC0BMMU_IN_ORDER

UPSTREAM_VC2B_IN_ORDER

UPSTREAM_VC1B_IN_ORDER

UPSTREAM_VC0B_IN_ORDER
UPSTREAM_VC2A_IN_ORDER

UPSTREAM_VC1A_IN_ORDER

UPSTREAM_VC0A_IN_ORDER
RESERVED_0

UPSTREAM_VC15_IN_ORDER
UPSTREAM_VC14_IN_ORDER
UPSTREAM_VC13_IN_ORDER
UPSTREAM_VC12_IN_ORDER
UPSTREAM_VC11_IN_ORDER

UPSTREAM_VC0AMMU_IN_ORDER
UPSTREAM_VCBR_IN_ORDER
UPSTREAM_VC2C_IN_ORDER
Bit Default &
Field Name (ID): Description
Range Access

31:16
0h Reserved 0 (RESERVED_0): Reserved for future VC growth.
RO

UPSTREAM_VC15 (UPSTREAM_VC15_IN_ORDER):
Configuration bit for upstream VC15 inorder read handling. 1
1h
15 indicates that it is an inorder VC and reads must be handled by
RW
the Upstream Ordering Block. 0 indicates that it is an outoforder
VC.
UPSTREAM_VC14 (UPSTREAM_VC14_IN_ORDER):
Configuration bit for upstream VC14 inorder read handling. 1
1h
14 indicates that it is an inorder VC and reads must be handled by
RW
the Upstream Ordering Block. 0 indicates that it is an outoforder
VC.
UPSTREAM_VC13 (UPSTREAM_VC13_IN_ORDER):
Configuration bit for upstream VC13 inorder read handling. 1
1h
13 indicates that it is an inorder VC and reads must be handled by
RW
the Upstream Ordering Block. 0 indicates that it is an outoforder
VC.
UPSTREAM_VC12 (UPSTREAM_VC12_IN_ORDER):
Configuration bit for upstream VC12 inorder read handling. 1
1h
12 indicates that it is an inorder VC and reads must be handled by
RW
the Upstream Ordering Block. 0 indicates that it is an outoforder
VC.
UPSTREAM_VC11 (UPSTREAM_VC11_IN_ORDER):
Configuration bit for upstream VC11 inorder read handling. 1
1h
11 indicates that it is an inorder VC and reads must be handled by
RW
the Upstream Ordering Block. 0 indicates that it is an outoforder
VC.
UPSTREAM_VC1BMMU_IN_ORDER
(UPSTREAM_VC1BMMU_IN_ORDER): Configuration bit for
0h
10 upstream VC1Bmmus inorder read handling. 1 indicates that it is
RW
an inorder VC and reads must be handled by the Upstream
Ordering Block. 0 indicates that it is an outoforder VC.

750 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

UPSTREAM_VC0BMMU_IN_ORDER
(UPSTREAM_VC0BMMU_IN_ORDER): Configuration bit for
0h
9 upstream VC0Bmmus inorder read handling. 1 indicates that it is
RW
an inorder VC and reads must be handled by the Upstream
Ordering Block. 0 indicates that it is an outoforder VC.
UPSTREAM_VC0AMMU_IN_ORDER
(UPSTREAM_VC0AMMU_IN_ORDER): Configuration bit for
1h
8 upstream VC0Ammus inorder read handling. 1 indicates that it is
RW
an inorder VC and reads must be handled by the Upstream
Ordering Block. 0 indicates that it is an outoforder VC.
Upstream VCBR In Order (UPSTREAM_VCBR_IN_ORDER): Configuration bit for
upstream VCbrs inorder read handling.
1h • 1: Indicates that it is an inorder VC and reads must be
7
RW handled by the Upstream Ordering Block
• 0: Indicates that it is an outoforder VC
Upstream VC2C In Order (UPSTREAM_VC2C_IN_ORDER): Configuration bit for
upstream VC2cs inorder read handling.
1h • 1: Indicates that it is an inorder VC and reads must be
6
RW handled by the Upstream Ordering Block
• 0: Indicates that it is an outoforder VC
Upstream VC2B In Order (UPSTREAM_VC2B_IN_ORDER): Configuration bit for
upstream VC2bs inorder read handling.
1h • 1: Indicates that it is an inorder VC and reads must be
5
RW handled by the Upstream Ordering Block
• 0: Indicates that it is an outoforder VC
Upstream VC2A In Order (UPSTREAM_VC2A_IN_ORDER): Configuration bit for
upstream VC2as inorder read handling.
1h • 1 indicates that it is an inorder VC and reads must be handled
4
RW by the Upstream Ordering Block.
• 0 indicates that it is an outoforder VC.
Upstream VC1B In Order (UPSTREAM_VC1B_IN_ORDER): Configuration bit for
upstream VC1bs inorder read handling.
0h • 1 indicates that it is an inorder VC and reads must be handled
3
RW by the Upstream Ordering Block.
• 0 indicates that it is an outoforder VC.
Upstream VC1A In Order (UPSTREAM_VC1A_IN_ORDER): Configuration bit for
upstream VC1as inorder read handling.
0h • 1 indicates that it is an inorder VC and reads must be handled
2
RW by the Upstream Ordering Block.
• 0 indicates that it is an outoforder VC.
Upstream VC0B In Order (UPSTREAM_VC0B_IN_ORDER): Configuration bit for
upstream VC0bs inorder read handling.
1h • 1 indicates that it is an inorder VC and reads must be handled
1
RW by the Upstream Ordering Block.
• 0 indicates that it is an outoforder VC.

334818 751
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Upstream VC0A In Order (UPSTREAM_VC0A_IN_ORDER): Configuration bit for

upstream VC0as inorder read handling.
1h • 1 indicates that it is an inorder VC and reads must be handled
0
RW by the Upstream Ordering Block.
• 0 indicates that it is an outoforder VC.

5.10.6 VC Write Ordering CFG

(VC_WRITE_ORDERING_CFG_MCHBAR)—Offset 7820h
Register that indicates whether a particular B2T agent ID is configured to be inorder 1
or can be outoforder 0 for write accesses. This is will cause the access to be routed
through the upstream ordering block value of 1 in the VCs bit or not value of 0 in the
VCs bit. This register is not meant to be a dynamic ability to change inorder/outoforder
nature and should be programmed by BIOS before devices are allowed to access
memory note that reset value should work without a write. The IDI attaches are not
upstream VCs or subject to the Upstream Ordering Block but to keep the handling
generic bits will be hardwired to 0 for each IDI attach in the system.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: F9F3h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1
UPSTREAM_VC0AMMU_IN_ORDER
RESERVED_0

UPSTREAM_VC15_IN_ORDER
UPSTREAM_VC14_IN_ORDER
UPSTREAM_VC13_IN_ORDER
UPSTREAM_VC12_IN_ORDER
UPSTREAM_VC11_IN_ORDER

UPSTREAM_VC2C_IN_ORDER
UPSTREAM_VC2B_IN_ORDER
UPSTREAM_VC2A_IN_ORDER
UPSTREAM_VC1B_IN_ORDER
UPSTREAM_VC1A_IN_ORDER
UPSTREAM_VC0B_IN_ORDER
UPSTREAM_VC0A_IN_ORDER
UPSTREAM_VCBR_IN_ORDER
UPSTREAM_VC1BMMU_IN_ORDER
UPSTREAM_VC0BMMU_IN_ORDER

Bit Default &

Field Name (ID): Description
Range Access

31:16
0h Reserved 0 (RESERVED_0): Reserved for future VC growth.
RO

UPSTREAM_VC15 (UPSTREAM_VC15_IN_ORDER):
Configuration bit for upstream VC15 inorder write handling. 1
1h
15 indicates that it is an inorder VC and writes must be handled by
RW
the Upstream Ordering Block. 0 indicates that it is an outoforder
VC.

752 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

UPSTREAM_VC14 (UPSTREAM_VC14_IN_ORDER):
Configuration bit for upstream VC14 inorder write handling. 1
1h
14 indicates that it is an inorder VC and writes must be handled by
RW
the Upstream Ordering Block. 0 indicates that it is an outoforder
VC.
UPSTREAM_VC13 (UPSTREAM_VC13_IN_ORDER):
Configuration bit for upstream VC13 inorder write handling. 1
1h
13 indicates that it is an inorder VC and writes must be handled by
RW
the Upstream Ordering Block. 0 indicates that it is an outoforder
VC.
UPSTREAM_VC12 (UPSTREAM_VC12_IN_ORDER):
Configuration bit for upstream VC12 inorder write handling. 1
1h
12 indicates that it is an inorder VC and writes must be handled by
RW
the Upstream Ordering Block. 0 indicates that it is an outoforder
VC.
UPSTREAM_VC11 (UPSTREAM_VC11_IN_ORDER):
Configuration bit for upstream VC11 inorder write handling. 1
1h
11 indicates that it is an inorder VC and writes must be handled by
RW
the Upstream Ordering Block. 0 indicates that it is an outoforder
VC.
UPSTREAM_VC1BMMU_IN_ORDER
(UPSTREAM_VC1BMMU_IN_ORDER): Configuration bit for
0h
10 upstream VC1Bmmus inorder write handling. 1 indicates that it is
RW
an inorder VC and writes must be handled by the Upstream
Ordering Block. 0 indicates that it is an outoforder VC.
UPSTREAM_VC0BMMU_IN_ORDER
(UPSTREAM_VC0BMMU_IN_ORDER): Configuration bit for
0h
9 upstream VC0Bmmus inorder write handling. 1 indicates that it is
RW
an inorder VC and writes must be handled by the Upstream
Ordering Block. 0 indicates that it is an outoforder VC.
Upstream VC0MMU In Order (UPSTREAM_VC0AMMU_IN_ORDER):
Configuration bit for upstream VC0mmus inorder write handling.
1h • 1 indicates that it is an inorder VC and writes must be
8
RW handled by the Upstream Ordering Block.
• 0 indicates that it is an outoforder VC.
Upstream VCBR In Order (UPSTREAM_VCBR_IN_ORDER): Configuration bit for
upstream VCbrs inorder write handling.
1h • 1 indicates that it is an inorder VC and writes must be
7
RW handled by the Upstream Ordering Block.
• 0 indicates that it is an outoforder VC.
Upstream VC2C In Order (UPSTREAM_VC2C_IN_ORDER): Configuration bit for
upstream VC2cs inorder write handling.
1h • 1 indicates that it is an inorder VC and writes must be
6
RW handled by the Upstream Ordering Block.
• 0 indicates that it is an outoforder VC.

334818 753
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

Upstream VC2B In Order (UPSTREAM_VC2B_IN_ORDER): Configuration bit for

upstream VC2bs inorder write handling.
1h • 1 indicates that it is an inorder VC and writes must be
5
RW handled by the Upstream Ordering Block.
• 0 indicates that it is an outoforder VC.
Upstream VC2A In Order (UPSTREAM_VC2A_IN_ORDER): Configuration bit for
upstream VC2as inorder write handling.
1h • 1 indicates that it is an inorder VC and writes must be
4
RW handled by the Upstream Ordering Block.
• 0 indicates that it is an outoforder VC.
Upstream VC1B In Order (UPSTREAM_VC1B_IN_ORDER): Configuration bit for
upstream VC1bs inorder write handling.
0h • 1 indicates that it is an inorder VC and writes must be
3
RW handled by the Upstream Ordering Block.
• 0 indicates that it is an outoforder VC.
Upstream VC1A In Order (UPSTREAM_VC1A_IN_ORDER): Configuration bit for
upstream VC1as inorder write handling.
0h • 1 indicates that it is an inorder VC and writes must be
2
RW handled by the Upstream Ordering Block.
• 0 indicates that it is an outoforder VC.
Upstream VC0B In Order (UPSTREAM_VC0B_IN_ORDER): Configuration bit for
upstream VC0bs inorder write handling.
1h • 1 indicates that it is an inorder VC and writes must be
1
RW handled by the Upstream Ordering Block.
• 0 indicates that it is an outoforder VC.
Upstream VC0A In Order (UPSTREAM_VC0A_IN_ORDER): Configuration bit for
upstream VC0as inorder write handling.
1h • 1 indicates that it is an inorder VC and writes must be
0
RW handled by the Upstream Ordering Block.
• 0 indicates that it is an outoforder VC.

5.10.7 IDI0 C2U Credit Control

(IDI0_C2U_CREDIT_CTRL_MCHBAR)—Offset 7824h
This register will provide the number of credits that IDI C2U channels should be
initialized to and other control mechanisms around IDI start/stop flows. A register will
be provided per IDI attach to allow for individual IDI tuning. This register will be for the
agent attached to IDI0.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 6104h

754 334818
MCHBAR

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0

IDI_IA_C2U_DATA_CREDIT_INIT

IDI_IA_C2U_RSP_CREDIT_INIT

IDI_IA_C2U_REQ_CREDIT_INIT
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

31:18
0h Reserved 0 (RESERVED_0): Reserved.
RO

IDI IA C2U Data Credit Initialization

(IDI_IA_C2U_DATA_CREDIT_INIT): This register is the
number of credits to initialize C2U data credits for the IDI attach
point associated with this register. It is not legal to program this
6h
17:12 field to a value larger than the C2U ingress data queue size in B-
RW
Unit. This provides an ability to limit data credits at the next IDI
start request change will only take place after the next IDI start
request. The default value of this register should work out of
reset.
IDI IA C2U Response Credit Initialization
(IDI_IA_C2U_RSP_CREDIT_INIT): This register is the
number of credits to initialize C2U response credits for the IDI
attach point associated with this register. It is not legal to program
4h
11:6 this field to a value larger than the C2U response shim ingress
RW
queue size in T-Unit. This provides an ability to limit response
credits at the next IDI start request. Change will only take place
after next IDI start request. The default value of this register
should work out of reset.
IDI IA C2U Request Credit Initialization
(IDI_IA_C2U_REQ_CREDIT_INIT): This register is the
number of credits to initialize C2U requests credits for the IDI
attach point associated with this register. It is not legal to program
4h
5:0 this field to a value larger than the C2U ingress queue size in
RW
Badmit. This provides an ability to limit request credits at the next
IDI start request. Change will only take place after next IDI start
request. The default value of this register should work out of
reset.

334818 755
 MCHBAR

5.10.8 IDI1 C2U Credit Control

(IDI1_C2U_CREDIT_CTRL_MCHBAR)—Offset 7828h
This register will provide the number of credits that IDI C2U channels should be
initialized to and other control mechanisms around IDI start/stop flows. A register will
be provided per IDI attach to allow for individual IDI tuning. This register will be for the
agent attached to IDI1.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 6104h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0

IDI_IA_C2U_DATA_CREDIT_INIT

IDI_IA_C2U_REQ_CREDIT_INIT
IDI_IA_C2U_RSP_CREDIT_INIT
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

31:18
0h Reserved 0 (RESERVED_0): Reserved
RO

IDI IA C2U Data Credit Initialization

(IDI_IA_C2U_DATA_CREDIT_INIT): This register is the
number of credits to initialize C2U data credits for the IDI attach
point associated with this register. It is not legal to program this
6h
17:12 field to a value larger than the C2U ingress data queue size in B-
RW
Unit. This provides an ability to limit data credits at the next IDI
start request. Change will only take place after next IDI start
request. The default value of this register should work out of
reset.
IDI IA C2U Response Credit Initialization
(IDI_IA_C2U_RSP_CREDIT_INIT): This bit field contains the
number of credits to initialize C2U response credits for the IDI
attach point associated with this register. It is not legal to program
4h
11:6 this field to a value larger than the C2U response shim ingress
RW
queue size in T-Unit. This provides an ability to limit response
credits at the next IDI start request. Change will only take place
after next IDI start request. The default value of this register
should work out of reset.

756 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IDI IA C2U Request Credit Initialization

(IDI_IA_C2U_REQ_CREDIT_INIT): This register is the
number of credits to initialize C2U requests credits for the IDI
attach point associated with this register. It is not legal to program
4h
5:0 this field to a value larger than the C2U ingress queue size in
RW
Badmit. This provides an ability to limit request credits at the next
IDI start request change will only take place after next IDI start
request. The default value of this register should work out of
reset.

5.10.9 IDI2 C2U Credit Control

(IDI2_C2U_CREDIT_CTRL_MCHBAR)—Offset 782Ch
This register will provide the number of credits that IDI C2U channels should be
initialized to and other control mechanisms around IDI start / stop flows. A register will
be provided per IDI attach to allow for individual IDI tuning. This register will be for the
agent attached to IDI2.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: A290h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0

IDI_C2U_REQ_CREDIT_INIT
IDI_C2U_RSP_CREDIT_INIT
IDI_C2U_DATA_CREDIT_INIT
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

31:18
0h Reserved 0 (RESERVED_0): Reserved
RO

334818 757
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IDI C2U Data Credit Initialization

(IDI_C2U_DATA_CREDIT_INIT): This register is the number
of credits to initialize C2U data credits for the IDI attach point
Ah associated with this register. It is not legal to program this field to
17:12
RW a value larger than the C2U ingress data queue size in B-Unit. This
provides an ability to limit data credits at the next IDI start
request change will only take place after next IDI start request.
The default value of this register should work out of reset.
IDI C2U Response Credit Initialization
(IDI_C2U_RSP_CREDIT_INIT): This register is the number of
credits to initialize C2U response credits for the IDI attach point
associated with this register. It is not legal to program this field to
Ah
11:6 a value larger than the C2U response shim ingress queue size in T-
RW
Unit. This provides an ability to limit response credits at the next
IDI start request change will only take place after next IDI start
request. The default value of this register should work out of
reset.
IDI C2U Request Credit Initialization
(IDI_C2U_REQ_CREDIT_INIT): This register is the number of
credits to initialize C2U requests credits for the IDI attach point
10h associated with this register. It is not legal to program this field to
5:0
RW a value larger than the C2U ingress queue size in Badmit. This
provides an ability to limit request credits at the next IDI start
request change will only take place after next IDI start request.
The default value of this register should work out of reset.

5.10.10 IDI3 C2U Credit Control

(IDI3_C2U_CREDIT_CTRL_MCHBAR)—Offset 7830h
This register will provide the number of credits that IDI C2U channels should be
initialized to and other control mechanisms around IDI start/stop flows. A register will
be provided per IDI attach to allow for individual IDI tuning. This register will be for the
agent attached to IDI3.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

758 334818
MCHBAR

IDI_IA_C2U_DATA_CREDIT_INIT
RESERVED_0

IDI_IA_C2U_REQ_CREDIT_INIT
IDI_IA_C2U_RSP_CREDIT_INIT
Bit Default &
Field Name (ID): Description
Range Access

31:18
0h Reserved 0 (RESERVED_0): Reserved.
RO

IDI IA C2U Data Credit Initialization

(IDI_IA_C2U_DATA_CREDIT_INIT): This register is the
number of credits to initialize C2U data credits for the IDI attach
point associated with this register. It is not legal to program this
0h
17:12 field to a value larger than the C2U ingress data queue size in B-
RO
Unit. This provides an ability to limit data credits at the next IDI
start request change will only take place after next IDI start
request. The default value of this register should work out of
reset.
IDI IA C2U Response Credit Initialization
(IDI_IA_C2U_RSP_CREDIT_INIT): This register is the
number of credits to initialize C2U response credits for the IDI
attach point associated with this register. It is not legal to program
0h
11:6 this field to a value larger than the C2U response shim ingress
RO
queue size in T-Unit. This provides an ability to limit response
credits at the next IDI start request change will only take place
after next IDI start request. The default value of this register
should work out of reset.
IDI IA C2U Request Credit Initialization
(IDI_IA_C2U_REQ_CREDIT_INIT): This register is the
number of credits to initialize C2U requests credits for the IDI
attach point associated with this register. It is not legal to program
0h
5:0 this field to a value larger than the C2U ingress queue size in
RO
Badmit. This provides an ability to limit request credits at the next
IDI start request change will only take place after next IDI start
request. The default value of this register should work out of
reset.

5.10.11 IDI4 C2U Credit Control

(IDI4_C2U_CREDIT_CTRL_MCHBAR)—Offset 7834h
This register will provide the number of credits that IDI C2U channels should be
initialized to and other control mechanisms around IDI start/stop flows. A register will
be provided per IDI attach to allow for individual IDI tuning. This register will be for the
agent attached to IDI4.

334818 759
 MCHBAR

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IDI_IA_C2U_DATA_CREDIT_INIT
RESERVED_0

IDI_IA_C2U_REQ_CREDIT_INIT
IDI_IA_C2U_RSP_CREDIT_INIT
Bit Default &
Field Name (ID): Description
Range Access

31:18
0h Reserved 0 (RESERVED_0): Reserved
RO

IDI IA C2U Data Credit Initialization

(IDI_IA_C2U_DATA_CREDIT_INIT): This register is the
number of credits to initialize C2U data credits for the IDI attach
point associated with this register. It is not legal to program this
0h
17:12 field to a value larger than the C2U ingress data queue size in B-
RO
Unit. This provides an ability to limit data credits at the next IDI
start request change will only take place after next IDI start
request. The default value of this register should work out of
reset.
IDI IA C2U Response Credit Initialization
(IDI_IA_C2U_RSP_CREDIT_INIT): This register is the
number of credits to initialize C2U response credits for the IDI
attach point associated with this register. It is not legal to program
0h
11:6 this field to a value larger than the C2U response shim ingress
RO
queue size in T-Unit. This provides an ability to limit response
credits at the next IDI start request change will only take place
after next IDI start request. The default value of this register
should work out of reset.

760 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IDI IA C2U Request Credit Initialization

(IDI_IA_C2U_REQ_CREDIT_INIT): This register is the
number of credits to initialize C2U requests credits for the IDI
attach point associated with this register. It is not legal to program
0h
5:0 this field to a value larger than the C2U ingress queue size in
RO
Badmit. This provides an ability to limit request credits at the next
IDI start request change will only take place after next IDI start
request. The default value of this register should work out of
reset.

5.10.12 IDI5 C2U Credit Control

(IDI5_C2U_CREDIT_CTRL_MCHBAR)—Offset 7838h
This register will provide the number of credits that IDI C2U channels should be
initialized to and other control mechanisms around IDI start/stop flows. A register will
be provided per IDI attach to allow for individual IDI tuning. This register will be for the
agent attached to IDI5.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IDI_IA_C2U_DATA_CREDIT_INIT
RESERVED_0

IDI_IA_C2U_RSP_CREDIT_INIT

IDI_IA_C2U_REQ_CREDIT_INIT

Bit Default &

Field Name (ID): Description
Range Access

31:18
0h Reserved 0 (RESERVED_0): Reserved
RO

334818 761
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IDI IA C2U Data Credit Initialization

(IDI_IA_C2U_DATA_CREDIT_INIT): This register is the
number of credits to initialize C2U data credits for the IDI attach
point associated with this register. It is not legal to program this
0h
17:12 field to a value larger than the C2U ingress data queue size in B-
RO
Unit. This provides an ability to limit data credits at the next IDI
start request change will only take place after next IDI start
request. The default value of this register should work out of
reset.
IDI IA C2U Response Credit Initialization
(IDI_IA_C2U_RSP_CREDIT_INIT): This register is the
number of credits to initialize C2U response credits for the IDI
attach point associated with this register. It is not legal to program
0h
11:6 this field to a value larger than the C2U response shim ingress
RO
queue size in T-Unit. This provides an ability to limit response
credits at the next IDI start request change will only take place
after next IDI start request. The default value of this register
should work out of reset.
IDI IA C2U Request Credit Initialization
(IDI_IA_C2U_REQ_CREDIT_INIT): This register is the
number of credits to initialize C2U requests credits for the IDI
attach point associated with this register. It is not legal to program
0h
5:0 this field to a value larger than the C2U ingress queue size in
RO
Badmit. This provides an ability to limit request credits at the next
IDI start request change will only take place after next IDI start
request. The default value of this register should work out of
reset.

5.10.13 IDI6 C2U Credit Control

(IDI6_C2U_CREDIT_CTRL_MCHBAR)—Offset 783Ch
This register will provide the number of credits that IDI C2U channels should be
initialized to and other control mechanisms around IDI start/stop flows. A register will
be provided per IDI attach to allow for individual IDI tuning. This register will be for the
agent attached to IDI6.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

762 334818
MCHBAR

IDI_IA_C2U_DATA_CREDIT_INIT
RESERVED_0

IDI_IA_C2U_REQ_CREDIT_INIT
IDI_IA_C2U_RSP_CREDIT_INIT
Bit Default &
Field Name (ID): Description
Range Access

31:18
0h Reserved 0 (RESERVED_0): Reserved.
RO

IDI IA C2U Data Credit Initialization

(IDI_IA_C2U_DATA_CREDIT_INIT): This register is the
number of credits to initialize C2U data credits for the IDI attach
point associated with this register. It is not legal to program this
0h
17:12 field to a value larger than the C2U ingress data queue size in B-
RO
Unit. This provides an ability to limit data credits at the next IDI
start request change will only take place after next IDI start
request. The default value of this register should work out of
reset.
IDI IA C2U Response Credit Initialization
(IDI_IA_C2U_RSP_CREDIT_INIT): This register is the
number of credits to initialize C2U response credits for the IDI
attach point associated with this register. It is not legal to program
0h
11:6 this field to a value larger than the C2U response shim ingress
RO
queue size in T-Unit. This provides an ability to limit response
credits at the next IDI start request change will only take place
after next IDI start request. The default value of this register
should work out of reset.
IDI IA C2U Request Credit Initialization
(IDI_IA_C2U_REQ_CREDIT_INIT): This register is the
number of credits to initialize C2U requests credits for the IDI
attach point associated with this register. It is not legal to program
0h
5:0 this field to a value larger than the C2U ingress queue size in
RO
Badmit. This provides an ability to limit request credits at the next
IDI start request change will only take place after next IDI start
request. The default value of this register should work out of
reset.

5.10.14 IDI7 C2U Credit Control

(IDI7_C2U_CREDIT_CTRL_MCHBAR)—Offset 7840h
This register will provide the number of credits that IDI C2U channels should be
initialized to and other control mechanisms around IDI start/stop flows. A register will
be provided per IDI attach to allow for individual IDI tuning. This register will be for the
agent attached to IDI4.

334818 763
 MCHBAR

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IDI_IA_C2U_DATA_CREDIT_INIT
RESERVED_0

IDI_IA_C2U_REQ_CREDIT_INIT
IDI_IA_C2U_RSP_CREDIT_INIT
Bit Default &
Field Name (ID): Description
Range Access

31:18
0h Reserved 0 (RESERVED_0): Reserved.
RO

IDI IA C2U Data Credit Initialization

(IDI_IA_C2U_DATA_CREDIT_INIT): This register is the
number of credits to initialize C2U data credits for the IDI attach
point associated with this register. It is not legal to program this
0h
17:12 field to a value larger than the C2U ingress data queue size in B-
RO
Unit. This provides an ability to limit data credits at the next IDI
start request change will only take place after next IDI start
request. The default value of this register should work out of
reset.
IDI IA C2U Response Credit Initialization
(IDI_IA_C2U_RSP_CREDIT_INIT): This register is the
number of credits to initialize C2U response credits for the IDI
attach point associated with this register. It is not legal to program
0h
11:6 this field to a value larger than the C2U response shim ingress
RO
queue size in T-Unit. This provides an ability to limit response
credits at the next IDI start request change will only take place
after next IDI start request. The default value of this register
should work out of reset.

764 334818
MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

IDI IA C2U Request Credit Initialization

(IDI_IA_C2U_REQ_CREDIT_INIT): This register is the
number of credits to initialize C2U requests credits for the IDI
attach point associated with this register. It is not legal to program
0h
5:0 this field to a value larger than the C2U ingress queue size in
RO
Badmit. This provides an ability to limit request credits at the next
IDI start request change will only take place after next IDI start
request. The default value of this register should work out of
reset.

5.10.15 PII2 A2T Credit Control

(PII2_A2T_CREDIT_CTRL_MCHBAR)—Offset 7844h
This register will provide the number of credits that the T-Unit will initialize for the A2T
credit initialization on PII2.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 808h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
PII2_A2T_VC0B_CREDIT_INIT

PII2_A2T_VC0A_CREDIT_INIT
RESERVED_0

Bit Default &

Field Name (ID): Description
Range Access

31:16
0h Reserved 0 (RESERVED_0): Reserved.
RO

PII2 A2T VC0B Credit Initialization

(PII2_A2T_VC0B_CREDIT_INIT): This field is the number of
credits to initialize A2T VC0b requests credits. It is not legal to
8h program this field to a value larger than the A2T VC0b FIFO
15:8
RW ingress queue size in the UAM block. This provides an ability to
limit request credits at the PII2 credit initialization change will
only take place at next credit initialization. The default value of
this register should work out of reset.

334818 765
 MCHBAR

Bit Default &

Field Name (ID): Description
Range Access

PII2 A2T VC0A Credit Initialization

(PII2_A2T_VC0A_CREDIT_INIT): This field is the number of
credits to initialize A2T VC0a requests credits. It is not legal to
8h program this field to a value larger than the A2T VC0a FIFO
7:0
RW ingress queue size in the UAM block. This provides an ability to
limit request credits at the PII2 credit initialization change will
only take place at next credit initialization. The default value of
this register should work out of reset.

5.10.16 BIOSWR Control Policy

(T_CR_BIOSWR_CP_0_0_0_MCHBAR)—Offset 7848h
Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C0061010202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000000010000001000000010
ACCESS_CTRL_POL

Bit Default &

Field Name (ID): Description
Range Access

C0061010 Access Control Policy (ACCESS_CTRL_POL): The Access

63:0 202h Control Policy for this register and the T-Unit Read/write Policy
RW Registers.

5.10.17 BIOSWR Read Access Control

(T_CR_BIOSWR_RAC_0_0_0_MCHBAR)—Offset 7850h
Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 80000C00630D0217h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

1000000000000000000011000000000001100011000011010000001000010111

766 334818
MCHBAR

READ_POL
Bit Default &
Field Name (ID): Description
Range Access

80000C00 Read Policy (READ_POL): The Read Policy for the T-Unit
630D0217
63:0 h
Registers.
RW

5.10.18 BIOSWR Write Access Control

(T_CR_BIOSWR_WAC_0_0_0_MCHBAR)—Offset 7858h
Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: C00610C0212h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000011000000000001100001000011000000001000010010
WRITE_POL

Bit Default &

Field Name (ID): Description
Range Access

C00610C0 Write Policy (WRITE_POL): The Write Policy for the T-Unit
63:0 212h
Registers.
RW

5.10.19 TUnit Pcode/Ucode Write, All Read Control Policy Register

(T_CR_P_U_CODEWR_ALLRD_CP_0_0_0_MCHBAR)—
Offset 7860h
TUnit Pcode/Ucode Write, All Read control policy: This register controls the access
policy to the Tunit P_U_CODEWR_ALLRD_RAC P_U_CODEWR_ALLRD_WAC

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 40001000202h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

334818 767
 MCHBAR

0000000000000000000001000000000000000001000000000000001000000010

ACCESS_CTRL_POL
Bit Default &
Field Name (ID): Description
Range Access

40001000 ACCESS_CTRL_POL (ACCESS_CTRL_POL): The Access Control

63:0 202h Policy for this register and the Tunit ucode Read/write Policy
RW Registers.

5.10.20 TUnit Pcode/Ucode Read Access Control

(T_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCHBAR)—
Offset 7868h
Pcode/Ucode Write, All Read Read Access Control Policy: This register controls the read
access policy to the Tunit P_U_CODEWR_ALLRD

Access Method

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: FFFFFFFFFFFFFFFFh

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

1111111111111111111111111111111111111111111111111111111111111111
READ_POL

Bit Default &

Field Name (ID): Description
Range Access

FFFFFFFFF READ_POL (READ_POL): The Read Policy for the Tunit ucode
63:0 FFFFFFFh
Registers.
RO

5.10.21 TUnit Pcode/Ucode Write Access Control

(T_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_MCHBAR)—
Offset 7870h
Pcode/Ucode Write, All Read Write Access Control Policy: This register controls the
write access policy to the Tunit P_U_CODEWR_ALLRD

Access Method

768 334818
MCHBAR

Type: MEM Register Device:

(Size: 64 bits) Function:

Default: 40801008602h

6 6 5 5 4 4 4 3 3 2 2 2 1 1
8 4 0
3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000001000000100000000001000000001000011000000010

WRITE_POL
Bit Default &
Field Name (ID): Description
Range Access

40801008 WRITE_POL (WRITE_POL): The Write Policy for the Tunit ucode
63:0 602h
Registers.
RW

5.11

334818 769
 MCHBAR

770 334818
5.12 Registers Summary
Table 5-11. Summary of cpgc_t_submap Registers
Offset Offset Default
Register Name (ID)—Offset
Start End Value

3C00h 3C03h Address Decode Repeats (CPGC2_ADDRESS_CONTROL)—Offset 3C18h 61010202h

3C04h 3C07h Address Decode Repeats (CPGC2_ADDRESS_CONTROL)—Offset 3C18h C00h

3C08h 3C0Bh Address Decode Repeats (CPGC2_ADDRESS_CONTROL)—Offset 3C18h FFFFFF3Fh

3C0Ch 3C0Fh Address Decode Repeats (CPGC2_ADDRESS_CONTROL)—Offset 3C18h 1371FFFh

3C10h 3C13h Address Decode Repeats (CPGC2_ADDRESS_CONTROL)—Offset 3C18h 1000212h

3C14h 3C17h Address Decode Repeats (CPGC2_ADDRESS_CONTROL)—Offset 3C18h C00h

3C18h 3C1Bh Address Decode Repeats (CPGC2_ADDRESS_CONTROL)—Offset 3C18h 0h

Address Instruction (CPGC2_ADDRESS_INSTRUCTION[0])—Offset

3C1Ch 3C1Ch 0h
3C1Ch

Address Instruction (CPGC2_ADDRESS_INSTRUCTION[1])—Offset

3C1Dh 3C1Dh 0h
3C1Dh

Address Instruction (CPGC2_ADDRESS_INSTRUCTION[2])—Offset

3C1Eh 3C1Eh 0h
3C1Eh

Address Instruction (CPGC2_ADDRESS_INSTRUCTION[3])—Offset

3C1Fh 3C1Fh 0h
3C1Fh

3C20h 3C20h Data Instruction (CPGC2_DATA_INSTRUCTION[0])—Offset 3C20h 0h

3C21h 3C21h Data Instruction (CPGC2_DATA_INSTRUCTION[1])—Offset 3C21h 0h

3C22h 3C22h Data Instruction (CPGC2_DATA_INSTRUCTION[2])—Offset 3C22h 0h

3C23h 3C23h Data Instruction (CPGC2_DATA_INSTRUCTION[3])—Offset 3C23h 0h

3C24h 3C27h Data Rotation Repeats (CPGC2_DATA_CONTROL)—Offset 3C24h 0h

Address and Data Repeats Status (CPGC2_ADDRESS_DATA_STATUS)—

3C28h 3C2Bh 0h
Offset 3C28h

Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[0])—Offset

3C2Ch 3C2Ch 0h
3C2Ch

Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[1])—Offset

3C2Dh 3C2Dh 0h
3C2Dh

Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[2])—Offset

3C2Eh 3C2Eh 0h
3C2Eh

Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[3])—Offset

3C2Fh 3C2Fh 0h
3C2Fh

Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[4])—Offset

3C30h 3C30h 0h
3C30h

Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[5])—Offset

3C31h 3C31h 0h
3C31h

Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[6])—Offset

3C32h 3C32h 0h
3C32h

Algorithm Instruction (CPGC2_ALGORITHM_INSTRUCTION[7])—Offset

3C33h 3C33h 0h
3C33h

Algorithm Instruction Control

3C34h 3C34h 0h
(CPGC2_ALGORITHM_INSTRUCTION_CTRL[0])—Offset 3C34h

Algorithm Instruction Control

3C35h 3C35h 0h
(CPGC2_ALGORITHM_INSTRUCTION_CTRL[1])—Offset 3C35h

Algorithm Instruction Control

3C36h 3C36h 0h
(CPGC2_ALGORITHM_INSTRUCTION_CTRL[2])—Offset 3C36h

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Table 5-11. Summary of cpgc_t_submap Registers (Continued)
Offset Offset Default
Register Name (ID)—Offset
Start End Value

Algorithm Instruction Control

3C37h 3C37h 0h
(CPGC2_ALGORITHM_INSTRUCTION_CTRL[3])—Offset 3C37h

Algorithm Instruction Control

3C38h 3C38h 0h
(CPGC2_ALGORITHM_INSTRUCTION_CTRL[4])—Offset 3C38h

Algorithm Instruction Control

3C39h 3C39h 0h
(CPGC2_ALGORITHM_INSTRUCTION_CTRL[5])—Offset 3C39h

Algorithm Instruction Control

3C3Ah 3C3Ah 0h
(CPGC2_ALGORITHM_INSTRUCTION_CTRL[6])—Offset 3C3Ah

Algorithm Instruction Control

3C3Bh 3C3Bh 0h
(CPGC2_ALGORITHM_INSTRUCTION_CTRL[7])—Offset 3C3Bh

Wait Timer Current (CPGC2_ALGORITHM_WAIT_COUNT_CURRENT)—

3C3Ch 3C3Fh 0h
Offset 3C3Ch

Algorithm Wait Event Control

3C40h 3C43h 0h
(CPGC2_ALGORITHM_WAIT_EVENT_CONTROL)—Offset 3C40h

3C44h 3C47h Base Repeats (CPGC2_BASE_REPEATS)—Offset 3C44h 0h

Current Base Repeats (CPGC2_BASE_REPEATS_CURRENT)—Offset

3C48h 3C4Bh 0h
3C48h

3C4Ch 3C4Fh Base Column Repeats (CPGC2_BASE_COL_REPEATS)—Offset 3C4Ch 0h

3C50h 3C53h Block Repeats (CPGC2_BLOCK_REPEATS)—Offset 3C50h 0h

Current Block Repeats (CPGC2_BLOCK_REPEATS_CURRENT)—Offset

3C54h 3C57h 0h
3C54h

Command Instruction (CPGC2_COMMAND_INSTRUCTION[0])—Offset

3C58h 3C58h 0h
3C58h

Command Instruction (CPGC2_COMMAND_INSTRUCTION[1])—Offset

3C59h 3C59h 0h
3C59h

Command Instruction (CPGC2_COMMAND_INSTRUCTION[2])—Offset

3C5Ah 3C5Ah 0h
3C5Ah

Command Instruction (CPGC2_COMMAND_INSTRUCTION[3])—Offset

3C5Bh 3C5Bh 0h
3C5Bh

Command Instruction (CPGC2_COMMAND_INSTRUCTION[4])—Offset

3C5Ch 3C5Ch 0h
3C5Ch

Command Instruction (CPGC2_COMMAND_INSTRUCTION[5])—Offset

3C5Dh 3C5Dh 0h
3C5Dh

Command Instruction (CPGC2_COMMAND_INSTRUCTION[6])—Offset

3C5Eh 3C5Eh 0h
3C5Eh

Command Instruction (CPGC2_COMMAND_INSTRUCTION[7])—Offset

3C5Fh 3C5Fh 0h
3C5Fh

Command Instruction (CPGC2_COMMAND_INSTRUCTION[8])—Offset

3C60h 3C60h 0h
3C60h

Command Instruction (CPGC2_COMMAND_INSTRUCTION[9])—Offset

3C61h 3C61h 0h
3C61h

Command Instruction (CPGC2_COMMAND_INSTRUCTION[10])—Offset

3C62h 3C62h 0h
3C62h

Command Instruction (CPGC2_COMMAND_INSTRUCTION[11])—Offset

3C63h 3C63h 0h
3C63h

Command Instruction (CPGC2_COMMAND_INSTRUCTION[12])—Offset

3C64h 3C64h 0h
3C64h

Command Instruction (CPGC2_COMMAND_INSTRUCTION[13])—Offset

3C65h 3C65h 0h
3C65h

772 Intel Confidential 514849

Table 5-11. Summary of cpgc_t_submap Registers (Continued)
Offset Offset Default
Register Name (ID)—Offset
Start End Value

Command Instruction (CPGC2_COMMAND_INSTRUCTION[14])—Offset

3C66h 3C66h 0h
3C66h

Command Instruction (CPGC2_COMMAND_INSTRUCTION[15])—Offset

3C67h 3C67h 0h
3C67h

Command Instruction (CPGC2_COMMAND_INSTRUCTION[16])—Offset

3C68h 3C68h 0h
3C68h

Command Instruction (CPGC2_COMMAND_INSTRUCTION[17])—Offset

3C69h 3C69h 0h
3C69h

Command Instruction (CPGC2_COMMAND_INSTRUCTION[18])—Offset

3C6Ah 3C6Ah 0h
3C6Ah

Command Instruction (CPGC2_COMMAND_INSTRUCTION[19])—Offset

3C6Bh 3C6Bh 0h
3C6Bh

Command Instruction (CPGC2_COMMAND_INSTRUCTION[20])—Offset

3C6Ch 3C6Ch 0h
3C6Ch

Command Instruction (CPGC2_COMMAND_INSTRUCTION[21])—Offset

3C6Dh 3C6Dh 0h
3C6Dh

Command Instruction (CPGC2_COMMAND_INSTRUCTION[22])—Offset

3C6Eh 3C6Eh 0h
3C6Eh

Command Instruction (CPGC2_COMMAND_INSTRUCTION[23])—Offset

3C6Fh 3C6Fh 0h
3C6Fh

3C70h 3C73h Hammer Repeats (CPGC2_HAMMER_REPEATS)—Offset 3C70h 0h

Current Hammer Repeats (CPGC2_HAMMER_REPEATS_CURRENT)—

3C74h 3C77h 0h
Offset 3C74h

Offset Address Instruction

3C78h 3C78h 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[0])—Offset 3C78h

Offset Address Instruction

3C79h 3C79h 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[1])—Offset 3C79h

Offset Address Instruction

3C7Ah 3C7Ah 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[2])—Offset 3C7Ah

Offset Address Instruction

3C7Bh 3C7Bh 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[3])—Offset 3C7Bh

Offset Address Instruction

3C7Ch 3C7Ch 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[4])—Offset 3C7Ch

Offset Address Instruction

3C7Dh 3C7Dh 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[5])—Offset 3C7Dh

Offset Address Instruction

3C7Eh 3C7Eh 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[6])—Offset 3C7Eh

Offset Address Instruction

3C7Fh 3C7Fh 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[7])—Offset 3C7Fh

Offset Address Instruction

3C80h 3C80h 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[8])—Offset 3C80h

Offset Address Instruction

3C81h 3C81h 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[9])—Offset 3C81h

Offset Address Instruction

3C82h 3C82h 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[10])—Offset 3C82h

Offset Address Instruction

3C83h 3C83h 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[11])—Offset 3C83h

Offset Address Instruction

3C84h 3C84h 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[12])—Offset 3C84h

Offset Address Instruction

3C85h 3C85h 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[13])—Offset 3C85h

514849 Intel Confidential 773

Table 5-11. Summary of cpgc_t_submap Registers (Continued)
Offset Offset Default
Register Name (ID)—Offset
Start End Value

Offset Address Instruction

3C86h 3C86h 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[14])—Offset 3C86h

Offset Address Instruction

3C87h 3C87h 0h
(CPGC2_OFFSET_ADDRESS_INSTRUCTION[15])—Offset 3C87h

Offset Command Instruction

3C88h 3C88h 0h
(CPGC2_OFFSET_COMMAND_INSTRUCTION[0])—Offset 3C88h

Offset Command Instruction

3C89h 3C89h 0h
(CPGC2_OFFSET_COMMAND_INSTRUCTION[1])—Offset 3C89h

Offset Command Instruction

3C8Ah 3C8Ah 0h
(CPGC2_OFFSET_COMMAND_INSTRUCTION[2])—Offset 3C8Ah

Offset Command Instruction

3C8Bh 3C8Bh 0h
(CPGC2_OFFSET_COMMAND_INSTRUCTION[3])—Offset 3C8Bh

Offset Command Instruction

3C8Ch 3C8Ch 0h
(CPGC2_OFFSET_COMMAND_INSTRUCTION[4])—Offset 3C8Ch

Offset Command Instruction

3C8Dh 3C8Dh 0h
(CPGC2_OFFSET_COMMAND_INSTRUCTION[5])—Offset 3C8Dh

Offset Command Instruction

3C8Eh 3C8Eh 0h
(CPGC2_OFFSET_COMMAND_INSTRUCTION[6])—Offset 3C8Eh

Offset Command Instruction

3C8Fh 3C8Fh 0h
(CPGC2_OFFSET_COMMAND_INSTRUCTION[7])—Offset 3C8Fh

Offset Command Instruction

3C90h 3C90h 0h
(CPGC2_OFFSET_COMMAND_INSTRUCTION[8])—Offset 3C90h

Offset Command Instruction

3C91h 3C91h 0h
(CPGC2_OFFSET_COMMAND_INSTRUCTION[9])—Offset 3C91h

Offset Command Instruction

3C92h 3C92h 0h
(CPGC2_OFFSET_COMMAND_INSTRUCTION[10])—Offset 3C92h

Offset Command Instruction

3C93h 3C93h 0h
(CPGC2_OFFSET_COMMAND_INSTRUCTION[11])—Offset 3C93h

3C94h 3C97h Offset Repeats (CPGC2_OFFSET_REPEATS[0])—Offset 3C94h 0h

3C98h 3C9Bh Offset Repeats (CPGC2_OFFSET_REPEATS[1])—Offset 3C98h 0h

Current Offset Repeats (CPGC2_OFFSET_REPEATS_CURRENT)—Offset

3C9Ch 3C9Fh 0h
3C9Ch

3CA0h 3CA3h Region Low Row Address (CPGC2_REGION_LOW_ROW)—Offset 3CA0h 0h

3CA4h 3CA7h Region Low Col Address (CPGC2_REGION_LOW_COL)—Offset 3CA4h 0h

Block Low Row Current (CPGC2_BLOCK_ORIGIN_ROW_CURRENT)—

3CA8h 3CABh 0h
Offset 3CA8h

Current Base Address Rank and Column

3CACh 3CAFh 0h
(CPGC2_BASE_ADDRESS_COL_RANK_CURRENT)—Offset 3CACh

Current Base Address Bank and Row

3CB0h 3CB3h 0h
(CPGC2_BASE_ADDRESS_ROW_BANK_CURRENT)—Offset 3CB0h

Current Offset Address Column

3CB4h 3CB7h 0h
(CPGC2_OFFSET_ADDRESS_COL_CURRENT)—Offset 3CB4h

Current Offset Address Row

3CB8h 3CBBh 0h
(CPGC2_OFFSET_ADDRESS_ROW_CURRENT)—Offset 3CB8h

3CBCh 3CBFh Address Size (CPGC2_ADDRESS_SIZE)—Offset 3CBCh 0h

Base Address Control (CPGC2_BASE_ADDRESS_CONTROL)—Offset

3CC0h 3CC3h 0h
3CC0h

Address PRBS Control (CPGC2_ADDRESS_PRBS_CONTROL)—Offset

3CC4h 3CC7h 0h
3CC4h

774 Intel Confidential 514849

Table 5-11. Summary of cpgc_t_submap Registers (Continued)
Offset Offset Default
Register Name (ID)—Offset
Start End Value

3CC8h 3CCBh Address PRBS Seed (CPGC2_ADDRESS_PRBS_SEED)—Offset 3CC8h 0h

Current Address PRBS Status (CPGC2_ADDRESS_PRBS_CURRENT)—

3CCCh 3CCFh 0h
Offset 3CCCh

3CD0h 3CD3h Address PRBS Save (CPGC2_ADDRESS_PRBS_SAVE)—Offset 3CD0h 0h

Command FSM Current State (CPGC2_CMD_FSM_CURRENT)—Offset

3CD4h 3CD7h 0h
3CD4h

Algorithm Wait Timer Configuration (CPGC2_WAIT_2_START_CONFIG)—

3CD8h 3CDBh 0h
Offset 3CD8h

3CDCh 3CDFh VISA Mux Selection (CPGC2_VISA_MUX_SEL)—Offset 3CDCh 0h

3CE0h 3CE3h Loopback Squencer Configuration (CPGC_LB_SEQ_CFG)—Offset 3CE0h 0h

3CE4h 3CE7h Loopback Sequencer Control (CPGC_LB_SEQ_CTL)—Offset 3CE4h 0h

Loopback Loopcount Tx Status

3CE8h 3CEBh 0h
(CPGC_LB_SEQ_LOOPCOUNT_TX_STATUS)—Offset 3CE8h

Loopback Loopcount Rx Status

3CECh 3CEFh 0h
(CPGC_LB_SEQ_LOOPCOUNT_RX_STATUS)—Offset 3CECh

3CF0h 3CF3h Pattern Length Status (CPGC_LB_SEQ_PL_RX_STATUS)—Offset 3CF0h 0h

3CF4h 3CF7h Refresh Control (CPGC_MISC_REFRESH_CTL)—Offset 3CF4h 0h

3CF8h 3CFBh ZQ Control (CPGC_MISC_ZQ_CTL)—Offset 3CF8h 0h

3CFCh 3CFFh ODT Control (CPGC_MISC_ODT_CTL)—Offset 3CFCh 0h

3D00h 3D03h CKE Control (CPGC_MISC_CKE_CTL)—Offset 3D00h 0h

3D04h 3D07h Command Rate (CPGC_MISC_CMD_RATE)—Offset 3D04h 100Ah

3D08h 3D0Bh External Trigger Control (CPGC_MISC_EXT_TRIGGER)—Offset 3D08h 0h

3D0Ch 3D0Fh Sequence Control (CPGC_SEQ_CTL)—Offset 3D0Ch 0h

3D10h 3D13h Sequence Configuration A (CPGC_SEQ_CFG_A)—Offset 3D10h 200000h

3D14h 3D17h Sequence Configuration B (CPGC_SEQ_CFG_B)—Offset 3D14h 0h

3D18h 3D1Bh Sequence Status (CPGC_SEQ_STATUS)—Offset 3D18h 0h

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[0])—

3D1Ch 3D1Fh 410h
Offset 3D20h

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[0])—

3D20h 3D23h 0h
Offset 3D20h

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[1])—

3D24h 3D27h 0h
Offset 3D24h

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[2])—

3D28h 3D2Bh 0h
Offset 3D28h

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[3])—

3D2Ch 3D2Fh 0h
Offset 3D2Ch

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[4])—

3D30h 3D33h 0h
Offset 3D30h

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[5])—

3D34h 3D37h 0h
Offset 3D34h

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[6])—

3D38h 3D3Bh 0h
Offset 3D38h

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[7])—

3D3Ch 3D3Fh 0h
Offset 3D3Ch

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[8])—

3D40h 3D43h 0h
Offset 3D40h

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Table 5-11. Summary of cpgc_t_submap Registers (Continued)
Offset Offset Default
Register Name (ID)—Offset
Start End Value

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[9])—

3D44h 3D47h 0h
Offset 3D44h

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[10])—

3D48h 3D4Bh 0h
Offset 3D48h

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[11])—

3D4Ch 3D4Fh 0h
Offset 3D4Ch

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[12])—

3D50h 3D53h 0h
Offset 3D50h

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[13])—

3D54h 3D57h 0h
Offset 3D54h

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[14])—

3D58h 3D5Bh 0h
Offset 3D58h

Raster Repository Content (CPGC2_RASTER_REPO_CONTENT[15])—

3D5Ch 3D5Fh 0h
Offset 3D5Ch

Mode3 Fail Status LSB (CPGC2_RASTER_REPO_CONTENT_ECC1)—Offset

3D60h 3D63h 0h
3D60h

Mode3 Fail Status MSB (CPGC2_RASTER_REPO_CONTENT_ECC2)—

3D64h 3D67h 0h
Offset 3D64h

Read Command Count (CPGC2_READ_COMMAND_COUNT_CURRENT)—

3D68h 3D6Bh 0h
Offset 3D68h

Mask Errors on First N Reads (CPGC2_MASK_ERRS_FIRST_N_READS)—

3D6Ch 3D6Fh 0h
Offset 3D6Ch

Raster Repository Status (CPGC2_RASTER_REPO_STATUS)—Offset

3D70h 3D73h 0h
3D70h

3D74h 3D77h Error Summary A (CPGC2_ERR_SUMMARY_A)—Offset 3D74h 0h

3D78h 3D7Bh Error Summary B (CPGC2_ERR_SUMMARY_B)—Offset 3D78h 0h

3D7Ch 3D7Fh Future use Reserved (CPGC2_ERR_SUMMARY_C)—Offset 3D7Ch 0h

Data Pattern Generation Buffer Control (CPGC_DPAT_BUF_CTL)—Offset

3D80h 3D83h 0h
3D80h

Data Pattern Generation Configuration (CPGC_DPAT_CFG)—Offset

3D84h 3D87h 0h
3D84h

LFSR Configuration and Lane Rotate (CPGC_DPAT_XTRA_LFSR_CFG)—

3D88h 3D8Bh 0h
Offset 3D88h

Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[0])—Offset

3D8Ch 3D8Fh AA55AA55h
3D8Ch

Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[1])—Offset

3D90h 3D93h AA55AA55h
3D90h

Unisequencer Data Pattern Buffer (CPGC_DPAT_UNISEQ[2])—Offset

3D94h 3D97h AA55AA55h
3D94h

Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[0])—Offset

3D98h 3D9Bh 1010100h
3D98h

Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[1])—Offset

3D9Ch 3D9Fh 1010100h
3D9Ch

Unisequencer LMN Control (CPGC_DPAT_UNISEQ_LMN[2])—Offset

3DA0h 3DA3h 1010100h
3DA0h

3DA4h 3DA7h Invert and DC Control (CPGC_DPAT_INVDCCTL)—Offset 3DA4h AA0000h

Data Invert/DC Enable Low (CPGC_DPAT_INV_DC_MASK_LO)—Offset

3DA8h 3DABh 0h
3DA8h

Data Invert/DC Enable High (CPGC_DPAT_INV_DC_MASK_HI)—Offset

3DACh 3DAFh 0h
3DACh

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Table 5-11. Summary of cpgc_t_submap Registers (Continued)
Offset Offset Default
Register Name (ID)—Offset
Start End Value

3DB0h 3DB3h Byte Enable Mask Lower (CPGC_DPAT_DRAMDM)—Offset 3DB0h FFFFFFFFh

3DB4h 3DB7h Byte Enable Mask Upper (CPGC_DPAT_XDRAMDM)—Offset 3DB4h FFFFFFFFh

Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[0])—Offset

3DB8h 3DBBh 0h
3DB8h

Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[1])—Offset

3DBCh 3DBFh 0h
3DBCh

Unisequencer Status - Write (CPGC_DPAT_UNISEQ_WRSTAT[2])—Offset

3DC0h 3DC3h 0h
3DC0h

Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[0])—Offset

3DC4h 3DC7h DEADBEEFh
3DC4h

Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[1])—Offset

3DC8h 3DCBh DEADBEEFh
3DC8h

Unisequencer Status - Read (CPGC_DPAT_UNISEQ_RDSTAT[2])—Offset

3DCCh 3DCFh DEADBEEFh
3DCCh

3DD0h 3DD3h LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[0])—Offset 3DD0h 0h

3DD4h 3DD7h LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[1])—Offset 3DD4h 0h

3DD8h 3DDBh LMN Status - Write (CPGC_DPAT_LMN_WRSTAT[2])—Offset 3DD8h 0h

3DDCh 3DDFh LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[0])—Offset 3DDCh DEADBEEFh

3DE0h 3DE3h LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[1])—Offset 3DE0h DEADBEEFh

3DE4h 3DE7h LMN Status - Read (CPGC_DPAT_LMN_RDSTAT[2])—Offset 3DE4h DEADBEEFh

Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[0])—

3DE8h 3DEBh DEADBEEFh
Offset 3DE8h

Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[1])—

3DECh 3DEFh DEADBEEFh
Offset 3DECh

Unisequencer Save Status - Write (CPGC_DPAT_UNISEQ_WRSAVE[2])—

3DF0h 3DF3h DEADBEEFh
Offset 3DF0h

Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[0])—

3DF4h 3DF7h 0h
Offset 3DF4h

Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[1])—

3DF8h 3DFBh 0h
Offset 3DF8h

Unisequencer Save Status - Read (CPGC_DPAT_UNISEQ_RDSAVE[2])—

3DFCh 3DFFh 0h
Offset 3DFCh

3E00h 3E03h Extended Pattern Buffer (CPGC_DPAT_EXTBUF[0])—Offset 3E00h AAAAAAAAh

3E04h 3E07h Extended Pattern Buffer (CPGC_DPAT_EXTBUF[1])—Offset 3E04h AAAAAAAAh

3E08h 3E0Bh Extended Pattern Buffer (CPGC_DPAT_EXTBUF[2])—Offset 3E08h AAAAAAAAh

3E0Ch 3E0Fh Extended Pattern Buffer (CPGC_DPAT_EXTBUF[3])—Offset 3E0Ch AAAAAAAAh

3E10h 3E13h Extended Pattern Buffer (CPGC_DPAT_EXTBUF[4])—Offset 3E10h AAAAAAAAh

3E14h 3E17h Extended Pattern Buffer (CPGC_DPAT_EXTBUF[5])—Offset 3E14h AAAAAAAAh

3E18h 3E1Bh Extended Pattern Buffer (CPGC_DPAT_EXTBUF[6])—Offset 3E18h AAAAAAAAh

3E1Ch 3E1Fh Extended Pattern Buffer (CPGC_DPAT_EXTBUF[7])—Offset 3E1Ch AAAAAAAAh

3E20h 3E23h Extended Pattern Buffer (CPGC_DPAT_EXTBUF[8])—Offset 3E20h AAAAAAAAh

3E24h 3E27h Extended Pattern Buffer (CPGC_DPAT_EXTBUF[9])—Offset 3E24h AAAAAAAAh

3E28h 3E2Bh Extended Pattern Buffer (CPGC_DPAT_EXTBUF[10])—Offset 3E28h AAAAAAAAh

3E2Ch 3E2Fh Extended Pattern Buffer (CPGC_DPAT_EXTBUF[11])—Offset 3E2Ch AAAAAAAAh

3E30h 3E33h Extended Pattern Buffer (CPGC_DPAT_EXTBUF[12])—Offset 3E30h AAAAAAAAh

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Table 5-11. Summary of cpgc_t_submap Registers (Continued)
Offset Offset Default
Register Name (ID)—Offset
Start End Value

3E34h 3E37h Extended Pattern Buffer (CPGC_DPAT_EXTBUF[13])—Offset 3E34h AAAAAAAAh

3E38h 3E3Bh Extended Pattern Buffer (CPGC_DPAT_EXTBUF[14])—Offset 3E38h AAAAAAAAh

3E3Ch 3E3Fh Extended Pattern Buffer (CPGC_DPAT_EXTBUF[15])—Offset 3E3Ch AAAAAAAAh

3E40h 3E43h Error Checker Control (CPGC_ERR_CTL)—Offset 3E40h 0h

3E44h 3E47h Lane Error Mask Lower Bytes (CPGC_ERR_LNEN_LO)—Offset 3E44h 0h

Lane Error Mask Upper Bytes or Extended Chunk Enable

3E48h 3E4Bh 0h
(CPGC_ERR_LNEN_HI)—Offset 3E48h

3E4Ch 3E4Fh Lane Error Mask ECC (CPGC_ERR_XLNEN)—Offset 3E4Ch FFh

3E50h 3E53h Lane Error Status Lower Bytes (CPGC_ERR_STAT03)—Offset 3E50h 0h

Lane Error Status Upper Bytes or Extended Chunk Error Status

3E54h 3E57h 0h
(CPGC_ERR_STAT47)—Offset 3E54h

ECC Lane Error Status (CPGC_ERR_ECC_CHNK_RANK_STAT)—Offset

3E58h 3E5Bh 0h
3E58h

ByteGroup Error Status (CPGC_ERR_BYTE_NTH_PAR_STAT)—Offset

3E5Ch 3E5Fh 0h
3E5Ch

3E60h 3E63h Error Counter Control (CPGC_ERR_CNTRCTL[0])—Offset 3E60h 0h

3E64h 3E67h Error Counter Control (CPGC_ERR_CNTRCTL[1])—Offset 3E64h 0h

3E68h 3E6Bh Error Counter Control (CPGC_ERR_CNTRCTL[2])—Offset 3E68h 0h

3E6Ch 3E6Fh Error Counter Control (CPGC_ERR_CNTRCTL[3])—Offset 3E6Ch 0h

3E70h 3E73h Error Counter Control (CPGC_ERR_CNTRCTL[4])—Offset 3E70h 0h

3E74h 3E77h Error Counter Control (CPGC_ERR_CNTRCTL[5])—Offset 3E74h 0h

3E78h 3E7Bh Error Counter Control (CPGC_ERR_CNTRCTL[6])—Offset 3E78h 0h

3E7Ch 3E7Fh Error Counter Control (CPGC_ERR_CNTRCTL[7])—Offset 3E7Ch 0h

3E80h 3E83h Error Counter Control (CPGC_ERR_CNTRCTL[8])—Offset 3E80h 0h

3E84h 3E87h Error Counter (CPGC_ERR_CNTR[0])—Offset 3E84h 0h

3E88h 3E8Bh Error Counter (CPGC_ERR_CNTR[1])—Offset 3E88h 0h

3E8Ch 3E8Fh Error Counter (CPGC_ERR_CNTR[2])—Offset 3E8Ch 0h

3E90h 3E93h Error Counter (CPGC_ERR_CNTR[3])—Offset 3E90h 0h

3E94h 3E97h Error Counter (CPGC_ERR_CNTR[4])—Offset 3E94h 0h

3E98h 3E9Bh Error Counter (CPGC_ERR_CNTR[5])—Offset 3E98h 0h

3E9Ch 3E9Fh Error Counter (CPGC_ERR_CNTR[6])—Offset 3E9Ch 0h

3EA0h 3EA3h Error Counter (CPGC_ERR_CNTR[7])—Offset 3EA0h 0h

3EA4h 3EA7h Error Counter (CPGC_ERR_CNTR[8])—Offset 3EA4h 0h

3EA8h 3EABh Error Counter Overflow (CPGC_ERR_CNTR_OV)—Offset 3EA8h 0h

3EACh 3EAFh Error Log Control and Status (CPGC_ERRLOG_CTL_STAT)—Offset 3EACh 0h

3EB0h 3EB3h Error Log Data Access (CPGC_ERRLOG_DATA)—Offset 3EB0h 0h

3EB4h 3EB7h Loopback Error Status (CPGC_ERR_TEST_ERR_STAT)—Offset 3EB4h 0h

Rank Logical To Physical Map (CPGC_SEQ_RANK_L2P_MAPPING)—Offset

3EB8h 3EBBh 76543210h
3EB8h

Bank Logical to Physical Map Low

3EBCh 3EBFh 76543210h
(CPGC_SEQ_BANK_L2P_MAPPING_A)—Offset 3EBCh

Bank Logical to Physical Map High

3EC0h 3EC3h FEDCBA98h
(CPGC_SEQ_BANK_L2P_MAPPING_B)—Offset 3EC0h

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Table 5-11. Summary of cpgc_t_submap Registers (Continued)
Offset Offset Default
Register Name (ID)—Offset
Start End Value

Rank Address Swizzle (CPGC_SEQ_RANK_ADDR_SWIZZLE)—Offset

3EC4h 3EC7h FEDCh
3EC4h

Bank Address Swizzle (CPGC_SEQ_BANK_ADDR_SWIZZLE)—Offset

3EC8h 3ECBh DEB38h
3EC8h

Row Address Swizzle Low (CPGC_SEQ_ROW_ADDR_SWIZZLE_A)—Offset

3ECCh 3ECFh A418820h
3ECCh

Row Address Swizzle Mid (CPGC_SEQ_ROW_ADDR_SWIZZLE_B)—Offset

3ED0h 3ED3h 16A4A0E6h
3ED0h

Row Address Swizzle High (CPGC_SEQ_ROW_ADDR_SWIZZLE_C)—

3ED4h 3ED7h 2307B9ACh
Offset 3ED4h

3ED8h 3EDBh Row Address XOR (CPGC_SEQ_ROW_ADDR_SWIZZLE_X)—Offset 3ED8h FFFFFh

Column Address Swizzle Low (CPGC_SEQ_COL_ADDR_SWIZZLE_A)—

3EDCh 3EDFh 65432100h
Offset 3EDCh

Column Address Swizzle High (CPGC_SEQ_COL_ADDR_SWIZZLE_B)—

3EE0h 3EE3h 87h
Offset 3EE0h

DQ Inversion Lookup Data Low (CPGC_SEQ_ROW_ADDR_DQ_MAP0)—

3EE8h 3EEBh 0h
Offset 3EE8h

DQ Inversion Lookup Data High (CPGC_SEQ_ROW_ADDR_DQ_MAP1)—

3EECh 3EEFh 0h
Offset 3EECh

5.12.1 Address Decode Repeats (CPGC2_ADDRESS_CONTROL)—

Offset 3C18h
If Algorithm_Address_#.Bits(6:6) is set to 1, then Address Decode is enabled.

Access Method

Type: MEM Register Device:

(Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1
8 4 0
1 8 4 0 6 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address_Decode_Rotate_Repeats
RSVD

514849 Intel Confidential 779

 Bit Default &
Field Name (ID): Description
Range Access

0h
31:6 Reserved.
RO

Address Decode Repeats

(Address_Decode_Rotate_Repeats): Number of times the
current Address_Instruction will repeat if Address_Decode_Enable
is set (as N-1) (0=1 time).
If for the current Address_Instruction, Address_Decode_Enable is
set, then at the start of that Address_Instruction, initialize the
XOR_Address_Pattern to a single 1 in the LSB of Column Address.
Otherwise, it is initialized to all zero's.
For (Address_Decode_Rotate_Repeat_Current = 0; Current_
Address_Decode_Rotate_Repeat_Current <=
Address_Decode_Rotate_Repeat;
Address_Decode_Rotate_Repeat_Current ++)
0h
5:0 Execute the entire Algorithm (Block Traversal,
RW
Algorithm_Instruction, Commands) with the following behavior:
At the end of each complete Block Traversal, rotate the XOR
Address Pattern 1 bit position from LSB to MSB (Column through
Region_Bits_Column, Region_Bits_Row, Region_Num_Banks, and
through Region_Num_Ranks).
Region_Size.Num_Bank and Region_Size.Num_Rank numbers are
converted to the equivalent number of adddress bits to cover their
range (ceil(log2(Num+1))) and should be programmed to a power
of 2 value (minus 1): 1,3,7, or 15.
If only one Rank is being tested, then you should limit the amount
in this register to the sum of the number of address bits without
Rank bits.

5.12.2 Address Instruction

(CPGC2_ADDRESS_INSTRUCTION[0])—Offset 3C1Ch
Address Instruction controlling Address_Order and Address_Direction reversal and
decode rotation/loop.

Access Method

Type: MEM Register Device:

(Size: 8 bits) Function:

Default: 0h

7 4 0

0 0 0 0 0 0 0 0

780 Intel Confidential 514849

 Address_Decode_Enable
Last

Address_Order
Address_Direction
Bit Default &
Field Name (ID): Description
Range Access

Last Address Instruction (Last): If set, then this is the last

Address Instruction and the test will terminate following full
0h
7 execution of this instruction. If there are no Last bits set in the
RW
Address Instruction list, then the test will not stop due to a
completion of the test, but will be an Infinite Test.
Address Decode Enable (Address_Decode_Enable): Enables
rotating XOR of address bits. Used in concert with the
0h
6 Address_Decode_Enable field in the Command_Instruction list.
RW
This bit enables repeating of the current Address_Instruction for
Address_Decode_Rotate_Repeats times.
Address Direction (Address_Direction): Address_Direction
There are 4 basic address directions and their inverse for a total of
8.
Denote this as a combination of a 1-bit field and a 2-bit field.
(0)(00) FastY -North Increment Column and Carry Increment
into Row.
(1)(00) Inv(FastY) - South Decrement Column and Carry
Decrement into Row.
(0)(01) Diagonal North East Increment Row and Column
together and Carry Increment Column into Row.
(1)(01) Inv(Diagonal) South West Decrement Row and
Column together and Carry Decrement Column into Row.
0h (0)(10) FastX South East Decrement Column and Increment
5:3
RW Row and Carry Increment Column into Row.
(1)(10) Inv(FastX) - North West Increment Column and
Decrement Row and Carry Decrement Column into Row.
(0)(11) Diagonal2 - East Increment Row and Carry Increment
into Column.
(1)(11) Inv(Diagonal2) West Decrement Row and Carry
Decrement into Column.
Note that the Bank and Rank Address direction follows the same
as the Column (Increment or Decrement).
Note for diagonal directions, a Carry results in twice the normal
increment/decrement of the Row field.
Incrementing fields start at 0, and Decrementing fields start at
2^(field_block_size)-2^(field_increment)= top of block.

514849 Intel Confidential 781

 Bit Default &
Field Name (ID): Description
Range Access

Address Order (Address_Order): Controls the fastest changing

address field, and how that carries into higher order fields.
000 Rank, Bank, Row/Col.
001 Rank, Row/Col, Bank.
010 Bank, Rank, Row/Col.
011 Bank, Row/Col, Rank.
0h
2:0 100 Row/Col, Rank, Bank.
RW
101 Row/Col, Bank, Rank.
110 Row/Col (Used for Offset) Rank and Bank are unchanged.
111 Row-Col (Used for Stripe Offset) No Carry from any field to
another.
Carry order between Row and Column is dependent on the
Address_Direction field.

5.12.3 Address Instruction

(CPGC2_ADDRESS_INSTRUCTION[1])—Offset 3C1Dh
Address Instruction controlling Address_Order and Address_Direction reversal and
decode rotation/loop.

Access Method

Type: MEM Register Device:

(Size: 8 bits) Function:

Default: 0h

7 4 0

0 0 0 0 0 0 0 0
Address_Decode_Enable
Last

Address_Order
Address_Direction

Bit Default &

Field Name (ID): Description
Range Access

Last Address Instruction (Last): If set, then this is the last

Address Instruction and the test will terminate following full
0h
7 execution of this instruction. If there are no Last bits set in the
RW
Address Instruction list, then the test will not stop due to a
completion of the test, but will be an Infinite Test.

782 Intel Confidential 514849

 Bit Default &
Field Name (ID): Description
Range Access

Address Decode Enable (Address_Decode_Enable): Enables

rotating XOR of address bits. Used in concert with the
0h
6 Address_Decode_Enable field in the Command_Instruction list.
RW
This bit enables repeating of the current Address_Instruction for
Address_Decode_Rotate_Repeats times.
Address Direction (Address_Direction): Address_Direction
There are 4 basic address directions and their inverse for a total of
8.
Denote this as a combination of a 1-bit field and a 2-bit field.
(0)(00) FastY -North Increment Column and Carry Increment
into Row.
(1)(00) Inv(FastY) - South Decrement Column and Carry
Decrement into Row.
(0)(01) Diagonal North East Increment Row and Column
together and Carry Increment Column into Row.
(1)(01) Inv(Diagonal) South West Decrement Row and
Column together and Carry Decrement Column into Row.
0h (0)(10) FastX South East Decrement Column and Increment
5:3
RW Row and Carry Increment Column into Row.
(1)(10) Inv(FastX) - North West Increment Column and
Decrement Row and Carry Decrement Column into Row.
(0)(11) Diagonal2 - East Increment Row and Carry Increment
into Column.
(1)(11) Inv(Diagonal2) West Decrement Row and Carry
Decrement into Column.
Note that the Bank and Rank Address direction follows the same
as the Column (Increment or Decrement).
Note for diagonal directions, a Carry results in twice the normal
increment/decrement of the Row field.
Incrementing fields start at 0, and Decrementing fields start at
2^(field_block_size)-2^(field_increment)= top of block.
Address Order (Address_Order): Controls the fastest changing
address field, and how that carries into higher order fields.
000 Rank, Bank, Row/Col.
001 Rank, Row/Col, Bank.
010 Bank, Rank, Row/Col.
011 Bank, Row/Col, Rank.
0h
2:0 100 Row/Col, Rank, Bank.
RW
101 Row/Col, Bank, Rank.
110 Row/Col (Used for Offset) Rank and Bank are unchanged.
111 Row-Col (Used for Stripe Offset) No Carry from any field to
another.
Carry order between Row and Column is dependent on the
Address_Direction field.

5.12.4 Address Instruction

(CPGC2_ADDRESS_INSTRUCTION[2])—Offset 3C1Eh
Address Instruction controlling Address_Order and Address_Direction reversal and
decode rotation/loop.

514849 Intel Confidential 783

 Access Method

Type: MEM Register Device:

(Size: 8 bits) Function:

Default: 0h

7 4 0

0 0 0 0 0 0 0 0
Last

Address_Direction
Address_Decode_Enable

Address_Order
Bit Default &
Field Name (ID): Description
Range Access

Last Address Instruction (Last): If set, then this is the last

Address Instruction and the test will terminate following full
0h
7 execution of this instruction. If there are no Last bits set in the
RW
Address Instruction list, then the test will not stop due to a
completion of the test, but will be an Infinite Test.
Address Decode Enable (Address_Decode_Enable): Enables
rotating XOR of address bits. Used in concert with the
0h
6 Address_Decode_Enable field in the Command_Instruction list.
RW
This bit enables repeating of the current Address_Instruction for
Address_Decode_Rotate_Repeats times.

784 Intel Confidential 514849

 Bit Default &
Field Name (ID): Description
Range Access

Address Direction (Address_Direction): Address_Direction

There are 4 basic address directions and their inverse for a total of
8.
Denote this as a combination of a 1-bit field and a 2-bit field.
(0)(00) FastY -North Increment Column and Carry Increment
into Row.
(1)(00) Inv(FastY) - South Decrement Column and Carry
Decrement into Row.
(0)(01) Diagonal North East Increment Row and Column
together and Carry Increment Column into Row.
(1)(01) Inv(Diagonal) South West Decrement Row and
Column together and Carry Decrement Column into Row.
0h (0)(10) FastX South East Decrement Column and Increment
5:3
RW Row and Carry Increment Column into Row.
(1)(10) Inv(FastX) - North West Increment Column and
Decrement Row and Carry Decrement Column into Row.
(0)(11) Diagonal2 - East Increment Row and Carry Increment
into Column.
(1)(11) Inv(Diagonal2) West Decrement Row and Carry
Decrement into Column.
Note that the Bank and Rank Address direction follows the same
as the Column (Increment or Decrement).
Note for diagonal directions, a Carry results in twice the normal
increment/decrement of the Row field.
Incrementing fields start at 0, and Decrementing fields start at
2^(field_block_size)-2^(field_increment)= top of block.
Address Order (Address_Order): Controls the fastest changing
address field, and how that carries into higher order fields.
000 Rank, Bank, Row/Col.
001 Rank, Row/Col, Bank.
010 Bank, Rank, Row/Col.
011 Bank, Row/Col, Rank.
0h
2:0 100 Row/Col, Rank, Bank.
RW
101 Row/Col, Bank, Rank.
110 Row/Col (Used for Offset) Rank and Bank are unchanged.
111 Row-Col (Used for Stripe Offset) No Carry from any field to
another.
Carry order between Row and Column is dependent on the
Address_Direction field.

5.12.5 Address Instruction

(CPGC2_ADDRESS_INSTRUCTION[3])—Offset 3C1Fh
Address Instruction controlling Address_Order and Address_Direction reversal and
decode rotation/loop.

Access Method

Type: MEM Register Device:

(Size: 8 bits) Function:

514849 Intel Confidential 785

 Default: 0h

7 4 0

0 0 0 0 0 0 0 0

Address_Decode_Enable
Last

Address_Order
Address_Direction
Bit Default &
Field Name (ID): Description
Range Access

Last Address Instruction (Last): If set, then this is the last

Address Instruction and the test will terminate following full
0h
7 execution of this instruction. If there are no Last bits set in the
RW
Address Instruction list, then the test will not stop due to a
completion of the test, but will be an Infinite Test.
Address Decode Enable (Address_Decode_Enable): Enables
rotating XOR of address bits. Used in concert with the
0h
6 Address_Decode_Enable field in the Command_Instruction list.
RW
This bit enables repeating of the current Address_Instruction for
Address_Decode_Rotate_Repeats times.
Address Direction (Address_Direction): Address_Direction
There are 4 basic address directions and their inverse for a total of
8.
Denote this as a combination of a 1-bit field and a 2-bit field.
(0)(00) FastY -North Increment Column and Carry Increment
into Row.
(1)(00) Inv(FastY) - South Decrement Column and Carry
Decrement into Row.
(0)(01) Diagonal North East Increment Row and Column
together and Carry Increment Column into Row.
(1)(01) Inv(Diagonal) South West Decrement Row and
Column together and Carry Decrement Column into Row.
0h (0)(10) FastX South East Decrement Column and Increment
5:3
RW Row and Carry Increment Column into Row.
(1)(10) Inv(FastX) - North West Increment Column and
Decrement Row and Carry Decrement Column into Row.
(0)(11) Diagonal2 - East Increment Row and Carry Increment
into Column.
(1)(11) Inv(Diagonal2) West Decrement Row and Carry
Decrement into Column.
Note that the Bank and Rank Address direction follows the same
as the Column (Increment or Decrement).
Note for diagonal directions, a Carry results in twice the normal
increment/decrement of the Row field.
Incrementing fields start at 0, and Decrementing fields start at
2^(field_block_size)-2^(field_increment)= top of block.

786 Intel Confidential 514849

 Bit Default &
Field Name (ID): Description
Range Access

Address Order (Address_Order): Controls the fastest changing

address field, and how that carries into higher order fields.
000 Rank, Bank, Row/Col.
001 Rank, Row/Col, Bank.
010 Bank, Rank, Row/Col.
011 Bank, Row/Col, Rank.
0h
2:0 100 Row/Col, Rank, Bank.
RW
101 Row/Col, Bank, Rank.
110 Row/Col (Used for Offset) Rank and Bank are unchanged.
111 Row-Col (Used for Stripe Offset) No Carry from any field to
another.
Carry order between Row and Column is dependent on the
Address_Direction field.

5.12.6 Data Instruction (CPGC2_DATA_INSTRUCTION[0])—

Offset 3C20h
Data Instruction controlling Alternate Data rotation, Background inversion pattern and
Data Inversion.

Access Method

Type: MEM Register Device:

(Size: 8 bits) Function:

Default: 0h

7 4 0

0 0 0 0 0 0 0 0
Data_Select_Rotation_Enable
Last

Invert_Data

Data_Background

RSVD

Bit Default &

Field Name (ID): Description
Range Access

Last Data Instruction (Last): Last Data_Instruction indication,

0h execution is continued at Data_Instruction[0] if the test does not
7
RW otherwise terminate. This bit is implied to be set for
Data_Instruction[3].

514849 Intel Confidential 787

 Bit Default &
Field Name (ID): Description
Range Access

Invert Data (Invert_Data): Globally Invert all data. Combined

0h with the Algorithm_Instruction Invert_Data field, and the
6
RW Command_Instruction or Offset_Command_Instruction
Invert_Data field to determine the final data polarity.
Data Background (Data_Background): 00 - Solid
0h 01 - Column Stripes
5:4
RW 10 - Row Stripes
11 - Checkerboard
Data Select Rotate Enable (Data_Select_Rotation_Enable):
Enables rotating lane pattern data. Used in concert with the
Data_Select_Rotation_Enable field in the Data_Instruction list.
This bit enables repeating of the current Data_Instruction for
Data_Select_Rotation_Repeat times.
0h
3 Data generated using the advanced pattern generation will rotate
RW
by one data bit (LSB toward MSB) for each
Data_Select_Rotation_Repeat.
For the purpose of this shift, the order follows the
Address_Instruction Address_Order and the
Algorithm_Instruction[0] Address_Direction.
0h
2:0 Reserved.
RO

5.12.7 Data Instruction (CPGC2_DATA_INSTRUCTION[1])—

Offset 3C21h
Data Instruction controlling Alternate Data rotation, Background inversion pattern and
Data Inversion.

Access Method

Type: MEM Register Device:

(Size: 8 bits) Function:

Default: 0h

7 4 0

0 0 0 0 0 0 0 0
Data_Background

Data_Select_Rotation_Enable
Invert_Data
Last

RSVD

788 Intel Confidential 514849

 Bit Default &
Field Name (ID): Description
Range Access

Last Data Instruction (Last): Last Data_Instruction indication,

0h execution is continued at Data_Instruction[0] if the test does not
7
RW otherwise terminate. This bit is implied to be set for
Data_Instruction[3].
Invert Data (Invert_Data): Globally Invert all data. Combined
0h with the Algorithm_Instruction Invert_Data field, and the
6
RW Command_Instruction or Offset_Command_Instruction
Invert_Data field to determine the final data polarity.
Data Background (Data_Background): 00 - Solid
0h 01 - Column Stripes