PowerSI Workshop Lab Instructions

Sigrity PowerSI Workshop
Rapid Adoption Kit (RAK)
Product Version: Allegro 17.4 Platform; Release Sigrity 2019

July 2020
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Sigrity PowerSI Workshop: RAK
Contents
Purpose ....................................................................................................................... 4
Audience ...................................................................................................................... 4
Overview ...................................................................................................................... 4
Module 1: Accessing PowerSI from Allegro ................................................................. 5
Introduction .............................................................................................................. 5
PowerSI Model Extraction ........................................................................................ 6
Module 2: Port Resolution in PowerSI ....................................................................... 21
Introduction ............................................................................................................ 21
PowerSI Setup Using Net-Based Ports .................................................................. 22
PowerSI Setup Using Pin-Based Ports .................................................................. 34
Impact of Special Voids on Impedance Calculations.............................................. 40
Module 3: PDN/Signal Model Extraction with PowerSI .............................................. 46
Introduction ............................................................................................................ 46
Launching PowerSI ................................................................................................ 47
Power-Aware PCB Model Extraction Setup ........................................................... 50
Updating the Decoupling Capacitor Models ........................................................... 72
Module 4: PDN Resonance Analysis with PowerSI Spatial Mode ............................. 84
Introduction ............................................................................................................ 84
Simulation Setup .................................................................................................... 85
Simulation Results ................................................................................................. 90
Module 5 (Optional): Compact Model Extraction with Broadband Spice.................... 95
Introduction ............................................................................................................ 95
Launching Broadband Spice .................................................................................. 96
Setup Extraction Options ....................................................................................... 98
Begin Spice Model Extraction ................................................................................ 98
Importing Broadband Spice Model into Topology Explorer .................................. 101
Checking Analysis Options .................................................................................. 103
Running Bus Simulation ....................................................................................... 104
Module 6 (Optional): Multi-Structure Simulation in PowerSI .................................... 108
Introduction .......................................................................................................... 108
Multi-Structure Workspace Setup......................................................................... 108
Support .................................................................................................................... 109
Feedback ................................................................................................................. 109

Purpose
The purpose of this RAK is to demonstrate how to use Allegro Sigrity PowerSI to
overcome power, signal, and EMI issues in integrated circuit (IC) packages and printed
circuit boards (PCBs).
Audience
This document is intended for designers who wish to use Sigrity PowerSI for fast,
accurate, and detailed electrical analysis of full IC packages or PCBs.
Overview
Allegro Sigrity PowerSI provides fast and accurate full-wave electrical analysis of IC
packages and PCBs to help overcome increasingly challenging and interrelated power,
signal, and EMI issues. A broad range of studies can be readily performed with PowerSI
to identify issues such as trace and via coupling, power/ground bounce caused by
simultaneously switching outputs, and to identify design regions that are under or over
voltage targets. PowerSI supports extraction of frequency-dependent network
parameter models and enables visualization of complex spatial relationships.
The following modules are included in this RAK:
• Module 1: Accessing PowerSI from Allegro
• Module 2: Port Resolution in PowerSI
• Module 3: PDN/Signal Model Extraction with PowerSI
• Module 4: PDN Resonance Analysis with PowerSI Spatial Mode
• Module 5: Compact Model Extraction with Broadband Spice
• Module 6: Multi-Structure Simulation in PowerSI

Module 1: Accessing PowerSI from Allegro

This module covers the following:
• Overview of PowerSI and Allegro Sigrity SI
• Launching PSI from Allegro Sigrity SI
• Model extraction setup and simulation in PSI
• Incremental layout update and re-simulation
Introduction
As part of Allegro Sigrity SI with Power-Aware SI Option or Serial Link SI Option,
PowerSI can be launched directly from Allegro’s popular PCB, IC package, and system-
in-package (SiP) design environments.
This module will illustrate the procedure for accessing PowerSI from Allegro Sigrity SI.
The internal translator is used to push the design from Allegro into PowerSI. Once the
PowerSI simulation setup is completed, the incremental layout update function is used
to make layout modifications on the Allegro side and push the changes to PowerSI for
re-simulation using a single mouse click.

PowerSI Model Extraction

PowerSI can be launched directly from Allegro/SiP Analyze menu when the Allegro
Sigrity SI or PI editor is selected (see figure below). The SI or PI editor can be selected
by choosing either the Allegro Sigrity SI or PI, which are part of the Sigrity2019
installation. Alternatively, you can select PCB Editor, APD or SiP, in the Allegro
installation and change the default editor to Allegro Sigrity SI or PI. When accessing
PowerSI from the Analyze menu, the layout is pushed into PowerSI using the internal
SPD translator SPDIF. Various translation preferences can be specified during this
stage. Users can also choose to either translate the entire design or a subset of the
XNets on the layout. Once PowerSI is launched, the layout can be modified on the
Allegro side and changes passed to the PowerSI side using the incremental layout
update functionality. This lab will cover the launching of PowerSI from SI, simulation
setup using PowerSI Model Extraction workflow, and incremental layout update and re-
simulation.

To run PowerSI analysis from the SI:
1. Click Start > All Programs > Cadence PCB 17.4-2019 > Signal Integrity 17.4.
Then, select “Allegro Sigrity SI (for package)” in the product list and check the
box before the product option “Power-Aware SI”.
2. From the Allegro Sigrity SI menu, select File > Open and load the package design
inc_update_rev1.mcm located in the Module1 folder of the workshop. Click Yes
to continue if you get a warning message.

3. Once the .mcm file is loaded in the SI base, select Analyze > PowerSI to load the
layout into PowerSI.
4. The XNet Selection window will open. Click on Preferences and select None for
Create bumps for mcm/sip design:
5. Click Ok to close the SPDIF Preferences window.

6. On the Xnet Selection window select Entire Design and click OK to translate the
database and load it into PowerSI.

7. You should see a window like the one shown below.

8. We are only going to extract a differential pair (TXDATA0+/TXDATA0-), located on

the upper-left corner of the package. On the lower-right corner of the PowerSI
window, select the Net Manager tab. Right-Mouse Click (RMC) in the Net List
window and select Disable All Nets.

9. In the Net Manager, enable nets VSS and TXDATA0-/TXDATA0+. At the bottom
of the Net Manager, select “Keep shape enabled when the net is disabled”.
The Net Manager window should now look like the figure below.
10. Next, we are going to define ports on the die and BGA ends of the nets. In the
Workflow pane (the pane on the left), select Generate Port(s). Keep the default
selection “Automatic port definition based on enabled nets” and click Next.

11. Again, select the default setting “Define ports on the components that are not
included in the simulation” and click Finish. Click OK to close the pop-up
window which indicates that the ports are generated from two components.
The Port window should open as shown below. Note that there are four ports, two
created on the die (FCHIP) side and the other two on the PCB (BGA) side of the
nets.

12. Next, we are going to specify the extraction frequency range. In the Workflow
pane, select Setup Simulation Frequencies. In the “Frequency Ranges”
window, change Ending Freq. to 12GHz. Click OK to close the Frequency
Ranges window.
13. In the Workflow pane, click Start Simulation. The simulation should take only a
few seconds to complete.
14. In the Network Parameters window, select the result S0-SIMULATION. Next,
select the Channel Filter icon as shown below.

15. In the Channel Filter window, unselect Return Loss and select Insertion Loss
as shown below. Click OK to close the window.
In the plot window, RMC and select Show Y-axis in log scale.
16. The insertion plot results should be like the results shown below.

17. Click on the S0-SIMULATION result again to select it. RMC and select Save As.
18. Save the results in the file inc_update_rev1.bnp as shown below. The folder
path may be different in your setup.

Optional Lab
19. Next, we are going to make layout changes on the Allegro side and use the
incremental layout update option in SI to update the PowerSI layout for quick re-
simulation. Leave the PowerSI window open. Go back to the Allegro SI window
which should still be open on the desktop. Ensure that the layer visibility is set as
shown below.
20. From the menu, select Shape > Select Shape or Void/Cavity.
21. In the upper-left corner of the layout, Left-Mouse Click (LMC) on the leftmost
edge of the VSS shape. LMC again and hold down the mouse button and drag the
edge to the left to expand the shape. Try to expand the VSS shape right up the
vias on the edge of the VDD plane as shown below.

22. Go back to the PowerSI window. From the menu, select the 2D View tab to
display the layout window. Click on the Layer Selection tab in the bottom-left
corner. Click on the layer Signal$VDD to select it. Notice that the VSS shape
does not reflect the change made on the Allegro side.
23. Click on the Net Manager tab in the bottom-right corner of the window. Click on
the VSS net in the Net Manager to select it. RMC on the VSS net and select
Update Selected Nets.

24. The VSS shape should now update to reflect the layout changes made on the
Allegro side.
25. The PowerSI setup is still intact; so, we can simply re-run the simulation and
gauge the impact of the layout changes on the results. In the Workflow pane, click
Start Simulation. The simulation should only take a few seconds to complete.

26. Follow steps 13 through 16 to display the insertion loss results in dB (decibel).
You should see results like what is shown below.
27. Next, we are going to load the results from the previous run to compare them with
the new results. RMC in the Network Parameters window and select Load.
28. Select to load the file inc_update_rev1.bnp that was saved in step 17.
29. Highlight the new S1 results just loaded and follow steps 13 through 16 to display
insertion loss.

30. As shown in the figure below, there is a significant improvement in the insertion
loss of the diff pair once the reference plane is extended to cover the trace routing
on the top layer.
31. Based on the designer’s needs, incremental layout updates can be performed
multiple times until the desired electrical performance is achieved.
32. You can now close both PowerSI and Allegro SI without saving the files.

Module 2: Port Resolution in PowerSI

This module covers:
• Overview of port resolution concepts
• PowerSI setup using net-based ports
• PowerSI setup using pin-based ports
• Impact of special void settings in PSI
Introduction
One key step in any field solver setup is port definition. Ports are localized regions
where power is injected into the layout and the transmitted/reflected power is measured.
PowerSI utilizes circuit-based ports, which are like lumped gap ports found in 3D
solvers. However, PowerSI provides a great deal of flexibility regarding how ports are
defined. This makes PowerSI highly suitable for both SI and PI applications, as well as
for model extraction for die-centric or system-centric analysis.
This lab will illustrate how port resolution in PowerSI can be controlled to obtain a model
with the appropriate abstraction level. For example, as shown in the figure below, if a
package model is to be extracted for die-centric analysis, pin-based ports can be
defined on the die side while using net-based port resolution on the BGA side. For most
system-centric analyses, the port resolution will most likely be reversed. Since PowerSI
ports are circuit based, this level of port resolution control is quite easily accomplished.
Ports can be net based, pin based, grid based, or arbitrarily defined. There is also a
great deal of flexibility in how a port reference is specified, including global/local pin-
group referencing or user-defined reference cell(s) or node.
Figure 1: Application-specific port resolution

We are going to start by extracting the model of a single power rail for a sample PCB,
using net-based port resolution. Loop impedance of the PDN will be calculated using
the extracted S-parameters. Next, we will re-extract the model of the power rail using
pin-based port definition. We will then compare the loop impedance of the PDN using
pin-based ports with that of the net-based port approach and discuss the differences
observed. In both cases, we will rely on the Port Wizard to generate the ports
automatically.
PowerSI Setup Using Net-Based Ports

For this lab, we will use a PCB layout that consists of a single power/ground pair. We
will define ports at the VRM (U31) and one IC device (U3). S-parameters will be
extracted from DC to 2GHz. The Port Reduction utility in PowerSI will be used to short
the VRM port and compute the loop Z of the PDN looking into the U3 port.
1. Click Start > All Programs > Cadence Sigrity 2019 > PowerSI.

2. Click Close if the Tip of the Day window opens.

3. In the Sigrity Suite window click on File – New and choose PowerSI and Model
Extraction:
4. In the Model Extraction workflow on the left side of the window, select Load
Layout File.
5. Select the file 1P5V_PDN.spd in the folder Module2 and click Open.

Your PowerSI canvas should look like the figure below:
6. Only the +1_5V and GND nets have been translated for this lab. If you select the
Net Manager tab in the bottom-right corner, you should see that both power and
ground nets are appropriately classified and enabled (as shown below).

7. In the Workflow pane, select Generate Port(s). On the first page of the Port Setup
Wizard, keep the default setting and click Next.
8. On the second page of the Port Setup Wizard, change the setting to “Define
ports on the selected components only”. DO NOT click Finish yet.
9. The Component Manager should be open on the right side of the PowerSI
window as shown below.

10. LMC on the RefDes column heading twice to sort the column values in
descending order. The window should now appear as shown below.

11. We want to highlight only two components: U3 and U18. Scroll down the list until
you can see both U18 and U3. Click on U18 to select it. Hold down the Ctrl key
and select U3. Your Component Manager selection should look like as shown in
the figure below.
12. Now that we have selected the appropriate components, click Finish in the Port
Setup Wizard which is still open towards the left side of the canvas.
13. A pop-up window should open as shown below. Click OK to close it.

14. The Port window should now open as shown below. There are two ports defined.
Click on a port to have it displayed on the layout. The port for component U3 is
defined on the bottom layer of the PCB; you will need to change the layer to
Signal$BOTTOM to get a better view of it. You can use the Layer Selection tab
on the bottom right to change layers.
Note: The procedure we used to generate ports uses net-based port definitions by
default. If you expand the port definition in the Port window, you can clearly see that all
the power pins of the component are used as the positive pins of the port and all the
ground pins of the component are selected as the negative pins of the port.
You can now close the Port window by clicking on the x in the upper-right corner of the
window.
15. In the Workflow pane, click Setup Simulation Frequencies. The Frequency
Ranges window should open as shown below. Do not change the setting. Click
OK to close.

16. In the Workflow pane, click Start Simulation. If a warning message related to via
overlap detection is displayed click on Yes to continue with simulation. It should
complete within 2 minutes.
17. After the simulation completes and the results are generated, choose to view the
Z parameters in the plot window.
18. RMC in the plot window and change the X-axis scale to log. Repeat that to
change the Y-axis scale to log as well.

19. You should get a plot like the one shown below. This is the open-circuit
impedance response of the PDN looking into the two ports defined.
20. Next, we are going to short the VRM port to obtain the loop impedance response
of the PDN looking into the U3 port. In the Network Parameters window, select
Z0 – SIMULATION.

21. RMC and select Matrix Operations > Reduction. If you get a popup about AFS
data format, click Yes to proceed.
22. In the Port Reduction window, change the connection status for the U18 port to
Short. Click OK to close the window.

23. In addition to the original Z0 database, there should now be a Z1 database in the
Network Parameters window, representing the results with the reduction
operation applied. Click on the Z0 curve colors to hide them. Once again, RMC in
the plot window to convert the X-axis and Y-axis to log scale. You should get the
loop impedance of the PDN looking into the U3 port as shown below. The low
frequency impedance is on the order of 27mohms. There are also multiple
resonance peaks from around 74MHz up to 2GHz.

24. Next, we will attempt to repeat this simulation by defining pin-based ports at U3
and see how the low frequency impedance and the resonance frequency change.
However, before we redefine the ports, we need to save the net-based port
results to compare them with the pin-based results. Select the Z1 database in the
Network Parameters window. RMC and select Save As.
25. Click on the … button to the right of the Save As field to change the name of the
file. Type in net_based_Z for the file name and click Save. We will reload this file
later to compare it with the pin-based results to be generated next.

PowerSI Setup Using Pin-Based Ports

We are going to return to the setup, delete the net-based ports for U3, and redefine new
pin-based ports for the device. We will not change the port definition for the VRM (U18),
as that component only has a single power pin; so, the net-based and pin-based port
definitions will not be different.
26. Switch back to the layout window by clicking on the 2D View tab.
27. From the menu, select Setup > Port.

28. When the Port window opens, delete the port for component U3, as shown
below:
29. Using the Layer Selection tab, switch to layer Signal$BOTTOM and zoom in
around component U3. In the Port window, select the Pin Based tab in the
middle of the window. Select RefDes U3 from the list (you can sort the list for
faster access). Set up the port definition as shown below by following the four
simple steps. Basically, pins are grouped using a 6x6 grid, which, in this case,
places each power pin in its own unique cell. For port reference, we are going to
use the GND pins located in the same cell as the power pin. We can also select a
reference cell or pin to act as the reference pin for all ports. Click on Generate
Ports to create pin-based ports for U3.

This time, six ports are generated for U3 instead of the one in the net-based
setup. You can review the ports by selecting them in the Port window and viewing
the port pins on the layout. The Port window should look like as shown below:
Close the Port window once you are done reviewing the ports.
30. In the Workflow pane, select Start Simulation. If a warning message related to
via overlap detection is displayed click on Yes to continue with simulation. The
simulation should complete within 2 minutes.

31. Once the simulation is completed, repeat steps 17 through 23 to display the
open-circuit and short-circuit Z responses. In this case, we have seven ports for
open-circuit Z response. We are still going to short the port at U18 to generate the
short-circuit Z response; however, in this case, we have six observation points
rather than one. The open-circuit and short-circuit Z responses should be like as
shown below. When repeating step 23, save the new data in a file called
pin_based_Z.BNP.

32. Next, we are going to load the short-circuit Z response we saved in the net-based
simulation. RMC in the Network Parameters window and select Load. Load the
file net_based_Z.BNP that was previously saved.
33. The net-based results should load into database Z2. Select Z2 and change the
property to the settings shown below by doing an RMC on Z2[1,1] and click on
Property. This is to clearly separate the graph from the pin-based results.
34. Adjust the x/y scales by using the enlarge/reduce buttons. You can clearly see
that the net-based plot and the pin-based plots all have their resonances at the
same frequencies. The amplitude of the resonances can vary greatly between
net-based results and some of the pin-based observation points. However, since
the resonance frequency is a function of the structural dimensions and the
loading, the resonance frequencies are always the same.

35. Next, zoom in on the low frequency end of the band. Two points to observe here
are as follows:
a.) The net-based loop Z is lower than all the pin-based observation points. The
reason for this has to do with how the circuit ports are defined in PowerSI.
When a port has multiple positive and multiple negative nodes, all the positive
nodes are equal potential and all the negative nodes are also equal potential.
This is equivalent to using a copper foil to short all the power pins together and
all the ground pins together. This, in effect, reduces the loop impedance to be
at or lower than the shortest path to the VRM. This can easily be observed
with the results.
b.) In the pin-based case, some of the observation points have low-frequency loop
Z at around 30mohm and some have a loop Z closer to 40mohms. Reviewing
the layout, there is no significant difference in the return path for the different
observation points. However, as shown in the figure below, there is a
significant difference in the signal (power) path between ports 2, 3, 4 and ports
5, 6, 7. The first three ports of U3 all have the signal path going through a
narrow trace that significantly increases the series R and L of the loop. Clearly,
a good PDN design should avoid such routing since decoupling capacitors will
not be able to overcome this degraded response at the low end of the
frequency band. PowerSI can help designers quickly isolate such design
problems.
Do not close PowerSI; we are going to reuse the setup in the next section.

Impact of Special Voids on Impedance Calculations

PowerSI is a hybrid solver, which means that a combination of field, transmission line,
and circuit simulators are utilized along with domain decomposition to extract AC
models of entire PCBs or IC packages, without requiring significant computational
resources. For the algorithms to work effectively, assumptions are made, and specific
setups are required which are unique to the tool. For example, for signal traces, the
user must specify % coupling and rise-time parameters, which are then used to
calculate which trace-to-trace coupling should be included in the analysis (the default
settings in the tool are 2% and 100ps, respectively). These parameters have a direct
impact on the computation cost of the analysis. For instance, if you are extracting 1000
nets on a large PCB, most nets are too far apart to have significant coupling. The ability
to ignore the week coupling between far-apart nets can significantly reduce the
computational cost of calculating trace-to-trace coupling in such a case.

Another set of parameters that can be controlled by the user are special voids. Special
voids are a specific way in which the solver handles various perforations on the planes
(shapes) of the layout. These perforations include via anti-pads, thermal holes, dog
legs, and small holes. The user can specify a value for each one of these parameters.
Holes smaller in diameter than the set value will be filled up during analysis. Again,
since PowerSI is a hybrid solver, the filling of the special voids does not mean that the
problem is changed electrically by shorting vias to the planes, for example. In the case
of anti-pads, special voids are handled by filling the hole for the field domain portion of
the calculation (calculations of fields between two adjacent planes). It is also assumed
that the holes are filled when calculating the impedance of vias and breakout traces, but
the via will not be electrically shorted to the plane in the simulation.
There are two main reasons for incorporating special voids into the solver:
• It helps control the size and complexity of the problem. If you are extracting the
model of a large board with many power/GND planes that are highly perforated, a
great deal of computational resource is required to model each hole in every
plane layer. If the results are not greatly impacted by ignoring the small holes, you
can arrive at reasonably accurate results much faster. In fact, for most PCBs, this
assumption is generally accurate.
• Since PowerSI does not apply a full 3D field solver to the calculation of every via
structure and its associated breakout traces, filling the holes provides references
for the impedance calculation which results in a much more accurate model of the
via. So, for most applications, it is best to set the special void size to the diameter
of the largest anti-pad in the design.
To better understand when special voids are important for accurate via modeling, refer
to the figure below. In the case of buried vias, you can ignore special voids (set it to a
small value). A buried via is generally going to be contained within the field domain,
which means that there is a plane covering it on top and at the bottom; therefore, the
proper referencing for impedance calculation is provided. In the other two cases,
through hole and blind vias, the via and break out traces are not in the field domain (not
covered on both sides with planes/shapes). Therefore, setting special voids to a value
to fill in the anti-pad holes during calculation will ensure that more accurate results can
be obtained.
Special voids are more critical for SI analysis, since through hole or blind vias are often
employed for signals. For PI analysis, in most instances, special voids can be set to a
small value if more accurate calculation of loop inductance or resistance is desired,
since the power/GND vias generally tend to be in the field domain.

To illustrate the impact of special voids on loop impedance, we are going to re-simulate
the pin-based model extraction of the power rail in the example above. However, this
time, we will set the special void to a small value (0.1mm); so, effectively, each
perforation in the planes is modeled as is. The expectation is that the loop impedance
should increase by a small amount because now, both the signal current path and the
return current path will be slightly altered to get around the perforations, hence,
increasing the inductance and resistance of the loop. Also, there is a slight decrease in
capacitance as a small fraction of the plane metal is removed due to the perforations,
also giving rise to increase in impedance.
Go back to the layout view by selecting the 2D View tab.
36. From the menu, select Tools > Options > Edit Options.
37. When the Options window opens, select Special Void under the Simulation
(Basic) section.
38. Set all the special void parameters to 0.1mm as shown below. We are not going
to set special voids to zero, since there is always the possibility that very small
holes are present on the planes, either due to some inadvertent layout process or
translation issues. Such small holes can make the meshing very memory
intensive; so, to avoid them, we set special void to a small number but not zero.
Click OK to close the Options window.

39. From the menu, select Setup > Port.

40. Ensure that pin-based ports are still defined as was specified in step 27. Close
the Port window once you have verified the port setup.
41. In the Workflow pane, click Start Simulation. If a warning message related to via
overlap detection is displayed click on Yes to continue with simulation. The
simulation should take around 7-8 minutes to run. Note that this is substantially
longer than the previous run as the mesh density is much higher to deal with all
the perforations in the power/ground planes.
42. Once the simulation is completed, repeat steps 17 through 23 to display the
open-circuit and short-circuit Z responses. When repeating step 23, save the new
data in a file called pin_based_SV_0p1_Z.BNP.
43. We can now load the short-circuit Z parameters from the initial run where the
special voids were set to 0.75mm, and then compare the impedance with this new
run. RMC in the Network Parameters window and select Load. Select the file
pin_based_Z.BNP and click Open.
44. Make sure that the plot display is in log-log mode.
Once you have the short-circuit Z response displayed for both 0.1mm and
0.75mm special void settings, notice that there is a small shift in the resonance
frequencies between the two cases. The inclusion of all the perforations has
impacted the structure slightly to shift the high-frequency resonances. This is not
too critical from the PDN design point of view, since the decoupling caps on the
PCB do not work at such high frequencies due to large loop inductance.

45. Next, focus on the response at the low end of the frequency band. As expected,
the impedance has increased for all observation points, since the current must get
around the various perforations, increasing the overall loop distance. However,
again, the differences are not very significant. In some applications, such as
mobile platforms, the differences may be more significant due to small size of the
planes and highly perforated nature of the planes.
This concludes the module. You can now close PowerSI.

Module 3: PDN/Signal Model Extraction with PowerSI

This module covers:
• Accessing PowerSI from Allegro PI
• Power-aware PCB model extraction
• S-parameter and input impedance analysis
• Decoupling capacitor model assignment
Introduction
PowerSI provides fast and accurate full-wave electrical analysis of IC packages and
PCBs to help overcome increasingly challenging and interrelated power, signal, and
EMI issues. A broad range of studies can be readily performed with PowerSI to identify
issues such as trace and via coupling, power/ground bounce caused by simultaneously
switching outputs, and to identify design regions that are under or over voltage targets.
PowerSI supports extraction of frequency-dependent network parameter models and
enables visualization of complex spatial relationships. Now, as part of Allegro Sigrity PI
with PI Sign-off and Optimization Option, PowerSI can be launched directly from
Allegro’s popular PCB, IC package, and SiP design environments.
In this lab, PowerSI will be used to extract the Broadband S-parameter model of a DDR
interface. The extraction will include both power distribution systems including a byte
lane of a data bus as well as a segment of an address bus. We will extract S-
parameters of the board with and without decoupling capacitors to observe the impact
of the decaps on the PDN AC response.

Launching PowerSI
We are first going to cover the procedure on how to load a layout .brd file into Allegro PI
and launch PowerSI. Module 1 covered the process of accessing PowerSI from Allegro
SI and using the incremental layout update functionality to assess the impact of layout
changes on signal integrity. Here, we are going to only cover the steps required to
access PowerSI from Allegro PI. However, the incremental layout update functionality
can also be used in Allegro PI to explore the impact of layout changes on power
integrity, although it is not covered here.
1. Click Start > All Programs > Cadence PCB 17.4-2019 > Power Integrity 17.4.
2. In the Product Choices window, choose Allegro Sigrity PI (for board) and check
the box next to the PI Signoff & Optimization option. Click OK to open Allegro.

3. Within Allegro, open the file Viper_PDN_PSI.brd located in the Module3 folder.
4. Once the .brd file is loaded in Allegro PI, select Analyze > PowerSI to invoke the
internal translator and launch PowerSI.

5. The XNet Selection window will open. Here, select Entire Design and click OK to
translate the database and load it into PowerSI.
6. PowerSI will launch, and the translated layout will be loaded as shown below. If the
Tip of the Day window opens, click OK to close it.
This is a brief demonstration of the Allegro PI and PowerSI integration. The integration
automated the layout database exchange between the two environments. There is also
the ability to perform incremental layout updates without the need to re-translate or redo

simulation setup. This was covered in Module 1 for Allegro SI. Further integration will be
added in future versions of the tool. There are just a few steps required now to complete
the setup for S-parameter extraction and run the simulation.
Since the board is large and we are only interested in extracting S-parameters for a
small segment of the design, we are going to now load an existing .spd file that is a cut
version of the original layout we just opened. The smaller .spd file will help reduce
simulation time and make the lab easier to follow.
Power-Aware PCB Model Extraction Setup

This section will go through the setup steps for model extraction with PowerSI.
7. With the PowerSI still open, select File > Open from the pull-down menu. Select
Viper_PDN_PSI.spd in the Module3 folder.
8. If you are not able to locate Viper_PDN_PSI.spd but can see
Viper_PDN_PSI.spd.bak in Windows Explorer, rename it to Viper_PDN_PSI.spd
and load it in PowerSI.
9. If you get a message asking to save the current project, select No.
10. After the layout is loaded, under View > Show, turn items on or off to match the
settings below.
11. In the Layer Selection windowpane on the far right of the main window, you can
LMC on the layer name text (NOT the eye icon) to change the active layer.

You can go through the layers as desired to get familiar with the stackup and routing.
The byte lane of data bus we are extracting is routed mainly on layer Signal$SIG_15V.
We are also going to extract a few nets from the address bus located on layer
Signal$SIG_16V. The address bus does not have as good a reference as the data bus;
we will illustrate this after the extraction is completed.
12. At the bottom of the Layer Selection windowpane, you can clear the check on
View Only Active Layer and disable Show Shapes. This will show all layers
without shapes.
Signals to be extracted are routed between the components U1 and XP1. VRMs of
interest for this extraction are the components U32, U14, U15, U16, U18, and U19.

13. At the bottom of the Layer Selection windowpane, check View Only Active
Layer and enable Show Shapes. This returns the GUI back to the typical view
settings.
14. In the Workflow pane towards the left, click Check Stackup.

15. Inside the Stackup window, change units to mils using the drop-down selector at
the bottom right of the window.
16. Use LMC and Ctrl-LMC to select the thicknesses for Medium$44, Medium$46,
Medium$70, and Medium$72 (use LMC to select the first layer and Ctrl-LMC to
select the subsequent layers).
17. Enter 7 in the Thickness text box at the bottom. This will update all four
thicknesses.
18. Click Apply.

19. Once you have reviewed the stackup, click OK to close the window.
20. In the Workflow pane, click Select Nets.
21. A pop-up window will appear. Select Setup P/G nets.
22. The P/G nets classification wizard will open. On the first page, select the
components U1 and XP1. Click Next.
23. The power and GND nets associated with the selected components will be
displayed on page 2 of the wizard, as shown below. Click Next.

24. On page 3 of the wizard, LMC to select the first power net, and then hold down
the Shift key and select the last power net. LMC on the E symbol on the right
corner of one of the Pairing P/G Net fields and select GND from the drop-down
menu (the E symbol appears once you move your mouse over the field). Click
Finish.
25. The Net Manager will appear on the right side of the canvas. At the top right of
the Net Manager, click the drop-down arrow and select Show Coupled Line from
the menu.
26. RMC anywhere in the spreadsheet area of the Net Manager and select Disable
All Nets. Note that you can still see the planes in the layout on layers with planes.

27. At the bottom of the Net Manager, clear the check for Keep shape enabled
when the net is disabled and check Hide Disabled. Make sure it looks like as
shown below.
28. Enable the following nets by checking the boxes next to their names (you can use
LMC and Ctrl-LMC to select multiple nets simultaneously; you can also use the
Search utility at the top of the Net Manager pane to look for net names):
• +0_75V
• +1V
• +1_2V
• +1_5V
• +1_8V
• +2_5V
• GND
• XP1_DDR3_DQ<0> through <7>
• XP1_DDR3_DM<0>

• XP1_DDR3_DQS0_N
• XP1_DDR3_DQS0_P
• XP1_DDR3_BA<2>
• XP1_DDR3_CKE0
• XP1_DDR3_CKE1
• XP1_DDR3_S1
• XP1_DDR3_ODT1
29. Change the power and ground net display colors by doing an LMC on the colored
square next to the net name. This is typically done to make it easier to identify a
shape’s identity; it does not impact simulation results. Use dark green for the GND
net as shown below.
30. Click on the Net List column header near the top of the Net Manager pane
multiple times until you get Sort enabled first as shown below. This will bring all
enabled signal nets to the top of the list.

31. Highlight the first enabled signal net with LMC. Then, group-select all enabled
signal nets with Shift-LMC. Then, RMC anywhere in the blue highlighted area and
select Set with Default Parameters. You will see the coupling percentage and
rise-time entries filled with 2% and 100ps, if not already set. This will tell the solver
which coupling terms to include in the simulation.
32. In the Workflow pane, LMC on Select Components.
The Component Manager should appear on the far right of the main window.
33. Adjust the width of the Component Manager windowpane and its columns as
desired. Scroll through the list to become familiar with the types of circuits. Make
sure that none of the circuits have a green check mark next to them. The green
check mark indicates that the circuit will participate in the simulation. For a circuit
to get a green check mark, the nets associated with the circuit pins must be
enabled. Also, the model definition for the circuit must be a valid Spice netlist. In
this case, none of the components have a valid Spice model; so, none of the
components should have a green check mark.

34. We are going to manually disable all components so that you can become familiar
with the procedure (although in this instance, it is not necessary). LMC in the
Component Manager pane and press Ctrl-A to select all circuits. RMC anywhere
in the blue highlighted area and then select Disable Selected Components.
Note that all circuits now have a red X next to their name. Now, even if the component
nets are enabled and a correct Spice model is associated with the component, the
circuit will still not participate in the simulation.

35. In the Workflow pane, verify the blue check mark next to Enable Extraction
Mode. If not checked, LMC on Enable Extraction Mode.
36. LMC on Generate Port(s) in the Workflow pane (shown above). The Port Wizard
will appear. Leave the selection as Automatic and click Next at the bottom of the
wizard.
37. Read the explanation of how the Port Wizard works. Change the selection to the
second radio button: Define ports on the selected components only.
Note that the Component Manager, on the right, now displays a subset list of
components. Also, note that the funnel button has been automatically selected by the
Port Wizard.
38. Click the Filter button (shown above) and LMC on By Property.

39. Change the filter to the third choice: with at least 1 enabled power and 1
enabled ground net (make sure option 1 is disabled). Click OK.
40. Notice that the list in the Component Manager changes. Scroll to the bottom of
the list. Use LMC and Shift-LMC to highlight the last eight components in the list
(U1, U14-U16, U18-U19, U32, XP1).
41. Click Finish on the left side of the screen in the Port Wizard. You should see a
confirmation message appear. Click OK to close the Port Wizard and generate
ports.

42. The Port window will appear with 45 ports defined. You can highlight a port name
and see the port location appear in the layout. Note that we have generated net-
based ports in this setup. This means that on all components, when ports are
generated for a given net, all pins of that net are lumped together in defining the
port’s + terminals, and all ground pins of the component are lumped together in
defining the port’s – terminals. In PowerSI, ports can also be defined using pin-
based or grid-based definitions. Close the Port window by doing an LMC on the
X.
43. In the Workflow pane, click Setup Simulation Frequencies.

44. Change the starting frequency to 30KHz and ending frequency to 5GHz. (We will
start at this frequency because later, we may use decap models whose first
frequency point is 30KHz.)
45. Click OK to close the Frequency Ranges window.

46. From the menu, click Tools > Options > Edit Options. Click Special Void under
the Simulation (Basic) section. Make sure that the four special void criteria are
set to 1.5 mm. This is a good default setting for this design.

47. Click on General under the Simulation (Basic) section. Change the maximum
number of CPUs to use in the simulation to “max – 1”. In the figure below, max is
12 (it may be different on your computer); so, we set the value to 11. We want to
take full advantage of multi-threading; however, we also want to leave one core
for other activities.
48. Click Network Parameters under Simulation (Basic). Make sure that Default
Output Format for Network Parameters is set to BNP, and not just
Touchstone.

49. At the bottom of the Options window, select Apply. Then, select Apply to All
Pages.
50. Click OK to close the Options window.
51. From the menu, select File > Save As.
52. Save the file as Viper_PDN_PSI_no_decaps.spd in the Module3 folder.
53. Click Save.
54. Click OK to perform Shape Processing (uncheck Error Checking) if a pop-up
window opens asking for save options.

55. Click Start Simulation in the Workflow pane. If a warning message related to via
overlap detection is displayed click on Yes to continue with simulation.
The simulation will likely take about 10 minutes to complete; so, now would be a good
time for a short break. During the simulation, PowerSI will solve all electrical parasitics
of the PCB structure using a built-in electromagnetic field solver. Using this electrical
model of the PCB, PowerSI will generate the S-parameter for frequencies that span
from 30KHz to 5GHz. The “Output” window will show the simulation progress in real
time. Upon completion of the simulation, the “Output” window will show AFS Finished
(Adaptive Frequency Sweep). Once the simulation is complete, you should see a
network parameter display like the one below.
56. Optional – Close the Output windowpane at the bottom of the screen by doing an
LMC on the X. You may have to do this twice to also close the folder browser.

57. LMC on the S0 – SIMULATION text to highlight it.

58. LMC on the Channel Filter toolbar button.
59. Click on All Channels (clear the checkbox) to uncheck all channels.
60. Click on the Channel column header to sort the column values by name.
61. Check the boxes next to the six power nets, as shown below (you may have to
scroll if the channel names are not sorted). Click OK.

62. Use the toolbar pull-down menu to change from S-parameter to Z-parameter
display. This is the open-circuit Z response of the PDNs.
63. RMC in the 2D plot area and change both X- and Y-axis to log scale. You can
only change one axis at a time; so, you will have to RMC twice.

64. To show or hide individual curves, LMC on the color box next to each curve
name. Shown below is the result for +1_2V at the U1 component. Notice the first
two impedance peaks around 219MHz and 399MHz.
65. Once again, LMC on the Z0 – SIMULATION text to highlight it.

67. Check All Channels and then uncheck the boxes next to the six power nets
(+0_75V, +1V, +1_2V, +1_5V, +1_8V, +2_5V). You may need to sort by channel
name first to make it easier to select.
68. Uncheck Return Loss and check Insertion Loss. Click OK.

69. Once again, use the toolbar pull-down menu, but change back to S-parameter
display.
70. RMC in the 2D plot area and uncheck Show X axis in log scale.
Notice that all the data bus lanes have similar insertion loss response. As you recall,
these nets are all routed on layer Signal$SIG_15V with a solid reference plane above;
so, other than the via transition, there are no other major impedance discontinuities to
impact the insertion loss. However, the five nets we selected from the address bus have
larger insertion loss and exhibit larger frequency fluctuation. Recall that these nets are
routed on layer Signal$SIG_16V and not all the nets have a solid reference on the
nearest plane layer. Perform these steps to see the problems with the routing:
71. Go back to the layout view by clicking on the 2D View tab.

72. Uncheck the box for View Only Active Layer in the Layer Selection
windowpane.

73. LMC to close the “eye” icons on the Layer Selection list except for the layers
Signal$SIG_16V and Signal$PWR_17.
74. Zoom in as necessary to see the segments of these five traces not covered by
the reference plane below. For those trace segments, the GND plane two layers
up will be used for reference, creating an impedance discontinuity. This is partly
what you see in the insertion loss plots.
75. Check the box for View Only Active Layer in the Layer Selection windowpane
to return to the typical single-layer view. (You do not have to re-open the “eyes”.
They will automatically open the next time you activate each layer.)
76. Use Windows Explorer to view the contents of the project folder Module3\. Notice
the numerous data files written to the disk by PowerSI. Of those, the
Viper_PDN_PSI_no_decaps_071720_094936_23988.bnp file is the S-
parameter file in BNP format, and the
Viper_PDN_PSI_no_decaps_071720_094936_23988.ckt file is the MCP circuit
wrapper, which will be used in tools such as Topology Explorer for system-level
bus analysis or time-domain noise analysis.

Note:
1) Your files will have different date-and-time stamps appended to the file
names.
2) BNP file format is a more compact binary form of S-parameter. This BNP file
is the frequency domain representation of the PCB with ports at the specified
locations. This BNP model includes the non-ideal power/ground effects that
are fully coupled with the signal distribution network of the DDR bus. The
BNP format can be used later for time/frequency domain analysis in Topology
Explorer, Spectre, or HSpice. PowerSI can also save S-parameters in
Touchstone format, if required.
Updating the Decoupling Capacitor Models
Next, we will update the capacitor definitions with realistic electrical models and will
enable decaps during the simulation.
77. We are first going to use the Analysis Model Manager (AMM) to load a capacitor
library. From the pull-down menu, select Tools > Analysis Model Manager.
78. On the AMM toolbar, select the icon next to Load Library File. Select the file
Module3.amm in the lab folder and click Open.

79. In the AMM window, under the Analysis Models pane, there is now a new
capacitor library called Module3. LMC on Module3 under Discrete > Capacitor
to display the library content.
80. Review the capacitors in the Project Library spreadsheet. Note that all the
models are RLC Spice models, and not S-parameters. LMC in the spreadsheet.
Press Ctrl-A to select all the capacitors. The impedance profile for all the
capacitors should be displayed in a graph at the bottom of the AMM window.
Adjust the size of the plot window to see it better.
81. The library only includes a few models, since this board only uses a few decap
values. If we were performing optimization, we would need to include a larger
range of capacitor values. LMC on the x in the upper-right corner of the AMM
window to close it for now.

82. In the Workflow pane, LMC on Assign Capacitor Models. The AMM Model
Assignment window should open. Also, the Component Manager pane should
display on the far right.
83. The Model Assignment window will only display the component models for
decaps that are on enabled power nets. We need to assign models from the
library for these decaps. Notice the capacitor values on the list based on the
component name: 660pF, 680pF, 4.7uF, 100uF. You may need to switch the view
list by clicking on the icon. If you explore the decaps placed under the device
U1 as well as bulk caps next to the VRM circuits, you will see that they are
associated with one of these models.
84. Select the component called CAP_0402-CDN-CAP-0032_4_7UF_4V_20% in the
Model Assignment window. LMC on the Browse Model button. The AMM
browser should open. Expand the window so that you can clearly see the models.

85. Select the model with the Cnom(nF) value of 4700nF (4.7uF). Click Select at the
bottom of the window to assign this model to the 4.7uF caps on the board. Your
Model Assignment window should now look like the figure below. Notice that the
4.7uF component has a model assigned from the library.
86. You need to repeat this process for the 660pF, 680pF, and 100uF components.
When selecting models for the 660pF and 680pF components, use the model with
Cnom=0.68nF in both cases. For the 100uF component, select the model with
Cnom=100000nF. When you have assigned models from the library to all four
components, your Model Assignment window should look as follows (the order
in which the models are displayed may be different in your case):

87. Click OK to close the Model Assignment window. In the Component Manager
pane on the right, LMC on any component. Press Ctrl-A to select all components.
RMC on the highlighted area and select Auto Selected Components.
88. In the Component Manager, click twice on the green arrow header to sort the
components based on which ones are enabled. You should now see several
decaps with green check marks next to them. These components now have valid
models assigned to them; so, they are enabled to participate in the simulation.
LMC on the first enabled decap and use the down-arrow key to scroll through the
list. As you select a decap, it will be highlighted on the layout. Notice that most of
the activated decaps are under the U1 component. A few are bulk caps next to
the VRM components.
89. Now that we have enabled the decaps, we are going to save the new setup in a
different file. Click File > Save As.
90. Save the file as Viper_PDN_PSI_decaps.spd in the Module3 folder.
91. Click Save. Click OK if prompted about any saving options.

92. Click Start Simulation in the Workflow pane. If a warning message related to via
overlap detection is displayed click on Yes to continue with simulation.
The simulation will likely take about 10 minutes to complete; so, now would be a good
time for a short break. The simulation results are shown below.
93. Optional – Close the Output windowpane at the bottom of the screen by doing an
LMC on the X. You may have to do this twice to also close the folder browser.
94. Repeat steps 57 to 63 in order to see the results shown below.

Notice that the impedance results are now very different than the previous simulation.
The decoupling capacitors change the PDN impedance response both at the lower end
of the frequency band and at the higher end of the band.
95. To show or hide individual curves, LMC on the color box next to each curve
name. Shown below is the result for +1_2V at the U1 component. Notice that the
large impedance peaks seen previously at around 280MHz and 398MHz have
been pushed higher in frequency and their magnitude has been reduced. You can
load the S-parameter results for the “no decap” run into the same display to
compare. If you wish to load the older run, RMC in the Network Parameters pane
and select Load. You can try this on your own.

96. Once again, LMC on the Z0 – SIMULATION text to highlight it.

98. Check All Channels and then uncheck the boxes next to the six power nets.

99. Uncheck Return Loss and check Insertion Loss. Click OK.
100. Once again, use the toolbar pull-down menu, but change back to S-parameter
display.
101. RMC in the 2D plot area and uncheck Show X axis in log scale.
Note that the insertion loss for the nets of the address bus are not much different than
the original run without decaps. Although the PDN’s impedance profiles have improved

by enabling the decoupling capacitors, the insertion loss has not. Decaps may have
slightly improved the current return path for these signals; however, there are still issues
with impedance discontinuities which we need to work on. For example, we can extend
the +1_5V power plane to fully cover all the nets and add decoupling capacitors near
the XP1 connector to improve the return current path. We are not going to make these
changes in this lab; however, you can see below the improvement in insertion loss after
these minor changes were made on the layout using Allegro PI. PowerSI is a very
useful tool for detecting SI/PI issues and exploring options to overcome these problems
quickly.
102. Finally, we are going to generate a report based on our final PowerSI run. Go
back to the layout view by clicking on the 2D View tab.
103. In the Workflow pane, LMC on Report.

104. In the Options window that appears, just click OK.

105. The report window will be displayed. Scroll through the report to inspect its
contents.
106. To save it, click File > Save As.
107. Accept the default name Simulation Report.htm and click Save.
108. Optional – Open the file in a web browser for viewing (see figure below).

109. Go to File > Exit to close and exit out of PowerSI.

Module 4: PDN Resonance Analysis with PowerSI

Spatial Mode
Introduction
In this module, we will use the PowerSI “Spatial mode” to analyze cavity resonances of
the PDN. Spatial mode handles designs containing multiples sources and performs AC
analysis of the design. It can obtain spatial variations across planes as well as voltages
and currents in the circuits and physical structures. The information obtained from this
analysis can help us determine the best decap characteristics and placement, to
enhance PDN AC response. Spatial mode can also be used for noise analysis and EMI
studies. We will use the design setup from Module 3 as our starting point. The steps for
setting up Spatial mode analysis are shown in the flow chart below.

Simulation Setup
1. Click Start > All Programs > Cadence Sigrity 2019 > PowerSI. If the license
window opens, select Choose all and then click Close. In PowerSI, close the “Tip
of the Day’’ window if it opens.
2. Create a new workflow by clicking on File > New in the top menu. Choose the
PowerSI tool, the Noise Coupling Analysis workflow and click on Ok.
It is also possible to choose the workflow by clicking on Switch Workflow in the

PowerSI workflow:
3. In the Workflow pane, select Load Layout File.

4. Open the file Viper_PDN_PSI_spatial.spd located in the Module4 folder.
5. If the workflow switches back to Model Extraction, click on Switch Workflow in
the workflow panel and repeat the setup of the figure above. If you get a warning
that says, “Adaptive is an invalid sweeping mode”, click OK to continue.

6. Check if Enable Spatial Mode is enabled.
7. In the Workflow pane, click Select Power Ground Nets.

8. A pop-up menu will appear. Select Skip setup P/G nets.
9. The Net Manager should appear on the right of the main window. If the Net
Manager does not appear on the right side, it may be behind the Layer Selection
pane. Look for the Net Manager tab at the bottom-right corner and select it to
bring the Net Manager to the front.
10. RMC anywhere in the spreadsheet area of the Net Manager and select Disable
All Nets.
11. At the bottom of the Net Manager, if not done already, clear the check for Keep
shape enabled when the net is disabled. Also, check Hide Disabled.
12. Enable the following nets by checking the boxes next to their names:
• +1_2V
• GND
13. In the Workflow pane, click Disable/Enable Decaps. The Component Manager
should appear on the far right.
14. LMC in the Component Manager and then press Ctrl-A to select all circuits.
15. RMC anywhere in the blue highlighted area and select Disable Selected
Components. Ignore this step and move on, if all the components are already
disabled.
16. In the Workflow pane, click Setup Excitation.

17. A Setup Wizard will appear. Click Next (Keep the default selection “Define
excitations on the enabled nets”).

18. Use the default selections for positive / negative nets and click Next.
19. Use the pull-down menu to select U1 from the list. This will drive the board with a
1A AC current source placed between power/ground pins of component U1.
Then, click Finish.
20. In the workflow, click Setup Simulation Frequencies.

21. Change the starting frequency to 10 MHz and ending frequency to 2 GHz. Click
OK.
22. In the Workflow pane, click Setup Field Observation.

23. A Setup Wizard will appear. Choose the manual option. Click OK.

24. Use the pull-down menu to select Signal$PWR_8 and Signal$GND_14 from the
list. Then, click Add and OK.
25. From the menu, click File > Save As.

26. Name the file as Viper_PDN_PSI_spatial_nodecaps.spd.
27. If the Saving Options window pops up, accept the defaults and click OK.
28. Ignore any warnings that might appear in the Output window.
29. In the Workflow pane, click Start Simulation. The simulation should take less
than 5 minutes to complete. If a warning message related to via overlap detection
is displayed click on Yes to continue with simulation.

Simulation Results
30. When the simulation completes, the 3D Result Display Control pane should
open in the right side of the main window. At the bottom-right, click Show Peak.
This will show the largest simulation results across the PCB, over the entire
simulation frequency band. This represents the voltage (electric field) between the
power and ground planes, which we specified in the field observation setup.

31. Use the Left Mouse Button (LMB) to grab and drag the slider underneath Start
Freq. Move the slider left and right. Notice that the peak values occur at 220MHz.
Recall that when we ran the extraction without decap, the first resonance for the
+1_2V rail was at 218MHz, as shown in the plot below. Other local peaks should
also correspond to the resonances in the impedance curve we generated in
Module 3. Note that the impedance plots generated in Module 3 tend to be
localized to an observation point, as an example for device U1. However, the
spatial distribution plots generated in this lab show voltage variation across the
entire PDN; so, they can be an effective tool for determining where to place
decaps on the power plane.
+1_2V rail impedance without decaps enabled
Now, we will re-enable the decaps to investigate their effects on the results.
32. Click on the 2D View tab to display the Viper_PDN_PSI_spatial_nodecaps.spd

layer view.
33. In the Workflow pane, click Disable / Enable Decaps.
34. The Component Manager should appear on the right. LMC in the Component
Manager and then press Ctrl-A to select all circuits.
35. RMC anywhere in the blue highlighted area and select Auto Selected
Components.
Note that many green check marks will appear. This has re-enabled those circuits for
simulation.

36. From the menu, click File > Save As.

37. Name the file as Viper_PDN_PSI_spatial_decaps.spd.
38. In the Saving Options window, accept the defaults and click OK.
39. In the Workflow pane, click Start Simulation. The simulation should take less
than 5 minutes.
40. When the simulation completes, at the bottom-right corner, click on Show Peak.
This will show the largest simulation results at each coordinate over the entire
simulated frequency band.
41. Use the LMB to grab and drag the slider underneath Start Freq. Move the slider
left and right. Notice that the peak voltage at 220MHz (max values for no decap
run) is now just 169mV. The decaps have been very effective at suppressing the
resonance at this frequency. The peak results are now at 1.57GHz. Again, you
can see that this correlates to the impedance response that was obtained in
Module 3, when running extraction with decaps enabled, as shown in the
impedance plot below.

+1_2V rail impedance with decaps enabled
42. In the 3D Result Display Control pane, click on 3D Structure and select the
Local Auto radio button.

43. Put the mouse cursor in the 3D display area. Press and hold the LMB. Drag the
mouse in all directions. You can rotate the 3D structure with this method. See
below for a common view.
Note that we could have run this analysis on the board prior to decap placement to
determine the best locations and values for decaps. The best decap placement
estimation workflow is available in Sigrity OptimizePI® tool, which can achieve a similar
goal using placement optimization.

Module 5 (Optional): Compact Model Extraction with

Broadband Spice
This module covers:
• Accessing Broadband Spice from Allegro SI
• Broadband Spice model extraction
• Using power-aware Broadband Spice model in Topology Explorer
• Parallel bus simulation options
• Browsing past simulations in Topology Explorer
Introduction
Allegro Sigrity Broadband SPICE extracts SPICE-equivalent circuits from network
parameters and provides a passive compact circuit model while maintaining accuracy
for efficient transient simulations in SPDSIM, SPECTRE, HSPICE, or other SPICE-
compatible circuit simulators. Broadband SPICE accepts network parameters such as
the scattering, impedance, or admittance (S, Z, or Y) parameters of N-port passive
networks in Touchstone format or Sigrity’ s more compact Broadband Network
Parameter (BNP) format. The compact black-box models extracted by Broadband
SPICE offer excellent convergence in transient simulations.
In Module 3, a power-aware S-parameter model (in BNP format) was extracted from a
real world DDR3 PCB layout using Allegro Sigrity PowerSI. In this module, a similar
BNP S-parameter model will be converted to a Spice-equivalent circuit model. The
Spice model will then be imported into the previously set-up bus simulation in Topology
Explorer.
In general, the use of Broadband Spice is optional in a time-domain system-level

simulation. It is only necessary if the S-parameter model does not converge in time-
domain circuit simulations such as in HSPICE or Topology Explorer. In many system-
level simulations, the extracted S-parameter models used generally include both signal
and power nets. As a result, the network parameter matrix tends to have more issues
with convergence and DC offsets when used in a time-domain simulation. Furthermore,
as the network parameter size increases, as in case of bus analysis for example, the
direct use of S-parameters in system simulations can result in longer simulation times.
Broadband Spice models can also help mitigate this problem. This module is offered as
an optional module to show the general flow when using Broadband Spice.

Launching Broadband Spice

Launch Broadband Spice from Allegro and load the input S-parameter file.
1. Open Start > All Programs > Cadence PCB 17.4-2019 > Sigrity Integrity 17.4.
2. Choose Allegro Sigrity SI (for board) and select the Power-Aware SI option.
3. Within Allegro Sigrity SI, go to Tools > BroadbandSPICE to launch Broadband

SPICE.

4. Once the Broadband SPICE tool launches, select the FD Checking, Tuning,
Extraction and TD Checking workflow and click Load original s-parameter in
the Workflow pane.
5. Select the cdn_ddr3_111212_205143.bnp S-parameter file located in the

Module5\Broadband Spice Module folder and click Open.
6. You should see the following in the Broadband Spice window when the S-
parameter file is loaded.

Setup Extraction Options

Prior to extracting the Spice circuit from the BNP S-parameter model, a few options are
available to customize the model output. In this module, we will use the default settings.
7. Click Setup extraction in the Workflow pane.

8. Ensure that the extraction settings are as shown below:
9. Click OK to close.
Begin Spice Model Extraction
10. Click Start extraction in the Workflow pane.
11. Model extraction begins, and its progress can be tracked in the Progress Report
window.

The Progress Report window will display the progress through the model extraction
and passivity enforcement until completion. For this case, the engine applies more than
one passivity algorithm in order to obtain the best results. The simulation may take up to
15 minutes to complete.

12. The Broadband Spice curve viewer displays both the original S-parameter curve
and the extracted model curves on the same plot. The solid black curve is the
original S-parameter curve. The pink dash curve is the extracted model. Clicking
on different Para. Entry values in the left column will show different S-parameter
entries and their corresponding curves.
13. Click on the large x to close and exit out of Broadband Spice. Do not save the
changes.

Importing Broadband Spice Model into Topology Explorer

14. Start Topology Explorer by selecting the shortcut on the desktop or from the Start
Menu (Start Menu->Cadence PCB 17.4-2019->Topology Explorer 17.4). If a
license window prompt appears, select SystemSI - Parallel Bus Analysis II.
15. Close the Tip of the Day popup, if it opens. Within Topology Explorer, click on
Topology > Open on the top menu:

16. Select the Module5.topx file in the Module5\Topology Explorer Module folder
and click Open.
17. Click Choose all if it prompts to select a license type and then click Close.
18. The bus topology consists of a controller, single DRAM, voltage regular, and the
PCB. The remainder of this workshop will focus on replacing the PCB S-
parameter model with the Broadband Spice model that we just extracted.

19. Double-click the LMB on the PCB block to open the PCB Property pane. Click on
View Subcircuit at the bottom of the PCB Property pane and notice that the
PCB block is pre-populated with the cdn_ddr3_111212_205143_BBSckt.txt file,
which is the Spice model extracted using Broadband Spice. (You may need to
scroll down to see this file name.)
20. Click OK to close the Subcircuit Editor window.

Checking Analysis Options
21. In the Workflow pane, click on Set Analysis Options.

22. Ensure that all settings are as shown below.
23. Once the analysis options are confirmed, click OK to close the Analysis Options
pane.
Running Bus Simulation
24. Save the file and click Start Bus Simulation in the Workflow pane.

25. The time-domain simulation will be performed using the SPDSIM engine.
26. Once the simulation completes, you will see the following display on the
SSIViewer.

27. Click on Browse Results in the Topology Explorer Workflow pane.
28. The Results Browser shows the previous simulations. Select S_Param_Results
and click the Show Result button.
29. Once the curves show, click Close to close the Results Browser pane.
30. Make sure that the curves from both simulations are enabled:

31. You can maximize the Time Domain Curve window as shown below.
Both sets of curves match up nicely. This demonstrates the strong correlation between
transient simulations using Broadband Spice-equivalent circuit model and those using
BNP S-parameter model. Although this is a relatively small S-parameter (23 ports),
there is still a 14% speedup in simulation time when using the circuit model. Generally,
this speedup is more dramatic as the S-parameter size increases.
In general, the use of Broadband Spice is optional in a system-level simulation. It is only

necessary if the S-parameter model does not converge in time-domain circuit
simulations such as in HSPICE or Topology Explorer. There are also features in
Broadband Spice to improve the quality of a given S-parameter, such as reciprocity
enforcement, data smoothing, low-frequency extrapolation, interpolation, and causality
enforcement. These tuning settings can be applied to the S-parameter directly to
generate a new, more robust S-parameter for time-domain simulation. This module is
offered as an optional module to show the general flow when using Broadband Spice.
As stated earlier, the compact black-box models extracted by Broadband SPICE offer
excellent convergence in transient simulations.
32. Go to Topology > Exit to close and exit out of Topology Explorer.

Module 6 (Optional): Multi-Structure Simulation in

PowerSI
Introduction
With PowerSI multi-structure workspace, a single S matrix can be generated to
represent the end-to-end interconnect model of a system consisting of motherboards,
daughter cards, IC packages, RDL, etc. Instead of physically merging the layouts of the
various blocks for field analysis, a block-based workspace is used to perform the
necessary connectivity between separate layout files. The connectivity between various
components is achieved by defining vias/solder balls/wirebonds/leads with the
appropriate dimension and electrical parameters. Virtual grounds are defined between
the components that will be used for defining internal ports. Internally, all internal ports
are reduced after simulation and a final S-parameter representing the end-to-end
connectivity is generated.
There are several advantages of using the PowerSI multi-structure workflow rather than
taking a system-level approach where individual models are extracted for each PCB
and package separately and cascaded together in a system-level tool. The benefits
include:
1. Better performance in reducing the huge number of internal ports in the component
connections
2. Numerical robustness without the need for large S matrix for separate components
3. Improved accuracy in capturing the coupling between components if applicable
Multi-Structure Workspace Setup
In this lab, we will use a simple example to illustrate how to use PowerSI multi-structure
workspace. The layout files to be used are included in the Module6 folder (PCB.spd,
PKG.spd). The workspace setup is shown in the video PSI_Multi_struct.mp4, which is
also located in the Module6 folder. You can follow the video to recreate the workspace
setup for yourself. In this video, we create a workspace to generate a single S-
parameter model for signal nets starting on the PCB (shown in the left figure) and
terminating at the die bumps on components D1 and D2 on the flip-chip package
(shown in the right figure). The setup includes the following steps:
1. Associate each layout with a new block on the workspace.

2. Use MCP to connect the two blocks, including ball grid parameters.
3. Load each block layout to set up simulation parameters (ports, frequency sweep).
4. Check the port setting and simulation frequencies for the workspace.
5. Run workspace simulation.

6. Review S-parameters.
Support
Cadence Support Portal provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit https://support.cadence.com.
Feedback
Email comments, questions, and suggestions to content_feedback@cadence.com.


PowerSI Workshop Lab Instructions

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Sigrity PowerSI Workshop

Rapid Adoption Kit (RAK)

Product Version: Allegro 17.4 Platform; Release Sigrity 2019

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The following modules are included in this RAK:

• Module 1: Accessing PowerSI from Allegro

• Module 2: Port Resolution in PowerSI

• Module 3: PDN/Signal Model Extraction with PowerSI

• Module 4: PDN Resonance Analysis with PowerSI Spatial Mode

• Module 5: Compact Model Extraction with Broadband Spice

• Module 6: Multi-Structure Simulation in PowerSI

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Module 1: Accessing PowerSI from Allegro

• Overview of PowerSI and Allegro Sigrity SI

• Launching PSI from Allegro Sigrity SI

• Model extraction setup and simulation in PSI

• Incremental layout update and re-simulation

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PowerSI Model Extraction

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To run PowerSI analysis from the SI:

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5. Click Ok to close the SPDIF Preferences window.

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7. You should see a window like the one shown below.

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8. We are only going to extract a differential pair (TXDATA0+/TXDATA0-), located on

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Module 2: Port Resolution in PowerSI

• Overview of port resolution concepts

• PowerSI setup using net-based ports

• PowerSI setup using pin-based ports

• Impact of special void settings in PSI

Figure 1: Application-specific port resolution

PowerSI Setup Using Net-Based Ports

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2. Click Close if the Tip of the Day window opens.

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Your PowerSI canvas should look like the figure below:

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PowerSI Setup Using Pin-Based Ports

27. From the menu, select Setup > Port.

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