pg392 Rfsoc Dfe Resampler - v1 0 - WTMKX

XILINX CONFIDENTIAL
RFSoC DFE Resampler v1.0
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LogiCORE IP Product Guide
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PG392 (v1.0) April 21, 2022
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XILINX CONFIDENTIAL
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Table of Contents
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Chapter 1: Introduction.............................................................................................. 4
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Features........................................................................................................................................ 4
IP Facts..........................................................................................................................................5
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Chapter 2: Overview......................................................................................................6
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Core Overview..............................................................................................................................6
Applications..................................................................................................................................7
Licensing and Ordering.............................................................................................................. 7
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Chapter 3: Product Specification........................................................................... 8
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Performance................................................................................................................................ 8
Port Descriptions.......................................................................................................................10
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Chapter 4: Designing with the Core................................................................... 14

General Design Guidelines.......................................................................................................14
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Clocking...................................................................................................................................... 14
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Resets..........................................................................................................................................15
Interfacing to the Core............................................................................................................. 15
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Configuring and Controlling the Core.................................................................................... 22

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Chapter 5: Design Flow Steps.................................................................................24

Customizing and Generating the Core................................................................................... 24
Constraining the Core...............................................................................................................27
Simulation.................................................................................................................................. 28
Synthesis and Implementation................................................................................................28
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Chapter 6: Example Design..................................................................................... 29

Overview.....................................................................................................................................29
Running the Example Design.................................................................................................. 30
Chapter 7: C Model....................................................................................................... 32
Features......................................................................................................................................32
PG392 (v1.0) April 21, 2022 www.xilinx.com

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RFSoC DFE Resampler 2
XILINX CONFIDENTIAL
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Overview.....................................................................................................................................32
Unpacking and Model Contents..............................................................................................33
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Installation................................................................................................................................. 33
C Model Interface...................................................................................................................... 34
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Compiling and Linking..............................................................................................................38
MATLAB Interface......................................................................................................................39
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Appendix A: Debugging............................................................................................ 42
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Finding Help on Xilinx.com...................................................................................................... 42
Debug Tools............................................................................................................................... 43
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Hardware Debug....................................................................................................................... 43
Appendix B: Additional Resources and Legal Notices............................. 45

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Xilinx Resources.........................................................................................................................45
Documentation Navigator and Design Hubs.........................................................................45
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References..................................................................................................................................45
Revision History......................................................................................................................... 46
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Please Read: Important Legal Notices................................................................................... 46

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XILINX CONFIDENTIAL
Chapter 1: Introduction
Chapter 1
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Introduction
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The Xilinx® Zynq® UltraScale+™ RFSoC DFE devices contain a variety of dedicated signal
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processing primitives, which address the challenges of high-speed, low-power digital front-end
design.
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The RFSoC DFE Resampler LogiCORE™ IP provides a versatile and configurable multi-channel
sample-rate conversion filter. It can be used in the uplink or downlink directions.
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Features
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• Supports up to eight antennas (channels) per instance

• 16-bit or (uplink mode only) 18-bit complex data input and output
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• AXI4-Stream interfaces
• Uplink sample rate decimation factors of 2/3, 3/4, 4/5, or 5/6
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• Downlink sample rate interpolation factors of 3/2, 2/1, 5/2, 3/1, 7/2, 4/1, 5/1, or 7/1
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• Super sample-rate output (SSRO) option, one to eight samples per cycle
• Super sample-rate input (SSRI) option, one to three samples per cycle (uplink mode only)
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• Latency-compensated sideband channel (TUSER) for sample-accurate framing

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• Optional deterministic latency operating mode

• Power-down and dynamic power saving modes available
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Chapter 1: Introduction
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IP Facts
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LogiCORE™ IP Facts Table
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Core Specifics
Family1
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Supported Device Zynq® UltraScale+™ RFSoC DFE
Supported User Interfaces AXI4-Stream
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Resources N/A
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Provided with Core
Design Files Encrypted RTL
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Example Design Verilog (simulation only)
Test Bench Provided with the example design
Constraints File
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Simulation Model Encrypted Verilog
C model
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Supported S/W Driver N/A
Tested Design Flows2
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Design Entry Vivado® Design Suite

Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
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Support
Release Notes and Known Issues Master Answer Record: 76134
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All Vivado IP Change Logs Master Vivado IP Change Logs: 72775

Xilinx Support web page
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Notes:
1. For a complete list of supported devices, see the Vivado® IP catalog.
2. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.
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Chapter 2: Overview
Chapter 2
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Overview
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Core Overview
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The RFSoC DFE Resampler IP core can perform fractional rate interpolation processing for up to
eight antenna channels. The sample rate change is expressed as a ratio P/Q, where P is the
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interpolation factor and Q is the decimation factor.
Standard AXI4-Stream interfaces are used for data input and output. According to the
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application, the width of the data buses can be configured as 16-bit or (in uplink mode) 18-bit.
Each sample comprises I and Q components, for a total of 32 or 36 bits per sample.
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Samples from multiple antennas are transferred in parallel on the input and output data buses.
When the super sample-rate feature is used on the output bus or (in uplink mode) the input bus,
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two or more samples are transferred in parallel on the same clock cycle for each antenna.
An overview of the core functional structure is shown in the following figure.

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Figure 1: Core Functional Overview

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s_axis_din_aclk domain m_axis_dout_aclk domain

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Fractional
Interpolation or Sample CDC Output
DIN DOUT
Decimation Filter gearbox FIFO gearbox
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X25839-100721

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Chapter 2: Overview
Note: the CDC FIFO between the input (s_axis_din_aclk) and output (m_axis_dout_aclk) clock
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domains is always present, even in configurations where the input and output clock frequencies are
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identical.
The interpolation and decimation filter banks have fixed and pre-optimized coefficients. The stop
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band attenuation is at least 85 dB in all operating modes. The pass-band is equal to 85% of the
input sampling rate when interpolating and is equal to 85% of the output sample rate when
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decimating.
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Each AXI4-Stream interface has associated TUSER and TLAST signals for user-defined framing/
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timing control purposes. The core provides a delay-matching feature to ensure the alignment of
this out-of-band information is preserved throughout the signal processing chain. Latency
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matching includes both processing latency and filter group delay.
The core is capable of maintaining a fixed latency between its input and its output when the
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"deterministic latency" option is selected at configuration time. This eliminates latency variation
due to the clock domain crossing uncertainty, at the expense of additional fabric resources.
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The core supports entry into and exit from low power modes triggered by transitions on a user-
defined bit of the TUSER bus.
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Applications
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The RFSoC DFE Resampler core can implement a fractional-rate resampling of antenna data for a
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communication system, including those based on the 3GPP LTE standard and the 3GPP 5G
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standard. The core can filter both for the downlink and uplink, which can aid system-level
optimization and frequency planning. It can also be used within the observation path of a digital
pre-distortion (DPD) subsystem.
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Licensing and Ordering

This Xilinx® LogiCORE IP module is provided at no additional cost in Vivado® for customers with
a valid license for the RFSoC DFE family of Adaptable SoCs.
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Information about other Xilinx® LogiCORE™ IP modules is available at the Xilinx Intellectual
Property page. For information about pricing and availability of other Xilinx LogiCORE IP modules
and tools, contact your local Xilinx sales representative.

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Chapter 3: Product Specification
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Product Specification
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Performance
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For full details about performance and resource use, visit the Performance and Resource Use web
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Latency
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The latency of the core depends on the parameters chosen at customization time. The following
table shows the latency values for all the possible core configurations.
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When customizing the core, the latency of the current configuration is also displayed in the Core
Summary section of the Configuration Parameters tab within the IP customization dialog box.
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Latency is measured in cycles of the m_axis_dout_aclk clock. The tabulated latency values
include both processing latency and the group delay of the filter. The 'D' column shows the
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latency when the deterministic latency option is select. The 'ND' column shows the approximate
latency when the deterministic latency option is not selected.
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Table 1: Resampler Latencies: Uplink Modes

D
P Q SSRI SSRO D ND P Q SSRI SSRO D ND

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2 3 1 1 45 42 4 5 1 1 47 44
2 3 1 2 30 27 4 5 1 2 31 28
2 3 1 3 26 23 4 5 1 3 28 25
2 3 1 4 24 21 4 5 1 4 23 20
2 3 1 5 22 19 4 5 1 5 25 21
2 3 1 6 20 18 4 5 1 6 21 19
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2 3 1 7 21 18 4 5 1 7 22 18
2 3 1 8 20 17 4 5 1 8 19 16
2 3 2 1 61 58 4 5 2 1 66 63
2 3 2 2 36 34 4 5 2 2 38 36
2 3 2 3 30 28 4 5 2 3 33 31
2 3 2 4 27 24 4 5 2 4 27 24
2 3 2 5 26 23 4 5 2 5 28 25

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Table 1: Resampler Latencies: Uplink Modes (cont'd)
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2 3 2 6 23 21 4 5 2 6 26 23
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2 3 2 7 24 21 4 5 2 7 25 23
2 3 2 8 22 19 4 5 2 8 23 20
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2 3 3 1 73 69 4 5 3 1 87 83
2 3 3 2 42 39 4 5 3 2 52 49
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2 3 3 3 34 31 4 5 3 3 36 34
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2 3 3 4 29 26 4 5 3 4 31 28
2 3 3 5 27 25 4 5 3 5 29 27
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2 3 3 6 25 22 4 5 3 6 29 27
2 3 3 7 24 22 4 5 3 7 29 27
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3 4 1 3 25 23 5 6 1 3 29 26
3 4 1 4 24 21 5 6 1 4 26 25
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3 4 1 5 23 20 5 6 1 5 22 20
3 4 1 6 20 18 5 6 1 6 23 20
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3 4 1 7 22 19 5 6 1 7 22 19
3 4 1 8 20 18 5 6 1 8 21 19
3 4 2 1 63 59 5 6 2 1 67 64
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3 4 2 2 37 34 5 6 2 2 39 36
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3 4 2 3 30 27 5 6 2 3 32 30
3 4 2 4 28 25 5 6 2 4 29 26
3 4 2 5 26 24 5 6 2 5 24 22
D
3 4 2 6 23 20 5 6 2 6 27 23
3 4 2 7 24 20 5 6 2 7 26 22
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3 4 2 8 22 19 5 6 2 8 24 22
3 4 3 1 79 75 5 6 3 1 85 80
3 4 3 2 48 45 5 6 3 2 50 47
3 4 3 3 34 32 5 6 3 3 36 33
3 4 3 4 33 31 5 6 3 4 33 29
3 4 3 5 31 28 5 6 3 5 28 25
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3 4 3 6 26 24 5 6 3 6 29 26
3 4 3 7 27 25 5 6 3 7 28 24
3 4 3 8 27 24 5 6 3 8 26 24

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Table 2: Resampler Latencies: Downlink Modes
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3 2 1 1 71 66 7 2 1 1 159 153
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3 2 1 2 40 37 7 2 1 2 86 83
3 2 1 3 33 29 7 2 1 3 64 60
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3 2 1 4 30 27 7 2 1 4 49 45
3 2 1 5 28 25 7 2 1 5 44 41
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3 2 1 6 25 21 7 2 1 6 41 38
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3 2 1 7 24 21 7 2 1 7 35 31
3 2 1 8 24 20 7 2 1 8 36 32
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2 1 1 1 87 82 4 1 1 1 155 148
2 1 1 2 49 45 4 1 1 2 85 80
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48
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2 1 1 6 27 24 4 1 1 6 38 34
2 1 1 7 26 24 4 1 1 7 37 33
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2 1 1 8 25 21 4 1 1 8 32 29
5 2 1 1 108 102 5 1 1 1 195 187
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5 2 1 2 62 58 5 1 1 2 106 100
5 2 1 3 44 41 5 1 1 3 76 72
5 2 1 4 38 35 5 1 1 4 61 57
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5 2 1 5 33 29 5 1 1 5 49 45
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5 2 1 6 33 29 5 1 1 6 45 42
5 2 1 7 31 28 5 1 1 7 42 38
5 2 1 8 29 26 5 1 1 8 38 35
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3 1 1 1 123 117 7 1 1 1 295 285

3 1 1 2 69 65 7 1 1 2 157 151
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3 1 1 3 49 45 7 1 1 3 111 107
3 1 1 4 41 38 7 1 1 4 87 83
3 1 1 5 37 33 7 1 1 5 70 65
3 1 1 6 33 29 7 1 1 6 60 56
3 1 1 7 32 29 7 1 1 7 52 48
3 1 1 8 30 27 7 1 1 8 49 45
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Port Descriptions
The core interfaces are shown in the following figure.

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Figure 2: Core Ports
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m_axis_dout_aclk
s_axis_din_aclk m_axis_dout_aresetn
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s_axis_din_aresetn
m_axis_dout_tdata[(2*NA*SSRO*OW)-1:0]
[2*NA*SSRI*IW)-1:0] s_axis_din_tdata m_axis_dout_tvalid
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s_axis_din_tvalid m_axis_dout_tuser [(UW*SSRO)-1:0]
[UW*SSRI)-1:0] s_axis_din_tuser xdfe_resampler m_axis_dout_tlast
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s_axis_din_tlast
s_axis_din_tready m_sysref
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m_latency_status
s_sysref
s_latency_status fifo_error
overflow
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The signals s_sysref, m_sysref, s_latency_status, and m_latency_status are only

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present when the deterministic latency option is selected when the core is customized.
Data Input Interface Ports

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Port Name I/O Clock Description

s_axis_din_tdata[2*IW*SSRI*NA-1:0] I s_axis_din_aclk Input sample data. Width is determined by the
input sample width IW (16 for 16-bit samples and
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24 for 18-bit samples), the number of antennas NA,

and (in uplink mode only) the number of input
samples per clock cycle SSRI.
s_axis_din_tvalid I s_axis_din_aclk Valid handshake signal for the data input channel.
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The upstream logic uses this to signal that it

provides valid data.
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s_axis_din_tready O s_axis_din_aclk Ready handshake signal for the data input channel.
The core uses this to signal that it can accept data.
s_axis_din_tlast I s_axis_din_aclk Last framing signal for the data input channel. The
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core does not rely on this signal for operation, but

passes it through the data output interface after
applying latency compensation.
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s_axis_din_tuser[UW*SSRI-1:0] I s_axis_din_aclk User-defined framing information. The width of

this field (UW) can be chosen when the core is
configured. Used for triggering configuration
updates within the core. Also passed through to
the data output interface after applying latency
compensation. In uplink mode, if there are multiple
data samples per clock cycle (SSRI>1) then there
are also multiple TUSER input samples per clock
cycle.
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Data Output Interface Ports

m_axis_dout_tdata[2*OW*SSRO*NA-1:0] O m_axis_dout_aclk Output sample data. Width is determined by the
output sample width OW (16 for 16-bit samples and
24 for 18-bit samples), the number of antennas NA,
and the number of output samples per clock SSRO.

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m_axis_dout_tvalid O m_axis_dout_aclk Valid handshake signal for the data output channel.
The downstream logic uses this to identify cycles
with valid sample data present.
m_axis_dout_tlast O m_axis_dout_aclk Last framing signal for the data input channel. This is
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a latency-compensated version of s_axis_din_tlast.
m_axis_dout_tuser[UW*SSRO-1:0] O m_axis_dout_aclk User-defined framing information. The width of this
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field (UW) can be chosen when the core is
configured. This is a latency-compensated version of
s_axis_din_tuser. If there are multiple data samples
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per clock cycle (SSRO>1) then there are also multiple
TUSER output samples per clock cycle.
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Status Output Ports
Port Name
or R to ial I/O Clock Description
fifo_error O s_axis_din_aclk Indicates that an underflow or overflow has
occurred in the rate-change CDC FIFO.
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overflow O s_axis_din_aclk Indicates that an internal arithmetic overflow has
occurred.
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Deterministic Latency Ports

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The following ports are only present when deterministic latency mode is selected.
Port name I/O Clock Description

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s_sysref I s_axis_din_aclk System timing reference pulse in input

clock domain.
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m_sysref I m_axis_dout_aclk System timing reference pulse in output

clock domain.
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s_latency_status O s_axis_din_aclk Status of deterministic latency

synchronization operation in input clock
domain. This signal is for information only.
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The value is initially 0 after reset, rising to 1

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when the deterministic latency

synchronization operation is complete.
m_latency_status O m_axis_dout_aclk Status of deterministic latency
synchronization operation in output clock
domain. This signal is for information only.
The value is initially 0 after reset, rising to 1
when the deterministic latency
synchronization operation is complete.
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Clock and Reset Ports

s_axis_din_aclk I - Clock for AXI input stream interface.
s_axis_din_aresetn I s_axis_din_aclk Active-Low synchronous reset for AXI input
stream interface.

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m_axis_dout_aclk I - Clock for AXI output stream interface.
m_axis_dout_aresetn I m_axis_dout_aclk Active-Low synchronous reset for AXI output
stream interface.
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Chapter 4: Designing with the Core
Chapter 4
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Designing with the Core
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This section includes guidelines and additional information to facilitate designing with the core.
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General Design Guidelines
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Registering Signals
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To simplify timing and increase system performance in a programmable device design, keep all
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inputs and outputs registered between the user application and the core. This means that all
inputs and outputs from the user application should come from, or connect to, a flip-flop. While
registering signals might not be possible for all paths, it simplifies timing analysis and makes it
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easier for the Xilinx® tools to place and route the design.
Make Only Allowed Modifications

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You should not modify the core. Any modifications can have adverse effects on system timing
and protocol compliance. Supported user configurations of the core can only be made by
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selecting the options in the customization IP dialog box when the core is generated.
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Clocking
The RFSoC DFE Resampler core has two clocks, s_axis_din_aclk and m_axis_dout_aclk.
The input datapath logic (including DFE PQ_DECIM and PQ_INTERP primitives) and the input
at
interface all operate synchronous to s_axis_din_aclk. The output datapath logic and output
interface operate synchronous to m_axis_dout_aclk. Typical rates for these clocks are from
61.44 MHz to 491.52 MHz in a 5G system.
Note: No assumption is made about the relative phase relationship between s_axis_din_aclk and
m_axis_dout_aclk. However, for correct operation it is essential that their frequency relationship be
exact, that is, both clocks are ultimately sourced from the same oscillator. Failure to observe this
requirement can lead to FIFO overflow or underflow errors inside the core.

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Resets
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The RFSoC DFE Resampler IP core has two resets, s_axis_din_aresetn and
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m_axis_dout_aresetn, corresponding to the two clock domains described in the Clocking
section. These signals are active-Low.
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Use both resets to reset the core to its default state. To achieve this, the reset signals should be
-D ea iro for
asserted for at least four active clock cycles of the slowest clock domain. The resets can be
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deasserted in any order, so long as the first reset is not released before the second reset has been
asserted. The reset signals are combined internally and used to reset all parts of the core
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including the FIFO, gearboxes and filter delay line contents.
Both reset signals must remain asserted at system start-up until both s_axis_din_aclk and
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m_axis_dout_aclk are stable.
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Interfacing to the Core

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Data Format
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The s_axis_din_tdata input bus and m_axis_dout_tdata output bus use the same
format for transferring sample data. The in-phase (I) part of each sample is placed at the lowest-
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numbered bit position, followed by the quadrature (Q) part. Each part of the sample is aligned to
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an 8-bit boundary, with zero-padding added above the most significant bit if the sample width is
not a multiple of 8 bits.
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If the super sample rate factor (SSRI or SSRO) is greater than one, the multiple samples for each
antenna are concatenated with data for the earliest sample in time on the RHS (lowest-numbered
AM
D
bits) and data for the latest sample in time on the LHS (highest-numbered bits).
If the number of antennas is greater than one, the samples (or groups of samples in the SSR case)
for the multiple antennas are concatenated with data for the lowest-numbered antenna on the
RHS (lowest-numbered bits) and data for the highest-numbered antenna on the LHS (highest-
numbered bits).
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The following figure shows the data format for both 16-bit and 18-bit sample widths.

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Figure 3: Data Format
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18-bit samples: 16-bit samples:
48 47 24 23 0 32 31 16 15 0
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42 41 18 17
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0 Q 0 I Q I
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Latest Earliest
sample sample
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Ak Sn Ak S1 Ak S0 A1 Sn A1 S1 A1 S0 A0 Sn A0 S1 A0 S0
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Antenna k samples Antenna 1 samples Antenna 0 samples
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X25927-110121
The sample data is treated as two’s complement fixed-point data. The position of the binary point
is arbitrary. In this document it will be assumed that the binary point is to the right of the MSB,
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meaning there are 15 fractional bits when the sample width is 16-bit and 17 fractional bits when
the sample width is 18-bit. The I and Q components of each input data item are taken to be the
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real and imaginary parts of one complex input sample. If the core connects to the RF Data
Converter IP, then you should ensure that the data widths on both IP cores match.
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Deterministic Latency Mode

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Because the RFSoC DFE Resampler core contains a CDC FIFO, phase differences between the
AM
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input and output clocks can cause the latency through the core to vary. The latency will always
remain fixed while the core is operational, but resetting the core may cause the latency to change
to a different value. For some applications, this behavior is undesirable. For such applications,
select the deterministic latency mode when customizing the core.
In deterministic latency mode, the core's latency can always be guaranteed to maintain a fixed
value. The latency can be determined precisely for those input samples that arrive when the
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rising edge of the input clock is aligned with the rising edge of the output clock. When SSRO > 1,
the core guarantees that these samples will not be decimated and they will be located in the
lowest numbered position (RHS) of the output m_axis_dout bus.

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The alignment of the two clocks’ rising edges must be indicated to the core using the periodic
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signals, s_sysref and m_sysref. Typically, these inputs would be derived from a slow signal
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glb_SYSREF, outside the core, which toggles in alignment with the two clocks. The period of
this signal should be at least 300 times the period of the slowest of the clocks
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s_axis_din_aclk and m_axis_dout_aclk.
ist rch Li ma
The glb_SYSREF signal is registered to generate s_sysref and m_sysref at their respective
i o i tu
clocks s_axis_din_aclk and m_axis_dout_aclk as seen in the following figure. For
-D ea iro for
simplicity, only one rising edge of the periodic signals glb_SYSREF, s_sysref, and m_sysref
are shown.
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Figure 4: DFE Resampler SYSREF Timing
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In deterministic latency mode, the core will not process any input samples until this
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synchronization process has been completed. The s_latency_status assertion shows that
the core has started processing the input data and this assertion is expected to happen within (Q
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x SSRO) to (4 x Q x SSRO) input clock cycles after the s_sysref edge that arrives after the
s_axis_din_tready assertion. The m_latency_status assertion shows that the
synchronization process has completed. You can safely rely on m_axid_dout_tvalid assertion
to process data and the latency status signals may be used for debug.
Latency Compensation for TUSER and TLAST

at
The TUSER and TLAST signals on the AXI4-Stream output interface are generated from the
equivalent signals on the input interface, after compensation for the processing latency and
group delay of the filter. Because of the fractional nature of the rate change within the RFSoC
DFE Resampler core, the relationship between TUSER/TLAST at the input and TUSER/TLAST at
the output is non-trivial.

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XILINX CONFIDENTIAL
The TLAST signal is defined by the AXI4-Stream interface standard as a single bit which marks
n
the end of a packet (for example: a radio framing boundary). The core provides the following
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guarantees when re-timing TLAST from the input to the output:
• TLAST at the output is always a single cycle pulse.
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• One pulse on TLAST at the input always becomes exactly one pulse on TLAST at the output.
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• A TLAST pulse always coincides as closely as possible with the same sample on the output
that it did on the input.
-D ea iro for
When there are multiple output samples per clock cycle, this is still true, but it is no longer
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○
possible to identify exactly which of the simultaneous output samples the TLAST pulse is
associated with.
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○ When there are multiple input samples per clock cycle, the input TLAST pulse is assumed
to correspond to the latest input sample in time.
○
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In the case of a tie, the earlier output cycle is chosen. For example, in the following figure,
the input TLAST pulse at t=14.5 ns has equal distance to the output samples at t=14 ns and
t f do ed nt
t=15 ns, so the output sample of t=14 ns is chosen.
Figure 5: DFE Resampler TUSER and TLAST Latency Compensation, P=5 Q=2
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The following figures show two possible scenarios in a 4/5 resampler configuration that result in
an output TLAST pulse at t=12.5 ns. In the first scenario, the input TLAST pulse is at t=11.5 ns. In
at
the second, the input TLAST pulse is at t=13.5 ns.

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Figure 6: DFE Resampler TLAST Positions
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The format of the TUSER signal is user-defined. When an interface of the RFSoC DFE Resampler
n
core is configured in super sample-rate mode, the TUSER bus width is expanded to allow each
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data sample to have an accompanying TUSER sample. The format of TUSER follows the
convention described above for TDATA, where the earliest TUSER sample in time is placed at the
n te
lowest-numbered (RHS) position and the latest TUSER sample in time is placed at the highest-
ist rch Li ma
numbered (LHS) position.
i o i tu
In downlink mode, the sample rate at the output is always greater than the sample rate at the
input. The TUSER rate change is handled by replicating TUSER samples. The core guarantees
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that:
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• Every output sample that corresponds unambiguously to an input sample will have the same
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TUSER sample associated with it on the output as it did on the input.
• The additional interpolated samples will receive copies of the TUSER sample associated with
or R to ial
their closest neighbor. In the case of a tie, the latest neighboring cycle is chosen. For example,
in the following figure, the output TUSER sample of t=7 ns has equal distance to the input
samples at t=6 ns and t=8 ns, so the input sample of t=6 ns is chosen.
t f do ed nt
Figure 7: DFE Resampler 4/1 TUSER Resampling
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As a consequence of the above rules, a TLAST pulse does not always propagate with the same
latency as the accompanying TUSER sample. This is demonstrated in the previous figure at t=7
ns.
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In uplink mode, the sample rate at the output is always less than the sample rate at the input. The
TUSER rate change is handled by dropping TUSER samples. The core uses the following rules to
decide which TUSER samples to drop:
• When an output sample corresponds unambiguously to a closest single input sample, the
TUSER sample of the output sample will be the same as the corresponding TUSER input
sample.

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XILINX CONFIDENTIAL
• When an output sample is exactly mid-way between two input samples, the TUSER output
n
sample will be taken from the later of the two input samples. The TUSER input sample
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corresponding to the earlier input sample will be dropped. This scenario is illustrated in the
following figure, where the input TUSER sample at t=11.5 ns is dropped.
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Figure 8: DFE Resampler TUSER Drop, P=4 Q=5
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-D ea iro for
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Flow Control
The RFSoC DFE Resampler IP core does not support sample-by-sample flow control on either the
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input or output data interfaces. Once s_axis_din_tvalid is asserted, it should not drop to
C
zero without a system reset.
On the data output interface, m_axis_dout_tvalid is asserted to indicate that valid data is
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present on m_axis_dout_tdata on the current cycle.

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In the input data interface, s_axis_din_tvalid should be asserted to indicate that valid data
is present on s_axis_din_tdata. The core will not deassert s_axis_din_tready during
normal operation. Once s_axis_din_tvalid has been asserted, it should not subsequently be
deasserted without also resetting the core.
at

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n
Configuring and Controlling the Core
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Status and Error Events
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The RFSoC DFE Resampler IP core continuously monitors for error conditions and reports them
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by means of event signaling pins. Error events are reported as soon as possible after the point at
-D ea iro for
which they occur, but are not synchronized with the data sample stream in any way.
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If the internal FIFO suffers an over-run or an under-run, the fifo_error signal will be pulsed
Re es C In
for the duration of the overrun or under-run. Assertion of this signal indicates a problem with the
frequency ratio between s_axis_din_aclk and m_axis_dout_aclk. No over-runs or
under-runs are expected to be seen when the clocks are correctly configured. A fifo_error
or R to ial
will also be signaled if the s_axis_din_tvalid signal is unexpectedly deasserted during
normal operation, to indicate a flow-control problem.
t f do ed nt
If the internal filter datapath suffers an arithmetic overflow and clipping occurs, the overflow
signal will be pulsed for the duration of the clipping event.
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Low Power Mode

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The IP core GUI provides configuration options to control low power behavior. When this feature
is disabled, by setting the Low Power Trigger parameter to ‘disabled’, the core will never enter low
power mode.
El is o C
When entry into the low power mode is enabled, an additional parameter called TUSER Low
Power Bit allows a bit within the TUSER bus to be designated as the lower power mode trigger
bit.
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When Low Power Trigger is set to active-High mode, the presence of a logic 1 on the TUSER low
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power bit will cause the core to enter low power mode. When the TUSER low power bit returns
to logic 0, the core will re-enter the operational state.
The behavior in active-Low mode is reversed; the presence of a logic 0 will cause the core to
enter low power mode and a return to logic 1 will cause the core to become operational again.
Transitions into low power mode are observed on the m_axis_dout_tdata bus approximately
at
two input clocks and nine output clock cycles after the TUSER trigger. The approximation
uncertainty is caused by the CDC logic.
Transitions out of low power mode are observed on the m_axis_dout_tdata bus within a
range of (32 x OUTPUT_CLOCK_RATE/INPUT_CLOCK_RATE + 13) to (52 x
OUTPUT_CLOCK_RATE/INPUT_CLOCK_RATE + 53) output clock cycles, with the exact number
depending on the core configuration.

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XILINX CONFIDENTIAL
While in low power mode, the RFSoC DFE Resampler IP does not accept or produce new data.
n
The internal state of the filter pipeline is frozen and the output data bus is driven to a constant
rib I ma tio
value of 0 until the core exits from low power mode.
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ist rch Li ma
i o i tu
-D ea iro for
ut nst
Re es C In
or R to ial
t f do ed nt
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D
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D
at

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Chapter 5: Design Flow Steps
Chapter 5
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Design Flow Steps
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-D ea iro for
This section describes customizing and generating the core, constraining the core, and the
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simulation, synthesis, and implementation steps that are specific to this IP core. More detailed
information about the standard Vivado® design flows and the IP integrator can be found in the
Re es C In
following Vivado Design Suite user guides:
• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
or R to ial
• Vivado Design Suite User Guide: Designing with IP (UG896)
• Vivado Design Suite User Guide: Getting Started (UG910)
t f do ed nt
• Vivado Design Suite User Guide: Logic Simulation (UG900)
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Customizing and Generating the Core

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This section includes information about using Xilinx® tools to customize and generate the core in
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the Vivado® Design Suite.

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If you are customizing and generating the core in the Vivado IP integrator, see the Vivado Design
Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP
integrator might auto-compute certain configuration values when validating or generating the
D
design. To check whether the values do change, see the description of the parameter in this
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chapter. To view the parameter value, run the validate_bd_design command in the Tcl
D
console.
You can customize the IP for use in your design by specifying values for the various parameters
associated with the IP core using the following steps:
1. Select the IP from the IP catalog.

at
2. Double-click the selected IP or select the Customize IP command from the toolbar or right-
click menu.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado
Design Suite User Guide: Getting Started (UG910).
Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary
from the current version.

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Configuration Tab
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Figure 9: IP Configuration GUI
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• Direction: Whether the core is to operate in downlink or uplink mode. The range of options
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available for many other parameters of the core depend on this setting.
• Sample Width: The number of bits used to represent the I and Q components of the input and
output data samples. Switchable between 16 (the default) and 18 bits. In downlink mode, the
sample width is always 16 bits. In uplink mode, either 16 or 18 can be used.
• Number of channels: The core can provide filtering for up to eight antennas in parallel.
at
• Input samples per cycle: The number of input samples provided per antenna channel on each
clock cycle. In downlink mode, this is fixed at one. In uplink mode, it can be up to three.
• Output samples per cycle: The number of output samples the core will provide per antenna
channel on each clock cycle. This can be any value from 1 to 8.

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XILINX CONFIDENTIAL
• Rate change: The rate change is defined as the output sample rate divided by the input
n
sample rate. It can take a value of 2/3, 3/4, 4/5 or 5/6 in uplink mode, or 3/2, 2, 5/2, 3, 7/2,
rib I ma tio
4, 5 or 7 in downlink mode.
• TUSER Width: The number of bits per TUSER sample in the s_axis_din_tuser and
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ist rch Li ma
m_axis_dout_tuser buses. Valid values are 0 (for no TUSER bus) up to 64 bits. The default
is 8 bits.
i o i tu
• Low Power Polarity: Defines the nature of the trigger for entering and exiting the lower
-D ea iro for
power mode, or disables low power mode completely.
ut nst
• TUSER Low Power Bit: Defines which bit of the TUSER sample will be monitored to control
entry into and exit from the low power mode. This parameter is only shown when Low Power
Re es C In
Polarity is set to Active-High or Active-Low.
• Input clock rate: Specifies the frequency of s_axis_din_aclk, in MHz.

or R to ial
Given the input clock frequency, the rate change and the super sample-rate configuration
parameters, the GUI calculates and reports the output clock frequency according to the
t f do ed nt
following equation:
freq_out = freq_in * rate_change * input_samples_per_cycle /

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output_samples_per_cycle
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• Use BRAM: Determines whether the rate-change FIFO within the RFSoC DFE Resampler IP
will store sample data using block RAM (box checked) or distributed RAM (box not checked).
The choice of which RAM type to use depends on the resource usage constraints of the
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overall DFE design.

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• Deterministic Latency: When the box is checked, the core will include additional circuitry to
enforce a deterministic latency through the internal CDC FIFO. This enables the optional
SYSREF signals as described in the Deterministic Latency Mode section, which must be
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driven appropriately to set the latency.

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Power Estimation Tab

The RFSoC DFE Resampler IP supports power estimation. The Power Estimation Attributes tab
in the IP customization dialog, shown in the following figure, allows power estimation parameters
to be specified. The values set for these fields have no effect on the functionality of the core.
at
Figure 10: Power Estimation Tab

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XILINX CONFIDENTIAL
• Active Duty Cycle: The duty cycle of the core as a percentage, where 100% means the core is
n
always operational and 0% means the core is always deactivated.
rib I ma tio
User Parameters
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The following table shows the relationship between the fields in the Vivado® IDE and the user
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parameters (which can be viewed in the Tcl Console).
-D ea iro for
Table 3: User Parameters
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Vivado IDE Parameter/Value User Parameter/Value Default Value
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Direction MODE downlink
Number of channels NUM_CHANNELS 1
Sample width SAMPLE_WIDTH 16
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Input samples per cycle INPUT_SAMPLES_PER_CYCLE 1
Output samples per cycle OUTPUT_SAMPLES_PER_CYCLE 1
t f do ed nt
Rate change RATE_CHANGE 3/2
TUSER width TUSER_WIDTH 8
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Low power trigger LOWPOWER_POLARITY disabled

TUSER Low power bit TUSER_LOWPOWER_BIT 0
Input clock rate (MHz) INPUT_CLOCK_RATE 122.88
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Use BRAM USE_BRAM false

Deterministic Latency DETERMINISTIC_LATENCY false
Active Duty Cycle ACTIVE_DUTYCYCLE 100.00
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Output Generation
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For details, see the Vivado Design Suite User Guide: Designing with IP (UG896).
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Constraining the Core

Required Constraints
This section is not applicable for this IP core.

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Device, Package, and Speed Grade Selections

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XILINX CONFIDENTIAL
Clock Frequencies
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Clock Management
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Clock Placement
-D ea iro for
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Banking

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Transceiver Placement
t f do ed nt
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I/O Standard and Placement

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Simulation
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For comprehensive information about Vivado® simulation components, as well as information

about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation
D
(UG900).
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Synthesis and Implementation

For details about synthesis and implementation, see the Vivado Design Suite User Guide: Designing
with IP (UG896).
at

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Chapter 6: Example Design
Chapter 6
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Example Design
i o i tu
-D ea iro for
This chapter contains information about the RFSoC DFE Resampler example design provided in
ut nst
the Vivado® Design Suite.
Note: The example design is provided for simulation purposes only. Synthesis, implementation, and
Re es C In
bitstream generation are not supported.
or R to ial
Overview
t f do ed nt
The following figure shows the structure of the example design.
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Figure 11: Example Design

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<name>_exdes_tb
<name>_traffic_gen
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Data generator
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s_axis_din_aclk
Testbench
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s_sysref
generated DUT
m_axis_dout_aclk
clock
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m_sysref
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signals <name>_traffic_mon
sysref
Data monitor
X26043-120221
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The example design includes:

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XILINX CONFIDENTIAL
• <comp_name>_traffic_gen: A basic data generator to provide stimulus to the DUT. In each
n
channel the generated samples form a low-frequency sinusoid. Different channels have
rib I ma tio
different frequencies, and within each channel the Real and Imaginary part of the data have
opposite values. The amplitude is chosen such that the full dynamic range of the data bus is
exercised (either 16 or 18 bits depending on the parameter Sample Width). Depending on the
n te
ist rch Li ma
core configuration, the generator may bring the DUT to low-power mode and then back to
normal operation. TUSER and TLAST samples are generated arbitrarily.
i o i tu
• <comp_name>_traffic_mon: A basic data monitor to read the DUT outputs. It expects to
-D ea iro for
receive a sinusoid data sequence, and will generate a test error if the sequence does not
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appear to be sinusoid. The monitor performs a basic check of the sequence monotonicity.
Observing either an increasing or a decreasing sequence outside the signal maxima and
Re es C In
minima is an indication that the sequence appears to be sinusoid. Not observing a strict
monotonicity or not observing enough monotonic samples will lead to a test error.
• <comp_name>_exdes_tb: A platform to instantiate the DUT, data generator and data checker.
or R to ial
Clock and reset signals are generated here.
t f do ed nt
Running the Example Design

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To run the example design, select SIMULATION → Run Simulation → Run Behavioral Simulation

do cl nfi
from the Vivado Flow Navigator panel.
The test bench has up to three test phases, depending on whether the core's customization
El is o
parameters enable support for the low power mode. Control signals within the test bench are
used to set the active phase.
C
• Phase 1: Sinusoid data is sent, accompanied by occasional TUSER samples and TLAST pulses.
D
• Phase 2: If supported, the core enters Low Power mode. The bit of s_axis_din_tuser
specified by the TUSER Low Power Bit customization option is used to bring the core into and
AM
D
out of Low Power mode. The test will fail if the output data do not settle to zero a few cycles
after Low Power mode is entered.
• Phase 3: The core exits Low Power mode (if supported) and switches back to normal
operation. The test will expect to see sinusoid sequences again and will generate a test error if
they are not seen. A different TUSER sample is sent on each input clock cycle to demonstrate
how these samples are repeated or dropped as explained in the Latency Compensation for
at
TUSER and TLAST section.
A waveform configuration file is supplied (for the Vivado Simulator) which allows the input and
output data to be observed. The example simulator screenshots below show the results of a
simulation with the core configured as a 5/2 resampler with SSRO=2, in deterministic latency
mode.

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Figure 12: DFE Resampler Example Design Simulation: Input Data
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Figure 13: DFE Resampler Example Design Simulation: Output Data
t f do ed nt
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When the edges of the two input clock signals are aligned and the core is configured in
deterministic latency mode, then the input samples aligned with those clock edges will be neither
decimated nor interpolated and their latency can be determined accurately. The simulation will
report the latency of those samples.
at
It can be seen that the real part of the input sample (decimal value -9404) aligned with SYSREF at
t=18034.240 ns is observed on the output 62 m_axis_dout_aclk cycles later at t=18198.912
ns.

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Chapter 7: C Model
Chapter 7
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C Model
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-D ea iro for
The DFE Resampler bit-accurate C model is a self-contained, linkable, shared library that models
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the functionality of this core. The model performs fractional-rate resampling using the same
internal fixed-point arithmetic as the IP core and produces bit-accurate results. It is suitable for
Re es C In
inclusion in a larger framework for system-level simulation or core-specific verification.
or R to ial
Features
t f do ed nt
The C model has the following features:
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• Bit accurate with the RFSoC DFE Resampler core.

• Supports 64-bit Linux and 64-bit Windows platforms.
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• Transaction-based interface.
The DFE Resampler bit-accurate C model does not model flow control, latency, or other timing-
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related aspects of the RFSoC DFE Resampler IP core's operation.

C
D
Overview
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The model consists of a set of C functions that reside in a shared library. Example C code
demonstrates how these functions form the interface to the C model. An example piece of
source code showing how to call the model is provided. The model is also available as a
MATLAB® software MEX function for seamless MATLAB software integration.
The model is bit accurate but not cycle-accurate; it produces exactly the same output data as the
core on a sample-by-sample basis. However, it does not model the core latency or its interface
at
signals.
Related Information
C Model Interface

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Chapter 7: C Model
n
Unpacking and Model Contents
rib I ma tio
Unzip the DFE Resampler C model zip file for your platform. This produces the directory
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ist rch Li ma
structure and files shown in the following tables.
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Table 4: C Model Zip File Contents: Linux
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File Description
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xdfe_resampler_v1_0_bitacc_cmodel.h Header file which defines the DFE Resampler C model API.
xip_common_bitacc_cmodel.h Header file with common definitions.
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libIp_xdfe_resampler_v1_0_bitacc_cmodel.so Model shared object library.
run_bitacc_cmodel.c Example program for calling the C model.
or R to ial
xdfe_resampler_v1_0_bitacc_mex.cpp
@xdfe_resampler_v1_0_bitacc
MATLAB® MEX function source.
MATLAB MEX function class directory.
make_xdfe_resampler_v1_0_mex.m MATLAB compile script.
t f do ed nt
run_xdfe_resampler_v1_0_mex.m Example program for calling the MATLAB MEX function.
No ra os de
Table 5: C Model Zip File Contents: Windows
File Description
do cl nfi
xdfe_resampler_v1_0_bitacc_cmodel.h Header file which defines the DFE Resampler C model API.
xip_common_bitacc_cmodel.h Header file with common definitions.
El is o
libIp_xdfe_resampler_v1_0_bitacc_cmodel.dll Model dynamically linked library.

libIp_xdfe_resampler_v1_0_bitacc_cmodel.lib Model statically linked library.
C
run_bitacc_cmodel.c Example program for calling the C model.

xdfe_resampler_v1_0_bitacc_mex.cpp MATLAB MEX function source.
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@xdfe_resampler_v1_0_bitacc MATLAB MEX function class directory.

make_xdfe_resampler_v1_0_mex.m MATLAB compile script.
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run_xdfe_resampler_v1_0_mex.m Example program for calling the MATLAB MEX function.
Installation
at
Linux
• Unzip the contents of the ZIP file.

• Ensure that the directory containing the file
libIp_xdfe_resampler_v1_0_bitacc_cmodel.so is in your $LD_LIBRARY_PATH
environment variable.

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Chapter 7: C Model
Windows
n
rib I ma tio
• Unzip the contents of the ZIP file.
• Ensure that the directory containing the file
libIp_xdfe_resampler_v1_0_bitacc_cmodel.dll is:
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ist rch Li ma
○ Either in your %PATH% environment variable
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○ Or the directory from which you run your executable that calls the DFE Resampler C
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model.
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C Model Interface
or R to ial
The API of the C model is defined in the header file
xdfe_resampler_v1_0_bitacc_cmodel.h. This interface consists of data structures and
functions as described in the following sections. To use the C model:
t f do ed nt
1. Create a model configuration structure and initialize the values within it according to your
No ra os de
application.
2. Use this model configuration structure to create an instance of the model.
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3. Allocate and initialize arrays for input and output samples.

4. Call the 'do'-function of the model to process blocks of data.
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5. When finished, destroy the model instance and deallocate memory as necessary.
C
One call to xdfe_resampler_v1_0_do will process an arbitrary number of samples on one

antenna. To process data for additional antennas, make multiple calls to this function.
D
An example C++ file called run_bitacc_cmodel.c is included in the ZIP file. This
demonstrates how to call the DFE Resampler C model. Refer to this file for examples of using the
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interface described below.
Constants
The following constants are defined by the API:
at
Table 6: Constants
Name Value Notes

XDFE_RESAMPLER_V1_0_SAMPLE_WIDTH_UL 18 Supported sample width of the uplink
mode
XDFE_RESAMPLER_V1_0_SAMPLE_WIDTH_DL 16 Supported sample width of the downlink
mode
XDFE_RESAMPLER_V1_0_RESAMPLER_MODE_UL 0 Uplink mode of the resampler

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Chapter 7: C Model
n
Table 6: Constants (cont'd)
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Name Value Notes
XDFE_RESAMPLER_V1_0_RESAMPLER_MODE_DL 1 Downlink mode of the resampler
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XDFE_RESAMPLER_V1_0_RATE_CHANGE_UL_2_3 0 2/3 rate change in uplink mode of the
resampler
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XDFE_RESAMPLER_V1_0_RATE_CHANGE_DL_3_2 4 3/2 rate change in downlink mode of the
resampler
XDFE_RESAMPLER_V1_0_RATE_CHANGE_DL_2 5 2/1 rate change in downlink mode of the
resampler
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resampler
t f do ed nt
resampler
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resampler
resampler
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resampler
resampler
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Data Types
The following types are defined by the API:
D
Table 7: Data Type Definitions

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Name Description
Standard Types
xdfe_resampler_v1_0 Model object type (opaque to user)
xip_bit Single bit type
xip_uint Unsigned integer type
at
xip_status Result code from API functions; XIP_STATUS_OK,

XIP_STATUS_ERROR
xip_msg_handler Message handler function signature
Structures
xdfe_resampler_v1_0_config Model configuration parameters, see
xdfe_resampler_v1_0_config structure section
Dynamic Arrays
xip_array_complex Dynamic array of a standard type

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Chapter 7: C Model
Functions
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The C model provides the following functions:
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xdfe_resampler_v1_0_get_version
ist rch Li ma
Gets version of library.
i o i tu
-D ea iro for
Table 8: Returns
ut nst
Type Description
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const char* Textual representation of library version
xdfe_resampler_v1_0_default_config
or R to ial
Gets default configuration struct.
t f do ed nt
Table 9: Arguments
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Argument Name Type Description

config xdfe_resampler_v1_0_config*
do cl nfi
Table 10: Returns
Type Description
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xip_status Exit code

C
xdfe_resampler_v1_0_create
D
Creates a new instance of the model based on specified configuration.

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Table 11: Arguments

config const xdfe_resampler_v1_0_config* Model configuration structure
msg_handler xip_msg_handler Callback function for errors and
warnings
at
msg_handle void* Optional argument to be passed back

to callback function
Table 12: Returns
Type Description
xdfe_resampler_v1_0* Model instance handle

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Chapter 7: C Model
xdfe_resampler_v1_0_reset
n
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Resets an instance of the core.
Table 13: Arguments
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i o i tu
model xdfe_resampler_v1_0* Model instance handle
-D ea iro for
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Table 14: Returns
Type Description
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xdfe_resampler_v1_0_do
Filters supplied data using the specified component carrier configuration.
t f do ed nt
Table 15: Arguments
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do cl nfi
data_in const xip_array_complex* Input data

data_out xip_array_complex* Output data
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Table 16: Returns

C
Type Description
D

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xdfe_resampler_v1_0_destroy
D
Destroys model instance and free any resources allocated.
Table 17: Arguments

at
Table 18: Returns
Type Description

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Chapter 7: C Model
Structures
n
rib I ma tio
The following structures are defined by the API:
n te
xdfe_resampler_v1_0_config
ist rch Li ma
i o i tu
Field Name Type Description
name const char* Instance name
-D ea iro for
rate_change xip_uint Rate change of the resampler
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resample_mode xip_bit Resampler in uplink or downlink mode
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Compiling and Linking
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Place the header files (xdfe_resampler_v1_0_bitacc_cmodel.h and
t f do ed nt
xip_common_bitacc_cmodel.h) with other header files in your project.
No ra os de
Compilation varies from platform to platform but GCC 6.2.0 or later is recommended.
Linux
do cl nfi
To compile the example code, run_bitacc_cmodel.c, first ensure that the directory in which
the file libIp_xdfe_resampler_v1_0_bitacc_cmodel.so is located is present on your
El is o
$LD_LIBRARY_PATH environment variable. This shared library is referenced during the

C
compilation and linking process.
Place the header file and C++ source file in a single directory. Then in that directory, compile
D
using the GNU C++ Compiler:

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gcc -x c++ -I. -L. -lIp_xdfe_resampler_v1_0_bitacc_cmodel -Wl,-rpath,.-o

D
run_bitacc_cmodel run_bitacc_cmodel.c
Windows
When compiling on Windows, the symbol 'NT' must be defined either by a compiler option or in
the user source code before the xdfe_resampler_v1_0_bitacc_cmodel.h header file is
included.
at
Link to the import library libIp_xdfe_resampler_v1_0_bitacc_cmodel.lib. For

example, in Microsoft Visual Studio.NET, in Project Properties, under Linker → Input, for
Additional Dependencies, specify libIp_xdfe_resampler_v1_0_bitacc_cmodel.lib.

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Chapter 7: C Model
n
MATLAB Interface
rib I ma tio
A MEX function and MATLAB® software class are provided to simplify the integration with
n te
ist rch Li ma
MATLAB®. The MEX function provides a low-level wrapper around the underlying C model,
while the class file provides a convenient interface to the MEX function.
i o i tu
Compiling
-D ea iro for
ut nst
Source code for a MATLAB MEX function is provided. This can be compiled within MATLAB with
Re es C In
the use of a helper script make_xdfe_resampler_v1_0_mex.m. This script will use the
contents of the C Model zip file to create a MEX object that can then be used within MATLAB.
Compilation varies from platform to platform but GCC 6.2.0 or later is recommended.
or R to ial
Installation
t f do ed nt
To use the MEX function, it must first be compiled and must be present on the MATLAB search
No ra os de
path. This can be achieved in two ways:
1. Add the directory where the compiled MEX function is located to the MATLAB search path
do cl nfi
(see the MATLAB addpath function)

2. Copy the files to a location already on the MATAB search path.
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As with all uses of the C model, the correct C model libraries also need to be present on the
C
platform library search path, either PATH or LD_LIBRARY_PATH.
Running
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Once the MEX object has been compiled it can then be called by a MATLAB script via the
D
provided MATLAB class. The class provides an equivalent MATLAB function for each C Model
function in the API as well as an model object.
Calling these functions automatically translates the MATLAB data-types, passes them to the C
Model, and executes the relevant function. Memory allocation and deallocation within the C
Model is automatically taken care of.
at
An example script run_xdfe_resampler_v1_0_mex.m is provided to show how the MEX

object is called via the MATLAB class.

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Chapter 7: C Model
MATLAB Class
n
rib I ma tio
The @xdfe_resampler_v1_0_bitacc class handles the create/destroy semantics on the C
model. The class provides objects for each of the data, configuration and control structures,
n te
defined for the C model and previously described in Structures.
ist rch Li ma
The class provides methods equivalent to the C model functions previously described in
i o i tu
Functions.
-D ea iro for
All structure elements have MATLAB type double. MATLAB arrays are used with the mapping of
ut nst
types between MATLAB and the C model.
Re es C In
Table 19: MATLAB to C Model Type Mapping
or R to ial C Model Type MATLAB Type

xip_bit uint8
xip_uint uint32
t f do ed nt
xip_int int32
xip_real double
No ra os de
xip_complex complex double
Constructor
do cl nfi
[model]=xdfe_resampler_v1_0_bitacc
El is o
This method constructs a model object using the default configuration.

C
[model]=xdfe_resampler_v1_0_bitacc(config)
D
This method constructs a model object using the configuration structure passed in.
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Get Version
D
[version]=get_version(model)
This method returns the version string of the C model library used.
Default Config
at
[config]=default_config(model)
This method returns a configuration structure populated with the default values.

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XILINX CONFIDENTIAL
Chapter 7: C Model
Reset
n
rib I ma tio
reset(model)
This method resets the model as per the C model function.
n te
ist rch Li ma
Get Status
i o i tu
-D ea iro for
[status]=get_status(model)
ut nst
This method returns a status structure populated with the current status of the model. This also
clears the internal overflow status of the model.
Re es C In
Do
or R to ial
[dout]=do(model, data_in)
t f do ed nt
The first method passes a MATLAB complex double array and returns the output from the mixer.
The din input should be a 1-D MATLAB complex double array. The dout output will be a 1-D
No ra os de
MATLAB complex double array.
Destroy
do cl nfi
destroy(model)
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This method destroys the model instance and free any resources allocated.
C
D
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D
at

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XILINX CONFIDENTIAL
Appendix A: Debugging
Appendix A
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rib I ma tio
n te
ist rch Li ma
Debugging
i o i tu
-D ea iro for
This appendix includes details about resources available on the Xilinx® Support website and
ut nst
debugging tools.
If the IP requires a license key, the key must be verified. The Vivado® design tools have several
Re es C In
license checkpoints for gating licensed IP through the flow. If the license check succeeds, the IP
can continue generation. Otherwise, generation halts with an error. License checkpoints are
or R to ial
enforced by the following tools:
• Vivado Synthesis
t f do ed nt
• Vivado Implementation
• write_bitstream (Tcl command)
No ra os de
IMPORTANT! IP license level is ignored at checkpoints. The test confirms a valid license exists. It does not
check IP license level.
do cl nfi
El is o
Finding Help on Xilinx.com

C
To help in the design and debug process when using the core, the Xilinx Support web page
D
contains key resources such as product documentation, release notes, answer records,
information about known issues, and links for obtaining further product support. The Xilinx
AM
D
Community Forums are also available where members can learn, participate, share, and ask
questions about Xilinx solutions.
Documentation
This product guide is the main document associated with the core. This guide, along with
at
documentation related to all products that aid in the design process, can be found on the Xilinx
Support web page or by using the Xilinx® Documentation Navigator. Download the Xilinx
Documentation Navigator from the Downloads page. For more information about this tool and
the features available, open the online help after installation.

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XILINX CONFIDENTIAL
Technical Support
n
rib I ma tio
Xilinx provides technical support on the Xilinx Community Forums for this LogiCORE™ IP product
when used as described in the product documentation. Xilinx cannot guarantee timing,
n te
functionality, or support if you do any of the following:
ist rch Li ma
• Implement the solution in devices that are not defined in the documentation.
i o i tu
• Customize the solution beyond that allowed in the product documentation.
-D ea iro for
• Change any section of the design labeled DO NOT MODIFY.
ut nst
To ask questions, navigate to the Xilinx Community Forums.
Re es C In
Debug Tools
or R to ial
t f do ed nt
There are many tools available to address RFSoC DFE Resampler design issues. It is important to
know which tools are useful for debugging various situations.
No ra os de
Vivado Design Suite Debug Feature

do cl nfi
The Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly into
your design. The debug feature also allows you to set trigger conditions to capture application
and integrated block port signals in hardware. Captured signals can then be analyzed. This
El is o
feature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx®
C
devices.
The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores, including:
D
• ILA 2.0 (and later versions)

AM
D
• VIO 2.0 (and later versions)
See the Vivado Design Suite User Guide: Programming and Debugging (UG908).
Hardware Debug
at
Hardware issues can range from link bring-up to problems seen after hours of testing. This
section provides debug steps for common issues. The Vivado® debug feature is a valuable
resource to use in hardware debug. The signal names mentioned in the following individual
sections can be probed using the debug feature for debugging the specific problems.

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General Checks
n
rib I ma tio
Ensure that all the timing constraints for the core were properly incorporated from the example
design and that all constraints were met during implementation.
n te
ist rch Li ma
• Does it work in post-place and route timing simulation? If problems are seen in hardware but
not in timing simulation, this could indicate a PCB issue. Ensure that all clock sources are
i o i tu
active and clean.
-D ea iro for
• If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the
ut nst
locked port.
• If your outputs go to 0, check your licensing.
Re es C In
or R to ial
t f do ed nt
No ra os de
do cl nfi
El is o C
D
AM
D
at

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XILINX CONFIDENTIAL
Appendix B: Additional Resources and Legal Notices
Appendix B
n
rib I ma tio
n te
ist rch Li ma
Additional Resources and Legal
i o i tu
Notices
-D ea iro for
ut nst
Re es C In
Xilinx Resources
or R to ial
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
t f do ed nt
Support.
No ra os de
Documentation Navigator and Design Hubs

do cl nfi
Xilinx® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, and
support resources, which you can filter and search to find information. To open DocNav:
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• From the Vivado® IDE, select Help → Documentation and Tutorials.

• On Windows, select Start → All Programs → Xilinx Design Tools → DocNav.
D
• At the Linux command prompt, enter docnav.

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Xilinx Design Hubs provide links to documentation organized by design tasks and other topics,
D
which you can use to learn key concepts and address frequently asked questions. To access the
Design Hubs:
• In DocNav, click the Design Hubs View tab.

• On the Xilinx website, see the Design Hubs page.
at
Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.
References
These documents provide supplemental material useful with this guide:

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XILINX CONFIDENTIAL
1. Vivado Design Suite: AXI Reference Guide (UG1037)
n
2. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
rib I ma tio
3. Vivado Design Suite User Guide: Designing with IP (UG896)
n te
ist rch Li ma
4. Vivado Design Suite User Guide: Getting Started (UG910)
5. Vivado Design Suite User Guide: Logic Simulation (UG900)
i o i tu
-D ea iro for
ut nst
Revision History
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The following table shows the revision history for this document.
or R to ial Section
04/21/2022 Version 1.0
Revision Summary
t f do ed nt
Xilinx Confidential Draft. Approved for external release N/A
under NDA only.
No ra os de
Please Read: Important Legal Notices

do cl nfi
The information disclosed to you hereunder (the "Materials") is provided solely for the selection
El is o
and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are
made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND
C
CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO

WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY
D
PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
negligence, or under any other theory of liability) for any loss or damage of any kind or nature
AM
D
related to, arising under, or in connection with, the Materials (including your use of the
Materials), including for any direct, indirect, special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any
action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx
had been advised of the possibility of the same. Xilinx assumes no obligation to correct any
errors contained in the Materials or to notify you of updates to the Materials or to product
specifications. You may not reproduce, modify, distribute, or publicly display the Materials
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without prior written consent. Certain products are subject to the terms and conditions of
Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://
www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained
in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or
for use in any application requiring fail-safe performance; you assume sole risk and liability for
use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can
be viewed at https://www.xilinx.com/legal.htm#tos.

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AUTOMOTIVE APPLICATIONS DISCLAIMER
n
rib I ma tio
AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT
WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS
THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A
n te
ist rch Li ma
SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262
AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING
i o i tu
OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST
SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION
-D ea iro for
WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO
ut nst
APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT
LIABILITY.
Re es C In
Copyright
or R to ial
© Copyright 2022 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Kria, Spartan, Versal,
Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
t f do ed nt
in the United States and other countries. MATLAB and Simulink are registered trademarks of The
MathWorks, Inc. AMBA, AMBA Designer, Arm, ARM1176JZ-S, CoreSight, Cortex, PrimeCell,
Mali, and MPCore are trademarks of Arm Limited in the EU and other countries. All other
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trademarks are the property of their respective owners.

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XILINX CONFIDENTIAL

RFSoC DFE Resampler v1.0

Xilinx is creating an environment where employees, customers, and

Chapter 4: Designing with the Core................................................................... 14

Configuring and Controlling the Core.................................................................................... 22

Chapter 5: Design Flow Steps.................................................................................24

Chapter 6: Example Design..................................................................................... 29

PG392 (v1.0) April 21, 2022 www.xilinx.com

Appendix B: Additional Resources and Legal Notices............................. 45

Please Read: Important Legal Notices................................................................................... 46

PG392 (v1.0) April 21, 2022 www.xilinx.com

• Supports up to eight antennas (channels) per instance

• Latency-compensated sideband channel (TUSER) for sample-accurate framing

• Optional deterministic latency operating mode

PG392 (v1.0) April 21, 2022 www.xilinx.com

Design Entry Vivado® Design Suite

All Vivado IP Change Logs Master Vivado IP Change Logs: 72775

PG392 (v1.0) April 21, 2022 www.xilinx.com

An overview of the core functional structure is shown in the following figure.

Figure 1: Core Functional Overview

s_axis_din_aclk domain m_axis_dout_aclk domain

PG392 (v1.0) April 21, 2022 www.xilinx.com

Licensing and Ordering

PG392 (v1.0) April 21, 2022 www.xilinx.com

Table 1: Resampler Latencies: Uplink Modes

P Q SSRI SSRO D ND P Q SSRI SSRO D ND

PG392 (v1.0) April 21, 2022 www.xilinx.com

PG392 (v1.0) April 21, 2022 www.xilinx.com

3 1 1 1 123 117 7 1 1 1 295 285

PG392 (v1.0) April 21, 2022 www.xilinx.com

Figure 2: Core Ports

The signals s_sysref, m_sysref, s_latency_status, and m_latency_status are only

Data Input Interface Ports

Port Name I/O Clock Description

24 for 18-bit samples), the number of antennas NA,

The upstream logic uses this to signal that it

core does not rely on this signal for operation, but

s_axis_din_tuser[UW*SSRI-1:0] I s_axis_din_aclk User-defined framing information. The width of

Data Output Interface Ports

PG392 (v1.0) April 21, 2022 www.xilinx.com

Deterministic Latency Ports

Port name I/O Clock Description

s_sysref I s_axis_din_aclk System timing reference pulse in input

m_sysref I m_axis_dout_aclk System timing reference pulse in output

s_latency_status O s_axis_din_aclk Status of deterministic latency

The value is initially 0 after reset, rising to 1

when the deterministic latency

Clock and Reset Ports

PG392 (v1.0) April 21, 2022 www.xilinx.com

PG392 (v1.0) April 21, 2022 www.xilinx.com

Make Only Allowed Modifications

PG392 (v1.0) April 21, 2022 www.xilinx.com

Interfacing to the Core

PG392 (v1.0) April 21, 2022 www.xilinx.com

Figure 3: Data Format

Deterministic Latency Mode

PG392 (v1.0) April 21, 2022 www.xilinx.com

Latency Compensation for TUSER and TLAST

PG392 (v1.0) April 21, 2022 www.xilinx.com

• TLAST at the output is always a single cycle pulse.

the second, the input TLAST pulse is at t=13.5 ns.

PG392 (v1.0) April 21, 2022 www.xilinx.com

Figure 6: DFE Resampler TLAST Positions