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Features
· Operating voltage: · Up to 0.5ms instruction cycle with 8MHz system clock
fSYS=4MHz: VLVR~5.5V with LVR enabled at VDD=5V
fSYS=8MHz: 3.3V~5.5V with LVR disabled · 6-level subroutine nesting
· 13 bidirectional I/O lines (max.) · 4 channels 9-bit resolution A/D converter
· 1 interrupt input shared with an I/O line · 1 channel 8-bit PWM output shared with an I/O line
· 8-bit programmable timer/event counter with overflow · Bit manipulation instruction
interrupt and 7-stage prescaler · 14-bit table read instruction
· On-chip crystal and RC oscillator
· 63 powerful instructions
· Watchdog Timer
· All instructions in one or two machine cycles
· 2048´14 program memory
· Low voltage reset function
· 64´8 data memory RAM · 18-pin DIP/SOP package
· Supports PFD for sound generation
· HALT function and wake-up feature reduce power
consumption
General Description
The HT46R47-H is an 8-bit high performance, RISC ar- tions, enhance the versatility of these devices to suit a
chitecture microcontroller devices specifically designed wide range of A/D application possibilities such as sen-
for A/D applications that interface directly to analog sig- sor signal processing, motor driving, industrial control,
nals, such as those from sensors. consumer products, subsystem controllers, etc.
The advantages of low power consumption, I/O flexibil- The higher operating voltage range and higher operat-
ity, programmable frequency divider, timer functions, ing temperature range of -40°C to +125°C for the
oscillator options, multi-channel A/D Converter, Pulse HT46R47-H make this series suitable for automotive ap-
Width Modulation function, HALT and wake-up func- plications as well.
Block Diagram
P A 5 /IN T
In te rru p t
C ir c u it
M P r e s c a le r fS Y S
S T A C K T M R C
U
P ro g ra m P ro g ra m IN T C X P A 4 /T M R
T M R
R O M C o u n te r
P A 3 /P F D P A 4
M fS Y S /4
In s tr u c tio n W D T U
R e g is te r M P M D A T A W D T O S C
X
U M e m o ry
X
P W M
P D C P o rt D
P D 0 /P W M
P D
In s tr u c tio n M U X
D e c o d e r 4 -C h a n n e l
A /D C o n v e rte r
A L U S T A T U S
P B C P o rt B
P B 0 /A N 0 ~ P B 3 /A N 3
T im in g S h ifte r
P B
G e n e ra to r
P A 3 , P A 5
P A 0 ~ P A 2
P A C P o rt A P A 3 /P F D
P A 4 /T M R
O S C 2 O S C 1 A C C L V R P A P A 5 /IN T
R E S P A 6 ~ P A 7
V D D
V S S
Pin Assignment
P A 3 /P F D 1 1 8 P A 4 /T M R
P A 2 2 1 7 P A 5 /IN T
P A 1 3 1 6 P A 6
P A 0 4 1 5 P A 7
P B 3 /A N 3 5 1 4 O S C 2
P B 2 /A N 2 6 1 3 O S C 1
P B 1 /A N 1 7 1 2 V D D
P B 0 /A N 0 8 1 1 R E S
V S S 9 1 0 P D 0 /P W M
H T 4 6 R 4 7 -H
1 8 D IP -A /S O P -A
Pin Description
Pin Name I/O Options Description
PA0~PA2 Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
PA3/PFD Pull-high input by options. Software instructions determine the CMOS output or Schmitt
PA4/TMR I/O Wake-up trigger input with or without pull-high resistor (determined by pull-high options: bit
PA5/INT PA3 or PFD option). The PFD, TMR and INT are pin-shared with PA3, PA4 and PA5, re-
PA6, PA7 spectively.
Bidirectional 4-bit input/output port. Software instructions determine the
PB0/AN0
CMOS output, Schmitt trigger input with or without pull-high resistor (deter-
PB1/AN1
I/O Pull-high mined by pull-high options: bit option) or A/D input.
PB2/AN2
Once a PB line is selected as an A/D input (by using software control), the I/O
PB3/AN3
function and pull-high resistor are disabled automatically.
Bidirectional I/O line. Software instructions determine the CMOS output,
Pull-high Schmitt trigger input with or without a pull-high resistor (determined by
PD0/PWM I/O
PD0 or PWM pull-high options: bit option). The PWM output function is pin-shared with
PD0 (dependent on PWM options).
RES I ¾ Schmitt trigger reset input. Active low.
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
fSYS=4MHz, LVR enabled VLVR ¾ 5.5 V
VDD Operating Voltage ¾
fSYS=8MHz, LVR disabled 3.3 ¾ 5.5 V
No load, fSYS=4MHz
IDD1 Operating Current (Crystal OSC) 5V ¾ 2 4 mA
ADC disabled
No load, fSYS=4MHz
IDD2 Operating Current (RC OSC) 5V ¾ 2.5 4 mA
ADC disabled
Operating Current No load, fSYS=8MHz
IDD3 5V ¾ 4 8 mA
(Crystal OSC, RC OSC) ADC disabled
ISTB1 Standby Current (WDT Enabled) 5V No load, system HALT ¾ ¾ 10 mA
ISTB2 Standby Current (WDT Disabled) 5V No load, system HALT ¾ ¾ 2 mA
Input Low Voltage for I/O Ports,
VIL1 ¾ ¾ 0 ¾ 0.3VDD V
TMR and INT
Input High Voltage for I/O Ports,
VIH1 ¾ ¾ 0.7VDD ¾ VDD V
TMR and INT
VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.4VDD V
VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V
VLVR Low Voltage Reset ¾ ¾ 3.4 3.8 4.2 V
IOL I/O Port Sink Current 5V VOL=0.1VDD 10 20 ¾ mA
IOH I/O Port Source Current 5V VOH=0.9VDD -5 -10 ¾ mA
RPH Pull-high Resistance 5V ¾ 10 30 50 kW
VAD A/D Input Voltage ¾ ¾ 0 ¾ VDD V
EAD A/D Conversion Error ¾ ¾ ¾ ±0.5 ±1 LSB
Additional Power Consumption
IADC 5V ¾ ¾ 1.5 3 mA
if A/D Converter is Used
Ta=125°C
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
fSYS=4MHz, LVR enabled VLVR ¾ 5.5 V
VDD Operating Voltage ¾
fSYS=8MHz, LVR disabled 3.3 ¾ 5.5 V
Operating Current No load, fSYS=4MHz
IDD1 5V ¾ 2.5 4 mA
(Crystal OSC, RC OSC) ADC disabled
Operating Current No load, fSYS=8MHz
IDD2 5V ¾ 4 8 mA
(Crystal OSC, RC OSC) ADC disabled
ISTB1 Standby Current (WDT Enabled) 5V No load, system HALT ¾ ¾ 40 mA
ISTB2 Standby Current (WDT Disabled) 5V No load, system HALT ¾ ¾ 30 mA
Input Low Voltage for I/O Ports,
VIL1 ¾ ¾ 0 ¾ 0.3VDD V
TMR and INT
Input High Voltage for I/O Ports,
VIH1 ¾ ¾ 0.7VDD ¾ VDD V
TMR and INT
VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.4VDD V
VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V
VLVR Low Voltage Reset ¾ ¾ 2.4 2.7 2.9 V
IOL I/O Port Sink Current 5V VOL=0.1VDD 7.5 15 ¾ mA
IOH I/O Port Source Current 5V VOH=0.9VDD -5 -10 ¾ mA
RPH Pull-high Resistance of I/O Ports 5V ¾ 15 40 60 kW
VAD A/D Input Voltage ¾ ¾ 0 ¾ VDD V
EAD A/D Conversion Error 5V ¾ ¾ ±1 ±2 LSB
Additional Power Consumption
IADC 5V ¾ ¾ 1.5 3 mA
if A/D Converter is Used
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VLVR~5.5V, LVR enabled 400 ¾ 4000 kHz
fSYS System Clock ¾
3.3V~5.5V, LVR disabled 400 ¾ 8000 kHz
VLVR~5.5V, LVR enabled 0 ¾ 4000 kHz
fTIMER Timer I/P Frequency (TMR) ¾
3.3V~5.5V, LVR disabled 0 ¾ 8000 kHz
tWDTOSC Watchdog Oscillator Period 5V ¾ 32 65 130 ms
15 16
tWDT1 Watchdog Time-out Period (RC) ¾ ¾ 2 ¾ 2 tWDTOSC
Note: *tSYS=1/fSYS
Ta=125°C
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VLVR~5.5V, LVR enabled 400 ¾ 4000 kHz
fSYS System Clock ¾
3.3V~5.5V, LVR disabled 400 ¾ 8000 kHz
VLVR~5.5V, LVR enabled 0 ¾ 4000 kHz
fTIMER Timer I/P Frequency (TMR) ¾
3.3V~5.5V, LVR disabled 0 ¾ 8000 kHz
tWDTOSC Watchdog Oscillator Period 5V ¾ 60 110 200 ms
15 16
tWDT1 Watchdog Time-out Period (RC) ¾ ¾ 2 ¾ 2 tWDTOSC
Note: *tSYS=1/fSYS
Functional Description
Execution Flow incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is When executing a jump instruction, conditional skip ex-
internally divided into four non-overlapping clocks. One ecution, loading PCL register, subroutine call, initial re-
instruction cycle consists of four system clock cycles. set, internal interrupt, external interrupt or return from
Instruction fetching and execution are pipelined in such subroutine, the PC manipulates the program transfer by
a way that a fetch takes an instruction cycle while de- loading the address corresponding to each instruction.
coding and execution takes the next instruction cycle. The conditional skip is activated by instructions. Once
However, the pipelining scheme causes each instruc- the condition is met, the next instruction, fetched during
tion to effectively execute in a cycle. If an instruction the current instruction execution, is discarded and a
changes the program counter, two cycles are required to dummy cycle replaces it to get the proper instruction.
complete the instruction. Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
Program Counter - PC
able and writeable register (06H). Moving data into the
The program counter (PC) controls the sequence in PCL performs a short jump. The destination will be
which the instructions stored in program ROM are exe- within 256 locations.
cuted and its contents specify full range of program
When a control transfer takes place, an additional
memory.
dummy cycle is required.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4
S y s te m C lo c k
O S C 2 (R C o n ly )
P C P C P C + 1 P C + 2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
Mode
*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset 0 0 0 0 0 0 0 0 0 0 0
External Interrupt 0 0 0 0 0 0 0 0 1 0 0
Timer/Event Counter Overflow 0 0 0 0 0 0 0 1 0 0 0
A/D Converter Interrupt 0 0 0 0 0 0 0 1 1 0 0
Skip Program Counter+2
Loading PCL *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program Counter
0 0 0 H
Program Memory - ROM D e v ic e In itia liz a tio n P r o g r a m
· Table location
Stack Register - STACK
Any location in the ROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the This is a special part of the memory which is used to
current page, 1 page=256 words) and ²TABRDL [m]² save the contents of the program counter only. The
(the last page) transfer the contents of the lower-order stack is organized into 6 levels and are neither part of
byte to the specified data memory, and the the data nor part of the program space, and is neither
higher-order byte to TBLH (08H). Only the destination readable nor writeable. The activated level is indexed by
of the lower-order byte in the table is well-defined, the the stack pointer (SP) and is neither readable nor
other bits of the table word are transferred to the lower writeable. At a subroutine call or interrupt acknowledg-
portion of TBLH, and the remaining 2 bits are read as ment, the contents of the program counter are pushed
²0². The Table Higher-order byte register (TBLH) is onto the stack. At the end of a subroutine or an interrupt
read only. The table pointer (TBLP) is a read/write
routine, signaled by a return instruction (RET or RETI),
register (07H), which indicates the table location.
the program counter is restored to its previous value
Before accessing the table, the location must be
placed in TBLP. The TBLH is read only and cannot be from the stack. After a chip reset, the SP will point to the
restored. If the main routine and the ISR (Interrupt top of the stack.
Table Location
Instruction
*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
TABRDC [m] P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0
Table Location
Note: *10~*0: Table location bits P10~P8: Current program counter bits
@7~@0: Table pointer bits
If the stack is full and a non-masked interrupt takes The special function registers include the indirect ad-
place, the interrupt request flag will be recorded but the dressing register (00H), timer/event counter
acknowledgment will be inhibited. When the stack (TMR;0DH), timer/event counter control register
pointer is decremented (by RET or RETI), the interrupt (TMRC;0EH), program counter lower-order byte regis-
will be serviced. This feature prevents stack overflow al- ter (PCL;06H), memory pointer register (MP;01H), ac-
lowing the programmer to use the structure more easily. cumulator (ACC;05H), table pointer (TBLP;07H), table
In a similar case, if the stack is full and a ²CALL² is sub- higher-order byte register (TBLH;08H), status register
sequently executed, stack overflow occurs and the first (STATUS;0AH), interrupt control register (INTC;0BH),
entry will be lost (only the most recent 6 return ad- PWM data register (PWM;1AH), the A/D result
dresses are stored). lower-order byte register (ADRL;20H), the A/D result
higher-order byte register (ADRH;21H), the A/D control
Data Memory - RAM register (ADCR;22H), the A/D clock setting register
(ACSR;23H), I/O registers (PA;12H, PB;14H, PD;18H)
The data memory is designed with 85´8 bits. The data
and I/O control registers (PAC;13H, PBC;15H,
memory is divided into two functional groups: special
PDC;19H). The remaining space before the 40H is re-
function registers and general purpose data memory
served for future expanded usage and reading these lo-
(64´8). Most are read/write, but some are read only.
cations will get ²00H². The general purpose data
0 0 H In d ir e c t A d d r e s s in g R e g is te r
memory, addressed from 40H to 7FH, is used for data
0 1 H M P
and control information under instruction commands.
0 2 H
0 3 H All of the data memory areas can handle arithmetic,
0 4 H logic, increment, decrement and rotate operations di-
0 5 H A C C rectly. Except for some dedicated bits, each bit in the
0 6 H P C L data memory can be set and reset by ²SET [m].i² and
0 7 H T B L P
²CLR [m].i². They are also indirectly accessible through
0 8 H T B L H
memory pointer register (MP;01H).
0 9 H
0 A H S T A T U S
Indirect Addressing Register
0 B H IN T C
0 C H Location 00H is an indirect addressing register that is
0 D H T M R not physically implemented. Any read/write operation of
0 E H T M R C [00H] accesses data memory pointed to by MP (01H).
0 F H Reading location 00H itself indirectly will return the re-
1 0 H sult 00H. Writing indirectly results in no operation.
1 1 H S p e c ia l P u r p o s e
1 2 H P A D a ta M e m o ry The memory pointer register MP (01H) is a 7-bit register.
1 3 H P A C The bit 7 of MP is undefined and reading will return the
1 4 H P B result ²1². Any writing operation to MP will only transfer the
1 5 H P B C lower 7-bit data to MP.
1 6 H
1 7 H Accumulator
1 8 H P D
The accumulator is closely related to ALU operations. It
1 9 H P D C
is also mapped to location 05H of the data memory and
1 A H P W M
can carry out immediate data operations. The data
1 B H
1 C H movement between two data memory locations must
1 D H pass through the accumulator.
1 E H
1 F H Arithmetic and Logic Unit - ALU
2 0 H A D R L This circuit performs 8-bit arithmetic and logic opera-
2 1 H A D R H tions. The ALU provides the following functions:
2 2 H A D C R
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
2 3 H A C S R
2 4 H · Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
3 F H
4 0 H · Increment and Decrement (INC, DEC)
G e n e ra l P u rp o s e
D a ta M e m o ry : U n u s e d · Branch decision (SZ, SNZ, SIZ, SDZ ....)
(6 4 B y te s )
R e a d a s "0 0 " The ALU not only saves the results of a data operation but
7 F H
also changes the status register.
RAM Mapping
Status Register - STATUS terrupt requires servicing within the service routine, the
This 8-bit register (0AH) contains the zero flag (Z), carry EMI bit and the corresponding bit of INTC may be set to
flag (C), auxiliary carry flag (AC), overflow flag (OV), allow interrupt nesting. If the stack is full, the interrupt re-
power down flag (PDF), and watchdog time-out flag quest will not be acknowledged, even if the related inter-
(TO). It also records the status information and controls rupt is enabled, until the SP is decremented. If immediate
the operation sequence. service is desired, the stack must be prevented from be-
coming full.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like All these kinds of interrupts have a wake-up capability.
most other registers. Any data written into the status As an interrupt is serviced, a control transfer occurs by
register will not change the TO or PDF flag. In addi- pushing the program counter onto the stack, followed by
tion operations related to the status register may give a branch to a subroutine at specified location in the pro-
different results from those intended. The TO flag gram memory. Only the program counter is pushed onto
can be affected only by system power-up, a WDT the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
time-out or executing the ²CLR WDT² or ²HALT² in-
which corrupts the desired control sequence, the con-
struction. The PDF flag can be affected only by exe-
tents should be saved in advance.
cuting the ²HALT² or ²CLR WDT² instruction or a
system power-up. External interrupts are triggered by a high to low transi-
tion of INT and the related interrupt request flag (EIF; bit
The Z, OV, AC and C flags generally reflect the status of
4 of INTC) will be set. When the interrupt is enabled, the
the latest operations.
stack is not full and the external interrupt is active, a sub-
In addition, on entering the interrupt sequence or exe- routine call to location 04H will occur. The interrupt re-
cuting the subroutine call, the status register will not be quest flag (EIF) and EMI bits will be cleared to disable
pushed onto the stack automatically. If the contents of other interrupts.
the status are important and if the subroutine can cor-
The internal timer/event counter interrupt is initialized by
rupt the status register, precautions must be taken to
setting the timer/event counter interrupt request flag
save it properly.
(TF;bit 5 of INTC), caused by a timer overflow. When the
Interrupt interrupt is enabled, the stack is not full and the TF bit is
set, a subroutine call to location 08H will occur. The re-
The device provides an external interrupt, internal lated interrupt request flag (TF) will be reset and the EMI
timer/event counter interrupt and A/D converter inter- bit cleared to disable further interrupts.
rupts. The Interrupt Control Register (INTC;0BH) con-
tains the interrupt control bits to set the enable or disable The A/D converter interrupt is initialized by setting the
and the interrupt request flags. A/D converter request flag (ADF; bit 6 of INTC), caused
by an end of A/D conversion. When the interrupt is en-
Once an interrupt subroutine is serviced, all the other in- abled, the stack is not full and the ADF is set, a subrou-
terrupts will be blocked (by clearing the EMI bit). This tine call to location 0CH will occur. The related interrupt
scheme may prevent any further interrupt nesting. Other request flag (ADF) will be reset and the EMI bit cleared
interrupt requests may happen during this interval but to disable further interrupts.
only the interrupt request flag is recorded. If a certain in-
RETI may be invoked. RETI will set the EMI bit to enable
an interrupt service, but RET will not.
O S C 2 fS Y S /4 O S C 2
Interrupts, occurring in the interval between the rising N M O S O p e n D r a in
edges of two consecutive T2 pulses, will be serviced on C r y s ta l O s c illa to r R C O s c illa to r
the latter of the two T2 pulses, if the corresponding inter- System Oscillator
rupts are enabled. In the case of simultaneous requests
Both are designed for system clocks, namely the RC os-
the following table shows the priority that is applied.
cillator and the Crystal oscillator, which are determined
These can be masked by resetting the EMI bit.
by the options. No matter what oscillator type is se-
Interrupt Source Priority Vector lected, the signal provides the system clock. The HALT
mode stops the system oscillator and ignores an exter-
External Interrupt 1 04H
nal signal to conserve power.
Timer/Event Counter Overflow 2 08H
If an RC oscillator is used, an external resistor between
A/D Converter Interrupt 3 0CH OSC1 and VSS is required and the resistance must
range from 30kW to 750kW. The system clock, divided
The timer/event counter interrupt request flag (TF), ex-
by 4, is available on OSC2, which can be used to syn-
ternal interrupt request flag (EIF), A/D converter request
chronize external logic. The RC oscillator provides the
flag (ADF), enable timer/event counter bit (ETI), enable
most cost effective solution. However, the frequency of
external interrupt bit (EEI), enable A/D converter inter-
oscillation may vary with VDD, temperatures and the
rupt bit (EADI) and enable master interrupt bit (EMI)
chip itself due to process variations. It is, therefore, not
constitute an interrupt control register (INTC) which is
suitable for timing sensitive operations where an accu-
located at 0BH in the data memory. EMI, EEI, ETI, EADI
rate oscillator frequency is desired.
are used to control the enabling/disabling of interrupts.
These bits prevent the requested interrupt from being If the Crystal oscillator is used, a crystal across OSC1
serviced. Once the interrupt request flags (TF, EIF, ADF) and OSC2 is needed to provide the feedback and phase
are set, they will remain in the INTC register until the in- shift required for the oscillator, and no other external
terrupts are serviced or cleared by a software instruc- components are required. Instead of a crystal, a resona-
tion. tor can also be connected between OSC1 and OSC2 to
get a frequency reference, but two external capacitors in
It is recommended that a program does not use the CALL
OSC1 and OSC2 are required (If the oscillating fre-
subroutine within the interrupt subroutine. Interrupts of-
quency is less than 1MHz).
ten occur in an unpredictable manner or need to be ser-
viced immediately in some applications. If only one stack The WDT oscillator is a free running on-chip RC oscilla-
is left and enabling the interrupt is not well controlled, the tor, and no external components are required. Even if
original control sequence will be damaged once the the system enters the power down mode, the system
²CALL² operates in the interrupt subroutine. clock is stopped, but the WDT oscillator still works with a
period of approximately 65ms at 5V. The WDT oscillator
can be disabled by options to conserve power.
Watchdog Timer - WDT · The contents of the on chip RAM and registers remain
unchanged.
The clock source of WDT is implemented by a dedicated
· WDT will be cleared and recounted again (if the WDT
RC oscillator (WDT oscillator) or instruction clock (sys-
clock is from the WDT oscillator).
tem clock divided by 4), decided by options. This timer is
· All of the I/O ports maintain their original status.
designed to prevent a software malfunction or sequence
from jumping to an unknown location with unpredictable · The PDF flag is set and the TO flag is cleared.
results. The Watchdog Timer can be disabled by an op- The system can leave the HALT mode by means of an
tion. If the Watchdog Timer is disabled, all the execu- external reset, an interrupt, an external falling edge sig-
tions related to the WDT result in no operation. nal on port A or a WDT overflow. An external reset
Once the internal oscillator (RC oscillator with a period causes a device initialization and the WDT overflow per-
of 65ms at 5V normally) is selected, it is divided by forms a ²warm reset². After the TO and PDF flags are
32768~65536 to get the time-out period of approxi- examined, the reason for chip reset can be determined.
mately 2.1s~4.3s. This time-out period may vary with The PDF flag is cleared by system power-up or execut-
temperatures, VDD and process variations. If the WDT ing the ²CLR WDT² instruction and is set when execut-
oscillator is disabled, the WDT clock may still come from ing the ²HALT² instruction. The TO flag is set if the WDT
the instruction clock and operate in the same manner time-out occurs, and causes a wake-up that only resets
except that in the HALT state the WDT may stop count- the program counter and SP; the others keep their origi-
ing and lose its protecting purpose. In this situation the nal status.
logic can only be restarted by external logic. The port A wake-up and interrupt methods can be con-
If the device operates in a noisy environment, using the sidered as a continuation of normal execution. Each bit
on-chip RC oscillator (WDT OSC) is strongly recom- in port A can be independently selected to wake up the
mended, since the HALT will stop the system clock. device by the options. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
The WDT overflow under normal operation will initialize
struction. If it is awakening from an interrupt, two
²chip reset² and set the status bit ²TO². But in the HALT
sequences may happen. If the related interrupt is dis-
mode, the overflow will initialize a ²warm reset², and
abled or the interrupt is enabled but the stack is full, the
only the program counter and SP are reset to zero. To
program will resume execution at the next instruction. If
clear the contents of WDT, three methods are adopted;
the interrupt is enabled and the stack is not full, the regu-
external reset (a low level to RES), software instruction
lar interrupt response takes place. If an interrupt request
and a HALT instruction. The software instruction include
flag is set to ²1² before entering the HALT mode, the
²CLR WDT² and the other set - ²CLR WDT1² and ²CLR
wake-up function of the related interrupt will be disabled.
WDT2². Of these two types of instruction, only one can
Once a wake-up event occurs, it takes 1024 tSYS (sys-
be active depending on the options - ²CLR WDT times tem clock period) to resume normal operation. In other
selection option². If the ²CLR WDT² is selected (i.e. CLR words, a dummy period will be inserted after wake-up. If
WDT times equal one), any execution of the ²CLR the wake-up results from an interrupt acknowledgment,
WDT² instruction will clear the WDT. In the case that the actual interrupt subroutine execution will be delayed
²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLR by one or more cycles. If the wake-up results in the next
WDT times equal two), these two instructions must be instruction execution, this will be executed immediately
executed to clear the WDT; otherwise, the WDT may re- after the dummy period is finished.
set the chip as a result of time-out.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction Reset
and results in the following... There are three ways in which a reset can occur:
· The system oscillator will be turned off but the WDT · RES reset during normal operation
oscillator keeps running (if the WDT oscillator is se-
· RES reset during HALT
lected).
· WDT time-out reset during normal operation
S y s te m C lo c k /4
O p tio n fS W D T T im e - o u t
8 - b it C o u n te r 7 - b it C o u n te r T T 1 5 1 6
S e le c t fS /2 ~ fS /2
W D T
O S C C L R W D T
Watchdog Timer
0 .0 1 m F *
TO PDF RESET Conditions
0 0 RES reset during power-up 1 0 0 k W
Timer/Event Counter The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
A timer/event counter (TMR) is implemented in the
which means the clock source comes from an external
microcontroller. The timer/event counter contains an
(TMR) pin. The timer mode functions as a normal timer
8-bit programmable count-up counter and the clock may
with the clock source coming from the fINT clock. The
come from an external source or the system clock.
pulse width measurement mode can be used to count the
Using external clock input allows the user to count exter- high or low level duration of the external signal (TMR). The
nal events, measure time internals or pulse widths, or counting is based on the fINT.
generate an accurate time base. While using the inter-
nal clock allows the user to generate an accurate time In the event count or timer mode, once the timer/event
base. counter starts counting, it will count from the current
contents in the timer/event counter to FFH. Once over-
The timer/event counter can generate PFD signal by us- flow occurs, the counter is reloaded from the timer/event
ing external or internal clock and PFD frequency is de- counter preload register and generates the interrupt re-
termine by the equation fINT/[2´(256-N)]. quest flag (TF; bit 5 of INTC) at the same time.
There are 2 registers related to the timer/event counter; In the pulse width measurement mode with the TON
TMR ([0DH]), TMRC ([0EH]). Two physical registers are and TE bits equal to one, once the TMR has received a
mapped to TMR location; writing TMR makes the start- transient from low to high (or high to low if the TE bits is
ing value be placed in the timer/event counter preload ²0²) it will start counting until the TMR returns to the orig-
register and reading TMR retrieves the contents of the inal level and resets the TON. The measured result will
timer/event counter. The TMRC is a timer/event counter remain in the timer/event counter even if the activated
control register, which defines some options.
transient occurs again. In other words, only one cycle In the case of timer/event counter OFF condition, writing
measurement can be done. Until setting the TON, the data to the timer/event counter preload register will also
cycle measurement will function again as long as it re- reload that data to the timer/event counter. But if the
ceives further transient pulse. Note that, in this operat- timer/event counter is turned on, data written to it will
ing mode, the timer/event counter starts counting not only be kept in the timer/event counter preload register.
according to the logic level but according to the transient The timer/event counter will still operate until overflow
edges. In the case of counter overflows, the counter is occurs. When the timer/event counter (reading TMR) is
reloaded from the timer/event counter preload register read, the clock will be blocked to avoid errors. As clock
and issues the interrupt request just like the other two blocking may results in a counting error, this must be
modes. To enable the counting operation, the timer ON taken into consideration by the programmer.
bit (TON; bit 4 of TMRC) should be set to 1. In the pulse The bit0~bit2 of the TMRC can be used to define the
width measurement mode, the TON will be cleared au- pre-scaling stages of the internal clock sources of
tomatically after the measurement cycle is completed. timer/event counter. The definitions are as shown. The
But in the other two modes the TON can only be reset by overflow signal of timer/event counter can be used to
instructions. The overflow of the timer/event counter is generate the PFD signal.
one of the wake-up sources. No matter what the opera-
tion mode is, writing a 0 to ETI can disable the interrupt
service.
P W M
(6 + 2 ) C o m p a re T o P D 0 C ir c u it
fS Y S 8 - s ta g e P r e s c a le r
f IN T D a ta B u s
8 -1 M U X
T M 1
T M 0 8 - B it T im e r /E v e n t R e lo a d
C o u n te r P r e lo a d
P S C 2 ~ P S C 0 T M R R e g is te r
T E
P u ls e W id th 8 - B it T im e r /E v e n t O v e r flo w
T M 1 M e a s u re m e n t C o u n te r
T M 0 to In te rru p t
M o d e C o n tro l
T O N
1 /2 P F D
Timer/Event Counter
Input/Output Ports [m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
There are 13 bidirectional input/output lines in the into the CPU, execute the defined operations
microcontroller, labeled as PA, PB and PD, which are (bit-operation), and then write the results back to the
mapped to the data memory of [12H], [14H] and [18H] latches or the accumulator.
respectively. All of these I/O ports can be used for input Each line of port A has the capability of waking-up the
and output operations. For input operation, these ports device. The highest 4-bit of port B and 7 bits of port D
are non-latching, that is, the inputs must be ready at the are not physically implemented; on reading them a ²0² is
T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H returned whereas writing then results in a no-operation.
or 18H). For output operation, all the data is latched and See Application note.
remains unchanged until the output latch is rewritten.
Each I/O line has a pull-high option. Once the pull-high
Each I/O line has its own control register (PAC, PBC, option is selected, the I/O line has a pull-high resistor,
PDC) to control the input/output configuration. With this otherwise, there¢s none. Take note that a non-pull-high
control register, CMOS output or Schmitt trigger input I/O line operating in input mode will cause a floating
with or without pull-high resistor structures can be re- state.
configured dynamically (i.e. on-the-fly) under software
The PA3 is pin-shared with the PFD signal. If the PFD
control. To function as an input, the corresponding latch
option is selected, the output signal in output mode of
of the control register must write ²1². The input source
PA3 will be the PFD signal generated by the timer/event
also depends on the control register. If the control regis-
counter overflow signal. The input mode always remain-
ter bit is ²1², the input will read the pad state. If the con- ing its original functions. Once the PFD option is se-
trol register bit is ²0², the contents of the latches will lected, the PFD output signal is controlled by PA3 data
move to the internal bus. The latter is possible in the register only. Writing ²1² to PA3 data register will enable
²read-modify-write² instruction. the PFD output function and writing ²0² will force the
For output function, CMOS is the only configuration. PA3 to remain at ²0². The I/O functions of PA3 are
These control registers are mapped to locations 13H, shown below.
15H and 19H.
I/O I/P O/P I/P O/P
After a chip reset, these input/output lines remain at high Mode (Normal) (Normal) (PFD) (PFD)
levels or floating state (dependent on pull-high options). Logical Logical Logical PFD
PA3
Each bit of these input/output latches can be set or Input Output Input (Timer on)
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or
Note: The PFD frequency is the timer/event counter
18H) instructions.
overflow frequency divided by 2.
Some instructions first input data and then follow the
The PA5 and PA4 are pin-shared with INT and TMR pins
output operations. For example, ²SET [m].i², ²CLR
respectively.
V D D
C o n tr o l B it P U
D a ta B u s D Q
W r ite C o n tr o l R e g is te r C K Q B
C h ip R e s e t S P A 0 ~ P A 2
P A 3 /P F D
P A 4 /T M R
R e a d C o n tr o l R e g is te r P A 5 /IN T
D a ta B it P A 6 , P A 7
D Q P B 0 /A N 0 ~ P B 3 /A N 3
P D 0 /P W M
W r ite D a ta R e g is te r C K Q B
S
M
U
(P D 0 o r P W M ) P A 3 X
P F D
P F D E N
M (P A 3 )
U
X
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly ) W a k e - u p o p tio n
IN T fo r P A 5 O n ly
T M R fo r P A 4 O n ly
Input/Output Ports
The PB can also be used as A/D converter inputs. The In a PWM cycle, the duty cycle of each modulation cycle
A/D function will be described later. There is a PWM is shown in the table.
function shared with PD0. If the PWM function is en-
Parameter AC (0~3) Duty Cycle
abled, the PWM signal will appear on PD0 (if PD0 is op-
DC+1
erating in output mode). Writing ²1² to PD0 data register i<AC
Modulation cycle i 64
will enable the PWM output function and writing ²0² will
(i=0~3) DC
force the PD0 to remain at ²0². The I/O functions of PD0 i³AC
64
are as shown.
I/O I/P O/P I/P O/P The modulation frequency, cycle frequency and cycle
Mode (Normal) (Normal) (PWM) (PWM) duty of the PWM output signal are summarized in the
following table.
Logical Logical Logical
PD0 PWM PWM Modulation PWM Cycle PWM Cycle
Input Output Input
Frequency Frequency Duty
It is recommended that unused or not bonded out I/O fSYS/64 fSYS/256 [PWM]/256
lines should be set as output pins by software instruction
to avoid consuming power under input floating state. A/D Converter
fS Y S /2
[P W M ] = 1 0 0
P W M
2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4
[P W M ] = 1 0 1
P W M
2 6 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4
[P W M ] = 1 0 2
P W M
2 6 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4
[P W M ] = 1 0 3
P W M
2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 6 /6 4
P W M m o d u la tio n p e r io d : 6 4 /fS Y S
M o d u la tio n c y c le 0 M o d u la tio n c y c le 1 M o d u la tio n c y c le 2 M o d u la tio n c y c le 3 M o d u la tio n c y c le 0
P W M c y c le : 2 5 6 /fS Y S
PWM
The A/D converter control register is used to control the Bit 7 of the ACSR register is used for test purposes only
A/D converter. The bit2~bit0 of the ADCR are used to and must not be used for other purposes by the applica-
select an analog input channel. There are a total of four tion program. Bit1 and bit0 of the ACSR register are
channels to select. The bit5~bit3 of the ADCR are used used to select the A/D clock source.
to set PB configurations. PB can be an analog input or When the A/D conversion has completed, the A/D inter-
as digital I/O line decided by these 3 bits. Once a PB line
rupt request flag will be set. The EOCB bit is set to ²1²
is selected as an analog input, the I/O functions and
when the START bit is set from ²0² to ²1².
pull-high resistor of this I/O line are disabled, and the
A/D converter circuit is power on. The EOCB bit (bit6 of Important Note for A/D initialization:
the ADCR) is end of A/D conversion flag. Check this bit Special care must be taken to initialize the A/D con-
to know when A/D conversion is completed. The START verter each time the Port B A/D channel selection bits
bit of the ADCR is used to begin the conversion of A/D are modified, otherwise the EOCB flag may be in an un-
converter. Give START bit a raising edge and falling defined condition. An A/D initialization is implemented
edge that means the A/D conversion has started. In or- by setting the START bit high and then clearing it to zero
der to ensure the A/D conversion is completed, the within 10 instruction cycles of the Port B channel selec-
START should stay at ²0² until the EOCB is cleared to tion bits being modified. Note that if the Port B channel
²0² (end of A/D conversion). selection bits are all cleared to zero then an A/D initial-
ization is not required.
S T A R T
P C R 2 ~ 0 0 0 B 1 0 0 B 1 0 0 B 1 0 1 B 0 0 0 B
P C R 0
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
0 0 0 B 0 1 0 B 0 0 0 B 0 0 1 B d o n 't c a r e
A C S 0
P o w e r-o n S ta rt o f A /D S ta rt o f A /D S ta rt o f A /D
R e s e t c o n v e r s io n c o n v e r s io n c o n v e r s io n
R e s e t A /D R e s e t A /D R e s e t A /D
c o n v e rte r c o n v e rte r c o n v e rte r
E n d o f A /D E n d o f A /D E n d o f A /D
1 : D e fin e P B c o n fig u r a tio n c o n v e r s io n c o n v e r s io n c o n v e r s io n
2 : S e le c t a n a lo g c h a n n e l
tA D C 1 tA D C 1 tA D C 1
A /D c o n v e r s io n tim e A /D c o n v e r s io n tim e A /D c o n v e r s io n tim e
N o te : A /D c lo c k m u s t b e fS Y S /2 , fS Y S /8 o r fS Y S /3 2
tA D C S 1 = 3 2 tA D
tA D C 1 = 7 6 tA D
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first exam-
ple, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr EADI ; disable ADC interrupt
mov a,00000001B
mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock
mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov ADCR,a ; and select AN0 to be connected to the A/D converter
:
: ; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr START
set START ; reset A/D
clr START ; start A/D
Polling_EOC:
sz EOCB ; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp polling_EOC ; continue polling
mov a,ADRH ; read conversion result high byte value from the ADRH register
mov adrh_buffer,a ; save result to user defined memory
mov a,ADRL ; read conversion result low byte value from the ADRL register
mov adrl_buffer,a ; save result to user defined memory
:
:
jmp start_conversion ; start next A/D conversion
mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov ADCR,a ; and select AN0 to be connected to the A/D converter
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr START
set START ; reset A/D
clr START ; start A/D
clr ADF ; clear ADC interrupt request flag
set EADI ; enable ADC interrupt
set EMI ; enable global interrupt
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov acc_stack,a ; save ACC to user defined memory
mov a,STATUS
mov status_stack,a ; save STATUS to user defined memory
:
:
mov a,ADRH ; read conversion result high byte value from the ADRH register
mov adrh_buffer,a ; save result to user defined register
mov a,ADRL ; read conversion result low byte value from the ADRL register
mov adrl_buffer,a ; save result to user defined register
clr START
set START ; reset A/D
clr START ; start A/D
:
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a ; restore STATUS from user defined memory
mov a,acc_stack ; restore ACC from user defined memory
reti
Low Voltage Reset - LVR The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in V D D V O P R
V D D
5 .5 V
V L V R L V R D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
R e s e t N o r m a l O p e r a tio n R e s e t
*1 *2
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since the low voltage has to maintain in its original state and exceed 1ms, therefore 1ms delay enter the
reset mode.
Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper
system functioning.
No. Options
1 WDT clock source: WDTOSC or T1 (fSYS/4)
2 WDT function: enable or disable
3 CLRWDT instruction(s): one or two clear WDT instruction(s)
4 System oscillator: RC or crystal
5 Pull-high resistors (PA, PB, PD): none or pull-high
6 PWM enable or disable
7 PA0~PA7 wake-up: enable or disable
8 PFD enable or disable
9 Low voltage reset selection: enable or disable LVR function.
Application Circuits
V D D
0 .0 1 m F *
V D D P A 0 ~ P A 2
V D D
1 0 0 k W P A 3 /P F D
R E S P A 4 /T M R 4 7 0 p F R C S y s te m O s c illa to r
0 .1 m F O S C 1
1 0 k W P A 5 /IN T 3 0 k W < R O S C < 7 5 0 k W
R O S C
P A 6 ~ P A 7 fS Y S /4
0 .1 m F * O S C 2
V S S P B 0 /A N 0 C 1
~
P B 3 /A N 3 O S C 1 C ry s ta l S y s te m O s c illa to r
F o r th e v a lu e s ,
P D 0 /P W M s e e ta b le b e lo w
O S C O S C 1 C 2
C ir c u it O S C 2 O S C 2
R 1
S e e R ig h t S id e
H T 4 6 R 4 7 -H O S C C ir c u it
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
Instruction Flag
Mnemonic Description
Cycle Affected
Branch
JMP addr Jump unconditionally 2 None
SZ [m] Skip if data memory is zero 1(2) None
SZA [m] Skip if data memory is zero with data movement to ACC 1(2) None
SZ [m].i Skip if bit i of data memory is zero 1(2) None
SNZ [m].i Skip if bit i of data memory is not zero 1(2) None
SIZ [m] Skip if increment data memory is zero 1(3) None
SDZ [m] Skip if decrement data memory is zero 1(3) None
SIZA [m] Skip if increment data memory is zero with result in ACC 1(2) None
SDZA [m] Skip if decrement data memory is zero with result in ACC 1(2) None
CALL addr Subroutine call 2 None
RET Return from subroutine 2 None
RET A,x Return from subroutine and load immediate data to ACC 2 None
RETI Return from interrupt 2 None
Table Read
TABRDC [m] Read ROM code (current page) to data memory and TBLH 2(1) None
TABRDL [m] Read ROM code (last page) to data memory and TBLH 2(1) None
Miscellaneous
NOP No operation 1 None
CLR [m] Clear data memory 1(1) None
SET [m] Set data memory 1(1) None
CLR WDT Clear Watchdog Timer 1 TO,PDF
CLR WDT1 Pre-clear Watchdog Timer 1 TO(4),PDF(4)
CLR WDT2 Pre-clear Watchdog Timer 1 TO(4),PDF(4)
SWAP [m] Swap nibbles of data memory 1(1) None
SWAPA [m] Swap nibbles of data memory with result in ACC 1 None
HALT Enter power down mode 1 TO,PDF
Instruction Definition
¾ ¾ Ö Ö Ö Ö
¾ ¾ Ö Ö Ö Ö
¾ ¾ Ö Ö Ö Ö
¾ ¾ Ö Ö Ö Ö
¾ ¾ Ö Ö Ö Ö
¾ ¾ ¾ Ö ¾ ¾
¾ ¾ ¾ Ö ¾ ¾
¾ ¾ ¾ Ö ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ Ö ¾ ¾
CPLA [m] Complement data memory and place result in the accumulator
Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation ACC ¬ [m]
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ Ö ¾ ¾
¾ ¾ ¾ ¾ ¾ Ö
¾ ¾ ¾ Ö ¾ ¾
DECA [m] Decrement data memory and place result in the accumulator
Description Data in the specified data memory is decremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation ACC ¬ [m]-1
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ Ö ¾ ¾
¾ ¾ ¾ Ö ¾ ¾
INCA [m] Increment data memory and place result in the accumulator
Description Data in the specified data memory is incremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation ACC ¬ [m]+1
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ Ö ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
NOP No operation
Description No operation is performed. Execution continues with the next instruction.
Operation Program Counter ¬ Program Counter+1
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ Ö ¾ ¾
¾ ¾ ¾ Ö ¾ ¾
¾ ¾ ¾ Ö ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
RLA [m] Rotate data memory left and place result in the accumulator
Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾
RLCA [m] Rotate left through carry and place result in the accumulator
Description Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö
RRCA [m] Rotate right through carry and place result in the accumulator
Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö
SBC A,[m] Subtract data memory and carry from the accumulator
Description The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the accumulator.
Operation ACC ¬ ACC+[m]+C
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ Ö Ö Ö Ö
SBCM A,[m] Subtract data memory and carry from the accumulator
Description The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the data memory.
Operation [m] ¬ ACC+[m]+C
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ Ö Ö Ö Ö
¾ ¾ ¾ ¾ ¾ ¾
SDZA [m] Decrement data memory and place result in ACC, skip if 0
Description The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-
cles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
SIZA [m] Increment data memory and place result in ACC, skip if 0
Description The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory re-
mains unchanged. If the result is 0, the following instruction, fetched during the current in-
struction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ Ö Ö Ö Ö
¾ ¾ Ö Ö Ö Ö
¾ ¾ Ö Ö Ö Ö
¾ ¾ ¾ ¾ ¾ ¾
SWAPA [m] Swap data memory and place result in the accumulator
Description The low-order and high-order nibbles of the specified data memory are interchanged, writ-
ing the result to the accumulator. The contents of the data memory remain unchanged.
Operation ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ ¾ ¾ ¾
TABRDC [m] Move the ROM code (current page) to TBLH and data memory
Description The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation [m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾
TABRDL [m] Move the ROM code (last page) to TBLH and data memory
Description The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation [m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾
¾ ¾ ¾ Ö ¾ ¾
¾ ¾ ¾ Ö ¾ ¾
¾ ¾ ¾ Ö ¾ ¾
Package Information
18-pin DIP (300mil) Outline Dimensions
1 8 1 0
B
1 9
D
a
E G I
F
Dimensions in mil
Symbol
Min. Nom. Max.
A 895 ¾ 915
B 240 ¾ 260
C 125 ¾ 135
D 125 ¾ 145
E 16 ¾ 20
F 50 ¾ 70
G ¾ 100 ¾
H 295 ¾ 315
I 335 ¾ 375
a 0° ¾ 15°
1 8 1 0
A B
1 9
C '
G
D H
E F a
Dimensions in mil
Symbol
Min. Nom. Max.
A 394 ¾ 419
B 290 ¾ 300
C 14 ¾ 20
C¢ 447 ¾ 460
D 92 ¾ 104
E ¾ 50 ¾
F 4 ¾ ¾
G 32 ¾ 38
H 4 ¾ 12
a 0° ¾ 10°
D
T 2
A B C
T 1
SOP 18W
P 0 P 1
D t
F
W
B 0
C
D 1 P
K 0
A 0
SOP 18W