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  • Compression-Controller (Updated)

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    Ang Ali
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    1) The document describes the states (S0 through S6) of a state machine. 2) It shows the transition from state S0 to state S6, with the values of various signals at each step. 3) The document provides detailed logic values for signals like sel_mux1, sel_mux2, and en_reg as the state machine transitions between states.

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    FSM Controller

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    1) The document describes the states (S0 through S6) of a state machine. 2) It shows the transition from state S0 to state S6, with the values of various signals at each step. 3) The document provides detailed logic values for signals like sel_mux1, sel_mux2, and en_reg as the state machine transitions between states.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    8 views1 page

    Compression-Controller (Updated)

    Uploaded by

    Ang Ali
    1) The document describes the states (S0 through S6) of a state machine. 2) It shows the transition from state S0 to state S6, with the values of various signals at each step. 3) The document provides detailed logic values for signals like sel_mux1, sel_mux2, and en_reg as the state machine transitions between states.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    rst

    Move to State S6
    S0

    7 6 5 4 3 2 1 0
    S1
    P P P P P P P P

    valid 0 en_reg[7:0]=0

    cen 0

    1
    7 6 5 4 3 2 1 0 sel_mux1[7:4]=0,
    B3 B2 B1 B0 - - - - sel_mux2[7:4]=1, 0 bit4
    en_reg[7:4]=1 S6
    1 7 6 5 4 3 2 1 0
    P P P P P P P P
    7 6 5 4 3 2 1 0 sel_mux1[7:5]=1,
    sel_mux2[7:5]=1, valid 0 en_reg[7:0]=0
    B2 B1 B0 - - - - -
    en_reg[7:5]=1
    1
    sel_mux1[7:5]=0(X),
    cen 1 sel_mux2[7:0]=3 (All
    S2 0's) en_reg[7:0]=1
    7 6 5 4 3 2 1 0

    7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0

    P P P P P P P P
    sel_mux1[7:4]=0, 7 6 5 4 3 2 1 0
    en_reg[7:0]=0 0 valid sel_mux2[7:4]=1, B3 B2 B1 B0 - - - -
    1 en_reg[7:4]=1

    cen 0

    1
    sel_mux1[4:1]=1,
    7 6 5 4 3 2 1 0
    sel_mux2[4:1]=1,
    bit4 0
    P P P B3 B2 B1 B0 -
    en_reg[7:5]=0,
    1 en_reg[4:1]=1

    7 6 5 4 3 2 1 0 sel_mux1[4:2]=2,
    P P P B2 B1 B0 - - sel_mux2[4:2]=1, S5
    en_reg[7:5]=0,
    en_reg[4:2]=1

    S3 valid 0 en_reg[7:0]=0
    1 7 6 5 4 3 2 1 0

    P P P P P P P P
    7 6 5 4 3 2 1 0
    en_reg[7:0]=0 0 valid cen 0
    7 6 5 4 3 2 1 0
    P P P P P P P P
    1 1 S S S B3 B2 B1 B0 -

    cen 0
    sel_mux1[4:1]=1,
    bv 0 sel_mux2[7:5]=2,
    1 sel_mux2[4:1]=1,
    sel_mux1[5:2]=2, 1 en_reg[7:1]=1
    7 6 5 4 3 2 1 0 sel_mux2[7:6]=2, 0 bv
    S S B3 B2 B1 B0 - - sel_mux2[5:2]=1, sel_mux1[4:2]=2, 7 6 5 4 3 2 1 0
    en_reg[7:2]=1 1 sel_mux2[7:5]=2, S S S B2 B1 B0 - -
    sel_mux2[4:2]=1,
    sel_mux1[5:3]=3, en_reg[7:2]=1
    7 6 5 4 3 2 1 0
    sel_mux2[7:6]=2,
    S S B2 B1 B0 - - - sel_mux2[5:3]=1,
    en_reg[7:3]=1

    S4

    7 6 5 4 3 2 1 0

    P P P P P P P P en_reg[7:0]=0 0 valid

    7 6 5 4 3 2 1 0 sel_mux1[6:3]=3,
    sel_mux2[7]=2, cen 0
    S B3 B2 B1 B0 - - - sel_mux2[6:3]=1,
    en_reg[7:3]=1 1

    7 6 5 4 3 2 1 0
    0 bv

    S B2 B1 B0 - - - - sel_mux1[6:4]=0, 1
    sel_mux2[7]=2,
    sel_mux2[6:4]=1,
    en_reg[7:4]=1

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