5 4 3 2 1

D D

Cottonwood Schematic
Broadwell-ULT
C
2014-06-09 C

REV : A00

DY : None Installed
B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cover Page
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 1 of 104
5 4 3 2 1
 5 4 3 2 1

CHARGER
BQ24770RUYR-GP 44
INPUTS OUTPUTS
Project code:4PD01V010001 Cottonwood Block Diagram AD+
BT+
DCBATOUT
PCB P/N: 13321 SYSTEM DC/DC
Revision: A00 TPS51225RUKR-GP 45
INPUTS OUTPUTS
3D3V_AUX_S5
D 5V_AUX_S5 D
DCBATOUT 5V_S5
3D3V_S5

CPU Core Power

TPS51624RSMR-GP 46,47
Intel CPU INPUTS OUTPUTS
33

DDR3L1600
Broadwell ULT DDR3L 1600MHz Channel A DCBATOUT VCC_CORE
HDMI V1.4a HDMI
54 SODIMM A
15W (UMA) 12 DDR3L SUS
TPS51716RUKR-GP 49
INPUTS OUTPUTS
DCBATOUT 1D35V_S3
13.3" 16:9 eDP eDP WPT-LP 0D65V_S0
PCIe x 1
8 USB 2.0/1.1 ports NGFF
4 USB 3.0 ports WLAN & BT CPU 1.05V
SY8208DQNC-GP-U 48
Touch Panel High Definition Audio USB2.0 x 1 combo module
USB2.0 x 1 INPUTS OUTPUTS
4 SATA ports
52 DCBATOUT 1D05V_S0
6 PCIE ports
LPC I/F Card reader SD/SDHC/MMC CPU 1D5V_S0
USB2.0 x 1 RealTek
C ACPI 4.0a RTS5176E TLV70215DBVR-GP 51 C

INPUTS OUTPUTS
USB3.0
USB3.0 Port1 3D3V_S5 1D5V_S0
USB PowerShare USB2.0 x 1 USB2.0 Port3
Power share USB2.0 TI USB2.0
Switches 36 83
34 TPS2544RTER 34 INPUTS OUTPUTS
USB3.0
IO Board 63 1D35V_S3 1D35V_S0
USB3.0 Port2 5V_S5 5V_S0

USB2.0 3D3V_S5 3D3V_S0

34
Gyro
ST
L3GD20

Sensor Hub G + E-compass

USB2.0 I2C ST
ST
HDA STM32L151CBU6TR 66 LSM303D
MIC_IN/GND
CODEC HOME button BD on Panel side 52 PCB LAYER
Realtek HDA
G Sensor L1:Top
HP_R/L
29 ALC3234 USB2.0 x 1 Camera / ALS 52
L2:VCC
Combo Jack 27 LNG3DMTR66 L3:Signal
B L4:Signal B

2CH SPEAKER L5:GND

(2CH 2W/4ohm) L6:Signal

29

LPC debug port LPC BUS INT2

65 SATA(Gen3) x 1 HDD
56

Thermal KBC
NUVOTON SMBUS NUVOTON
NCT7718W SPI
26 NPCE285P
24

A A
Flash ROM
PWM FAN PS2 8MB
26
Quad Read 25 <Core Design>

Touch PAD I2C Wistron Corporation

Int. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Image sensor
KB 62
62 Title
Block Diagram
Size Document Number Rev
C Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 2 of 104
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)
C C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A4
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 3 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
1D05S_VCCST

RN401
XDP_TMS 1 8
XDP_TDI 2 7
D 3 6 D
XDP_TDO 4
DY 5

SRN51J-1-GP

XDP_TRST# R402 1
DY 2 51R2J-2-GP
XDP_TCLK R406 1 2 51R2J-2-GP

1D05S_VCCST
HSW_ULT_DDR3L
CPU1B 2 OF 19
1

R401 D61
62R2J-GP TP402 H_CATERR# PROC_DETECT# MISC
1 K61 CATERR# XDP_PRDY#
C
Layout Note: [24] H_PECI N62 PECI PRDY# J62
K62 XDP_PREQ#
XDP_PRDY# [96]
XDP_PREQ# [96] C
2

PREQ# XDP_TCLK
Impedance control:50 ohm PROC_TCK E60 XDP_TCLK [96]
E61 XDP_TMS XDP_TMS [96]
JTAG PROC_TMS
[24,44,46] H_PROCHOT# 1 2 H_PROCHOT#_R K63 PROCHOT# PROC_TRST# E59 XDP_TRST# XDP_TRST# [96]
R403 THERMAL F63 XDP_TDI XDP_TDI [96]
PROC_TDI XDP_TDO
56R2J-4-GP PROC_TDO F62 XDP_TDO [96]
H_CPUPWRGD C61 PROCPWRGD PWR XDP_BPM[7:0]
XDP_BPM[7:0] [96]
1

J60 XDP_BPM0
R405 BPM#0 XDP_BPM1
BPM#1 H60
10KR2J-3-GP H61 XDP_BPM2
BPM#2 XDP_BPM3
BPM#3 H62
SM_RCOMP_0 AU60 K59 XDP_BPM4
2

SM_RCOMP_1 SM_RCOMP0 DDR3L BPM#4 XDP_BPM5

AV60 SM_RCOMP1 BPM#5 H63
SM_RCOMP_2 AU61 K60 XDP_BPM6
SM_DRAMRST# SM_RCOMP2 BPM#6 XDP_BPM7
AV15 SM_DRAMRST# BPM#7 J61
DDR_PG_CTRL AV61
[12] DDR_PG_CTRL SM_PG_CNTL1

B B
HASWELL-6-GP-U

R407 1 200R2F-L-GP SM_RCOMP_0 1D35V_S3

2
Layout Note:
R408 1 2 121R2F-GP SM_RCOMP_1 Place close to DIMM
R409 1 2 100R2F-L1-GP-U SM_RCOMP_2 1 R410
470R2J-2-GP X02 0414

R404
2

SM_DRAMRST# 1 2 DDR3_DRAMRST# [12]

Layout Note: 0R0402-PAD-2-GP

<Core Design>
Design Guideline:
SM_RCOMP keep routing length less than 500 mils.
A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (THERMAL/MISC/PM)
Size Document Number Rev
A4 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 4 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
DDR3L ball type: Non-Interleaved Type
CPU1D HSW_ULT_DDR3L 4 OF 19
HSW_ULT_DDR3L 3 OF 19
CPU1C

M_A_DQ[63:0]
[12] M_A_DQ[63:0]
M_A_DQ0 AH63 AU37 AY31 AM38
M_A_DQ1 SA_DQ0 SA_CLK#0 M_A_DIMA_CLK_DDR#0 [12] SB_DQ0 SB_CK#0
AH62 AV37 AW31 AN38
M_A_DQ2 SA_DQ1 SA_CLK0 M_A_DIMA_CLK_DDR0 [12] SB_DQ1 SB_CK0
AK63 AW36 AY29 AK38
M_A_DQ3 SA_DQ2 SA_CLK#1 M_A_DIMA_CLK_DDR#1 [12] SB_DQ2 SB_CK#1
AK62 AY36 AW29 AL38
M_A_DQ4 SA_DQ3 SA_CLK1 M_A_DIMA_CLK_DDR1 [12] SB_DQ3 SB_CK1
D AH61 AV31 D
M_A_DQ5 SA_DQ4 SB_DQ4
AH60 AU43 AU31 AY49
M_A_DQ6 SA_DQ5 SA_CKE0 M_A_DIMA_CKE0 [12] SB_DQ5 SB_CKE0
AK61 AW43 AV29 AU50
M_A_DQ7 SA_DQ6 SA_CKE1 M_A_DIMA_CKE1 [12] SB_DQ6 SB_CKE1
AK60 AY42 AU29 AW49
M_A_DQ8 SA_DQ7 SA_CKE2 SB_DQ7 SB_CKE2
AM63 AY43 AY27 AV50
M_A_DQ9 SA_DQ8 SA_CKE3 SB_DQ8 SB_CKE3
AM62 AW27
M_A_DQ10 SA_DQ9 SB_DQ9
AP63 AP33 AY25 AM32
M_A_DQ11 SA_DQ10 SA_CS#0 M_A_DIMA_CS#0 [12] SB_DQ10 SB_CS#0
AP62 AR32 AW25 AK32
M_A_DQ12 SA_DQ11 SA_CS#1 M_A_DIMA_CS#1 [12] SB_DQ11 SB_CS#1
AM61 AV27
M_A_DQ13 SA_DQ12 TP_M_A_DIMA_ODT0 TP501 SB_DQ12
AM60 AP32 1 AU27 AL32
M_A_DQ14 SA_DQ13 SA_ODT0 SB_DQ13 SB_ODT0
AP61 AV25
M_A_DQ15 SA_DQ14 SB_DQ14
AP60 AY34 M_A_RAS# [12] AU25 AM35
M_A_DQ16 SA_DQ15 SA_RAS# SB_DQ15 SB_RAS#
AP58 AW34 M_A_WE# [12] AM29 AK35
M_A_DQ17 SA_DQ16 SA_WE# SB_DQ16 SB_WE#
AR58 AU34 M_A_CAS# [12] AK29 AM33
M_A_DQ18 SA_DQ17 SA_CAS# SB_DQ17 SB_CAS#
AM57 AL28
M_A_DQ19 SA_DQ18 SB_DQ18
AK57 AU35 M_A_BS0 [12] AK28 AL35
M_A_DQ20 SA_DQ19 SA_BA0 SB_DQ19 SB_BA0
AL58 AV35 M_A_BS1 [12] AR29 AM36
M_A_DQ21 SA_DQ20 SA_BA1 SB_DQ20 SB_BA1
AK58 AY41 M_A_BS2 [12] AN29 AU49
M_A_DQ22 SA_DQ21 SA_BA2 SB_DQ21 SB_BA2
AR57 AR28
M_A_DQ23 SA_DQ22 M_A_A0 M_A_A[15:0] [12] SB_DQ22
AN57 AU36 AP28 AP40
M_A_DQ24 SA_DQ23 SA_MA0 M_A_A1 SB_DQ23 SB_MA0
AP55 AY37 AN26 AR40
M_A_DQ25 SA_DQ24 SA_MA1 M_A_A2 SB_DQ24 SB_MA1
AR55 AR38 AR26 AP42
M_A_DQ26 SA_DQ25 SA_MA2 M_A_A3 SB_DQ25 SB_MA2
AM54 AP36 AR25 AR42
M_A_DQ27 SA_DQ26 SA_MA3 M_A_A4 SB_DQ26 SB_MA3
AK54 AU39 AP25 AR45
M_A_DQ28 SA_DQ27 SA_MA4 M_A_A5 SB_DQ27 SB_MA4
AL55 AR36 AK26 AP45
M_A_DQ29 SA_DQ28 SA_MA5 M_A_A6 SB_DQ28 SB_MA5
AK55 AV40 AM26 AW46
M_A_DQ30 SA_DQ29 SA_MA6 M_A_A7 SB_DQ29 SB_MA6
AR54 AW39 AK25 AY46
M_A_DQ31 SA_DQ30 DDR CHANNEL A SA_MA7 M_A_A8 SB_DQ30 SB_MA7
AN54 AY39 AL25 AY47
M_A_DQ32 SA_DQ31 SA_MA8 M_A_A9 SB_DQ31 DDR CHANNEL B SB_MA8
AY58 AU40 AY23 AU46
M_A_DQ33 SA_DQ32 SA_MA9 M_A_A10 SB_DQ32 SB_MA9
AW58 AP35 AW23 AK36
M_A_DQ34 SA_DQ33 SA_MA10 M_A_A11 SB_DQ33 SB_MA10
AY56 AW41 AY21 AV47
M_A_DQ35 SA_DQ34 SA_MA11 M_A_A12 SB_DQ34 SB_MA11
AW56 AU41 AW21 AU47
M_A_DQ36 SA_DQ35 SA_MA12 M_A_A13 SB_DQ35 SB_MA12
AV58 AR35 AV23 AK33
M_A_DQ37 SA_DQ36 SA_MA13 M_A_A14 SB_DQ36 SB_MA13
AU58 AV42 AU23 AR46
M_A_DQ38 SA_DQ37 SA_MA14 M_A_A15 SB_DQ37 SB_MA14
AV56 AU42 AV21 AP46
M_A_DQ39 SA_DQ38 SA_MA15 SB_DQ38 SB_MA15
AU56 M_A_DQS#[7:0] [12] AU21
M_A_DQ40 SA_DQ39 M_A_DQS#0 SB_DQ39
AY54 AJ61 AY19 AW30
M_A_DQ41 SA_DQ40 SA_DQSN0 M_A_DQS#1 SB_DQ40 SB_DQSN0
AW54 AN62 AW19 AV26
M_A_DQ42 SA_DQ41 SA_DQSN1 M_A_DQS#2 SB_DQ41 SB_DQSN1
AY52 AM58 AY17 AN28
M_A_DQ43 SA_DQ42 SA_DQSN2 M_A_DQS#3 SB_DQ42 SB_DQSN2
AW52 AM55 AW17 AN25
M_A_DQ44 SA_DQ43 SA_DQSN3 M_A_DQS#4 SB_DQ43 SB_DQSN3
AV54 AV57 AV19 AW22
M_A_DQ45 SA_DQ44 SA_DQSN4 M_A_DQS#5 SB_DQ44 SB_DQSN4
C AU54 AV53 AU19 AV18 C
M_A_DQ46 SA_DQ45 SA_DQSN5 M_A_DQS#6 SB_DQ45 SB_DQSN5
AV52 AL43 AV17 AN21
M_A_DQ47 SA_DQ46 SA_DQSN6 M_A_DQS#7 SB_DQ46 SB_DQSN6
AU52 AL48 AU17 AN18
M_A_DQ48 SA_DQ47 SA_DQSN7 SB_DQ47 SB_DQSN7
AK40 M_A_DQS[7:0] [12] AR21
M_A_DQ49 SA_DQ48 M_A_DQS0 SB_DQ48
AK42 AJ62 AR22 AV30
M_A_DQ50 SA_DQ49 SA_DQSP0 M_A_DQS1 SB_DQ49 SB_DQSP0
AM43 AN61 AL21 AW26
M_A_DQ51 SA_DQ50 SA_DQSP1 M_A_DQS2 SB_DQ50 SB_DQSP1
AM45 AN58 AM22 AM28
M_A_DQ52 SA_DQ51 SA_DQSP2 M_A_DQS3 SB_DQ51 SB_DQSP2
AK45 AN55 AN22 AM25
M_A_DQ53 SA_DQ52 SA_DQSP3 M_A_DQS4 SB_DQ52 SB_DQSP3
AK43 AW57 AP21 AV22
M_A_DQ54 SA_DQ53 SA_DQSP4 M_A_DQS5 SB_DQ53 SB_DQSP4
AM40 AW53 AK21 AW18
M_A_DQ55 SA_DQ54 SA_DQSP5 M_A_DQS6 SB_DQ54 SB_DQSP5
AM42 AL42 AK22 AM21
M_A_DQ56 SA_DQ55 SA_DQSP6 M_A_DQS7 SB_DQ55 SB_DQSP6
AM46 AL49 AN20 AM18
M_A_DQ57 SA_DQ56 SA_DQSP7 SB_DQ56 SB_DQSP7
AK46 AR20
M_A_DQ58 SA_DQ57 SB_DQ57
AM49 AP49 +V_SM_VREF_CNT +V_SM_VREF_CNT [37] AK18
M_A_DQ59 SA_DQ58 SM_VREF_CA SB_DQ58
AK49 AR51 DDR_WR_VREF01 [37] AL18
M_A_DQ60 SA_DQ59 SM_VREF_DQ0 SB_DQ59
AM48 AP51 AK20
M_A_DQ61 SA_DQ60 SM_VREF_DQ1 SB_DQ60
AK48 AM20
M_A_DQ62 SA_DQ61 SB_DQ61
AM51 AR18
M_A_DQ63 SA_DQ62 SB_DQ62
AK51 AP18
SA_DQ63 SB_DQ63

HASWELL-6-GP-U
HASWELL-6-GP-U

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDR)
Size Document Number Rev
A2 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 5 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

D D

CPU1S HSW_ULT_DDR3L 19 OF 19
#514405

CFG[19:0]
[96] CFG[19:0]
CFG0 AC60 AV63 RSVDAV63 1 TP601
CFG1 CFG0 RSVD_TP#AV63 RSVDAU63 TP602
AC62 CFG1 RSVD_TP#AU63 AU63 1
CFG2 AC63
CFG3 CFG2
AA63 CFG3
CFG4 AA60 C63 RSVDC63 1 TP603
CFG5 CFG4 RSVD_TP#C63 RSVDC62 TP604
Y62 CFG5 RSVD_TP#C62 C62 1
CFG6 Y61 B43 EDP_SPARE 1 TP605
CFG7 CFG6 RSVD#B43
Y60 CFG7
CFG8 V62 A51 RSVDA51 1 TP606
CFG9 CFG8 RSVD_TP#A51 RSVDB51 TP607
V61 CFG9 RSVD_TP#B51 B51 1
CFG10 V60
CFG11 CFG10 RSVDL60 TP608
U60 CFG11 RSVD_TP#L60 L60 1
CFG12 T63
CFG13 CFG12 RESERVED
T62 CFG13 RSVD#N60 N60
CFG14 T61 Intel Recommend
CFG15 CFG14
T60 CFG15 RSVD#W23 W23
Y22 PROC_OPI_COMP3 R606 1 DY 2 49D9R2F-GP
CFG16 RSVD#Y22
AA62 CFG16 PROC_OPI_RCOMP AY15 PROC_OPI_COMP R602 1 2 49D9R2F-GP
CFG18 U63
C CFG17 CFG18 C
AA61 CFG17 RSVD#AV62 AV62
CFG19 U62 D58
CFG19 RSVD#D58
CFG_RCOMP
1 2 V63 CFG_RCOMP VSS P22
N21
Layout Note:
VSS
R601 A5 RSVD#A5
1.Referenced "continuous" VSS plane only.
49D9R2F-GP P20 HVM_CLK# 1 2.Avoid routing next to clock pins or noisy
RSVD#P20
E1 R20 HVM_CLK 1 TP619
D1
RSVD#E1 RSVD#R20 TP620 signals.
RSVD#D1 3.Trace width: 12~15mil
J20 RSVD#J20
H18 RSVD#H18 4.Isolation Spacing: 12mil
1 2 TD_IREF B12 5.Max length: 500mil
TD_IREF
R603
8K2R2F-1-GP

#514405 PCH strap pin:

CFG3
1

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

R604
1KR2J-1-GP 0 : ENABLED
DY CFG[3] SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
2

1 : DISABLED
B B

CFG4
1

DISPLAY PORT PRESENCE STRAP

R605
1KR2J-1-GP 0 : ENABLED
CFG[4] AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT
2

1 : DISABLED
NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (CFG)
Size Document Number Rev
A3 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 6 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

VCC_CORE
HSW_ULT_DDR3L
D CPU1L 12 OF 19 D

L59 RSVD#L59 VCC C36

1D35V_S3 J58 C40
RSVD#J58 VCC
VCC C44
1D05S_VCCST AH26 C48
VDDQ VCC
AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
R703 1 2 75R2F-2-GP VR_SVID_ALERT# AJ37 E23
VDDQ VCC
AN33 VDDQ VCC E25
R704 1 2 130R2F-1-GP H_CPU_SVIDDAT AP43 E27
VCC_CORE VDDQ VCC
Layout Note: AR48
AY35
VDDQ VCC E29
E31
VDDQ VCC
1. Place close to CPU AY40 VDDQ VCC E33
#487822 2. VCC_SENSE/ VSS_SENSE AY44 VDDQ VCC E35

1
AY50 E37
impedance=50 ohm VDDQ VCC
E39
3. Length match<25mil R702 VCC
VCC_CORE F59 VCC VCC E41
100R2F-L1-GP-U N58 E43
RSVD#N58 VCC
AC58 E45

2
RSVD#AC58 VCC
VCC E47
[46] VCC_SENSE E63 VCC_SENSE VCC E49
AB23 RSVD#AB23 VCC E51
TP701 1 TP_VCCIO_OUT A59 VCCIO_OUT VCC E53
+VCCIOA_OUT E20 VCCIOA_OUT VCC E55
AD23 RSVD#AD23 VCC E57
AA23 RSVD#AA23 VCC F24
R701 AE59 F28
43R2J-GP RSVD#AE59 VCC
VCC F32
C
[46] VR_SVID_ALERT# 1 2H_CPU_SVIDALRT# L62 VIDALERT# VCC F36 C
H_CPU_SVIDCLK N63 HSW ULT POWER F40
3D3V_S5 [46] H_CPU_SVIDCLK VIDSCLK VCC
H_CPU_SVIDDAT L63 F44
[46] H_CPU_SVIDDAT VIDSOUT VCC
H_VCCST_PW RGD B59 F48
VCCST_PWRGD VCC
[46] H_VR_ENABLE F60 VR_EN VCC F52
R710 1 2 10KR2J-3-GP C59 F56
1D05S_VCCST IMVP_PW RGD_R DY VR_READY VCC
G23
VCC
1

D63 G25
C702 DY [96] PW R_DEBUG 150R2J-L1-GP-U PW R_DEBUG H59
VSS VCC
G27
SCD1U10V2KX-5GP R705 1 PWR_DEBUG# VCC
1D05S_VCCST 2 P62 G29
2

RSVDP60 VSS VCC

TP702 1 P60 RSVD_TP#P60 VCC G31
1

TP703 1 RSVDP61 P61 G33

U701 R706 RSVDN59 RSVD_TP#P61 VCC
TP704 1 N59 RSVD_TP#N59 VCC G35
DY 10KR2J-3-GP 1D05V_S0
X02 04141D05S_VCCST TP705 1 RSVDN61 N61 RSVD_TP#N61 VCC G37
1 NC#1 VCC 5 R711 T59 RSVD#T59 VCC G39
0.1A AD60 G41
2

RSVD#AD60 VCC
2 1 2 AD59 G43
[36,48] 1D05V_VTT_PW RGD A DY AA59
RSVD#AD59 VCC
G45
RSVD#AA59 VCC

C701
SC22U6D3V3MX-1-GP

C703
SC1U6D3V2KX-GP
3 4 H_VCCST_PW RGD [96] 0R0603-PAD-2-GP-U AE60 G47
GND Y RSVD#AE60 VCC

1
AC59 RSVD#AC59 VCC G49
DY DY AG58 RSVD#AG58 VCC G51
1

74LVC1G07GW -GP U59 G53

2
1D05S_VCCST RSVD#U59 VCC
EC701

73.01G07.0HG DY V59 G55

SCD1U10V2KX-5GP

RSVD#V59 VCC
G57
2

VCC
AC22 VCCST VCC H23
AE22 VCCST VCC J23
1 2 VCC_CORE AE23 K23
R707 VCCST VCC
VCC K57
100KR2F-L1-GP AB57 L22
VCC VCC
1

B B
AD57 VCC VCC M23
R709 AG57 M57
47KR2F-GP VCC VCC
C24 VCC VCC P57
C28 VCC VCC U57
C32 W57
2

VCC VCC
Need to fine tune to 1.05V.
HASW ELL-6-GP-U

[24,46] IMVP_PW RGD 1 2 IMVP_PW RGD_R

R713
100KR2F-L1-GP
1

R712 1

EC702
DY

SCD1U10V2KX-5GP
47KR2F-GP
2
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC CORE)

Size Document Number Rev
A3 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 7 of 104
5 4 3 2 1
 5 4 3 2 1
SSID = CPU

D D

CPU1A HSW_ULT_DDR3L 1 OF 19

[54] HDMI_DATA2# C54 DDI1_TXN0 EDP_TXN0 C45 EDP_TX0_DN [52]

[54] HDMI_DATA2 C55 DDI1_TXP0 EDP_TXP0 B46 EDP_TX0_DP [52]
[54] HDMI_DATA1# B58 A47
HDMI [54] HDMI_DATA1 C58
DDI1_TXN1
DDI1_TXP1
EDP_TXN1
EDP_TXP1 B47
EDP_TX1_DN
EDP_TX1_DP
[52]
[52]
[54] HDMI_DATA0# B55 DDI1_TXN2
A55 C47 +VCCIOA_OUT
[54] HDMI_DATA0 DDI1_TXP2 EDP_TXN2
[54] HDMI_CLK# A57 C46 Design Guideline:
DDI1_TXN3 EDP_TXP2
C [54] HDMI_CLK B57 DDI1_TXP3 EDP_TXN3 A49 EDP_COMP keep routing length max 100 mils. C

1
DDI EDP B49 R801
EDP_TXP3 Trace Width:20 mils.
C51 24D9R2F-L-GP
DDI2_TXN0
C50 DDI2_TXP0 EDP_AUXN A45 EDP_AUX_DN [52]
C53 DDI2_TXN1 EDP_AUXP B45 EDP_AUX_DP [52]
B54

2
DDI2_TXP1 EDP_COMP
C49 DDI2_TXN2 EDP_RCOMP D20
B50 A43 EDP_BRIGHTNESS 1 TP801
DDI2_TXP2 EDP_DISP_UTIL
A53 DDI2_TXN3
B53 DDI2_TXP3

HASW ELL-6-GP-U

B B

A <Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDI/EDP)
Size Document Number Rev
A3 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 8 of 104
 5 4 3 2 1

SSID = CPU
CPU1P HSW_ULT_DDR3L 16 OF 19

VSS H17
D33 VSS VSS H57
D34 VSS VSS J10
D D35 J22 D
VSS VSS
D37 VSS VSS J59
D38 VSS VSS J63
D39 VSS VSS K1
D41 VSS VSS K12
D42 VSS VSS L13
D43 VSS VSS L15
D45 VSS VSS L17
D46 VSS VSS L18
D47 VSS VSS L20
D49 VSS VSS L58
D5 VSS VSS L61
D50 VSS VSS L7
D51 VSS VSS M22
D53 VSS VSS N10
D54 VSS VSS N3
D55 VSS VSS P59
D57 VSS VSS P63
D59 VSS VSS R10
D62 VSS VSS R22
C D8 VSS VSS R8 C
E11 VSS VSS T1
E17 VSS VSS T58
F20 VSS VSS U20
F26 VSS VSS U22
F30 VSS VSS U61
F34 VSS VSS U9
F38 VSS VSS V10
F42 VSS VSS V3
F46 VSS VSS V7
F50 VSS VSS W20
F54 VSS VSS W22
F58 VSS VSS Y10
F61 VSS VSS Y59
G18 VSS VSS Y63
G22 VSS
G3 VSS
G5 VSS VSS V58
G6 VSS VSS AH46
G8 VSS VSS V23
B H13 E62 VSS_SENSE VSS_SENSE [46] B
VSS VSS_SENSE
VSS AH16

100R2F-L1-GP-U
1
HASWELL-6-GP-U
Layout Note:

R901
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE

2
impedance=50 ohm
3. Length match<25mil

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VSS)
Size Document Number Rev
A4 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 9 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

1D35V_S3

D D

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

SC10U6D3V3MX-GP
C1001

C1002

C1003

C1004

C1005

C1006
Layout Note:
1

1
DY DY DY As close to CPU as possible
2

2
SC2D2U6D3V2MX-GP

SC2D2U6D3V2MX-GP

C1019
SC2200P50V2KX-2GP

C1020
SC2200P50V2KX-2GP
C1017

C1018
1

1
2

BDW CAP BDW CAP

Layout Note:
Direct tie to CPU VccIn/Vss balls

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (Power CAP1)

Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 10 of 104
5 4 3 2 1
 5 4 3 2 1

MAX: 1.92A

1.838A 41mA 42mA

X02 0414
D
1D05V_HSIO +V1.05DX_MODPHY_PCH 1D05V_HSIO
X02 0414 +V1.05S_ASATA3PLL
D
R1101 1D05V_HSIO
X02 0414 +V1.05S_AUSB3PLL L1102
L1101
1 2 1 2 +V1.05S_ASATA3PLL

C1102
SC1U6D3V2KX-GP

C1101
SC1U6D3V2KX-GP
1 2 +V1.05S_AUSB3PLL

C1105
SC1U6D3V2KX-GP
0R0805-PAD-2-GP-U 0R0603-PAD-2-GP-U

C1106

C1107
1

1
C1103
SC1U6D3V2KX-GP
0R0603-PAD-2-GP-U

C1104

C1123
DY DY

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
1

1
DY DY

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
2

2
2

2
CAP need close to pin K9 L10 CAP need close to pin B18 CAP need close to pin B11

57mA 62mA 185mA

1D05V_S0 X02 0414 +V1.05S_APLLOPI X02 0414 1D05V_S0 +V1.05S_AXCK_DCB

3D3V_S5_PCH +V3.3A_PSUS
R1102 R1103
L1103 1 2 IND-2D2UH-196-GP +V1.05S_AXCK_DCB

SC10U6D3V3MX-GP
C 1 2 +V1.05S_APLLOPI 1 2 C
68.2R21D.10R

C1108

C1111
SC1U6D3V2KX-GP

C1112
SC10U6D3V3MX-GP

C1125
SC10U6D3V3MX-GP
1

1
C1109
SC1U6D3V2KX-GP

C1110
SC10U6D3V3MX-GP

C1124
SC10U6D3V3MX-GP
0R0603-PAD-2-GP-U 0R0603-PAD-2-GP-U
1

1
DY DY DY
DY DY

2
2

2
CAP need close to pin AA21 CAP need close to pin AC9 CAP need close to pin J18

31mA 658mA 1.632A 1mA

1D05V_S0
X02 0414 +1.05M_ASW 1D05V_S0
X02 0414 +V1.05S_CORE_PCH
1D05V_S0 R1104 R1105
IND-2D2UH-196-GP +V1.05S_AXCK_LCPLL RTC_AUX_S5
L1104 1 2 1 2
1 2 0R0805-PAD-2-GP-U
C1115
SC10U6D3V3MX-GP

C1116
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
C1117

SC1U6D3V2KX-GP
C1118

C1119
SC10U6D3V3MX-GP

C1120
SCD1U10V2KX-5GP

C1121
SCD1U10V2KX-5GP

C1122
SC1U6D3V2KX-GP
0R0603-PAD-2-GP-U
68.2R21D.10R
1

1
C1113
SC1U6D3V2KX-GP

C1114
1

DY DY DY DY
SC10U6D3V5KX-1GP

2
B B
2

CAP need close to pin A20 CAP need close to pin AE9 CAP need close to pin AE8 J11 CAP need close to pin AG10

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (Power CAP2)

Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 11 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = MEMORY
SA0_DIMA
SA1_DIMA
Note:
SA0 DIM0 = 0, SA1_DIM0 = 0

1
X02 0414 SO-DIMMA SPD Address is 0xA0
DIMM1 R1202 R1201
D [5] M_A_A[15:0] 0R0402-PAD-2-GP SO-DIMMA
0R0402-PAD-2-GP TS Address is 0x30 D
M_A_A0 98 NP1
M_A_A1 A0 NP1
97 NP2

2
M_A_A2 A1 NP2
96
M_A_A3 A2
95 110 M_A_RAS# [5]
M_A_A4 A3 RAS#
92 113 M_A_WE# [5]
M_A_A5 A4 WE#
91 115 M_A_CAS# [5]
M_A_A6 A5 CAS#
90
M_A_A7 A6
86 114 M_A_DIMA_CS#0 [5]
M_A_A8 A7 CS0#
89 121 M_A_DIMA_CS#1 [5]
M_A_A9 A8 CS1#
85
M_A_A10 A9
107 73 M_A_DIMA_CKE0 [5]
M_A_A11 A10/AP CKE0
84 74 M_A_DIMA_CKE1 [5]
M_A_A12 A11 CKE1
83
M_A_A13 A12
119 101 M_A_DIMA_CLK_DDR0 [5]
M_A_A14 A13 CK0
80 103 M_A_DIMA_CLK_DDR#0 [5]
M_A_A15 A14 CK0#
78
A15
79 102 M_A_DIMA_CLK_DDR1 [5]
[5] M_A_BS2 A16/BA2 CK1
104 M_A_DIMA_CLK_DDR#1 [5]
CK1#
109
[5] M_A_BS0 BA0
108 11
[5] M_A_BS1 BA1 DM0
[5] M_A_DQ[63:0] 28
M_A_DQ13 DM1
5 46
M_A_DQ8 DQ0 DM2
7 63
M_A_DQ14 DQ1 DM3
15 136
M_A_DQ10 DQ2 DM4
17 153
Layout Note: M_A_DQ9 4
DQ3 DM5
170
M_VREF_CA_DIMMA M_A_DQ12 DQ4 DM6
Place these caps 6
DQ5 DM7
187
M_A_DQ15 16
close to VREF_CA M_A_DQ11 DQ6
18 200 PCH_SMBDATA [18,67,96]
M_A_DQ29 DQ7 SDA
21 202 PCH_SMBCLK [18,67,96]
M_A_DQ28 DQ8 SCL
23
M_A_DQ30 DQ9 3D3V_S0
33 198
M_A_DQ31 DQ10 EVENT#
35
1

M_A_DQ25 DQ11
22 199
M_A_DQ24 DQ12 VDDSPD
C1201

C1218

C1202

24
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

M_A_DQ27 DQ13 SA0_DIMA

34 197
2

1
M_A_DQ26 DQ14 SA0 SA1_DIMA
36 201
M_A_DQ44 DQ15 SA1 C1203
M_A_DQ41
39
DQ16 DY
41 77

SCD1U16V2KX-3GP
2
M_A_DQ43 DQ17 NC#1
51 122
M_A_DQ47 DQ18 NC#2 1D35V_S3
C 53 125 C
M_A_DQ45 DQ19 NC#/TEST
40
M_A_DQ40 DQ20
42 75
M_A_DQ42 DQ21 VDD1
50 76
M_A_DQ46 DQ22 VDD2
52 81
Layout Note: M_A_DQ51 57
DQ23 VDD3
82
M_A_DQ50 DQ24 VDD4
Place these caps 59
DQ25 VDD5
87
M_A_DQ49 67 88
close to VREF_DQ M_A_DQ48 DQ26 VDD6
69 93
M_A_DQ52 DQ27 VDD7 1D35V_S3
56 94
M_VREF_DQ_DIMMA M_A_DQ53 DQ28 VDD8
58 99
M_A_DQ54 DQ29 VDD9
68 100
M_A_DQ55 DQ30 VDD10
M_A_DQ0
70
DQ31 VDD11
105 BDW CAP BDW CAP
129 106
M_A_DQ1 DQ32 VDD12
131 111

ST330U2VDM-4-GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
TC1201
DQ33 VDD13

C1207
SC2D2U10V3KX-1GP

C1208
SC2D2U6D3V2MX-GP

C1209
SC2D2U10V3KX-1GP
M_A_DQ2

C1220

C1221

C1222
141 112

1
M_A_DQ6 DQ34 VDD14
143 117
DQ35 VDD15
1

M_A_DQ5 130 118 DY

M_A_DQ4 DQ36 VDD16
C1204

C1205

C1206

132 123
DY
SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

2
M_A_DQ3 DQ37 VDD17
140 124
2

M_A_DQ7 DQ38 VDD18

M_A_DQ21
142
DQ39 BDW CAP
147 2
M_A_DQ20 DQ40 VSS
149 3
M_A_DQ17 DQ41 VSS
157 8
M_A_DQ16 DQ42 VSS
159 9
M_A_DQ18 DQ43 VSS
146 13
M_A_DQ19 DQ44 VSS
148
DQ45 VSS
14 X01 0224
0D675V_S0 M_A_DQ22 158 19

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
M_A_DQ23 DQ46 VSS

C1211

C1212

C1213
160 20

1
M_A_DQ36 DQ47 VSS
163 25
M_A_DQ33 DQ48 VSS C1210
165 26
M_A_DQ34 DQ49 VSS
175 31

SC1KP50V2KX-1GP
2

2
M_A_DQ38 DQ50 VSS
177 32
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

M_A_DQ37 DQ51 VSS

C1214

C1215

C1216

164 37
Layout Note:
1

M_A_DQ32 DQ52 VSS

166 38
M_A_DQ35 DQ53 VSS
DY Place these caps 174
DQ54 VSS
43
M_A_DQ39 176 44
close to VTT1 and
2

M_A_DQ62 DQ55 VSS

181 48
VTT2. M_A_DQ58 DQ56 VSS
183 49
M_A_DQ60 DQ57 VSS
191 54
M_A_DQ61 DQ58 VSS 1D35V_S3
B M_A_DQ63
193
180
DQ59 VSS
55
60
Layout Note: B
M_A_DQ59 DQ60 VSS
182
DQ61 VSS
61 Place these Caps near SO-DIMMA.
M_A_DQ56 192 65
M_A_DQ57 DQ62 VSS
194 66
DQ63 VSS
[5] M_A_DQS#[7:0] 71

D
M_A_DQS#1 VSS
10 72
M_A_DQS#3 DQS0# VSS Q1202
27 127
M_A_DQS#5 DQS1# VSS 5V_S5
45 128 2N7002K-2-GP
M_A_DQS#6 DQS2# VSS
62 133
M_A_DQS#0 135
DQS3# VSS
134
84.2N702.J31
M_A_DQS#2 DQS4# VSS 1D35V_S3 2ND = 84.2N702.031
152 138
M_A_DQS#4 DQS5# VSS
169 139

1
M_A_DQS#7 DQS6# VSS
186 144

S
DQS7# VSS R1208
[5] M_A_DQS[7:0] 145
M_A_DQS1 VSS 220KR2J-L2-GP M_A_B_DIMM_ODT R1206 M_A_DIMA_ODT0
12 150 1 2 66D5R2F-GP
M_A_DQS3 DQS0 VSS
29
DQS1 VSS
151 X02 0414
M_A_DQS5 47 155 R1207 1 2 66D5R2F-GP M_A_DIMA_ODT1

2
M_A_DQS6 DQS2 VSS Q1201
64 156
M_A_DQS0 DQS3 VSS FDV301N-NL-GP
137 161 R1205
M_A_DQS2 DQS4 VSS Vth = 1V max.
154 162
M_A_DQS4 DQS5 VSS DDR_PG_CTRL_R DDR_VTT_PG_CTRL
171 167 1 2 S D

D
DQS6 VSS [4] DDR_PG_CTRL DDR_VTT_PG_CTRL [49]
M_A_DQS7 188 168

1
DQS7 VSS
172
M_A_DIMA_ODT0 VSS 0R0402-PAD-2-GP R1204
116 173
M_A_DIMA_ODT1 ODT0 VSS 2MR2-GP
120 178 Q1201 must use Vth=1V. 84.00301.A31
2nd = 84.05067.031 DY
ODT1 VSS
179
VSS
M_VREF_CA_DIMMA 126 184 3rd = 84.3K329.031

2
VREF_CA VSS
1 185
Layout Note: M_VREF_DQ_DIMMA VREF_DQ VSS
189
VSS
All VREF traces should [4] DDR3_DRAMRST#
30
RESET# VSS
190
have width=20mil; 195
VSS
196
1

spacing=20 mil VSS

0D675V_S0 203 205
VTT1 VSS
204 206
ED1217 VTT2 VSS
AZ5725-01FDR7G-GP SKT_DDR 204P SMD
DDR3-204P-215-GP-U
62.10024.M31
2

A A

close to dimm

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM1
Size Document Number Rev
A2 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 12 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)DDR3-SODIMM2
Size Document Number Rev
A3 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 13 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C
(Blanking) C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)_SODIMM _SODIMM4
Size Document Number Rev
A4 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 14 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

D D

3D3V_S0

2
1
RN1501
SRN2K2J-1-GP
HSW_ULT_DDR3L
CPU1I 9 OF 19

3
4
HDMI
[52] L_BKLT_CTRL B8 EDP_BKLCTL DDPB_CTRLCLK B9 PCH_HDMI_CLK [54]
[24] L_BKLT_EN A9 EDP_BKLEN DDPB_CTRLDATA C9 PCH_HDMI_DATA [54]
C6 eDP SIDEBAND D9
[52] EDP_VDD_EN EDP_VDDEN DDPC_CTRLCLK
D11 DDPC_CTRLDATA 1 TP1502
DDPC_CTRLDATA
X02 0414

[19] PIRQA# U6 PIRQA#/GPIO77

[66,67] HDD_FALL_INT R1501 1 2 PIRQB# P4 C5
0R0402-PAD-2-GP PIRQC# PIRQB#/GPIO78 DDPB_AUXN
N4 PIRQC#/GPIO79 DDPC_AUXN B6
C PIRQD# N2 DISPLAY B5 C
TP1501 PCI_PME# PIRQD#/GPIO80 DDPB_AUXP
1 AD4 PME# DDPC_AUXP A6
PCIE

[19,20] MCP_GPIO55 MCP_GPIO55 U7

MCP_GPIO52 GPIO55
L1 GPIO52
MCP_GPIO54 L3 C8
GPIO54 DDPB_HPD HDMI_PCH_DET [54]
[20] MCP_GPIO51 R5 GPIO51 DDPC_HPD A8
[66] SENSOR_HUB_RST# L4 GPIO53 EDP_HPD D6 EDP_HPD [52]

3D3V_S0

HASW ELL-6-GP-U

SRN10KJ-6-GP
1 8 PIRQD#
2 7 PIRQB#
3 6 MCP_GPIO17 [20]
4 5 MCP_GPIO35 [19]
RN1505
SRN10KJ-6-GP
1 8
2 7 MCP_GPIO54
3 6 MCP_GPIO52
4 5 PIRQC#

RN1506
B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH ( EDP/GPIO/DDI )
Size Document Number Rev
A3 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 15 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PCH
CPU1K HSW_ULT_DDR3L 11 OF 19 USB 2.0 Table
Pair Device
F10 PERN5_L0 USB2N0 AN8 USB_PN0 [34]
E10 PERP5_L0 USB2P0 AM8 USB_PP0 [34]
0 USB3.0 port2
C23 PETN5_L0 USB2N1 AR7 USB_PN1 [35]
C22 PETP5_L0 USB2P1 AT7 USB_PP1 [35]
D 1 USB3.0 Port1 (Debug Port) D
F8 PERN5_L1 USB2N2 AR8 USB_PN2 [63]
E8 PERP5_L1 USB2P2 AP8 USB_PP2 [63]
2 USB2.0 Port3 (IOBD)
B23 PETN5_L1 USB2N3 AR10 USB_PN3 [66]
A23 PETP5_L1 USB2P3 AT10 USB_PP3 [66]
3 Sensor HUB
H10 PERN5_L2 USB2N4 AM15 USB_PN4 [52]
G10 PERP5_L2 USB2P4 AL15 USB_PP4 [52]
4 CAMERA
B21 PETN5_L2 USB2N5 AM13 USB_PN5 [63]
C21 PETP5_L2 USB2P5 AN13 USB_PP5 [63]
5 WLAN
E6 PERN5_L3 USB2N6 AP11 USB_PN6 [52]
F6 PERP5_L3 USB2P6 AN11 USB_PP6 [52]
6 Touch Panel
B22 PETN5_L3 USB2N7 AR13 USB_PN7 [63]
A21 PETP5_L3 USB2P7 AP13 USB_PP7 [63]
7 Card Reader
[63] PCIE_PRX_W LANTX_N3 G11 PERN3
[63] PCIE_PRX_W LANTX_P3 F11 PERP3 USB3RN1 G20 USB3_PRX_CTX_N0 [34]
SCD1U10V2KX-5GP H20
USB3RP1 USB3_PRX_CTX_P0 [34]
[63] PCIE_PTX_W LANRX_N3_C C1601 1 2 PCIE_PTX_W LANRX_N3 C29 PETN3 WLAN PCIE USB
[63] PCIE_PTX_W LANRX_P3_C 1 2 PCIE_PTX_W LANRX_P3 B30 C33 USB3_PTX_CRX_N0 [34]
C1602 SCD1U10V2KX-5GP PETP3 USB3TN1
USB3TP1 B34 USB3_PTX_CRX_P0 [34]
F13 PERN4
G13 PERP4 USB3RN2 E18 USB3_PRX_CTX_N1 [34]
USB3RP2 F18 USB3_PRX_CTX_P1 [34]
B29 PETN4
C A29 B33 C
PETP4 USB3TN2 USB3_PTX_CRX_N1 [34]
USB3TP2 A33 USB3_PTX_CRX_P1 [34]
G17 PERN1/USB3RN3
F17 PERP1/USB3RP3
C30
Layout Note:
PETN1/USB3TN3
C31 PETP1/USB3TP3 USBRBIAS# AJ10 USB_COMP 1 2 1. USB_COMP using 50 ohm single-ended impedance
AJ11 R1602 2. Isolation Spacing :15mil
USBRBIAS 22D6R2F-L1-GP
F15 PERN2/USB3RN4 RSVD#AN10 AN10 3. Total trace length<500mil
G15 PERP2/USB3RP4 RSVD#AM10 AM10

B31 PETN2/USB3TN4
A31 PETP2/USB3TP4
AL3 USB_OC#0_1 USB_OC#0_1 [18,35]
OC0/GPIO40# USB_OC#2_3
OC1/GPIO41# AT1 USB_OC#2_3 [63]
AH2 USB_OC#4_5 USB_OC#4_5 [20]
+V1.05S_AUSB3PLL R1601 OC2/GPIO42# USB_OC#6_7
E15 RSVD#E15 OC3/GPIO43# AV3
3KR2F-GP E13
PCIE_RCOMP RSVD#E13
1 2 A27 PCIE_RCOMP
B27 PCIE_IREF
3D3V_S5_PCH
RN1601
USB_OC#2_3 8 1
HASW ELL-6-GP-U USB_OC#6_7 7 2
Layout Note: [18] MCP_GPIO73 6
5
3
4
[17] PM_SUSW ARN#_R
1. PCIE_RCOMP/ PCIE_IREF trace width=12~15mil
B
2. Isolation Spacing: 12mil B
3. Total trace length<500mil SRN10KJ-6-GP

#515621

PCIE Table
Port Device Share BUS

1 N/A USB3.0_3

2 N/A USB3.0_4

3 WLAN

4 N/A
GPU GPU GPU GPU
5(L0~L3) N/A

6(L3) HDD SATA0

A <Core Design> A

6(L2) N/A SATA1

Wistron Corporation
6(L0~L1) N/A 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
GPU GPU GPU GPU Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (PCIE/USB)
Size Document Number Rev
A3 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 16 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PCH

RN1703
PM_RSMRST#
D 1
2
4
3 PM_PCH_PW ROK PCH strap pin: D

SRN10KJ-5-GP On Die DSW VR Enable R1720 RTC_AUX_S5

R1717 2 1 10KR2J-3-GP SYS_PW ROK 330KR2J-L1-GP
DY DSW ODVREN 1 2
Low = Disable
DSWODVREN High = Enable (default) 1
DY 2
* R1721
330KR2J-L1-GP

3D3V_S0

1
R1701
10KR2J-3-GP
CPU1H HSW_ULT_DDR3L 8 OF 19
2

SYSTEM POWER MANAGEMENT R1704

0R2J-2-GP
PM_SUSACK#_R AK2 AW7 DSW ODVREN NON DS3
XDP_DBRESET# SUSACK# DSWVRMEN PCH_DPW ROK
[96] XDP_DBRESET# AC3 SYS_RESET# DPWROK AV5 1 2 PM_RSMRST#
[24,96] SYS_PW ROK SYS_PW ROK AG2 AJ5 PCH_W AKE# 1 DY 2 PCIE_W AKE# [20,24]
R1706 1 PM_PCH_PW ROK AY7 SYS_PWROK WAKE# R1705 0R2J-2-GP
[24,26,36] PCH_PW ROK 2 PCH_PWROK
0R0402-PAD-2-GP 1 R1707 2 MPW ROK AB5 R1705: DY for OBFF disable
0R0402-PAD-2-GP PCI_PLTRST# APWROK PM_CLKRUN#
AG7 PLTRST# CLKRUN#/GPIO32 V5 1 R1709 2 PM_CLKRUN#_EC [24]
C X02 0414 AG4 PM_SUS_STAT#1 0R0402-PAD-2-GP C
SUS_STAT#/GPIO61 SUS_CLK_PCH TP1702 R1710
SUSCLK/GPIO62 AE6 1 2 SUS_CLK [24]
AP5 PM_SLP_S5# 1 0R0402-PAD-2-GP
PM_RSMRST# SLP_S5#/GPIO63 TP1703 A00 0604
AW6 RSMRST#
PM_SUSW ARN#_R AV4
[16] PM_SUSW ARN#_R PM_PW RBTN# SUSWARN#/SUSPWRDNACK#/GPIO30 PM_SLP_S4#
[24,96] PM_PW RBTN# AL7 PWRBTN# SLP_S4# AJ6 PM_SLP_S4# [24,49]
[24] AC_PRESENT AC_PRESENT AJ8 AT4 PM_SLP_S3# PM_SLP_S3# [24,36,48,49,51]
BATLOW # ACPRESENT/GPIO31 SLP_S3# PM_SLP_A#
AN4 BATLOW#/GPIO72 SLP_A# AL5 1
1 PCH_SLP_S0# AF3 AP4 PM_SLP_SUS# TP1704 PM_SLP_SUS# [24,38]
TP1706 PCH_SLP_W LAN# AM5 SLP_S0# SLP_SUS# PM_SLP_LAN# 1
1 SLP_WLAN#/GPIO29 SLP_LAN# AJ7
AC_PRESENT TP1705 TP1707

X02 0414
1

1 R1713 2 PCI_PLTRST#
EC1707

DY
SCD1U10V2KX-5GP

[24,63,65] PLT_RST#
0R0402-PAD-2-GP HASW ELL-6-GP-U
2

R1715 C1701
100KR2J-1-GP SC220P50V2KX-3GP NON DS3
DY A00 0609
DY
2

R1708
2

PM_SUSW ARN#_R 1 2 PM_SUSACK#_R

3D3V_S5 0R2J-2-GP PCH_DPW ROK 1 R1718 2
SRN0J-6-GP KBC_DPW ROK [24]
0R0402-PAD-2-GP
RN1701 [24] PM_SUSACK# 1 4 PM_SUSACK#_R

2
2 3 BATLOW # 2 3 PM_SUSW ARN#_R
1 4 AC_PRESENT
[24] PM_SUSW ARN# DS3 DS3 R1725
RN1702 100KR2F-L1-GP
SRN10KJ-5-GP
B B

1
R1703
1 2 PCH_W AKE#
1KR2J-1-GP
(CRB#514469)
3D3V_S5_PCH 3D3V_S0
R1714
8K2R2F-1-GP
1 2 PM_SUS_STAT# PM_CLKRUN# 1 2
R1724 DY 10KR2J-3-GP 3D3V_AUX_S5 R1727
100KR2J-1-GP
1 2 SUS_CLK_PCH
NON DS3
2

A00 0609

2
XDP_DBRESET# R1726
SYS_PW ROK 10KR2J-3-GP EC1701
PLT_RST# SC4D7P50V2CN-1GP DY

1
PCH_PW ROK 1KR2J-1-GP
Q1701
1

KBC_DPW ROK R1702

4 3 PM_RSMRST# 1 2 RSMRST#_KBC [24]
R1728
3V_5V_POK# 5 2 3V_5V_POK_C 1 2 3V_5V_POK [45]
DY DY DY DY DY NON DS3
1

6 1
EC1706 EC1702 EC1703 EC1704 EC1705 0R2J-2-GP
SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
2

2N7002KDW -GP
1 R1729 2 PM_SLP_SUS#
A 0R0402-PAD-2-GP <Core Design> A

84.2N702.A3F
2nd = 84.2N702.E3F Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
3rd = 75.00601.07C Taipei Hsien 221, Taiwan, R.O.C.
4th = 84.DMN66.03F
Title

PCH (PM)
Size Document Number Rev
A3 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 17 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PCH

X02 0414 C1801

D D
XTAL24_IN 1 R1810 2 XTAL24_IN_R 2 1

0R0402-PAD-2-GP
3D3V_S0 SC15P50V2JN-2-GP

1
X1801
RN1801

1
XTAL-24MHZ-86-GP
1 4 CLK_PCIE_WLAN_REQ3# R1802
1MR2J-1-GP 82.30004.891
2 3 MCP_GPIO37 [19] HSW_ULT_DDR3L 2nd = 82.30004.841
CPU1F 6 OF 19

4
C1802

2
SRN10KJ-5-GP
XTAL24_OUT 2 1

C43 A25 XTAL24_IN

CLKOUT_PCIE_N0 XTAL24_IN XTAL24_OUT SC15P50V2JN-2-GP
C42 B25
CLK_PCIE_REQ# CLKOUT_PCIE_P0 XTAL24_OUT +V1.05S_AXCK_LCPLL
[19] CLK_PCIE_REQ# U2
PCIECLKRQ0#/GPIO18
K21
RSVD#K21
B41 CLKOUT_PCIE_N1 RSVD#M21 M21
A41 C26 XCLK_BIASREF R1803 1 2 3KR2F-GP
CLK_PCIE_REQ# CLKOUT_PCIE_P1 DIFFCLK_BIASREF SRN10KJ-5-GP
Y5 PCIECLKRQ1#/GPIO19
C35 MCP_TESTLOW1 3 2
CLOCK TESTLOW_C35 MCP_TESTLOW2
[63] CLK_PCIE_WLAN_N3 C41 C34 4 1
CLKOUT_PCIE_N2 TESTLOW_C34 MCP_TESTLOW3 1SRN10KJ-5-GP
[63] CLK_PCIE_WLAN_P3
[63] CLK_PCIE_WLAN_REQ3# CLK_PCIE_WLAN_REQ3#
B42
AD1
CLKOUT_PCIE_P2
PCIECLKRQ2#/GPIO20
WLAN SIGNALS TESTLOW_AK8
TESTLOW_AL8
AK8
AL8 MCP_TESTLOW4 RN1803
4
3 2
RN1804
B38 AN15 CLK_PCI_LPC_R R1804 DEBUG
1 2 0R2J-2-GP CLK_PCI_LPC [65]
CLKOUT_PCIE_N3 CLKOUT_LPC_0 CLK_PCI_KBC_R R1805
C37 AP15 1 2 33R2J-2-GP CLK_PCI_KBC [24]
CLK_PCIE_REQ# CLKOUT_PCIE_P3 CLKOUT_LPC_1
N1 PCIECLKRQ3#/GPIO21
B35 PCIE_CLK_XDP_N [96]
CLKOUT_ITPXDP#
A39 A35 PCIE_CLK_XDP_P [96]
CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
B39 CLKOUT_PCIE_P4
C CLK_PCIE_REQ# U5 C
PCIECLKRQ4#/GPIO22

EC1801
SC10P50V2JN-4GP

EC1802
SC10P50V2JN-4GP
B37
CLKOUT_PCIE_N5 DY DY

1
A37
CLK_PCIE_REQ# CLKOUT_PCIE_P5
T2
PCIECLKRQ5#/GPIO23

2
HASWELL-6-GP-U
3D3V_S5_PCH

Based on the swap report.

RN1807
SML0_DATA 8 1
LPC_AD[3..0] HSW_ULT_DDR3L
[24,65] LPC_AD[3..0] CPU1G 7 OF 19 SML0_CLK 7 2
RN1806 SMB_CLK 6 3
LPC_AD0 8 1 LPC_LAD0_PCH LPC_LAD0_PCH AU14 AN2 MCP_GPIO11 SMB_DATA 5 4
LPC_AD1 LPC_LAD1_PCH LPC_LAD1_PCH LAD0 SMBALERT#/GPIO11 SMB_CLK
7 2 AW12 AP2
LPC_AD2 LPC_LAD2_PCH LPC_LAD2_PCH LAD1 SMBCLK SMB_DATA SRN2K2J-4-GP
6 3 AY12 LPC AH1
LPC_AD3 LPC_LAD3_PCH LPC_LAD3_PCH LAD2 SMBUS SMBDATA CARD_PWR_EN
5 4 AW11 AL2
LPC_LFRAME#_PCH LAD3 SML0ALERT#/GPIO60 SML0_CLK
AV12 LFRAME# SML0CLK AN1
SRN0J-7-GP-U AK1 SML0_DATA RN1809
R1801 1 SML0DATA MCP_GPIO73 SRN10KJ-6-GP
[24,65] LPC_FRAME# 2 AU4 MCP_GPIO73 [16]
0R0402-PAD-2-GP SML1ALERT#/PCHHOT#/GPIO73 SML1_CLK CARD_PWR_EN
SML1CLK/GPIO75 AU3 SML1_CLK [24,26] 8 1
AH3 SML1_DATA [16,35] USB_OC#0_1 7 2
SML1DATA/GPIO74 SML1_DATA [24,26]
[24,25] SPI_CLK_R 33R2J-2-GP 1 2 R1806 PCH_SPI_CLK AA3 [20,24] EC_SCI# 6 3
R1807 1 PCH_SPI_CS0# SPI_CLK TP_CL_CLK 1 TP1801 MCP_GPIO11
[24,25] SPI_CS0#_R 2 Y7 AF2 5 4
0R0402-PAD-2-GP SPI_CS0# CL_CLK TP_CL_DATA1 TP1802
Y4 SPI_CS1# CL_DATA AD2
AC2 SPI C-LINK AF4 TP_CL_RST# 1 TP1803
0R0402-PAD-2-GP R1808 PCH_SPI_SI SPI_CS2# CL_RST#
[24,25] SPI_SI_R 1 2 AA2 SRN2K2J-1-GP
0R0402-PAD-2-GP R1809 PCH_SPI_SO SPI_MOSI
[24,25] SPI_SO_R 1 2 AA4 SPI_MISO
0R0402-PAD-2-GP 1 2 R1811 PCH_SPI_DQ2 Y6 SML1_DATA 3 2
[25] SPI_WP# SPI_IO2
0R0402-PAD-2-GP 1 2 R1812 PCH_SPI_DQ3 AF1 SML1_CLK 4 1
[25] SPI_HOLD# SPI_IO3
B B
RN1811
X02 0414
3D3V_S5 3D3V_S0

HASWELL-6-GP-U
RN1810
2
1

3 2 3D3V_S0
RN1802 4 1
SRN1KJ-7-GP
SRN10KJ-5-GP
2N7002KDW-GP
3
4

SMB_DATA 6 1 PCH_SMBDATA [12,67,96]

PCH_SPI_DQ3
84.2N702.A3F 5 2
PCH_SPI_DQ2 2nd = 84.2N702.E3F
3rd = 75.00601.07C 4 3
4th = 84.DMN66.03F
Q1801

PCH_SMBCLK [12,67,96]

SMB_CLK

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
PCH (CLOCK/SMBUS/CL/LPC/SPI)Rev
Document Number
Custom A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 18 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
RTC_X1

1 2 RTC_X2
R1915 10MR2J-L-GP
X1901
X02 0414 X02 0414
1 4

D
RTC_AUX_S5 D
R1913

2
1 2 PCH_INTVRMEN SC12P50V2JN-3GP 2 3 SC12P50V2JN-3GP
DY C1903 C1904
330KR2J-L1-GP

1
X-32D768KHZ-65-GP

1
Integrated SUS 1V VRM Enable RTC_AUX_S5 R1903 R1901 82.30001.A41
330KR2J-L1-GP 1MR2J-1-GP 2nd = 82.30001.841
Low = External VRs
INTVRMEN High = Internal VRs*

2
1
2
RN1901
CPU1E HSW_ULT_DDR3L 5 OF 19
SRN20KJ-1-GP

RTC_X1 AW5

4
3
RTC_X2 RTCX1
Q1901 AY5 RTCX2
SM_INTRUDER# AU6 J5 SATA3_PRX_HDDTX_N0 [56]
PCH_INTVRMEN AV7 INTRUDER# SATA_RN0/PERN6_L3
[24] RTCRST_ON G INTVRMEN SATA_RP0/PERP6_L3 H5 SATA3_PRX_HDDTX_P0 [56]
SRTC_RST# AV6 RTC B15 SATA3_PTX_HDDRX_N0 [56]
D RTC_RST# AU7
SRTCRST#
RTCRST#
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3 A15 SATA3_PTX_HDDRX_P0 [56]
HDD1

SC1U6D3V2KX-GP
1

2
C1901
S SATA_RN1/PERN6_L2 J8

1
R1902 G1901 H8
SATA_RP1/PERP6_L2

1
10KR2J-3-GP C1902 A17
2N7002K-2-GP SATA_TN1/PETN6_L2

GAP-OPEN
SC1U6D3V2KX-GP B17

2
C 84.2N702.J31 SATA_TP1/PETP6_L2 C
2

2
2ND = 84.2N702.031 HDA_BITCLK AW8 J6
HDA_SYNC HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1
AV11 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 H6
(#514849) HDA_RST# AU8 B14
HDA_SDIN0 HDA_RST#/I2S_MCLK# AUDIO SATA SATA_TN2/PETN6_L1
[27] HDA_SDIN0 AY10 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1 C15
AU12 HDA_SDI1/I2S1_RXD
HDA_SDOUT AU11 F5
HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0
Layout: Place at the open door area. TP1902 1TP_HDA_DOCK_EN# AW10 HDA_DOCK_EN#/I2S1_TXD# SATA_RP3/PERP6_L0 E5
AV10 HDA_DOCK_RST#/I2S1_SFRM# SATA_TN3/PETN6_L0 C17
AY8 I2S1_SCLK SATA_TP3/PETP6_L0 D17
[27] HDA_CODEC_BITCLK R1907 1 2 33R2J-2-GP HDA_BITCLK
X02 0414
[27] HDA_CODEC_SYNC R1908 1 2 0R0402-PAD-2-GPHDA_SYNC V1 EC_SMI# EC_SMI# [20,24]
SATA0GP/GPIO34 +V1.05S_ASATA3PLL
SATA1GP/GPIO35 U1 MCP_GPIO35 [15]
[27,29] HDA_CODEC_RST# R1911 1 2 33R2J-2-GP HDA_RST# V6
SATA2GP/GPIO36 MCP_GPIO36 [20]
SATA3GP/GPIO37 AC1 MCP_GPIO37 [18]
X02 0414 TP1901 1 PCH_JTAG_TRST# AU62
PCH_JTAG_TCK PCH_TRST# SATA_IREF R1904 1
AE62 PCH_TCK SATA_IREF A12 2
Flash Descriptor Security Overide/ [27] HDA_CODEC_SDOUT R1912 1 2 33R2J-2-GP HDA_SDOUT PCH_JTAG_TDI AD61 L11 0R0402-PAD-2-GP
PCH_JTAG_TDO PCH_TDI RSVD#L11
Intel ME Debug Mode AE61 PCH_TDO RSVD#K10 K10
[24] ME_UNLOCK R1909 1 2 1KR2J-1-GP PCH_JTAG_TMS AD62 JTAG C12 SATA_RCOMP 1 2
PCH_TMS SATA_RCOMP SATA_LED#
Low = Default * AL11 RSVD#AL11 SATALED# U3
HDA_SDOUT High = Enable AC4 R1906
XDP_TCK_JTAGX RSVD#AC4 3KR2F-GP
AE63 JTAGX
The internal pull-down is disabled after AV2 RSVD#AV2
PLTRST# deasserts

B Layout Note: B
HASW ELL-6-GP-U 4mil trace at break-out and 3
1D05S_VCCST 12-15mil trace with <0.2 ohms
and length total <= 500mils.
2
DY 1 PCH_JTAG_TDI
R1916 51R2J-2-GP 3D3V_S0
2 1 PCH_JTAG_TDO
R1917 DY 51R2J-2-GP RN1902
2 1 PCH_JTAG_TMS 1 8
R1918 DY 51R2J-2-GP
[15] PIRQA#
[20,24] INT_SERIRQ 2 7
2 1 XDP_TCK_JTAGX 3 6
R1919 DY 1KR2J-1-GP
[18] CLK_PCIE_REQ#
[15,20] MCP_GPIO55 4 5

SRN10KJ-6-GP
X01 0224
3D3V_S0
R1905
1 2 HDA_CODEC_BITCLK SATA_LED# 2 DY 1
1 2 PCH_JTAG_TCK
EC1901 R1920 DY 51R2J-2-GP
SC10P50V2JN-4GP 10KR2J-3-GP

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (RTC/SATA/HDA/JTAG)
Size Document Number Rev
A3 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 19 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

3D3V_S5
RN2006
1 4 MCP_GPIO12
2 3 MCP_GPIO27 1D05S_VCCST

1
SRN10KJ-5-GP
HSW_ULT_DDR3L 10 OF 19
CPU1J R2018
1KR2J-1-GP

2
D P1 D60 PCH_THERMTRIP D
[67] INT2_SELECT BMBUSY#/GPIO76 THRMTRIP#
MCP_GPIO8 AU2 V4 H_RCIN# H_RCIN# [24]
MCP_GPIO12 GPIO8 RCIN#/GPIO82 INT_SERIRQ
AM7 T4 INT_SERIRQ [19,24]
MCP_GPIO15 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ PCH_OPIRCOMP
2nd = 83.R2004.C8F AD6
GPIO15 PCH_OPI_RCOMP
AW15 1 2
TP2008 1MCP_GPIO16 Y1 MISC AF20
MCP_GPIO17 GPIO16 RSVD#AF20 R2003
83.R2004.G8F [15] MCP_GPIO17 T3
GPIO17 RSVD#AB21
AB21
49D9R2F-GP Layout Note:
[25] RTC_DET# AD5
RB751V-40H-GP MCP_GPIO27 GPIO24
[17,24] PCIE_WAKE# 1 DY 2 AN5
GPIO27 1.Referenced "continuous" VSS plane only.
D2001 R2005 MCP_GPIO28 AD7
0R2J-2-GP MCP_GPIO26 GPIO28 2.Avoid routing next to clock pins or noisy
AN3
INT_TP#_C GPIO26 signals.
[24,62] INT_TP# K A R6
MCP_GPIO56 GSPI0_CS#/GPIO83
A00 0604 AG6
GPIO56 GSPI0_CLK/GPIO84
L6 3. Trace width: 12~15mil
AP1 N6 SATA_ODD_PWRGT 1 TP2004
[44] AD_IA_HW2 GPIO57 GSPI0_MISO/GPIO85 LPSS_GSPI0_MOSI_BBS0_R
4. Isolation Spacing: 12mil
[44] AD_IA_HW AL4 L8
MCP_GPIO59 GPIO58 GSPI0_MOSI/GPIO86 5. Max length: 500mil
[15,19] MCP_GPIO55 1 R2008 2 AT5 R7
0R0402-PAD-2-GP MCP_GPIO44 GPIO59 GPIO GSPI1_CS#/GPIO87
AK4 L5
MCP_GPIO47 GPIO44 GSPI1_CLK/GPIO88
AB6 N7
MCP_GPIO46 R2026 1 BOARD_ID1 GPIO47 GSPI1_MISO/GPIO89 MCP_GPIO90 TP2014
DY 2
ALS_INT#
U4
GPIO48 GSPI_MOSI/GPIO90
K2
KB_LED_BL_DET
1
0R2J-2-GP [52,66] ALS_INT# Y3
GPIO49 UART0_RXD/GPIO91
J1 1 TP2015 X02 0417
MCP_GPIO50 P3 K3 DBC_EN [52]
3D3V_S5_PCH MCP_GPIO8 R2027 1 GPIO50 UART0_TXD/GPIO92 3D3V_S0
0R2J-2-GP
DY 2 [21] HSIOPC
MCP_GPIO13
Y2
HSIOPC/GPIO71 SERIAL IO UART0_RTS#/GPIO93
J2 CAMERA_DET# [52]
RN2002
AT3 G1
MCP_GPIO14 GPIO13 UART0_CTS#/GPIO94 MCP_GPIO0 1
AH4
GPIO14 UART1_RXD/GPIO0
K4 TP2007 X01 0214 SRN10KJ-6-GP
1

TP2002 1CAMERA_PWR_EN AM4 G2 MCP_GPIO1 1 TP2009 ALS_INT# 8 1

R2022 MCP_GPIO45 GPIO25 UART1_TXD/GPIO1 H_RCIN#
AG5 J3 7 2
MCP_GPIO46 GPIO45 UART1_RST#/GPIO2
10KR2J-3-GP AG3 J4 BLUETOOTH_EN [63] [19,24] EC_SMI# 6 3
GPIO46 UART1_CTS#/GPIO3 I2C0_SDA
F2 [19] MCP_GPIO36 5 4
EC_SWI# I2C0_SDA/GPIO4 I2C0_SCL
AM3 F3
2

GPIO9 I2C0_SCL/GPIO5 I2C1_SDA

[18,24] EC_SCI# AM2 G4 I2C1_SDA [62]
HDD_DEVSLP GPIO10 I2C1_SDA/GPIO6 I2C1_SCL
P2
DEVSLP0/GPIO33 I2C1_SCL/GPIO7
F1 I2C1_SCL [62] X01 0214
A00 0604 TP2005 1MCP_GPIO70 C4 E3 COLOR_ENGINE 1 TP2003
SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64
MCP_R

0R0402-PAD-2-GP 1 2 R2002 MCP_GPIO44 1MCP_GPIO38 L2 F4 3D3V_S0

TP2006 DEVSLP1/GPIO38 SDIO_CMD/GPIO65
0R0402-PAD-2-GP 1 2 R2009 MCP_GPIO26 N5 D3 LPSS_SDIO_D0_CMNHDR RN2007
0R0402-PAD-2-GP R2010 MCP_GPIO56 HDA_SPKR DEVSLP2/GPIO39 SDIO_D0/GPIO66 I2C0_SCL
1 2 [27] HDA_SPKR V2 E4 4 1
0R0402-PAD-2-GP R2020 MCP_GPIO47 SPKR/GPIO81 SDIO_D1/GPIO67 MCP_GPIO68 TP2019 I2C0_SDA
1 2 C3 1 3 2
0R0402-PAD-2-GP R2015 MCP_GPIO14 SDIO_D2/GPIO68
1 2 E2
0R0402-PAD-2-GP R2016 MCP_GPIO28 SDIO_D3/GPIO69 SRN10KJ-5-GP
1 2
0R0402-PAD-2-GP 1 2 R2019 MCP_GPIO13 RN2008
0R0402-PAD-2-GP 1 2 R2028 MCP_GPIO45 HASWELL-6-GP-U X01 0303 I2C1_SDA 4 1
I2C1_SCL 3 2

C X02 0414 SRN2K2J-1-GP C

3D3V_S5_PCH
HSIOPC R2007 1 2100KR2J-1-GP
CAMERA_DET# 1 2
R2013 100KR2J-1-GP
10KR2J-3-GP 1 2 R2017 MCP_GPIO8
10KR2J-3-GP 1 2 R2004 MCP_GPIO46
10KR2J-3-GP 1 2 R2001 AD_IA_HW
10KR2J-3-GP 1 2 R2021 AD_IA_HW2

3D3V_S5_PCH
RN2012
SRN10KJ-6-GP
1 8 EC_SWI#
2 7 USB_OC#4_5 [16]
PCH strap pin:
3 6 RTC_DET#
4 5 MCP_GPIO59 NO REBOOT
3D3V_S0
1KR2J-1-GP
* Low = Disable (Default) R2006
3D3V_S0 HDA_SPKR 1 2 HDA_SPKR
High = Enable DY
RN2011
SRN10KJ-6-GP
1 8 MCP_GPIO50 The internal pull-down is disabled after
2 7 MCP_GPIO51 [15] PLTRST# deasserts
3 6 DBC_EN
4 5 BLUETOOTH_EN

1 2 INT2_SELECT
R2025 10KR2J-3-GP
3D3V_S0
Top-Block Swap Override mode

1
3D3V_S0
High = Enable "Top-Block swap" DY R2011
SDIO_D0 mode (Default) 1KR2J-1-GP
1 2 BOARD_ID1
R2023 10KR2J-3-GP
/ GPIO66 * Low = Disable "Top-Block swap" mode

2
HDD_DEVSLP LPSS_SDIO_D0_CMNHDR
1 DY 2
R2024 10KR2J-3-GP The internal pull-down is disabled after
B B
PLTRST# deasserts

Need SW double confirm if that's needed Top-Block swap

3D3V_S5_PCH
TLS Confidentiality
1

GPIO15
* Low = Disable Intel ME Crypto TLS DY R2014
1KR2J-1-GP
High = Enable Intel ME Crypto TLS
2

The internal pull-down is disabled after MCP_GPIO15

RSMRST# deasserts.

3D3V_S0
Boot BIOS Strap Bit BBS
1

Boot BIOS * Low = SPI DY R2012

Destination High = LPC 1KR2J-1-GP
2

The internal pull-down is disabled after LPSS_GSPI0_MOSI_BBS0_R

PLTRST# deasserts

Need double confirm, GPIO table set to GPI if that's needed PH or PL

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (GPIO/MISC)
Size Document Number Rev
A2 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 20 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
3D3V_S5_PCH
DSW
X02 0414

+3.3A_DSW _PRTCSUS 1 R2102 2

1
+V1.05DX_MODPHY_PCH
0R0603-PAD-2-GP-U Intel Recommend
D D
HSW_ULT_DDR3L
CPU1M 13 OF 19 C2109

2
X02 0414 SC1U6D3V2KX-GP
K9 VCCHSIO
1D05V_S0 L10 VCCHSIO RTC_AUX_S5
M9 VCCHSIO
1 R2105 2 +V1.05S_AIDLE N8 HSIO RTC AH11
0R0402-PAD-2-GP VCC1_05 VCCSUS3_3
P9 VCC1_05 VCCRTC AG10
+V1.05S_AUSB3PLL B18 AE7 +VCCRTCEXT 1 2
VCCUSB3PLL DCPRTC

1
C2105
SC1U6D3V2KX-GP
+V1.05S_ASATA3PLL B11 C2110
VCCSATA3PLL SCD1U16V2KX-3GP 3D3V_S5
DY

2
TP2102 1 TP_VCCAPLLOPI_VAL Y20 SPI Y8
RSVD#Y20 VCCSPI
+V1.05S_APLLOPI AA21 VCCAPLL
OPI

1
W21 VCCAPLL
AG14 C2147
VCCASW
AG13 1D05V_S0

2
VCCASW SCD1U16V2KX-3GP
TP2107 1 +V1.05A_VCCUSB3SUS J13 USB3
3D3V_S5_PCH +V3.3A_1.5A_HDA DCPSUS3
VCC1_05 J11 +V1.05S_CORE_PCH Broadwell(#514849): No series resistors (0 ohm).
VCC1_05 H11 Haswell(#486713):Series resistor:5 ohm.
1 R2108 2 +V3.3A_1.5A_HDA AH14 HDA H15
VCCHDA VCC1_05
X02 0414 VCC1_05 AE8 R2110 C2114

1
C2116
SC1U6D3V2KX-GP
0R0603-PAD-2-GP-U AF22 5D1R2F-GP SC1U6D3V2KX-GP
TP2108 +V1.05A_USB2SUS VRM VCC1_05
1 AH13 DCPSUS2 DCPSUSBYP#AG19 AG19 +PCH_VCCDSW 1 2 PCH_VCCDSW _R 1 2
CORE AG20 BDW/HSW

2
DCPSUSBYP#AG20
X02 0414 VCCASW AE9 +1.05M_ASW
AF9 C2101
3D3V_S5 +V3.3A_DSW _P 3D3V_S0 VCCASW
+V3.3A_PSUS AC9 VCCSUS3_3 VCCASW AG8
C X02 0414 AA9 VCCSUS3_3
GPIO/LPC
DCPSUS1#AD10 AD10 +V1.05A_SUS_PCH 1 TP2106 +V3.3A_DSW _P 1 2 +PCH_VCCDSW C
1 R2101 2 +V3.3A_DSW _P +V3.3A_DSW _P AH10 VCCDSW3_3 DCPSUS1#AD8 AD8
0R0402-PAD-2-GP 1 R2112 2 +V3.3S_PCORE V8
0R0402-PAD-2-GP C2123 VCC3_3 3D3V_S0 SCD47U10V2KX-GP
W9 VCC3_3
1

1
SC10U6D3V3MX-GP
THERMAL SENSOR VCCTS1_5 J15 1D5V_S0 WistronSKB: match Intel design_20130417
DY C2136 K14
SCD1U16V2KX-3GP
VCC3_3
K16
(#489999_2013WW15)
2

2
VCC3_3

C2128
SC1U6D3V2KX-GP
1
X02 0414
+V1.05S_AXCK_DCB J18 VCCCLK
1D05V_S0 +V1.05S_SSCF100 K19 SERIAL IO U8 +V3.3S_1.8S_LPSS_SDIO

2
VCCCLK VCCSDIO
+V1.05S_AXCK_LCPLL A20 VCCACLKPLL VCCSDIO T9
1 R2117 2 +V1.05S_SSCF100 +V1.05S_SSCF100 J17 VCCCLK
0R0402-PAD-2-GP +V1.05S_SSCFF R21 VCCCLK
C2137
SC1U6D3V2KX-GP

T21 LPT LP POWER

VCCCLK
1

1 TP_V1.05S_SSCF100 K18 SUS OSCILLATOR AB8 +V1.05A_AOSCSUS 1 TP2109

TP2103 RSVD#K18 DCPSUS4
1 TP_V1.05S_AXCK_DCB M20 RSVD#M20
TP2104 1 TP_V1.05S_SSCFF V21
2

TP2101 RSVD#V21
+V3.3A_PSUS AE20 VCCSUS3_3 RSVD#AC20 AC20 TP_V1.05S_APLLOPI 1 TP2105
AE21 VCCSUS3_3 VCC1_05 AG16 1D05V_S0
USB2 AG17
VCC1_05

1
C2135
SC1U6D3V2KX-GP
2
X02 0414 HASW ELL-6-GP-U

1D05V_S0 +V1.05S_SSCFF

B B
1 R2118 2 +V1.05S_SSCFF
0R0402-PAD-2-GP A00 0604
C2138
SC1U6D3V2KX-GP
1

1D05V_S0 1D05V_HSIO
R2122
2

1 2

0R0805-PAD-2-GP-U X02 0414

+V3.3S_1.8S_LPSS_SDIO 3D3V_S0
R2123
1 2 HSIOPC_R 1 R2103 2
[20] HSIOPC
HSIO 0R0402-PAD-2-GP

1
0R2J-2-GP 1D05V_HSIO
9

U2101 C2104
SC1U6D3V2KX-GP
ON

2
5V_S5 1 8 R2114
VDD GND HSIO_OUT
1D05V_S0 2 D#2 S#7 7 1 0R5J-5-GP
2
3 D#3 S#6 6
4 D#4 S#5 5 HSIO
HSIO

1
SLG59M1470VTR-GP C2142
74.59147.093 SC10U6D3V5KX-1GP
1

2
HSIO C2141 HSIO
SC4D7U6D3V3KX-GP
A <Core Design> A
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (POWER2)
Size Document Number Rev
A3 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 21 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PCH

D D

HSW_ULT_DDR3L
CPU1Q 17 OF 19

DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 TP_DC_TEST_A4 TP2202
AY3 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 A4 1
TP2201 1TP_DC_TEST_AY60 AY60 DAISY_CHAIN_NCTF_AY60
DC_TEST_AY61_AW61 AY61 A60 TP_DC_TEST_A60 1 TP2203
DC_TEST_AY62_AW62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 DC_TEST_A61_B61
AY62 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A61
TP2204 1TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 A62 TP_DC_TEST_A62 1 TP2205
DC_TEST_A3_B3 B3 AV1 TP_DC_TEST_AV1 1 TP2206
DC_TEST_A61_B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 TP_DC_TEST_AW1 TP2207
B61 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW1 1
DC_TEST_B62_B63 B62 AW2 DC_TEST_AY2_AW2
DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 DC_TEST_AY3_AW3
B63 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW3
DC_TEST_C1_C2 C1 AW61 DC_TEST_AY61_AW61
DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 DC_TEST_AY62_AW62
C2 DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW62
AW63 TP_DC_TEST_AW63 1 TP2208
C
DAISY_CHAIN_NCTF_AW63 C
HASWELL-6-GP-U

HSW_ULT_DDR3L
CPU1R 18 OF 19

RSVD#N23 N23
RSVD#R23 R23
AT2 RSVD#AT2 RSVD#T23 T23
AU44 RSVD#AU44 RSVD#U10 U10
AV44 RSVD#AV44
D15 RSVD#D15
RSVD#AL1 AL1
RSVD#AM11 AM11
F22 RSVD#F22 RSVD#AP7 AP7
B H22 RSVD#H22 RSVD#AU10 AU10 B
J21 RSVD#J21 RSVD#AU15 AU15
RSVD#AW14 AW14
RSVD#AY14 AY14

HASWELL-6-GP-U

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (RSVD)
Size Document Number Rev
A4 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 22 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PCH

D D

HSW_ULT_DDR3L HSW_ULT_DDR3L
CPU1N 14 OF 19 CPU1O 15 OF 19

A11 VSS VSS AJ35 AP22 VSS VSS AV59

A14 VSS VSS AJ39 AP23 VSS VSS AV8
A18 VSS VSS AJ41 AP26 VSS VSS AW16
A24 VSS VSS AJ43 AP29 VSS VSS AW24
A28 VSS VSS AJ45 AP3 VSS VSS AW33
A32 VSS VSS AJ47 AP31 VSS VSS AW35
A36 VSS VSS AJ50 AP38 VSS VSS AW37
A40 VSS VSS AJ52 AP39 VSS VSS AW4
A44 VSS VSS AJ54 AP48 VSS VSS AW40
A48 VSS VSS AJ56 AP52 VSS VSS AW42
A52 VSS VSS AJ58 AP54 VSS VSS AW44
A56 VSS VSS AJ60 AP57 VSS VSS AW47
AA1 VSS VSS AJ63 AR11 VSS VSS AW50
AA58 VSS VSS AK23 AR15 VSS VSS AW51
AB10 VSS VSS AK3 AR17 VSS VSS AW59
AB20 VSS VSS AK52 AR23 VSS VSS AW60
AB22 VSS VSS AL10 AR31 VSS VSS AY11
AB7 VSS VSS AL13 AR33 VSS VSS AY16
AC61 VSS VSS AL17 AR39 VSS VSS AY18
AD21 VSS VSS AL20 AR43 VSS VSS AY22
AD3 VSS VSS AL22 AR49 VSS VSS AY24
AD63 VSS VSS AL23 AR5 VSS VSS AY26
AE10 VSS VSS AL26 AR52 VSS VSS AY30
C AE5 AL29 AT13 AY33 C
VSS VSS VSS VSS
AE58 VSS VSS AL31 AT35 VSS VSS AY4
AF11 VSS VSS AL33 AT37 VSS VSS AY51
AF12 VSS VSS AL36 AT40 VSS VSS AY53
AF14 VSS VSS AL39 AT42 VSS VSS AY57
AF15 VSS VSS AL40 AT43 VSS VSS AY59
AF17 VSS VSS AL45 AT46 VSS VSS AY6
AF18 VSS VSS AL46 AT49 VSS VSS B20
AG1 VSS VSS AL51 AT61 VSS VSS B24
AG11 VSS VSS AL52 AT62 VSS VSS B26
AG21 VSS VSS AL54 AT63 VSS VSS B28
AG23 VSS VSS AL57 AU1 VSS VSS B32
AG60 VSS VSS AL60 AU16 VSS VSS B36
AG61 VSS VSS AL61 AU18 VSS VSS B4
AG62 VSS VSS AM1 AU20 VSS VSS B40
AG63 VSS VSS AM17 AU22 VSS VSS B44
AH17 VSS VSS AM23 AU24 VSS VSS B48
AH19 VSS VSS AM31 AU26 VSS VSS B52
AH20 VSS VSS AM52 AU28 VSS VSS B56
AH22 VSS VSS AN17 AU30 VSS VSS B60
AH24 VSS VSS AN23 AU33 VSS VSS C11
AH28 VSS VSS AN31 AU51 VSS VSS C14
AH30 VSS VSS AN32 AU53 VSS VSS C18
AH32 VSS VSS AN35 AU55 VSS VSS C20
AH34 VSS VSS AN36 AU57 VSS VSS C25
AH36 VSS VSS AN39 AU59 VSS VSS C27
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH40 VSS VSS AN42 AV16 VSS VSS C39
AH42 VSS VSS AN43 AV20 VSS VSS C57
B B
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
AH51 VSS VSS AN48 AV33 VSS VSS D18
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
AH57 VSS VSS AN52 AV39 VSS VSS D23
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31

HASW ELL-6-GP-U

HASW ELL-6-GP-U

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU(VSS)
Size Document Number Rev
A3 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 23 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = KBC VBAT 3D3V_AUX_KBC

X02 0414 VBAT MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
VBAT PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
R2402 A00 0609 TBD 100.0K 10.0K(64.10025.6DL) 3.0V
X00 100.0K 10.0K 3.0V TBD 100.0K 13.7K(64.13725.6DL) 2.902V

1
VBAT 1 2 R2405 TBD 100.0K 17.8K(64.17825.6DL) 2.801V

1
X01 100.0K 20.0K 2.75V 10KR2F-2-GP TBD 100.0K 22.1K(64.22125.6DL) 2.702V

2
0R0603-PAD-2-GP-U R2404 MODEL TBD 100.0K 27.0K(64.27025.6DL) 2.598V
R2403 64K9R2F-1-GP X02 100.0K 33.0K 2.48V TBD 100.0K 32.4K(64.32425.6DL) 2.492V
2D2R3-1-U-GP TBD 100.0K 37.4K(64.37425.6DL) 2.402V

2
X03 100.0K 47.0K 2.24V TBD 100.0K 43.2K(64.43225.6DL) 2.304V

2
3D3V_AUX_KBC_VCC TBD 100.0K 49.9K(64.49925.6DL) 2.201V

1
PCB_VER_AD A00 100.0K 64.9K 2.0V MODEL_ID_DET TBD 100.0K 57.6K(64.57625.6DL) 2.093V
X02 0414 TBD 100.0K 64.9K(64.64925.6DL) 2.001V

1
Reserved 100.0K 76.8 1.87V TBD 100.0K 73.2K(64.73225.6DL) 1.905V

2
C2402 R2406 R2407 TBD 100.0K 82.5K(64.82525.6DL) 1.808V

2
1D05V_S0

SC2D2U10V3KX-1GP
100KR2F-L1-GP Reserved 100.0K 100.0K 1.65V C2403 100KR2F-L1-GP TBD 100.0K 93.1K(64.93125.6DL) 1.709V
R2401

C2405

SCD1U16V2KX-3GP C2406

SCD1U16V2KX-3GP C2407

SCD1U16V2KX-3GP C2408

SCD1U16V2KX-3GP C2409

SCD1U16V2KX-3GP C2410

C2411

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
DY TBD 100.0K 107K(64.10735.6DL) 1.594V

1
1

1
D 1 2 EC_VTT DY DY Reserved 100.0K 143.0K 1.358V TBD 100.0K 120K(64.12035.6DL) 1.499V D
DY

2
C2404 TBD 100.0K 137K(64.13735.6DL) 1.392V
DY
1

SCD1U16V2KX-3GP
0R0402-PAD-2-GP Reserved 100.0K 174.0K 1.204V TBD 100.0K 154K(64.15435.6DL) 1.299V

2
SC2D2U10V3KX-1GP
C2401 TBD 100.0K 200K(64.20035.6DL) 1.099V

SCD1U16V2KX-3GP
2 Reserved 100.0K 215.0K 1.048V EC_AGND TBD 100.0K 232K(64.23236.6DL) 0.994V
EC_AGND

Layout Note:
Need very close to EC
EC_AGND

ECSCI#_KBC 0R0402-PAD-1-GP 1 2 R2408 EC_SCI# [18,20]

KBC24
ECSMI#_KBC 0R0402-PAD-1-GP 1 2 R2409 EC_SMI# [19,20]
KROW[0..7] [62]
19 54 KROW0
VCC KBSIN0/GPIOA0/N2TCK KROW1
46 55
VCC KBSIN1/GPIOA1/N2TMS KROW2
76 56
3D3V_S0 VCC KBSIN2/GPIOA2 KROW3 3D3V_AUX_KBC
88 57
VCC KBSIN3/GPIOA3 KROW4
115 58
VCC KBSIN4/GPIOA4 KROW5
59
KBSIN5/GPIOA5

1
102 60 KROW6
AVCC KBSIN6/GPIOA6 KROW7 R2452
61
KBSIN7/GPIOA7
4 KCOL[0..16] [62] 10KR2J-3-GP
VDD
SCD1U16V2KX-3GP C2412
1

[44] AD_IA EC_VTT 12 53 KCOL0

2
C2413 VTT KBSOUT0/GPOB0/SOUT_CR/JENK# KCOL1 PANEL_SIZE
52
DY SC2D2U10V3KX-1GP C2414 KBSOUT1/GPIOB1/TCK
51 KCOL2 X02 0414
2

KBSOUT2/GPIOB2/TMS KCOL3
EC_AGND 1 2 SCD1U16V2KX-3GP 97 50
PCB_VER_AD GPIO90/AD0 KBSOUT3/GPIOB3/TDI KCOL4
98 49
GPIO91/AD1 KBSOUT4/GPOB4 KCOL5
[42] PSID_EC 99 48 R2453
GPIO92/AD2 KBSOUT5/GPIOB5/TDO KCOL6 3D3V_AUX_S5
[17,26,36] PCH_PWROK 100 47
GPIO93/AD3 KBSOUT6/GPIOB6/RDY# KCOL7
[17,38] PM_SLP_SUS# 108 43 1 2
GPIO05/AD4 KBSOUT7/GPIOB7 KCOL8 0R0402-PAD-2-GP
[44] BOOST_MON 96
GPIO04/AD5 KBSOUT8/GPIOC0
42 A00 0609
[44] P_SYS 95 41 KCOL9
MODEL_ID_DET GPIO03/EXT_PURST#/AD6 KBSOUT9/GPOC1/SDP_VIS# KCOL10 USB_DET# R2451 1
94 40 R2457 D2402 2 10KR2J-3-GP
GPIO07/AD7/VD_IN2 KBSOUT10/P80_CLK/GPIOC2 KCOL11 USB_DET#
ALL_SYS_PWRGD assert, KBSOUT11/P80_DAT/GPIOC3
39 1
38 KCOL12 HOME_BTN# 1 2
delay 10ms; PCH_PWROK assert. KBSOUT12/GPO64/TEST# KCOL13
HOME_BTN#_C [52]
[35,63] USB_PWR_EN# 101
GPIO94/DA0 KBSOUT13/GP(I)O63/TRIST#
37
KCOL14 0R0402-PAD-2-GP
DY 3 USBDET_CON# [34]
[35] USB_CHG_EN 105 36
GPIO95/DA1 KBSOUT14/GP(I)O62/XORTR# KCOL15 KBC_ON#_GATE_L
[35] USBCHARGER_CB0 106 35 2
GPIO96/DA2 KBSOUT15/GPIO61/XOR_OUT KCOL16 3D3V_AUX_KBC
[7,46] IMVP_PWRGD 107 34
GPIO97/DA3 GPIO60/KBSOUT16/DSR1# HOME_BTN# BAT54C-7-F-3-GP
C 33 C
GPIO57/KBSOUT17/DCD1# RN2401
BAT_SCL
75.00054.E7D BAT_SCL
[43,44] BAT_SCL 70 LPC_AD[3..0] [18,65] 1 4
BAT_SDA GPIO17/SCL1/N2TCK LPC_AD0 BAT_SDA
[43,44] BAT_SDA 69 126 2 3
GPIO22/SDA1/N2TMS LAD0/GPIOF1 LPC_AD1
X02 0414 [18,26] SML1_CLK 67
GPIO73/SCL2/N2TCK LAD1/GPIOF2
127 X01 0219
68 128 LPC_AD2 A00 0609 SRN4K7J-8-GP
[18,26] SML1_DATA GPIO74/SDA2/N2TMS LAD2/GPIOF3
[62] TP_ON# 119 1 LPC_AD3 ECRST# R2418 1 2 10KR2J-3-GP
R2417 GPIO23/SCL3/N2TCK LAD3/GPIOF4
120 2 CLK_PCI_KBC [18] HOME_BTN# R2454 1 2 10KR2J-3-GP
[19] RTCRST_ON GPIO31/SDA3/N2TMS LCLK/GPIOF5 R2416
[52] LCD_TST 1 2 PROCHOT_EC 24 3 LPC_FRAME# [18,65]
LCD_TST_EN LCD_TST_EN GPIO47/SCL4A/N2TCK LFRAME#/GPIOF6 PLT_RST#_EC
[52] LCD_TST_EN 28 7 1 2 PLT_RST# [17,63,65]
0R0402-PAD-2-GP GPIO53/SDA4A/N2TMS LRESET#/GPIOF7
[63] VOL_DOWN# 26
GPIO51/TA3/N2TCK 3D3V_AUX_KBC
[62] TP_LOCK# 1 R2437 2TP_LOCK#_C 123 0R0402-PAD-2-GP
GPIO67/SOUT1/N2TMS

2
X02 0414 0R0402-PAD-2-GP 90 EC_SPI_CS#_C 2 R2419 1 33R2J-2-GP
GPIOC6/F_CS0# SPI_CS0#_R [18,25]
EC_SPI_CLK_C 2 R2420 1 33R2J-2-GP C2415
72
GPIOC7/F_SCK
92
109
SPI_CLK_R [18,25] DY SC220P50V2KX-3GP AC_IN# R2413 1 2 100KR2J-1-GP
[62] TPCLK CAP_LED# [62] DY

1
GPIO37/PSCLK1 GPIO30/F_WP#/RTS1# BAT_IN# BAT_IN# R2414 1
[62] TPDATA 71 80 BAT_IN# [43,44] 2 10KR2J-3-GP
GPIO35/PSDAT1 GPIO41/F_WP#/PSL_GPIO41 EC_SPI_DI_C
[36] ALL_SYS_PWRGD 10 87 2 R2422 1 33R2J-2-GP SPI_SI_R [18,25]
KB_DISABLE GPIO26/PSCLK2 GPIOC5/F_SDIO/F_SDIO0 EC_SPI_DO_C
[66] KB_DISABLE 11 86 2 R2423 1 33R2J-2-GP SPI_SO_R [18,25]
GPIO27/PSDAT2 GPIOC4/F_SDI/F_SDIO1
[52] PANEL_SIZE 25 91 PM_SUSACK# [17]
GPIO50/PSCLK3 GPIO81/F_WP#/F_SDIO2 SUSCLK_KBC
[52] BLON_OUT 27 77 1 R2441 2 SUS_CLK [17]
GPIO52/PSDAT3 GPIO00/32KCLKIN/F_SDIO3
0R0402-PAD-2-GP
X02 0414 3D3V_AUX_S5 3D3V_S0
[26] FAN_TACH1 31
GPIO56/TA1 PSL_IN1#/GPI70
73 PSL_IN1#
Layout Note: Power Switch Logic(PSL)
[17,96] PM_PWRBTN# 117 93 PSL_IN2#
GPIO20/TA2/IOX_DIN_DIO PSL_IN2#/GPI06/EXT_PURST#

2
[63] VOL_UP# 63 74 PSL_OUT# Need very close to EC FAN_TACH1 R2415 1 2 10KR2J-3-GP
GPIO14/TB1 PSL_OUT#/GPIO71 R2425
[17,36,48,49,51] PM_SLP_S3# 64
GPIO01/TB2
X02 0414
330KR2J-L1-GP TOUCH_PANEL_INTR# R2443 1 DY 2 10KR2J-3-GP
29 ECSCI#_KBC Touch Panel PH internally.
ECSCI#/GPIO54 R2427
[27] KBC_BEEP 32 85 ECRST# VOL_UP# R2446 1 2 10KR2J-3-GP

1
GPIO15/A_PWM EXT_RST# PSL_IN2#
X01 0219 [54] HDMI_EC_DET# 118
GPIO21/B_PWM KBRST#/GPIO86
122 H_RCIN# [20] [63] KBC_PWRBTN# 1 2
62 VOL_DOWN# R2448 1 2 10KR2J-3-GP
[63] BATT_WHITE_LED# GPIO13/C_PWM X02 0414 0R0402-PAD-2-GP
[26] FAN_PWM1 65 75 3D3V_AUX_S5
GPIO32/D_PWM VSBY EC_VBKUP 3D3V_S5
[62] KB_BL_CTRL 22 114 1 R2428 2 RTC_AUX_S5 C2416 SC1U6D3V2KX-GP
R2430
GPIO45/E_PWM/DTR1#_BOUT1 VBKUP KBC_VCORF 0R0402-PAD-2-GP
[63] CHG_AMBER_LED# 16 44 1 2
GPIO40/F_PWM/1_WIRE/RI1# VCORF PECI PSL_IN1#
[17] KBC_DPWROK 81 13 1 2 H_PECI [4] [44] AC_IN# 1 2
VD1_EN# GPIO66/G_PWM/PSL_GPIO66 PECI R2429 LID_CLOSE# R2421 1
1 2 66 125 2100KR2J-1-GP
DY GPO33/H_PWM/VD1_EN# SERIRQ/GPIOF0 INT_SERIRQ [19,20]

C2422
SC100P50V2JN-3GP
R2449 1KR2J-1-GP 6 ECSMI#_KBC 43R2J-GP 0R0402-PAD-2-GP
GPIO24

1
[26] VD_IN1 104
GPIO80/VD_IN1 GPIO36/TB3/CTS1#
15 RSMRST#_KBC [17] USB_PWR_EN# R2412 1 DY 2100KR2J-1-GP
DY TP_ON# R2445 1
[26] VD_OUT1# 110 21 PM_SLP_S4# [17,49] 2100KR2J-1-GP

2
GPIO82/IOX_LDSH/VD_OUT1 GPIO44/SCL4B USB_DET#
[17] AC_PRESENT 112 20
GPIO84/IOX_SCLK/VD_OUT2 PSL_IN4#/GPI43 PCIE_WAKE# R2450 1
ALL_SYS_PWRGD de-assert, 17 LID_CLOSE# [63] 2100KR2J-1-GP
PSL_IN3#/GPI42
delay 100ms; SYS_PWROK assert. 23 ME_UNLOCK [19]
B GPIO46/SDA4B/CIRRXM TP_LOCK#_C R2455 1 B
2100KR2J-1-GP
[17,96] SYS_PWROK
[64] KB_CLOSE#_2
84
83
GPIO77/SPI_MISO
113 PCIE_WAKE# PCIE_WAKE# [17,20]
Layout Note:
GPIO76/SPI_MOSI GPIO87/CIRRXM/SIN_CR
LVDS backlight Control from PS8625 [63] WIFI_RF_EN 82
GPIO75/SPI_SCK GPIO34/SIN1/CIRRXL
14 S5_ENABLE [36] Need very close to EC
79 3D3V_AUX_S5 3D3V_AUX_S5
[17] PM_SUSWARN# GPIO02/SPI_CS#

2
X02 0414 GND
5
TP2409 1 EC_GPIO10 124 18 R2431 C2417 1 2 SCD1U16V2KX-3GP
R2426 1 TP_WAKE_KBC# GPIO10/LPCPD# GND
2 121 45 330KR2J-L1-GP
[20,62] INT_TP# 0R0402-PAD-2-GP E51_TxD GPIO85/GA20 GND
TP2408 1 111 78
L_BKLT_EN_EC GPIO83/SOUT_CR GND
9 89 D2401 R2432

S
GPIO65/SMI# GND
116
GND

2
[17] PM_CLKRUN#_EC 8 LID_CLOSE# K A TOUCH_PANEL_INTR# [52] PSL_OUT# 1 2 KBC_ON#_GATE_L 1 2 KBC_ON#_GATE G
GPIO11/CLKRUN# EC_AGND G
R2434
30 103
[27] AMP_MUTE# GPIO55/CLKOUT/IOX_DIN_DIO AGND
X02 0414 R2433 DY 0R2J-2-GP
1KR2J-1-GP
1

20KR2F-L-GP Q2402 D
RB751V-40H-GP
NPCE285PA0DX-GP R2435 DMP2130L-7-GP

1
X02 0414 0R0402-PAD-2-GP 83.R2004.G8F 84.02130.031
071.00285.000G 2ND = 84.03413.A31
[15] L_BKLT_EN 1 R2444 2 L_BKLT_EN_EC 2nd = 83.R2004.C8F
2

0R0402-PAD-2-GP 3D3V_AUX_KBC
eDP backlight Control from PCH Layout Note:
1

Connect GND and AGND planes via either 3D3V_AUX_KBC

R2447 0R resistor or connect directly.
100KR2J-1-GP

1
Q2403
EC_AGND R2436
2

G 10KR2J-3-GP

D S5_ENABLE
EC_GPIO47 High Active

2
3D3V_AUX_S5 S
R2424
R2438 0R2J-2-GP
2N7002K-2-GP
1

0R2J-2-GP 1 2 ECRST#
1 2 R2439 DY 84.2N702.J31
DY 10KR2J-3-GP 2ND = 84.2N702.031
X02 0414 C2418
2

SC1U6D3V2KX-GP
Q2401
E

PROCHOT_EC G [26,36] PURE_HW_SHUTDOWN# B

DY
R2440
2
A H_PROCHOT#_EC 1 Q2404 A
D 2 H_PROCHOT# [4,44,46]
C

MMBT3906-4-GP
1

S 0R0402-PAD-2-GP 84.T3906.A11
1

R2442 C2421 2nd = 84.03906.P11

100KR2J-1-GP SC47P50V2JN-3GP
DY 2N7002K-2-GP DY
2

84.2N702.J31
2

<Core Design>
2ND = 84.2N702.031

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

KBC Nuvoton NPCE885

Size Document Number Rev
Custom
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 24 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = Flash.ROM

SPI Flash ROM(8M) for PCH 3D3V_S5 3D3V_S5

1
D D
C2501 C2502
DY

2
SC10U6D3V5KX-1GP SCD1U16V2KX-3GP

2
R2501
4K7R2J-2-GP Single SPI shared flash connection (SPI Quad I/O mode)

1
X02 0422
SPI25 3D3V_S5

[18,24] SPI_CS0#_R 1 CS# VCC 8

[18,24] SPI_SO_R 2 SO/SIO1 SIO3 7 SPI_HOLD# [18]
[18] SPI_W P# 3 SIO2 SCLK 6 SPI_CLK_R [18,24]
4 GND SI/SIO0 5 SPI_SI_R [18,24]
1

1
MX25L6473EM21-10G-GP
EC2502 EC2501 DY DY EC2503
SC4D7P50V2CN-1GP DY 72.25647.00A SC4D7P50V2CN-1GP SC10P50V2JN-4GP
2

2
C C

X01 0219 Source QUAD/DUAL fast read DUAL fast read

72.25647.00A O O

072.25B64.0001 O O
Refer to "NCPE985x/ NPCE995x board design reference guide"

SSID = RBATT
+RTC_VCC 3D3V_AUX_S5 RTC_AUX_S5

B B

D2501
1

1
C2503
BAS40C-2-GP
2 SCD47U10V2KX-GP
75.00040.07D
2nd = 75.00040.C7D
3rd = 75.00040.A7D

Q2505
G
1

D RTC_DET# [20]
R2504
10MR2J-L-GP S
2

2N7002K-2-GP
A 84.2N702.J31 <Core Design> A
2ND = 84.2N702.031

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Flash/RTC
Size Document Number Rev
A3 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 25 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = Thermal
3D3V_S0 3D3V_S0

1
2
RN2602
SRN2K2J-1-GP
X02 0414 PWM FAN1
D
3D3V_S0 2N7002KDW -GP D

4
3
6 1 THM_SML1_DATA 5V_S0 Layout Note:
[18,24] SML1_DATA R2612
Signal Routing Guideline:
FAN_VCC_1
C2601
84.2N702.A3F 5 2 1 2 Trace width = 15mil
SC10U6D3V3MX-GP
2nd = 84.2N702.E3F
1

1
3rd = 75.00601.07C 4 3 0R0402-PAD-2-GP

K
C2604
SC4D7U6D3V3KX-GP

C2605
SCD1U10V2KX-5GP

C2603
SC2200P50V2KX-2GP
DY C2602 4th = 84.DMN66.03F

1
D2601
RB551V30-1-GP
SCD1U16V2KX-3GP Q2601
2

THM_SML1_CLK DY DY

2
A
[18,24] SML1_CLK
84.03904.P11
2nd = 84.03904.T11
NCT7718_DXP
THM261 FAN1
A00 0609 5
C

Q2603 1 8 THM_SML1_CLK FAN_VCC_1 1

CH3904PT-GP C2606 C2607 VDD SCL THM_SML1_DATA
B 2 D+ SDA 7
SC470P50V3JN-2GP SC2200P50V2KX-2GP 3 6 ALERT# 0R4P2R-PAD 2
DY
2

T_CRIT# D- ALERT# FAN_TACH1_C

4 5 2 3 3

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
[24] FAN_TACH1
E

T_CRIT# GND

1
NCT7718_DXN FAN_PW M1_C

C2608

C2609
[24] FAN_PW M1 1 4 4
DY DY RN2601
6
2.System Sensor, Put on palm rest NCT7718W -GP

RN
74.07718.0B9 AFTP2604 1 ACES-CON4-29-GP
C X02 0414 20.F1639.004 C
1

R2601
0R0402-PAD-2-GP
Q2602
Layout Note: [17,24,36] PCH_PW ROK G FAN_TACH1_C 1 AFTP2601
2

C2607 close THM2601

D FAN_PW M1_C 1 AFTP2602
PURE_HW _SHUTDOW N# [24,36]
THERM_SYS_SHDN# S FAN_VCC_1 1 AFTP2603

SCD1U16V2KX-3GP
1

C2610
Layout Note: 2N7002K-2-GP
DY
Both DXN and DXP routing 10 mil trace width and 10 mil spacing. 84.2N702.J31
KBC T8

2
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31 3D3V_S0
3D3V_S0 A00 0604
R2607 1 2 2KR2F-3-GP

R2603 1 2 7K5R2F-1-GP ALERT#

THERM_SYS_SHDN# 1 2 VD_OUT1# [24]
R2604 1 2 7K5R2F-1-GP T_CRIT# R2602 DY 0R2J-2-GP

Close to KBC
Close to Thermal sensor VD_IN1 for system thermal sensor
B B
3D3V_S0 3D3V_AUX_KBC

1
R2609 R2608
24K3R2F-1-GP
DY 10R2F-L-GP

2
VD_IN1 [24]

1
C2612

1
R2610 SCD1U16V2KX-3GP
NTC-100K-8-GP C2613

2
SC100P50V2JN-3GP

2
VD_IN1_C 1 R2611 2

0R0402-PAD-2-GP
A00 0609

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

THERMAL NCT7718W/Fan
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 26 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = AUDIO

D D

[29] LINE1_VREFO_R MIC2_VREFO [29]

[29] LINE1_VREFO_L AUD_AGND

Reserved for ALC3234
moat

SC10U6D3V3MX-GP
SC2D2U6D3V2MX-GP
[29] AUD_HP1_JACK_L
3D3V_S0 25mA +3V_AVDD
[29] AUD_HP1_JACK_R
EC2707 1 2 DY SC1KP50V2KX-1GP

1
X02 0414 EC2706 1 2 DY SC1KP50V2KX-1GP

1 C2705

C2702
R2701 1 2 0R0402-PAD-2-GP R2711 EC2705 1 2 DY SC1KP50V2KX-1GP
X02 0414 SC1U10V2KX-1GP 100KR2J-1-GP moat EC2704 1 2 DY SC1KP50V2KX-1GP
C2704 EC2703 1 2 DY SC1KP50V2KX-1GP
1

1 2

2
1
C2701
SC4D7U6D3V3KX-GP +5V_AVDD 5V_S0
2

Close pin36 AUD_AGND

2
X02 0414 R2703

1
+3V_AVDD
C2703 X02 0414

AUD_VREF
1 2

LDO1_CAP
1.5A +5V_AVDD

CPVEE
SC1U10V2KX-1GP

CBN
5V_S0 +5V_PVDD 0R0603-PAD-2-GP-U R2706
AUD_AGND

1
C2710 C2711 1 2
R2704
Layout Note:

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP
1 2 0R0603-PAD-2-GP-U

2
Place close to Pin 26

36

35

34

33

32

31

30

29

28

27

26

25
0R0805-PAD-2-GP-U C2706 C2707 C2708 C2709 HDA27
1

1
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

CPVEE

HPOUT-L/PORT-I-L

LINE1-VREFO-L

MIC2-VREFO

LDO1-CAP

AVDD1

AVSS1
CPVDD

CBN

HPOUT-R/PORT-I-R

LINE1-VREFO-R

VREF
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

AUD_AGND
2

CBP 37 24 AUD_AGND Layout Note:

CBP LINE2_L/PORT-E-L
Tied at point only under
AUD_AGND 38 23 Codec or near the Codec
AVSS2 LINE2_R/PORT-E-R

AUD_AGND C2712 1 2 SC10U6D3V3MX-GP LDO2_CAP 39 22

LDO2-CAP LINE1_L/PORT-C-L LINE1_L [29] 3D3V_S5

Layout Note: Layout Note: +3V_1D5V_AVDD 40

AVDD2 LINE1_R/PORT-C-R
21
LINE1_R [29] X02 0417
C C
Close pin41 Close pin46 41 20 V3D3_STB 1 R2712 2 0R2J-2-GP
+5V_PVDD PVDD1 NC#20
AUD_SPK_L+ 42 19 MIC_CAP C2713 1 2 SC10U6D3V3MX-GP AUD_AGND
[29] AUD_SPK_L+ SPK-OUT-L+ MIC-CAP
Layout Note: AUD_SPK_L-
moat Speaker trace width >40mil @ 2W4ohm speaker power [29] AUD_SPK_L-
43
SPK-OUT-L- MIC2_R/PORT-F-R/SLEEVE
18
SLEEVE [29] Layout Note:
AUD_SPK_R-
71.03234.003
X02 0414 [29] AUD_SPK_R-
44
SPK-OUT-R- MIC2_L/PORT-F-L/RING
17
RING2 [29]
Width>40mil, to improve Headpohone Crosstalk noise
3D3V_S0 1D5V_S0 +3V_1D5V_AVDD AUD_SPK_R+
Change it to sharp will be better.
45 16
[29] AUD_SPK_R+ SPK-OUT-R+ MONO-OUT Add 2 vias (>0.5A) when trace layer change.
R2705 2 0R0402-PAD-2-GP JDREF R2707 1 2 20KR2F-L-GP
1 +5V_PVDD 46
PVDD2 SPDIFO/FRONT_JD/JD3/GPIO3
15 DY AUD_AGND

GPIO0/DMIC-DATA
1

GPIO1/DMIC-CLK
R2710 1 2 0R2J-2-GP 1 R2708 2 EAPD# 47 14
DY C2715 [24] AMP_MUTE# 0R0402-PAD-2-GP PDB MIC2/LINE2_JD/JD2 +3V_AVDD

SDATA-OUT
SC4D7U6D3V3KX-GP COMBO-GPI 48 13 AUD_SENSE_A 1 2 AUD_SENSE 100KR2J-1-GP
2

SPDIF-OUT/GPIO2 HP/LINE1_JD/JD1 AUD_SENSE [29]

LDO3-CAP

SDATA-IN
X02 0414 R2709 R2722

DVDD-IO

PCBEEP
RESET#
Close pin40 200KR2F-L-GP AUD_SENSE_A
49
GND Layout Note: 1 2

DVDD

SYNC
DVSS

BCLK
AUD_AGND Place close to Pin 13
ALC3234-CG-GP moat

10

11

12
+3V_AVDD
AUD_PC_BEEP

LDO3_CAP
TP2702 1 +3V_AVDD
Azalia I/F EMI C2717

C2718

C2719
1

1
C2716
SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP

1
X01 0224 DMIC_DATA_R

2
SC10P50V2JN-4GP
EC2701

HDA_CODEC_SDOUT
HDA_CODEC_BITCLK DY

2
1

SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP
EC2708
1

EC2709
2
SC22P50V2JN-4GP

SC22P50V2JN-4GP

A00 0604
X01 0227
2

0R0402-PAD-2-GP 1 R2714 2 DMIC_DATA_R

[52] DMIC_DATA
B 0R2J-2-GP 1 R2716 2 DMIC_CLK_R B
[52] DMIC_CLK
0R0402-PAD-2-GP 1 R2719 2 CODEC_SDOUT_R
2

[19] HDA_CODEC_SDOUT
C2723 0R2J-2-GP 1 R2720 2 CODEC_BITCLK_R
SC22P50V2JN-4GP
DY [19] HDA_CODEC_BITCLK
1

0R0402-PAD-2-GP 1 R2718 2 HDA_CODEC_SDIN0

[19] HDA_SDIN0
Close pin3 HDA_CODEC_SYNC
[19] HDA_CODEC_SYNC
A00 0609
HDA_CODEC_RST#
[19,29] HDA_CODEC_RST#
D2701
0R4P2R-PAD HDA_SPKR_R 2
[20] HDA_SPKR 2 3 C2720
[24] KBC_BEEP 1 4 3 AUD_PC_BEEP_C 1 2AUD_PC_BEEP
RN2701 KBC_BEEP_R 1 SCD1U16V2KX-3GP

RN

1
BAT54C-7-F-3-GP R2717
1KR2J-1-GP

75.00054.E7D

2
A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Audio Codec ALC3223

Size Document Number Rev
A2
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 27 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = AUDIO

D D

(Blanking)
C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

AUDIO AMP
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 28 of 107
5 4 3 2 1
 5 4 3 2 1

SSID = AUDIO

Layout Note: X02 0414

Speaker
Speaker trace width >40mil @ 2W4ohm speaker power
SPK1
5
0R0603-PAD-2-GP-U 1 2 R2904 AUD_SPK_R+_C 1
[27] AUD_SPK_R+
D D
0R0603-PAD-2-GP-U 1 2 R2903 AUD_SPK_R-_C 2
[27] AUD_SPK_R- 0R0603-PAD-2-GP-U
[27] AUD_SPK_L+ 1 2 R2902 AUD_SPK_L+_C 3
0R0603-PAD-2-GP-U 1 2 R2901 AUD_SPK_L-_C 4 CONN Pin Net name
[27] AUD_SPK_L-
6
Pin1 SPK_R+
X01 0224 ACES-CON4-29-GP
20.F1639.004 Pin2 SPK_R-
Pin3 SPK_L+

1
Pin4 SPK_L_

SC1KP50V2KX-1GP
EC2901

SC1KP50V2KX-1GP
EC2902

SC1KP50V2KX-1GP
EC2903

SC1KP50V2KX-1GP
EC2904
2

2
AUD_SPK_L-_C 1 AFTP2901
AUD_SPK_L+_C 1 AFTP2902
AUD_SPK_R-_C 1 AFTP2903
AUD_SPK_R+_C 1 AFTP2904

C C
Combo Jack
JACK_POW ER
SRN2K2J-1-GP X02 0414
RN2901
[27] MIC2_VREFO 1 4

2
2 3

HPMIC1 Non-Delay R2923 AUD_PORTA_L_R_B 1 AFTP2906

[27] RING2 0R0603-PAD-2-GP-U 1 2 R2906 RING2_R 3 0R2J-2-GP AUD_PORTA_R_R_B 1 AFTP2907
R2908 1 2 10R2F-L-GP AUD_HP1_JACK_L1 0R0603-PAD-2-GP-U 1 2 R2907 AUD_PORTA_L_R_B 1 AUD_AGND 1 AFTP2908

1
[27] AUD_HP1_JACK_L C2907 1
[27] LINE1_L 2LINE1-L_C R2922 1 2 1KR2J-1-GP JACK_PLUG 1 AFTP2909
SC4D7U6D3V3KX-GP R2912 1 2 4K7R2J-2-GP 3D3V_S0 R2916 1 Delay 210KR2J-3-GP JACK_POW ER 5 JACK_POW ER 1 AFTP2910
[27] LINE1_VREFO_L JACK_PLUG 6
R2910 1 2 10R2F-L-GP AUD_HP1_JACK_R1 0R0603-PAD-2-GP-U 1 2 R2909 AUD_PORTA_R_R_B 2
[27] AUD_HP1_JACK_R C2908 1
[27] LINE1_R 2LINE1-L_R R2921 1 2 1KR2J-1-GP 0R0603-PAD-2-GP-U 1 2 R2911 SLEEVE_R 4 AUD_AGND
SC4D7U6D3V3KX-GP R2913 1 2 4K7R2J-2-GP MS
[27] LINE1_VREFO_R
SC100P50V2JN-3GP
EC2908

SC100P50V2JN-3GP
EC2907

SC100P50V2JN-3GP
EC2906

SC100P50V2JN-3GP
EC2905
Audio(IP/NK comb)
1

1
10KR2J-3-GP
R2920

10KR2J-3-GP
R2919

[27] SLEEVE AUDIO-JK443-GP

1

1
022.10002.0141
DY DY DY DY DY DY
2

2
Delay circuit
2

AUD_AGND

B JACK_PLUG B

AUD_AGND AUD_AGND

1
C2902

2
R2905 Delay

SC10U6D3V3MX-L-GP
100KR2J-1-GP Delay AUD_AGND

G
1

S
Q2901

2
2N7002K-2-GP
84.2N702.J31
AUD_AGND AUD_AGND 2nd = 84.2N702.W31
Delay
3rd = 84.07002.I31

D
AUD_PORTA_R_R_B
AUD_PORTA_L_R_B
RING2_R 5V_PW R_2 +3V_AVDD
JACK_PLUG
SLEEVE_R 1 DY 2 AUD_SENSE [27]
1

JACK_POW ER
R2915 R2918 R2914
DY 470KR2J-2-GP 100KR2J-1-GP 0R3J-6-GP
DY
2

2
AZ2025-01H-R7G-GP

AZ2025-01H-R7G-GP

AZ2025-01H-R7G-GP

AZ2025-01H-R7G-GP

AZ2025-01H-R7G-GP

AZ2025-01H-R7G-GP

R2917
2

2
ED2901

ED2902

ED2903

ED2904

ED2905

ED2906

A <Core Design> A
2 1
U2901 DY
0R3J-0-U-GP HDA_CODEC_RST# [19,27]
DY DY DY DY DY DY S D
moat AUD_AGND 4 3 SLEEVE [27] Wistron Corporation
SLEEVE_CTRL
G
5 DY 2
G MUTE_CTRL 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
D S
1

6 1
1

4th = 84.DMN66.03F C2901 Title

3rd = 75.00601.07C DY SC1U6D3V2KX-GP
Speaker/HPMIC
2

2N7002KDW -GP
2nd = 84.2N702.E3F
84.2N702.A3F Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 29 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LAN RTL8111/RTL8106
Size Document Number Rev
A2
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 30 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = LOM

D D

(Blanking)
C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

XFOM&RJ45
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 31 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
(Reserved)Card Reader
Document Number Rev
A4
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 32 of 104
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)
C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 33 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = USB X02 0416

EU3401
USB3.0 Port1
USB30_RXDN1_C 1 9 USB30_RXDN1_C
USB30_RXDP1_C 2 8 USB30_RXDP1_C
3
USB30_TXDN1_C 4 7 USB30_TXDN1_C
USB30_TXDP1_C USB30_TXDP1_C
1 2 USB30_TXDN1_R
A00 0604 USB30_TXDN1_C
A00 0604 5 6
[16] USB3_PTX_CRX_N1 USB30_RXDN1_C
D C3406 [16] USB3_PRX_CTX_N1 ESD3V3U4ULC-GP D
SCD1U10V2KX-5GP 83.3V3U4.0A0 USB30_VCCA
FILTER-4P-171-GP FILTER-4P-171-GP
2 3 2 3 EU3402

1 4 1 4 USB20_DN1_C 1 6 USB20_DP1_C
I/O1 I/O4
DY
2 GND VDD 5
TR3404 TR3405
3 I/O2 I/O3 4

1 2 USB30_TXDP1_R USB30_TXDP1_C [16] USB3_PRX_CTX_P1 USB30_RXDP1_C

[16] USB3_PTX_CRX_P1 AZC099-04S-1-GP
C3405 75.09904.07C
SCD1U10V2KX-5GP
2nd = 75.02304.07C

USB30_VCCA
X02 0415 USB20_DP1_C
[35] USB_PP1_R
USB1
USB 3.0 Connector
1 VBUS CHASSIS#11 11
12
Pin definition
FILTER-4P-171-GP USB20_DN1_C CHASSIS#12
2 D- CHASSIS#13 13
2 3 USB20_DP1_C 3 14 1 POWER
D+ CHASSIS#14
C 1 4 2 USB 2.0 D- C
USB30_RXDN1_C 5 D1
SSRX- DET# USBDET_CON# [24]
USB30_RXDP1_C 6 3 USB 2.0 D+
TR3401 SSRX+
GND 4
USB30_TXDN1_C 8 4 GND
69.10118.001 USB30_TXDP1_C 9
SSTX-
7
SSTX+ GND_DRAIN
USB3.0 5 StdA_SSRX- SuperSpeed RX
[35] USB_PN1_R USB20_DN1_C
SKT-USB14-5-GP-U 6 StdA_SSRX+
022.10005.0441 7 GND
8 StdA_SSTX- SuperSpeed TX
9 StdA_SSTX+

USB3.0 Port2
R3413 R3414
1 2 USB30_TXDN0_R 1 2 USB30_TXDN0_C 1 2 USB30_RXDN0_C
X02 0416
[16] USB3_PTX_CRX_N0 [16] USB3_PRX_CTX_N0
C3407 0R0402-PAD-2-GP 0R0402-PAD-2-GP
SCD1U10V2KX-5GP EU3403

USB30_RXDN0_C 1 9 USB30_RXDN0_C
USB30_RXDP0_C 2 8 USB30_RXDP0_C
B B
3
USB30_TXDN0_C 4 7 USB30_TXDN0_C
USB30_TXDP0_C USB30_TXDP0_C
A00 0604 A00 0604 5 6

ESD3V3U4ULC-GP
83.3V3U4.0A0 USB30_VCCB

EU3404
R3416 R3415
1 2 USB30_TXDP0_R 1 2 USB30_TXDP0_C [16] USB3_PRX_CTX_P0 1 2 USB30_RXDP0_C USB20_DN0_C 1 6 USB20_DP0_C
[16] USB3_PTX_CRX_P0 I/O1 I/O4
C3408 0R0402-PAD-2-GP 0R0402-PAD-2-GP 2 DY 5
SCD1U10V2KX-5GP GND VDD
3 I/O2 I/O3 4

X02 0415 USB30_VCCB

[16] USB_PP0 USB20_DP0_C USB2 AZC099-04S-1-GP

USB30_TXDP0_C
10 CHASSIS CHASSIS
13 75.09904.07C
9
1 2nd = 75.02304.07C
FILTER-4P-171-GP USB30_TXDN0_C 8
2 3 USB20_DN0_C 2
7
1 4 USB20_DP0_C 3
A USB30_RXDP0_C 6 <Core Design> A
4
TR3402 USB30_RXDN0_C 5
69.10118.001 11
CHASSIS CHASSIS
12
Wistron Corporation
SKT-USB13-90-GP-U 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
USB20_DN0_C Taipei Hsien 221, Taiwan, R.O.C.
[16] USB_PN0
Title

USB 3.0
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 34 of 104
5 4 3 2 1
 5 4 3 2 1

USB Charger Port1

USB30_VCCA

5V_S5 USB_OC#0_1 [16,18]

C3505 C3503

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP
1

1
C3504 C3404

SCD1U10V2KX-5GP
SC100U6D3V6MX-GP If MLCC is used as Main Source.

2
D D

2
78.10710.52L Inform Layout team to remark Pin 1 as positive.

13

12
In case MLCC shortage and other type of Cap With Polarity Is Used.

9
U3503
X02 0414

NC#9
FAULT#
IN

OUT
[24] USB_CHG_EN 5 EN DP_OUT 3 USB_PP1 [16]
DM_OUT 2 USB_PN1 [16]
5V_S5 R3505 1 2 0R0402-PAD-2-GP ILIM_SEL 4
R3506 1 ILIM_SEL
DY 2 20KR2F-L-GP ILIM_LO 15 10 USB_PP1_R [34]
R3508 1 2 22K1R2F-L-GP ILIM_HI 16 ILIM_LO
ILIM_HI
DP_IN
DM_IN 11 USB_PN1_R [34]
Device Control Pins

CTL1
CTL2
CTL3

GND
GND
CTL1
CTL2 CTL3 ILIM_SEL
TPS2544RTER-GP (EC control)

6
7
8

14
17
X02 0414 74.02544.073

[24] USBCHARGER_CB0 R3501 1 2 0R0402-PAD-2-GP CTL1 CDP 1 1 1 1

5V_S5 R3507 1 2 0R0402-PAD-2-GP CTL2
R3504 1 2 0R0402-PAD-2-GP CTL3
DCP Auto
0 1 1 X

C C
Layout Note: Close CON1

5V_S5 USB30_VCCB
U3502

5 1 2A
IN OUT
2

100KR2J-1-GP
GND USB3.0 Port2
1

1
R3503

C3522
SCD1U16V2KX-3GP

C3521
SC1U10V2KX-1GP
[24,63] USB_PW R_EN# 4 EN# OC# 3 USB_OC#0_1 [16,18]

1
C3502 Active Low C3409
DY SC100U6D3V6MX-GP
2

SY6288DAAC-GP
SCD1U16V2KX-3GP

2
074.06288.009B 78.10710.52L

2
B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB Power SW
Size Document Number Rev
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 35 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = Reset.Suspend
Power Good
3D3V_S0

ROSA Run Power

1
D X02 0414 D
R3601
1KR2J-1-GP 5V_S0
[49] 1D35V_VTT_PW RGD R3610 1 2 0R0402-PAD-2-GP 5V_S0 Comsumption

2
3D3V_AUX_S5 Peak current 5A
[7,48] 1D05V_VTT_PW RGD R3611 1 2 0R0402-PAD-2-GP ALL_SYS_PW RGD [24]
1
DY 2 PS_S3CNTRL 3D3V_S0
R3607 3D3V_S0 Comsumption
100KR2J-1-GP
Peak current 2.5A
D G S
X01 0219
6

Q3601
2N7002KDW -GP DY
84.2N702.A3F X02 0414 5V_S5 5V_S5 U3601 5V_S0
1

2nd = 84.2N702.E3F S G D
3rd = 75.00601.07C GND 15
R3609 1 VIN1#1 VOUT1#14 14
4th = 84.DMN66.03F 2 13
3V5V_S0_ON VIN1#2 VOUT1#13 3V5V_CT1
[17,24,48,49,51] PM_SLP_S3# 1 2 3 ON1 CT1 12

C3601
SC10U6D3V5KX-1GP
4 11 3D3V_S0
VBIAS GND

1
[17,24,26] PCH_PW ROK 5 10 3V5V_CT2
0R0402-PAD-2-GP ON2 CT2
3D3V_S5 6 VIN2#6 VOUT2#9 9
7 8

2
C VIN2#7 VOUT2#8 C

C3603
SC470P50V2KX-3GP

C3602
SC470P50V2KX-3GP

C3605
SC10U6D3V5KX-1GP
1

1
TPS22966DPUR-GP
74.22966.093

2
B B

D3602
BAS16-6-GP
2ND = 83.00016.F11
2
3rd = 83.00016.P11
3 PURE_HW _SHUTDOW N# [24,26]
4th = 83.00016.G11
[45] 3V_5V_EN 1
83.00016.K11
1

1 2 S5_ENABLE [24]
R3602
DY R3603
200KR2F-L-GP

1KR2J-1-GP
A <Core Design> A
2

Check R3603 is 1k or 2k.

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Plane Enable

Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 36 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = Reset.Suspend

Layout Note:
Place Close SO-DIMM1
D D
DDR_VREF_S3
1D35V_S3

1
R3704
0R2J-2-GP R3706
1K8R2F-GP

SA_DIMM_VREFDQ DY

2
2R2F-GP
1 R3708 2
SODIMM1 M_VREF_CA_DIMMA +V_SM_VREF_CNT [5]

1
C3701
SCD022U16V2KX-3GP

2
1
R3703 +V_VREF_PATH3

1
1K8R2F-GP
R3707
24D9R2F-L-GP

2
C C

Layout Note:
Place Close SO-DIMM1

DDR_VREF_S3 1D35V_S3

1
R3710
0R2J-2-GP R3701
1K8R2F-GP
DY
2R2F-GP
2

R3702
[5] DDR_W R_VREF01 1 2 M_VREF_DQ_DIMMA
1

C3702 R3709
SCD022U16V2KX-3GP 1K8R2F-GP
2

+V_VREF_PATH1
2
1

B R3711 B
24D9R2F-L-GP
2

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

S3 Reduction Circuit
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 37 of 104
5 4 3 2 1
 5 4 3 2 1

3D3V_S5 3D3V_S5_PCH
R3801
1 2
D
NON DS3 D
0R5J-5-GP

3D3V_S5 Obs reason:

For new project,
pls help to use cost down version
SY6288C10CAC for instead.
C3801

1
3D3V_S5_PCH

SC1U10V2KX-1GP
2
U3801
DS3
1
DS3 8
GND OUT#8
2 IN#2 OUT#7 7
C 3 IN#3 OUT#6 6 C
[17,24] PM_SLP_SUS# 1 2 DS3_PWRCTL 4 EN/EN# OCB 5
R3802 C3802

1
0R0402-PAD-2-GP

SC1U10V2KX-1GP
SY6288CCAC-GP
74.06288.079 (OBS)

2
DS3
RdsON: 100m ohm

DS3

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DSW
Size Document Number Rev
A4 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 38 of 104
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)
C C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved) 1D05_M
Size Document Number Rev
A4 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 39 of 104
5 4 3 2 1
(Blanking)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 40 of 104
 5 4 3 2 1

D D

C
(Blanking) C

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 41 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Support
5V_S5
X01 0224

2
84.03904.P11
2nd = 84.03904.T11

1
PR4202 3D3V_S5
15KR2F-GP PR4203

E
10KR2J-3-GP

1
PQ3802_1 B 3D3V_S5

1
D
CH3904PT-GP D

2
2
PQ4202 PD4203

1
PR4209 PSID_DISABLE#_R_C DA3X101F0L-1-GP
100KR2J-1-GP PR4204
75.03101.07D 2K2R2J-2-GP
A00 0609

G
1

3
PQ4201

2
FDV301N-NL-GP
PR4217
PR4205
PS_ID_R 1 2 PS_ID_R2 D S PS_ID 1 2

D
PSID_EC [24]
0R0603-PAD-2-GP-U 84.00301.A31 33R2J-2-GP
Layout Note: 2nd = 84.3K329.031
PSID Layout width > 25mil

1
X01 0219
PD4204 PR4206
DY PESD24VS2UT-GP 1 2
DY
33R2J-2-GP

3
DCIN1
9 60ohm@100MHz
1
DCR=0.02 ohm
Max current = 6000mA
2 1 AFTP4205
3 1 AFTP4204 +DC_IN AD+
C 4 C
5 PU4201
+DC_IN_C 1 EL4201 2 S D

PC4206
6 1 8

SC10U25V5KX-GP
0R0805-PAD-2-GP-U S D

PC4205

PC4203

PC4204
7 2 7

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP
1

1
PC4201
SC1U25V3KX-1-GP
S D

240KR3-GP
8 3 6

K
1

1
1 EL4203 2 G D

PR4207
4 5
10 EC4201 EC4202 0R0805-PAD-2-GP-U PD4201 PC4202

2
SC10U25V3MX-GP

SC1KP50V2KX-1GP

1SMB22AT3G-GP-U1 SCD1U25V3KX-GP SI7121DN-T1-GE3-GP

2

2
1 EL4204 2 83.22R03.03G

2
ACES-CON8-13-GP-U1 0R0805-PAD-2-GP-U
DY DY

A
20.F1295.008
A00 0609

1
Id=-9.6A
PR4208
47KR3J-L-GP Qg=-25nC
Rdson=18~30mohm
X01 0219

2
AFTP4201 1 +DC_IN_C
AFTP4202 1 +DC_IN_C
AFTP4203 1 PS_ID_R

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number

DCIN Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 42 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Support
BT+
X01 0303 X01 0224
PBAT_PRES1# 1 AFTP4301
D PBAT_SMBDAT1 1 AFTP4302 D

K
PBAT_SMBCLK1 1 AFTP4303

1
EC4304 EC4303 SYS_PRES1# AFTP4304
1
SCD1U50V3KX-GP 2 SCD1U25V2KX-GP
DY PD4302
SMF18AT1G-GP Batt Connecter BT+
BT+
1
1
AFTP4305
AFTP4306

2
BT+ 1 AFTP4307

A
BATT1
9
1
RN4301
4 5 2 X02 0414
3 6 PBAT_SMBCLK1 3
[24,44] BAT_SCL
2 7 PBAT_SMBDAT1 4 R4301
[24,44] BAT_SDA
1 8 PBAT_PRES1# 5 SYS_PRES1# 1 2
[24,44] BAT_IN#
SYS_PRES1# 6 0R0402-PAD-2-GP
SRN100J-4-GP 7
8
10

C
X01 0226 C
ALP-CON8-17-GP-U1
2
EC4301 EC4302 EC4305
1

1
SC10P50V2JN-4GP

SC10P50V2JN-4GP

SC10P50V2JN-4GP
BATSW1
DY DY DY 1 AFTP4308 5 4
1

1 AFTP4309 1 SYS_PRES1#
2

1 AFTP4310
NP1
DY 2
NP2
3
7 6
Placement: Close to Batt Connector
SW-SLIDE77-GP
62.40068.021
BAT_SCL
BAT_IN#

BAT_SDA

B B

DY DY DY
3

D4302 D4303 D4301

DA3X101F0L-1-GP DA3X101F0L-1-GP DA3X101F0L-1-GP
1

<Core Design>
3D3V_AUX_KBC

75.03101.07D 75.03101.07D 75.03101.07D Wistron Corporation

A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
2nd = 83.00099.K11 2nd = 83.00099.K11 2nd = 83.00099.K11 Taipei Hsien 221, Taiwan, R.O.C.
3rd = 83.00099.M11 3rd = 83.00099.M11 3rd = 83.00099.M11 Title

BATT CONN
Size Document Number Rev
A4
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 43 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = Charger
AD+ +SDC_IN CHARGER_SRC
PU4405

8 D S 1 PR4426 1 2
7 D S 2 D01R3721F-GP-U
6 D S 3
5 D G 4

1
PG4406 PG4402
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
PR4435
100KR2J-1-GP
SI7121DN-T1-GE3-GP

2
2
84.07121.037

1
PR4418 2nd = 84.06675.030 AD+_G_2
3K3R6J-GP PR4421 2 DY 1 0R2J-2-GP

2
PC4428

2
DC_IN_D
PR4423 2 1
10KR2F-2-GP
SCD1U25V2KX-GP
PQ4407

1
D D

AD+_G_1

SCD1U25V2KX-GP
3 4

SCD1U25V2KX-GP
PC4418

2
ACAV_IN

PC4416
2 5
DY

1
1 6

1
BT+
2N7002KDW-GP
PD4405 A K 84.2N702.A3F BQ24770_AGND
CH035H-40PT0-GP 83.1R504.B8F 2nd = 84.DM601.03F
3rd = 84.2N702.E3F
AD+ BQ24770_AGND
4th = 84.2N702.F3F
PD4406 A K PWR_CHG_1 1 2 PWR_CHG_VCC
PC4410
CH035H-40PT0-GP 83.1R504.B8F PR4403 10R5J-GP
SC1U25V3KX-1-GP

1
1
PC4433 CHARGER_SRC
AD+ SCD1U25V2KX-GP PC4421

PU4406:

2
VacDET=2.4V PC4432 PWR_CHG_BTST1 1 2

PWR_CHG_ACP
2

PWR_CHG_ACN
Acok setting=2.4*((PR4444+PR4411)/PR4411) X01 0225

SC1U25V3KX-1-GP
SCD047U25V3KX-3-GP

2
Setting=17.055v
main source: 84.03660.037

PC4425
SC10U25V5KX-GP

PC4411
SC10U25V5KX-GP

PC4427
SC10U25V5KX-GP

PC4407
SC10U25V5KX-GP

PC4434
SC10U25V5KX-GP
BQ24770_AGND DY

1
PC4413
SCD1U25V2KX-GP
BQ24770_AGND PR4425

2
PR4444 0R3J-0-U-GP

K
287KR2F-GP +SDC_IN PU4406
KBC FOR DT MODE

2
PD4401 FDMS3600-02-RJK0215-COLAY-GP

PWR_CHG_BTST 1
BQ24770_AGND CH035H-40PT0-GP 2
CHECK EE PULL HIGH

1
83.1R504.B8F 3

1
PR4439 PU4401 1 4

A
4K02R2F-GP 10 DCBATOUT

ACP

ACN
3D3V_AUX_KBC 28 9
PWR_CHG_REGN

SCD01U50V2KX-1GP
VCC
7

2
1

1
DY PR4411 8 6

PC4403
SC10U25V5KX-GP

PC4430
SC10U25V5KX-GP

PC4408
SC10U25V5KX-GP

PC4409
SC10U25V5KX-GP
47KR2F-GP PWR_CHG_CMSRC 3 25 5
CMSRC BTST

1
2
1

PC4402
4
PR4432 PR4414 ACDRV PWR_CHG_REGN +VCHGR
24 1 2
ZZ.00215.037

2
3K3R2J-3-GP 3K3R2J-3-GP REGN PD4402 V8P10-5300M3-86A-GP
DY DY PWR_CHG_ACDET PC4422 PL4401
6 1
ACDET
ACAV_IN BQ24770_AGND SC2D2U25V3KX-GP COIL-2D2UH-11-GP
2

BQ24770_AGNDH=ACIN 26 PWR_CHG_HIDRV 1 2 1 2 3
ACAV_IN HIDRV
2 1 PR4430 PWR_CHG_ACOK 5 68.2R210.20C PR4443
L=UNAC ACOK

PR4427

2D2R5F-2-GP
0R0402-PAD-2-GP D01R2512F-3-GP 2

1
BT+

SC10U25V5KX-GP
PC4442

PC4441
SC10U25V5KX-GP

PC4439
SC10U25V5KX-GP

PC4440
SC10U25V5KX-GP

PC4420

PC4415
SC10U25V5KX-GP
27 PWR_CHG_PHASE

SC1U25V3KX-1-GP
PHASE

1
PG4401 2 1 GAP-CLOSE-PWR-3-GP PWR_SCL 12
[24,43] BAT_SCL SCL
DY DY 83.8R010.A87

2
GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
23 PWR_CHG_LODRV

2
LODRV

PG4407

PG4403
PG4408 2 1 GAP-CLOSE-PWR-3-GP PWR_SDA 11 PU4403
[24,43] BAT_SDA

2
SDA S D 8
1
22 DCBATOUT_SNUB 2 S D 7

1
0R0402-PAD-2-GP GND S D 6
2 1 PR4466 BQ24770_IADP 7 3 PC4424

SC330P50V3KX-GP
[24] AD_IA IADP BATDRV# G D 5
Discharge Current Monitor 4

SCD01U25V2KX-3GP
0R0402-PAD-2-GP 1 PR4434 BQ24770_IDCHG

PC4406
2 8
[24] BOOST_MON IBAT
20 PWR_CHG_SRP PR4438 1 2 0R0402-PAD-2-GP PWR_CHG_SRP_R DY
DY
0R0402-PAD-2-GP SRP
2 1 PR4467 BQ24770_PMON 9

2
[24] P_SYS PMON SI7121DN-T1-GE3-GP
SC100P50V2JN-3GP
PC4435

SC100P50V2JN-3GP
PC4436

SC100P50V2JN-3GP
PC4437

System Power Monitor

19 PWR_CHG_SRN PR4417 1 2 0R0402-PAD-2-GP PC4429
SRN
These pins can be floating PR4469 1 2 PROCHOT#_BQ24770 10 1 2
PROCHOT# 84.07121.037
1

C 0R0402-PAD-2-GP PWR_CHG_BAT C
if they are not in use. 17 2 1 BT+
BAT

1
PR4413 PC4401 SCD1U25V2KX-GP PC4412 2nd = 84.06675.030
IADP=40*V(acp_acn) or 80*V(acp_acn) 0R2J-2-GP PR4408 SCD1U25V2KX-GP SCD1U25V2KX-GP
15
2

IDCHG=8*V(srn-srp) or 16*V(srn-srp) PWR_CHG_CMPIN 2CHG_CMPIN_1

BATPRES# BAT_IN# [24,43] 20R3F-L-GP
1 DY 13

2
CMPIN
18
BATDRV#

1
PWR_CHG_CMPOUT1 2CHG_CMPOUT_1
DY 0R2J-2-GP 14 PWR_CHG_BATDRV 1 2 BATDRV# PC4438 PWR_CHG_SRN_R
PR4415 CMPOUT
ILIM
21 SC1U25V3KX-1-GP BQ24770_AGND BQ24770_AGND
[4,24,46] H_PROCHOT# 16 PR4409

GND

2
3D3V_AUX_S5 PWR_CHG_REGN CELL 1KR2F-3-GP

3D3V_S5
PWR_CHG_REGN

29
BQ24770RUYR-1-GP
074.24770.0003
1
1

150KR2F-L-GP
PR4468

PR4449
PR4424
100KR2F-L1-GP

100KR2J-1-GP
X02 0421

1
DY DY BQ24770_AGND
PR4470
A00 0604 100KR2J-1-GP
2
2

2
CHARGER_CELL_PIN PR4406 1 2 0R0402-PAD-2-GP
1

1
PR4445
33KR2F-GP

DY BQ24770_AGND DY PR4471
100KR2J-1-GP
2

2
AD+ PWR_CHG_CMPIN:
V-=3.3*(PR4402/(PR4428+PR4402))=1.1099V
100KR2J-1-GP
PR4416

3D3V_AUX_S5

150KR2F-L-GP
1

PR4428
A00 0604

1
1
PR4422 DY
2

3D3V_S5
DY 1M8R2J-L-GP
100KR2F-L1-GP

2 PWR_CHG_CMPIN
2
1
1

1 DY 2
PR4431

PR4433 DY PR4402 PWR_CHG_CMPOUT

1MR2J-1-GP
DY 75KR2F-GP 84.2N702.A3F
E PQ4408_E

5V_S5 A00 0604 2nd = 84.DM601.03F

H_PROCHOT# [4,24,46]
5V_S5 3rd = 84.2N702.E3F
2
2

PC4419
SCD01U50V2KX-1GP
Follow custormer circuits BQ24770_IADP
2

1
4th = 84.2N702.F3F DY
PD4403 PR4455 BAT_IN# [24,43]

PC4426
84.2N702.A3F DY DY 1 2

SC100P50V2JN-3GP

1
1N4148WS-7-F-GP 0R0402-PAD-2-GP 2nd = 84.DM601.03F PQ4413 PR4457 H_PROCHOT# [4,24,46]

2
1

APD4403_A B DY PR4437 2N7002KDW-GP 0R2J-2-GP

CHARGER_CELL_PIN
K 3rd = 84.2N702.E3F
CHECK PM BATTERY TYPE

5
6
7
8
4th = 84.2N702.F3F DY PC4414 100KR2J-1-GP PQ4413_3
PQ4405
CHECK EE PWR_CHG_REGN
1

PD4403_K PQ4408 SCD47U6D3V2KX-1-GP 4 3

2IN-
2OUT
VCC
2IN+
CHECK CELL for DT mode PR4436
C

LM393PWR-GP
MMBT3906-4-GP PQ4405_3

PU4402
PR4462 3 4

2
2

84.T3906.A11 PWR_CHG_CMPOUT 1 DY 2 PQ4413_5 5 2

PR4458 2nd = 84.03906.P11 PQ4408_C 2 1 PQ4405_2 2 5 PQ4405_5 DY

1
B B

SCD01U50V2KX-1GP
PC4405
0R0402-PAD-2-GP PQ4406_G 220KR2F-GP

1OUT
6 1

GND
1IN+
1

1
1IN-
PC4404
SC1U25V3KX-1-GP

0R0402-PAD-2-GP 1 6 PR4410
1

3D3V_AUX_S5 100KR2J-1-GP
DY
1

2N7002KDW-GP PWR_CHG_REGN PWR_CHG_REGN

PQ4406
2

4
3
2
1

2
PR4451 PR4463 5V_S5 5V_S5
DY PR4429

2
1
100KR2F-L1-GP

100KR2F-L1-GP

100KR2F-L1-GP

100KR2F-L1-GP
680KR2F-GP 100KR2J-1-GP PWR_CHG_ACOK

DIS_DTM_CELL
0R2J-2-GP DY DY G

1
DCBATOUT PR4412
PQ4405_6

DY
2

1
1 2 PQ4406_D D PR4464 100KR2J-1-GP
2

[4,24,46] H_PROCHOT#

PR4461

PR4441

PR4453

PR4460
PR4404
PWR_CHG_ACOK

DY 0R2J-2-GP
2

PR4456 S DY DY DY DY 120KR2J-GP

2
PR4405 0R2J-2-GP

2
[24] AC_IN#
100KR2F-L1-GP

2
2N7002K-2-GP
1

PU4402_1IN+ PQ4401_D
CHECK EE PR4450 84.2N702.J31
1

1
10KR2F-2-GP DCBATOUT BT+
2ND = 84.2N702.031
follow custormer circuits. PR4440

D
PR4465
316KR2F-GP

PR4442
412KR2F-GP
120KR2J-GP DY
2

1
PQ4401
2N7002K-2-GP
CHECK PM ADAPTER TYPE

2
3D3V_S5 DY DY DY 84.2N702.J31
2ND = 84.2N702.031

PU4402_1IN-
And setting adapter type

2
PR4419

S
0R2J-2-GP

Customer Request Close PR4443 1 DY 2 PQ4401_G

84.2N702.A3F
2nd = 84.DM601.03F
(AD_IA_HW) 3rd = 84.2N702.E3F

1
PR4401 4th = 84.2N702.F3F
DIS_DTM_HW: PR4447
182KR2F-GP
PQ4411
180KR2F-GP
DCBATOUT

PWR_CHG_REGN=6V DY PWR_CHG_CMPIN 1 2 PQ4411_D1 3 4

+VCHGR

V+=6*(PR4440/(PR4441+PR4440))=3.27V

2
[20] AD_IA_HW2
2 5 AD_IA_HW [20]
Setting=3.27*((PR4442+PR4447)/PR4447)=9V
1 6 PQ4411_D2 1 2 PWR_CHG_CMPIN
GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

2N7002KDW-GP PR4420
2

75KR2F-GP
(AD_IA_HW_2)
PG4404

PG4405

DY DY
1DCBATOUT_R 1

1
1+VCHGR_R

PR4448 PR4454
DY 0R2J-2-GP DY 10R2F-L-GP ADAPTER TYPE AD_IA_HW AD_IA_HW_2 SETTING
2

1 DY
PR4407
2
90W L L 1.099V
PU4401_5

6D8R2F-GP
A A
BATTERY MON 1 DY2 65W H L 0.862329V
PR4446 PC4423
1 DY 2 BOOST_MON_1 1 DY 2PU4401_6 SCD1U25V2KX-GP
[24] BOOST_MON PR4452 PU4401_4
1
PC4417
SC1U25V3KX-1-GP

0R2J-2-GP 20KR2F-L-GP
DY 45W L H 0.659648V
6
5
4
2

PU4404
-
+

DY INA199A1-GP
1
2
3

DCBATOUT <Core Design>

PC4431
Wistron Corporation
1

SC1U25V3KX-1-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
2

Title
BDW CAP
044P_CHARGER(BQ24770)
Size Document Number Rev
A1
A00
Date: Tuesday, June 17, 2014 Sheet 44 of 102
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_5v3p3v

3D3V_AUX_S5

1
PR4501
0R2J-2-GP DY

2
PR4530
PR4504
D 2 1 PWR_5V_EN1_R 1 2 PWR_5V_EN1 D
DY
0R2J-2-GP 0R0402-PAD-2-GP

2
PR4515
0R0402-PAD-2-GP

1
PR4506
1 2 PWR_3D3V_EN2
[36] 3V_5V_EN
0R0402-PAD-2-GP

DCBATOUT

PC4525 PC4528 PC4509

SCD1U50V3KX-GP
1

1
DCBATOUT
SC10U25V5KX-GP

SC10U25V5KX-GP
DCBATOUT
2

2
PC4530 PC4529 PC4527
Design Current=6.7A

1
SCD1U50V3KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
PC4519 PC4531
PU4502 10.6A<OCP>12.5A

SC10U25V5KX-GP
1

SCD01U50V2KX-1GP
1

2
TG
Design Current=4A VIN
2
DY PU4501
3 1
6A<OCP>6.5A

2
PGAND TG
4 2
BG VIN
5 3
VSW PGAND
4
BG
5
CSD87381P-GP VSW

12
PU4503
CSD87381P-GP

VIN
PR4528
C PC4535 C
2 1PWR_3D3V_VBST2_11 2 PWR_3D3V_VBST2 TPS51225RUKR-GP SCD1U25V3KX-GP
1D5R3-GP PR4524 PC4516
SCD1U25V3KX-GP
9 17 PWR_5V_VBST1 1 2 PWR_5V_VBST1_1 1 2
VBST2 VBST1
3D3V_S5 PWR_3D3V_DRVH2 PWR_5V_DRVH1 1D5R3-GP 5V_S5
10
DRVH2 DRVH1
16 68.3R310.20A
PL4503
1 2 PWR_3D3V_LL2 8 18 PWR_5V_LL1 1 2
COIL-4D7UH-33-GP SW2 SW1 PL4501
1

68.4R71A.20H PWR_3D3V_DRVL2 11 15 PWR_5V_DRVL1 IND-3D3UH-57GP

DRVL2 DRVL1

1
PR4533 DY PR4529
PC4518
PC4517 2D2R5F-2-GP 14 PWR_5V_VO1 DY 2D2R5F-2-GP
1

1
VO1
SCD1U10V2KX-4GP

PT4501 PG4535 PG4532 PT4502

2
1

SCD1U10V2KX-4GP
PWR_3D3V_FB2 4 2 PWR_5V_FB1

2
VFB2 VFB1
ST220U6D3VBM-3-GP

ST220U6D3VBM-3-GP
1PWR_3D3V_SNUB
2

2
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
2

2
1PWR_5V_SNUB
PWR_3D3V_EN2 6 20 PWR_5V_EN1
EN2 EN1
3V_FEEDBACK

PWR_3D3V_CS2 5 1 PWR_5V_CS1
CS2 CS1
R2 R1
1

1
PR4517 PWR_5V_VCLK PR4531
PC4520
DY 34K8R2F-1-GP VCLK
19 1
49K9R2F-L-GP PC4536
DY
2

SC330P50V3KX-GP AFTP4501 SC560P50V-GP

2
7 21
2

2
PGOOD GND

VREG3

VREG5
1

1
R3
3

13
PR4535 3D3V_S5 5V_PWR_2 PR4525

1
PR4512 3D3V_PWR_2
DY0R2J-2-GP DY PR4502 0R2J-2-GP DY
6K65R2F-GP 200R2J-L1-GP PR4527
1

15KR2F-GP
2

1 2

1 2
PWR_3D3V_FB2_R PR4534 PWR_5V_FB1_R
PC4523 100KR2J-1-GP

2
1

1
DYSC18P50V2JN-1-GP PC4524 PC4522 DY
PC4526 SC4D7U6D3V3KX-GP SC18P50V2JN-1-GP
2

2
B SC4D7U6D3V3KX-GP B
2

2
1

1
PR4523 [17] 3V_5V_POK PR4526
10KR2F-2-GP 9K76R2F-1-GP

Close to VFB Pin (pin2)

2

2
3D3V_PWR_2 3D3V_AUX_S5
PR4532
2 1
Close to VFB Pin (pin5)
0R0402-PAD-2-GP

TPS51225 & TPS51285 Co-lay

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L
Inductor: CHIP CHOKE 4.7UH PCMB063T-4R7MS Cyntec 28mohm/33mohm Isat =6.5Arms 68.4R71A.20H Inductor: CHIP CHOKE 2.2U PCMC063T-2R2MN 18mohm/20mohm Isat =14Arms 68.2R210.20B
O/P capCHIP CAP T 220U 6.3V M3528 PSL /NEC/ 25mOhm / 77.C2271.45L TPS51225 TPS51285 O/P capCHIP CAP T 220U 6.3V M3528 PSL /NEC/ 25mOhm / 77.C2271.45L
H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037 H/S:SIS412 / 24mOhm/30mOhm@4.5Vgs / 84.00412.037
L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037 R1 100K 20K L/S:SIS780 / 14.5mOhm/17.5mOhm@4.5Vgs / 84.00780.037

R2 64.9K 13K
R3 DY 200

A A

Wistron Confidential document, Anyone can not

Duplicate, Modify, Forward or any other purpose
application without get Wistron permission
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51225_5V/3D3V
Size Document Number Rev
A2
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 45 of 102
5 4 3 2 1
 5 4 3 2 1

SSID = CPU.Regulator
PW R_VCC_VREF

1
D D
PR4602 PR4603 PR4604 PR4605
499KR2F-1-GP 71K5R2F-1-GP
NTC-100K-10-GP-U DY 75R2F-2-GP

2
PC4602

2
R3024 1 2 X01 0227

1
15KR2F-GP SC4700P50V2KX-1GP
1 2 PR4601 PR4607 PR4608
1 2 1 2 150KR2F-L-GP 75KR2F-GP 39KR2F-GP
PR4610 PR4609
PC4603 392KR2F-GP 56KR2F-GP

2
1 2

SC1KP50V2KX-1GP

PR4611 1 DY 2 75R2F-2-GP PW R_VCC_B-RAMP

PW R_VCC_F-Imax
PR4612

PWR_VCC_THERM
PW R_VCC_O-USR

PWR_VCC_OCP-1
PWR_VCC_IMON
1 2PW R_VCC_SLEW A

39KR2F-GP

PR4613
DCBATOUT 1 2PW R_VCC_VBAT
C 10R3J-3-GP 3D3V_S0 C

16

15

14

13

12

11

10

9
PU4601
IMVP_PW RGD PR4614 2 1 2KR2F-3-GP

THERM

IMON

O-USR
SLEWA

OCP-I

F-IMAX
VBAT

BOOT
PR4615
17 8 IMVP_VRON 1 2 H_VR_ENABLE [7]
[47] PW R_VCC_CSP1 CSP1 VR_ON 0R0402-PAD-2-GP EC4602
0117 Add EC4602

SC10P50V2JN-4GP
[47] PW R_VCC_CSN1 18 CSN1 SKIP# 7 PW R_VCC_SKIP# [47]
19 6 PW R_VCC_PW M1 [47]
X01 0224 stuff

2
CSN2 PWM1
3D3V_S5 20 CSP2 PWM2 5
TPS51624RSMR-GP-U NC#4 PR4626 1 DY
21 NC#21 MODE 4 2
0R2J-2-GP
22
74.51624.073 3 PW R_PG PR4625 1 2 IMVP_PW RGD [7,24]
NC#22 PGOOD 0R0402-PAD-2-GP
PR4616 1 2 PW R_VCC_GFB 23 2 PW R_VCC_VDD PR4618 1 2 10R3J-3-GP
[9] VSS_SENSE 0R0402-PAD-2-GP GFB VDD 3D3V_S5 X01 0227 1D05S_VCCST

PC4601
SC1U6D3V2KX-GP
PR4617 1 2 PW R_VCC_VFB 24 1
[7] VCC_SENSE VFB VDIO

1
0R0402-PAD-2-GP SCD1U10V2KX-5GP 1 PC4605
VR_HOT#
2

ALERT#
DROOP

COMP

VREF

VCLK
H_CPU_SVIDDAT 130R2F-1-GP 1 2 PR4621
GND

GND

2
V5A

H_CPU_SVIDCLK 54D9R2F-L1-GP 1 2 PR4622

25

26

27

28

29

30

31

32

33
VR_SVID_ALERT# 130R2F-1-GP 1 DY 2 PR4623
B B

PW R_VCC_DROOP

PC4604 H_CPU_SVIDDAT [7]

PWR_VCC_V5A

SC470P50V2JN-GP
VR_SVID_ALERT# [7]
28W 15W
2 DY 1 PW R_VCC_COMP

H_CPU_SVIDCLK [7] Fsw PR4604 392K 1M

H_PROCHOT# [4,24,44]
1 2 1 2 PW R_VCC_VREF Fsw PR4607 75K 150K
PR4619 PR4620 PR4624 1 2 10R3J-3-GP 5V_S5
2
SCD33U6D3V2KX-1-GP
PC4606

10KR2F-2-GP 3K4R2F-GP OCP PR4609 150k 75K

PC4607
SC10U6D3V3MX-GP
1

IMON PR4610 680K 422K

1

X01 0227
1 2 1 2 Load line PR4620 2.8K 3K
2

PR4627 PC4608
4K75R2F-1-GP SC1500P50V2KX-2GP
PWR_VCC_COMP_1

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

046P_TPS51624_CPUCORE(1/2)
Size Document Number Rev
A3 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 46 of 102
5 4 3 2 1
 5 4 3 2 1

SSID = CPU.Regulator
For acoustic noice
DCBATOUT
DCBATOUT X01 0224

D 1 D

1
PC4702 PC4703 PC4704 EC4701
PT4702 DY

SCD1U50V3KX-GP
SC10U25V5KX-GP

SC10U25V5KX-GP

SC10U25V5KX-GP
ST33U25VDM-2-GP
2

2
DCBATOUT

1
PC4708 PU4701 5V_S5
SC1000P100V3KX-GP PC4705 SC2D2U10V3KX-1GP

2
5 VIN VDD 2 1 2
PC4706

PR4702 1 2PW R_VCC_SKIP#1 1 6 PW R_VCC_BOOTR11 2VCC_BOOTR1_R 1 2

[46] PW R_VCC_SKIP# 0R0402-PAD-2-GP SKIP# BOOT_R PR4703 2D2R3F-L-GP
SCD22U25V3KX-GP
8 7 PW R_VCC_BOOT1 VCC_CORE
[46] PW R_VCC_PW M1 PWM BOOT

PGND
3 4 PW R_VCC_VSW 1 1 2
PGND VSW PL4701
IND-D22UH-46-GP

1
C C
068.R2210.2011

9
CSD97374Q4M-GP-U1 PR4701

2
GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP
2D2R5F-2-GP
74.97374.043

PG4707

PG4708
X01 0227

2
VCC_CORE

VCC_VSW1_GP 1

1
VCC_VSW 1_R

1
PC4701
PC4729

PC4730

PC4731

PC4732

PC4733

PC4734

PC4725

PC4736

PC4737

PC4738
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP SC820P50V2KX-1GP

2
1

1
DY DY DY DY
X01 0227
2

1
PR4704
2K32R2F-1-GP

2
1 2

PR4705
PC4719

PC4720

PC4721

PC4722

PC4726

PC4709

PC4710

PC4711

PC4724

PC4735
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

16K2R2F-GP
1

PR4706 PR4707
DY DY 1 2VCC_CSN1_R 1 2 PW R_VCC_CSN1 [46]
2K94R2F-GP
2

B NTC-10K-26-GP-U B

X02 0414
0318 Add EC4702, need close to PC4741 PC4707
1 2
SCD15U25V3KX-2-GP
PC4714

PC4727

PC4728

PC4715

PC4739

PC4740

PC4716

PC4741

PC4742

PC4743
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

SC22U6D3V3MX-1-GP

PW R_VCC_CSP1 [46]
1

EC4702
DY DY DY SCD1U10V2KX-5GP
2

X01 0227
(total:22uF/0603 x14pcs, 22uF/0805 x7pcs)

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

047P_TPS51624_CPUCORE(2/2)
Size Document Number Rev
A3 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 47 of 102
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p05v

D D

C
SY8208D for 1D05V C

DCBATOUT
1

PC4808 PC4804
SC4D7U25V5KX-L2-GP

SC4D7U25V5KX-L2-GP

PC4806
PR4801
PU4801 Design Current=7.3A
2

1 2 1D05V_PW R_BS_R 1 2
OCP=12A
SCD1U25V3KX-L-GP
0R3J-0-U-GP

8 6 1D05V_PW R_BS
IN BS 1D05V_S0
PL4801
[7,36] 1D05V_VTT_PW RGD
10 1D05V_PW R_PH 1 2
LX
A00 0604 IND-D68UH-40-GP

1
GAP-CLOSE-PWR-3-GP
2 4 1D05V_PW R_FB PC4811 PC4812 PC4810 PC4813 PC4805 PC4803
PG FB

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP
2

SCD1U50V3KX-L-GP
2 1 PR4802 PW R_1D05V_PW R_ILIM 3 7 1D05V_PW R_BYP

2
0R0402-PAD-2-GP ILMT BYP 3D3V_S5 PG4801
PR4804 1 PW R_1D05V_PW R_EN
DY DY
[17,24,36,49,51] PM_SLP_S3# 2 1 EN
B 0R0402-PAD-2-GP B
1 PR4807 2

1
9 5 1D05V_PW R_LDO 0R0402-PAD-2-GP
GND LDO
1

PC4801

1
SCD1U10V2KX-5GP

DY PR4803
DY 1MR2J-L3-GP SY8208DQNC-GP-U PC4807 1D05V_PW R_FBH
2

1
PC4809

SC1U6D3V2KX-GP
2

SC2D2U6D3V2MX-GP

1
PR4806

1
75KR2F-GP
PC4802
SC220P50V2KX-3GP

2
1
Vo=0.6x(1+R1/R2) PR4805
=0.6x(1+75/100) 100KR2F-L3-GP
=1.05V

2
<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SY8208DQNC_1D05V
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 48 of 104

5 4 3 2 1
 5 4 3 2 1

SY8206D for 1D35V

D D

DCBATOUT PWR_DCBATOUT_1D35V
PG4907
1 2

GAP-CLOSE-PWR
PG4903
1 2

GAP-CLOSE-PWR
PG4901
1 2

GAP-CLOSE-PWR
PG4906
1 2

GAP-CLOSE-PWR

PWR_DCBATOUT_1D35V
1

PC4906 PC4908 PC4907

PWR_1D35V 1D35V_S3
SC10U25V5KX-GP

SC10U25V5KX-GP

DY PG4902
SCD01U50V2KX-L-GP
2

1 2

GAP-CLOSE-PWR
PG4904
1 2
PU4901
GAP-CLOSE-PWR
C
Freq=800KHz CYNTEC R68 5*5*3 Design Current=4A
C
OCP=8A PG4905
PC4917 DCR:11 ~ 12 mOhm
3D3V_S5 PR4901 SCD1U25V3KX-GP 1 2
2D2R3F-L-GP Idc : 8.5 A , Isat : 14A
8 6 PWR_1D35V_BOOT 1 2 PWR_1D35V_BOOT_R 1 2 GAP-CLOSE-PWR
IN BS
1

PWR_1D35V
PG4908
PR4910 PL4901
1KR2J-1-GP DY 1 2
10 PWR_1D35V_PHASE 1 2
LX GAP-CLOSE-PWR
2

PR4907 IND-D68UH-40-GP
PG4909
1 2 PWR_1D35V_PGOOD 2 4 PWR_1D35V_VFB
[36] 1D35V_VTT_PWRGD PG FB

1
0R0402-PAD-2-GP PR4906 PR4902 1 2
1 2 PWR_1D35V_IMAX 3 7 PWR_1D35V_BYP 1 2 3D3V_S0 PC4903DY PC4905 PC4904 PC4901 PC4902
ILMT BYP

SCD1U16V2KX-3GP
PR4905 0R0402-PAD-2-GP 0R0402-PAD-2-GP PC4912 GAP-CLOSE-PWR

2
SC220P50V2KX-3GP
[17,24] PM_SLP_S4# 1 2 PWR_1D35V_EN 1

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP

SC22U6D3V5MX-L3-GP
EN

1
0R0402-PAD-2-GP
9 5 PWR_1D35V_LDO_P5
GND LDO
PC4909
SCD1U10V2KX-5GP

2
1

A00 0604
DY SY8206DQNC-GP-U
74.08206.C73
2

1
PR4903
1

1
150KR2F-L-GP
PC4913 PC4910 R1
SC1U6D3V2KX-L-1-GP SC1U6D3V2KX-L-1-GP
2

2
PWR_1D35V_VFB

1
OCP setting PR4904
High 12A 120KR2F-L-GP R2 Vo=0.6x(1+R1/R2)
=0.6x(1+68.1/100)
Float 8A =1.008V

2
B B
Low 6A

0D675V_PWR 0D675V_S0
PG4917
1 2

GAP-CLOSE-PWR
PG4918
1 2
DDR_VREF_S3 GAP-CLOSE-PWR
1

PC4916
SCD1U10V2KX-5GP
2

1D35V_S3

3D3V_S0
Peak Current = 0.5A
PR4909 1 2 10KR2J-3-GP

[12] DDR_VTT_PG_CTRL PR4926 1 DY 2 0R2J-2-GP PC4915

1

SC10U6D3V3MX-GP
[17,24,36,48,51] PM_SLP_S3# PR4925 1 DY 2 0R2J-2-GP VTT_EN PC4918
SCD1U10V2KX-5GP
2

2
11

PR4914 PU4902
1 2 PU4902_S5 0D675V_PWR
GND

[17,24] PM_SLP_S4#
0R0402-PAD-2-GP
0326 6
VTTREF VTTSEN
5
PR4917 7 4
S3 PGND
A 5V_S5 2 0D6751 1st 8
GND VTT
3 A
1

9 2
0R2J-2-GP PU4902_VCNTL S5 VIN PC4914 Wistron Confidential document, Anyone can not
10 1
VCNTL VREF SC22U6D3V3MX-1-GP Duplicate, Modify, Forward or any other purpose
2
1

PR4918 PC4911 application without get Wistron permission

<Core Design>
3D3V_S5 2 0D6751 2nd SC1U10V2KX-1GP APL5338XAI-TRG-GP
74.05338.079
2

0R2J-2-GP
Wistron Corporation
If use 74.02997.B79, Stuff PR4918 and Dummy PR4917. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
2nd source: DC to DC_1D05V(SY8208D)
74.02997.B79 Size Document Number Rev
C
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 49 of 102
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)
C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 50 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p5v

D D

3D3V_S5
TLV70215 for 1D5V_S0

PC5108
SC1U6D3V2KX-GP
1
Design Current = 150mA

2
C C
PU5101 1D5V_PWR 1D5V_S0
PG5101
1 IN OUT 5 1 2
2 GND
PWR_1D5V_EN 3 4 GAP-CLOSE-PWR
EN NC#4

PC5109
SC1U6D3V2KX-GP
1
TLV70215DBVR-GP
74.70215.03F
A00 0604

2
[17,24,36,48,49] PM_SLP_S3# 0R0402-PAD-2-GP 1 2 PR5101 PWR_1D5V_EN

PC5101
SCD1U10V2KX-5GP
1

DY
B B
2

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51367_1D5V
Size Document Number Rev
A4 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 51 of 104
5 4 3 2 1
SSID = VIDEO
Hi:2.0V
Lo:0.8V
CAMERA POWER
Panel Conn. LCDVDD Layout 80 mil
3D3V_S0

D5201
1 U5201 3D3V_S0 3D3V_CAMERA_S0
[15] EDP_VDD_EN
LCD1 3 LVDS_VDD_EN_R 1 5
DCBATOUT_LCD EN VIN#5
41 2 F5202
LCDVDD GND
1 [24] LCD_TST_EN 2 3 4 1 2
VOUT VIN#4
42
2 BAT54C-7-F-3-GP POLYSW-D5A6V-1-GP EC5210

1
SCD1U25V2KX-GP
3 X01 0219 75.00054.E7D RT9724GB-GP C5212 69.50007.921

SC4D7U6D3V3KX-L-GP
4 74.09724.09F C5214
5 2ND = 74.03514.07F SC4D7U6D3V3KX-GP

2
1

1
6 EDP_TX1# C5231 1 2SCD1U10V2KX-5GP C5208 C5209 C5211
EDP_TX1_DN [8]

SCD1U10V2KX-L1-GP

SC1U6D3V2KX-L-1-GP
7 EDP_TX1 C5232 1 2SCD1U10V2KX-5GP SC4D7U6D3V3KX-L-GP
EDP_TX1_DP [8]
8

2
9 EDP_TX0# C5230 1 2SCD1U10V2KX-5GP
EDP_TX0 EDP_TX0_DN [8]
10 C5229 1 2SCD1U10V2KX-5GP EDP_TX0_DP [8]
11
12 EDP_AUX C5226 1 2SCD1U10V2KX-5GP EDP_AUX_DP [8]
EDP_AUX# C5225 1 2SCD1U10V2KX-5GP
13
14
EDP_AUX_DN [8] INVERTER POWER
15 USB_CAMERA_P
16 USB_CAMERA_N
17 R5224
18 DMIC_CLK_C 0R2J-2-GP DCBATOUT DCBATOUT_LCD
43 19 DMIC_DATA_C 1 DY 2 F5201
20 MIC_GND 2 1
21 X02 0414
22 DBC_EN_R 1 R5201 2 D5202 POLYSW-1D1A24V-GP-U

1
LCD_TST_C 0R0402-PAD-2-GP DBC_EN [20] C5204 C5203 C5202
23 1 L_BKLT_CTRL [15] 69.50007.A31

SCD1U50V3KX-L-GP

SC1KP50V2KX-L-1-GP

SC4D7U25V5KX-L2-GP
24 EDP_HPD_CONN 2nd = 69.50007.D31
25 BLON_OUT_C BKLT_CTRL 3

2
26 LCD_BRIGHTNESS
27 CAMERA_DET# [20] 2 LCD_TST
28
29 BAT54C-7-F-3-GP
30 SENSOR_I2C_SDA [66] 75.00054.E7D X01 0219
31 SENSOR_I2C_SCL [66]
32
33 ALS_INT# [20,66]
34 DMIC_CLK_C R5204 1 2 100R2J-2-GP DMIC_CLK [27]
35 PANEL_SIZE [24] DMIC_DATA_C R5205 1 2 33R2J-2-GP DMIC_DATA [27]
36
37 LCDVDD EC5205 EC5206 X01 0227

1
38 X01 0227 DY DY

SC22P50V2JN-4GP

SC22P50V2JN-4GP
44 39
40 3D3V_CAMERA_S0
SENSOR POWER

2
45

ACES-CON40-11-GP Power Pin Count : 7 3D3V_S0 X02 0415 3D3V_SEN_S0

20.F2037.040
GND Pin Count : 7 F5204
1 2
X02 0414
RN5201

1
1 R5202 2 LCD_TST_C 1 8 POLYSW-1D1A6V-9-GP-U
LCD_TST [24]
0R0402-PAD-2-GP BLON_OUT_C 2 7 EC5211 DY C5215
3 6
BLON_OUT [24] 69.48001.081
SC33P50V2JN-3GP SC4D7U6D3V3KX-GP

2
LCD_BRIGHTNESS 4 5 BKLT_CTRL

SRN100J-4-GP
MIC_GND
EDP_HPD_CONN 1 R5203 2 EDP_HPD [15]
100R2J-2-GP

TOUCH PANEL POWER

RN5203 LCD_BRIGHTNESS
1 8 LVDS_VDD_EN_R 5V_S0 TPAN_VDD
2 7 EDP_HPD_CONN

1
3 6 BLON_OUT_C EC5207 69.50007.A31
4 5 BKLT_CTRL DY SC6D8P50V2DN-GP
2nd = 69.50007.D31

2
SRN100KJ-5-GP 3rd = 69.50007.A41
F5203
POLYSW-1D1A24V-GP-U
1 2

1
0R3J-6-GP
DY 2
R5233
X02 0415

1
USB_CAMERA_N USB_PN4 [16] C5206 C5205

SCD1U50V3KX-L-GP

SC4D7U25V5KX-L2-GP
2

2
X01 0214
FILTER-4P-171-GP
3 2

4 1

HOMBD1
17 TR5208
1 3D3V_SEN_S0 69.10118.001
2
3 TPAN_VDD
4 USB_CAMERA_P USB_PP4 [16]
5 TOUCH_PANEL_INTR# [24]
6 SENSOR_I2C_SDA [66]
7 SENSOR_I2C_SCL [66]
8 HOME_BTN#_C [24]
9 GSEN_INT1 [66]
10 GSEN_INT2 [66]
11 GYRO_INT [66] R5230
12 GYRO_DRDY [66]
13 USB_PN6_TPNL 2 1 USB_PN6 [16]
14 USB_PP6_TPNL
15 USB_PN6_TPNL 0R0603-PAD-2-GP-U
16
18

PSC-CON16-GP A00 0604

020.K0028.0016

R5223
USB_PP6_TPNL 2 1 USB_PP6 [16]
0R0603-PAD-2-GP-U

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LCD Connector
Size Document Number Rev
A2
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 52 of 102
 5 4 3 2 1

D D

(Blanking)
C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 53 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
HDMI_CLK#_R R5401 1 2 HDMI_CLK#_R_C HDMI_DATA0#_R R5403 1 2 HDMI_DATA0#_R_C
0R0402-PAD-2-GP 0R0402-PAD-2-GP

C5402 1 2 SCD1U16V2KX-3GP HDMI_CLK#_R

[8] HDMI_CLK#

1
C5403 1 2 SCD1U16V2KX-3GP HDMI_CLK_R
[8] HDMI_CLK R5414 X02 0414 R5416
[8] HDMI_DATA0#
C5404 1 2 SCD1U16V2KX-3GP HDMI_DATA0#_R X02 0414 150R2J-L1-GP-U 150R2J-L1-GP-U
C5405 1 2 SCD1U16V2KX-3GP HDMI_DATA0_R
[8] HDMI_DATA0
D D

2
C5409 1 2 SCD1U16V2KX-3GP HDMI_DATA1#_R
[8] HDMI_DATA1# C5406 SCD1U16V2KX-3GP HDMI_DATA1_R
[8] HDMI_DATA1 1 2

C5407 1 2 SCD1U16V2KX-3GP HDMI_DATA2#_R HDMI_CLK_R R5402 1 2 HDMI_CLK_R_C HDMI_DATA0_R R5404 1 2 HDMI_DATA0_R_C

[8] HDMI_DATA2# C5408 SCD1U16V2KX-3GP HDMI_DATA2_R 0R0402-PAD-2-GP 0R0402-PAD-2-GP
[8] HDMI_DATA2 1 2

8
7
6
5

8
7
6
5
HDMI_DATA2#_R R5405 1 2 HDMI_DATA2#_R_C HDMI_DATA1#_R R5407 1 2 HDMI_DATA1#_R_C
RN5402 RN5403 0R0402-PAD-2-GP 0R0402-PAD-2-GP
SRN470J-3-GP SRN470J-3-GP

1
2
3
4

1
2
3
4

1
HDMI_PLL_GND
R5415 R5417
150R2J-L1-GP-U 150R2J-L1-GP-U

2
X02 0414
R5418 X02 0414

2
DY 0R2J-2-GP
D

Q5403

1
2N7002K-2-GP
C 84.2N702.J31 C
2ND = 84.2N702.031 HDMI_DATA2_R R5406 1 2 HDMI_DATA2_R_C HDMI_DATA1_R R5408 1 2 HDMI_DATA1_R_C
3rd = 84.07002.I31 0R0402-PAD-2-GP 0R0402-PAD-2-GP
4th = 84.2N702.W31
G

5V_S0
HDMI CONN
5V_S0
HDMI1
R5413 22
3

20
1 DY 2 D5401 HDMI_DATA2_R_C 1
BAW 56-5-GP
100KR2J-1-GP 2
83.00056.Q11 HDMI_DATA2#_R_C 3
HDMI_DATA1_R_C 4
DDC_CLK_PH1 2

DDC_DATA_PH2 1

2nd = 83.00056.Y11 HDMI_DATA1#_R_C

5
6
HDMI_DATA0_R_C 7
8
84.2N702.A3F HDMI_DATA0#_R_C 9
2nd = 84.2N702.E3F HDMI_CLK_R_C 10
3rd = 75.00601.07C 11
4th = 84.DMN66.03F 69.50007.691: HDMI_CLK#_R_C 12
OBS REASON: Please transfer to down size item 69.48001.081 for cost reduction and good cost down trend 13
3
4

3D3V_S0 X01 0214 14

DDC_CLK_HDMI 15
RN5401 5V_HDMI_S5 DDC_DATA_HDMI 16
SRN2K2J-1-GP 5V_S0 5V_S5 X02 0414 5V_HDMI_R_S5 5V_HDMI_S5 17
F5401 18
B Q5402 B
POLYSW -1D1A6V-9-GP-U 19
2
1

4 3 DDC_CLK_HDMI R5409 1 2 1 2 21
[15] PCH_HDMI_CLK 0R0603-PAD-2-GP-U 23

1
5 2 1 DY 2 C5401
R5423 0R3J-0-U-GP 69.48001.081

SCD1U16V2KX-3GP
6 1 X01 0227 SKT-HDMI23-15-GP-U

2
2nd = 69.50011.081 22.10296.431

HPD_HDMI_CON
For DIODE in case of leakage from HDMI1
2N7002KDW -GP
[15] PCH_HDMI_DATA
DDC_DATA_HDMI
3D3V_S0

Q5401
X01 0214 R5411

C
3D3V_S5 CH3904PT-GP 150KR2F-L-GP
4th = 84.2N702.W31 B HDMI_HPD_B 2 1
3rd = 84.07002.I31
1

1
84.03904.P11

E
R5420 2ND = 84.2N702.031 X02 0414 R5419 DY R5410
X02 0414 10KR2J-3-GP 84.2N702.J31 [15] HDMI_PCH_DET 1 2 HDMI_HPD_E 2nd = 84.03904.T11 200KR2F-L-GP
2N7002K-2-GP R5421

1
0R0402-PAD-1-GP
2

2
G HPD_HDMI_CON_C 1 2 HPD_HDMI_CON R5412
R5422
10KR2J-3-GP
[24] HDMI_EC_DET# 1 2 HDMI_EC_DET#_C D 0R0402-PAD-2-GP

2
0R0402-PAD-2-GP S <Core Design>
A A
Q5404
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

HDMI Level Shifter/Connector

Size Document Number Rev
A3 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 54 of 104

5 4 3 2 1
 5 4 3 2 1

D D

C
(Blanking) C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)DP to VGA Converter
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 55 of 104
5 4 3 2 1
SSID = SATA

SATA HDD Connector X02 0414

HDD1
R5601
22 21
[67] FFS_INT2_Q 2 1 FFS_INT2_Q_R 1 NP1

0R0402-PAD-2-GP 2
3 Layout Note:
4
5V_S0 5
Place near HDD1
6 1A
7 U5602
8 5V_S0
9 SATA_TXP0_R 1 10 SATA_TXP0_R
SATA_TXN0_R LINE_1 NC#10 SATA_TXN0_R
10 2 LINE_2 NC#9 9
11
SATA_RXN0_R
3 GND DY GND 8
SATA_RXN0_R
12 4 LINE_3 NC#7 7
13 SATA_RXP0_R 5 6 SATA_RXP0_R
LINE_4 NC#6

1
14
[19] SATA3_PTX_HDDRX_P0 SCD01U50V2KX-1GP 1 2 C5602 SATA_TXP0_R 15 C5605 C5606
SCD01U50V2KX-1GP 1 2 C5603 SATA_TXN0_R 16 SC2D2U10V3KX-1GP AZ1045-04F-R7G-GP
[19] SATA3_PTX_HDDRX_N0

2
17 BDW CAP SCD1U16V2KX-3GP
SCD01U50V2KX-1GP 1 2 C5616 SATA_RXN0_R 18
[19] SATA3_PRX_HDDTX_N0 SCD01U50V2KX-1GP 1 2 C5615 SATA_RXP0_R 19 75.01045.073
[19] SATA3_PRX_HDDTX_P0 Swap based on the swap report.
20 NP2
24 23

FOX-CON20-1-GP-U1
20.F1546.020 Close to HDD1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

HDD/ODD
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 56 of 104
 5 4 3 2 1

SSID = ESATA

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
ESATA
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 57 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Taipei Hsien 221, Taiwan, R.O.C.

Title

WLAN (NGFF) CONN

Size Document Number Rev
A4
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 58 of 104
5 4 3 2 1
 A B C D E

4 4

3
(Blanking) 3

2 2

<Core Design>

1
Wistron Corporation 1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A4
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 59 of 104
A B C D E
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)
Size Document Number Rev
A4 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 60 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface

D D

C C

(Blanking)

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LED Bard/Power Button

Size Document Number Rev
A4
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 61 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = KBC

Keyboard Touch.Pad
D D

X01 0214

3D3V_S5
TP_VDD Discharge Circuit
3D3V_S0 TP_VDD
NON TP_WAKE TP_VDD
20.K0615.026 TP_WAKE
Q6203
R6211 1 2 X01 0303
ACES-CON26-13-GP-U 0R3J-0-U-GP
DMP2130L-7-GP

1
28
AFTP6228 1 KROW1 26 S R6210
AFTP6201 1 KROW7 25 D 100R3J-4-GP
Q6205

D
AFTP6202 KROW6
1 24 TP_WAKE

G
[24] KROW[0..7] AFTP6223 1 KCOL9 23 TP_ON#_GATE G

2
1
AFTP6203 1 KROW4 22 SCD1U16V2KX-3GP 84.02130.031

G
AFTP6227 1 KROW5 21 TP_WAKE C6204 2ND = 84.03413.A31 D Q6205_Q
[24] KCOL[0..16] AFTP6217 1 KCOL0 20

2
AFTP6206 1 KROW2 19 1 2 TP_ON#_GATE S
[24] TP_ON#
AFTP6207 1 KROW3 18
AFTP6215 1 KCOL5 17 R6204
AFTP6219 KCOL1 20KR2F-L-GP 2N7002K-2-GP
1 16
AFTP6208 1 KROW0 15 84.2N702.J31
AFTP6216 1 KCOL2 14 2ND = 84.2N702.031
AFTP6210 1 KCOL4 13
AFTP6211 KCOL7 3rd = 84.07002.I31
1 12
AFTP6213 1 KCOL8 11 4th = 84.2N702.W31
AFTP6212 1 KCOL6 10
AFTP6214 1 KCOL3 9
AFTP6218 1 KCOL12 8
AFTP6221 1 KCOL13 7
AFTP6222 1 KCOL14 6
AFTP6224 1 KCOL11 5
AFTP6225 1 KCOL10 4
C AFTP6220 1 KCOL15 3 TP_VDD C
CAP_LED 2
CAP_LED
1
AFTP6233 1 GPIO_TPAD: TBD
27
(Touch pad wake# for S3 wake up @ PCH GPIO??)

2
1
KB1
RN6201
SRN10KJ-5-GP Touch Pad Connector
AFTP6226 1
TP_VDD

3
4
RN6202
C6201
SRN33J-5-GP-U
2 3 TPCLK_C 2 1
[24] TPCLK
1 4 TPDATA_C
PS2 [24] TPDATA
SCD1U16V2KX-3GP
0R2J-2-GP 1 2 R6212 I2C1_SCL_R TP1
[20] I2C1_SCL
0R2J-2-GP 1
DY I2C1_SDA_R
DY 2 R6213 10
5V_S0 +5V_KB_BL I2C [20] I2C1_SDA
8
I2C1_SDA_R 7
F6201 I2C1_SCL_R 6
1 2
69.50007.921 5

EC6202
SC33P50V2JN-3GP

EC6203
SC33P50V2JN-3GP

EC6204
SC33P50V2JN-3GP
[20,24] INT_TP# 4
1

1
POLYSW-D5A6V-1-GP [24] TP_LOCK# 3
C6202 EC6201 TPDATA_C 2
1 2 SC33P50V2JN-3GP DY DY DY DY
DY
2

2
R6205 0R3J-0-U-GP SCD1U16V2KX-3GP X02 0415 TPCLK_C 1
9

KBLIT1 ACES-CON8-40-GP
5 20.K0667.008
X02 0417 1
1 AFTP6235

2
3
KCOL16
KB_BL_CTRL#

1 4
AFTP6229
6 Pin number Pin name
B Need to check if it is Active High or Active Low B

and check if there is PH on TPAD side. 1 VDD

ACES-CON4-39-GP
D

5V_S0 2 DAT(I2C)
KB Backlight Power Consumption: 285mA max. Q6202 20.K0422.004
P8503BMG-GP X02 0415 3 CLK(I2C)
[24] KB_BL_CTRL
G 84.P8503.031
TP_VDD TP_VDD 4 GND
2nd = 84.03404.C31 A00 0609
1

1
DY R6208 5 ATTN
100KR2J-1-GP R6216
+5V_KB_BL 1 0R0402-PAD-2-GP 6 GPIO

1
AFTP6248
2

1
2
KB_BL_CTRL# 1 R6203 7 DAT(PS2)

2
AFTP6247 RN6204 10KR2J-3-GP
SRN2K2J-1-GP 8 CLK(PS2)

2
Q6204_G INT_TP#

4
3
Q6204
CAP LED Control 2N7002KDW-GP
I2C1_SCL 1 6 I2C1_SCL_R TP_VDD 1 AFTP6239
LOW actived from KBC GPIO TPCLK_C 1 AFTP6238
84.2N702.A3F 2 5 TPDATA_C 1 AFTP6236
2nd = 84.2N702.E3F I2C1_SCL_R 1 AFTP6237
3rd = 75.00601.07C 3 4 I2C1_SDA_R I2C1_SDA_R 1 AFTP6240
4th = 84.DMN66.03F INT_TP# 1 AFTP6241
TP_LOCK# 1 AFTP6242

5V_S5
X02 0414 I2C1_SDA
Q6201R2
E
1 2 CAP_LED_R# B
[24] CAP_LED# R6202 0R0402-PAD-2-GP
R1
CAP_LED_Q CAP_LED
C 1 2
R6201 1KR2J-1-GP
DDTA144VCA-7-F-GP
84.00144.N11
A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Key Board/Touch Pad

Size Document Number Rev
A2 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 62 of 104
5 4 3 2 1
 5 4 3 2 1

IOBD1
41
1
42
2 USB_PP2 [16]
D 3 D
USB_PN2 [16]
4
5 USB_PN7 [16]
6 USB_PP7 [16]
7 KBC_PWRBTN# [24]
8 USB_PP5 [16]
9 USB_PN5 [16]
10 VOL_UP# [24]
11 PCIE_PRX_WLANTX_N3 [16]
12 PCIE_PRX_WLANTX_P3 [16]
13 VOL_DOWN# [24]
14 PCIE_PTX_WLANRX_N3_C [16]
15 PCIE_PTX_WLANRX_P3_C [16]
16
17 CLK_PCIE_WLAN_P3 [18]
18 CLK_PCIE_WLAN_N3 [18]
43 19
20 CHG_AMBER_LED# [24]
21 BATT_WHITE_LED# [24]
22 CLK_PCIE_WLAN_REQ3# [18]
C 23 PLT_RST# [17,24,65] C
24 WIFI_RF_EN [24]
25 BLUETOOTH_EN [20]
26 LID_CLOSE# [24]
27 USB_PWR_EN# [24,35]
28 USB_OC#2_3 [16]
29
30
31 +RTC_VCC
32 3D3V_S0
33
34
35
36 3D3V_S5
37 5V_S5
38
44 39
40
45

B STAR-CON40-GP B
20.F2248.040

Power Pin Count : 10

GND Pin Count :5

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

IO Board Connector
Size Document Number Rev
A4 Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 63 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface

D D

3D3V_S5

3D3V_S5

SCD1U16V2KX-3GP
C6402

1
R6401
100KR2J-1-GP LIDSW1
DY

2
1

1
VSS
2 VDD
[24] KB_CLOSE#_2 3 OUT
C C
S-5712ACDL1-M3T1U-GP

1
C6401
DY SCD047U16V2KX-1-GP 74.05712.0BB
2
2nd = 74.09132.C7B

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Hall Sensor
Size Document Number Rev
A4 A00
Cottonwood
Date: Tuesday, June 17, 2014 Sheet 64 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = DEBUG PORT

D D

Debug Connector
3D3V_S0
DB1
12
LPC_AD[3..0]
[18,24] LPC_AD[3..0]
10
LPC_AD0 9
LPC_AD1 8
LPC_AD2 7
C LPC_AD3 6 C

[18,24] LPC_FRAME# 5
[17,24,63] PLT_RST# 4 Debug
3
[18] CLK_PCI_LPC 2

11

ACES-CON10-14-GP
20.F1180.010
20.D0075.110: Dummy Pad with solder mask is ZZ.00PAD.Y41
DB1 Optional: New one smaller LPC connector is 20.F1180.010.

B B

X01 0214

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Dubug connector
Size Document Number Rev
A4
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 65 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = User.Interface 1209 Add

[67] GYRO_INT_P11
0R2J-2-GP
1 DY 2
R6624
GYRO_INT [52]
R6602 3D3V_MCU From APU
*Sensor HUB Version Differences 100KR2J-1-GP
GYRO_INT_C 1 2 MCU_RST# 1 2
071.32151.000U is for Redwood R6625 0R0402-PAD-2-GP

071.32151.0A0U is for Cottonwood 1 DY 2 SENSOR_HUB_RST# [15]

X02 0414

1
C6602 R6603
0R2J-2-GP
SCD1U10V2KX-5GP
Sensor Hub

2
D
3D3V_S0 3D3V_MCU D
R6607
150mA
1 2
U6601

C6608
SC1U10V2KX-1GP

C6605
SCD01U50V2KX-1GP

C6606
SCD01U50V2KX-1GP

C6607
SCD01U50V2KX-1GP

C6604
SCD1U10V2KX-5GP

C6603

SCD1U10V2KX-5GP
0R0603-PAD-2-GP-U

1
1 VLCD PB0 18 GSEN_INT1 [52]
PB1 19 GSEN_INT2 [52]
9 20 GYRO_INT_C

2
VDDA PB2
PB3 39 GYRO_DRDY [52]
24 VDD_1 PB4 40
36 VDD_2 PB5 41 X6601
48 42 SENSOR_I2C_SCL
VDD_3 PB6 SENSOR_I2C_SDA
PB7 43
45 MCU_OSCO 3 2
PB8
10 PA0_WKUP1 PB9 46
HUB_PA1 11 21
HUB_PA2 PA1 PB10
12 PA2 PB11 22

1
HUB_PA3 13 25 C6609 4 1 MCU_OSCI
HUB_PA4 PA3 PB12
14 PA4 PB13 26

1
HUB_PA5 15 27 SC15P50V2JN-2-GP

2
PA5 PB14
X02 0414 HUB_PA6 16 PA6 PB15 28 ALS_INT# [20,52] XTAL-12MHZ-67-GP
C6601
GSEN2_INT1_C 17

2
PA7 MCU_OSCI SC15P50V2JN-2-GP
R6605
29 PA8 PH0_OSC_IN 5
MCU_OSCO
82.30006.641
30 PA9 PH1_OSC_OUT 6
1K5R2F-2-GP
1 2 USBDISABLE 31
R6604 PA10
[16] USB_PN3 1 2 0R0402-PAD-2-GP USB_3- 32 PA11 RST# 7 MCU_RST#
[16] USB_PP3 R6601 1 2 0R0402-PAD-2-GP USB_3+ 33 44 MCU_BOOT0
SW DIO PA12 BOOT0
34 PA13

1
SW CLK 37
C GSEN2_INT2_C PA14 R6606 C
38 PA15 VSSA 8
20KR2J-L2-GP
[24] KB_DISABLE 2 PC13_WKUP2 VSS_1 23
3 35

2
PC14_OSC32_IN VSS_2
4 PC15_OSC32_OUT VSS_3 47 X02 0414
49 3D3V_GSEN2 3D3V_S0
GND

STM32L151CBU6TR-GP
G sensor 11uA
1 2
R6622 0R0402-PAD-2-GP
071.32151.000U

1
C6610 C6611

SCD1U10V2KX-5GP

SC10U6D3V3MX-L-GP
For Sensor Orientation Setting

2
3D3V_MCU 3D3V_MCU
U6602
RN6601
R6609 1 DY 2 10KR2J-3-GP R6610 1 2 10KR2J-3-GP 4 1 10 1
[52] SENSOR_I2C_SCL RES#10 VDD_IO
[52] SENSOR_I2C_SDA 3 2 13 RES#13
R6611 1 2 10KR2J-3-GP R6612 1 DY 2 10KR2J-3-GP 15 14
RES#15 VDD
SRN2K2J-1-GP 16 RES#16
R6613 2 10KR2J-3-GP R6614 2 10KR2J-3-GP near pin14
1 1 DY SENSOR_I2C_SCL_2G GSEN2_INT1
4 SCL/SPC INT1 11
R6615 1 DY 2 10KR2J-3-GP R6616 1 2 10KR2J-3-GP SENSOR_I2C_SDA_2G 6 9 GSEN2_INT2
SDA/SDI/SDO INT2
R6617 1 2 10KR2J-3-GP R6618 1 DY 2 10KR2J-3-GP 3D3V_GSEN2 1 2 7 8 GSENSOR_CS 2 1 3D3V_GSEN2
R6626 10KR2J-3-GP SDO/SA0 CS R6623 10KR2J-3-GP
R6619 1 2 10KR2J-3-GP R6620 1 DY 2 10KR2J-3-GP 1 DY 2 GSENSOR_SDO
B B
For MCU debug port R6627 0R2J-2-GP 5 GND NC#2 2
HUB_PA1 12 3
HUB_PA2 GND NC#3
HUB_PA3 3D3V_MCU
HUB_PA4 LNG3DMTR-GP
HUB_PA5 SW DIO 1
HUB_PA6 SW CLK 1
TP6601
TP6602
TPAD14-OP-GP
TPAD14-OP-GP
74.LNG3D.0BZ
1 TP6603 TPAD14-OP-GP
1 TP6604 TPAD14-OP-GP

GSEN2_INT1_C R6628 1 2 0R0402-PAD-2-GP GSEN2_INT1

GSEN2_INT2_C R6629 1 2 0R0402-PAD-2-GP GSEN2_INT2

A00 0609
R6621 1 2 0R2J-2-GP
[15,67] HDD_FALL_INT
R6608 1 2 0R2J-2-GP
[67] FFS_INT2

A A00 0609 <Core Design> A

0R4P2R-PAD Wistron Corporation

SENSOR_I2C_SCL 2 3 SENSOR_I2C_SCL_2G 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
SENSOR_I2C_SDA 1 4 SENSOR_I2C_SDA_2G Taipei Hsien 221, Taiwan, R.O.C.

RN6604 Title
Gyro / G sensor / E-compass
RN

Size Document Number Rev

A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 66 of 104
5 4 3 2 1
 5 4 3 2 1

X01 0227

D6701
D [66] GYRO_INT_P11 1 D

3 INT2_SELECT [20]

[66] FFS_INT2 2

BAT54A-7-F-2-GP
75.00054.R7D

R6705 1 DY 2 0R2J-2-GP

Note:
- no via, trace, under the sensor (keep out area around 2mm)
C C
3D3V_S0 - stay away from the screw hole or metal shield soldering joints
- design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
Free Fall Sensor 3D3V_RUN_FFS 1FFS 2 - mount the sensor near the center of mass of the NB as possible as you can

C6701
SCD1U16V2KX-3GP

C6702
SCD1U16V2KX-3GP

C6703
SC10U6D3V3MX-GP
R6702
0R3J-6-GP

1
U6701
FFS FFS DY

2
10
13
RES#10
RES#13
VDD_IO 1
Please help to close with U6602
15 RES#15 VDD 14
16 RES#16 3D3V_S0
R6708 1 FFS 2 0R2J-2-GP FFS_SCL 4 11 FFS_INT1_D R6706 1 FFS 2 0R2J-2-GP HDD_FALL_INT
[12,18,96] PCH_SMBCLK SCL/SPC INT1 HDD_FALL_INT [15,66]
R6709 1 2 0R2J-2-GP FFS_SDA 6 9 FFS_INT2_D R6707 1 2 0R2J-2-GP FFS_INT2
[12,18,96] PCH_SMBDATA SDA/SDI/SDO INT2

1
FFS 3D3V_RUN_FFS
FFS R6701
7 SDO/SA0 CS 8
100KR2J-1-GP
FFS
5 2

2
GND NC#2 FALL_INT2
12 GND NC#3 3

LNG3DMTR-GP
B Q6701 B
74.LNG3D.0BZ

1
2N7002KDW -GP
84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F

6
INT2_SELECT
FFS_INT2_Q [56]

Note:
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom.

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 67 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
RESERVED
Document Number Rev
A3 Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 68 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

USB3.0 PORT
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 69 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 70 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 71 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 72 of 104
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_PCIE/STRAPPING(1/5)
Size Document Number Rev
A2
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 73 of 104

5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU Memory(2/5)
Size Document Number Rev
A2
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 74 of 104
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_DP/LVDS/CRT/GPIO(3/5)
Size Document Number Rev
A2
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 75 of 104
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_POWER(4/5)
Size Document Number Rev
Custom
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 76 of 104
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_DPPWR/GND(5/5)
Size Document Number Rev
Custom
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 77 of 104
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)

C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM1,2 (1/4)
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 78 of 104

5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)

C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM3,4 (2/4)
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 79 of 104

5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)

C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM5,6 (3/4)
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 80 of 104

5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)

C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM7,8 (4/4)
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 81 of 104

5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8812_VGACORE
Size Document Number Rev
A2
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 82 of 104

5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)

C C

B B

A A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DISCRETE VGA POWER
Size Document Number Rev
Custom Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 83 of 104

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 84 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 85 of 104
5 4 3 2 1
 5 4 3 2 1

SSID = Mechanical

D ZZ.00PAD.7F1 34.4GD01.001 ZZ.00PAD.7G1 D

34.4T025.001 HS1 HS2 HS3

SPRING-52-GP SPRING-52-GP H1 H5 H6 H2 H3 H4
SPR1 1 SPR2 HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP STF237R125H42-1-GP STF237R125H42-1-GP STF237R125H42-1-GP HOLE335R229-GP HOLE335R229-GP HOLE335R229-GP

1
SSID = EMI
Mind the voltage rating of the caps.

C C

X01 0303
X01 0303
X01 0303
AUD_AGND DCBATOUT 3D3V_S0 3D3V_S5 +DC_IN 5V_S5 5V_S0 1D35V_S3

EC8603 EC8604 EC8602 EC8601

1

EC8630
SC1KP50V2KX-1GP

EC8631
SC1KP50V2KX-1GP
EC8605 EC8606 EC8610 EC8632 EC8607 EC8608 EC8613 EC8609 EC8611 EC8612 EC8614 EC8616 EC8615
1

1
SCD1U25V2KX-GP

SCD1U25V2KX-GP

SC1U25V3KX-1-GP

SC2200P50V2KX-2GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP
DY DY DY DY DY DY DY DY DY DY DY
SC1KP50V2KX-1GP

SC1KP50V2KX-1GP
2

2
BDW CAP
BDW CAP

SSID = RF
B
X01 0224 B

1D35V_S3 DCBATOUT
EC8623
SC1U25V3KX-1-GP

EC8624
SC1U25V3KX-1-GP

EC8625
SC1U25V3KX-1-GP

EC8626
SC1U25V3KX-1-GP

EC8627
SC1U25V3KX-1-GP

EC8628
SC1U25V3KX-1-GP

EC8629
SC1U25V3KX-1-GP
EC8617 EC8618 EC8619
1

1
SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

EC8620 EC8621 EC8622

SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP
2

2
X02 0415
1D35V_S3
1

A <Core Design> A
EC8633 EC8634 EC8635 EC8636 EC8637 EC8638
SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

SC2200P50V2KX-2GP
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors

Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 86 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 87 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 88 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C (Blanking) C

B B

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
(Reserved)Finger Print
Size Document Number Rev
A4
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 89 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Free Fall Sensor

Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 90 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 91 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 92 of 104
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Express Card
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 93 of 104

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LVDS_Switch
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 94 of 104

5 4 3 2 1
 5 4 3 2 1

D D

C C

(Blanking)

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CRT_Switch
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 95 of 104

5 4 3 2 1
 5 4 3 2 1

SSID = XDP
CPU XDP

D D

CFG[19:0]
[6] CFG[19:0]
XDP_BPM[7:0]
[4] XDP_BPM[7:0]
XDP_PREQ# 1 TP9601 TPAD14-OP-GP
[4] XDP_PREQ#

[4] XDP_PRDY# XDP_PRDY# 1 TP9602 TPAD14-OP-GP

[4] XDP_TDO XDP_TDO 1 TP9624 TPAD14-OP-GP
[4] XDP_TRST# XDP_TRST# 1 TP9621 TPAD14-OP-GP
[4] XDP_TDI XDP_TDI 1 TP9623 TPAD14-OP-GP
XDP_TMS 1 TP9611 TPAD14-OP-GP
[4] XDP_TMS
XDP_BPM0 1 TP9612 TPAD14-OP-GP
XDP_BPM1 1 TP9613 TPAD14-OP-GP
XDP_BPM2 1 TP9614 TPAD14-OP-GP
[7] H_VCCST_PWRGD 1 TP9648 TPAD14-OP-GP XDP_BPM3 1 TP9615 TPAD14-OP-GP
1 TP9645 TPAD14-OP-GP XDP_BPM4 1 TP9616 TPAD14-OP-GP
[17,24] PM_PWRBTN# XDP_BPM5 TP9617 TPAD14-OP-GP
1
C 1 TP9647 TPAD14-OP-GP XDP_BPM6 1 TP9618 TPAD14-OP-GP C
[7] PWR_DEBUG TP9644 TPAD14-OP-GP XDP_BPM7 TP9619 TPAD14-OP-GP
[17,24] SYS_PWROK 1 1

1 TP9646 TPAD14-OP-GP
[12,18,67] PCH_SMBDATA
1 TP9649 TPAD14-OP-GP CFG0 1 TP9626 TPAD14-OP-GP
[12,18,67] PCH_SMBCLK
CFG1 1 TP9627 TPAD14-OP-GP
[4] XDP_TCLK XDP_TCLK 1 TP9650 TPAD14-OP-GP CFG2 1 TP9620 TPAD14-OP-GP
CFG3 1 TP9622 TPAD14-OP-GP
CFG4 1 TP9630 TPAD14-OP-GP
[18] PCIE_CLK_XDP_P PCIE_CLK_XDP_P 1 TP9652 TPAD14-OP-GP CFG5 1 TP9631 TPAD14-OP-GP
[18] PCIE_CLK_XDP_N PCIE_CLK_XDP_N 1 TP9651 TPAD14-OP-GP CFG6 1 TP9629 TPAD14-OP-GP
CFG7 1 TP9628 TPAD14-OP-GP
CFG17 1 TP9634 TPAD14-OP-GP
XDP_DBRESET# 1 TP9653 TPAD14-OP-GP CFG16 1 TP9635 TPAD14-OP-GP
[17] XDP_DBRESET# CFG8 TP9633 TPAD14-OP-GP
1
CFG9 1 TP9632 TPAD14-OP-GP
CFG10 1 TP9637 TPAD14-OP-GP
CFG11 1 TP9639 TPAD14-OP-GP
CFG19 1 TP9638 TPAD14-OP-GP
CFG18 1 TP9636 TPAD14-OP-GP
B CFG12 1 TP9640 TPAD14-OP-GP B
CFG13 1 TP9643 TPAD14-OP-GP
CFG14 1 TP9642 TPAD14-OP-GP
CFG15 1 TP9641 TPAD14-OP-GP

<Core Design>

A
Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU/PCH XDP
Size Document Number Rev
A4
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 96 of 104
5 4 3 2 1
 5 4 3 2 1

Shark Bay Platform Power Sequence

(DC mode) Red Words: Controlled by EC GPIO

+RTC_VCC t01 >9ms

RTC_RST#

DCBATOUT

3D3V_AUX_S5
D D

Sense the power button status

Press Power button
KBC_PWRBTN# Platform to KBC PSL_IN2
PSL_OUT#(GPIO71) keep low
3D3V_AUX_KBC
KBC GPIO34 control power on by 3V_5V_EN
S5_ENABLE

5V_S5
V5REF_Sus must be powered up before
5V_S5 & 3D3V_S5 need meet 0.7V difference
VccSus3_3, or after VccSus3_3 within 3D3V_S5
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before
5V_S5 & 3D3V_S5 need meet 0.7V difference
VccSus3_3 within 0.7 V.
+5VA_PCH_VCC5REFSUS Ta
KBC GPIO43 to PCH
PM_RSMRST#(RSMRST#_RST) t05 >10ms
In case of a non-Deep S4/S5 Platform
t07 >100ms PCH to KBC GPIO00
timing t42 should be added to t07 PCH_SUSCLK_KBC
which will make it 100mS minimum.

KBC GPIO20 to PCH

PM_PWRBTN#

DC PM_PWRBTN#
After Power Button
PCH to KBC GPIO44
PM_SLP_S4#
t10 PCH to KBC GPIO01
PM_SLP_S3# >30us
KBC GPIO47 to LAN
PM_LAN_ENABLE
Enable by PM_SLP_S4#
1D5V_S3
C C
DDR_VREF_S3(0.75V)
5V_S0 & 3D3V_S0 need meet 0.7V difference
5V_S0

V5REF must be powered up before 3D3V_S0

Vcc3_3, or after Vcc3_3 within 0.7
V. Also, V5REF must power down
after Vcc3_3, or before Vcc3_3
within 0.7 V.
+5VS_PCH_VCC5REF Tb

1D5V_S0

1D8V_S0

0D75V_S0
1D8V_S0 & 1D5V_S3 power ready
RUNPWROK

1D05V_PCH

VCCP_CPU

1D05_VTT_PWRGD

0D85V_S0

0D85V_S0
D85V_PWRGD

CPU SVID BUS SetVID ACK

50us< t36 <2000us

VCC_CORE

VCC_GFXCORE
t37
<5ms
IMVP_PWRGD
B B

PCH_CLOCK_OUT

This signal represents the Power

ALL_SYS_PWRGD=D85V_PWRGD t14 >99ms KBC GPIO77 to PCH
Good for all the non-CORE and
non-graphics power rails.
PWROK(S0_PWR_GOOD)
t18
D85V_PWRGD >0us PCH to CPU
DRAMPWROK(VDDPWRGOOD) 2ms<t17 <650ms
t19 >1ms
t20 >2ms
1D8V_S0
5ms<t13 <650ms PCH to CPU
UNCOREPWRGOOD(H_CPUPWRGD)

SYS_PWROK t21+t22 >1ms+60us

1ms< t25 <100ms PCH to all system
PLT_RST#
t39 <200us
DMI

N14P-GT Power-Up/Down Sequence

3D3V_S0
PCH GPIO54 output
DGPU_PWR_EN#(Discrete only)

3D3V_VGA_S0(VDD33)

A
8209A_EN/DEM_VGA(Discrete only) A

VGA_CORE(NVVDD) tNVVDD >0ms

RT8208 PGOOD
DGPU_PWROK(Discrete only)

1D5V_VGA_S0(FBVDDQ) tNV-FBVDDQ >0ms

1D05V_VGA_S0(PEX_VDD) tNV-PEX_VDD >0ms

First rail to power down VGA_CORE,1D05V_VGA_S0 <Core Design>

1D5V_VGA_S0,3D3V_VGA_S0
Last rail to power down Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
tPOWER-OFF <10ms Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Sequence
Size Document Number Rev
For power-down, reversing the ramp-up sequence is recommended. A1
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 97 of 104
5 4 3 2 1
 5 4 3 2 1

Wistron SHARK BAY POWER UP SEQUENCE DIAGRAM

D D

DC 3
BT+ SWITCH
Battery PM_SLP_S4#
Page43 Page44

-7 -3 DCBATOUT
AC +DC_IN SWITCH DCBATOUT
Adapter in S5_ENABLE 3a
Page44 4a
Page42 VIN 1D35V_S3
SW
VIN 1D05V_S0
AD+ SW

4 TPS51367
-5 EN1 EN2 RUNPWROK
3D3V_S5 TPS51367 EN PGOOD
PM_SLP_S3# RUNPWROK Page48
Charger EN PGOOD
DCBATOUT TPS51225CRUKR Page48 4b
BQ24715 VIN
DC/DC -2 4b
(3.3V/5V) 5V_S5
ACOK Page44 1D35V_S3
Page41

3D3V_AUX_S5 RUNPWROK 5V_S0

4 SWITCH
Page36
DDR_VTT_PG_CTRL 0D675V_S0
C
-4 SWITCH TPS51206 C

Page24 Page46
RUNPWROK 3D3V_S0
-6 SWITCH
3D3V_AUX_KBC -3 4b Page36
5
AC_IN S5_ENABLE 7
PSL_IN1# GPIO34
DDR_PG_CTL RUNPWROK Level H_VCCST_PWRGD
1 H_VR_ENABLE Shifter
VR_EN
Page7
KBC_PWRBTN# -1
PSL_IN2# KBC DPWROK H_CPU_SVIDDAT
VIDSOUT
PM_SLP_S4#
NPCE985 GPIO43
RSMRST#_KBC
RSMRST# Haswell ULT CPU
GPIO8 PM_PWRBTN# 11
PM_SLP_S3#
GPIO01
GPIO20 PWRBTN#
with
3D3V_S5
GPIO80 2 Lynx Point PCH
Page24 12 4a
SLP_S3# de-assert, delay 20ms; APWROK PCI_PLTRST# 4 VIN 1D5V_S0
PCH_PWROK assert. PLTRST# VOUT
10 S0_PWR_GOOD
6 PCH_PWROK VCCST_PWRGD SYS_PWROK VR_READY PM_SLP_S3# TPS51312 RUNPWROK
SLP_S3# de-assert, delay 200ms; EN PGOOD
S0_PWR_GOOD assert. Page51

5 4b
PCH_PWROK H_VCCST_PWRGD
B B

SYS_PWROK be asserted after S0_PWR_GOOD

assertion and CPU core VR power good
assertion.
11
S0_PWR_GOOD
H_CPU_SVIDDAT
VDIO

TPS51622 9
7 H_VR_ENABLE IMVP_PWRGD
VR_ON PGOOD

Page46

PWR_VCC_PWM1

DCBATOUT 8
CSD97374
VCC_CORE
VSW
Page47

A A

<Core Design>

1 2 3a 4 4a 4b 5 6 7 8 9 10 11 12
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Sequence Diagram

Size Document Number Rev
A2
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 98 of 104
5 4 3 2 1
 5 4 3 2 1

DCBATOUT
Adapter
RT8237 TPS51216RUKR ISL95813 AP3211
D D

Charger
1D05V_S0
BQ24717
1D35V_S3 0D675V_S0 VCC_CORE VGA_CORE
Battery +PBATT

TPS22966 TLV70215 SIRA06DP

1D05V_VGA_S0 1D5V_S0 1D35V_VGA_S0

C C

TPS51125ARGER

15V_S5 3D3V_AUX_S5 5V_AUX_S5 5V_S5 3D3V_S5

TPS22966
AP2182SG AP2301M8G TPS22966 AO3403
TLV70215

3D3V_S0
USB30_VCCA +5V_USB1 5V_S0 3D3V_LAN_S5
USB30_VCCB 1D5V_S0
B B

SY6288

ODD_PWR_5V
RT9724 TPS22966
Power Shape

LCDVDD 3D3V_VGA_S0
Regulator LDO Switch

A <Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Power Block Diagram
Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 99 of 104
5 4 3 2 1
 A B C D E

PCH SMBus Block Diagram KBC SMBus Block Diagram

3D3V_S5_PCH 3D3V_S0

‧ ‧ TP_VDD

3D3V_S0 ‧
SRN2K2J-1-GP
‧ SRN10KJ-5-GP

DIMM 1
‧ ‧
SRN10KJ-5-GP

‧ ‧
SMBCLK SMB_CLK PCH_SMBCLK
1
TouchPad Conn. 1

‧
SCL
SMBDATA SMB_DATA PCH_SMBDATA

‧
SDA PSDAT1 TPDATA TPDATA TPDATA

PSCLK1 TPCLK TPCLK TPCLK

SMBus Address:0xA0
2N7002SPT
3D3V_AUX_KBC
Free Fall
‧
3D3V_S5_PCH
Sensor
‧ PCH_SMBCLK

PCH_SMBDATA
SCL

SDA
SRN4K7J-8-GP

SRN2K2J-1-GP SMBus Address:0x32

Battery Conn.
XDP Port ‧‧ SRN33J-7-GP

‧ ‧
GPIO17/SCL1 BAT_SCL PBAT_SMBCLK1 CLK_SMB

SML0CLK SML0_CLK
PCH_SMBCLK
(Reserve) GPIO22/SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB

SML0DATA SML0_DATA SCL

PCH_SMBDATA SMBus address:16
SDA

SCL
BQ24770RUYR-GP
KBC SDA

NPCE285P SMBus address:12

2 2

GPIO73/SCL2

GPIO74/SDA2

PCH 3D3V_S0 SMBus Address:

‧
3D3V_S5_PCH 0x94/0x95/0x96/0x97

3D3V_S0 0R2J-2-GP

‧
SRN2K2J-8-GP
DY
SRN2K2J-8-GP Thermal
‧ ‧ ‧ NCT7718W ‧
‧ ‧
GPIO47/SCL4A PROCHOT_EC

‧ ‧ ‧
SML1CLK SML1_CLK THM_SML1_CLK SCL H_PROCHOT_EC
GPIO53/SDA4A LCD_TST_EN LCD_TST_EN
SML1DATA SML1_DATA THM_SML1_DATA SDL
0R2J-2-GP

LCD_TST
SMBus Address:0x82/0x83 SMBus Address:0x98
2N7002SPT

3D3V_MCU
3D3V_GSEN2

‧ ‧
Co-Lay
Sensor Hub
3
SRN4K7J-8-GP 3
3D3V_GSEN2 STM32L151CBU6TR
‧ LNG3DMTR SRN2K2J-8-GP

SMBC_Therm_NV
SMBD_Therm_NV
‧‧ I2CS_SCL
I2CS_SDA ‧‧
I2C Address:30

LSM303DTR
I2CS_SCL
I2CS_SDA ‧‧
I2C Address:3A

3D3V_S0
L3GD20TR
5V_S0
I2CS_SCL

‧ ‧
I2CS_SDA

I2C Address:D2
3D3V_S0 Home button board
SRN2K2J-1-GP
‧ SRN2K2J-1-GP

‧ ‧
4 4

‧ ‧‧ ‧
DDPB_CTRLCLK PCH_HDMI_CLK DDC_CLK_HDMI

DDPB_CTRLDATA PCH_HDMI_DATA DDC_DATA_HDMI

HDMI CONN <Core Design>

2N7002DW-1-GP Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SMBUS Block Diagram

Size Document Number Rev
Custom Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 100 of 104
A B C D E
 5 4 3 2 1

CLK Block Diagram

D D

Intel CPU
Haswell/Broadwell ULT
CLK_PCIE_WLAN_P3
M_A_DIMA_CLK_DDR0 CLKOUT_PCIE_P2 REFCLKP0
CK0 SA_CLK0 WLAN
M_A_DIMA_CLK_DDR#0 CLK_PCIE_WLAN_N3
CK0# SA_CLK#0 CLKOUT_PCIE_N2 REFCLKN0 NGFF
DDR3L DIMM1
M_A_DIMA_CLK_DDR1
CK1 SA_CLK1
M_A_DIMA_CLK_DDR#1
CK1# SA_CLK#1
C C

Audio
R1907
Realtek
HDA_BITCLK HDA_CODEC_BITCLK
RTC_X1
RTCX1
HDA_BCLK/I2S0_SCLK BITCLK ALC3234
SR33J-5-GP-U

X1901
32.768KHz

RTC_X2
RTCX2 KBC
XTAL24_IN
NPCE285P
B XTAL24_IN
SUS_CLK_PCH R1710 SUS_CLK R2441 SUS_CLK_KBC B
SUSCLK/GPIO62 GPIO0/EXTCLK/F_SDIO3
0R2J-2-GP 0R2J-2-GP
X1801 CLK_PCI_KBC_R R1805 CLK_PCI_KBC
24MHz CLKOUT_LPC_1 LCLK/GPIOF5
0R2J-2-GP
CLKOUT_LPC_0 CLK_PCI_LPC_R R1804 CLK_PCI_LPC
XTAL24_OUT
0R2J-2-GP
LPC
XTAL24_OUT

CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
Test Point

A <Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CLK Block Diagram
Size Document Number Rev
Custom
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 101 of 104

5 4 3 2 1
 A B C D E

Thermal Block Diagram Audio Block Diagram

1 1

3D3V_S5_PCH 3D3V_S0
PAGE28 D+ NCT7718_DXP
PCH MMBT3904-3-GP
SPKR_L+
SPKR_L-

D- NCT7718_DXN
SC2200P50V2KX-2GP SPKR_R-
SPKR_R+ SPEAKER
Thermal Place near CPU
NCT7718
‧ ‧ ‧
PWM CORE
SML1DATA/GPIO74
SML1_DATA THM_SML1_DATA SDA
Codec
‧‧ ‧
2N7002
SML1CLK/GPIO75 SML1_CLK THM_SML1_CLK SCL
MMBT3904-3-GP
ALC3234
T8 AUD_HP1_JACK_L HP MIC
SML1_DATA

AUD_HP1_JACK_R
SML1_CLK

PAGE20
T_CRIT# THERM_SYS_SHDN#
2N7002
S
D
PURE_HW_SHUTDOWN#

PCH_PWROK
EN 3V/5V SLEEVE COMBO
G RING2
2 2
Put under CPU(T8 HW shutdown)

PAGE27 GPIO74

KBC GPIO73
DMIC_DATA_R R2714 DMIC_DATA
Digital
NPCE285P
GPIO0/DMIC_DATA
0R2J-2-GP MIC
DMIC_CLK_R R2716 DMIC_CLK
GPIO1/DMIC_CLK
0R2J-2-GP

GPIO4
GPIO94 GPIO56
FAN_TACH1
FAN_PWM1

5V

FAN_VCC1
3 3
TACH VIN

FAN

4 4
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Thermal/Audio Block Diagram
Document Number Rev
Custom
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 102 of 104
A B C D E
 5 4 3 2 1

Change notes -
DATE VERSON DATE Page Modify List OWNER

D D

C C

B B

<Core Design>
A A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Change History
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 103 of 104

5 4 3 2 1
 5 4 3 2 1
VERSION DATA PAGE Change Iteam

D D

C C

B B

<Core Design>
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Change History
Size Document Number Rev
A3
Cottonwood A00
Date: Tuesday, June 17, 2014 Sheet 104 of 104