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TPOS7B(CIE2-04) for 2.0 SOP Panel Application Circuit_Ver .H_20070305.sch-2 - Mon Mar 05 14:21:53 2007 20050204: 20050323: 20050323: 20051215: 20051222: 20060216: 20061011: 20070305: History Record: Ver.A Ver.B Ver.c Ver.D Ver.E Ver.F Ver.G Ver.H New Design 1.Add NOTE.7: VDDLED(Pin 88) must be connect to +2.8V 2.Add copacitance to GND for VDDP(Pin 32) 3.Add NOTE.2.1 CPU Interface mode: SELMODE connect to +2.8V 1. ISV(Pin 93) connect to VDD56 change to VDD42 2. Image sticking circuit Ul_G point and D1 connect to VDDS56 change to VDD42 1. Take off charge pump CAP C13, C14, C18, C19 2, Change CAP C1 to tuF/6.3V 1, ADD ESD protection component 2. Modify useless pin connect to GND 1. Modify CPU interface RD pin useless connect to VDDL 1. Define Data pin voltage level 1. Modify VDDL(Pin 41 and Pin77) connect to VODI&(Pin 39) 2. Add Note.tt Toppoly ater Yukue tiie CIE2-06 FPC Circuit ee H] owe 2007/3/5 TPOS?B(CIE2-04) for 2.0 SOP Panel Application Circuit_Ver .H_20070305.sch-3 - Mon Mar 05 14:21:53 200; NOTE: . 1. The HOST select is follow as: 7. ESD protection component ore Po 5 me Wiath: 0.075mm van [an [it 7 Space: 0.075mm STL Pasir] stm te a7 Length: 15mm 2. Interface select: 2.4. CPU Interface mode: (1) SCLK, LOAD, DATA, MCLK connect to 42.8V/(Dor't floting) (2) SOA0, SDA, SELMODE comect to 42.8V/ (3) CPULVSYNC. mode: Si crys me oe oe! er! a. (4) IF RD pin(Pin Si)useless, please connect to +2.8V/ 2.2 Poralel RGB Interface. mode (1) RS connect to GND(Don't looting) (2) CPU_VS comect to GND(Dom't floting) (3) The SELMODE select is follow os: Se Sgn i 287 8. Pin 2 and 5 are FPC bonding test pin. Don't care! (4) 126 mode: 9. If Data pin(Pin 53°70)useless, please connect to GND or +2.8V/ - sear 3 Tw Pos coma esa) 10. Data pin DO"DI7(Pin 53°70) Voltage level,

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