Experiment 02: Make use of universal gates to implement Basic gates

Learning Objectives: Illustrate the function of basic logic gates using universal gates
Tools: Online Simulator

Theory:
NAND gate is actually a combination of two logic gates: AND gate followed by NOT gate. So its
output is complement of the output of an AND gate. This gate can have minimum two inputs,
output is always one. By using only NAND gates, we can realize all logic functions: AND, OR,
NOT, X-OR, X-NOR, NOR. So this gate is also called universal gate.
 
NAND gates as NOT gate
A NOT produces complement of the input. It can have only one input, tie the inputs of a NAND
gate together. Now it will work as a NOT gate. Its output is
Y = (A.A)’
=>                                      Y = (A)’

NAND gates as AND gate

A NAND produces complement of AND gate. So, if the output of a NAND gate is inverted,
overall output will be that of an AND gate.
                                                Y = ((A.B)’)’
=>                                     Y = (A.B)

NAND gates as OR gate

From DeMorgan’s theorems: (A.B)’ = A’ + B’
=>                                         (A’.B’)’ = A’’ + B’’ = A + B
So, give the inverted inputs to a NAND gate, obtain OR operation at output.
 NAND gate as XOR Gate

An XOR gate is made by connecting four NAND gates as shown below. This construction entails a
propagation delay three times that of a single NAND gate.

Desired XOR Gate NAND Construction

Q = A XOR B = [ A NAND ( A NAND B ) ] NAND [ B NAND ( A NAND B ) ]

Truth Table
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 0

Alternatively, an XOR gate is made by considering the disjunctive normal form noting from de
Morgan's Law that a NAND gate is an inverted-input OR gate. This construction uses five gates
instead of four.

Desired Gate NAND Construction

 Q = A XOR B = [ B NAND ( A NAND A ) ] NAND[ A NAND ( B NAND B ) ]

NAND gate as NOR gate

A NOR gate is an OR gate with an inverted output. Output is high when neither input A nor input B
is high.

Desired NOR Gate NAND Construction

= [ ( A NAND A ) NAND ( B NAND B ) ] NAND

Q = A NOR B
[ ( A NAND A ) NAND ( B NAND B ) ]
Truth Table
Input A Input B Output Q
0 0 1
0 1 0
1 0 0
1 1 0

NAND gate as - NOR gate

An XNOR gate is made by considering the disjunctive normal form, noting from de Morgan's
Law that a NAND gate is an inverted-input OR gate. This construction entails a propagation delay
three times that of a single NAND gate and uses five gates.

NAND Construction
Desired XNOR Gate
 = [ ( A NAND A ) NAND ( B NAND B ) ] NAND
Q = A XNOR B
( A NAND B )
Input A Input B Output Q
0 0 1
0 1 0
1 0 0
1 1 1

Alternatively, the 4-gate version of the XOR gate can be used with an inverter. This construction
has a propagation delay four times (instead of three times) that of a single NAND gate.
Desired Gate NAND Construction

= { [ A NAND ( A NAND B ) ] NAND

[ B NAND ( A NAND B ) ] } NAND
Q = A XNOR B
{ [ A NAND ( A NAND B ) ]
NAND [ B NAND ( A NAND B ) ] }

Observation Tables:
Learning Outcomes: Students will able to
LO2.1 Define the De Morgan’s theorems
LO2.2 Use the De Morgan’s theorem to derive a Boolean expression with universal gates
Course Outcome: After completion of this experiment the students will be able to solve Boolean
expressions with exclusive OR, NOR, X-NOR, XOR gate.

Conclusion:

For Faculty Use

Correction Formative Timely completion Attendance /
Parameters Assessment of Practical [ 40%] Learning
[40%] Attitude [20%]

Marks
Obtained