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Preliminary Preliminary
Preliminary Preliminary
MITSUBISHI
SEMICONDUCTOR
SEMICONDUCTOR
<Application
<Application
Specific
Specific
Intelligent
Intelligent
Power
Power
Module>
Module>
M I N ARY PS11037
PS11037
I on. ange.
PREL
ificati h
l spec ct to c
n o t a finaare subje
T h is is ic limits
e :
Notice parame
tr FLAT-BASE
FLAT-BASE
TYPE
TYPE
Som
INSULATED
INSULATED
TYPE
TYPE
PS11037
INTEGRATED FUNCTIONS AND FEATURES
• 3 phase IGBT inverter bridge configured by the latest 3rd.
generation IGBT and diode technology.
• Inverter output current capability IO (Note 1):
Type Name Motor Rating IO (100%) IO (150%; 60sec)
PS11037 3.7 kW/200V AC 17.0Arms 25.5Arms
(Note 1) : The inverter output current is assumed to be sinu-
soidal and the peak current value of each of the
above loading cases is defined as : IOP = IO × √
2,
TC < 100°C
APPLICATION
Acoustic noise-less 3.7kW/200V AC Class 3 phase inverters, motor control applications, and
motors with built-in small size inverter package
PACKAGE OUTLINES
95 ± 1
85 ± 0.3
4-φ4.6
24.5 42 (18.5) (MOUNTING HOLE) Terminals Assignment
2 6 18 20.4 ± 1 1 CBU+ 21 P
2 CBU– 22 U
0.5
3 CBV+ 23 V
9
15
12 34 56 7 16 4 CBV– 24 W
3
0.5 5 CBW+ 25 N
(31.65)
6 CBW–
7 VD
23.5
2.5 71
8 UP
62.35 ± 0.8
9 VP
59 ± 0.3
74 ± 1
10 WP
4
11 UN
(35)
(4-φ5) 12 VN
30.7 ± 0.5
✽2 (82.1)
13 WN
23.5
14 FO
15 Vamp
16 GND
1
3
21 22 23 24 25
15
12.7 ± 0.3 3
3 ± 0.5
50.8 ± 0.8
17 ± 0.8
8 ± 0.5
3.5
MITSUBISHI
ELECTRIC
Type name
JAPAN Lot.No
(Fig. 1)
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
INA RY PS11037
ELIM
on. ange.
ificati h
l spec ct to c
PR e: T h is
Notice parame
is n o
tric
t a finaare subje
li m its
FLAT-BASE TYPE
Som
INSULATED TYPE
UV Protection P
VD
Input signal conditioning
Level shifter
Drive circuit
(Interlock circuit)
UP
VP
WP
UN
VN U
WN
V
FO Fo Circuit
W
Drive circuit
OC/SC Protection
UV Protection
V(amp)
+–
GND N
(Fig. 2)
CONTROL PART
Symbol Item Ratings Unit
VD, VDB Supply voltage –0.5 ~ 20 V
VCIN Input signal voltage –0.5 ~ +7.5 V
VFO Fault output supply voltage –0.5 ~ +7.5 V
IFO Fault output current 15 mA
Iamp DC-Link IGBT current signal Amp output current 1 mA
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
TOTAL SYSTEM
Symbol Item Condition Ratings Unit
Tj Junction temperature (Note 2) –20 ~ +125 °C
Tstg Storage temperature — –40 ~ +125 °C
TC Module case operating temperature (Fig. 3) –20 ~ +100 °C
60 Hz sinusoidal AC applied between all terminals and
VISO Isolation voltage 2500 Vrms
the base plate for 1 minute.
— Mounting torque Mounting screw: M4 0.98 ~ 1.47 N·m
(Note 2) : The indicated values are specified considering the safe operation of all the parts within the ASIPM. The max. ratings for the ASIPM
power chips (IGBT & FWDi) is Tj < 150.
LABEL
Tc
(Fig. 3)
THERMAL RESISTANCE
Ratings
Symbol Item Condition Unit
Min. Typ. Max.
Rth(jc) Q Junction to case Thermal Inverter IGBT (1/6) — — 1.75 °C/W
Rth(jc) F Resistance Inverter FWDi (1/6) — — 2.4 °C/W
Rth(cf) Contact Thermal Resistance Case to fin thermal, grease applied (1 Module) — — 0.031 °C/W
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
INA RY PS11037
ELIM
on. ange.
ificati h
l spec ct to c
PR e: T h is
Notice parame
is n o
tric
t a finaare subje
li m its
FLAT-BASE TYPE
Som
INSULATED TYPE
Vamp
5
INVERTER DC-LINK IGBT CURRENT ANALOGUE
SIGNALING OUTPUT (TYPICAL) VD = 15V
4 Tj = 25°C
Vamp (200%)
3
Vamp (V)
2
Vamp (100%)
0
(Fig. 4)
0 100 200 300
DC-LINK IGBT Current (%), (IC = IO✕ 2)
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
OC
Collector current
0
2 10
tw (µs)
(Fig. 5)
a1 b4
P-Side Input Signal : VCIN(p) ON
a4 b1
N-Side Input Signal : VCIN(n) ON
a3 b2
P-Side IGBT Gate : VGE(p)
0
a2
(Fig. 6)
Description:
(1) During the ON-State of either of the upper-arm or the lower-arm IGBT, the inter-lock protection circuit blocks any erroneous ON pulses (re-
sulting from input noise) from triggering the other arm IGBT and thus it prevents the arm-shoot-through situation.
(2) When two ON-signals are received for both the upper and the lower arms, the signal received first will be passed to the IGBT and the sec-
ond signal will be blocked. The second signal will be passed to its corresponding IGBT immediately after the first signal is OFF.
Note: This protective function provides no fault signaling output.
Operation:
a1. P-side normal ON-signal ⇒ P-side IGBT gate turns ON. b1. N-side normal ON-signal ⇒ N-side IGBT gate turns ON.
a2. N-side erroneous ON-signal ⇒ N-side IGBT gate remains OFF. b2. Simultaneous ON-signals ⇒ P-side IGBT gate remains OFF.
a3. While P-side ON-signal remains ⇒ P-side IGBT gate remains ON. b3. N-side receives OFF-signal ⇒ N-side IGBT gate turns OFF.
a4. N-side normal ON-signal ⇒ N-side IGBT gate turns ON. b4. Immediately after (b3) ⇒ P-side IGBT gate turns ON.
5V VD(15V) ASIPM
5.1kΩ
Note : R
The parts shown dotted
UP,VP,WP,UN,VN,WN
are to be used if noise R
CPU Fo
filtering is required.
10kΩ
V(amp)
0.1nF 0.1nF
GND(Logic)
(Fig. 7)
Jan. 2000