Machine Instruction

Course Number : TTI3I3

CLO :1
Week :4

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 How It Works? Case Study: B  A
3

3 Data Register

3A A

B
1 CU
C
Instruction 2
Pointer Instruction Register

MOV B  A
ALU Instruction
Decoder
Mem 2

Mem 1 1E

Mem 0 www.telkomuniversity.ac.id
DEBUG.EXE

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 Machine Instruction Type

Basic:
• Data Transfer, ex: MOV, PUSH, POP
• Arithmetic and Logic, ex: ADD, SUB, AND, OR, SHL
• Control, ex: JMP, JZ
Additional:
• System Call
• Floating Point Processing
• String Processing
• Cryptography Processing
• Multimedia Processing (Compression/Decompression, Coding/Decoding)
• 3D Image Manipulation

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 How Microprocessor RUNS an instruction?

1. Instruction Fetch (IF) is where

microprocessor fetch the
Instruction
instruction from memory Fetch
2. Instruction Decode (DE) is where
the microprocessor decode the Instruction
Decode
instruction to understand what
needs to be done
3. Execution (EX) is where the Execution

microprocessor execute the

instruction

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 Microprocessor Family

• Based on the instruction length: IF

– Fixed Length Instruction, ex. RISC, DLX
– Variable Length Instruction, ex. x86
• Based on ISA (Instruction Set Architecture): DE
EX
– RISC (Reduced Instruction Set Computer)
– CISC (Complex Instruction Set Computer)

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 Machine Instruction Structure

• Opcode (operation code) consists of a code that explain the

instruction’s type
• In CISC, opcode also determine the length of the instruction
(how many bytes more should be fetched)
• After the opcode, is the operand (could be data or another
information)

CISC opcode ? ? ?

0 7

RISC opcode

0 5
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 How does x86 decode instruction?

1. First CU fetch “B8” or 1011 1000 from the memory

2. Based on the table, CU understand that “B?” is a MOV Immediate to
Register and “B8” is w=1 (16 bit register) with reg=000 (AX). So “B8” is
MOV AX,????
3. CU fetch the remaining parts of the instruction “3412”
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 DLX Instruction Set Architecture

• 32 bit instruction = 6 bit opcode + operand (5 bit register select and data)
• Three types of instruction: R-type, I-type and J-type
– R-type is register instructions, with 3 register references contained in the 32-
bit instruction
– I-type specify two registers, and use 16 bits to hold an immediate value
– J-type instructions are jumps, containing a 26-bit address
Example:
• ADD R1, R2, R3 → Regs[R1] <- Regs[R2]+Regs[R3]
• LW R1,30(R2) → Regs[R1] <-32Mem[30+Regs[R2]]
• BEQZ R4, name → if (Regs[R4]==0) PC<-name; ((PC+4)-215)<=name<((PC+4)+215)

opcode

0 5
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 How DLX does Instruction Decode?
3

3 Data Register

R1

R2
1 CU
4 R3
Program 2
Counter Instruction Register
3
ADD R3,R2, R1

ALU
Mem 2

Mem 1

Mem 0 www.telkomuniversity.ac.id
 Microprocessor Speed

1. By Frequency Clock (GHz) from kHz → MHz → GHz

2. By Number Instruction can be run (MIPS)
3. By Number of Cycles per Instruction (CPI)
resource efficiency

“everyone must work”

“use correct supply chain”

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 Pipeline in x86

• Without Pipeline
t= 1 2 3 4 5 6 7 8 9 10

ADD AX,AX IF DE IF DE EX
ADD BX,CX IF DE IF DE EX

• With Pipeline
t= 1 2 3 4 5 6 7 8 9 10

ADD AX,AX IF DE IF DE EX

ADD BX,CX IF DE IF DE EX CPI = 6/2 = 3

ADD AX,CX IF DE IF DE EX CPI = 7/3 = 2.3
ADD BX,AX CPI = 8/4 = 2 IF DE IF DE EX
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 Problem with Pipeline

• Structural Hazards, happens because of

resource conflict when hardware is not able to
support running 2 instructions at one time
• Data Hazards, happens because of data
dependency when the next following
instruction use data from previous instruction
• Control Hazards, happens when running
control transfer instruction type (branch,
jump, call)
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 Structural Hazard

t= 1 2 3 4 5 6 7 8 9 10

PUSH AX IF DE EX

PUSH BX IF DE EX

ADD AX,BX IF DE EX

• Executing “PUSH AX” needs access to memory

(data bus, address bus, WR signal)
• Fetching “ADD AX,BX” needs access to
memory (data bus, address bus, RD signal)

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 Data Hazard #1: RAW (Read After Write)

t= 1 2 3 4 5 6 7 8 9 10

MOV AX,0000 IF DE IF DE EX

MOV AX,FFFF IF DE IF DE EX

PUSH AX IF DE EX

• Executing “PUSH AX” at t=5 will push (write)

data ‘0000’ because ‘FFFF’ is executed at t=6

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 Data Hazard #2: WAW (Write After Write)

t= 1 2 3 4 5 6 7 8 9 10

MOV AX,FFFF IF DE IF DE EX

POP AX IF DE EX

• Executing “POP AX” at t=4 will make AX to

have other data instead of ‘FFFF’ because
‘FFFF’ is executed at t=5

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 Data Hazard #3: WAR (Write After Read)

t= 1 2 3 4 5 6 7 8 9 10

MOV AX,FFFF IF DE IF DE EX

MOV BX,AX IF DE IF DE EX

POP AX IF DE EX

• Executing “POP AX” at t=5 will make BX to

have data from stack instead of ‘FFFF’ because
“MOV BX,AX” is executed at t=6

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 Control Hazard

Offset t= 1 2 3 4 5 6 7 8 9 10

0100 MOV AX,0000 IF DE IF DE EX

0103 MOV CX,000A IF DE IF DE EX

0106 ADD AX,0001 IF DE IF DE EX

0109 XOR CX,AX IF DE IF DE EX

010B JNZ 0103 IF DE IF DE EX

010D POP AX IF DE EX

• At t=9, if JNZ is taken (do the jump) then it is a

waste to fetch-decode-execute “POP AX”
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See you on next class

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